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r23885 Sunday 23rd June, 2013 at 17:01:23 UTC by Carl
i386: preliminary cpu-side smi support (nw)
[src/emu/cpu/i386]i386.c i386.h i386ops.c i386ops.h i386priv.h pentops.c

trunk/src/emu/cpu/i386/i386priv.h
r23884r23885
170170   MMX_MM7=X87_ST7
171171};
172172
173enum smram
174{
175   SMRAM_SMBASE = 0xF8,
176   SMRAM_SMREV  = 0xFC,
177   SMRAM_IORSRT = 0x100,
178   SMRAM_AHALT  = 0x102,
179   SMRAM_IOEDI  = 0x104,
180   SMRAM_IOECX  = 0x108,
181   SMRAM_IOESI  = 0x10C,
182
183   SMRAM_ES     = 0x1A8,
184   SMRAM_CS     = 0x1AC,
185   SMRAM_SS     = 0x1B0,
186   SMRAM_DS     = 0x1B4,
187   SMRAM_FS     = 0x1B8,
188   SMRAM_GS     = 0x1BC,
189   SMRAM_LDTR   = 0x1C0,
190   SMRAM_TR     = 0x1C4,
191   SMRAM_DR7    = 0x1C8,
192   SMRAM_DR6    = 0x1CC,
193   SMRAM_EAX    = 0x1D0,
194   SMRAM_ECX    = 0x1D4,
195   SMRAM_EDX    = 0x1D8,
196   SMRAM_EBX    = 0x1DC,
197   SMRAM_ESP    = 0x1E0,
198   SMRAM_EBP    = 0x1E4,
199   SMRAM_ESI    = 0x1E8,
200   SMRAM_EDI    = 0x1EC,
201   SMRAM_EIP    = 0x1F0,
202   SMRAM_EFLAGS = 0x1F4,
203   SMRAM_CR3    = 0x1F8,
204   SMRAM_CR0    = 0x1FC,
205};
206
207enum smram_intel_p5
208{
209   SMRAM_IP5_IOEIP   = 0x110,
210   SMRAM_IP5_CR4     = 0x128,
211   SMRAM_IP5_ESLIM   = 0x130,
212   SMRAM_IP5_ESBASE  = 0x134,
213   SMRAM_IP5_ESACC   = 0x138,
214   SMRAM_IP5_CSLIM   = 0x13C,
215   SMRAM_IP5_CSBASE  = 0x140,
216   SMRAM_IP5_CSACC   = 0x144,
217   SMRAM_IP5_SSLIM   = 0x148,
218   SMRAM_IP5_SSBASE  = 0x14C,
219   SMRAM_IP5_SSACC   = 0x150,
220   SMRAM_IP5_DSLIM   = 0x154,
221   SMRAM_IP5_DSBASE  = 0x158,
222   SMRAM_IP5_DSACC   = 0x15C,
223   SMRAM_IP5_FSLIM   = 0x160,
224   SMRAM_IP5_FSBASE  = 0x164,
225   SMRAM_IP5_FSACC   = 0x168,
226   SMRAM_IP5_GSLIM   = 0x16C,
227   SMRAM_IP5_GSBASE  = 0x170,
228   SMRAM_IP5_GSACC   = 0x174,
229   SMRAM_IP5_LDTLIM  = 0x178,
230   SMRAM_IP5_LDTBASE = 0x17C,
231   SMRAM_IP5_LDTACC  = 0x180,
232   SMRAM_IP5_GDTLIM  = 0x184,
233   SMRAM_IP5_GDTBASE = 0x188,
234   SMRAM_IP5_GDTACC  = 0x18C,
235   SMRAM_IP5_IDTLIM  = 0x190,
236   SMRAM_IP5_IDTBASE = 0x194,
237   SMRAM_IP5_IDTACC  = 0x198,
238   SMRAM_IP5_TRLIM   = 0x19C,
239   SMRAM_IP5_TRBASE  = 0x1A0,
240   SMRAM_IP5_TRACC   = 0x1A4,
241};
242
173243/* Protected mode exceptions */
174244#define FAULT_UD 6   // Invalid Opcode
175245#define FAULT_NM 7   // Coprocessor not available
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363433
364434   vtlb_state *vtlb;
365435
436   bool smm;
437   bool nmi_masked;
438   bool nmi_latched;
439   UINT32 smbase;
440   devcb_resolved_write_line smiact;
441
366442   // bytes in current opcode, debug only
367443#ifdef DEBUG_MISSING_OPCODE
368444   UINT8 opcode_bytes[16];
trunk/src/emu/cpu/i386/i386ops.h
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354354   { 0xA5,     OP_2BYTE|OP_I386,           I386OP(shld16_cl),              I386OP(shld32_cl),          },
355355   { 0xA8,     OP_2BYTE|OP_I386,           I386OP(push_gs16),              I386OP(push_gs32),          },
356356   { 0xA9,     OP_2BYTE|OP_I386,           I386OP(pop_gs16),               I386OP(pop_gs32),           },
357   { 0xAA,     OP_2BYTE|OP_I386,           I386OP(rsm),                    I386OP(rsm),                },
357   { 0xAA,     OP_2BYTE|OP_PENTIUM,        PENTIUMOP(rsm),                 PENTIUMOP(rsm),             },
358358   { 0xAB,     OP_2BYTE|OP_I386,           I386OP(bts_rm16_r16),           I386OP(bts_rm32_r32),       },
359359   { 0xAC,     OP_2BYTE|OP_I386,           I386OP(shrd16_i8),              I386OP(shrd32_i8),          },
360360   { 0xAD,     OP_2BYTE|OP_I386,           I386OP(shrd16_cl),              I386OP(shrd32_cl),          },
trunk/src/emu/cpu/i386/pentops.c
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144144   i386_trap(cpustate, 6, 0, 0);
145145}
146146
147static void PENTIUMOP(rsm)(i386_state *cpustate)
148{
149   UINT32 smram_state = cpustate->smbase + 0xfe00;
150   if(!cpustate->smm)
151   {
152      logerror("i386: Invalid RSM outside SMM at %08X\n", cpustate->pc - 1);
153      i386_trap(cpustate, 6, 0, 0);
154      return;
155   }
156
157   // load state, no sanity checks anywhere
158   cpustate->smbase = READ32(cpustate, smram_state+SMRAM_SMBASE);
159   cpustate->cr[4] = READ32(cpustate, smram_state+SMRAM_IP5_CR4);
160   cpustate->sreg[ES].limit = READ32(cpustate, smram_state+SMRAM_IP5_ESLIM);
161   cpustate->sreg[ES].base = READ32(cpustate, smram_state+SMRAM_IP5_ESBASE);
162   cpustate->sreg[ES].flags = READ32(cpustate, smram_state+SMRAM_IP5_ESACC);
163   cpustate->sreg[CS].limit = READ32(cpustate, smram_state+SMRAM_IP5_CSLIM);
164   cpustate->sreg[CS].base = READ32(cpustate, smram_state+SMRAM_IP5_CSBASE);
165   cpustate->sreg[CS].flags = READ32(cpustate, smram_state+SMRAM_IP5_CSACC);
166   cpustate->sreg[SS].limit = READ32(cpustate, smram_state+SMRAM_IP5_SSLIM);
167   cpustate->sreg[SS].base = READ32(cpustate, smram_state+SMRAM_IP5_SSBASE);
168   cpustate->sreg[SS].flags = READ32(cpustate, smram_state+SMRAM_IP5_SSACC);
169   cpustate->sreg[DS].limit = READ32(cpustate, smram_state+SMRAM_IP5_DSLIM);
170   cpustate->sreg[DS].base = READ32(cpustate, smram_state+SMRAM_IP5_DSBASE);
171   cpustate->sreg[DS].flags = READ32(cpustate, smram_state+SMRAM_IP5_DSACC);
172   cpustate->sreg[FS].limit = READ32(cpustate, smram_state+SMRAM_IP5_FSLIM);
173   cpustate->sreg[FS].base = READ32(cpustate, smram_state+SMRAM_IP5_FSBASE);
174   cpustate->sreg[FS].flags = READ32(cpustate, smram_state+SMRAM_IP5_FSACC);
175   cpustate->sreg[GS].limit = READ32(cpustate, smram_state+SMRAM_IP5_GSLIM);
176   cpustate->sreg[GS].base = READ32(cpustate, smram_state+SMRAM_IP5_GSBASE);
177   cpustate->sreg[GS].flags = READ32(cpustate, smram_state+SMRAM_IP5_GSACC);
178   cpustate->ldtr.flags = READ32(cpustate, smram_state+SMRAM_IP5_LDTACC);
179   cpustate->ldtr.limit = READ32(cpustate, smram_state+SMRAM_IP5_LDTLIM);
180   cpustate->ldtr.base = READ32(cpustate, smram_state+SMRAM_IP5_LDTBASE);
181   cpustate->gdtr.limit = READ32(cpustate, smram_state+SMRAM_IP5_GDTLIM);
182   cpustate->gdtr.base = READ32(cpustate, smram_state+SMRAM_IP5_GDTBASE);
183   cpustate->idtr.limit = READ32(cpustate, smram_state+SMRAM_IP5_IDTLIM);
184   cpustate->idtr.base = READ32(cpustate, smram_state+SMRAM_IP5_IDTBASE);
185   cpustate->task.limit = READ32(cpustate, smram_state+SMRAM_IP5_TRLIM);
186   cpustate->task.base = READ32(cpustate, smram_state+SMRAM_IP5_TRBASE);
187   cpustate->task.flags = READ32(cpustate, smram_state+SMRAM_IP5_TRACC);
188
189   cpustate->sreg[ES].selector = READ32(cpustate, smram_state+SMRAM_ES);
190   cpustate->sreg[CS].selector = READ32(cpustate, smram_state+SMRAM_CS);
191   cpustate->sreg[SS].selector = READ32(cpustate, smram_state+SMRAM_SS);
192   cpustate->sreg[DS].selector = READ32(cpustate, smram_state+SMRAM_DS);
193   cpustate->sreg[FS].selector = READ32(cpustate, smram_state+SMRAM_FS);
194   cpustate->sreg[GS].selector = READ32(cpustate, smram_state+SMRAM_GS);
195   cpustate->ldtr.segment = READ32(cpustate, smram_state+SMRAM_LDTR);
196   cpustate->task.segment = READ32(cpustate, smram_state+SMRAM_TR);
197
198   cpustate->dr[7] = READ32(cpustate, smram_state+SMRAM_DR7);
199   cpustate->dr[6] = READ32(cpustate, smram_state+SMRAM_DR6);
200   REG32(EAX) = READ32(cpustate, smram_state+SMRAM_EAX);
201   REG32(ECX) = READ32(cpustate, smram_state+SMRAM_ECX);
202   REG32(EDX) = READ32(cpustate, smram_state+SMRAM_EDX);
203   REG32(EBX) = READ32(cpustate, smram_state+SMRAM_EBX);
204   REG32(ESP) = READ32(cpustate, smram_state+SMRAM_ESP);
205   REG32(EBP) = READ32(cpustate, smram_state+SMRAM_EBP);
206   REG32(ESI) = READ32(cpustate, smram_state+SMRAM_ESI);
207   REG32(EDI) = READ32(cpustate, smram_state+SMRAM_EDI);
208   cpustate->eip = READ32(cpustate, smram_state+SMRAM_EIP);
209   cpustate->eflags = READ32(cpustate, smram_state+SMRAM_EAX);
210   cpustate->cr[3] = READ32(cpustate, smram_state+SMRAM_CR3);
211   cpustate->cr[0] = READ32(cpustate, smram_state+SMRAM_CR0);
212
213   cpustate->CPL = (cpustate->sreg[SS].flags >> 13) & 3; // cpl == dpl of ss
214
215   for(int i = 0; i < GS; i++)
216   {
217      if(PROTECTED_MODE && !V8086_MODE)
218      {
219         cpustate->sreg[i].valid = cpustate->sreg[i].selector ? true : false;
220         cpustate->sreg[i].d = (cpustate->sreg[i].flags & 0x4000) ? 1 : 0;
221      }
222      else
223         cpustate->sreg[i].valid = true;
224   }
225
226   if(!cpustate->smiact.isnull())
227      cpustate->smiact(false);
228   cpustate->smm = false;
229
230   CHANGE_PC(cpustate,cpustate->eip);
231   cpustate->nmi_masked = false;
232   if(cpustate->nmi_latched)
233   {
234      cpustate->nmi_latched = false;
235      i386_trap(cpustate, 2, 1, 0);
236   }
237}
238
147239static void SSEOP(cvttss2si)(i386_state *cpustate) // Opcode f3 0f 2c
148240{
149241   UINT32 src;
trunk/src/emu/cpu/i386/i386.c
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136136      {
137137         cpustate->sreg[segment].base = cpustate->sreg[segment].selector << 4;
138138         cpustate->sreg[segment].limit = 0xffff;
139         cpustate->sreg[segment].flags = (segment == CS) ? 0x009a : 0x0092;
139         cpustate->sreg[segment].flags = (segment == CS) ? 0x00fb : 0x00f3;
140140         cpustate->sreg[segment].d = 0;
141141         cpustate->sreg[segment].valid = true;
142142      }
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30693069   device->save_item(NAME(cpustate->irq_state));
30703070   device->save_item(NAME(cpustate->performed_intersegment_jump));
30713071   device->save_item(NAME(cpustate->mxcsr));
3072   device->save_item(NAME(cpustate->smm));
3073   device->save_item(NAME(cpustate->nmi_masked));
3074   device->save_item(NAME(cpustate->nmi_latched));
3075   device->save_item(NAME(cpustate->smbase));
30723076   device->machine().save().register_postload(save_prepost_delegate(FUNC(i386_postload), cpustate));
3077
3078   i386_interface *intf = (i386_interface *) device->static_config();
3079
3080   if (intf != NULL)
3081      cpustate->smiact.resolve(intf->smiact, *device);
3082   else
3083      memset(&cpustate->smiact, 0, sizeof(cpustate->smiact));
30733084}
30743085
30753086CPU_INIT( i386 )
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31593170
31603171   cpustate->idtr.base = 0;
31613172   cpustate->idtr.limit = 0x3ff;
3173   cpustate->smm = false;
3174   cpustate->nmi_masked = false;
3175   cpustate->nmi_latched = false;
31623176
31633177   cpustate->a20_mask = ~0;
31643178
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31833197   CHANGE_PC(cpustate,cpustate->eip);
31843198}
31853199
3200static void pentium_smi(i386_state *cpustate)
3201{
3202   UINT32 smram_state = cpustate->smbase + 0xfe00;
3203   UINT32 old_cr0 = cpustate->cr[0];
3204   UINT32 old_flags = get_flags(cpustate);
3205
3206   if(cpustate->smm)
3207      return; // TODO: latch
3208
3209   cpustate->cr[0] &= ~(0x8000000d);
3210   set_flags(cpustate, 2);
3211   if(!cpustate->smiact.isnull())
3212      cpustate->smiact(true);
3213   cpustate->smm = true;
3214
3215   // save state
3216   WRITE32(cpustate, cpustate->cr[4], smram_state+SMRAM_IP5_CR4);
3217   WRITE32(cpustate, cpustate->sreg[ES].limit, smram_state+SMRAM_IP5_ESLIM);
3218   WRITE32(cpustate, cpustate->sreg[ES].base, smram_state+SMRAM_IP5_ESBASE);
3219   WRITE32(cpustate, cpustate->sreg[ES].flags, smram_state+SMRAM_IP5_ESACC);
3220   WRITE32(cpustate, cpustate->sreg[CS].limit, smram_state+SMRAM_IP5_CSLIM);
3221   WRITE32(cpustate, cpustate->sreg[CS].base, smram_state+SMRAM_IP5_CSBASE);
3222   WRITE32(cpustate, cpustate->sreg[CS].flags, smram_state+SMRAM_IP5_CSACC);
3223   WRITE32(cpustate, cpustate->sreg[SS].limit, smram_state+SMRAM_IP5_SSLIM);
3224   WRITE32(cpustate, cpustate->sreg[SS].base, smram_state+SMRAM_IP5_SSBASE);
3225   WRITE32(cpustate, cpustate->sreg[SS].flags, smram_state+SMRAM_IP5_SSACC);
3226   WRITE32(cpustate, cpustate->sreg[DS].limit, smram_state+SMRAM_IP5_DSLIM);
3227   WRITE32(cpustate, cpustate->sreg[DS].base, smram_state+SMRAM_IP5_DSBASE);
3228   WRITE32(cpustate, cpustate->sreg[DS].flags, smram_state+SMRAM_IP5_DSACC);
3229   WRITE32(cpustate, cpustate->sreg[FS].limit, smram_state+SMRAM_IP5_FSLIM);
3230   WRITE32(cpustate, cpustate->sreg[FS].base, smram_state+SMRAM_IP5_FSBASE);
3231   WRITE32(cpustate, cpustate->sreg[FS].flags, smram_state+SMRAM_IP5_FSACC);
3232   WRITE32(cpustate, cpustate->sreg[GS].limit, smram_state+SMRAM_IP5_GSLIM);
3233   WRITE32(cpustate, cpustate->sreg[GS].base, smram_state+SMRAM_IP5_GSBASE);
3234   WRITE32(cpustate, cpustate->sreg[GS].flags, smram_state+SMRAM_IP5_GSACC);
3235   WRITE32(cpustate, cpustate->ldtr.flags, smram_state+SMRAM_IP5_LDTACC);
3236   WRITE32(cpustate, cpustate->ldtr.limit, smram_state+SMRAM_IP5_LDTLIM);
3237   WRITE32(cpustate, cpustate->ldtr.base, smram_state+SMRAM_IP5_LDTBASE);
3238   WRITE32(cpustate, cpustate->gdtr.limit, smram_state+SMRAM_IP5_GDTLIM);
3239   WRITE32(cpustate, cpustate->gdtr.base, smram_state+SMRAM_IP5_GDTBASE);
3240   WRITE32(cpustate, cpustate->idtr.limit, smram_state+SMRAM_IP5_IDTLIM);
3241   WRITE32(cpustate, cpustate->idtr.base, smram_state+SMRAM_IP5_IDTBASE);
3242   WRITE32(cpustate, cpustate->task.limit, smram_state+SMRAM_IP5_TRLIM);
3243   WRITE32(cpustate, cpustate->task.base, smram_state+SMRAM_IP5_TRBASE);
3244   WRITE32(cpustate, cpustate->task.flags, smram_state+SMRAM_IP5_TRACC);
3245
3246   WRITE32(cpustate, cpustate->sreg[ES].selector, smram_state+SMRAM_ES);
3247   WRITE32(cpustate, cpustate->sreg[CS].selector, smram_state+SMRAM_CS);
3248   WRITE32(cpustate, cpustate->sreg[SS].selector, smram_state+SMRAM_SS);
3249   WRITE32(cpustate, cpustate->sreg[DS].selector, smram_state+SMRAM_DS);
3250   WRITE32(cpustate, cpustate->sreg[FS].selector, smram_state+SMRAM_FS);
3251   WRITE32(cpustate, cpustate->sreg[GS].selector, smram_state+SMRAM_GS);
3252   WRITE32(cpustate, cpustate->ldtr.segment, smram_state+SMRAM_LDTR);
3253   WRITE32(cpustate, cpustate->task.segment, smram_state+SMRAM_TR);
3254
3255   WRITE32(cpustate, cpustate->dr[7], smram_state+SMRAM_DR7);
3256   WRITE32(cpustate, cpustate->dr[6], smram_state+SMRAM_DR6);
3257   WRITE32(cpustate, REG32(EAX), smram_state+SMRAM_EAX);
3258   WRITE32(cpustate, REG32(ECX), smram_state+SMRAM_ECX);
3259   WRITE32(cpustate, REG32(EDX), smram_state+SMRAM_EDX);
3260   WRITE32(cpustate, REG32(EBX), smram_state+SMRAM_EBX);
3261   WRITE32(cpustate, REG32(ESP), smram_state+SMRAM_ESP);
3262   WRITE32(cpustate, REG32(EBP), smram_state+SMRAM_EBP);
3263   WRITE32(cpustate, REG32(ESI), smram_state+SMRAM_ESI);
3264   WRITE32(cpustate, REG32(EDI), smram_state+SMRAM_EDI);
3265   WRITE32(cpustate, cpustate->eip, smram_state+SMRAM_EIP);
3266   WRITE32(cpustate, old_flags, smram_state+SMRAM_EAX);
3267   WRITE32(cpustate, cpustate->cr[3], smram_state+SMRAM_CR3);
3268   WRITE32(cpustate, old_cr0, smram_state+SMRAM_CR0);
3269
3270   cpustate->sreg[DS].selector = cpustate->sreg[ES].selector = cpustate->sreg[FS].selector = cpustate->sreg[GS].selector = cpustate->sreg[SS].selector = 0;
3271   cpustate->sreg[DS].base = cpustate->sreg[ES].base = cpustate->sreg[FS].base = cpustate->sreg[GS].base = cpustate->sreg[SS].base = 0x00000000;
3272   cpustate->sreg[DS].limit = cpustate->sreg[ES].limit = cpustate->sreg[FS].limit = cpustate->sreg[GS].limit = cpustate->sreg[SS].limit = 0xffffffff;
3273   cpustate->sreg[DS].flags = cpustate->sreg[ES].flags = cpustate->sreg[FS].flags = cpustate->sreg[GS].flags = cpustate->sreg[SS].flags = 0x8093;
3274   cpustate->sreg[DS].valid = cpustate->sreg[ES].valid = cpustate->sreg[FS].valid = cpustate->sreg[GS].valid = cpustate->sreg[SS].valid =true;
3275   cpustate->sreg[CS].selector = 0x3000; // pentium only, ppro sel = smbase >> 4
3276   cpustate->sreg[CS].base = cpustate->smbase;
3277   cpustate->sreg[CS].limit = 0xffffffff;
3278   cpustate->sreg[CS].flags = 0x809b;
3279   cpustate->sreg[CS].valid = true;
3280   cpustate->cr[4] = 0;
3281   cpustate->dr[7] = 0x400;
3282   cpustate->eip = 0x8000;
3283
3284   cpustate->nmi_masked = true;
3285   CHANGE_PC(cpustate,cpustate->eip);
3286}
3287
31863288static void i386_set_irq_line(i386_state *cpustate,int irqline, int state)
31873289{
31883290   if (state != CLEAR_LINE && cpustate->halted)
r23884r23885
31933295   if ( irqline == INPUT_LINE_NMI )
31943296   {
31953297      /* NMI (I do not think that this is 100% right) */
3298      if(cpustate->nmi_masked)
3299      {
3300         cpustate->nmi_latched = true;
3301         return;
3302      }
31963303      if ( state )
31973304         i386_trap(cpustate,2, 1, 0);
31983305   }
r23884r23885
36693776   cpustate->eflags = 0;
36703777   cpustate->eflags_mask = 0x00077fd7;
36713778   cpustate->eip = 0xfff0;
3779   cpustate->smm = false;
3780   cpustate->nmi_masked = false;
3781   cpustate->nmi_latched = false;
36723782
36733783   x87_reset(cpustate);
36743784
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37813891   cpustate->eflags_mask = 0x003f7fd7;
37823892   cpustate->eip = 0xfff0;
37833893   cpustate->mxcsr = 0x1f80;
3894   cpustate->smm = false;
3895   cpustate->smbase = 0x30000;
3896   cpustate->nmi_masked = false;
3897   cpustate->nmi_latched = false;
37843898
37853899   x87_reset(cpustate);
37863900
r23884r23885
38233937   i386_state *cpustate = get_safe_token(device);
38243938   switch (state)
38253939   {
3940      case CPUINFO_INT_INPUT_STATE+INPUT_LINE_SMI:
3941         if(state)
3942            pentium_smi(cpustate);
3943         break;
38263944      case CPUINFO_INT_REGISTER + X87_CTRL:           cpustate->x87_cw = info->i;     break;
38273945      case CPUINFO_INT_REGISTER + X87_STATUS:         cpustate->x87_sw = info->i;     break;
38283946      case CPUINFO_INT_REGISTER + X87_TAG:            cpustate->x87_tw = info->i;     break;
r23884r23885
39074025   cpustate->eflags = 0x00200000;
39084026   cpustate->eflags_mask = 0x00277fd7; /* TODO: is this correct? */
39094027   cpustate->eip = 0xfff0;
4028   cpustate->smm = false;
4029   cpustate->nmi_masked = false;
4030   cpustate->nmi_latched = false;
39104031
39114032   x87_reset(cpustate);
39124033
r23884r23885
40274148   cpustate->eflags_mask = 0x00277fd7; /* TODO: is this correct? */
40284149   cpustate->eip = 0xfff0;
40294150   cpustate->mxcsr = 0x1f80;
4151   cpustate->smm = false;
4152   cpustate->smbase = 0x30000;
4153   cpustate->nmi_masked = false;
4154   cpustate->nmi_latched = false;
40304155
40314156   x87_reset(cpustate);
40324157
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41274252   cpustate->eflags_mask = 0x00277fd7; /* TODO: is this correct? */
41284253   cpustate->eip = 0xfff0;
41294254   cpustate->mxcsr = 0x1f80;
4255   cpustate->smm = false;
4256   cpustate->smbase = 0x30000;
4257   cpustate->nmi_masked = false;
4258   cpustate->nmi_latched = false;
41304259
41314260   x87_reset(cpustate);
41324261
r23884r23885
42274356   cpustate->eflags_mask = 0x00277fd7; /* TODO: is this correct? */
42284357   cpustate->eip = 0xfff0;
42294358   cpustate->mxcsr = 0x1f80;
4359   cpustate->smm = false;
4360   cpustate->smbase = 0x30000;
4361   cpustate->nmi_masked = false;
4362   cpustate->nmi_latched = false;
42304363
42314364   x87_reset(cpustate);
42324365
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43274460   cpustate->eflags_mask = 0x00277fd7; /* TODO: is this correct? */
43284461   cpustate->eip = 0xfff0;
43294462   cpustate->mxcsr = 0x1f80;
4463   cpustate->smm = false;
4464   cpustate->smbase = 0x30000;
4465   cpustate->nmi_masked = false;
4466   cpustate->nmi_latched = false;
43304467
43314468   x87_reset(cpustate);
43324469
r23884r23885
44294566   cpustate->eflags_mask = 0x00277fd7; /* TODO: is this correct? */
44304567   cpustate->eip = 0xfff0;
44314568   cpustate->mxcsr = 0x1f80;
4569   cpustate->smm = false;
4570   cpustate->smbase = 0x30000;
4571   cpustate->nmi_masked = false;
4572   cpustate->nmi_latched = false;
44324573
44334574   x87_reset(cpustate);
44344575
trunk/src/emu/cpu/i386/i386ops.c
r23884r23885
24982498   fatalerror("i386: LOADALL unimplemented at %08X\n", cpustate->pc - 1);
24992499}
25002500
2501static void I386OP(rsm)(i386_state *cpustate)
2502{
2503   logerror("i386: Invalid RSM outside SMM at %08X\n", cpustate->pc - 1);
2504   i386_trap(cpustate, 6, 0, 0);
2505}
2506
25072501static void I386OP(invalid)(i386_state *cpustate)
25082502{
25092503   report_invalid_opcode(cpustate);
trunk/src/emu/cpu/i386/i386.h
r23884r23885
44#define __I386INTF_H__
55
66#define INPUT_LINE_A20      1
7#define INPUT_LINE_SMI      2
78
9struct i386_interface
10{
11   devcb_write_line smiact;
12};
813
914// mingw has this defined for 32-bit compiles
1015#undef i386

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