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r23803 Wednesday 19th June, 2013 at 20:26:22 UTC by Wilbert Pol
alph8201.c: Modernized cpu cores. (nw)
[src/emu/cpu/alph8201]alph8201.c alph8201.h

trunk/src/emu/cpu/alph8201/alph8201.h
r23802r23803
3535   ALPHA8201_R4,ALPHA8201_R5,ALPHA8201_R6,ALPHA8201_R7
3636};
3737
38DECLARE_LEGACY_CPU_DEVICE(ALPHA8201, alpha8201);
39DECLARE_LEGACY_CPU_DEVICE(ALPHA8301, alpha8301);
4038
41CPU_DISASSEMBLE( alpha8201 );
39class alpha8201_cpu_device : public cpu_device
40{
41public:
42   // construction/destruction
43   alpha8201_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
44   alpha8201_cpu_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock);
4245
46protected:
47   // device-level overrides
48   virtual void device_start();
49   virtual void device_reset();
50
51   // device_execute_interface overrides
52   virtual UINT32 execute_min_cycles() const { return 1; }
53   virtual UINT32 execute_max_cycles() const { return 16; }
54   virtual UINT32 execute_input_lines() const { return 1; }
55   virtual void execute_run();
56   virtual void execute_set_input(int inputnum, int state);
57
58   // device_memory_interface overrides
59   virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const { return (spacenum == AS_PROGRAM) ? &m_program_config : ( (spacenum == AS_IO) ? &m_io_config : NULL ); }
60
61   // device_state_interface overrides
62   virtual void state_import(const device_state_entry &entry);
63   virtual void state_export(const device_state_entry &entry);
64   void state_string_export(const device_state_entry &entry, astring &string);
65
66   // device_disasm_interface overrides
67   virtual UINT32 disasm_min_opcode_bytes() const { return 1; }
68   virtual UINT32 disasm_max_opcode_bytes() const { return 4; }
69   virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options);
70
71   UINT8 M_RDMEM(UINT16 A) { return m_program->read_byte(A); }
72   void M_WRMEM(UINT16 A,UINT8 V) { m_program->write_byte(A, V); }
73   UINT8 M_RDOP(UINT16 A) { return m_direct->read_decrypted_byte(A); }
74   UINT8 M_RDOP_ARG(UINT16 A) { return m_direct->read_raw_byte(A); }
75   UINT8 RD_REG(UINT8 x) { return m_RAM[(m_regPtr<<3)+(x)]; }
76   void WR_REG(UINT8 x, UINT8 d) { m_RAM[(m_regPtr<<3)+(x)]=(d); }
77
78   unsigned M_RDMEM_OPCODE();
79   void M_ADD(UINT8 dat);
80   void M_ADDB(UINT8 dat);
81   void M_SUB(UINT8 dat);
82   void M_AND(UINT8 dat);
83   void M_OR(UINT8 dat);
84   void M_XOR(UINT8 dat);
85   void M_JMP(UINT8 dat);
86   void M_UNDEFINED();
87   void M_UNDEFINED2();
88
89   void undefined()    { M_UNDEFINED(); }
90   void undefined2()   { M_UNDEFINED2(); }
91
92   void nop()       { }
93   void rora()      { m_cf = m_A &1;     m_A = (m_A>>1) | (m_A<<7); }
94   void rola()      { m_cf = (m_A>>7)&1; m_A = (m_A<<1) | (m_A>>7); }
95   void inc_b()         { M_ADDB(0x02); }
96   void dec_b()         { M_ADDB(0xfe); }
97   void inc_a()         { M_ADD(0x01); }
98   void dec_a()         { M_ADD(0xff); }
99   void cpl()       { m_A ^= 0xff; };
100
101   void ld_a_ix0_0() { m_A = M_RDMEM(m_ix0.w.l+0); }
102   void ld_a_ix0_1() { m_A = M_RDMEM(m_ix0.w.l+1); }
103   void ld_a_ix0_2() { m_A = M_RDMEM(m_ix0.w.l+2); }
104   void ld_a_ix0_3() { m_A = M_RDMEM(m_ix0.w.l+3); }
105   void ld_a_ix0_4() { m_A = M_RDMEM(m_ix0.w.l+4); }
106   void ld_a_ix0_5() { m_A = M_RDMEM(m_ix0.w.l+5); }
107   void ld_a_ix0_6() { m_A = M_RDMEM(m_ix0.w.l+6); }
108   void ld_a_ix0_7() { m_A = M_RDMEM(m_ix0.w.l+7); }
109
110   void ld_a_ix1_0() { m_A = M_RDMEM(m_ix1.w.l+0); }
111   void ld_a_ix1_1() { m_A = M_RDMEM(m_ix1.w.l+1); }
112   void ld_a_ix1_2() { m_A = M_RDMEM(m_ix1.w.l+2); }
113   void ld_a_ix1_3() { m_A = M_RDMEM(m_ix1.w.l+3); }
114   void ld_a_ix1_4() { m_A = M_RDMEM(m_ix1.w.l+4); }
115   void ld_a_ix1_5() { m_A = M_RDMEM(m_ix1.w.l+5); }
116   void ld_a_ix1_6() { m_A = M_RDMEM(m_ix1.w.l+6); }
117   void ld_a_ix1_7() { m_A = M_RDMEM(m_ix1.w.l+7); }
118
119   void ld_ix2_0_a() { M_WRMEM(m_ix2.w.l+0,m_A); }
120   void ld_ix2_1_a() { M_WRMEM(m_ix2.w.l+1,m_A); }
121   void ld_ix2_2_a() { M_WRMEM(m_ix2.w.l+2,m_A); }
122   void ld_ix2_3_a() { M_WRMEM(m_ix2.w.l+3,m_A); }
123   void ld_ix2_4_a() { M_WRMEM(m_ix2.w.l+4,m_A); }
124   void ld_ix2_5_a() { M_WRMEM(m_ix2.w.l+5,m_A); }
125   void ld_ix2_6_a() { M_WRMEM(m_ix2.w.l+6,m_A); }
126   void ld_ix2_7_a() { M_WRMEM(m_ix2.w.l+7,m_A); }
127
128   void ld_ix0_0_b() { m_RAM[(m_B>>1)&0x3f] = M_RDMEM(m_ix0.w.l+0); }
129   void ld_ix0_1_b() { m_RAM[(m_B>>1)&0x3f] = M_RDMEM(m_ix0.w.l+1); }
130   void ld_ix0_2_b() { m_RAM[(m_B>>1)&0x3f] = M_RDMEM(m_ix0.w.l+2); }
131   void ld_ix0_3_b() { m_RAM[(m_B>>1)&0x3f] = M_RDMEM(m_ix0.w.l+3); }
132   void ld_ix0_4_b() { m_RAM[(m_B>>1)&0x3f] = M_RDMEM(m_ix0.w.l+4); }
133   void ld_ix0_5_b() { m_RAM[(m_B>>1)&0x3f] = M_RDMEM(m_ix0.w.l+5); }
134   void ld_ix0_6_b() { m_RAM[(m_B>>1)&0x3f] = M_RDMEM(m_ix0.w.l+6); }
135   void ld_ix0_7_b() { m_RAM[(m_B>>1)&0x3f] = M_RDMEM(m_ix0.w.l+7); }
136
137   void bit_r0_0()  { m_zf = RD_REG(0)&(1<<0)?0:1; }
138   void bit_r0_1()  { m_zf = RD_REG(0)&(1<<1)?0:1; }
139   void bit_r0_2()  { m_zf = RD_REG(0)&(1<<2)?0:1; }
140   void bit_r0_3()  { m_zf = RD_REG(0)&(1<<3)?0:1; }
141   void bit_r0_4()  { m_zf = RD_REG(0)&(1<<4)?0:1; }
142   void bit_r0_5()  { m_zf = RD_REG(0)&(1<<5)?0:1; }
143   void bit_r0_6()  { m_zf = RD_REG(0)&(1<<6)?0:1; }
144   void bit_r0_7()  { m_zf = RD_REG(0)&(1<<7)?0:1; }
145
146   void ld_a_n()    { m_A = M_RDMEM_OPCODE(); }
147
148   void ld_a_r0()   { m_A = RD_REG(0); m_zf = (m_A==0); }
149   void ld_a_r1()   { m_A = RD_REG(1); m_zf = (m_A==0); }
150   void ld_a_r2()   { m_A = RD_REG(2); m_zf = (m_A==0); }
151   void ld_a_r3()   { m_A = RD_REG(3); m_zf = (m_A==0); }
152   void ld_a_r4()   { m_A = RD_REG(4); m_zf = (m_A==0); }
153   void ld_a_r5()   { m_A = RD_REG(5); m_zf = (m_A==0); }
154   void ld_a_r6()   { m_A = RD_REG(6); m_zf = (m_A==0); }
155   void ld_a_r7()   { m_A = RD_REG(7); m_zf = (m_A==0); }
156
157   void ld_r0_a()   { WR_REG(0,m_A); }
158   void ld_r1_a()   { WR_REG(1,m_A); }
159   void ld_r2_a()   { WR_REG(2,m_A); }
160   void ld_r3_a()   { WR_REG(3,m_A); }
161   void ld_r4_a()   { WR_REG(4,m_A); }
162   void ld_r5_a()   { WR_REG(5,m_A); }
163   void ld_r6_a()   { WR_REG(6,m_A); }
164   void ld_r7_a()   { WR_REG(7,m_A); }
165
166   void add_a_n()   { M_ADD(M_RDMEM_OPCODE()); }
167
168   void add_a_r0()  { M_ADD(RD_REG(0)); }
169   void add_a_r1()  { M_ADD(RD_REG(1)); }
170   void add_a_r2()  { M_ADD(RD_REG(2)); }
171   void add_a_r3()  { M_ADD(RD_REG(3)); }
172   void add_a_r4()  { M_ADD(RD_REG(4)); }
173   void add_a_r5()  { M_ADD(RD_REG(5)); }
174   void add_a_r6()  { M_ADD(RD_REG(6)); }
175   void add_a_r7()  { M_ADD(RD_REG(7)); }
176
177   void sub_a_n()   { M_SUB(M_RDMEM_OPCODE()); }
178
179   void sub_a_r0()  { M_SUB(RD_REG(0)); }
180   void sub_a_r1()  { M_SUB(RD_REG(1)); }
181   void sub_a_r2()  { M_SUB(RD_REG(2)); }
182   void sub_a_r3()  { M_SUB(RD_REG(3)); }
183   void sub_a_r4()  { M_SUB(RD_REG(4)); }
184   void sub_a_r5()  { M_SUB(RD_REG(5)); }
185   void sub_a_r6()  { M_SUB(RD_REG(6)); }
186   void sub_a_r7()  { M_SUB(RD_REG(7)); }
187
188   void and_a_n()   { M_AND(M_RDMEM_OPCODE()); }
189
190   void and_a_r0()  { M_AND(RD_REG(0)); }
191   void and_a_r1()  { M_AND(RD_REG(1)); }
192   void and_a_r2()  { M_AND(RD_REG(2)); }
193   void and_a_r3()  { M_AND(RD_REG(3)); }
194   void and_a_r4()  { M_AND(RD_REG(4)); }
195   void and_a_r5()  { M_AND(RD_REG(5)); }
196   void and_a_r6()  { M_AND(RD_REG(6)); }
197   void and_a_r7()  { M_AND(RD_REG(7)); }
198
199   void or_a_n()    { M_OR(M_RDMEM_OPCODE()); }
200
201   void or_a_r0()   { M_OR(RD_REG(0)); }
202   void or_a_r1()   { M_OR(RD_REG(1)); }
203   void or_a_r2()   { M_OR(RD_REG(2)); }
204   void or_a_r3()   { M_OR(RD_REG(3)); }
205   void or_a_r4()   { M_OR(RD_REG(4)); }
206   void or_a_r5()   { M_OR(RD_REG(5)); }
207   void or_a_r6()   { M_OR(RD_REG(6)); }
208   void or_a_r7()   { M_OR(RD_REG(7)); }
209
210   void add_ix0_0()     { }
211   void add_ix0_1()     { m_ix0.b.l += 1; }
212   void add_ix0_2()     { m_ix0.b.l += 2; }
213   void add_ix0_3()     { m_ix0.b.l += 3; }
214   void add_ix0_4()     { m_ix0.b.l += 4; }
215   void add_ix0_5()     { m_ix0.b.l += 5; }
216   void add_ix0_6()     { m_ix0.b.l += 6; }
217   void add_ix0_7()     { m_ix0.b.l += 7; }
218   void add_ix0_8()     { m_ix0.b.l += 8; }
219   void add_ix0_9()     { m_ix0.b.l += 9; }
220   void add_ix0_a()     { m_ix0.b.l += 10; }
221   void add_ix0_b()     { m_ix0.b.l += 11; }
222   void add_ix0_c()     { m_ix0.b.l += 12; }
223   void add_ix0_d()     { m_ix0.b.l += 13; }
224   void add_ix0_e()     { m_ix0.b.l += 14; }
225   void add_ix0_f()     { m_ix0.b.l += 15; }
226
227   void add_ix1_0()     { }
228   void add_ix1_1()     { m_ix1.b.l += 1; }
229   void add_ix1_2()     { m_ix1.b.l += 2; }
230   void add_ix1_3()     { m_ix1.b.l += 3; }
231   void add_ix1_4()     { m_ix1.b.l += 4; }
232   void add_ix1_5()     { m_ix1.b.l += 5; }
233   void add_ix1_6()     { m_ix1.b.l += 6; }
234   void add_ix1_7()     { m_ix1.b.l += 7; }
235   void add_ix1_8()     { m_ix1.b.l += 8; }
236   void add_ix1_9()     { m_ix1.b.l += 9; }
237   void add_ix1_a()     { m_ix1.b.l += 10; }
238   void add_ix1_b()     { m_ix1.b.l += 11; }
239   void add_ix1_c()     { m_ix1.b.l += 12; }
240   void add_ix1_d()     { m_ix1.b.l += 13; }
241   void add_ix1_e()     { m_ix1.b.l += 14; }
242   void add_ix1_f()     { m_ix1.b.l += 15; }
243
244   void add_ix2_0()     { }
245   void add_ix2_1()     { m_ix2.b.l += 1; }
246   void add_ix2_2()     { m_ix2.b.l += 2; }
247   void add_ix2_3()     { m_ix2.b.l += 3; }
248   void add_ix2_4()     { m_ix2.b.l += 4; }
249   void add_ix2_5()     { m_ix2.b.l += 5; }
250   void add_ix2_6()     { m_ix2.b.l += 6; }
251   void add_ix2_7()     { m_ix2.b.l += 7; }
252   void add_ix2_8()     { m_ix2.b.l += 8; }
253   void add_ix2_9()     { m_ix2.b.l += 9; }
254   void add_ix2_a()     { m_ix2.b.l += 10; }
255   void add_ix2_b()     { m_ix2.b.l += 11; }
256   void add_ix2_c()     { m_ix2.b.l += 12; }
257   void add_ix2_d()     { m_ix2.b.l += 13; }
258   void add_ix2_e()     { m_ix2.b.l += 14; }
259   void add_ix2_f()     { m_ix2.b.l += 15; }
260
261   void ld_base_0()     { m_regPtr = 0; }
262   void ld_base_1()     { m_regPtr = 1; }
263   void ld_base_2()     { m_regPtr = 2; }
264   void ld_base_3()     { m_regPtr = 3; }
265   void ld_base_4()     { m_regPtr = 4; }
266   void ld_base_5()     { m_regPtr = 5; }
267   void ld_base_6()     { m_regPtr = 6; }
268   void ld_base_7()     { m_regPtr = 7; }
269
270   void ld_bank_0()     { m_mb = 0; }
271   void ld_bank_1()     { m_mb = 1; }
272   void ld_bank_2()     { m_mb = 2; }
273   void ld_bank_3()     { m_mb = 3; }
274
275   void ld_ix0_n()  { m_ix0.b.l = M_RDMEM_OPCODE(); }
276   void ld_ix1_n()  { m_ix1.b.l = M_RDMEM_OPCODE(); }
277   void ld_ix2_n()  { m_ix2.b.l = M_RDMEM_OPCODE(); }
278   void ld_lp0_n()  { m_lp0 = M_RDMEM_OPCODE(); }
279   void ld_lp1_n()  { m_lp1 = M_RDMEM_OPCODE(); }
280   void ld_lp2_n()  { m_lp2 = M_RDMEM_OPCODE(); }
281   void ld_b_n()    { m_B = M_RDMEM_OPCODE(); }
282
283   void djnz_lp0() { UINT8 i=M_RDMEM_OPCODE(); m_lp0--; if (m_lp0 != 0) M_JMP(i); }
284   void djnz_lp1() { UINT8 i=M_RDMEM_OPCODE(); m_lp1--; if (m_lp1 != 0) M_JMP(i); }
285   void djnz_lp2() { UINT8 i=M_RDMEM_OPCODE(); m_lp2--; if (m_lp2 != 0) M_JMP(i); }
286   void jnz()  { UINT8 i=M_RDMEM_OPCODE(); if (!m_zf) M_JMP(i); }
287   void jnc()  { UINT8 i=M_RDMEM_OPCODE(); if (!m_cf) M_JMP(i);}
288   void jz()   { UINT8 i=M_RDMEM_OPCODE(); if ( m_zf) M_JMP(i); }
289   void jc()   { UINT8 i=M_RDMEM_OPCODE(); if ( m_cf) M_JMP(i);}
290   void jmp()  { M_JMP(M_RDMEM_OPCODE() ); }
291
292   void stop();
293
294   /* ALPHA 8301 : added instruction */
295   void exg_a_ix0()  { UINT8 t=m_A; m_A = m_ix0.b.l; m_ix0.b.l = t; }
296   void exg_a_ix1()  { UINT8 t=m_A; m_A = m_ix1.b.l; m_ix1.b.l = t; }
297   void exg_a_ix2()  { UINT8 t=m_A; m_A = m_ix2.b.l; m_ix2.b.l = t; }
298   void exg_a_lp0()  { UINT8 t=m_A; m_A = m_lp0; m_lp0 = t; }
299   void exg_a_lp1()  { UINT8 t=m_A; m_A = m_lp1; m_lp1 = t; }
300   void exg_a_lp2()  { UINT8 t=m_A; m_A = m_lp2; m_lp2 = t; }
301   void exg_a_b()    { UINT8 t=m_A; m_A = m_B; m_B = t; }
302   void exg_a_rb()   { UINT8 t=m_A; m_A = m_regPtr; m_regPtr = t; }
303
304   void ld_ix0_a()    { m_ix0.b.l = m_A; }
305   void ld_ix1_a()    { m_ix1.b.l = m_A; }
306   void ld_ix2_a()    { m_ix2.b.l = m_A; }
307   void ld_lp0_a()    { m_lp0 = m_A; }
308   void ld_lp1_a()    { m_lp1 = m_A; }
309   void ld_lp2_a()    { m_lp2 = m_A; }
310   void ld_b_a()      { m_B = m_A; }
311   void ld_rb_a()     { m_regPtr = m_A; }
312
313   void exg_ix0_ix1()  { UINT8 t=m_ix1.b.l; m_ix1.b.l = m_ix0.b.l; m_ix0.b.l = t; }
314   void exg_ix0_ix2()  { UINT8 t=m_ix2.b.l; m_ix2.b.l = m_ix0.b.l; m_ix0.b.l = t; }
315
316   void op_d4() { m_A = M_RDMEM( ((m_RAM[(7<<3)+7] & 3) << 8) | M_RDMEM_OPCODE() ); }
317   void op_d5() { M_WRMEM( ((m_RAM[(7<<3)+7] & 3) << 8) | M_RDMEM_OPCODE(), m_A ); }
318   void op_d6() { m_lp0 = M_RDMEM( ((m_RAM[(7<<3)+7] & 3) << 8) | M_RDMEM_OPCODE() ); }
319   void op_d7() { M_WRMEM( ((m_RAM[(7<<3)+7] & 3) << 8) | M_RDMEM_OPCODE(), m_lp0 ); }
320
321   void ld_a_abs() { m_A = M_RDMEM( ((m_mb & 3) << 8) | M_RDMEM_OPCODE() ); }
322   void ld_abs_a() { M_WRMEM( ((m_mb & 3) << 8) | M_RDMEM_OPCODE(), m_A ); }
323
324   void ld_a_r() { m_A = m_RAM[(M_RDMEM_OPCODE()>>1)&0x3f]; }
325   void ld_r_a() { m_RAM[(M_RDMEM_OPCODE()>>1)&0x3f] = m_A; }
326   void op_rep_ld_ix2_b() { do { M_WRMEM(m_ix2.w.l, m_RAM[(m_B>>1)&0x3f]); m_ix2.b.l++; m_B+=2; m_lp0--; } while (m_lp0 != 0); }
327   void op_rep_ld_b_ix0() { do { m_RAM[(m_B>>1)&0x3f] = M_RDMEM(m_ix0.w.l); m_ix0.b.l++; m_B+=2; m_lp0--; } while (m_lp0 != 0); }
328   void ld_rxb_a() { m_RAM[(m_B>>1)&0x3f] = m_A; }
329   void ld_a_rxb() { m_A = m_RAM[(m_B>>1)&0x3f]; }
330   void cmp_a_rxb() { UINT8 i=m_RAM[(m_B>>1)&0x3f];  m_zf = (m_A==i); m_cf = (m_A>=i); }
331   void xor_a_rxb() { M_XOR(m_RAM[(m_B>>1)&0x3f] ); }
332
333   void add_a_cf() { if (m_cf) inc_a(); }
334   void sub_a_cf() { if (m_cf) dec_a(); }
335   void tst_a()     { m_zf = (m_A==0); }
336   void clr_a()     { m_A = 0; m_zf = (m_A==0); }
337   void cmp_a_n()  { UINT8 i=M_RDMEM_OPCODE();  m_zf = (m_A==i); m_cf = (m_A>=i); }
338   void xor_a_n()  { M_XOR(M_RDMEM_OPCODE() ); }
339   void call() { UINT8 i=M_RDMEM_OPCODE(); m_retptr.w.l = m_pc.w.l; M_JMP(i); };
340   void ld_a_ix0_a() { m_A = M_RDMEM(m_ix0.w.l+m_A); }
341   void ret() { m_mb = m_retptr.b.h; M_JMP( m_retptr.b.l ); };
342   void save_zc() { m_savez = m_zf; m_savec = m_cf; };
343   void rest_zc() { m_zf = m_savez; m_cf = m_savec; };
344
345   typedef void ( alpha8201_cpu_device::*opcode_fun ) ();
346
347   /* The opcode table now is a combination of cycle counts and function pointers */
348   struct s_opcode {
349      unsigned cycles;
350      opcode_fun opcode_func;
351   };
352
353   static const s_opcode opcode_8201[256];
354   static const s_opcode opcode_8301[256];
355
356   address_space_config m_program_config;
357   address_space_config m_io_config;
358
359   UINT8 m_RAM[8*8];  /* internal GP register 8 * 8bank       */
360   unsigned m_PREVPC;
361   PAIR  m_retptr;   /* for 8301, return address of CALL       */
362   PAIR  m_pc;       /* 2bit+8bit program counter              */
363   UINT8 m_regPtr;   /* RB register base                       */
364   UINT8 m_mb;       /* MB memory bank reg. latch after Branch */
365   UINT8 m_cf;       /* C flag                                 */
366   UINT8 m_zf;       /* Z flag                                 */
367   UINT8 m_savec;    /* for 8301, save flags                   */
368   UINT8 m_savez;    /* for 8301, save flags                   */
369//
370   PAIR m_ix0;       /* 8bit memory read index reg. */
371   PAIR m_ix1;       /* 8bitmemory read index reg.  */
372   PAIR m_ix2;       /* 8bitmemory write index reg. */
373   UINT8 m_lp0;       /* 8bit loop reg.             */
374   UINT8 m_lp1;       /* 8bit loop reg.             */
375   UINT8 m_lp2;       /* 8bit loop reg.             */
376   UINT8 m_A;         /* 8bit accumerator           */
377   UINT8 m_B;         /* 8bit regiser               */
378//
379   UINT8 m_halt;     /* halt input line                        */
380
381   address_space *m_program;
382   direct_read_data *m_direct;
383   int m_icount;
384   int m_inst_cycles;
385
386   const s_opcode *m_opmap;
387
388   // Used for import/export only
389   UINT8 m_sp;
390   UINT8 m_R[8];
391};
392
393
394class alpha8301_cpu_device : public alpha8201_cpu_device
395{
396public:
397   // construction/destruction
398   alpha8301_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
399};
400
401
402extern const device_type ALPHA8201;
403extern const device_type ALPHA8301;
404
405
43406#endif  /* __ALPH8201_H__ */
trunk/src/emu/cpu/alph8201/alph8201.c
r23802r23803
151151#include "debugger.h"
152152#include "alph8201.h"
153153
154
155const device_type ALPHA8201 = &device_creator<alpha8201_cpu_device>;
156const device_type ALPHA8301 = &device_creator<alpha8301_cpu_device>;
157
158
154159/* instruction cycle count */
155160#define C1 16
156161#define C2 32
r23802r23803
162167#define BREAK_ON_UNKNOWN_OPCODE 0
163168#define BREAK_ON_UNCERTAIN_OPCODE 0
164169
165/* MAME is unnecessary */
166#define HANDLE_HALT_LINE 0
167170
168#define M_RDMEM(A)      cpustate->program->read_byte(A)
169#define M_WRMEM(A,V)    cpustate->program->write_byte(A, V)
170#define M_RDOP(A)       cpustate->direct->read_decrypted_byte(A)
171#define M_RDOP_ARG(A)   cpustate->direct->read_raw_byte(A)
171#define FN(x) &alpha8201_cpu_device::x
172172
173struct alpha8201_state
173
174alpha8201_cpu_device::alpha8201_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
175   : cpu_device(mconfig, ALPHA8201, "ALPHA-8201", tag, owner, clock)
176   , m_program_config("program", ENDIANNESS_LITTLE, 8, 10, 0)
177   , m_io_config("io", ENDIANNESS_LITTLE, 8, 6, 0)
178   , m_opmap(opcode_8201)
174179{
175   UINT8 RAM[8*8];  /* internal GP register 8 * 8bank       */
176   unsigned PREVPC;
177   PAIR  retptr;   /* for 8301, return address of CALL       */
178   PAIR  pc;       /* 2bit+8bit program counter              */
179   UINT8 regPtr;   /* RB register base                       */
180   UINT8 mb;       /* MB memory bank reg. latch after Branch */
181   UINT8 cf;       /* C flag                                 */
182   UINT8 zf;       /* Z flag                                 */
183   UINT8 savec;    /* for 8301, save flags                   */
184   UINT8 savez;    /* for 8301, save flags                   */
185//
186   PAIR ix0;       /* 8bit memory read index reg. */
187   PAIR ix1;       /* 8bitmemory read index reg.  */
188   PAIR ix2;       /* 8bitmemory write index reg. */
189   UINT8 lp0;       /* 8bit loop reg.             */
190   UINT8 lp1;       /* 8bit loop reg.             */
191   UINT8 lp2;       /* 8bit loop reg.             */
192   UINT8 A;         /* 8bit accumerator           */
193   UINT8 B;         /* 8bit regiser               */
194//
195#if HANDLE_HALT_LINE
196   UINT8 halt;     /* halt input line                        */
197#endif
180}
198181
199   legacy_cpu_device *device;
200   address_space *program;
201   direct_read_data *direct;
202   int icount;
203   int inst_cycles;
204};
205182
206/* The opcode table now is a combination of cycle counts and function pointers */
207struct s_opcode {
208   unsigned cycles;
209   void (*function) (alpha8201_state *cpustate);
210};
183alpha8201_cpu_device::alpha8201_cpu_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock)
184   : cpu_device(mconfig, type, name, tag, owner, clock)
185   , m_program_config("program", ENDIANNESS_LITTLE, 8, 10, 0)
186   , m_io_config("io", ENDIANNESS_LITTLE, 8, 6, 0)
187   , m_opmap(opcode_8201)
188{
189}
211190
212
213#define PC              pc.w.l
214#define PCL             pc.b.l
215#define RD_REG(x)       cpustate->RAM[(cpustate->regPtr<<3)+(x)]
216#define WR_REG(x,d)     cpustate->RAM[(cpustate->regPtr<<3)+(x)]=(d)
217#define IX0             ix0.b.l
218#define IX1             ix1.b.l
219#define IX2             ix2.b.l
220#define BIX0            ix0.w.l
221#define BIX1            ix1.w.l
222#define BIX2            ix2.w.l
223#define LP0             lp0
224#define LP1             lp1
225#define LP2             lp2
226
227INLINE alpha8201_state *get_safe_token(device_t *device)
191alpha8301_cpu_device::alpha8301_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
192   : alpha8201_cpu_device(mconfig, ALPHA8301, "ALPHA-8301", tag, owner, clock)
228193{
229   assert(device != NULL);
230   assert(device->type() == ALPHA8201 ||
231         device->type() == ALPHA8301);
232   return (alpha8201_state *)downcast<legacy_cpu_device *>(device)->token();
194   m_opmap = opcode_8301;
233195}
234196
197
235198/* Get next opcode argument and increment program counter */
236INLINE unsigned M_RDMEM_OPCODE (alpha8201_state *cpustate)
199unsigned alpha8201_cpu_device::M_RDMEM_OPCODE()
237200{
238201   unsigned retval;
239   retval=M_RDOP_ARG(cpustate->PC);
240   cpustate->PCL++;
202   retval=M_RDOP_ARG(m_pc.w.l);
203   m_pc.b.l++;
241204   return retval;
242205}
243206
244INLINE void M_ADD(alpha8201_state *cpustate, UINT8 dat)
207void alpha8201_cpu_device::M_ADD(UINT8 dat)
245208{
246   UINT16 temp = cpustate->A + dat;
247   cpustate->A = temp & 0xff;
248   cpustate->zf = (cpustate->A==0);
249   cpustate->cf = temp>>8;
209   UINT16 temp = m_A + dat;
210   m_A = temp & 0xff;
211   m_zf = (m_A==0);
212   m_cf = temp>>8;
250213}
251214
252INLINE void M_ADDB(alpha8201_state *cpustate, UINT8 dat)
215void alpha8201_cpu_device::M_ADDB(UINT8 dat)
253216{
254   UINT16 temp = cpustate->B + dat;
255   cpustate->B = temp & 0xff;
256   cpustate->zf = (cpustate->B==0);
257   cpustate->cf = temp>>8;
217   UINT16 temp = m_B + dat;
218   m_B = temp & 0xff;
219   m_zf = (m_B==0);
220   m_cf = temp>>8;
258221}
259222
260INLINE void M_SUB(alpha8201_state *cpustate, UINT8 dat)
223void alpha8201_cpu_device::M_SUB(UINT8 dat)
261224{
262   cpustate->cf = (cpustate->A>=dat);  // cpustate->cf is No Borrow
263   cpustate->A -= dat;
264   cpustate->zf = (cpustate->A==0);
225   m_cf = (m_A>=dat);  // m_cf is No Borrow
226   m_A -= dat;
227   m_zf = (m_A==0);
265228}
266229
267INLINE void M_AND(alpha8201_state *cpustate, UINT8 dat)
230void alpha8201_cpu_device::M_AND(UINT8 dat)
268231{
269   cpustate->A &= dat;
270   cpustate->zf = (cpustate->A==0);
232   m_A &= dat;
233   m_zf = (m_A==0);
271234}
272235
273INLINE void M_OR(alpha8201_state *cpustate, UINT8 dat)
236void alpha8201_cpu_device::M_OR(UINT8 dat)
274237{
275   cpustate->A |= dat;
276   cpustate->zf = (cpustate->A==0);
238   m_A |= dat;
239   m_zf = (m_A==0);
277240}
278241
279INLINE void M_XOR(alpha8201_state *cpustate, UINT8 dat)
242void alpha8201_cpu_device::M_XOR(UINT8 dat)
280243{
281   cpustate->A ^= dat;
282   cpustate->zf = (cpustate->A==0);
283   cpustate->cf = 0;
244   m_A ^= dat;
245   m_zf = (m_A==0);
246   m_cf = 0;
284247}
285248
286INLINE void M_JMP(alpha8201_state *cpustate, UINT8 dat)
249void alpha8201_cpu_device::M_JMP(UINT8 dat)
287250{
288   cpustate->PCL = dat;
251   m_pc.b.l = dat;
289252   /* update pc page */
290   cpustate->pc.b.h  = cpustate->ix0.b.h = cpustate->ix1.b.h = cpustate->ix2.b.h = cpustate->mb & 3;
253   m_pc.b.h  = m_ix0.b.h = m_ix1.b.h = m_ix2.b.h = m_mb & 3;
291254}
292255
293INLINE void M_UNDEFINED(alpha8201_state *cpustate)
256void alpha8201_cpu_device::M_UNDEFINED()
294257{
295   logerror("alpha8201:  cpustate->PC = %03x,  Unimplemented opcode = %02x\n", cpustate->PC-1, M_RDMEM(cpustate->PC-1));
258   logerror("alpha8201:  PC = %03x,  Unimplemented opcode = %02x\n", m_pc.w.l-1, M_RDMEM(m_pc.w.l-1));
296259#if SHOW_MESSAGE_CONSOLE
297   mame_printf_debug("alpha8201:  cpustate->PC = %03x,  Unimplemented opcode = %02x\n", cpustate->PC-1, M_RDMEM(cpustate->PC-1));
260   mame_printf_debug("alpha8201:  PC = %03x,  Unimplemented opcode = %02x\n", m_pc.w.l-1, M_RDMEM(m_pc.w.l-1));
298261#endif
299262#if BREAK_ON_UNKNOWN_OPCODE
300   debugger_break(cpustate->device->machine());
263   debugger_break(machine());
301264#endif
302265}
303266
304INLINE void M_UNDEFINED2(alpha8201_state *cpustate)
267void alpha8201_cpu_device::M_UNDEFINED2()
305268{
306   UINT8 op  = M_RDOP(cpustate->PC-1);
307   UINT8 imm = M_RDMEM_OPCODE(cpustate);
308   logerror("alpha8201:  cpustate->PC = %03x,  Unimplemented opcode = %02x,%02x\n", cpustate->PC-2, op,imm);
269   UINT8 op  = M_RDOP(m_pc.w.l-1);
270   UINT8 imm = M_RDMEM_OPCODE();
271   logerror("alpha8201:  PC = %03x,  Unimplemented opcode = %02x,%02x\n", m_pc.w.l-2, op,imm);
309272#if SHOW_MESSAGE_CONSOLE
310   mame_printf_debug("alpha8201:  cpustate->PC = %03x,  Unimplemented opcode = %02x,%02x\n", cpustate->PC-2, op,imm);
273   mame_printf_debug("alpha8201:  PC = %03x,  Unimplemented opcode = %02x,%02x\n", m_pc.w.l-2, op,imm);
311274#endif
312275#if BREAK_ON_UNKNOWN_OPCODE
313   debugger_break(cpustate->device->machine());
276   debugger_break(machine());
314277#endif
315278}
316279
317static void undefined(alpha8201_state *cpustate)    { M_UNDEFINED(cpustate); }
318static void undefined2(alpha8201_state *cpustate)   { M_UNDEFINED2(cpustate); }
319280
320static void nop(alpha8201_state *cpustate)       { }
321static void rora(alpha8201_state *cpustate)      { cpustate->cf = cpustate->A &1;     cpustate->A = (cpustate->A>>1) | (cpustate->A<<7); }
322static void rola(alpha8201_state *cpustate)      { cpustate->cf = (cpustate->A>>7)&1; cpustate->A = (cpustate->A<<1) | (cpustate->A>>7); }
323static void inc_b(alpha8201_state *cpustate)         { M_ADDB(cpustate, 0x02); }
324static void dec_b(alpha8201_state *cpustate)         { M_ADDB(cpustate, 0xfe); }
325static void inc_a(alpha8201_state *cpustate)         { M_ADD(cpustate, 0x01); }
326static void dec_a(alpha8201_state *cpustate)         { M_ADD(cpustate, 0xff); }
327static void cpl(alpha8201_state *cpustate)       { cpustate->A ^= 0xff; };
281void alpha8201_cpu_device::stop()
282{
283   UINT8 pcptr = M_RDMEM(0x001) & 0x1f;
284   M_WRMEM(pcptr,(M_RDMEM(pcptr)&0xf)+0x08); /* mark entry point ODD to HALT */
285   m_mb |= 0x08;        /* mark internal HALT state */
286}
328287
329static void ld_a_ix0_0(alpha8201_state *cpustate) { cpustate->A = M_RDMEM(cpustate->BIX0+0); }
330static void ld_a_ix0_1(alpha8201_state *cpustate) { cpustate->A = M_RDMEM(cpustate->BIX0+1); }
331static void ld_a_ix0_2(alpha8201_state *cpustate) { cpustate->A = M_RDMEM(cpustate->BIX0+2); }
332static void ld_a_ix0_3(alpha8201_state *cpustate) { cpustate->A = M_RDMEM(cpustate->BIX0+3); }
333static void ld_a_ix0_4(alpha8201_state *cpustate) { cpustate->A = M_RDMEM(cpustate->BIX0+4); }
334static void ld_a_ix0_5(alpha8201_state *cpustate) { cpustate->A = M_RDMEM(cpustate->BIX0+5); }
335static void ld_a_ix0_6(alpha8201_state *cpustate) { cpustate->A = M_RDMEM(cpustate->BIX0+6); }
336static void ld_a_ix0_7(alpha8201_state *cpustate) { cpustate->A = M_RDMEM(cpustate->BIX0+7); }
337288
338static void ld_a_ix1_0(alpha8201_state *cpustate) { cpustate->A = M_RDMEM(cpustate->BIX1+0); }
339static void ld_a_ix1_1(alpha8201_state *cpustate) { cpustate->A = M_RDMEM(cpustate->BIX1+1); }
340static void ld_a_ix1_2(alpha8201_state *cpustate) { cpustate->A = M_RDMEM(cpustate->BIX1+2); }
341static void ld_a_ix1_3(alpha8201_state *cpustate) { cpustate->A = M_RDMEM(cpustate->BIX1+3); }
342static void ld_a_ix1_4(alpha8201_state *cpustate) { cpustate->A = M_RDMEM(cpustate->BIX1+4); }
343static void ld_a_ix1_5(alpha8201_state *cpustate) { cpustate->A = M_RDMEM(cpustate->BIX1+5); }
344static void ld_a_ix1_6(alpha8201_state *cpustate) { cpustate->A = M_RDMEM(cpustate->BIX1+6); }
345static void ld_a_ix1_7(alpha8201_state *cpustate) { cpustate->A = M_RDMEM(cpustate->BIX1+7); }
289const alpha8201_cpu_device::s_opcode alpha8201_cpu_device::opcode_8201[256]=
290{
291   {C1, FN(nop)        },{C1,FN(rora)      },{C1, FN(rola)      },{C1,FN(inc_b)     },{C1,FN(dec_b)     },{C1, FN(inc_a)    },{C1, FN(dec_a)    },{C1, FN(cpl)      },
292   {C2,FN(ld_a_ix0_0)  },{C2,FN(ld_a_ix0_1)},{C2, FN(ld_a_ix0_2)},{C2,FN(ld_a_ix0_3)},{C2,FN(ld_a_ix0_4)},{C2,FN(ld_a_ix0_5)},{C2,FN(ld_a_ix0_6)},{C2,FN(ld_a_ix0_7)},
293   {C2,FN(ld_a_ix1_0)  },{C2,FN(ld_a_ix1_1)},{C2, FN(ld_a_ix1_2)},{C2,FN(ld_a_ix1_3)},{C2,FN(ld_a_ix1_4)},{C2,FN(ld_a_ix1_5)},{C2,FN(ld_a_ix1_6)},{C2,FN(ld_a_ix1_7)},
294   {C2,FN(ld_ix2_0_a)  },{C2,FN(ld_ix2_1_a)},{C2, FN(ld_ix2_2_a)},{C2,FN(ld_ix2_3_a)},{C2,FN(ld_ix2_4_a)},{C2,FN(ld_ix2_5_a)},{C2,FN(ld_ix2_6_a)},{C2,FN(ld_ix2_7_a)},
295/* 20 */
296   {C2,FN(ld_ix0_0_b)  },{C2,FN(ld_ix0_1_b)},{C2, FN(ld_ix0_2_b)},{C2,FN(ld_ix0_3_b)},{C2,FN(ld_ix0_4_b)},{C2,FN(ld_ix0_5_b)},{C2,FN(ld_ix0_6_b)},{C2,FN(ld_ix0_7_b)},
297   {C2,FN(undefined)   },{C2,FN(undefined) },{C2, FN(undefined) },{C2,FN(undefined) },{C2,FN(undefined) },{C2,FN(undefined) },{C2,FN(undefined) },{C2,FN(undefined) },
298   {C2,FN(undefined)   },{C2,FN(undefined) },{C2, FN(undefined) },{C2,FN(undefined) },{C2,FN(undefined) },{C2,FN(undefined) },{C2,FN(undefined) },{C2,FN(undefined) },
299   {C2,FN(bit_r0_0)    },{C2,FN(bit_r0_1)  },{C2, FN(bit_r0_2) },{C2, FN(bit_r0_3) },{C2, FN(bit_r0_4) },{C2, FN(bit_r0_5) },{C2, FN(bit_r0_6) },{C2, FN(bit_r0_7) },
300/* 40 : 8201 */
301   {C2, FN(ld_a_r0)    },{C2, FN(ld_r0_a)  },{C2, FN(ld_a_r1)  },{C2, FN(ld_r1_a)  },{C2, FN(ld_a_r2)  },{C2, FN(ld_r2_a)  },{C2, FN(ld_a_r3)  },{C2, FN(ld_r3_a)  },
302   {C2, FN(ld_a_r4)    },{C2, FN(ld_r4_a)  },{C2, FN(ld_a_r5)  },{C2, FN(ld_r5_a)  },{C2, FN(ld_a_r6)  },{C2, FN(ld_r6_a)  },{C2, FN(ld_a_r7)  },{C2, FN(ld_r7_a)  },
303   {C1, FN(add_a_r0)   },{C1, FN(sub_a_r0) },{C1, FN(add_a_r1) },{C1, FN(sub_a_r1) },{C1, FN(add_a_r2) },{C1, FN(sub_a_r2) },{C1, FN(add_a_r3) },{C1, FN(sub_a_r3) },
304   {C1, FN(add_a_r4)   },{C1, FN(sub_a_r4) },{C1, FN(add_a_r5) },{C1, FN(sub_a_r5) },{C1, FN(add_a_r6) },{C1, FN(sub_a_r6) },{C1, FN(add_a_r7) },{C1, FN(sub_a_r7) },
305   {C1, FN(and_a_r0)   },{C1, FN(or_a_r0)  },{C1, FN(and_a_r1) },{C1, FN(or_a_r1)  },{C1, FN(and_a_r2) },{C1, FN(or_a_r2)  },{C1, FN(and_a_r3) },{C1, FN(or_a_r3)  },
306   {C1, FN(and_a_r4)   },{C1, FN(or_a_r4)  },{C1, FN(and_a_r5) },{C1, FN(or_a_r5)  },{C1, FN(and_a_r6) },{C1, FN(or_a_r6)  },{C1, FN(and_a_r7) },{C1, FN(or_a_r7)  },
307   {C1, FN(add_ix0_0)  },{C1, FN(add_ix0_1)},{C1, FN(add_ix0_2)},{C1, FN(add_ix0_3)},{C1, FN(add_ix0_4)},{C1, FN(add_ix0_5)},{C1, FN(add_ix0_6)},{C1, FN(add_ix0_7)},
308   {C1, FN(add_ix0_8)  },{C1, FN(add_ix0_9)},{C1, FN(add_ix0_a)},{C1, FN(add_ix0_b)},{C1, FN(add_ix0_c)},{C1, FN(add_ix0_d)},{C1, FN(add_ix0_e)},{C1, FN(add_ix0_f)},
309/* 80 : 8201 */
310   {C1, FN(add_ix1_0)  },{C1, FN(add_ix1_1)},{C1, FN(add_ix1_2)},{C1, FN(add_ix1_3)},{C1, FN(add_ix1_4)},{C1, FN(add_ix1_5)},{C1, FN(add_ix1_6)},{C1, FN(add_ix1_7)},
311   {C1, FN(add_ix1_8)  },{C1, FN(add_ix1_9)},{C1, FN(add_ix1_a)},{C1, FN(add_ix1_b)},{C1, FN(add_ix1_c)},{C1, FN(add_ix1_d)},{C1, FN(add_ix1_e)},{C1, FN(add_ix1_f)},
312   {C1, FN(add_ix2_0)  },{C1, FN(add_ix2_1)},{C1, FN(add_ix2_2)},{C1, FN(add_ix2_3)},{C1, FN(add_ix2_4)},{C1, FN(add_ix2_5)},{C1, FN(add_ix2_6)},{C1, FN(add_ix2_7)},
313   {C1, FN(add_ix2_8)  },{C1, FN(add_ix2_9)},{C1, FN(add_ix2_a)},{C1, FN(add_ix2_b)},{C1, FN(add_ix2_c)},{C1, FN(add_ix2_d)},{C1, FN(add_ix2_e)},{C1, FN(add_ix2_f)},
314   {C1, FN(ld_base_0)  },{C1, FN(ld_base_1)},{C1, FN(ld_base_2)},{C1, FN(ld_base_3)},{C1, FN(ld_base_4)},{C1, FN(ld_base_5)},{C1, FN(ld_base_6)},{C1, FN(ld_base_7)},
315   {C1, FN(undefined)  },{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined)},
316   {C1, FN(ld_bank_0)  },{C1, FN(ld_bank_1)},{C1, FN(ld_bank_2)},{C1, FN(ld_bank_3)},{C2, FN(stop)     },{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined)},
317   {C1, FN(undefined)  },{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined)},
318/* c0 : 8201 */
319   {C2, FN(ld_ix0_n)   },{C2, FN(ld_ix1_n) },{C2, FN(ld_ix2_n) },{C2, FN(ld_a_n)   },{C2, FN(ld_lp0_n) },{C2, FN(ld_lp1_n) },{C2, FN(ld_lp2_n) },{C2, FN(ld_b_n)   },
320   {C2, FN(add_a_n)    },{C2, FN(sub_a_n)  },{C2, FN(and_a_n)  },{C2, FN(or_a_n)   },{C2, FN(djnz_lp0) },{C2, FN(djnz_lp1) },{C2, FN(djnz_lp2) },{C2, FN(jnz)      },
321   {C2, FN(jnc)            },{C2, FN(jz)       },{C2, FN(jmp)      },{C2,FN(undefined2)},{C2,FN(undefined2)},{C2,FN(undefined2)},{C2,FN(undefined2)},{C2, FN(undefined2)},
322   {C2, FN(undefined2) },{C2,FN(undefined2)},{C2,FN(undefined2)},{C2,FN(undefined2)},{C2,FN(undefined2)},{C2,FN(undefined2)},{C2,FN(undefined2)},{C2, FN(undefined2)},
323/* E0 : 8201*/
324   {C1, FN(undefined)  },{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined)},
325   {C1, FN(undefined)  },{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined)},
326   {C1, FN(undefined)  },{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined)},
327   {C1, FN(undefined)  },{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined) }
328};
346329
347static void ld_ix2_0_a(alpha8201_state *cpustate) { M_WRMEM(cpustate->BIX2+0,cpustate->A); }
348static void ld_ix2_1_a(alpha8201_state *cpustate) { M_WRMEM(cpustate->BIX2+1,cpustate->A); }
349static void ld_ix2_2_a(alpha8201_state *cpustate) { M_WRMEM(cpustate->BIX2+2,cpustate->A); }
350static void ld_ix2_3_a(alpha8201_state *cpustate) { M_WRMEM(cpustate->BIX2+3,cpustate->A); }
351static void ld_ix2_4_a(alpha8201_state *cpustate) { M_WRMEM(cpustate->BIX2+4,cpustate->A); }
352static void ld_ix2_5_a(alpha8201_state *cpustate) { M_WRMEM(cpustate->BIX2+5,cpustate->A); }
353static void ld_ix2_6_a(alpha8201_state *cpustate) { M_WRMEM(cpustate->BIX2+6,cpustate->A); }
354static void ld_ix2_7_a(alpha8201_state *cpustate) { M_WRMEM(cpustate->BIX2+7,cpustate->A); }
355330
356static void ld_ix0_0_b(alpha8201_state *cpustate) { cpustate->RAM[(cpustate->B>>1)&0x3f] = M_RDMEM(cpustate->BIX0+0); }
357static void ld_ix0_1_b(alpha8201_state *cpustate) { cpustate->RAM[(cpustate->B>>1)&0x3f] = M_RDMEM(cpustate->BIX0+1); }
358static void ld_ix0_2_b(alpha8201_state *cpustate) { cpustate->RAM[(cpustate->B>>1)&0x3f] = M_RDMEM(cpustate->BIX0+2); }
359static void ld_ix0_3_b(alpha8201_state *cpustate) { cpustate->RAM[(cpustate->B>>1)&0x3f] = M_RDMEM(cpustate->BIX0+3); }
360static void ld_ix0_4_b(alpha8201_state *cpustate) { cpustate->RAM[(cpustate->B>>1)&0x3f] = M_RDMEM(cpustate->BIX0+4); }
361static void ld_ix0_5_b(alpha8201_state *cpustate) { cpustate->RAM[(cpustate->B>>1)&0x3f] = M_RDMEM(cpustate->BIX0+5); }
362static void ld_ix0_6_b(alpha8201_state *cpustate) { cpustate->RAM[(cpustate->B>>1)&0x3f] = M_RDMEM(cpustate->BIX0+6); }
363static void ld_ix0_7_b(alpha8201_state *cpustate) { cpustate->RAM[(cpustate->B>>1)&0x3f] = M_RDMEM(cpustate->BIX0+7); }
331const alpha8201_cpu_device::s_opcode alpha8201_cpu_device::opcode_8301[256]=
332{
333   {C1, FN(nop)        },{C1,FN(rora)      },{C1, FN(rola)      },{C1,FN(inc_b)     },{C1,FN(dec_b)     },{C1, FN(inc_a)    },{C1, FN(dec_a)    },{C1, FN(cpl)      },
334   {C2,FN(ld_a_ix0_0)  },{C2,FN(ld_a_ix0_1)},{C2, FN(ld_a_ix0_2)},{C2,FN(ld_a_ix0_3)},{C2,FN(ld_a_ix0_4)},{C2,FN(ld_a_ix0_5)},{C2,FN(ld_a_ix0_6)},{C2,FN(ld_a_ix0_7)},
335   {C2,FN(ld_a_ix1_0)  },{C2,FN(ld_a_ix1_1)},{C2, FN(ld_a_ix1_2)},{C2,FN(ld_a_ix1_3)},{C2,FN(ld_a_ix1_4)},{C2,FN(ld_a_ix1_5)},{C2,FN(ld_a_ix1_6)},{C2,FN(ld_a_ix1_7)},
336   {C2,FN(ld_ix2_0_a)  },{C2,FN(ld_ix2_1_a)},{C2, FN(ld_ix2_2_a)},{C2,FN(ld_ix2_3_a)},{C2,FN(ld_ix2_4_a)},{C2,FN(ld_ix2_5_a)},{C2,FN(ld_ix2_6_a)},{C2,FN(ld_ix2_7_a)},
337/* 20 : 8301 */
338   {C2,FN(ld_ix0_0_b)  },{C2,FN(ld_ix0_1_b)},{C2, FN(ld_ix0_2_b)},{C2,FN(ld_ix0_3_b)},{C2,FN(ld_ix0_4_b)},{C2,FN(ld_ix0_5_b)},{C2,FN(ld_ix0_6_b)},{C2,FN(ld_ix0_7_b)},
339   {C2,FN(undefined)   },{C2,FN(undefined) },{C2, FN(undefined) },{C2,FN(undefined) },{C2,FN(undefined) },{C2,FN(undefined) },{C2,FN(undefined) },{C2,FN(undefined) },
340   {C2,FN(undefined)   },{C2,FN(undefined) },{C2, FN(undefined) },{C2,FN(undefined) },{C2,FN(undefined) },{C2,FN(undefined) },{C2,FN(undefined) },{C2,FN(undefined) },
341   {C2,FN(bit_r0_0)    },{C2,FN(bit_r0_1)  },{C2, FN(bit_r0_2) },{C2, FN(bit_r0_3) },{C2, FN(bit_r0_4) },{C2, FN(bit_r0_5) },{C2, FN(bit_r0_6) },{C2, FN(bit_r0_7) },
342/* 40 : 8301 */
343   {C2, FN(ld_a_r0)    },{C2, FN(ld_r0_a)  },{C2, FN(ld_a_r1)  },{C2, FN(ld_r1_a)  },{C2, FN(ld_a_r2)  },{C2, FN(ld_r2_a)  },{C2, FN(ld_a_r3)  },{C2, FN(ld_r3_a)  },
344   {C2, FN(ld_a_r4)    },{C2, FN(ld_r4_a)  },{C2, FN(ld_a_r5)  },{C2, FN(ld_r5_a)  },{C2, FN(ld_a_r6)  },{C2, FN(ld_r6_a)  },{C2, FN(ld_a_r7)  },{C2, FN(ld_r7_a)  },
345   {C1, FN(add_a_r0)   },{C1, FN(sub_a_r0) },{C1, FN(add_a_r1) },{C1, FN(sub_a_r1) },{C1, FN(add_a_r2) },{C1, FN(sub_a_r2) },{C1, FN(add_a_r3) },{C1, FN(sub_a_r3) },
346   {C1, FN(add_a_r4)   },{C1, FN(sub_a_r4) },{C1, FN(add_a_r5) },{C1, FN(sub_a_r5) },{C1, FN(add_a_r6) },{C1, FN(sub_a_r6) },{C1, FN(add_a_r7) },{C1, FN(sub_a_r7) },
347/* 60 : 8301 */
348   {C1, FN(and_a_r0)   },{C1, FN(or_a_r0)  },{C1, FN(and_a_r1) },{C1, FN(or_a_r1)  },{C1, FN(and_a_r2) },{C1, FN(or_a_r2)  },{C1, FN(and_a_r3) },{C1, FN(or_a_r3)  },
349   {C1, FN(and_a_r4)   },{C1, FN(or_a_r4)  },{C1, FN(and_a_r5) },{C1, FN(or_a_r5)  },{C1, FN(and_a_r6) },{C1, FN(or_a_r6)  },{C1, FN(and_a_r7) },{C1, FN(or_a_r7)  },
350   {C1, FN(add_ix0_0)  },{C1, FN(add_ix0_1)},{C1, FN(add_ix0_2)},{C1, FN(add_ix0_3)},{C1, FN(add_ix0_4)},{C1, FN(add_ix0_5)},{C1, FN(add_ix0_6)},{C1, FN(add_ix0_7)},
351   {C1, FN(add_ix0_8)  },{C1, FN(add_ix0_9)},{C1, FN(add_ix0_a)},{C1, FN(add_ix0_b)},{C1, FN(add_ix0_c)},{C1, FN(add_ix0_d)},{C1, FN(add_ix0_e)},{C1, FN(add_ix0_f)},
352/* 80 : 8301 */
353   {C1, FN(add_ix1_0)  },{C1, FN(add_ix1_1)},{C1, FN(add_ix1_2)},{C1, FN(add_ix1_3)},{C1, FN(add_ix1_4)},{C1, FN(add_ix1_5)},{C1, FN(add_ix1_6)},{C1, FN(add_ix1_7)},
354   {C1, FN(add_ix1_8)  },{C1, FN(add_ix1_9)},{C1, FN(add_ix1_a)},{C1, FN(add_ix1_b)},{C1, FN(add_ix1_c)},{C1, FN(add_ix1_d)},{C1, FN(add_ix1_e)},{C1, FN(add_ix1_f)},
355   {C1, FN(add_ix2_0)  },{C1, FN(add_ix2_1)},{C1, FN(add_ix2_2)},{C1, FN(add_ix2_3)},{C1, FN(add_ix2_4)},{C1, FN(add_ix2_5)},{C1, FN(add_ix2_6)},{C1, FN(add_ix2_7)},
356   {C1, FN(add_ix2_8)  },{C1, FN(add_ix2_9)},{C1, FN(add_ix2_a)},{C1, FN(add_ix2_b)},{C1, FN(add_ix2_c)},{C1, FN(add_ix2_d)},{C1, FN(add_ix2_e)},{C1, FN(add_ix2_f)},
357/* A0 : 8301 */
358   {C1, FN(ld_base_0)  },{C1, FN(ld_base_1)},{C1, FN(ld_base_2)},{C1, FN(ld_base_3)},{C1, FN(ld_base_4)},{C1, FN(ld_base_5)},{C1, FN(ld_base_6)},{C1, FN(ld_base_7)},
359   {C1, FN(undefined)  },{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined)},
360   {C1, FN(ld_bank_0)  },{C1, FN(ld_bank_1)},{C1, FN(ld_bank_2)},{C1, FN(ld_bank_3)},{C2, FN(stop)     },{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined)},
361   {C1, FN(undefined)  },{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined)},
362/* c0 : 8301 */
363   {C2, FN(ld_ix0_n)   },{C2, FN(ld_ix1_n)},{C2, FN(ld_ix2_n)  },{C2, FN(ld_a_n)   },{C2, FN(ld_lp0_n) },{C2, FN(ld_lp1_n) },{C2, FN(ld_lp2_n) },{C2, FN(ld_b_n)   },
364   {C2, FN(add_a_n)    },{C2, FN(sub_a_n)  },{C2, FN(and_a_n)  },{C2, FN(or_a_n)   },{C2, FN(djnz_lp0) },{C2, FN(djnz_lp1) },{C2, FN(djnz_lp2) },{C2, FN(jnz)      },
365   {C2, FN(jnc)            },{C2, FN(jz)       },{C2, FN(jmp)      },{C2,FN(undefined2)},{C2, FN(op_d4)    },{C2, FN(op_d5)    },{C2, FN(op_d6)    },{C2, FN(op_d7)    },
366   {C2, FN(ld_a_abs)  },{C2, FN(ld_abs_a)},{C2,FN(cmp_a_n) },{C2,FN(xor_a_n)   },{C2, FN(ld_a_r)   },{C2, FN(ld_r_a)   },{C2, FN(jc)       },{C2, FN(call)},
367/* E0 : 8301 */
368   {C1, FN(exg_a_ix0)  },{C1, FN(exg_a_ix1)},{C1, FN(exg_a_ix2)},{C1, FN(exg_a_lp1)},{C1, FN(exg_a_lp2)},{C1, FN(exg_a_b)  },{C1, FN(exg_a_lp0)},{C1, FN(exg_a_rb) },
369   {C1, FN(ld_ix0_a)   },{C1, FN(ld_ix1_a) },{C1, FN(ld_ix2_a) },{C1, FN(ld_lp1_a) },{C1, FN(ld_lp2_a) },{C1, FN(ld_b_a)   },{C1, FN(ld_lp0_a) },{C1, FN(ld_rb_a)  },
370   {C1,FN(exg_ix0_ix1)},{C1,FN(exg_ix0_ix2)},{C1,FN(op_rep_ld_ix2_b)},{C1, FN(op_rep_ld_b_ix0)},{C1, FN(save_zc)},{C1, FN(rest_zc)},{C1, FN(ld_rxb_a) },{C1, FN(ld_a_rxb) },
371   {C1, FN(cmp_a_rxb) },{C1, FN(xor_a_rxb)},{C1, FN(add_a_cf) },{C1, FN(sub_a_cf) },{C1, FN(tst_a)    },{C1, FN(clr_a)    },{C1, FN(ld_a_ix0_a)},{C1, FN(ret)     }
372};
364373
365static void bit_r0_0(alpha8201_state *cpustate)  { cpustate->zf = RD_REG(0)&(1<<0)?0:1; }
366static void bit_r0_1(alpha8201_state *cpustate)  { cpustate->zf = RD_REG(0)&(1<<1)?0:1; }
367static void bit_r0_2(alpha8201_state *cpustate)  { cpustate->zf = RD_REG(0)&(1<<2)?0:1; }
368static void bit_r0_3(alpha8201_state *cpustate)  { cpustate->zf = RD_REG(0)&(1<<3)?0:1; }
369static void bit_r0_4(alpha8201_state *cpustate)  { cpustate->zf = RD_REG(0)&(1<<4)?0:1; }
370static void bit_r0_5(alpha8201_state *cpustate)  { cpustate->zf = RD_REG(0)&(1<<5)?0:1; }
371static void bit_r0_6(alpha8201_state *cpustate)  { cpustate->zf = RD_REG(0)&(1<<6)?0:1; }
372static void bit_r0_7(alpha8201_state *cpustate)  { cpustate->zf = RD_REG(0)&(1<<7)?0:1; }
373374
374static void ld_a_n(alpha8201_state *cpustate)    { cpustate->A = M_RDMEM_OPCODE(cpustate); }
375/****************************************************************************
376 * Initialize emulation
377 ****************************************************************************/
378void alpha8201_cpu_device::device_start()
379{
380   m_program = &space(AS_PROGRAM);
381   m_direct = &m_program->direct();
375382
376static void ld_a_r0(alpha8201_state *cpustate)   { cpustate->A = RD_REG(0); cpustate->zf = (cpustate->A==0); }
377static void ld_a_r1(alpha8201_state *cpustate)   { cpustate->A = RD_REG(1); cpustate->zf = (cpustate->A==0); }
378static void ld_a_r2(alpha8201_state *cpustate)   { cpustate->A = RD_REG(2); cpustate->zf = (cpustate->A==0); }
379static void ld_a_r3(alpha8201_state *cpustate)   { cpustate->A = RD_REG(3); cpustate->zf = (cpustate->A==0); }
380static void ld_a_r4(alpha8201_state *cpustate)   { cpustate->A = RD_REG(4); cpustate->zf = (cpustate->A==0); }
381static void ld_a_r5(alpha8201_state *cpustate)   { cpustate->A = RD_REG(5); cpustate->zf = (cpustate->A==0); }
382static void ld_a_r6(alpha8201_state *cpustate)   { cpustate->A = RD_REG(6); cpustate->zf = (cpustate->A==0); }
383static void ld_a_r7(alpha8201_state *cpustate)   { cpustate->A = RD_REG(7); cpustate->zf = (cpustate->A==0); }
383   state_add( ALPHA8201_PC, "PC", m_pc.w.l ).mask(0x3ff).formatstr("%03X");
384   state_add( ALPHA8201_SP, "SP", m_sp ).callimport().callexport().formatstr("%02X");
385   state_add( ALPHA8201_RB, "RB", m_regPtr ).mask(0x7);
386   state_add( ALPHA8201_MB, "MB", m_mb ).mask(0x3);
387   state_add( ALPHA8201_CF, "CF", m_cf ).mask(0x1);
388   state_add( ALPHA8201_ZF, "ZF", m_zf ).mask(0x1);
389   state_add( ALPHA8201_IX0, "IX0", m_ix0.b.l );
390   state_add( ALPHA8201_IX1, "IX1", m_ix1.b.l );
391   state_add( ALPHA8201_IX2, "IX2", m_ix2.b.l );
392   state_add( ALPHA8201_LP0, "LP0", m_lp0 );
393   state_add( ALPHA8201_LP1, "LP1", m_lp1 );
394   state_add( ALPHA8201_LP2, "LP2", m_lp2 );
395   state_add( ALPHA8201_A, "A", m_A );
396   state_add( ALPHA8201_B, "B", m_B );
397   state_add( ALPHA8201_R0, "R0", m_R[0] ).callimport().callexport().formatstr("%02X");
398   state_add( ALPHA8201_R1, "R1", m_R[1] ).callimport().callexport().formatstr("%02X");
399   state_add( ALPHA8201_R2, "R2", m_R[2] ).callimport().callexport().formatstr("%02X");
400   state_add( ALPHA8201_R3, "R3", m_R[3] ).callimport().callexport().formatstr("%02X");
401   state_add( ALPHA8201_R4, "R4", m_R[4] ).callimport().callexport().formatstr("%02X");
402   state_add( ALPHA8201_R5, "R5", m_R[5] ).callimport().callexport().formatstr("%02X");
403   state_add( ALPHA8201_R6, "R6", m_R[6] ).callimport().callexport().formatstr("%02X");
404   state_add( ALPHA8201_R7, "R7", m_R[7] ).callimport().callexport().formatstr("%02X");
384405
385static void ld_r0_a(alpha8201_state *cpustate)   { WR_REG(0,cpustate->A); }
386static void ld_r1_a(alpha8201_state *cpustate)   { WR_REG(1,cpustate->A); }
387static void ld_r2_a(alpha8201_state *cpustate)   { WR_REG(2,cpustate->A); }
388static void ld_r3_a(alpha8201_state *cpustate)   { WR_REG(3,cpustate->A); }
389static void ld_r4_a(alpha8201_state *cpustate)   { WR_REG(4,cpustate->A); }
390static void ld_r5_a(alpha8201_state *cpustate)   { WR_REG(5,cpustate->A); }
391static void ld_r6_a(alpha8201_state *cpustate)   { WR_REG(6,cpustate->A); }
392static void ld_r7_a(alpha8201_state *cpustate)   { WR_REG(7,cpustate->A); }
406   save_item(NAME(m_RAM));
407   save_item(NAME(m_PREVPC));
408   save_item(NAME(m_pc.w.l));
409   save_item(NAME(m_regPtr));
410   save_item(NAME(m_zf));
411   save_item(NAME(m_cf));
412   save_item(NAME(m_mb));
413   save_item(NAME(m_halt));
414   save_item(NAME(m_ix0.b.l));
415   save_item(NAME(m_ix1.b.l));
416   save_item(NAME(m_ix2.b.l));
417   save_item(NAME(m_lp0));
418   save_item(NAME(m_lp1));
419   save_item(NAME(m_lp2));
420   save_item(NAME(m_A));
421   save_item(NAME(m_B));
422   save_item(NAME(m_retptr));
423   save_item(NAME(m_savec));
424   save_item(NAME(m_savez));
393425
394static void add_a_n(alpha8201_state *cpustate)   { M_ADD(cpustate, M_RDMEM_OPCODE(cpustate)); }
426   m_icountptr = &m_icount;
427}
395428
396static void add_a_r0(alpha8201_state *cpustate)  { M_ADD(cpustate, RD_REG(0)); }
397static void add_a_r1(alpha8201_state *cpustate)  { M_ADD(cpustate, RD_REG(1)); }
398static void add_a_r2(alpha8201_state *cpustate)  { M_ADD(cpustate, RD_REG(2)); }
399static void add_a_r3(alpha8201_state *cpustate)  { M_ADD(cpustate, RD_REG(3)); }
400static void add_a_r4(alpha8201_state *cpustate)  { M_ADD(cpustate, RD_REG(4)); }
401static void add_a_r5(alpha8201_state *cpustate)  { M_ADD(cpustate, RD_REG(5)); }
402static void add_a_r6(alpha8201_state *cpustate)  { M_ADD(cpustate, RD_REG(6)); }
403static void add_a_r7(alpha8201_state *cpustate)  { M_ADD(cpustate, RD_REG(7)); }
404429
405static void sub_a_n(alpha8201_state *cpustate)   { M_SUB(cpustate, M_RDMEM_OPCODE(cpustate)); }
430void alpha8201_cpu_device::state_import(const device_state_entry &entry)
431{
432   switch (entry.index())
433   {
434      case ALPHA8201_SP:
435         M_WRMEM(0x001, m_sp);
436         break;
406437
407static void sub_a_r0(alpha8201_state *cpustate)  { M_SUB(cpustate, RD_REG(0)); }
408static void sub_a_r1(alpha8201_state *cpustate)  { M_SUB(cpustate, RD_REG(1)); }
409static void sub_a_r2(alpha8201_state *cpustate)  { M_SUB(cpustate, RD_REG(2)); }
410static void sub_a_r3(alpha8201_state *cpustate)  { M_SUB(cpustate, RD_REG(3)); }
411static void sub_a_r4(alpha8201_state *cpustate)  { M_SUB(cpustate, RD_REG(4)); }
412static void sub_a_r5(alpha8201_state *cpustate)  { M_SUB(cpustate, RD_REG(5)); }
413static void sub_a_r6(alpha8201_state *cpustate)  { M_SUB(cpustate, RD_REG(6)); }
414static void sub_a_r7(alpha8201_state *cpustate)  { M_SUB(cpustate, RD_REG(7)); }
438      case ALPHA8201_R0:
439         WR_REG(0, m_R[0]);
440         break;
415441
416static void and_a_n(alpha8201_state *cpustate)   { M_AND(cpustate, M_RDMEM_OPCODE(cpustate)); }
442      case ALPHA8201_R1:
443         WR_REG(1, m_R[1]);
444         break;
417445
418static void and_a_r0(alpha8201_state *cpustate)  { M_AND(cpustate, RD_REG(0)); }
419static void and_a_r1(alpha8201_state *cpustate)  { M_AND(cpustate, RD_REG(1)); }
420static void and_a_r2(alpha8201_state *cpustate)  { M_AND(cpustate, RD_REG(2)); }
421static void and_a_r3(alpha8201_state *cpustate)  { M_AND(cpustate, RD_REG(3)); }
422static void and_a_r4(alpha8201_state *cpustate)  { M_AND(cpustate, RD_REG(4)); }
423static void and_a_r5(alpha8201_state *cpustate)  { M_AND(cpustate, RD_REG(5)); }
424static void and_a_r6(alpha8201_state *cpustate)  { M_AND(cpustate, RD_REG(6)); }
425static void and_a_r7(alpha8201_state *cpustate)  { M_AND(cpustate, RD_REG(7)); }
446      case ALPHA8201_R2:
447         WR_REG(2, m_R[2]);
448         break;
426449
427static void or_a_n(alpha8201_state *cpustate)    { M_OR(cpustate, M_RDMEM_OPCODE(cpustate)); }
450      case ALPHA8201_R3:
451         WR_REG(3, m_R[3]);
452         break;
428453
429static void or_a_r0(alpha8201_state *cpustate)   { M_OR(cpustate, RD_REG(0)); }
430static void or_a_r1(alpha8201_state *cpustate)   { M_OR(cpustate, RD_REG(1)); }
431static void or_a_r2(alpha8201_state *cpustate)   { M_OR(cpustate, RD_REG(2)); }
432static void or_a_r3(alpha8201_state *cpustate)   { M_OR(cpustate, RD_REG(3)); }
433static void or_a_r4(alpha8201_state *cpustate)   { M_OR(cpustate, RD_REG(4)); }
434static void or_a_r5(alpha8201_state *cpustate)   { M_OR(cpustate, RD_REG(5)); }
435static void or_a_r6(alpha8201_state *cpustate)   { M_OR(cpustate, RD_REG(6)); }
436static void or_a_r7(alpha8201_state *cpustate)   { M_OR(cpustate, RD_REG(7)); }
454      case ALPHA8201_R4:
455         WR_REG(4, m_R[4]);
456         break;
437457
438static void add_ix0_0(alpha8201_state *cpustate)     { }
439static void add_ix0_1(alpha8201_state *cpustate)     { cpustate->IX0 += 1; }
440static void add_ix0_2(alpha8201_state *cpustate)     { cpustate->IX0 += 2; }
441static void add_ix0_3(alpha8201_state *cpustate)     { cpustate->IX0 += 3; }
442static void add_ix0_4(alpha8201_state *cpustate)     { cpustate->IX0 += 4; }
443static void add_ix0_5(alpha8201_state *cpustate)     { cpustate->IX0 += 5; }
444static void add_ix0_6(alpha8201_state *cpustate)     { cpustate->IX0 += 6; }
445static void add_ix0_7(alpha8201_state *cpustate)     { cpustate->IX0 += 7; }
446static void add_ix0_8(alpha8201_state *cpustate)     { cpustate->IX0 += 8; }
447static void add_ix0_9(alpha8201_state *cpustate)     { cpustate->IX0 += 9; }
448static void add_ix0_a(alpha8201_state *cpustate)     { cpustate->IX0 += 10; }
449static void add_ix0_b(alpha8201_state *cpustate)     { cpustate->IX0 += 11; }
450static void add_ix0_c(alpha8201_state *cpustate)     { cpustate->IX0 += 12; }
451static void add_ix0_d(alpha8201_state *cpustate)     { cpustate->IX0 += 13; }
452static void add_ix0_e(alpha8201_state *cpustate)     { cpustate->IX0 += 14; }
453static void add_ix0_f(alpha8201_state *cpustate)     { cpustate->IX0 += 15; }
458      case ALPHA8201_R5:
459         WR_REG(5, m_R[5]);
460         break;
454461
455static void add_ix1_0(alpha8201_state *cpustate)     { }
456static void add_ix1_1(alpha8201_state *cpustate)     { cpustate->IX1 += 1; }
457static void add_ix1_2(alpha8201_state *cpustate)     { cpustate->IX1 += 2; }
458static void add_ix1_3(alpha8201_state *cpustate)     { cpustate->IX1 += 3; }
459static void add_ix1_4(alpha8201_state *cpustate)     { cpustate->IX1 += 4; }
460static void add_ix1_5(alpha8201_state *cpustate)     { cpustate->IX1 += 5; }
461static void add_ix1_6(alpha8201_state *cpustate)     { cpustate->IX1 += 6; }
462static void add_ix1_7(alpha8201_state *cpustate)     { cpustate->IX1 += 7; }
463static void add_ix1_8(alpha8201_state *cpustate)     { cpustate->IX1 += 8; }
464static void add_ix1_9(alpha8201_state *cpustate)     { cpustate->IX1 += 9; }
465static void add_ix1_a(alpha8201_state *cpustate)     { cpustate->IX1 += 10; }
466static void add_ix1_b(alpha8201_state *cpustate)     { cpustate->IX1 += 11; }
467static void add_ix1_c(alpha8201_state *cpustate)     { cpustate->IX1 += 12; }
468static void add_ix1_d(alpha8201_state *cpustate)     { cpustate->IX1 += 13; }
469static void add_ix1_e(alpha8201_state *cpustate)     { cpustate->IX1 += 14; }
470static void add_ix1_f(alpha8201_state *cpustate)     { cpustate->IX1 += 15; }
462      case ALPHA8201_R6:
463         WR_REG(6, m_R[6]);
464         break;
471465
472static void add_ix2_0(alpha8201_state *cpustate)     { }
473static void add_ix2_1(alpha8201_state *cpustate)     { cpustate->IX2 += 1; }
474static void add_ix2_2(alpha8201_state *cpustate)     { cpustate->IX2 += 2; }
475static void add_ix2_3(alpha8201_state *cpustate)     { cpustate->IX2 += 3; }
476static void add_ix2_4(alpha8201_state *cpustate)     { cpustate->IX2 += 4; }
477static void add_ix2_5(alpha8201_state *cpustate)     { cpustate->IX2 += 5; }
478static void add_ix2_6(alpha8201_state *cpustate)     { cpustate->IX2 += 6; }
479static void add_ix2_7(alpha8201_state *cpustate)     { cpustate->IX2 += 7; }
480static void add_ix2_8(alpha8201_state *cpustate)     { cpustate->IX2 += 8; }
481static void add_ix2_9(alpha8201_state *cpustate)     { cpustate->IX2 += 9; }
482static void add_ix2_a(alpha8201_state *cpustate)     { cpustate->IX2 += 10; }
483static void add_ix2_b(alpha8201_state *cpustate)     { cpustate->IX2 += 11; }
484static void add_ix2_c(alpha8201_state *cpustate)     { cpustate->IX2 += 12; }
485static void add_ix2_d(alpha8201_state *cpustate)     { cpustate->IX2 += 13; }
486static void add_ix2_e(alpha8201_state *cpustate)     { cpustate->IX2 += 14; }
487static void add_ix2_f(alpha8201_state *cpustate)     { cpustate->IX2 += 15; }
488
489static void ld_base_0(alpha8201_state *cpustate)     { cpustate->regPtr = 0; }
490static void ld_base_1(alpha8201_state *cpustate)     { cpustate->regPtr = 1; }
491static void ld_base_2(alpha8201_state *cpustate)     { cpustate->regPtr = 2; }
492static void ld_base_3(alpha8201_state *cpustate)     { cpustate->regPtr = 3; }
493static void ld_base_4(alpha8201_state *cpustate)     { cpustate->regPtr = 4; }
494static void ld_base_5(alpha8201_state *cpustate)     { cpustate->regPtr = 5; }
495static void ld_base_6(alpha8201_state *cpustate)     { cpustate->regPtr = 6; }
496static void ld_base_7(alpha8201_state *cpustate)     { cpustate->regPtr = 7; }
497
498static void ld_bank_0(alpha8201_state *cpustate)     { cpustate->mb = 0; }
499static void ld_bank_1(alpha8201_state *cpustate)     { cpustate->mb = 1; }
500static void ld_bank_2(alpha8201_state *cpustate)     { cpustate->mb = 2; }
501static void ld_bank_3(alpha8201_state *cpustate)     { cpustate->mb = 3; }
502
503static void stop(alpha8201_state *cpustate)
504{
505   UINT8 pcptr = M_RDMEM(0x001) & 0x1f;
506   M_WRMEM(pcptr,(M_RDMEM(pcptr)&0xf)+0x08); /* mark entry point ODD to HALT */
507   cpustate->mb |= 0x08;        /* mark internal HALT state */
466      case ALPHA8201_R7:
467         WR_REG(7, m_R[7]);
468         break;
469   }
508470}
509471
510static void ld_ix0_n(alpha8201_state *cpustate)  { cpustate->IX0 = M_RDMEM_OPCODE(cpustate); }
511static void ld_ix1_n(alpha8201_state *cpustate)  { cpustate->IX1 = M_RDMEM_OPCODE(cpustate); }
512static void ld_ix2_n(alpha8201_state *cpustate)  { cpustate->IX2 = M_RDMEM_OPCODE(cpustate); }
513static void ld_lp0_n(alpha8201_state *cpustate)  { cpustate->LP0 = M_RDMEM_OPCODE(cpustate); }
514static void ld_lp1_n(alpha8201_state *cpustate)  { cpustate->LP1 = M_RDMEM_OPCODE(cpustate); }
515static void ld_lp2_n(alpha8201_state *cpustate)  { cpustate->LP2 = M_RDMEM_OPCODE(cpustate); }
516static void ld_b_n(alpha8201_state *cpustate)    { cpustate->B = M_RDMEM_OPCODE(cpustate); }
517472
518static void djnz_lp0(alpha8201_state *cpustate) { UINT8 i=M_RDMEM_OPCODE(cpustate); cpustate->LP0--; if (cpustate->LP0 != 0) M_JMP(cpustate, i); }
519static void djnz_lp1(alpha8201_state *cpustate) { UINT8 i=M_RDMEM_OPCODE(cpustate); cpustate->LP1--; if (cpustate->LP1 != 0) M_JMP(cpustate, i); }
520static void djnz_lp2(alpha8201_state *cpustate) { UINT8 i=M_RDMEM_OPCODE(cpustate); cpustate->LP2--; if (cpustate->LP2 != 0) M_JMP(cpustate, i); }
521static void jnz(alpha8201_state *cpustate)  { UINT8 i=M_RDMEM_OPCODE(cpustate); if (!cpustate->zf) M_JMP(cpustate, i); }
522static void jnc(alpha8201_state *cpustate)  { UINT8 i=M_RDMEM_OPCODE(cpustate); if (!cpustate->cf) M_JMP(cpustate, i);}
523static void jz(alpha8201_state *cpustate)   { UINT8 i=M_RDMEM_OPCODE(cpustate); if ( cpustate->zf) M_JMP(cpustate, i); }
524static void jc(alpha8201_state *cpustate)   { UINT8 i=M_RDMEM_OPCODE(cpustate); if ( cpustate->cf) M_JMP(cpustate, i);}
525static void jmp(alpha8201_state *cpustate)  { M_JMP(cpustate,  M_RDMEM_OPCODE(cpustate) ); }
526
527static const s_opcode opcode_8201[256]=
473void alpha8201_cpu_device::state_export(const device_state_entry &entry)
528474{
529   {C1, nop        },{C1,rora      },{C1, rola      },{C1,inc_b     },{C1,dec_b     },{C1, inc_a    },{C1, dec_a    },{C1, cpl      },
530   {C2,ld_a_ix0_0  },{C2,ld_a_ix0_1},{C2, ld_a_ix0_2},{C2,ld_a_ix0_3},{C2,ld_a_ix0_4},{C2,ld_a_ix0_5},{C2,ld_a_ix0_6},{C2,ld_a_ix0_7},
531   {C2,ld_a_ix1_0  },{C2,ld_a_ix1_1},{C2, ld_a_ix1_2},{C2,ld_a_ix1_3},{C2,ld_a_ix1_4},{C2,ld_a_ix1_5},{C2,ld_a_ix1_6},{C2,ld_a_ix1_7},
532   {C2,ld_ix2_0_a  },{C2,ld_ix2_1_a},{C2, ld_ix2_2_a},{C2,ld_ix2_3_a},{C2,ld_ix2_4_a},{C2,ld_ix2_5_a},{C2,ld_ix2_6_a},{C2,ld_ix2_7_a},
533/* 20 */
534   {C2,ld_ix0_0_b  },{C2,ld_ix0_1_b},{C2, ld_ix0_2_b},{C2,ld_ix0_3_b},{C2,ld_ix0_4_b},{C2,ld_ix0_5_b},{C2,ld_ix0_6_b},{C2,ld_ix0_7_b},
535   {C2,undefined   },{C2,undefined },{C2, undefined },{C2,undefined },{C2,undefined },{C2,undefined },{C2,undefined },{C2,undefined },
536   {C2,undefined   },{C2,undefined },{C2, undefined },{C2,undefined },{C2,undefined },{C2,undefined },{C2,undefined },{C2,undefined },
537   {C2,bit_r0_0    },{C2,bit_r0_1  },{C2, bit_r0_2 },{C2, bit_r0_3 },{C2, bit_r0_4 },{C2, bit_r0_5 },{C2, bit_r0_6 },{C2, bit_r0_7 },
538/* 40 : 8201 */
539   {C2, ld_a_r0    },{C2, ld_r0_a  },{C2, ld_a_r1  },{C2, ld_r1_a  },{C2, ld_a_r2  },{C2, ld_r2_a  },{C2, ld_a_r3  },{C2, ld_r3_a  },
540   {C2, ld_a_r4    },{C2, ld_r4_a  },{C2, ld_a_r5  },{C2, ld_r5_a  },{C2, ld_a_r6  },{C2, ld_r6_a  },{C2, ld_a_r7  },{C2, ld_r7_a  },
541   {C1, add_a_r0   },{C1, sub_a_r0 },{C1, add_a_r1 },{C1, sub_a_r1 },{C1, add_a_r2 },{C1, sub_a_r2 },{C1, add_a_r3 },{C1, sub_a_r3 },
542   {C1, add_a_r4   },{C1, sub_a_r4 },{C1, add_a_r5 },{C1, sub_a_r5 },{C1, add_a_r6 },{C1, sub_a_r6 },{C1, add_a_r7 },{C1, sub_a_r7 },
543   {C1, and_a_r0   },{C1, or_a_r0  },{C1, and_a_r1 },{C1, or_a_r1  },{C1, and_a_r2 },{C1, or_a_r2  },{C1, and_a_r3 },{C1, or_a_r3  },
544   {C1, and_a_r4   },{C1, or_a_r4  },{C1, and_a_r5 },{C1, or_a_r5  },{C1, and_a_r6 },{C1, or_a_r6  },{C1, and_a_r7 },{C1, or_a_r7  },
545   {C1, add_ix0_0  },{C1, add_ix0_1},{C1, add_ix0_2},{C1, add_ix0_3},{C1, add_ix0_4},{C1, add_ix0_5},{C1, add_ix0_6},{C1, add_ix0_7},
546   {C1, add_ix0_8  },{C1, add_ix0_9},{C1, add_ix0_a},{C1, add_ix0_b},{C1, add_ix0_c},{C1, add_ix0_d},{C1, add_ix0_e},{C1, add_ix0_f},
547/* 80 : 8201 */
548   {C1, add_ix1_0  },{C1, add_ix1_1},{C1, add_ix1_2},{C1, add_ix1_3},{C1, add_ix1_4},{C1, add_ix1_5},{C1, add_ix1_6},{C1, add_ix1_7},
549   {C1, add_ix1_8  },{C1, add_ix1_9},{C1, add_ix1_a},{C1, add_ix1_b},{C1, add_ix1_c},{C1, add_ix1_d},{C1, add_ix1_e},{C1, add_ix1_f},
550   {C1, add_ix2_0  },{C1, add_ix2_1},{C1, add_ix2_2},{C1, add_ix2_3},{C1, add_ix2_4},{C1, add_ix2_5},{C1, add_ix2_6},{C1, add_ix2_7},
551   {C1, add_ix2_8  },{C1, add_ix2_9},{C1, add_ix2_a},{C1, add_ix2_b},{C1, add_ix2_c},{C1, add_ix2_d},{C1, add_ix2_e},{C1, add_ix2_f},
552   {C1, ld_base_0  },{C1, ld_base_1},{C1, ld_base_2},{C1, ld_base_3},{C1, ld_base_4},{C1, ld_base_5},{C1, ld_base_6},{C1, ld_base_7},
553   {C1, undefined  },{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined},
554   {C1, ld_bank_0  },{C1, ld_bank_1},{C1, ld_bank_2},{C1, ld_bank_3},{C2, stop     },{C1, undefined},{C1, undefined},{C1, undefined},
555   {C1, undefined  },{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined},
556/* c0 : 8201 */
557   {C2, ld_ix0_n   },{C2, ld_ix1_n },{C2, ld_ix2_n },{C2, ld_a_n   },{C2, ld_lp0_n },{C2, ld_lp1_n },{C2, ld_lp2_n },{C2, ld_b_n   },
558   {C2, add_a_n    },{C2, sub_a_n  },{C2, and_a_n  },{C2, or_a_n   },{C2, djnz_lp0 },{C2, djnz_lp1 },{C2, djnz_lp2 },{C2, jnz      },
559   {C2, jnc            },{C2, jz       },{C2, jmp      },{C2,undefined2},{C2,undefined2},{C2,undefined2},{C2,undefined2},{C2, undefined2},
560   {C2, undefined2 },{C2,undefined2},{C2,undefined2},{C2,undefined2},{C2,undefined2},{C2,undefined2},{C2,undefined2},{C2, undefined2},
561/* E0 : 8201*/
562   {C1, undefined  },{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined},
563   {C1, undefined  },{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined},
564   {C1, undefined  },{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined},
565   {C1, undefined  },{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined }
566};
475   switch (entry.index())
476   {
477      case ALPHA8201_SP:
478         m_sp = M_RDMEM(0x001);
479         break;
567480
481      case ALPHA8201_R0:
482         m_R[0] = RD_REG(0);
483         break;
568484
569/* ALPHA 8301 : added instruction */
570static void exg_a_ix0(alpha8201_state *cpustate)  { UINT8 t=cpustate->A; cpustate->A = cpustate->IX0; cpustate->IX0 = t; }
571static void exg_a_ix1(alpha8201_state *cpustate)  { UINT8 t=cpustate->A; cpustate->A = cpustate->IX1; cpustate->IX1 = t; }
572static void exg_a_ix2(alpha8201_state *cpustate)  { UINT8 t=cpustate->A; cpustate->A = cpustate->IX2; cpustate->IX2 = t; }
573static void exg_a_lp0(alpha8201_state *cpustate)  { UINT8 t=cpustate->A; cpustate->A = cpustate->LP0; cpustate->LP0 = t; }
574static void exg_a_lp1(alpha8201_state *cpustate)  { UINT8 t=cpustate->A; cpustate->A = cpustate->LP1; cpustate->LP1 = t; }
575static void exg_a_lp2(alpha8201_state *cpustate)  { UINT8 t=cpustate->A; cpustate->A = cpustate->LP2; cpustate->LP2 = t; }
576static void exg_a_b(alpha8201_state *cpustate)    { UINT8 t=cpustate->A; cpustate->A = cpustate->B; cpustate->B = t; }
577static void exg_a_rb(alpha8201_state *cpustate)   { UINT8 t=cpustate->A; cpustate->A = cpustate->regPtr; cpustate->regPtr = t; }
485      case ALPHA8201_R1:
486         m_R[1] = RD_REG(1);
487         break;
578488
579static void ld_ix0_a(alpha8201_state *cpustate)    { cpustate->IX0 = cpustate->A; }
580static void ld_ix1_a(alpha8201_state *cpustate)    { cpustate->IX1 = cpustate->A; }
581static void ld_ix2_a(alpha8201_state *cpustate)    { cpustate->IX2 = cpustate->A; }
582static void ld_lp0_a(alpha8201_state *cpustate)    { cpustate->LP0 = cpustate->A; }
583static void ld_lp1_a(alpha8201_state *cpustate)    { cpustate->LP1 = cpustate->A; }
584static void ld_lp2_a(alpha8201_state *cpustate)    { cpustate->LP2 = cpustate->A; }
585static void ld_b_a(alpha8201_state *cpustate)      { cpustate->B = cpustate->A; }
586static void ld_rb_a(alpha8201_state *cpustate)     { cpustate->regPtr = cpustate->A; }
489      case ALPHA8201_R2:
490         m_R[2] = RD_REG(2);
491         break;
587492
588static void exg_ix0_ix1(alpha8201_state *cpustate)  { UINT8 t=cpustate->IX1; cpustate->IX1 = cpustate->IX0; cpustate->IX0 = t; }
589static void exg_ix0_ix2(alpha8201_state *cpustate)  { UINT8 t=cpustate->IX2; cpustate->IX2 = cpustate->IX0; cpustate->IX0 = t; }
493      case ALPHA8201_R3:
494         m_R[3] = RD_REG(3);
495         break;
590496
591static void op_d4(alpha8201_state *cpustate) { cpustate->A = M_RDMEM( ((cpustate->RAM[(7<<3)+7] & 3) << 8) | M_RDMEM_OPCODE(cpustate) ); }
592static void op_d5(alpha8201_state *cpustate) { M_WRMEM( ((cpustate->RAM[(7<<3)+7] & 3) << 8) | M_RDMEM_OPCODE(cpustate), cpustate->A ); }
593static void op_d6(alpha8201_state *cpustate) { cpustate->LP0 = M_RDMEM( ((cpustate->RAM[(7<<3)+7] & 3) << 8) | M_RDMEM_OPCODE(cpustate) ); }
594static void op_d7(alpha8201_state *cpustate) { M_WRMEM( ((cpustate->RAM[(7<<3)+7] & 3) << 8) | M_RDMEM_OPCODE(cpustate), cpustate->LP0 ); }
497      case ALPHA8201_R4:
498         m_R[4] = RD_REG(4);
499         break;
595500
596static void ld_a_abs(alpha8201_state *cpustate) { cpustate->A = M_RDMEM( ((cpustate->mb & 3) << 8) | M_RDMEM_OPCODE(cpustate) ); }
597static void ld_abs_a(alpha8201_state *cpustate) { M_WRMEM( ((cpustate->mb & 3) << 8) | M_RDMEM_OPCODE(cpustate), cpustate->A ); }
501      case ALPHA8201_R5:
502         m_R[5] = RD_REG(5);
503         break;
598504
599static void ld_a_r(alpha8201_state *cpustate) { cpustate->A = cpustate->RAM[(M_RDMEM_OPCODE(cpustate)>>1)&0x3f]; }
600static void ld_r_a(alpha8201_state *cpustate) { cpustate->RAM[(M_RDMEM_OPCODE(cpustate)>>1)&0x3f] = cpustate->A; }
601static void op_rep_ld_ix2_b(alpha8201_state *cpustate) { do { M_WRMEM(cpustate->BIX2, cpustate->RAM[(cpustate->B>>1)&0x3f]); cpustate->IX2++; cpustate->B+=2; cpustate->LP0--; } while (cpustate->LP0 != 0); }
602static void op_rep_ld_b_ix0(alpha8201_state *cpustate) { do { cpustate->RAM[(cpustate->B>>1)&0x3f] = M_RDMEM(cpustate->BIX0); cpustate->IX0++; cpustate->B+=2; cpustate->LP0--; } while (cpustate->LP0 != 0); }
603static void ld_rxb_a(alpha8201_state *cpustate) { cpustate->RAM[(cpustate->B>>1)&0x3f] = cpustate->A; }
604static void ld_a_rxb(alpha8201_state *cpustate) { cpustate->A = cpustate->RAM[(cpustate->B>>1)&0x3f]; }
605static void cmp_a_rxb(alpha8201_state *cpustate) { UINT8 i=cpustate->RAM[(cpustate->B>>1)&0x3f];  cpustate->zf = (cpustate->A==i); cpustate->cf = (cpustate->A>=i); }
606static void xor_a_rxb(alpha8201_state *cpustate) { M_XOR(cpustate, cpustate->RAM[(cpustate->B>>1)&0x3f] ); }
505      case ALPHA8201_R6:
506         m_R[6] = RD_REG(6);
507         break;
607508
608static void add_a_cf(alpha8201_state *cpustate) { if (cpustate->cf) inc_a(cpustate); }
609static void sub_a_cf(alpha8201_state *cpustate) { if (cpustate->cf) dec_a(cpustate); }
610static void tst_a(alpha8201_state *cpustate)     { cpustate->zf = (cpustate->A==0); }
611static void clr_a(alpha8201_state *cpustate)     { cpustate->A = 0; cpustate->zf = (cpustate->A==0); }
612static void cmp_a_n(alpha8201_state *cpustate)  { UINT8 i=M_RDMEM_OPCODE(cpustate);  cpustate->zf = (cpustate->A==i); cpustate->cf = (cpustate->A>=i); }
613static void xor_a_n(alpha8201_state *cpustate)  { M_XOR(cpustate, M_RDMEM_OPCODE(cpustate) ); }
614static void call(alpha8201_state *cpustate) { UINT8 i=M_RDMEM_OPCODE(cpustate); cpustate->retptr.w.l = cpustate->PC; M_JMP(cpustate, i); };
615static void ld_a_ix0_a(alpha8201_state *cpustate) { cpustate->A = M_RDMEM(cpustate->BIX0+cpustate->A); }
616static void ret(alpha8201_state *cpustate) { cpustate->mb = cpustate->retptr.b.h; M_JMP(cpustate,  cpustate->retptr.b.l ); };
617static void save_zc(alpha8201_state *cpustate) { cpustate->savez = cpustate->zf; cpustate->savec = cpustate->cf; };
618static void rest_zc(alpha8201_state *cpustate) { cpustate->zf = cpustate->savez; cpustate->cf = cpustate->savec; };
509      case ALPHA8201_R7:
510         m_R[7] = RD_REG(7);
511         break;
512   }
513}
619514
620static const s_opcode opcode_8301[256]=
621{
622   {C1, nop        },{C1,rora      },{C1, rola      },{C1,inc_b     },{C1,dec_b     },{C1, inc_a    },{C1, dec_a    },{C1, cpl      },
623   {C2,ld_a_ix0_0  },{C2,ld_a_ix0_1},{C2, ld_a_ix0_2},{C2,ld_a_ix0_3},{C2,ld_a_ix0_4},{C2,ld_a_ix0_5},{C2,ld_a_ix0_6},{C2,ld_a_ix0_7},
624   {C2,ld_a_ix1_0  },{C2,ld_a_ix1_1},{C2, ld_a_ix1_2},{C2,ld_a_ix1_3},{C2,ld_a_ix1_4},{C2,ld_a_ix1_5},{C2,ld_a_ix1_6},{C2,ld_a_ix1_7},
625   {C2,ld_ix2_0_a  },{C2,ld_ix2_1_a},{C2, ld_ix2_2_a},{C2,ld_ix2_3_a},{C2,ld_ix2_4_a},{C2,ld_ix2_5_a},{C2,ld_ix2_6_a},{C2,ld_ix2_7_a},
626/* 20 : 8301 */
627   {C2,ld_ix0_0_b  },{C2,ld_ix0_1_b},{C2, ld_ix0_2_b},{C2,ld_ix0_3_b},{C2,ld_ix0_4_b},{C2,ld_ix0_5_b},{C2,ld_ix0_6_b},{C2,ld_ix0_7_b},
628   {C2,undefined   },{C2,undefined },{C2, undefined },{C2,undefined },{C2,undefined },{C2,undefined },{C2,undefined },{C2,undefined },
629   {C2,undefined   },{C2,undefined },{C2, undefined },{C2,undefined },{C2,undefined },{C2,undefined },{C2,undefined },{C2,undefined },
630   {C2,bit_r0_0    },{C2,bit_r0_1  },{C2, bit_r0_2 },{C2, bit_r0_3 },{C2, bit_r0_4 },{C2, bit_r0_5 },{C2, bit_r0_6 },{C2, bit_r0_7 },
631/* 40 : 8301 */
632   {C2, ld_a_r0    },{C2, ld_r0_a  },{C2, ld_a_r1  },{C2, ld_r1_a  },{C2, ld_a_r2  },{C2, ld_r2_a  },{C2, ld_a_r3  },{C2, ld_r3_a  },
633   {C2, ld_a_r4    },{C2, ld_r4_a  },{C2, ld_a_r5  },{C2, ld_r5_a  },{C2, ld_a_r6  },{C2, ld_r6_a  },{C2, ld_a_r7  },{C2, ld_r7_a  },
634   {C1, add_a_r0   },{C1, sub_a_r0 },{C1, add_a_r1 },{C1, sub_a_r1 },{C1, add_a_r2 },{C1, sub_a_r2 },{C1, add_a_r3 },{C1, sub_a_r3 },
635   {C1, add_a_r4   },{C1, sub_a_r4 },{C1, add_a_r5 },{C1, sub_a_r5 },{C1, add_a_r6 },{C1, sub_a_r6 },{C1, add_a_r7 },{C1, sub_a_r7 },
636/* 60 : 8301 */
637   {C1, and_a_r0   },{C1, or_a_r0  },{C1, and_a_r1 },{C1, or_a_r1  },{C1, and_a_r2 },{C1, or_a_r2  },{C1, and_a_r3 },{C1, or_a_r3  },
638   {C1, and_a_r4   },{C1, or_a_r4  },{C1, and_a_r5 },{C1, or_a_r5  },{C1, and_a_r6 },{C1, or_a_r6  },{C1, and_a_r7 },{C1, or_a_r7  },
639   {C1, add_ix0_0  },{C1, add_ix0_1},{C1, add_ix0_2},{C1, add_ix0_3},{C1, add_ix0_4},{C1, add_ix0_5},{C1, add_ix0_6},{C1, add_ix0_7},
640   {C1, add_ix0_8  },{C1, add_ix0_9},{C1, add_ix0_a},{C1, add_ix0_b},{C1, add_ix0_c},{C1, add_ix0_d},{C1, add_ix0_e},{C1, add_ix0_f},
641/* 80 : 8301 */
642   {C1, add_ix1_0  },{C1, add_ix1_1},{C1, add_ix1_2},{C1, add_ix1_3},{C1, add_ix1_4},{C1, add_ix1_5},{C1, add_ix1_6},{C1, add_ix1_7},
643   {C1, add_ix1_8  },{C1, add_ix1_9},{C1, add_ix1_a},{C1, add_ix1_b},{C1, add_ix1_c},{C1, add_ix1_d},{C1, add_ix1_e},{C1, add_ix1_f},
644   {C1, add_ix2_0  },{C1, add_ix2_1},{C1, add_ix2_2},{C1, add_ix2_3},{C1, add_ix2_4},{C1, add_ix2_5},{C1, add_ix2_6},{C1, add_ix2_7},
645   {C1, add_ix2_8  },{C1, add_ix2_9},{C1, add_ix2_a},{C1, add_ix2_b},{C1, add_ix2_c},{C1, add_ix2_d},{C1, add_ix2_e},{C1, add_ix2_f},
646/* A0 : 8301 */
647   {C1, ld_base_0  },{C1, ld_base_1},{C1, ld_base_2},{C1, ld_base_3},{C1, ld_base_4},{C1, ld_base_5},{C1, ld_base_6},{C1, ld_base_7},
648   {C1, undefined  },{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined},
649   {C1, ld_bank_0  },{C1, ld_bank_1},{C1, ld_bank_2},{C1, ld_bank_3},{C2, stop     },{C1, undefined},{C1, undefined},{C1, undefined},
650   {C1, undefined  },{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined},
651/* c0 : 8301 */
652   {C2, ld_ix0_n   },{C2, ld_ix1_n},{C2, ld_ix2_n  },{C2, ld_a_n   },{C2, ld_lp0_n },{C2, ld_lp1_n },{C2, ld_lp2_n },{C2, ld_b_n   },
653   {C2, add_a_n    },{C2, sub_a_n  },{C2, and_a_n  },{C2, or_a_n   },{C2, djnz_lp0 },{C2, djnz_lp1 },{C2, djnz_lp2 },{C2, jnz      },
654   {C2, jnc            },{C2, jz       },{C2, jmp      },{C2,undefined2},{C2, op_d4    },{C2, op_d5    },{C2, op_d6    },{C2, op_d7    },
655   {C2, ld_a_abs  },{C2, ld_abs_a},{C2,cmp_a_n },{C2,xor_a_n   },{C2, ld_a_r   },{C2, ld_r_a   },{C2, jc       },{C2, call},
656/* E0 : 8301 */
657   {C1, exg_a_ix0  },{C1, exg_a_ix1},{C1, exg_a_ix2},{C1, exg_a_lp1},{C1, exg_a_lp2},{C1, exg_a_b  },{C1, exg_a_lp0},{C1, exg_a_rb },
658   {C1, ld_ix0_a   },{C1, ld_ix1_a },{C1, ld_ix2_a },{C1, ld_lp1_a },{C1, ld_lp2_a },{C1, ld_b_a   },{C1, ld_lp0_a },{C1, ld_rb_a  },
659   {C1,exg_ix0_ix1},{C1,exg_ix0_ix2},{C1,op_rep_ld_ix2_b},{C1, op_rep_ld_b_ix0},{C1, save_zc},{C1, rest_zc},{C1, ld_rxb_a },{C1, ld_a_rxb },
660   {C1, cmp_a_rxb },{C1, xor_a_rxb},{C1, add_a_cf },{C1, sub_a_cf },{C1, tst_a    },{C1, clr_a    },{C1, ld_a_ix0_a},{C1, ret     }
661};
662515
663/****************************************************************************
664 * Initialize emulation
665 ****************************************************************************/
666static CPU_INIT( alpha8201 )
516void alpha8201_cpu_device::state_string_export(const device_state_entry &entry, astring &string)
667517{
668   alpha8201_state *cpustate = get_safe_token(device);
669
670   cpustate->device = device;
671   cpustate->program = &device->space(AS_PROGRAM);
672   cpustate->direct = &cpustate->program->direct();
673
674   device->save_item(NAME(cpustate->RAM));
675   device->save_item(NAME(cpustate->PREVPC));
676   device->save_item(NAME(cpustate->PC));
677   device->save_item(NAME(cpustate->regPtr));
678   device->save_item(NAME(cpustate->zf));
679   device->save_item(NAME(cpustate->cf));
680   device->save_item(NAME(cpustate->mb));
681#if HANDLE_HALT_LINE
682   device->save_item(NAME(cpustate->halt));
683#endif
684   device->save_item(NAME(cpustate->IX0));
685   device->save_item(NAME(cpustate->IX1));
686   device->save_item(NAME(cpustate->IX2));
687   device->save_item(NAME(cpustate->LP0));
688   device->save_item(NAME(cpustate->LP1));
689   device->save_item(NAME(cpustate->LP2));
690   device->save_item(NAME(cpustate->A));
691   device->save_item(NAME(cpustate->B));
692   device->save_item(NAME(cpustate->retptr));
693   device->save_item(NAME(cpustate->savec));
694   device->save_item(NAME(cpustate->savez));
518   switch (entry.index())
519   {
520      case STATE_GENFLAGS:
521         string.printf("%c%c", m_cf?'C':'.', m_zf?'Z':'.');
522         break;
523   }
695524}
525
696526/****************************************************************************
697527 * Reset registers to their initial values
698528 ****************************************************************************/
699static CPU_RESET( alpha8201 )
529void alpha8201_cpu_device::device_reset()
700530{
701   alpha8201_state *cpustate = get_safe_token(device);
702   cpustate->PC     = 0;
703   cpustate->regPtr = 0;
704   cpustate->zf     = 0;
705   cpustate->cf     = 0;
706   cpustate->mb   = 0;
707   cpustate->BIX0   = 0;
708   cpustate->BIX1   = 0;
709   cpustate->BIX2   = 0;
710   cpustate->LP0    = 0;
711   cpustate->LP1    = 0;
712   cpustate->LP2    = 0;
713   cpustate->A    = 0;
714   cpustate->B   = 0;
715#if HANDLE_HALT_LINE
716   cpustate->halt = 0;
717#endif
531   m_pc.w.l = 0;
532   m_regPtr = 0;
533   m_zf     = 0;
534   m_cf     = 0;
535   m_mb   = 0;
536   m_ix0.w.l = 0;
537   m_ix1.w.l = 0;
538   m_ix2.w.l = 0;
539   m_lp0  = 0;
540   m_lp1  = 0;
541   m_lp2  = 0;
542   m_A    = 0;
543   m_B   = 0;
544   m_halt = 0;
718545}
719546
720/****************************************************************************
721 * Shut down CPU emulation
722 ****************************************************************************/
723static CPU_EXIT( alpha8201 )
724{
725   /* nothing to do ? */
726}
727547
728548/****************************************************************************
729549 * Execute cycles CPU cycles. Return number of cycles really executed
730550 ****************************************************************************/
731551
732static void alpha8xxx_execute(device_t *device,const s_opcode *op_map)
552void alpha8201_cpu_device::execute_run()
733553{
734   alpha8201_state *cpustate = get_safe_token(device);
735554   unsigned opcode;
736555   UINT8 pcptr;
737556
738#if HANDLE_HALT_LINE
739   if(cpustate->halt)
557   if(m_halt)
740558   {
741      cpustate->icount = 0;
559      m_icount = 0;
742560      return;
743561   }
744#endif
745562
746563   /* setup address bank & fall safe */
747   cpustate->ix0.b.h =
748   cpustate->ix1.b.h =
749   cpustate->ix2.b.h = (cpustate->pc.b.h &= 3);
564   m_ix0.b.h =
565   m_ix1.b.h =
566   m_ix2.b.h = (m_pc.b.h &= 3);
750567
751568   /* reset start hack */
752   if(cpustate->PC<0x20)
753      cpustate->mb |= 0x08;
569   if(m_pc.w.l<0x20)
570      m_mb |= 0x08;
754571
755572   do
756573   {
757      if(cpustate->mb & 0x08)
574      if(m_mb & 0x08)
758575      {
759576         pcptr = M_RDMEM(0x001) & 0x1f; /* pointer of entry point */
760         cpustate->icount -= C1;
577         m_icount -= C1;
761578
762579         /* entry point scan phase */
763580         if( (pcptr&1) == 0)
764581         {
765            /* EVEN , get cpustate->PC low */
766            cpustate->pc.b.l = M_RDMEM(pcptr);
767//mame_printf_debug("alpha8201 load PCL ENTRY=%02X PCL=%02X\n",pcptr, cpustate->pc.b.l);
768            cpustate->icount -= C1;
582            /* EVEN , get PC low */
583            m_pc.b.l = M_RDMEM(pcptr);
584//mame_printf_debug("alpha8201 load PCL ENTRY=%02X PCL=%02X\n",pcptr, m_pc.b.l);
585            m_icount -= C1;
769586            M_WRMEM(0x001,pcptr+1);
770587            continue;
771588         }
772589
773590         /* ODD , check HALT flag */
774         cpustate->mb   = M_RDMEM(pcptr) & (0x08|0x03);
775         cpustate->icount -= C1;
591         m_mb   = M_RDMEM(pcptr) & (0x08|0x03);
592         m_icount -= C1;
776593
777594         /* not entryaddress 000,001 */
778         if(pcptr<2) cpustate->mb |= 0x08;
595         if(pcptr<2) m_mb |= 0x08;
779596
780         if(cpustate->mb & 0x08)
597         if(m_mb & 0x08)
781598         {
782599            /* HALTED current entry point . next one */
783600            pcptr = (pcptr+1)&0x1f;
784601            M_WRMEM(0x001,pcptr);
785            cpustate->icount -= C1;
602            m_icount -= C1;
786603            continue;
787604         }
788605
789606         /* goto run phase */
790         M_JMP(cpustate, cpustate->pc.b.l);
607         M_JMP(m_pc.b.l);
791608
792609#if SHOW_ENTRY_POINT
793logerror("alpha8201 START ENTRY=%02X cpustate->PC=%03X\n",pcptr,cpustate->PC);
794mame_printf_debug("alpha8201 START ENTRY=%02X cpustate->PC=%03X\n",pcptr,cpustate->PC);
610logerror("alpha8201 START ENTRY=%02X PC=%03X\n",pcptr,m_pc.w.l);
611mame_printf_debug("alpha8201 START ENTRY=%02X PC=%03X\n",pcptr,m_pc.w.l);
795612#endif
796613      }
797614
798615      /* run */
799      cpustate->PREVPC = cpustate->PC;
800      debugger_instruction_hook(device, cpustate->PC);
801      opcode =M_RDOP(cpustate->PC);
616      m_PREVPC = m_pc.w.l;
617      debugger_instruction_hook(this, m_pc.w.l);
618      opcode =M_RDOP(m_pc.w.l);
802619#if TRACE_PC
803mame_printf_debug("alpha8201:  cpustate->PC = %03x,  opcode = %02x\n", cpustate->PC, opcode);
620mame_printf_debug("alpha8201:  PC = %03x,  opcode = %02x\n", m_pc.w.l, opcode);
804621#endif
805      cpustate->PCL++;
806      cpustate->inst_cycles = op_map[opcode].cycles;
807      (*(op_map[opcode].function))(cpustate);
808      cpustate->icount -= cpustate->inst_cycles;
809   } while (cpustate->icount>0);
622      m_pc.b.l++;
623      m_inst_cycles = m_opmap[opcode].cycles;
624      (this->*m_opmap[opcode].opcode_func)();
625      m_icount -= m_inst_cycles;
626   } while (m_icount>0);
810627}
811628
812static CPU_EXECUTE( alpha8201 ) { alpha8xxx_execute(device,opcode_8201); }
813629
814static CPU_EXECUTE( ALPHA8301 ) { alpha8xxx_execute(device,opcode_8301); }
815
816630/****************************************************************************
817631 * Set IRQ line state
818632 ****************************************************************************/
819#if HANDLE_HALT_LINE
820static void set_irq_line(alpha8201_state *cpustate, int irqline, int state)
633void alpha8201_cpu_device::execute_set_input(int inputnum, int state)
821634{
822   if(irqline == INPUT_LINE_HALT)
635   if(inputnum == INPUT_LINE_HALT)
823636   {
824      cpustate->halt = (state==ASSERT_LINE) ? 1 : 0;
825/* mame_printf_debug("alpha8201 HALT %d\n",cpustate->halt); */
637      m_halt = (state==ASSERT_LINE) ? 1 : 0;
638/* mame_printf_debug("alpha8201 HALT %d\n",m_halt); */
826639   }
827640}
828#endif
829641
830/**************************************************************************
831 * Generic set_info
832 **************************************************************************/
833642
834static CPU_SET_INFO( alpha8201 )
643offs_t alpha8201_cpu_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options)
835644{
836   alpha8201_state *cpustate = get_safe_token(device);
837   switch (state)
838   {
839#if HANDLE_HALT_LINE
840      case CPUINFO_INT_INPUT_STATE + INPUT_LINE_HALT: set_irq_line(cpustate, INPUT_LINE_HALT, info->i);   break;
841#endif
842      case CPUINFO_INT_PC:
843      case CPUINFO_INT_REGISTER + ALPHA8201_PC:           cpustate->PC = info->i;                     break;
844      case CPUINFO_INT_SP:
845      case CPUINFO_INT_REGISTER + ALPHA8201_SP:           M_WRMEM(0x001,info->i);             break;
846      case CPUINFO_INT_REGISTER + ALPHA8201_RB:           cpustate->regPtr = info->i & 7;             break;
847      case CPUINFO_INT_REGISTER + ALPHA8201_MB:           cpustate->mb = info->i & 0x03;              break;
848#if 0
849      case CPUINFO_INT_REGISTER + ALPHA8201_ZF:           cpustate->zf= info->i & 0x01;               break;
850      case CPUINFO_INT_REGISTER + ALPHA8201_CF:           cpustate->cf= info->i & 0x01;               break;
851#endif
852      case CPUINFO_INT_REGISTER + ALPHA8201_IX0:          cpustate->IX0 = info->i;                        break;
853      case CPUINFO_INT_REGISTER + ALPHA8201_IX1:          cpustate->IX1 = info->i;                        break;
854      case CPUINFO_INT_REGISTER + ALPHA8201_IX2:          cpustate->IX2 = info->i;                        break;
855      case CPUINFO_INT_REGISTER + ALPHA8201_LP0:          cpustate->LP0 = info->i;                        break;
856      case CPUINFO_INT_REGISTER + ALPHA8201_LP1:          cpustate->LP1 = info->i;                        break;
857      case CPUINFO_INT_REGISTER + ALPHA8201_LP2:          cpustate->LP2 = info->i;                        break;
858      case CPUINFO_INT_REGISTER + ALPHA8201_A:            cpustate->A = info->i;                      break;
859      case CPUINFO_INT_REGISTER + ALPHA8201_B:            cpustate->B = info->i;                      break;
860      case CPUINFO_INT_REGISTER + ALPHA8201_R0:           WR_REG(0,info->i);                  break;
861      case CPUINFO_INT_REGISTER + ALPHA8201_R1:           WR_REG(1,info->i);                  break;
862      case CPUINFO_INT_REGISTER + ALPHA8201_R2:           WR_REG(2,info->i);                  break;
863      case CPUINFO_INT_REGISTER + ALPHA8201_R3:           WR_REG(3,info->i);                  break;
864      case CPUINFO_INT_REGISTER + ALPHA8201_R4:           WR_REG(4,info->i);                  break;
865      case CPUINFO_INT_REGISTER + ALPHA8201_R5:           WR_REG(5,info->i);                  break;
866      case CPUINFO_INT_REGISTER + ALPHA8201_R6:           WR_REG(6,info->i);                  break;
867      case CPUINFO_INT_REGISTER + ALPHA8201_R7:           WR_REG(7,info->i);                  break;
868   }
645   extern CPU_DISASSEMBLE( alpha8201 );
646   return CPU_DISASSEMBLE_NAME(alpha8201)(this, buffer, pc, oprom, opram, options);
869647}
870648
871
872
873/**************************************************************************
874 * Generic get_info
875 **************************************************************************/
876
877/* 8201 and 8301 */
878static CPU_GET_INFO( alpha8xxx )
879{
880   alpha8201_state *cpustate = (device != NULL && device->token() != NULL) ? get_safe_token(device) : NULL;
881   switch (state)
882   {
883      /* --- the following bits of info are returned as 64-bit signed integers --- */
884      case CPUINFO_INT_CONTEXT_SIZE:                  info->i = sizeof(alpha8201_state);      break;
885      case CPUINFO_INT_INPUT_LINES:                   info->i = 0;                            break;
886      case CPUINFO_INT_DEFAULT_IRQ_VECTOR:            info->i = 0;                            break;
887      case CPUINFO_INT_ENDIANNESS:                    info->i = ENDIANNESS_LITTLE;                    break;
888      case CPUINFO_INT_CLOCK_MULTIPLIER:              info->i = 1;                            break;
889      case CPUINFO_INT_CLOCK_DIVIDER:                 info->i = 1;                            break;
890      case CPUINFO_INT_MIN_INSTRUCTION_BYTES:         info->i = 1;                            break;
891      case CPUINFO_INT_MAX_INSTRUCTION_BYTES:         info->i = 2;                            break;
892      case CPUINFO_INT_MIN_CYCLES:                    info->i = 1;                            break;
893      case CPUINFO_INT_MAX_CYCLES:                    info->i = 16;                           break;
894
895      case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM:    info->i = 8;                    break;
896      case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 10;                  break;
897      case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = 0;                   break;
898      case CPUINFO_INT_DATABUS_WIDTH + AS_DATA:   info->i = 0;                    break;
899      case CPUINFO_INT_ADDRBUS_WIDTH + AS_DATA:   info->i = 0;                    break;
900      case CPUINFO_INT_ADDRBUS_SHIFT + AS_DATA:   info->i = 0;                    break;
901      case CPUINFO_INT_DATABUS_WIDTH + AS_IO:     info->i = 8;                    break;
902      case CPUINFO_INT_ADDRBUS_WIDTH + AS_IO:     info->i = 6;                    break;
903      case CPUINFO_INT_ADDRBUS_SHIFT + AS_IO:     info->i = 0;                    break;
904#if HANDLE_HALT_LINE
905      case CPUINFO_INT_INPUT_STATE + INPUT_LINE_HALT:     info->i = cpustate->halt ? ASSERT_LINE : CLEAR_LINE; break;
906#endif
907      case CPUINFO_INT_PREVIOUSPC:                        info->i = cpustate->PREVPC;                 break;
908      case CPUINFO_INT_PC:
909      case CPUINFO_INT_REGISTER + ALPHA8201_PC:           info->i = cpustate->PC & 0x3ff;             break;
910      case CPUINFO_INT_SP:
911      case CPUINFO_INT_REGISTER + ALPHA8201_SP:           info->i = M_RDMEM(0x001);           break;
912      case CPUINFO_INT_REGISTER + ALPHA8201_RB:           info->i = cpustate->regPtr;                 break;
913      case CPUINFO_INT_REGISTER + ALPHA8201_MB:           info->i = cpustate->mb;                     break;
914      case CPUINFO_INT_REGISTER + ALPHA8201_ZF:           info->i = cpustate->zf;                     break;
915      case CPUINFO_INT_REGISTER + ALPHA8201_CF:           info->i = cpustate->cf;                     break;
916      case CPUINFO_INT_REGISTER + ALPHA8201_IX0:          info->i = cpustate->IX0;                        break;
917      case CPUINFO_INT_REGISTER + ALPHA8201_IX1:          info->i = cpustate->IX1;                        break;
918      case CPUINFO_INT_REGISTER + ALPHA8201_IX2:          info->i = cpustate->IX2;                        break;
919      case CPUINFO_INT_REGISTER + ALPHA8201_LP0:          info->i = cpustate->LP0;                        break;
920      case CPUINFO_INT_REGISTER + ALPHA8201_LP1:          info->i = cpustate->LP1;                        break;
921      case CPUINFO_INT_REGISTER + ALPHA8201_LP2:          info->i = cpustate->LP2;                        break;
922      case CPUINFO_INT_REGISTER + ALPHA8201_A:            info->i = cpustate->A;                      break;
923      case CPUINFO_INT_REGISTER + ALPHA8201_B:            info->i = cpustate->B;                      break;
924      case CPUINFO_INT_REGISTER + ALPHA8201_R0:           info->i = RD_REG(0);                break;
925      case CPUINFO_INT_REGISTER + ALPHA8201_R1:           info->i = RD_REG(1);                break;
926      case CPUINFO_INT_REGISTER + ALPHA8201_R2:           info->i = RD_REG(2);                break;
927      case CPUINFO_INT_REGISTER + ALPHA8201_R3:           info->i = RD_REG(3);                break;
928      case CPUINFO_INT_REGISTER + ALPHA8201_R4:           info->i = RD_REG(4);                break;
929      case CPUINFO_INT_REGISTER + ALPHA8201_R5:           info->i = RD_REG(5);                break;
930      case CPUINFO_INT_REGISTER + ALPHA8201_R6:           info->i = RD_REG(6);                break;
931      case CPUINFO_INT_REGISTER + ALPHA8201_R7:           info->i = RD_REG(7);                break;
932
933      /* --- the following bits of info are returned as pointers to data or functions --- */
934      case CPUINFO_FCT_SET_INFO:                      info->setinfo = CPU_SET_INFO_NAME(alpha8201);       break;
935      case CPUINFO_FCT_INIT:                          info->init = CPU_INIT_NAME(alpha8201);          break;
936      case CPUINFO_FCT_RESET:                         info->reset = CPU_RESET_NAME(alpha8201);            break;
937      case CPUINFO_FCT_EXIT:                          info->exit = CPU_EXIT_NAME(alpha8201);          break;
938      case CPUINFO_FCT_BURN:                          info->burn = NULL;                      break;
939      case CPUINFO_FCT_DISASSEMBLE:                   info->disassemble = CPU_DISASSEMBLE_NAME(alpha8201);        break;
940      case CPUINFO_PTR_INSTRUCTION_COUNTER:           info->icount = &cpustate->icount;       break;
941
942      /* --- the following bits of info are returned as NULL-terminated strings --- */
943      case CPUINFO_STR_FAMILY:                    strcpy(info->s, "AlphaDenshi MCU");     break;
944      case CPUINFO_STR_VERSION:                   strcpy(info->s, "0.1");                 break;
945      case CPUINFO_STR_SOURCE_FILE:                       strcpy(info->s, __FILE__);              break;
946      case CPUINFO_STR_CREDITS:                   strcpy(info->s, "Copyright Tatsuyuki Satoh"); break;
947      case CPUINFO_STR_FLAGS:                         sprintf(info->s, "%c%c", cpustate->cf?'C':'.',cpustate->zf?'Z':'.'); break;
948      case CPUINFO_STR_REGISTER + ALPHA8201_PC:       sprintf(info->s, "cpustate->PC:%03X", cpustate->PC);        break;
949      case CPUINFO_STR_REGISTER + ALPHA8201_SP:       sprintf(info->s, "SP:%02X", M_RDMEM(0x001) ); break;
950      case CPUINFO_STR_REGISTER + ALPHA8201_RB:       sprintf(info->s, "RB:%X", cpustate->regPtr);        break;
951      case CPUINFO_STR_REGISTER + ALPHA8201_MB:       sprintf(info->s, "MB:%X", cpustate->mb);        break;
952#if 0
953      case CPUINFO_STR_REGISTER + ALPHA8201_ZF:       sprintf(info->s, "cpustate->zf:%X", cpustate->zf);      break;
954      case CPUINFO_STR_REGISTER + ALPHA8201_CF:       sprintf(info->s, "cpustate->cf:%X", cpustate->cf);      break;
955#endif
956      case CPUINFO_STR_REGISTER + ALPHA8201_IX0:      sprintf(info->s, "cpustate->IX0:%02X", cpustate->IX0);      break;
957      case CPUINFO_STR_REGISTER + ALPHA8201_IX1:      sprintf(info->s, "cpustate->IX1:%02X", cpustate->IX1);      break;
958      case CPUINFO_STR_REGISTER + ALPHA8201_IX2:      sprintf(info->s, "cpustate->IX2:%02X", cpustate->IX2);      break;
959      case CPUINFO_STR_REGISTER + ALPHA8201_LP0:      sprintf(info->s, "cpustate->LP0:%02X", cpustate->LP0);      break;
960      case CPUINFO_STR_REGISTER + ALPHA8201_LP1:      sprintf(info->s, "cpustate->LP1:%02X", cpustate->LP1);      break;
961      case CPUINFO_STR_REGISTER + ALPHA8201_LP2:      sprintf(info->s, "cpustate->LP2:%02X", cpustate->LP2);      break;
962      case CPUINFO_STR_REGISTER + ALPHA8201_A:        sprintf(info->s, "A:%02X", cpustate->A);        break;
963      case CPUINFO_STR_REGISTER + ALPHA8201_B:        sprintf(info->s, "B:%02X", cpustate->B);        break;
964      case CPUINFO_STR_REGISTER + ALPHA8201_R0:       sprintf(info->s, "R0:%02X", RD_REG(0));     break;
965      case CPUINFO_STR_REGISTER + ALPHA8201_R1:       sprintf(info->s, "R1:%02X", RD_REG(1));     break;
966      case CPUINFO_STR_REGISTER + ALPHA8201_R2:       sprintf(info->s, "R2:%02X", RD_REG(2));     break;
967      case CPUINFO_STR_REGISTER + ALPHA8201_R3:       sprintf(info->s, "R3:%02X", RD_REG(3));     break;
968      case CPUINFO_STR_REGISTER + ALPHA8201_R4:       sprintf(info->s, "R4:%02X", RD_REG(4));     break;
969      case CPUINFO_STR_REGISTER + ALPHA8201_R5:       sprintf(info->s, "R5:%02X", RD_REG(5));     break;
970      case CPUINFO_STR_REGISTER + ALPHA8201_R6:       sprintf(info->s, "R6:%02X", RD_REG(6));     break;
971      case CPUINFO_STR_REGISTER + ALPHA8201_R7:       sprintf(info->s, "R7:%02X", RD_REG(7));     break;
972   }
973}
974CPU_GET_INFO( alpha8201 )
975{
976   switch (state)
977   {
978   case CPUINFO_STR_NAME:                          strcpy(info->s, "ALPHA-8201");              break;
979   case CPUINFO_FCT_EXECUTE:                       info->execute = CPU_EXECUTE_NAME(alpha8201);            break;
980   default:
981      /* 8201 / 8301 */
982      CPU_GET_INFO_CALL(alpha8xxx);
983   }
984}
985
986CPU_GET_INFO( alpha8301 )
987{
988   switch (state)
989   {
990   case CPUINFO_STR_NAME:                          strcpy(info->s, "ALPHA-8301");              break;
991   case CPUINFO_FCT_EXECUTE:                       info->execute = CPU_EXECUTE_NAME(ALPHA8301);            break;
992   default:
993      /* 8201 / 8301 */
994      CPU_GET_INFO_CALL(alpha8xxx);
995   }
996}
997
998DEFINE_LEGACY_CPU_DEVICE(ALPHA8201, alpha8201);
999DEFINE_LEGACY_CPU_DEVICE(ALPHA8301, alpha8301);

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