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r23802 Wednesday 19th June, 2013 at 18:48:00 UTC by smf
Added vt83c461, which is currently implemented as a 32 bit chip. This allows hooking up to the jaguar driver without any glue, but primal rage 2 does as the io bus it's connected to is only 16 bit. (nw)
[src/emu/machine]idectrl.c idectrl.h machine.mak vt83c461.c* vt83c461.h*
[src/mame/drivers]jaguar.c zn.c
[src/mame/includes]jaguar.h

trunk/src/mame/drivers/zn.c
r23801r23802
2020#include "machine/znsec.h"
2121#include "machine/zndip.h"
2222#include "machine/ataintf.h"
23#include "machine/idectrl.h"
23#include "machine/vt83c461.h"
2424#include "audio/taitosnd.h"
2525#include "sound/2610intf.h"
2626#include "sound/ymz280b.h"
r23801r23802
4646      m_cbaj_fifo1(*this, "cbaj_fifo1"),
4747      m_cbaj_fifo2(*this, "cbaj_fifo2"),
4848      m_mb3773(*this, "mb3773"),
49      m_ide(*this, "ide")
49      m_vt83c461(*this, "ide")
5050   {
5151   }
5252
r23801r23802
8383   DECLARE_WRITE8_MEMBER(coh1002m_bank_w);
8484   DECLARE_READ8_MEMBER(cbaj_sound_main_status_r);
8585   DECLARE_READ8_MEMBER(cbaj_sound_z80_status_r);
86   DECLARE_READ16_MEMBER(vt83c461_16_r);
87   DECLARE_WRITE16_MEMBER(vt83c461_16_w);
88   DECLARE_READ16_MEMBER(vt83c461_32_r);
89   DECLARE_WRITE16_MEMBER(vt83c461_32_w);
8690   DECLARE_DRIVER_INIT(coh1000ta);
8791   DECLARE_DRIVER_INIT(coh1000tb);
8892   DECLARE_DRIVER_INIT(coh1000c);
r23801r23802
116120   size_t m_nbajamex_eeprom_size;
117121   UINT8 *m_nbajamex_eeprom;
118122
123   UINT16 vt83c461_latch;
124
119125   required_device<psxgpu_device> m_gpu;
120126   required_device<znsec_device> m_znsec0;
121127   required_device<znsec_device> m_znsec1;
r23801r23802
126132   optional_device<fifo7200_device> m_cbaj_fifo1;
127133   optional_device<fifo7200_device> m_cbaj_fifo2;
128134   optional_device<mb3773_device> m_mb3773;
129   optional_device<ide_controller_device> m_ide;
135   optional_device<vt83c461_device> m_vt83c461;
130136};
131137
132138inline void ATTR_PRINTF(3,4) zn_state::verboselog( int n_level, const char *s_fmt, ... )
r23801r23802
13431349   n_size <<= 1;
13441350   while( n_size > 0 )
13451351   {
1346      psxwriteword( p_n_psxram, n_address, m_ide->read_cs0(space, 0, 0xffff) );
1352      psxwriteword( p_n_psxram, n_address, m_vt83c461->read_cs0(space, (UINT32) 0, (UINT32) 0xffff) );
13471353      n_address += 2;
13481354      n_size--;
13491355   }
r23801r23802
13541360   logerror("DMA write from %08x for %d bytes\n", n_address, n_size<<2);
13551361}
13561362
1363READ16_MEMBER(zn_state::vt83c461_16_r)
1364{
1365   int shift = (16 * (offset & 1));
1366
1367   if( offset >= 0x30 / 2 && offset < 0x40 / 2 )
1368   {
1369      return m_vt83c461->read_config( space, ( offset / 2 ) & 3, mem_mask << shift ) >> shift;
1370   }
1371   else if( offset >= 0x1f0 / 2 && offset < 0x1f8 / 2 )
1372   {
1373      return m_vt83c461->read_cs0( space, ( offset / 2 ) & 1, (UINT32) mem_mask << shift ) >> shift;
1374   }
1375   else if( offset >= 0x3f0 / 2 && offset < 0x3f8 / 2 )
1376   {
1377      return m_vt83c461->read_cs1( space, ( offset / 2 ) & 1, (UINT32) mem_mask << shift ) >> shift;
1378   }
1379   else
1380   {
1381      logerror( "unhandled 16 bit read %04x %04x\n", offset, mem_mask );
1382      return 0xffff;
1383   }
1384}
1385
1386WRITE16_MEMBER(zn_state::vt83c461_16_w)
1387{
1388   int shift = (16 * (offset & 1));
1389
1390   if( offset >= 0x30 / 2 && offset < 0x40 / 2 )
1391   {
1392      m_vt83c461->write_config( space, ( offset / 2 ) & 3, data << shift, mem_mask << shift );
1393   }
1394   else if( offset >= 0x1f0 / 2 && offset < 0x1f8 / 2 )
1395   {
1396      m_vt83c461->write_cs0( space, ( offset / 2 ) & 1, (UINT32) data << shift, (UINT32) mem_mask << shift );
1397   }
1398   else if( offset >= 0x3f0 / 2 && offset < 0x3f8 / 2 )
1399   {
1400      m_vt83c461->write_cs1( space, ( offset / 2 ) & 1, (UINT32) data << shift, (UINT32) mem_mask << shift );
1401   }
1402   else
1403   {
1404      logerror( "unhandled 16 bit write %04x %04x %04x\n", offset, data, mem_mask );
1405   }
1406}
1407
1408READ16_MEMBER(zn_state::vt83c461_32_r)
1409{
1410   if( offset == 0x1f0/2 )
1411   {
1412      UINT32 data = m_vt83c461->read_cs0(space, 0, 0xffffffff);
1413      vt83c461_latch = data >> 16;
1414      return data & 0xffff;
1415   }
1416   else if( offset == 0x1f2/2 )
1417   {
1418      return vt83c461_latch;
1419   }
1420   else
1421   {
1422      logerror( "unhandled 32 bit read %04x %04x\n", offset, mem_mask );
1423      return 0xffff;
1424   }
1425}
1426
1427WRITE16_MEMBER(zn_state::vt83c461_32_w)
1428{
1429   logerror( "unhandled 32 bit write %04x %04x %04x\n", offset, data, mem_mask );
1430}
1431
13571432static ADDRESS_MAP_START(coh1000w_map, AS_PROGRAM, 32, zn_state)
13581433   AM_RANGE(0x1f000000, 0x1f1fffff) AM_ROM AM_REGION("roms", 0)
13591434   AM_RANGE(0x1f000000, 0x1f000003) AM_WRITENOP
13601435   AM_RANGE(0x1f7e8000, 0x1f7e8003) AM_NOP
1361   // 8/16
1362   AM_RANGE(0x1f7e4030, 0x1f7e403f) AM_DEVREADWRITE8("ide", ide_controller_device, read_via_config, write_via_config, 0xffffffff)
1363   AM_RANGE(0x1f7e41f0, 0x1f7e41f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0, write_cs0, 0xffffffff)
1364   AM_RANGE(0x1f7e43f0, 0x1f7e43f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1, write_cs1, 0xffffffff)
1365   // 32
1366   AM_RANGE(0x1f7f41f0, 0x1f7f41f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0, write_cs0, 0xffffffff)
1367   AM_RANGE(0x1f7f43f0, 0x1f7f43f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1, write_cs1, 0xffffffff)
1368
1436   AM_RANGE(0x1f7e4000, 0x1f7e4fff) AM_READWRITE16(vt83c461_16_r, vt83c461_16_w, 0xffffffff)
1437   AM_RANGE(0x1f7f4000, 0x1f7f4fff) AM_READWRITE16(vt83c461_32_r, vt83c461_32_w, 0xffffffff)
13691438   AM_IMPORT_FROM(zn_map)
13701439ADDRESS_MAP_END
13711440
r23801r23802
13761445   MCFG_RAM_MODIFY("maincpu:ram")
13771446   MCFG_RAM_DEFAULT_SIZE("8M")
13781447
1379   MCFG_IDE_CONTROLLER_ADD("ide", ata_devices, "hdd", NULL, true)
1448   MCFG_VT83C461_ADD("ide", ata_devices, "hdd", NULL, true)
13801449   MCFG_ATA_INTERFACE_IRQ_HANDLER(DEVWRITELINE("maincpu:irq", psxirq_device, intin10))
13811450   MCFG_PSX_DMA_CHANNEL_READ( "maincpu", 5, psx_dma_read_delegate( FUNC( zn_state::atpsx_dma_read ), (zn_state *) owner ) )
13821451   MCFG_PSX_DMA_CHANNEL_WRITE( "maincpu", 5, psx_dma_write_delegate( FUNC( zn_state::atpsx_dma_write ), (zn_state *) owner ) )
trunk/src/mame/drivers/jaguar.c
r23801r23802
334334#include "cpu/m68000/m68000.h"
335335#include "cpu/mips/r3000.h"
336336#include "cpu/jaguar/jaguar.h"
337#include "machine/idectrl.h"
337#include "machine/vt83c461.h"
338338#include "sound/dac.h"
339339#include "includes/jaguar.h"
340340#include "emuopts.h"
r23801r23802
10771077   AM_RANGE(0xf1d000, 0xf1dfff) AM_READWRITE(wave_rom_r16, wave_rom_w16 )
10781078ADDRESS_MAP_END
10791079
1080/// hack for 32 big endian bus talking to 16 bit little endian ide
1081READ32_MEMBER(jaguar_state::vt83c461_r)
1082{
1083   UINT32 data = 0;
10841080
1085   if(offset >= 0x30/4 && offset < 0x40/4)
1086   {
1087      if (ACCESSING_BITS_0_7)
1088         data = m_ide->read_via_config(space, (offset * 4) & 0xf, mem_mask);
1089   }
1090   else if( offset >= 0x1f0/4 && offset < 0x1f8/4 )
1091   {
1092      if (ACCESSING_BITS_0_15)
1093         data |= m_ide->read_cs0(space, (offset * 2) & 7, mem_mask);
1094      if (ACCESSING_BITS_16_31)
1095         data |= m_ide->read_cs0(space, ((offset * 2) & 7) + 1, mem_mask >> 16) << 16;
1096   }
1097   else if( offset >= 0x3f0/4 && offset < 0x3f8/4 )
1098   {
1099      if (ACCESSING_BITS_0_15)
1100         data |= m_ide->read_cs1(space, (offset * 2) & 7, mem_mask);
1101      if (ACCESSING_BITS_16_31)
1102         data |= m_ide->read_cs1(space, ((offset * 2) & 7) + 1, mem_mask >> 16) << 16;
1103   }
11041081
1105   return data;
1106}
1107
1108WRITE32_MEMBER(jaguar_state::vt83c461_w)
1109{
1110   if(offset >= 0x30/4 && offset < 0x40/4)
1111   {
1112      if (ACCESSING_BITS_0_7)
1113         m_ide->write_via_config(space, (offset * 4) & 0xf, data, mem_mask);
1114   }
1115   else if( offset >= 0x1f0/4 && offset < 0x1f8/4 )
1116   {
1117      if (ACCESSING_BITS_0_15)
1118         m_ide->write_cs0(space, (offset * 2) & 7, data, mem_mask);
1119      if (ACCESSING_BITS_16_31)
1120         m_ide->write_cs0(space, ((offset * 2) & 7) + 1, data >> 16, mem_mask >> 16);
1121   }
1122   else if( offset >= 0x3f0/4 && offset < 0x3f8/4 )
1123   {
1124      if (ACCESSING_BITS_0_15)
1125         m_ide->write_cs1(space, (offset * 2) & 7, data, mem_mask);
1126      if (ACCESSING_BITS_16_31)
1127         m_ide->write_cs1(space, ((offset * 2) & 7) + 1, data >> 16, mem_mask >> 16);
1128   }
1129}
1130
1131
1132
11331082/*************************************
11341083 *
11351084 *  Main CPU memory handlers
r23801r23802
11401089   AM_RANGE(0x04000000, 0x047fffff) AM_RAM AM_SHARE("sharedram")
11411090   AM_RANGE(0x04800000, 0x04bfffff) AM_ROMBANK("maingfxbank")
11421091   AM_RANGE(0x04c00000, 0x04dfffff) AM_ROMBANK("mainsndbank")
1143   AM_RANGE(0x04e00000, 0x04e003ff) AM_READWRITE(vt83c461_r, vt83c461_w)
1092   AM_RANGE(0x04e00030, 0x04e0003f) AM_DEVREADWRITE("ide", vt83c461_device, read_config, write_config)
1093   AM_RANGE(0x04e001f0, 0x04e001f7) AM_DEVREADWRITE("ide", vt83c461_device, read_cs0, write_cs0)
1094   AM_RANGE(0x04e003f0, 0x04e003f7) AM_DEVREADWRITE("ide", vt83c461_device, read_cs1, write_cs1)
11441095   AM_RANGE(0x04f00000, 0x04f003ff) AM_READWRITE16(tom_regs_r, tom_regs_w, 0xffffffff)
11451096   AM_RANGE(0x04f00400, 0x04f007ff) AM_RAM AM_SHARE("gpuclut")
11461097   AM_RANGE(0x04f02100, 0x04f021ff) AM_READWRITE(gpuctrl_r, gpuctrl_w)
r23801r23802
11741125   AM_RANGE(0xa40000, 0xa40003) AM_WRITE(eeprom_enable_w)
11751126   AM_RANGE(0xb70000, 0xb70003) AM_READWRITE(misc_control_r, misc_control_w)
11761127   AM_RANGE(0xc00000, 0xdfffff) AM_ROMBANK("mainsndbank")
1177   AM_RANGE(0xe00000, 0xe003ff) AM_READWRITE(vt83c461_r, vt83c461_w)
1128   AM_RANGE(0xe00030, 0xe0003f) AM_DEVREADWRITE("ide", vt83c461_device, read_config, write_config)
1129   AM_RANGE(0xe001f0, 0xe001f7) AM_DEVREADWRITE("ide", vt83c461_device, read_cs0, write_cs0)
1130   AM_RANGE(0xe003f0, 0xe003f7) AM_DEVREADWRITE("ide", vt83c461_device, read_cs1, write_cs1)
11781131   AM_RANGE(0xf00000, 0xf003ff) AM_READWRITE16(tom_regs_r, tom_regs_w, 0xffffffff)
11791132   AM_RANGE(0xf00400, 0xf007ff) AM_RAM AM_SHARE("gpuclut")
11801133   AM_RANGE(0xf02100, 0xf021ff) AM_READWRITE(gpuctrl_r, gpuctrl_w)
r23801r23802
12021155   AM_RANGE(0x000000, 0x7fffff) AM_RAM AM_SHARE("sharedram")
12031156   AM_RANGE(0x800000, 0xbfffff) AM_ROMBANK("gpugfxbank")
12041157   AM_RANGE(0xc00000, 0xdfffff) AM_ROMBANK("dspsndbank")
1205   AM_RANGE(0xe00000, 0xe003ff) AM_READWRITE(vt83c461_r, vt83c461_w)
1158   AM_RANGE(0xe00030, 0xe0003f) AM_DEVREADWRITE("ide", vt83c461_device, read_config, write_config)
1159   AM_RANGE(0xe001f0, 0xe001f7) AM_DEVREADWRITE("ide", vt83c461_device, read_cs0, write_cs0)
1160   AM_RANGE(0xe003f0, 0xe003f7) AM_DEVREADWRITE("ide", vt83c461_device, read_cs1, write_cs1)
12061161   AM_RANGE(0xf00000, 0xf003ff) AM_READWRITE16(tom_regs_r, tom_regs_w, 0xffffffff)
12071162   AM_RANGE(0xf00400, 0xf007ff) AM_RAM AM_SHARE("gpuclut")
12081163   AM_RANGE(0xf02100, 0xf021ff) AM_READWRITE(gpuctrl_r, gpuctrl_w)
r23801r23802
16011556
16021557   MCFG_NVRAM_ADD_1FILL("nvram")
16031558
1604   MCFG_IDE_CONTROLLER_ADD("ide", ata_devices, "hdd", NULL, true)
1559   MCFG_VT83C461_ADD("ide", ata_devices, "hdd", NULL, true)
16051560   MCFG_ATA_INTERFACE_IRQ_HANDLER(WRITELINE(jaguar_state, external_int))
16061561
16071562   /* video hardware */
trunk/src/mame/includes/jaguar.h
r23801r23802
88#include "machine/nvram.h"
99#include "sound/dac.h"
1010#include "machine/eeprom.h"
11#include "machine/idectrl.h"
11#include "machine/vt83c461.h"
1212#include "imagedev/snapquik.h"
1313
1414#ifndef ENABLE_SPEEDUP_HACKS
r23801r23802
211211   DECLARE_WRITE32_MEMBER( blitter_w );
212212   DECLARE_READ16_MEMBER( tom_regs_r );
213213   DECLARE_WRITE16_MEMBER( tom_regs_w );
214   DECLARE_READ32_MEMBER( vt83c461_r );
215   DECLARE_WRITE32_MEMBER( vt83c461_w );
216214   DECLARE_READ32_MEMBER( cojag_gun_input_r );
217215   UINT32 screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
218216
r23801r23802
325323   void jaguar_nvram_load();
326324   void jaguar_nvram_save();
327325   optional_device<eeprom_device> m_eeprom;
328   optional_device<ide_controller_device> m_ide;
326   optional_device<vt83c461_device> m_ide;
329327};
trunk/src/emu/machine/idectrl.c
r23801r23802
2525    CONSTANTS
2626***************************************************************************/
2727
28#define IDE_BANK2_CONFIG_UNK                4
29#define IDE_BANK2_CONFIG_REGISTER           8
30#define IDE_BANK2_CONFIG_DATA               0xc
31
3228const device_type IDE_CONTROLLER = &device_creator<ide_controller_device>;
3329
3430ide_controller_device::ide_controller_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
35   ata_interface_device(mconfig, IDE_CONTROLLER, "IDE Controller", tag, owner, clock),
36   m_config_unknown(0),
37   m_config_register_num(0)
31   ata_interface_device(mconfig, IDE_CONTROLLER, "IDE Controller", tag, owner, clock)
3832{
3933}
4034
4135ide_controller_device::ide_controller_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock) :
42   ata_interface_device(mconfig, type, name, tag, owner, clock),
43   m_config_unknown(0),
44   m_config_register_num(0)
36   ata_interface_device(mconfig, type, name, tag, owner, clock)
4537{
4638}
4739
48//-------------------------------------------------
49//  device_start - device-specific startup
50//-------------------------------------------------
51
52void ide_controller_device::device_start()
53{
54   ata_interface_device::device_start();
55
56   /* register ide states */
57   save_item(NAME(m_config_unknown));
58   save_item(NAME(m_config_register));
59   save_item(NAME(m_config_register_num));
60}
61
62READ8_MEMBER( ide_controller_device::read_via_config )
63{
64   UINT16 result = 0;
65
66   /* logit */
67   LOG(("%s:IDE via config read at %X, mem_mask=%d\n", machine().describe_context(), offset, mem_mask));
68
69   switch(offset)
70   {
71      /* unknown config register */
72      case IDE_BANK2_CONFIG_UNK:
73         result = m_config_unknown;
74         break;
75
76      /* active config register */
77      case IDE_BANK2_CONFIG_REGISTER:
78         result = m_config_register_num;
79         break;
80
81      /* data from active config register */
82      case IDE_BANK2_CONFIG_DATA:
83         if (m_config_register_num < IDE_CONFIG_REGISTERS)
84            result = m_config_register[m_config_register_num];
85         break;
86
87      default:
88         logerror("%s:unknown IDE via config read at %03X, mem_mask=%d\n", machine().describe_context(), offset, mem_mask);
89         break;
90   }
91
92//  printf( "read via config %04x %04x %04x\n", offset, result, mem_mask );
93   return result;
94}
95
9640READ16_MEMBER( ide_controller_device::read_cs0 )
9741{
98   if (mem_mask == 0xffff && offset == 1 ) offset = 0; // hack for 32 bit read of data register
9942   if (mem_mask == 0xff00)
10043   {
10144      return ata_interface_device::read_cs0(space, (offset * 2) + 1, 0xff) << 8;
r23801r23802
11861   }
11962}
12063
121WRITE8_MEMBER( ide_controller_device::write_via_config )
122{
123//  printf( "write via config %04x %04x %04x\n", offset, data, mem_mask );
124
125   /* logit */
126   LOG(("%s:IDE via config write to %X = %08X, mem_mask=%d\n", machine().describe_context(), offset, data, mem_mask));
127
128   switch (offset)
129   {
130      /* unknown config register */
131      case IDE_BANK2_CONFIG_UNK:
132         m_config_unknown = data;
133         break;
134
135      /* active config register */
136      case IDE_BANK2_CONFIG_REGISTER:
137         m_config_register_num = data;
138         break;
139
140      /* data from active config register */
141      case IDE_BANK2_CONFIG_DATA:
142         if (m_config_register_num < IDE_CONFIG_REGISTERS)
143            m_config_register[m_config_register_num] = data;
144         break;
145   }
146}
147
14864WRITE16_MEMBER( ide_controller_device::write_cs0 )
14965{
150   if (mem_mask == 0xffff && offset == 1 ) offset = 0; // hack for 32 bit write to data register
15166   if (mem_mask == 0xff00)
15267   {
15368      return ata_interface_device::write_cs0(space, (offset * 2) + 1, data >> 8, 0xff);
trunk/src/emu/machine/idectrl.h
r23801r23802
2626   MCFG_ATA_SLOT_ADD(_tag ":1", _slotintf, _slave, _fixed) \
2727   MCFG_DEVICE_MODIFY(_tag)
2828
29#define IDE_CONFIG_REGISTERS                0x10
30
3129class ide_controller_device : public ata_interface_device
3230{
3331public:
3432   ide_controller_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
3533   ide_controller_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock);
3634
37   DECLARE_READ8_MEMBER(read_via_config);
38   DECLARE_WRITE8_MEMBER(write_via_config);
3935   virtual DECLARE_READ16_MEMBER(read_cs0);
4036   virtual DECLARE_READ16_MEMBER(read_cs1);
4137   virtual DECLARE_WRITE16_MEMBER(write_cs0);
4238   virtual DECLARE_WRITE16_MEMBER(write_cs1);
43
44protected:
45   virtual void device_start();
46
47private:
48   UINT8           m_config_unknown;
49   UINT8           m_config_register[IDE_CONFIG_REGISTERS];
50   UINT8           m_config_register_num;
5139};
5240
5341extern const device_type IDE_CONTROLLER;
trunk/src/emu/machine/vt83c461.c
r0r23802
1#include "vt83c461.h"
2
3/***************************************************************************
4    DEBUGGING
5***************************************************************************/
6
7#define VERBOSE                     0
8
9#define LOG(x)  do { if (VERBOSE) logerror x; } while (0)
10
11
12#define VT83C461_CONFIG_UNK                1
13#define VT83C461_CONFIG_REGISTER           2
14#define VT83C461_CONFIG_DATA               3
15
16
17const device_type VT83C461 = &device_creator<vt83c461_device>;
18
19vt83c461_device::vt83c461_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
20   ide_controller_device(mconfig, VT83C461, "VIA VT83C461", tag, owner, clock),
21   m_config_unknown(0),
22   m_config_register_num(0)
23{
24}
25
26//-------------------------------------------------
27//  device_start - device-specific startup
28//-------------------------------------------------
29
30void vt83c461_device::device_start()
31{
32   ide_controller_device::device_start();
33
34   /* register ide states */
35   save_item(NAME(m_config_unknown));
36   save_item(NAME(m_config_register));
37   save_item(NAME(m_config_register_num));
38}
39
40READ32_MEMBER( vt83c461_device::read_config )
41{
42   UINT32 result = 0;
43
44   /* logit */
45   LOG(("%s:IDE via config read at %X, mem_mask=%d\n", machine().describe_context(), offset, mem_mask));
46
47   switch(offset)
48   {
49   /* unknown config register */
50   case VT83C461_CONFIG_UNK:
51      result = m_config_unknown;
52      break;
53
54   /* active config register */
55   case VT83C461_CONFIG_REGISTER:
56      result = m_config_register_num;
57      break;
58
59   /* data from active config register */
60   case VT83C461_CONFIG_DATA:
61      if (m_config_register_num < IDE_CONFIG_REGISTERS)
62         result = m_config_register[m_config_register_num];
63      break;
64
65   default:
66      logerror("%s:unknown IDE via config read at %03X, mem_mask=%d\n", machine().describe_context(), offset, mem_mask);
67      break;
68   }
69
70//  printf( "vt83c461 read config %04x %08x %04x\n", offset, result, mem_mask );
71   return result;
72}
73
74WRITE32_MEMBER( vt83c461_device::write_config )
75{
76//  printf( "vt83c461 write config %04x %08x %04x\n", offset, data, mem_mask );
77
78   /* logit */
79   LOG(("%s:IDE via config write to %X = %08X, mem_mask=%d\n", machine().describe_context(), offset, data, mem_mask));
80
81   switch (offset)
82   {
83   /* unknown config register */
84   case VT83C461_CONFIG_UNK:
85      m_config_unknown = data;
86      break;
87
88   /* active config register */
89   case VT83C461_CONFIG_REGISTER:
90      m_config_register_num = data;
91      break;
92
93   /* data from active config register */
94   case VT83C461_CONFIG_DATA:
95      if (m_config_register_num < IDE_CONFIG_REGISTERS)
96         m_config_register[m_config_register_num] = data;
97      break;
98
99   default:
100      logerror("%s:unknown IDE via config write at %03X = %08x, mem_mask=%d\n", machine().describe_context(), offset, data, mem_mask);
101      break;
102   }
103}
104
105READ32_MEMBER(vt83c461_device::read_cs0)
106{
107   UINT32 data = 0;
108
109   if (ACCESSING_BITS_0_15)
110   {
111      data = ide_controller_device::read_cs0(space, (offset * 2), mem_mask);
112
113      if (offset == 0 && ACCESSING_BITS_16_31)
114         data |= ide_controller_device::read_cs0(space, (offset * 2), mem_mask >> 16) << 16;
115   }
116   else if (ACCESSING_BITS_16_31)
117   {
118      data = ide_controller_device::read_cs0(space, (offset * 2) + 1, mem_mask >> 16) << 16;
119   }
120
121//   printf( "vt83c461 read cs0 %08x %08x %08x\n", offset, data, mem_mask );
122
123   return data;
124}
125
126READ32_MEMBER(vt83c461_device::read_cs1)
127{
128   UINT32 data = 0;
129
130   if (ACCESSING_BITS_0_15)
131   {
132      data = ide_controller_device::read_cs1(space, (offset * 2), mem_mask);
133   }
134   else if (ACCESSING_BITS_16_23)
135   {
136      data = ide_controller_device::read_cs1(space, (offset * 2) + 1, mem_mask >> 16) << 16;
137   }
138
139//   printf( "vt83c461 read cs1 %08x %08x %08x\n", offset, data, mem_mask );
140
141   return data;
142}
143
144WRITE32_MEMBER(vt83c461_device::write_cs0)
145{
146//   printf( "vt83c461 write cs0 %08x %08x %08x\n", offset, data, mem_mask );
147
148   if (ACCESSING_BITS_0_15)
149   {
150      ide_controller_device::write_cs0(space, (offset * 2), data, mem_mask);
151
152      if (offset == 0 && ACCESSING_BITS_16_31)
153         ata_interface_device::write_cs0(space, (offset * 2), data >> 16, mem_mask >> 16);
154   }
155   else if (ACCESSING_BITS_16_31)
156   {
157      ide_controller_device::write_cs0(space, (offset * 2) + 1, data >> 16, mem_mask >> 16);
158   }
159}
160
161WRITE32_MEMBER(vt83c461_device::write_cs1)
162{
163//   printf( "vt83c461 write cs1 %08x %08x %08x\n", offset, data, mem_mask );
164
165   if (ACCESSING_BITS_0_7)
166   {
167      ide_controller_device::write_cs1(space, (offset * 2), data, mem_mask);
168   }
169   else if (ACCESSING_BITS_16_23)
170   {
171      ide_controller_device::write_cs1(space, (offset * 2) + 1, data >> 16, mem_mask >> 16);
172   }
173}
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trunk/src/emu/machine/vt83c461.h
r0r23802
1/***************************************************************************
2
3    vt83c461.h
4
5    VIA VT83C461 (IDE Hard Drive controller).
6
7    Copyright Nicola Salmoria and the MAME Team.
8    Visit http://mamedev.org for licensing and usage restrictions.
9
10***************************************************************************/
11
12#pragma once
13
14#ifndef __VT83C461_H__
15#define __VT83C461_H__
16
17#include "idectrl.h"
18
19/***************************************************************************
20    DEVICE CONFIGURATION MACROS
21***************************************************************************/
22
23#define MCFG_VT83C461_ADD(_tag, _slotintf, _master, _slave, _fixed) \
24   MCFG_DEVICE_ADD(_tag, VT83C461, 0) \
25   MCFG_ATA_SLOT_ADD(_tag ":0", _slotintf, _master, _fixed) \
26   MCFG_ATA_SLOT_ADD(_tag ":1", _slotintf, _slave, _fixed) \
27   MCFG_DEVICE_MODIFY(_tag)
28
29#define IDE_CONFIG_REGISTERS                0x10
30
31class vt83c461_device : public ide_controller_device
32{
33public:
34   vt83c461_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
35
36   DECLARE_READ32_MEMBER(read_config);
37   DECLARE_WRITE32_MEMBER(write_config);
38
39   virtual DECLARE_READ32_MEMBER(read_cs0);
40   virtual DECLARE_READ32_MEMBER(read_cs1);
41   virtual DECLARE_WRITE32_MEMBER(write_cs0);
42   virtual DECLARE_WRITE32_MEMBER(write_cs1);
43
44protected:
45   virtual void device_start();
46
47private:
48   using ide_controller_device::read_cs0;
49   using ide_controller_device::read_cs1;
50   using ide_controller_device::write_cs0;
51   using ide_controller_device::write_cs1;
52
53   UINT8           m_config_unknown;
54   UINT8           m_config_register[IDE_CONFIG_REGISTERS];
55   UINT8           m_config_register_num;
56};
57
58extern const device_type VT83C461;
59
60#endif
Property changes on: trunk/src/emu/machine/vt83c461.h
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trunk/src/emu/machine/machine.mak
r23801r23802
535535MACHINEOBJS += $(MACHINEOBJ)/atadev.o
536536MACHINEOBJS += $(MACHINEOBJ)/idectrl.o
537537MACHINEOBJS += $(MACHINEOBJ)/idehd.o
538MACHINEOBJS += $(MACHINEOBJ)/vt83c461.o
538539endif
539540
540541#-------------------------------------------------

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