trunk/src/mess/machine/ti99/ti32kmem.c
| r23538 | r23539 | |
| 36 | 36 | |
| 37 | 37 | READ8Z_MEMBER(ti_32k_expcard_device::readz) |
| 38 | 38 | { |
| 39 | UINT8 val = 0; |
| 40 | bool access = true; |
| 39 | 41 | switch((offset & 0xe000)>>13) |
| 40 | 42 | { |
| 41 | 43 | case 1: |
| 42 | | *value = m_ram_ptr[offset & 0x1fff]; |
| 44 | val = m_ram_ptr[offset & 0x1fff]; |
| 43 | 45 | break; |
| 44 | 46 | case 5: |
| 45 | | *value = m_ram_ptr[(offset & 0x1fff) | 0x2000]; |
| 47 | val = m_ram_ptr[(offset & 0x1fff) | 0x2000]; |
| 46 | 48 | break; |
| 47 | 49 | case 6: |
| 48 | | *value = m_ram_ptr[(offset & 0x1fff) | 0x4000]; |
| 50 | val = m_ram_ptr[(offset & 0x1fff) | 0x4000]; |
| 49 | 51 | break; |
| 50 | 52 | case 7: |
| 51 | | *value = m_ram_ptr[(offset & 0x1fff) | 0x6000]; |
| 53 | val = m_ram_ptr[(offset & 0x1fff) | 0x6000]; |
| 52 | 54 | break; |
| 53 | 55 | default: |
| 56 | access = false; |
| 54 | 57 | break; |
| 55 | 58 | } |
| 59 | if (access) |
| 60 | { |
| 61 | if ((offset&1)!=1) *value = ~val; |
| 62 | else *value = val; |
| 63 | } |
| 56 | 64 | } |
| 57 | 65 | |
| 58 | 66 | WRITE8_MEMBER(ti_32k_expcard_device::write) |
| 59 | 67 | { |
| 68 | UINT8 data1 = data; |
| 69 | if ((offset&1)!=1) data1 = ~data; |
| 60 | 70 | switch((offset & 0xe000)>>13) |
| 61 | 71 | { |
| 62 | 72 | case 1: |
| 63 | | m_ram_ptr[offset & 0x1fff] = data; |
| 73 | m_ram_ptr[offset & 0x1fff] = data1; |
| 64 | 74 | break; |
| 65 | 75 | case 5: |
| 66 | | m_ram_ptr[(offset & 0x1fff) | 0x2000] = data; |
| 76 | m_ram_ptr[(offset & 0x1fff) | 0x2000] = data1; |
| 67 | 77 | break; |
| 68 | 78 | case 6: |
| 69 | | m_ram_ptr[(offset & 0x1fff) | 0x4000] = data; |
| 79 | m_ram_ptr[(offset & 0x1fff) | 0x4000] = data1; |
| 70 | 80 | break; |
| 71 | 81 | case 7: |
| 72 | | m_ram_ptr[(offset & 0x1fff) | 0x6000] = data; |
| 82 | m_ram_ptr[(offset & 0x1fff) | 0x6000] = data1; |
| 73 | 83 | break; |
| 74 | 84 | default: |
| 75 | 85 | break; |