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r23499 Thursday 6th June, 2013 at 16:26:48 UTC by smf
moved handlers into the ide_controller_device (nw)

[src/emu/machine]	ataflash.c idectrl.c idectrl.h
[src/mame/drivers]	calchase.c chihiro.c cobra.c djmain.c fruitpc.c funkball.c gamecstl.c jaguar.c kinst.c mediagx.c midqslvr.c photoply.c qdrmfgp.c queen.c savquest.c seattle.c taitotz.c twinkle.c vegas.c viper.c voyager.c zn.c
[src/mame/includes]	djmain.h qdrmfgp.h
[src/mame/machine]	midwayic.c
[src/mess/includes]	bebox.h
[src/mess/machine]	a2cffa.c a2vulcan.c a2zipdrive.c adam_ide.c bebox.c c64_ide64.c isa_ide.c kc_d004.c
[src/mess/machine/ti99]	tn_ide.c tn_ide.h

trunk/src/emu/machine/ataflash.c

r23498	r23499
41	41
42	42	READ16_MEMBER( ata_flash_pccard_device::read_memory )
43	43	{
44		return ide_controller16_pcmcia_r(m_card, space, offset, mem_mask);
	44	return m_card->ide_controller16_pcmcia_r(space, offset, mem_mask);
45	45	}
46	46
47	47	WRITE16_MEMBER( ata_flash_pccard_device::write_memory )
48	48	{
49		ide_controller16_pcmcia_w(m_card, space, offset, data, mem_mask);
	49	m_card->ide_controller16_pcmcia_w(space, offset, data, mem_mask);
50	50	}
51	51
52	52	READ16_MEMBER( ata_flash_pccard_device::read_reg )

trunk/src/emu/machine/idectrl.c

r23498	r23499
1370	1370	select: 0->CS1Fx active, 1->CS3Fx active
1371	1371	offset: register offset (state of DA2-DA0)
1372	1372	*/
1373		int ide_bus_r(device_t *device, int select, int offset)
	1373	int ide_controller_device::ide_bus_r(int select, int offset)
1374	1374	{
1375		ide_controller_device *ide = (ide_controller_device *) device;
1376		return ide->ide_controller_read(select ? 1 : 0, offset, select == 0 && offset == 0 ? 2 : 1);
	1375	return ide_controller_read(select ? 1 : 0, offset, select == 0 && offset == 0 ? 2 : 1);
1377	1376	}
1378	1377
1379	1378	/*
r23498	r23499
1385	1384	offset: register offset (state of DA2-DA0)
1386	1385	data: data written (state of D0-D15 or D0-D7)
1387	1386	*/
1388		void ide_bus_w(device_t *device, int select, int offset, int data)
	1387	void ide_controller_device::ide_bus_w(int select, int offset, int data)
1389	1388	{
1390		ide_controller_device *ide = (ide_controller_device *) device;
1391	1389	if (select == 0 && offset == 0)
1392		ide->ide_controller_write(0, 0, 2, data);
	1390	ide_controller_write(0, 0, 2, data);
1393	1391	else
1394		ide->ide_controller_write(select ? 1 : 0, offset, 1, data & 0xff);
	1392	ide_controller_write(select ? 1 : 0, offset, 1, data & 0xff);
1395	1393	}
1396	1394
1397		UINT32 ide_controller_r(device_t *device, int reg, int size)
	1395	UINT32 ide_controller_device::ide_controller_r(int reg, int size)
1398	1396	{
1399		ide_controller_device *ide = (ide_controller_device *) device;
1400	1397	if (reg >= 0x1f0 && reg < 0x1f8)
1401		return ide->ide_controller_read(0, reg & 7, size);
	1398	return ide_controller_read(0, reg & 7, size);
1402	1399	if (reg >= 0x3f0 && reg < 0x3f8)
1403		return ide->ide_controller_read(1, reg & 7, size);
	1400	return ide_controller_read(1, reg & 7, size);
1404	1401	if (reg >= 0x030 && reg < 0x040)
1405		return ide->ide_controller_read(2, reg & 0xf, size);
	1402	return ide_controller_read(2, reg & 0xf, size);
1406	1403	return 0xffffffff;
1407	1404	}
1408	1405
1409		void ide_controller_w(device_t *device, int reg, int size, UINT32 data)
	1406	void ide_controller_device::ide_controller_w(int reg, int size, UINT32 data)
1410	1407	{
1411		ide_controller_device *ide = (ide_controller_device *) device;
1412	1408	if (reg >= 0x1f0 && reg < 0x1f8)
1413		ide->ide_controller_write(0, reg & 7, size, data);
	1409	ide_controller_write(0, reg & 7, size, data);
1414	1410	if (reg >= 0x3f0 && reg < 0x3f8)
1415		ide->ide_controller_write(1, reg & 7, size, data);
	1411	ide_controller_write(1, reg & 7, size, data);
1416	1412	if (reg >= 0x030 && reg < 0x040)
1417		ide->ide_controller_write(2, reg & 0xf, size, data);
	1413	ide_controller_write(2, reg & 0xf, size, data);
1418	1414	}
1419	1415
1420	1416
r23498	r23499
1424	1420	*
1425	1421	*************************************/
1426	1422
1427		READ32_DEVICE_HANDLER( ide_controller32_r )
	1423	READ32_MEMBER( ide_controller_device::ide_controller32_r )
1428	1424	{
1429	1425	int size;
1430	1426
1431	1427	offset *= 4;
1432	1428	size = convert_to_offset_and_size32(&offset, mem_mask);
1433	1429
1434		return ide_controller_r(device, offset, size) << ((offset & 3) * 8);
	1430	return ide_controller_r(offset, size) << ((offset & 3) * 8);
1435	1431	}
1436	1432
1437	1433
1438		WRITE32_DEVICE_HANDLER( ide_controller32_w )
	1434	WRITE32_MEMBER( ide_controller_device::ide_controller32_w )
1439	1435	{
1440	1436	int size;
1441	1437
r23498	r23499
1443	1439	size = convert_to_offset_and_size32(&offset, mem_mask);
1444	1440	data = data >> ((offset & 3) * 8);
1445	1441
1446		ide_controller_w(device, offset, size, data);
	1442	ide_controller_w(offset, size, data);
1447	1443	}
1448	1444
1449	1445
1450		READ16_DEVICE_HANDLER( ide_controller16_pcmcia_r )
	1446	READ16_MEMBER( ide_controller_device::ide_controller16_pcmcia_r )
1451	1447	{
1452		ide_controller_device *ide = (ide_controller_device *) device;
1453
1454	1448	int size;
1455	1449	UINT32 res = 0xffff;
1456	1450
r23498	r23499
1458	1452	size = convert_to_offset_and_size16(&offset, mem_mask);
1459	1453
1460	1454	if (offset < 0x008)
1461		res = ide->ide_controller_read(0, offset & 7, size);
	1455	res = ide_controller_read(0, offset & 7, size);
1462	1456	if (offset >= 0x008 && offset < 0x010)
1463		res = ide->ide_controller_read(1, offset & 7, size);
	1457	res = ide_controller_read(1, offset & 7, size);
1464	1458
1465	1459	return res << ((offset & 1) * 8);
1466	1460	}
1467	1461
1468	1462
1469		WRITE16_DEVICE_HANDLER( ide_controller16_pcmcia_w )
	1463	WRITE16_MEMBER( ide_controller_device::ide_controller16_pcmcia_w )
1470	1464	{
1471	1465	int size;
1472	1466
1473		ide_controller_device *ide = (ide_controller_device *) device;
1474
1475	1467	offset *= 2;
1476	1468	size = convert_to_offset_and_size16(&offset, mem_mask);
1477	1469	data = data >> ((offset & 1) * 8);
1478	1470
1479	1471	if (offset < 0x008)
1480		ide->ide_controller_write(0, offset & 7, size, data);
	1472	ide_controller_write(0, offset & 7, size, data);
1481	1473	if (offset >= 0x008 && offset < 0x010)
1482		ide->ide_controller_write(1, offset & 7, size, data);
	1474	ide_controller_write(1, offset & 7, size, data);
1483	1475	}
1484	1476
1485		READ32_DEVICE_HANDLER( ide_bus_master32_r )
	1477	READ32_MEMBER( ide_controller_device::ide_bus_master32_r )
1486	1478	{
1487	1479	int size;
1488	1480
1489		ide_controller_device *ide = (ide_controller_device *) device;
1490
1491	1481	offset *= 4;
1492	1482	size = convert_to_offset_and_size32(&offset, mem_mask);
1493	1483
1494		return ide->ide_bus_master_read(offset, size) << ((offset & 3) * 8);
	1484	return ide_bus_master_read(offset, size) << ((offset & 3) * 8);
1495	1485	}
1496	1486
1497	1487
1498		WRITE32_DEVICE_HANDLER( ide_bus_master32_w )
	1488	WRITE32_MEMBER( ide_controller_device::ide_bus_master32_w )
1499	1489	{
1500	1490	int size;
1501	1491
1502		ide_controller_device *ide = (ide_controller_device *) device;
1503
1504	1492	offset *= 4;
1505	1493	size = convert_to_offset_and_size32(&offset, mem_mask);
1506	1494
1507		ide->ide_bus_master_write(offset, size, data >> ((offset & 3) * 8));
	1495	ide_bus_master_write(offset, size, data >> ((offset & 3) * 8));
1508	1496	}
1509	1497
1510	1498
r23498	r23499
1515	1503	*
1516	1504	*************************************/
1517	1505
1518		READ16_DEVICE_HANDLER( ide_controller16_r )
	1506	READ16_MEMBER( ide_controller_device::ide_controller16_r )
1519	1507	{
1520	1508	int size;
1521	1509
1522	1510	offset *= 2;
1523	1511	size = convert_to_offset_and_size16(&offset, mem_mask);
1524	1512
1525		return ide_controller_r(device, offset, size) << ((offset & 1) * 8);
	1513	return ide_controller_r(offset, size) << ((offset & 1) * 8);
1526	1514	}
1527	1515
1528	1516
1529		WRITE16_DEVICE_HANDLER( ide_controller16_w )
	1517	WRITE16_MEMBER( ide_controller_device::ide_controller16_w )
1530	1518	{
1531	1519	int size;
1532	1520
1533	1521	offset *= 2;
1534	1522	size = convert_to_offset_and_size16(&offset, mem_mask);
1535	1523
1536		ide_controller_w(device, offset, size, data >> ((offset & 1) * 8));
	1524	ide_controller_w(offset, size, data >> ((offset & 1) * 8));
1537	1525	}
1538	1526
1539	1527	SLOT_INTERFACE_START(ide_devices)

trunk/src/emu/machine/idectrl.h

r23498	r23499
14	14	#ifndef __IDECTRL_H__
15	15	#define __IDECTRL_H__
16	16
17		#include "devlegcy.h"
18
19	17	#include "idehd.h"
20	18	#include "harddisk.h"
21	19
r23498	r23499
71	69	MCFG_DEVICE_SLOT_INTERFACE(_slot_intf, _def_slot, _fixed)
72	70
73	71	/***************************************************************************
74		FUNCTION PROTOTYPES
75		***************************************************************************/
76
77		int ide_bus_r(device_t *config, int select, int offset);
78		void ide_bus_w(device_t *config, int select, int offset, int data);
79
80		UINT32 ide_controller_r(device_t *config, int reg, int size);
81		void ide_controller_w(device_t *config, int reg, int size, UINT32 data);
82
83		DECLARE_READ32_DEVICE_HANDLER( ide_controller32_r );
84		DECLARE_WRITE32_DEVICE_HANDLER( ide_controller32_w );
85		DECLARE_READ16_DEVICE_HANDLER( ide_controller16_pcmcia_r );
86		DECLARE_WRITE16_DEVICE_HANDLER( ide_controller16_pcmcia_w );
87		DECLARE_READ32_DEVICE_HANDLER( ide_bus_master32_r );
88		DECLARE_WRITE32_DEVICE_HANDLER( ide_bus_master32_w );
89
90		DECLARE_READ16_DEVICE_HANDLER( ide_controller16_r );
91		DECLARE_WRITE16_DEVICE_HANDLER( ide_controller16_w );
92
93		/***************************************************************************
94	72	TYPE DEFINITIONS
95	73	***************************************************************************/
96	74
r23498	r23499
112	90	void ide_set_master_password(const UINT8 *password);
113	91	void ide_set_user_password(const UINT8 *password);
114	92
	93	int ide_bus_r(int select, int offset);
	94	void ide_bus_w(int select, int offset, int data);
	95
	96	UINT32 ide_controller_r(int reg, int size);
	97	void ide_controller_w(int reg, int size, UINT32 data);
	98
	99	DECLARE_READ32_MEMBER( ide_controller32_r );
	100	DECLARE_WRITE32_MEMBER( ide_controller32_w );
	101	DECLARE_READ16_MEMBER( ide_controller16_pcmcia_r );
	102	DECLARE_WRITE16_MEMBER( ide_controller16_pcmcia_w );
	103	DECLARE_READ32_MEMBER( ide_bus_master32_r );
	104	DECLARE_WRITE32_MEMBER( ide_bus_master32_w );
	105
	106	DECLARE_READ16_MEMBER( ide_controller16_r );
	107	DECLARE_WRITE16_MEMBER( ide_controller16_w );
	108
115	109	UINT32 ide_controller_read(int bank, offs_t offset, int size);
116	110	void ide_controller_write(int bank, offs_t offset, int size, UINT32 data);
117	111	UINT32 ide_bus_master_read(offs_t offset, int size);
r23498	r23499
190	184
191	185	extern const device_type IDE_CONTROLLER;
192	186
193
194
195	187	#endif  /* __IDECTRL_H__ */

trunk/src/mess/includes/bebox.h

r23498	r23499
10	10	#define BEBOX_H_
11	11
12	12	#include "emu.h"
	13	#include "machine/53c810.h"
	14	#include "machine/am9517a.h"
	15	#include "machine/idectrl.h"
13	16	#include "machine/ins8250.h"
14		#include "machine/am9517a.h"
15		#include "machine/53c810.h"
16		#include "machine/upd765.h"
17		#include "machine/ram.h"
18	17	#include "machine/pic8259.h"
19	18	#include "machine/pit8253.h"
	19	#include "machine/ram.h"
	20	#include "machine/upd765.h"
20	21
21	22	class bebox_state : public driver_device
22	23	{
r23498	r23499
36	37	m_pic8259_1(*this, "pic8259_1"),
37	38	m_pic8259_2(*this, "pic8259_2"),
38	39	m_pit8254(*this, "pit8254"),
39		m_ram(*this, RAM_TAG){ }
	40	m_ram(*this, RAM_TAG),
	41	m_ide(*this, "ide")
	42	{
	43	}
40	44
41	45	required_device<cpu_device> m_ppc1;
42	46	required_device<cpu_device> m_ppc2;
r23498	r23499
47	51	required_device<pic8259_device> m_pic8259_2;
48	52	required_device<pit8254_device> m_pit8254;
49	53	required_device<ram_device> m_ram;
	54	required_device<ide_controller_device> m_ide;
50	55	UINT32 m_cpu_imask[2];
51	56	UINT32 m_interrupts;
52	57	UINT32 m_crossproc_interrupts;

trunk/src/mess/machine/a2zipdrive.c

r23498	r23499
116	116	case 5:
117	117	case 6:
118	118	case 7:
119		return ide_controller_r(m_ide, 0x1f0+offset, 1);
	119	return m_ide->ide_controller_r(0x1f0+offset, 1);
120	120
121	121	case 8: // data port
122		m_lastdata = ide_controller_r(m_ide, 0x1f0, 2);
	122	m_lastdata = m_ide->ide_controller_r(0x1f0, 2);
123	123	//          printf("%04x @ IDE data\n", m_lastdata);
124	124	return m_lastdata&0xff;
125	125
r23498	r23499
152	152	case 6:
153	153	case 7:
154	154	//          printf("%02x to IDE controller @ %x\n", data, offset);
155		ide_controller_w(m_ide, 0x1f0+offset, 1, data);
	155	m_ide->ide_controller_w(0x1f0+offset, 1, data);
156	156	break;
157	157
158	158	case 8:
r23498	r23499
164	164	//          printf("%02x to IDE data hi\n", data);
165	165	m_lastdata &= 0x00ff;
166	166	m_lastdata |= (data << 8);
167		ide_controller_w(m_ide, 0x1f0, 2, m_lastdata);
	167	m_ide->ide_controller_w(0x1f0, 2, m_lastdata);
168	168	break;
169	169
170	170	default:

trunk/src/mess/machine/bebox.c

r23498	r23499
504	504	*
505	505	*************************************/
506	506
507		static device_t *ide_device(running_machine &machine)
508		{
509		return machine.device("ide");
510		}
	507	READ8_MEMBER(bebox_state::bebox_800001F0_r ) { return m_ide->ide_controller_r(offset + 0x1F0, 1); }
	508	WRITE8_MEMBER(bebox_state::bebox_800001F0_w ) { m_ide->ide_controller_w(offset + 0x1F0, 1, data); }
511	509
512		READ8_MEMBER(bebox_state::bebox_800001F0_r ) { return ide_controller_r(ide_device(space.machine()), offset + 0x1F0, 1); }
513		WRITE8_MEMBER(bebox_state::bebox_800001F0_w ) { ide_controller_w(ide_device(space.machine()), offset + 0x1F0, 1, data); }
514
515	510	READ64_MEMBER(bebox_state::bebox_800003F0_r )
516	511	{
517	512	UINT64 result = 0;
518	513
519	514	if (((mem_mask >> 8) & 0xFF) == 0)
520	515	{
521		result |= ide_controller_r(space.machine().device("ide"), 0x3F6, 1) << 8;
	516	result |= m_ide->ide_controller_r(0x3F6, 1) << 8;
522	517	}
523	518	return result;
524	519	}
r23498	r23499
527	522	WRITE64_MEMBER(bebox_state::bebox_800003F0_w )
528	523	{
529	524	if (((mem_mask >> 8) & 0xFF) == 0)
530		ide_controller_w(space.machine().device("ide"), 0x3F6, 1, (data >> 8) & 0xFF);
	525	m_ide->ide_controller_w(0x3F6, 1, (data >> 8) & 0xFF);
531	526	}
532	527
533	528

trunk/src/mess/machine/c64_ide64.c

r23498	r23499
181	181
182	182	if (io1_offset >= 0x20 && io1_offset < 0x30)
183	183	{
184		m_ide_data = ide_bus_r(m_ide, BIT(offset, 3), offset & 0x07);
	184	m_ide_data = m_ide->ide_bus_r(BIT(offset, 3), offset & 0x07);
185	185
186	186	data = m_ide_data & 0xff;
187	187	}
r23498	r23499
278	278	{
279	279	m_ide_data = (m_ide_data & 0xff00) | data;
280	280
281		ide_bus_w(m_ide, BIT(offset, 3), offset & 0x07, m_ide_data);
	281	m_ide->ide_bus_w(BIT(offset, 3), offset & 0x07, m_ide_data);
282	282	}
283	283	else if (io1_offset == 0x31)
284	284	{

trunk/src/mess/machine/adam_ide.c

r23498	r23499
121	121	case 0x05:
122	122	case 0x06:
123	123	case 0x07:
124		data = ide_bus_r(m_ide, 0, offset & 0x07) & 0xff;
	124	data = m_ide->ide_bus_r(0, offset & 0x07) & 0xff;
125	125	break;
126	126
127	127	case 0x40: // Printer status
r23498	r23499
142	142	break;
143	143
144	144	case 0x58:
145		m_ide_data = ide_bus_r(m_ide, 0, 0);
	145	m_ide_data = m_ide->ide_bus_r(0, 0);
146	146
147	147	data = m_ide_data & 0xff;
148	148	break;
r23498	r23499
152	152	break;
153	153
154	154	case 0x5a:
155		data = ide_bus_r(m_ide, 1, 6) & 0xff;
	155	data = m_ide->ide_bus_r(1, 6) & 0xff;
156	156	break;
157	157
158	158	case 0x5b: // Digital Input Register
r23498	r23499
181	181	case 0x05:
182	182	case 0x06:
183	183	case 0x07:
184		ide_bus_w(m_ide, 0, offset & 0x07, data);
	184	m_ide->ide_bus_w(0, offset & 0x07, data);
185	185	break;
186	186
187	187	case 0x40:
r23498	r23499
193	193
194	194	case 0x58:
195	195	m_ide_data |= data;
196		ide_bus_w(m_ide, 0, 0, m_ide_data);
	196	m_ide->ide_bus_w(0, 0, m_ide_data);
197	197	break;
198	198
199	199	case 0x59:

trunk/src/mess/machine/isa_ide.c

r23498	r23499
11	11
12	12	READ16_MEMBER(isa16_ide_device::ide16_r)
13	13	{
14		return ide_controller16_r(m_ide, space, 0x1f0/2 + offset, mem_mask);
	14	return m_ide->ide_controller16_r(space, 0x1f0/2 + offset, mem_mask);
15	15	}
16	16
17	17	WRITE16_MEMBER(isa16_ide_device::ide16_w)
18	18	{
19		ide_controller16_w(m_ide, space, 0x1f0/2 + offset, data, mem_mask);
	19	m_ide->ide_controller16_w(space, 0x1f0/2 + offset, data, mem_mask);
20	20	}
21	21
22	22	READ8_MEMBER(isa16_ide_device::ide16_alt_r )
23	23	{
24		return ide_controller16_r(m_ide, space, 0x3f6/2, 0x00ff);
	24	return m_ide->ide_controller16_r(space, 0x3f6/2, 0x00ff);
25	25	}
26	26
27	27	WRITE8_MEMBER(isa16_ide_device::ide16_alt_w )
28	28	{
29		ide_controller16_w(m_ide, space, 0x3f6/2, data, 0x00ff);
	29	m_ide->ide_controller16_w(space, 0x3f6/2, data, 0x00ff);
30	30	}
31	31
32	32	DEVICE_ADDRESS_MAP_START(map, 16, isa16_ide_device)

trunk/src/mess/machine/a2vulcan.c

r23498	r23499
151	151	switch (offset)
152	152	{
153	153	case 0:
154		m_lastdata = ide_controller_r(m_ide, 0x1f0+offset, 2);
	154	m_lastdata = m_ide->ide_controller_r(0x1f0+offset, 2);
155	155	//          printf("IDE: read %04x\n", m_lastdata);
156	156	m_last_read_was_0 = true;
157	157	return m_lastdata&0xff;
r23498	r23499
164	164	}
165	165	else
166	166	{
167		return ide_controller_r(m_ide, 0x1f0+offset, 1);
	167	return m_ide->ide_controller_r(0x1f0+offset, 1);
168	168	}
169	169	break;
170	170
r23498	r23499
174	174	case 5:
175	175	case 6:
176	176	case 7:
177		return ide_controller_r(m_ide, 0x1f0+offset, 1);
	177	return m_ide->ide_controller_r(0x1f0+offset, 1);
178	178
179	179	default:
180	180	//          printf("Read @ C0n%x\n", offset);
r23498	r23499
206	206	m_lastdata &= 0x00ff;
207	207	m_lastdata |= (data << 8);
208	208	//              printf("IDE: write %04x\n", m_lastdata);
209		ide_controller_w(m_ide, 0x1f0, 2, m_lastdata);
	209	m_ide->ide_controller_w(0x1f0, 2, m_lastdata);
210	210	}
211	211	else
212	212	{
213		ide_controller_w(m_ide, 0x1f0+offset, 1, data);
	213	m_ide->ide_controller_w(0x1f0+offset, 1, data);
214	214	}
215	215	break;
216	216
r23498	r23499
221	221	case 6:
222	222	case 7:
223	223	//          printf("%02x to IDE controller @ %x\n", data, offset);
224		ide_controller_w(m_ide, 0x1f0+offset, 1, data);
	224	m_ide->ide_controller_w(0x1f0+offset, 1, data);
225	225	break;
226	226
227	227	case 9: // ROM bank

trunk/src/mess/machine/ti99/tn_ide.c

r23498	r23499
151	151	case 2:     /* IDE registers set 1 (CS1Fx) */
152	152	if (m_tms9995_mode ? (!(addr & 1)) : (addr & 1))
153	153	{   /* first read triggers 16-bit read cycle */
154		m_input_latch = (! (addr & 0x10)) ? ide_bus_r(m_ide, 0, (addr >> 1) & 0x7) : 0;
	154	m_input_latch = (! (addr & 0x10)) ? m_ide->ide_bus_r(0, (addr >> 1) & 0x7) : 0;
155	155	}
156	156
157	157	/* return latched input */
r23498	r23499
162	162	case 3:     /* IDE registers set 2 (CS3Fx) */
163	163	if (m_tms9995_mode ? (!(addr & 1)) : (addr & 1))
164	164	{   /* first read triggers 16-bit read cycle */
165		m_input_latch = (! (addr & 0x10)) ? ide_bus_r(m_ide, 1, (addr >> 1) & 0x7) : 0;
	165	m_input_latch = (! (addr & 0x10)) ? m_ide->ide_bus_r(1, (addr >> 1) & 0x7) : 0;
166	166	}
167	167
168	168	/* return latched input */
r23498	r23499
232	232
233	233	if (m_tms9995_mode ? (addr & 1) : (!(addr & 1)))
234	234	{   /* second write triggers 16-bit write cycle */
235		ide_bus_w(m_ide, 0, (addr >> 1) & 0x7, m_output_latch);
	235	m_ide->ide_bus_w(0, (addr >> 1) & 0x7, m_output_latch);
236	236	}
237	237	break;
238	238	case 3:     /* IDE registers set 2 (CS3Fx) */
r23498	r23499
250	250
251	251	if (m_tms9995_mode ? (addr & 1) : (!(addr & 1)))
252	252	{   /* second write triggers 16-bit write cycle */
253		ide_bus_w(m_ide, 1, (addr >> 1) & 0x7, m_output_latch);
	253	m_ide->ide_bus_w(1, (addr >> 1) & 0x7, m_output_latch);
254	254	}
255	255	break;
256	256	}
r23498	r23499
297	297	void nouspikel_ide_interface_device::device_start()
298	298	{
299	299	m_rtc = subdevice<rtc65271_device>("ide_rtc");
300		m_ide = subdevice("ide");
	300	m_ide = subdevice<ide_controller_device>("ide");
301	301
302	302	m_ram = memregion(BUFFER_TAG)->base();
303	303	m_sram_enable_dip = false; // TODO: what is this?

trunk/src/mess/machine/ti99/tn_ide.h

r23498	r23499
14	14
15	15	#include "emu.h"
16	16	#include "ti99defs.h"
	17	#include "machine/idectrl.h"
17	18	#include "machine/rtc65271.h"
18	19
19	20	extern const device_type TI99_IDE;
r23498	r23499
44	45
45	46	private:
46	47	rtc65271_device*    m_rtc;
47		device_t*          m_ide;
	48	ide_controller_device* m_ide;
48	49
49	50	bool    m_clk_irq;
50	51	bool    m_sram_enable;

trunk/src/mess/machine/a2cffa.c

r23498	r23499
143	143	break;
144	144
145	145	case 8:
146		m_lastdata = ide_controller_r(m_ide, 0x1f0+offset-8, 2);
	146	m_lastdata = m_ide->ide_controller_r(0x1f0+offset-8, 2);
147	147	return m_lastdata & 0xff;
148	148
149	149	case 9:
r23498	r23499
153	153	case 0xd:
154	154	case 0xe:
155	155	case 0xf:
156		return ide_controller_r(m_ide, 0x1f0+offset-8, 1);
	156	return m_ide->ide_controller_r(0x1f0+offset-8, 1);
157	157	}
158	158
159	159	return 0xff;
r23498	r23499
184	184	case 8:
185	185	m_lastdata &= 0xff00;
186	186	m_lastdata |= data;
187		ide_controller_w(m_ide, 0x1f0+offset-8, 2, m_lastdata);
	187	m_ide->ide_controller_w(0x1f0+offset-8, 2, m_lastdata);
188	188	break;
189	189
190	190	case 9:
r23498	r23499
194	194	case 0xd:
195	195	case 0xe:
196	196	case 0xf:
197		ide_controller_w(m_ide, 0x1f0+offset-8, 1, data);
	197	m_ide->ide_controller_w(0x1f0+offset-8, 1, data);
198	198	break;
199	199	}
200	200	}

trunk/src/mess/machine/kc_d004.c

r23498	r23499
454	454	data_shift = 8;
455	455
456	456	if (io_addr == 0x06 || io_addr == 0x07 || io_addr > 0x08 || (io_addr == 0x08 && !m_lh))
457		m_ide_data = ide_bus_r(m_ide, ide_cs, io_addr & 0x07);
	457	m_ide_data = m_ide->ide_bus_r(ide_cs, io_addr & 0x07);
458	458
459	459	data = (m_ide_data >> data_shift) & 0xff;
460	460	}
r23498	r23499
494	494	m_ide_data = (data << data_shift) | (m_ide_data & (0xff00 >> data_shift));
495	495
496	496	if (io_addr == 0x06 || io_addr == 0x07 || io_addr > 0x08 || (io_addr == 0x08 && m_lh))
497		ide_bus_w(m_ide, ide_cs, io_addr & 0x07, m_ide_data);
	497	m_ide->ide_bus_w(ide_cs, io_addr & 0x07, m_ide_data);
498	498	}
499	499
500	500	m_lh = (io_addr == 0x08) ? !m_lh : ((io_addr > 0x08) ? 0 : m_lh);

trunk/src/mame/machine/midwayic.c

r23498	r23499
1065	1065	UINT8 shift = 8 * (offset & 3);
1066	1066	UINT32 result;
1067	1067
	1068	ide_controller_device *ide = (ide_controller_device *) device;
	1069
1068	1070	/* offset 0 is a special case */
1069	1071	if (offset == 0)
1070		result = ide_controller32_r(device, space, ideoffs, 0x0000ffff);
	1072	result = ide->ide_controller32_r(space, ideoffs, 0x0000ffff);
1071	1073
1072	1074	/* everything else is byte-sized */
1073	1075	else
1074		result = ide_controller32_r(device, space, ideoffs, 0xff << shift) >> shift;
	1076	result = ide->ide_controller32_r(space, ideoffs, 0xff << shift) >> shift;
1075	1077	return result;
1076	1078	}
1077	1079
r23498	r23499
1082	1084	offs_t ideoffs = 0x1f0/4 + (offset >> 2);
1083	1085	UINT8 shift = 8 * (offset & 3);
1084	1086
	1087	ide_controller_device *ide = (ide_controller_device *) device;
	1088
1085	1089	/* offset 0 is a special case */
1086	1090	if (offset == 0)
1087		ide_controller32_w(device, space, ideoffs, data, 0x0000ffff);
	1091	ide->ide_controller32_w(space, ideoffs, data, 0x0000ffff);
1088	1092
1089	1093	/* everything else is byte-sized */
1090	1094	else
1091		ide_controller32_w(device, space, ideoffs, data << shift, 0xff << shift);
	1095	ide->ide_controller32_w(space, ideoffs, data << shift, 0xff << shift);
1092	1096	}

trunk/src/mame/includes/qdrmfgp.h

r23498	r23499
	1	#include "machine/idectrl.h"
1	2	#include "sound/k054539.h"
2	3
3	4	class qdrmfgp_state : public driver_device
r23498	r23499
9	10	m_nvram(*this, "nvram"),
10	11	m_workram(*this, "workram"),
11	12	m_k056832(*this, "k056832"),
12		m_k054539(*this, "k054539") { }
	13	m_k054539(*this, "k054539"),
	14	m_ide(*this, "ide")
	15	{
	16	}
13	17
14	18	required_device<cpu_device> m_maincpu;
15	19	required_shared_ptr<UINT16> m_nvram;
r23498	r23499
17	21	required_shared_ptr<UINT16> m_workram;
18	22	required_device<k056832_device> m_k056832;
19	23	required_device<k054539_device> m_k054539;
	24	required_device<ide_controller_device> m_ide;
20	25	UINT16 m_control;
21	26	INT32 m_gp2_irq_control;
22	27	INT32 m_pal;

trunk/src/mame/includes/djmain.h

r23498	r23499
	1	#include "machine/idectrl.h"
	2
1	3	class djmain_state : public driver_device
2	4	{
3	5	public:
r23498	r23499
6	8	m_obj_ram(*this, "obj_ram"),
7	9	m_maincpu(*this, "maincpu"),
8	10	m_k056832(*this, "k056832"),
9		m_k055555(*this, "k055555") { }
	11	m_k055555(*this, "k055555"),
	12	m_ide(*this, "ide")
	13	{
	14	}
10	15
11	16	int m_sndram_bank;
12	17	UINT8 *m_sndram;
r23498	r23499
64	69	required_device<cpu_device> m_maincpu;
65	70	required_device<k056832_device> m_k056832;
66	71	required_device<k055555_device> m_k055555;
	72	required_device<ide_controller_device> m_ide;
67	73	};
68	74
69	75	/*----------- defined in video/djmain.c -----------*/

trunk/src/mame/drivers/vegas.c

r23498	r23499
1458	1458
1459	1459	static READ32_DEVICE_HANDLER( ide_main_r )
1460	1460	{
1461		return ide_controller32_r(device, space, 0x1f0/4 + offset, mem_mask);
	1461	ide_controller_device *ide = (ide_controller_device *) device;
	1462	return ide->ide_controller32_r(space, 0x1f0/4 + offset, mem_mask);
1462	1463	}
1463	1464
1464	1465
1465	1466	static WRITE32_DEVICE_HANDLER( ide_main_w )
1466	1467	{
1467		ide_controller32_w(device, space, 0x1f0/4 + offset, data, mem_mask);
	1468	ide_controller_device *ide = (ide_controller_device *) device;
	1469	ide->ide_controller32_w(space, 0x1f0/4 + offset, data, mem_mask);
1468	1470	}
1469	1471
1470	1472
1471	1473	static READ32_DEVICE_HANDLER( ide_alt_r )
1472	1474	{
1473		return ide_controller32_r(device, space, 0x3f4/4 + offset, mem_mask);
	1475	ide_controller_device *ide = (ide_controller_device *) device;
	1476	return ide->ide_controller32_r(space, 0x3f4/4 + offset, mem_mask);
1474	1477	}
1475	1478
1476	1479
1477	1480	static WRITE32_DEVICE_HANDLER( ide_alt_w )
1478	1481	{
1479		ide_controller32_w(device, space, 0x3f4/4 + offset, data, mem_mask);
	1482	ide_controller_device *ide = (ide_controller_device *) device;
	1483	ide->ide_controller32_w(space, 0x3f4/4 + offset, data, mem_mask);
1480	1484	}
1481	1485
1482	1486
	1487	static READ32_DEVICE_HANDLER( ide_bus_master32_r )
	1488	{
	1489	ide_controller_device *ide = (ide_controller_device *) device;
	1490	return ide->ide_bus_master32_r(space, offset, mem_mask);
	1491	}
	1492
	1493
	1494	static WRITE32_DEVICE_HANDLER( ide_bus_master32_w )
	1495	{
	1496	ide_controller_device *ide = (ide_controller_device *) device;
	1497	ide->ide_bus_master32_w(space, offset, data, mem_mask);
	1498	}
	1499
	1500
1483	1501	static READ32_DEVICE_HANDLER( ethernet_r )
1484	1502	{
1485	1503	UINT32 result = 0;

trunk/src/mame/drivers/funkball.c

r23498	r23499
215	215	#if 0
216	216	READ32_MEMBER(funkball_state::ide_r)
217	217	{
218		device_t *device = machine().device("ide");
219		return ide_controller32_r(device, space, 0x1f0/4 + offset, mem_mask);
	218	return m_ide->ide_controller32_r(space, 0x1f0/4 + offset, mem_mask);
220	219	}
221	220
222	221	WRITE32_MEMBER(funkball_state::ide_w)
223	222	{
224		device_t *device = machine().device("ide");
225		ide_controller32_w(device, space, 0x1f0/4 + offset, data, mem_mask);
	223	m_ide->ide_controller32_w(space, 0x1f0/4 + offset, data, mem_mask);
226	224	}
227	225
228	226	READ32_MEMBER(funkball_state::fdc_r)
229	227	{
230		device_t *device = machine().device("ide");
231		return ide_controller32_r(device, space, 0x3f0/4 + offset, mem_mask);
	228	return m-ide->ide_controller32_r(space, 0x3f0/4 + offset, mem_mask);
232	229	}
233	230
234	231	WRITE32_MEMBER(funkball_state::fdc_w)
235	232	{
236		device_t *device = machine().device("ide");
237	233	//mame_printf_debug("FDC: write %08X, %08X, %08X\n", data, offset, mem_mask);
238		ide_controller32_w(device, space, 0x3f0/4 + offset, data, mem_mask);
	234	m_ide->ide_controller32_w(space, 0x3f0/4 + offset, data, mem_mask);
239	235	}
240	236	#endif
241	237

trunk/src/mame/drivers/qdrmfgp.c

r23498	r23499
181	181
182	182	/*************/
183	183
184		#define IDE_STD_OFFSET  (0x1f0/2)
185		#define IDE_ALT_OFFSET  (0x3f6/2)
186
187	184	READ16_MEMBER(qdrmfgp_state::ide_std_r)
188	185	{
189		device_t *device = machine().device("ide");
190	186	if (offset & 0x01)
191		return ide_controller16_r(device, space, IDE_STD_OFFSET + offset/2, 0xff00) >> 8;
	187	return m_ide->ide_controller16_r(space, 0x1f0/2 + offset/2, 0xff00) >> 8;
192	188	else
193		return ide_controller16_r(device, space, IDE_STD_OFFSET + offset/2, 0xffff);
	189	return m_ide->ide_controller16_r(space, 0x1f0/2 + offset/2, 0xffff);
194	190	}
195	191
196	192	WRITE16_MEMBER(qdrmfgp_state::ide_std_w)
197	193	{
198		device_t *device = machine().device("ide");
199	194	if (offset & 0x01)
200		ide_controller16_w(device, space, IDE_STD_OFFSET + offset/2, data << 8, 0xff00);
	195	m_ide->ide_controller16_w(space, 0x1f0/2 + offset/2, data << 8, 0xff00);
201	196	else
202		ide_controller16_w(device, space, IDE_STD_OFFSET + offset/2, data, 0xffff);
	197	m_ide->ide_controller16_w(space, 0x1f0/2 + offset/2, data, 0xffff);
203	198	}
204	199
205	200	READ16_MEMBER(qdrmfgp_state::ide_alt_r)
206	201	{
207		device_t *device = machine().device("ide");
208	202	if (offset == 0)
209		return ide_controller16_r(device, space, IDE_ALT_OFFSET, 0x00ff);
	203	return m_ide->ide_controller16_r(space, 0x3f6/2, 0x00ff);
210	204
211	205	return 0;
212	206	}
213	207
214	208	WRITE16_MEMBER(qdrmfgp_state::ide_alt_w)
215	209	{
216		device_t *device = machine().device("ide");
217	210	if (offset == 0)
218		ide_controller16_w(device, space, IDE_ALT_OFFSET, data, 0x00ff);
	211	m_ide->ide_controller16_w(space, 0x3f6/2, data, 0x00ff);
219	212	}
220	213
221	214
222	215	READ16_MEMBER(qdrmfgp_state::gp2_ide_std_r)
223	216	{
224		device_t *device = machine().device("ide");
225	217	if (offset & 0x01)
226	218	{
227	219	if (offset == 0x07)
r23498	r23499
238	230	break;
239	231	}
240	232	}
241		return ide_controller16_r(device, space, IDE_STD_OFFSET + offset/2, 0xff00) >> 8;
242		} else {
243		return ide_controller16_r(device, space, IDE_STD_OFFSET + offset/2, 0xffff);
	233
	234	return m_ide->ide_controller16_r(space, 0x1f0/2 + offset/2, 0xff00) >> 8;
244	235	}
	236	else
	237	{
	238	return m_ide->ide_controller16_r(space, 0x1f0/2 + offset/2, 0xffff);
	239	}
245	240	}
246	241
247	242
r23498	r23499
638	633
639	634	/* reset the IDE controller */
640	635	m_gp2_irq_control = 0;
641		machine().device("ide")->reset();
	636	m_ide->reset();
642	637	}
643	638
644	639

trunk/src/mame/drivers/gamecstl.c

r23498	r23499
328	328
329	329	READ32_MEMBER(gamecstl_state::ide_r)
330	330	{
331		return ide_controller32_r(m_ide, space, 0x1f0/4 + offset, mem_mask);
	331	return m_ide->ide_controller32_r(space, 0x1f0/4 + offset, mem_mask);
332	332	}
333	333
334	334	WRITE32_MEMBER(gamecstl_state::ide_w)
335	335	{
336		ide_controller32_w(m_ide, space, 0x1f0/4 + offset, data, mem_mask);
	336	m_ide->ide_controller32_w(space, 0x1f0/4 + offset, data, mem_mask);
337	337	}
338	338
339	339	READ32_MEMBER(gamecstl_state::fdc_r)
340	340	{
341		return ide_controller32_r(m_ide, space, 0x3f0/4 + offset, mem_mask);
	341	return m_ide->ide_controller32_r(space, 0x3f0/4 + offset, mem_mask);
342	342	}
343	343
344	344	WRITE32_MEMBER(gamecstl_state::fdc_w)
345	345	{
346	346	//mame_printf_debug("FDC: write %08X, %08X, %08X\n", data, offset, mem_mask);
347		ide_controller32_w(m_ide, space, 0x3f0/4 + offset, data, mem_mask);
	347	m_ide->ide_controller32_w(space, 0x3f0/4 + offset, data, mem_mask);
348	348	}
349	349
350	350

trunk/src/mame/drivers/seattle.c

r23498	r23499
429	429	m_interrupt_config(*this, "int_config"),
430	430	m_asic_reset(*this, "asic_reset"),
431	431	m_rombase(*this, "rombase"),
432		m_maincpu(*this, "maincpu") { }
	432	m_maincpu(*this, "maincpu"),
	433	m_ide(*this, "ide")
	434	{
	435	}
433	436
434	437	required_shared_ptr<UINT32> m_nvram;
435	438	required_shared_ptr<UINT32> m_rambase;
r23498	r23499
515	518	void update_widget_irq();
516	519	void init_common(int ioasic, int serialnum, int yearoffs, int config);
517	520	required_device<cpu_device> m_maincpu;
	521	required_device<ide_controller_device> m_ide;
518	522	};
519	523
520	524	/*************************************
r23498	r23499
1771	1775
1772	1776	READ32_MEMBER(seattle_state::seattle_ide_r)
1773	1777	{
1774		device_t *device = machine().device("ide");
1775	1778	/* note that blitz times out if we don't have this cycle stealing */
1776	1779	if (offset == 0x3f6/4)
1777	1780	m_maincpu->eat_cycles(100);
1778		return ide_controller32_r(device, space, offset, mem_mask);
	1781	return m_ide->ide_controller32_r(space, offset, mem_mask);
1779	1782	}
1780	1783
1781	1784	static ADDRESS_MAP_START( seattle_map, AS_PROGRAM, 32, seattle_state )
1782	1785	ADDRESS_MAP_UNMAP_HIGH
1783	1786	AM_RANGE(0x00000000, 0x007fffff) AM_RAM AM_SHARE("rambase") // wg3dh only has 4MB; sfrush, blitz99 8MB
1784	1787	AM_RANGE(0x08000000, 0x08ffffff) AM_DEVREAD_LEGACY("voodoo", voodoo_r) AM_WRITE(seattle_voodoo_w)
1785		AM_RANGE(0x0a000000, 0x0a0003ff) AM_READ(seattle_ide_r) AM_DEVWRITE_LEGACY("ide", ide_controller32_w)
	1788	AM_RANGE(0x0a000000, 0x0a0003ff) AM_READ(seattle_ide_r) AM_DEVWRITE("ide", ide_controller_device, ide_controller32_w)
1786	1789	AM_RANGE(0x0a00040c, 0x0a00040f) AM_NOP                     // IDE-related, but annoying
1787		AM_RANGE(0x0a000f00, 0x0a000f07) AM_DEVREADWRITE_LEGACY("ide", ide_bus_master32_r, ide_bus_master32_w)
	1790	AM_RANGE(0x0a000f00, 0x0a000f07) AM_DEVREADWRITE("ide", ide_controller_device, ide_bus_master32_r, ide_bus_master32_w)
1788	1791	AM_RANGE(0x0c000000, 0x0c000fff) AM_READWRITE(galileo_r, galileo_w)
1789	1792	AM_RANGE(0x13000000, 0x13000003) AM_WRITE(asic_fifo_w)
1790	1793	AM_RANGE(0x16000000, 0x1600003f) AM_READWRITE_LEGACY(midway_ioasic_r, midway_ioasic_w)

trunk/src/mame/drivers/zn.c

r23498	r23499
44	44	m_ram(*this, "maincpu:ram"),
45	45	m_cbaj_fifo1(*this, "cbaj_fifo1"),
46	46	m_cbaj_fifo2(*this, "cbaj_fifo2"),
47		m_mb3773(*this, "mb3773")
	47	m_mb3773(*this, "mb3773"),
	48	m_ide(*this, "ide")
48	49	{
49	50	}
50	51
r23498	r23499
129	130	optional_device<fifo7200_device> m_cbaj_fifo1;
130	131	optional_device<fifo7200_device> m_cbaj_fifo2;
131	132	optional_device<mb3773_device> m_mb3773;
	133	optional_device<ide_controller_device> m_ide;
132	134	};
133	135
134	136	inline void ATTR_PRINTF(3,4) zn_state::verboselog( int n_level, const char *s_fmt, ... )
r23498	r23499
1331	1333
1332	1334	void zn_state::atpsx_dma_read( UINT32 *p_n_psxram, UINT32 n_address, INT32 n_size )
1333	1335	{
1334		device_t *ide = machine().device("ide");
1335
1336	1336	//  logerror("DMA read: %d bytes (%d words) to %08x\n", n_size<<2, n_size, n_address);
1337	1337
1338	1338	if (n_address < 0x10000)
r23498	r23499
1346	1346	address_space &space = machine().firstcpu->space(AS_PROGRAM);
1347	1347	while( n_size > 0 )
1348	1348	{
1349		psxwritebyte( p_n_psxram, n_address, ide_controller32_r( ide, space, 0x1f0 / 4, 0x000000ff ) );
	1349	psxwritebyte( p_n_psxram, n_address, m_ide->ide_controller32_r( space, 0x1f0 / 4, 0x000000ff ) );
1350	1350	n_address++;
1351	1351	n_size--;
1352	1352	}
r23498	r23499
1361	1361	AM_RANGE(0x1f000000, 0x1f1fffff) AM_ROM AM_REGION("roms", 0)
1362	1362	AM_RANGE(0x1f000000, 0x1f000003) AM_WRITENOP
1363	1363	AM_RANGE(0x1f7e8000, 0x1f7e8003) AM_NOP
1364		AM_RANGE(0x1f7e4000, 0x1f7e4fff) AM_DEVREADWRITE_LEGACY("ide", ide_controller32_r, ide_controller32_w )
1365		AM_RANGE(0x1f7f4000, 0x1f7f4fff) AM_DEVREADWRITE_LEGACY("ide", ide_controller32_r, ide_controller32_w )
	1364	AM_RANGE(0x1f7e4000, 0x1f7e4fff) AM_DEVREADWRITE("ide", ide_controller_device, ide_controller32_r, ide_controller32_w )
	1365	AM_RANGE(0x1f7f4000, 0x1f7f4fff) AM_DEVREADWRITE("ide", ide_controller_device, ide_controller32_r, ide_controller32_w )
1366	1366
1367	1367	AM_IMPORT_FROM(zn_map)
1368	1368	ADDRESS_MAP_END
1369	1369
1370	1370	MACHINE_RESET_MEMBER(zn_state,coh1000w)
1371	1371	{
1372		machine().device("ide")->reset();
	1372	m_ide->reset();
1373	1373	}
1374	1374
1375	1375	static MACHINE_CONFIG_DERIVED( coh1000w, zn1_2mb_vram )
r23498	r23499
1876	1876
1877	1877	READ8_MEMBER(zn_state::jdredd_idestat_r)
1878	1878	{
1879		device_t *device = machine().device("ide");
1880		return ide_controller_r( device, 0x1f7, 1 );
	1879	return m_ide->ide_controller_r( 0x1f7, 1 );
1881	1880	}
1882	1881
1883	1882	READ16_MEMBER(zn_state::jdredd_ide_r)
1884	1883	{
1885		device_t *device = machine().device("ide");
1886	1884	UINT16 data = 0;
1887	1885
1888	1886	if( ACCESSING_BITS_0_7 )
1889	1887	{
1890		data |= ide_controller_r( device, 0x1f0 + offset, 1 ) << 0;
	1888	data |= m_ide->ide_controller_r( 0x1f0 + offset, 1 ) << 0;
1891	1889	}
1892	1890	if( ACCESSING_BITS_8_15 )
1893	1891	{
1894		data |= ide_controller_r( device, 0x1f0 + offset, 1 ) << 8;
	1892	data |= m_ide->ide_controller_r( 0x1f0 + offset, 1 ) << 8;
1895	1893	}
1896	1894
1897	1895	return data;
r23498	r23499
1899	1897
1900	1898	WRITE16_MEMBER(zn_state::jdredd_ide_w)
1901	1899	{
1902		device_t *device = machine().device("ide");
1903	1900	if( ACCESSING_BITS_0_7 )
1904	1901	{
1905		ide_controller_w( device, 0x1f0 + offset, 1, data >> 0 );
	1902	m_ide->ide_controller_w( 0x1f0 + offset, 1, data >> 0 );
1906	1903	}
1907	1904	if( ACCESSING_BITS_8_15 )
1908	1905	{
1909		ide_controller_w( device, 0x1f0 + offset, 1, data >> 8 );
	1906	m_ide->ide_controller_w( 0x1f0 + offset, 1, data >> 8 );
1910	1907	}
1911	1908	}
1912	1909
r23498	r23499
1999	1996
2000	1997	MACHINE_RESET_MEMBER(zn_state,jdredd)
2001	1998	{
2002		machine().device("ide")->reset();
	1999	m_ide->reset();
2003	2000	}
2004	2001
2005	2002	static MACHINE_CONFIG_DERIVED( coh1000a, zn1_2mb_vram )

trunk/src/mame/drivers/jaguar.c

r23498	r23499
1089	1089	AM_RANGE(0x04000000, 0x047fffff) AM_RAM AM_SHARE("sharedram")
1090	1090	AM_RANGE(0x04800000, 0x04bfffff) AM_ROMBANK("maingfxbank")
1091	1091	AM_RANGE(0x04c00000, 0x04dfffff) AM_ROMBANK("mainsndbank")
1092		AM_RANGE(0x04e00000, 0x04e003ff) AM_DEVREADWRITE_LEGACY("ide", ide_controller32_r, ide_controller32_w)
	1092	AM_RANGE(0x04e00000, 0x04e003ff) AM_DEVREADWRITE("ide", ide_controller_device, ide_controller32_r, ide_controller32_w)
1093	1093	AM_RANGE(0x04f00000, 0x04f003ff) AM_READWRITE16(tom_regs_r, tom_regs_w, 0xffffffff)
1094	1094	AM_RANGE(0x04f00400, 0x04f007ff) AM_RAM AM_SHARE("gpuclut")
1095	1095	AM_RANGE(0x04f02100, 0x04f021ff) AM_READWRITE(gpuctrl_r, gpuctrl_w)
r23498	r23499
1123	1123	AM_RANGE(0xa40000, 0xa40003) AM_WRITE(eeprom_enable_w)
1124	1124	AM_RANGE(0xb70000, 0xb70003) AM_READWRITE(misc_control_r, misc_control_w)
1125	1125	AM_RANGE(0xc00000, 0xdfffff) AM_ROMBANK("mainsndbank")
1126		AM_RANGE(0xe00000, 0xe003ff) AM_DEVREADWRITE_LEGACY("ide",  ide_controller32_r, ide_controller32_w)
	1126	AM_RANGE(0xe00000, 0xe003ff) AM_DEVREADWRITE("ide", ide_controller_device, ide_controller32_r, ide_controller32_w)
1127	1127	AM_RANGE(0xf00000, 0xf003ff) AM_READWRITE16(tom_regs_r, tom_regs_w, 0xffffffff)
1128	1128	AM_RANGE(0xf00400, 0xf007ff) AM_RAM AM_SHARE("gpuclut")
1129	1129	AM_RANGE(0xf02100, 0xf021ff) AM_READWRITE(gpuctrl_r, gpuctrl_w)
r23498	r23499
1151	1151	AM_RANGE(0x000000, 0x7fffff) AM_RAM AM_SHARE("sharedram")
1152	1152	AM_RANGE(0x800000, 0xbfffff) AM_ROMBANK("gpugfxbank")
1153	1153	AM_RANGE(0xc00000, 0xdfffff) AM_ROMBANK("dspsndbank")
1154		AM_RANGE(0xe00000, 0xe003ff) AM_DEVREADWRITE_LEGACY("ide", ide_controller32_r, ide_controller32_w)
	1154	AM_RANGE(0xe00000, 0xe003ff) AM_DEVREADWRITE("ide", ide_controller_device, ide_controller32_r, ide_controller32_w)
1155	1155	AM_RANGE(0xf00000, 0xf003ff) AM_READWRITE16(tom_regs_r, tom_regs_w, 0xffffffff)
1156	1156	AM_RANGE(0xf00400, 0xf007ff) AM_RAM AM_SHARE("gpuclut")
1157	1157	AM_RANGE(0xf02100, 0xf021ff) AM_READWRITE(gpuctrl_r, gpuctrl_w)

trunk/src/mame/drivers/mediagx.c

r23498	r23499
416	416
417	417	READ32_MEMBER(mediagx_state::ide_r)
418	418	{
419		return ide_controller32_r(m_ide, space, 0x1f0/4 + offset, mem_mask);
	419	return m_ide->ide_controller32_r(space, 0x1f0/4 + offset, mem_mask);
420	420	}
421	421
422	422	WRITE32_MEMBER(mediagx_state::ide_w)
423	423	{
424		ide_controller32_w(m_ide, space, 0x1f0/4 + offset, data, mem_mask);
	424	m_ide->ide_controller32_w(space, 0x1f0/4 + offset, data, mem_mask);
425	425	}
426	426
427	427	READ32_MEMBER(mediagx_state::fdc_r)
428	428	{
429		return ide_controller32_r(m_ide, space, 0x3f0/4 + offset, mem_mask);
	429	return m_ide->ide_controller32_r(space, 0x3f0/4 + offset, mem_mask);
430	430	}
431	431
432	432	WRITE32_MEMBER(mediagx_state::fdc_w)
433	433	{
434		ide_controller32_w(m_ide, space, 0x3f0/4 + offset, data, mem_mask);
	434	m_ide->ide_controller32_w(space, 0x3f0/4 + offset, data, mem_mask);
435	435	}
436	436
437	437

trunk/src/mame/drivers/fruitpc.c

r23498	r23499
67	67
68	68	READ32_MEMBER(fruitpc_state::ide_r)
69	69	{
70		return ide_controller32_r(m_ide, space, 0x1f0/4 + offset, mem_mask);
	70	return m_ide->ide_controller32_r(space, 0x1f0/4 + offset, mem_mask);
71	71	}
72	72
73	73	WRITE32_MEMBER(fruitpc_state::ide_w)
74	74	{
75		ide_controller32_w(m_ide, space, 0x1f0/4 + offset, data, mem_mask);
	75	m_ide->ide_controller32_w(space, 0x1f0/4 + offset, data, mem_mask);
76	76	}
77	77
78	78	READ32_MEMBER(fruitpc_state::fdc_r)
79	79	{
80		return ide_controller32_r(m_ide, space, 0x3f0/4 + offset, mem_mask);
	80	return m_ide->ide_controller32_r(space, 0x3f0/4 + offset, mem_mask);
81	81	}
82	82
83	83	WRITE32_MEMBER(fruitpc_state::fdc_w)
84	84	{
85	85	//mame_printf_debug("FDC: write %08X, %08X, %08X\n", data, offset, mem_mask);
86		ide_controller32_w(m_ide, space, 0x3f0/4 + offset, data, mem_mask);
	86	m_ide->ide_controller32_w(space, 0x3f0/4 + offset, data, mem_mask);
87	87	}
88	88
89	89	static ADDRESS_MAP_START( fruitpc_map, AS_PROGRAM, 32, fruitpc_state )

trunk/src/mame/drivers/viper.c

r23498	r23499
309	309	public:
310	310	viper_state(const machine_config &mconfig, device_type type, const char *tag)
311	311	: driver_device(mconfig, type, tag),
312		m_maincpu(*this, "maincpu") { }
	312	m_maincpu(*this, "maincpu"),
	313	m_ide(*this, "ide")
	314	{
	315	}
313	316
314
315	317	UINT32 m_epic_iack;
316	318	int m_cf_card_ide;
317	319	int m_unk1_bit;
r23498	r23499
361	363	int ds2430_insert_cmd_bit(int bit);
362	364	void DS2430_w(int bit);
363	365	required_device<cpu_device> m_maincpu;
	366	required_device<ide_controller_device> m_ide;
364	367	};
365	368
366	369	UINT32 viper_state::screen_update_viper(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
r23498	r23499
1255	1258
1256	1259	READ64_MEMBER(viper_state::cf_card_data_r)
1257	1260	{
1258		device_t *device = machine().device("ide");
1259	1261	UINT64 r = 0;
1260	1262
1261	1263	if (ACCESSING_BITS_16_31)
r23498	r23499
1264	1266	{
1265	1267	case 0x8:   // Duplicate Even RD Data
1266	1268	{
1267		r |= ide_bus_r(device, 0, 0) << 16;
	1269	r |= m_ide->ide_bus_r(0, 0) << 16;
1268	1270	break;
1269	1271	}
1270	1272
r23498	r23499
1279	1281
1280	1282	WRITE64_MEMBER(viper_state::cf_card_data_w)
1281	1283	{
1282		device_t *device = machine().device("ide");
1283	1284	if (ACCESSING_BITS_16_31)
1284	1285	{
1285	1286	switch (offset & 0xf)
1286	1287	{
1287	1288	case 0x8:   // Duplicate Even RD Data
1288	1289	{
1289		ide_bus_w(device, 0, 0, (data >> 16) & 0xffff);
	1290	m_ide->ide_bus_w(0, 0, (data >> 16) & 0xffff);
1290	1291	break;
1291	1292	}
1292	1293
r23498	r23499
1300	1301
1301	1302	READ64_MEMBER(viper_state::cf_card_r)
1302	1303	{
1303		device_t *device = machine().device("ide");
1304	1304	UINT64 r = 0;
1305	1305
1306	1306	if (ACCESSING_BITS_16_31)
r23498	r23499
1318	1318	case 0x6:   // Select Card/Head
1319	1319	case 0x7:   // Status
1320	1320	{
1321		r |= ide_bus_r(device, 0, offset & 7) << 16;
	1321	r |= m_ide->ide_bus_r(0, offset & 7) << 16;
1322	1322	break;
1323	1323	}
1324	1324
r23498	r23499
1327	1327
1328	1328	case 0xd:   // Duplicate Error
1329	1329	{
1330		r |= ide_bus_r(device, 0, 1) << 16;
	1330	r |= m_ide->ide_bus_r(0, 1) << 16;
1331	1331	break;
1332	1332	}
1333	1333	case 0xe:   // Alt Status
1334	1334	case 0xf:   // Drive Address
1335	1335	{
1336		r |= ide_bus_r(device, 1, offset & 7) << 16;
	1336	r |= m_ide->ide_bus_r(1, offset & 7) << 16;
1337	1337	break;
1338	1338	}
1339	1339
r23498	r23499
1364	1364
1365	1365	WRITE64_MEMBER(viper_state::cf_card_w)
1366	1366	{
1367		device_t *device = machine().device("ide");
1368
1369	1367	#ifdef VIPER_DEBUG_LOG
1370	1368	//printf("%s:compact_flash_w: %08X%08X, %08X, %08X%08X\n", machine().describe_context(), (UINT32)(data>>32), (UINT32)(data), offset, (UINT32)(mem_mask >> 32), (UINT32)(mem_mask));
1371	1369	#endif
r23498	r23499
1385	1383	case 0x6:   // Select Card/Head
1386	1384	case 0x7:   // Command
1387	1385	{
1388		ide_bus_w(device, 0, offset & 7, (data >> 16) & 0xffff);
	1386	m_ide->ide_bus_w(0, offset & 7, (data >> 16) & 0xffff);
1389	1387	break;
1390	1388	}
1391	1389
r23498	r23499
1394	1392
1395	1393	case 0xd:   // Duplicate Features
1396	1394	{
1397		ide_bus_w(device, 0, 1, (data >> 16) & 0xffff);
	1395	m_ide->ide_bus_w(0, 1, (data >> 16) & 0xffff);
1398	1396	break;
1399	1397	}
1400	1398	case 0xe:   // Device Ctl
1401	1399	case 0xf:   // Reserved
1402	1400	{
1403		ide_bus_w(device, 1, offset & 7, (data >> 16) & 0xffff);
	1401	m_ide->ide_bus_w(1, offset & 7, (data >> 16) & 0xffff);
1404	1402	break;
1405	1403	}
1406	1404
r23498	r23499
1426	1424	// cylinder low register is set to 0x00
1427	1425	// cylinder high register is set to 0x00
1428	1426
1429		ide_bus_w(device, 1, 6, 0x04);
	1427	m_ide->ide_bus_w(1, 6, 0x04);
1430	1428
1431		ide_bus_w(device, 0, 2, 0x01);
1432		ide_bus_w(device, 0, 3, 0x01);
1433		ide_bus_w(device, 0, 4, 0x00);
1434		ide_bus_w(device, 0, 5, 0x00);
	1429	m_ide->ide_bus_w(0, 2, 0x01);
	1430	m_ide->ide_bus_w(0, 3, 0x01);
	1431	m_ide->ide_bus_w(0, 4, 0x00);
	1432	m_ide->ide_bus_w(0, 5, 0x00);
1435	1433	}
1436	1434	break;
1437	1435	}
r23498	r23499
1457	1455
1458	1456	READ64_MEMBER(viper_state::ata_r)
1459	1457	{
1460		device_t *device = machine().device("ide");
1461	1458	UINT64 r = 0;
1462	1459
1463	1460	if (ACCESSING_BITS_16_31)
1464	1461	{
1465	1462	int reg = (offset >> 4) & 0x7;
1466	1463
1467		r |= ide_bus_r(device, (offset & 0x80) ? 1 : 0, reg) << 16;
	1464	r |= m_ide->ide_bus_r((offset & 0x80) ? 1 : 0, reg) << 16;
1468	1465	}
1469	1466
1470	1467	return r;
r23498	r23499
1472	1469
1473	1470	WRITE64_MEMBER(viper_state::ata_w)
1474	1471	{
1475		device_t *device = machine().device("ide");
1476	1472	if (ACCESSING_BITS_16_31)
1477	1473	{
1478	1474	int reg = (offset >> 4) & 0x7;
1479	1475
1480		ide_bus_w(device, (offset & 0x80) ? 1 : 0, reg, (UINT16)(data >> 16));
	1476	m_ide->ide_bus_w((offset & 0x80) ? 1 : 0, reg, (UINT16)(data >> 16));
1481	1477	}
1482	1478	}
1483	1479
r23498	r23499
2019	2015
2020	2016	void viper_state::machine_reset()
2021	2017	{
2022		ide_controller_device *ide = (ide_controller_device *) machine().device("ide");
2023
2024		ide->reset();
	2018	m_ide->reset();
2025	2019	mpc8240_epic_reset();
2026	2020
2027		UINT8 *ide_features = ide->ide_get_features(0);
	2021	UINT8 *ide_features = m_ide->ide_get_features(0);
2028	2022
2029	2023	// Viper expects these settings or the BIOS fails
2030	2024	ide_features[51*2+0] = 0;           /* 51: PIO data transfer cycle timing mode */

trunk/src/mame/drivers/djmain.c

r23498	r23499
271	271
272	272	//---------
273	273
274		#define IDE_STD_OFFSET  (0x1f0/2)
275		#define IDE_ALT_OFFSET  (0x3f6/2)
276
277	274	READ32_MEMBER(djmain_state::ide_std_r)
278	275	{
279		device_t *device = machine().device("ide");
280	276	if (ACCESSING_BITS_0_7)
281		return ide_controller16_r(device, space, IDE_STD_OFFSET + offset, 0xff00) >> 8;
	277	return m_ide->ide_controller16_r(space, 0x1f0/2 + offset, 0xff00) >> 8;
282	278	else
283		return ide_controller16_r(device, space, IDE_STD_OFFSET + offset, 0xffff) << 16;
	279	return m_ide->ide_controller16_r(space, 0x1f0/2 + offset, 0xffff) << 16;
284	280	}
285	281
286	282	WRITE32_MEMBER(djmain_state::ide_std_w)
287	283	{
288		device_t *device = machine().device("ide");
289	284	if (ACCESSING_BITS_0_7)
290		ide_controller16_w(device, space, IDE_STD_OFFSET + offset, data << 8, 0xff00);
	285	m_ide->ide_controller16_w(space, 0x1f0/2 + offset, data << 8, 0xff00);
291	286	else
292		ide_controller16_w(device, space, IDE_STD_OFFSET + offset, data >> 16, 0xffff);
	287	m_ide->ide_controller16_w(space, 0x1f0/2 + offset, data >> 16, 0xffff);
293	288	}
294	289
295	290
296	291	READ32_MEMBER(djmain_state::ide_alt_r)
297	292	{
298		device_t *device = machine().device("ide");
299	293	if (offset == 0)
300		return ide_controller16_r(device, space, IDE_ALT_OFFSET, 0x00ff) << 24;
	294	return m_ide->ide_controller16_r(space, 0x3f6/2, 0x00ff) << 24;
301	295
302	296	return 0;
303	297	}
304	298
305	299	WRITE32_MEMBER(djmain_state::ide_alt_w)
306	300	{
307		device_t *device = machine().device("ide");
308	301	if (offset == 0 && ACCESSING_BITS_16_23)
309		ide_controller16_w(device, space, IDE_ALT_OFFSET, data >> 24, 0x00ff);
	302	m_ide->ide_controller16_w(space, 0x3f6/2, data >> 24, 0x00ff);
310	303	}
311	304
312	305
r23498	r23499
1395	1388
1396	1389	void djmain_state::machine_start()
1397	1390	{
1398		ide_controller_device *ide = (ide_controller_device *) machine().device("ide");
	1391	if (m_ide_master_password != NULL)
	1392	m_ide->ide_set_master_password(m_ide_master_password);
	1393	if (m_ide_user_password != NULL)
	1394	m_ide->ide_set_user_password(m_ide_user_password);
1399	1395
1400		if (ide != NULL && m_ide_master_password != NULL)
1401		ide->ide_set_master_password(m_ide_master_password);
1402		if (ide != NULL && m_ide_user_password != NULL)
1403		ide->ide_set_user_password(m_ide_user_password);
1404
1405	1396	save_item(NAME(m_sndram_bank));
1406	1397	save_item(NAME(m_pending_vb_int));
1407	1398	save_item(NAME(m_v_ctrl));
r23498	r23499
1418	1409	sndram_set_bank();
1419	1410
1420	1411	/* reset the IDE controller */
1421		machine().device("ide")->reset();
	1412	m_ide->reset();
1422	1413
1423	1414	/* reset LEDs */
1424	1415	set_led_status(machine(), 0, 1);

trunk/src/mame/drivers/voyager.c

r23498	r23499
49	49
50	50	READ32_MEMBER(voyager_state::ide_r)
51	51	{
52		return ide_controller32_r(m_ide, space, 0x1f0/4 + offset, mem_mask);
	52	return m_ide->ide_controller32_r(space, 0x1f0/4 + offset, mem_mask);
53	53	}
54	54
55	55	WRITE32_MEMBER(voyager_state::ide_w)
56	56	{
57		ide_controller32_w(m_ide, space, 0x1f0/4 + offset, data, mem_mask);
	57	m_ide->ide_controller32_w(space, 0x1f0/4 + offset, data, mem_mask);
58	58	}
59	59
60	60	READ32_MEMBER(voyager_state::fdc_r)
61	61	{
62		return ide_controller32_r(m_ide, space, 0x3f0/4 + offset, mem_mask);
	62	return m_ide->ide_controller32_r(space, 0x3f0/4 + offset, mem_mask);
63	63	}
64	64
65	65	WRITE32_MEMBER(voyager_state::fdc_w)
66	66	{
67	67	//mame_printf_debug("FDC: write %08X, %08X, %08X\n", data, offset, mem_mask);
68		ide_controller32_w(m_ide, space, 0x3f0/4 + offset, data, mem_mask);
	68	m_ide->ide_controller32_w(space, 0x3f0/4 + offset, data, mem_mask);
69	69	}
70	70
71	71

trunk/src/mame/drivers/kinst.c

r23498	r23499
150	150	m_rambase2(*this, "rambase2"),
151	151	m_control(*this, "control"),
152	152	m_rombase(*this, "rombase"),
153		m_maincpu(*this, "maincpu") { }
	153	m_maincpu(*this, "maincpu"),
	154	m_ide(*this, "ide" )
	155	{
	156	}
154	157
155	158	required_shared_ptr<UINT32> m_rambase;
156	159	required_shared_ptr<UINT32> m_rambase2;
r23498	r23499
172	175	UINT32 screen_update_kinst(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
173	176	INTERRUPT_GEN_MEMBER(irq0_start);
174	177	required_device<cpu_device> m_maincpu;
	178	required_device<ide_controller_device> m_ide;
175	179
176	180	protected:
177	181	virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
r23498	r23499
211	215
212	216	void kinst_state::machine_reset()
213	217	{
214		ide_controller_device *ide = (ide_controller_device *) machine().device("ide");
215		UINT8 *features = ide->ide_get_features(0);
	218	UINT8 *features = m_ide->ide_get_features(0);
216	219
217	220	if (strncmp(machine().system().name, "kinst2", 6) != 0)
218	221	{
r23498	r23499
322	325
323	326	READ32_MEMBER(kinst_state::kinst_ide_r)
324	327	{
325		device_t *device = machine().device("ide");
326		return midway_ide_asic_r(device, space, offset / 2, mem_mask);
	328	return midway_ide_asic_r(m_ide, space, offset / 2, mem_mask);
327	329	}
328	330
329	331
330	332	WRITE32_MEMBER(kinst_state::kinst_ide_w)
331	333	{
332		device_t *device = machine().device("ide");
333		midway_ide_asic_w(device, space, offset / 2, data, mem_mask);
	334	midway_ide_asic_w(m_ide, space, offset / 2, data, mem_mask);
334	335	}
335	336
336	337
337	338	READ32_MEMBER(kinst_state::kinst_ide_extra_r)
338	339	{
339		device_t *device = machine().device("ide");
340		return ide_controller32_r(device, space, 0x3f6/4, 0x00ff0000) >> 16;
	340	return m_ide->ide_controller32_r(space, 0x3f6/4, 0x00ff0000) >> 16;
341	341	}
342	342
343	343
344	344	WRITE32_MEMBER(kinst_state::kinst_ide_extra_w)
345	345	{
346		device_t *device = machine().device("ide");
347		ide_controller32_w(device, space, 0x3f6/4, data << 16, 0x00ff0000);
	346	m_ide->ide_controller32_w(space, 0x3f6/4, data << 16, 0x00ff0000);
348	347	}
349	348
350	349

trunk/src/mame/drivers/savquest.c

r23498	r23499
537	537
538	538	READ32_MEMBER(savquest_state::ide_r)
539	539	{
540		return ide_controller32_r(m_ide, space, 0x1f0/4 + offset, mem_mask);
	540	return m_ide->ide_controller32_r(space, 0x1f0/4 + offset, mem_mask);
541	541	}
542	542
543	543	WRITE32_MEMBER(savquest_state::ide_w)
544	544	{
545		ide_controller32_w(m_ide, space, 0x1f0/4 + offset, data, mem_mask);
	545	m_ide->ide_controller32_w(space, 0x1f0/4 + offset, data, mem_mask);
546	546	}
547	547
548	548	READ32_MEMBER(savquest_state::fdc_r)
549	549	{
550		return ide_controller32_r(m_ide, space, 0x3f0/4 + offset, mem_mask);
	550	return m_ide->ide_controller32_r(space, 0x3f0/4 + offset, mem_mask);
551	551	}
552	552
553	553	WRITE32_MEMBER(savquest_state::fdc_w)
554	554	{
555	555	//mame_printf_debug("FDC: write %08X, %08X, %08X\n", data, offset, mem_mask);
556		ide_controller32_w(m_ide, space, 0x3f0/4 + offset, data, mem_mask);
	556	m_ide->ide_controller32_w(space, 0x3f0/4 + offset, data, mem_mask);
557	557	}
558	558
559	559	static ADDRESS_MAP_START(savquest_map, AS_PROGRAM, 32, savquest_state)

trunk/src/mame/drivers/photoply.c

r23498	r23499
40	40
41	41	READ32_MEMBER(photoply_state::ide_r)
42	42	{
43		device_t *device = machine().device("ide");
44		return ide_controller32_r(device, space, 0x1f0/4 + offset, mem_mask);
	43	return m_ide->ide_controller32_r(space, 0x1f0/4 + offset, mem_mask);
45	44	}
46	45
47	46	WRITE32_MEMBER(photoply_state::ide_w)
48	47	{
49		device_t *device = machine().device("ide");
50		ide_controller32_w(device, space, 0x1f0/4 + offset, data, mem_mask);
	48	m_ide->ide_controller32_w(space, 0x1f0/4 + offset, data, mem_mask);
51	49	}
52	50
53	51	READ32_MEMBER(photoply_state::fdc_r)
54	52	{
55		device_t *device = machine().device("ide");
56		return ide_controller32_r(device, space, 0x3f0/4 + offset, mem_mask);
	53	return m_ide->ide_controller32_r(space, 0x3f0/4 + offset, mem_mask);
57	54	}
58	55
59	56	WRITE32_MEMBER(photoply_state::fdc_w)
60	57	{
61		device_t *device = machine().device("ide");
62	58	//mame_printf_debug("FDC: write %08X, %08X, %08X\n", data, offset, mem_mask);
63		ide_controller32_w(device, space, 0x3f0/4 + offset, data, mem_mask);
	59	m_ide->ide_controller32_w(space, 0x3f0/4 + offset, data, mem_mask);
64	60	}
65	61
66	62	static ADDRESS_MAP_START( photoply_map, AS_PROGRAM, 32, photoply_state )

trunk/src/mame/drivers/chihiro.c

r23498	r23499
412	412	struct chihiro_devices {
413	413	pic8259_device    *pic8259_1;
414	414	pic8259_device    *pic8259_2;
415		device_t    *ide;
	415	ide_controller_device *ide;
416	416	} chihiro_devs;
417	417
418	418	nv2a_renderer *nvidia_nv2a;
r23498	r23499
2687	2687
2688	2688	offset *= 4;
2689	2689	size = convert_to_offset_and_size32(&offset, mem_mask);
2690		return ide_controller_r(chihiro_devs.ide, offset+0x01f0, size) << ((offset & 3) * 8);
	2690	return chihiro_devs.ide->ide_controller_r(offset+0x01f0, size) << ((offset & 3) * 8);
2691	2691	}
2692	2692
2693	2693	WRITE32_MEMBER( chihiro_state::ide_w )
r23498	r23499
2697	2697	offset *= 4;
2698	2698	size = convert_to_offset_and_size32(&offset, mem_mask);
2699	2699	data = data >> ((offset & 3) * 8);
2700		ide_controller_w(chihiro_devs.ide, offset+0x01f0, size, data);
	2700	chihiro_devs.ide->ide_controller_w(offset+0x01f0, size, data);
2701	2701	}
2702	2702
2703	2703	// ======================> ide_baseboard_device
r23498	r23499
3003	3003	AM_RANGE(0x0cf8, 0x0cff) AM_DEVREADWRITE("pcibus", pci_bus_legacy_device, read, write)
3004	3004	AM_RANGE(0x8000, 0x80ff) AM_READWRITE(dummy_r, dummy_w)
3005	3005	AM_RANGE(0xc000, 0xc0ff) AM_READWRITE(smbus_r, smbus_w)
3006		AM_RANGE(0xff60, 0xff67) AM_DEVREADWRITE_LEGACY("ide", ide_bus_master32_r, ide_bus_master32_w)
	3006	AM_RANGE(0xff60, 0xff67) AM_DEVREADWRITE("ide", ide_controller_device, ide_bus_master32_r, ide_bus_master32_w)
3007	3007	ADDRESS_MAP_END
3008	3008
3009	3009	static INPUT_PORTS_START( chihiro )
r23498	r23499
3021	3021	m_maincpu->set_irq_acknowledge_callback(device_irq_acknowledge_delegate(FUNC(chihiro_state::irq_callback),this));
3022	3022	chihiro_devs.pic8259_1 = machine().device<pic8259_device>( "pic8259_1" );
3023	3023	chihiro_devs.pic8259_2 = machine().device<pic8259_device>( "pic8259_2" );
3024		chihiro_devs.ide = machine().device( "ide" );
	3024	chihiro_devs.ide = machine().device<ide_controller_device>( "ide" );
3025	3025	if (machine().debug_flags & DEBUG_FLAG_ENABLED)
3026	3026	debug_console_register_command(machine(),"chihiro",CMDFLAG_NONE,0,1,4,chihiro_debug_commands);
3027	3027	}

trunk/src/mame/drivers/midqslvr.c

r23498	r23499
362	362
363	363	READ32_MEMBER(midqslvr_state::ide_r)
364	364	{
365		return ide_controller32_r(m_ide, space, 0x1f0/4 + offset, mem_mask);
	365	return m_ide->ide_controller32_r(space, 0x1f0/4 + offset, mem_mask);
366	366	}
367	367
368	368	WRITE32_MEMBER(midqslvr_state::ide_w)
369	369	{
370		ide_controller32_w(m_ide, space, 0x1f0/4 + offset, data, mem_mask);
	370	m_ide->ide_controller32_w(space, 0x1f0/4 + offset, data, mem_mask);
371	371	}
372	372
373	373	READ32_MEMBER(midqslvr_state::fdc_r)
374	374	{
375		return ide_controller32_r(m_ide, space, 0x3f0/4 + offset, mem_mask);
	375	return m_ide->ide_controller32_r(space, 0x3f0/4 + offset, mem_mask);
376	376	}
377	377
378	378	WRITE32_MEMBER(midqslvr_state::fdc_w)
379	379	{
380	380	//mame_printf_debug("FDC: write %08X, %08X, %08X\n", data, offset, mem_mask);
381		ide_controller32_w(m_ide, space, 0x3f0/4 + offset, data, mem_mask);
	381	m_ide->ide_controller32_w(space, 0x3f0/4 + offset, data, mem_mask);
382	382	}
383	383
384	384	static ADDRESS_MAP_START(midqslvr_map, AS_PROGRAM, 32, midqslvr_state)

trunk/src/mame/drivers/calchase.c

r23498	r23499
376	376
377	377	READ32_MEMBER(calchase_state::ide_r)
378	378	{
379		return ide_controller32_r(m_ide, space, 0x1f0/4 + offset, mem_mask);
	379	return m_ide->ide_controller32_r(space, 0x1f0/4 + offset, mem_mask);
380	380	}
381	381
382	382	WRITE32_MEMBER(calchase_state::ide_w)
383	383	{
384		ide_controller32_w(m_ide, space, 0x1f0/4 + offset, data, mem_mask);
	384	m_ide->ide_controller32_w(space, 0x1f0/4 + offset, data, mem_mask);
385	385	}
386	386
387	387	READ32_MEMBER(calchase_state::fdc_r)
388	388	{
389		return ide_controller32_r(m_ide, space, 0x3f0/4 + offset, mem_mask);
	389	return m_ide->ide_controller32_r(space, 0x3f0/4 + offset, mem_mask);
390	390	}
391	391
392	392	WRITE32_MEMBER(calchase_state::fdc_w)
393	393	{
394	394	//mame_printf_debug("FDC: write %08X, %08X, %08X\n", data, offset, mem_mask);
395		ide_controller32_w(m_ide, space, 0x3f0/4 + offset, data, mem_mask);
	395	m_ide->ide_controller32_w(space, 0x3f0/4 + offset, data, mem_mask);
396	396	}
397	397
398	398	static ADDRESS_MAP_START( calchase_map, AS_PROGRAM, 32, calchase_state )

trunk/src/mame/drivers/queen.c

r23498	r23499
232	232
233	233	READ32_MEMBER(queen_state::ide_r)
234	234	{
235		return ide_controller32_r(m_ide, space, 0x1f0/4 + offset, mem_mask);
	235	return m_ide->ide_controller32_r(space, 0x1f0/4 + offset, mem_mask);
236	236	}
237	237
238	238	WRITE32_MEMBER(queen_state::ide_w)
239	239	{
240		ide_controller32_w(m_ide, space, 0x1f0/4 + offset, data, mem_mask);
	240	m_ide->ide_controller32_w(space, 0x1f0/4 + offset, data, mem_mask);
241	241	}
242	242
243	243	READ32_MEMBER(queen_state::fdc_r)
244	244	{
245		return ide_controller32_r(m_ide, space, 0x3f0/4 + offset, mem_mask);
	245	return m_ide->ide_controller32_r(space, 0x3f0/4 + offset, mem_mask);
246	246	}
247	247
248	248	WRITE32_MEMBER(queen_state::fdc_w)
249	249	{
250	250	//mame_printf_debug("FDC: write %08X, %08X, %08X\n", data, offset, mem_mask);
251		ide_controller32_w(m_ide, space, 0x3f0/4 + offset, data, mem_mask);
	251	m_ide->ide_controller32_w(space, 0x3f0/4 + offset, data, mem_mask);
252	252	}
253	253
254	254	static ADDRESS_MAP_START( queen_map, AS_PROGRAM, 32, queen_state )

trunk/src/mame/drivers/taitotz.c

r23498	r23499
566	566	m_maincpu(*this, "maincpu"),
567	567	m_iocpu(*this, "iocpu"),
568	568	m_work_ram(*this, "work_ram"),
569		m_mbox_ram(*this, "mbox_ram") { }
	569	m_mbox_ram(*this, "mbox_ram"),
	570	m_ide(*this, "ide")
	571	{
	572	}
570	573
571	574	required_device<cpu_device> m_maincpu;
572	575	required_device<cpu_device> m_iocpu;
573	576	required_shared_ptr<UINT64> m_work_ram;
574	577	required_shared_ptr<UINT8>  m_mbox_ram;
	578	required_device<ide_controller_device> m_ide;
575	579
576	580	DECLARE_READ64_MEMBER(ppc_common_r);
577	581	DECLARE_WRITE64_MEMBER(ppc_common_w);
r23498	r23499
2105	2109
2106	2110	READ8_MEMBER(taitotz_state::tlcs_ide0_r)
2107	2111	{
2108		device_t *device = machine().device("ide");
2109	2112	static UINT16 ide_reg_latch;
2110	2113	int reg = offset >> 1;
2111	2114
r23498	r23499
2113	2116	{
2114	2117	if ((offset & 1) == 0)
2115	2118	{
2116		ide_reg_latch = ide_bus_r(device, 0, reg);
	2119	ide_reg_latch = m_ide->ide_bus_r(0, reg);
2117	2120	return (ide_reg_latch & 0xff);
2118	2121	}
2119	2122	else
r23498	r23499
2126	2129	if (offset & 1)
2127	2130	fatalerror("tlcs_ide0_r: %02X, odd offset\n", offset);
2128	2131
2129		UINT8 d = ide_bus_r(device, 0, reg);
	2132	UINT8 d = m_ide->ide_bus_r(0, reg);
2130	2133	if (reg == 7)
2131	2134	d &= ~0x2;      // Type Zero doesn't like the index bit. It's defined as vendor-specific, so it probably shouldn't be up...
2132	2135	// The status check explicitly checks for 0x50 (drive ready, seek complete).
r23498	r23499
2136	2139
2137	2140	WRITE8_MEMBER(taitotz_state::tlcs_ide0_w)
2138	2141	{
2139		device_t *device = machine().device("ide");
2140	2142	static UINT16 ide_reg_latch;
2141	2143	int reg = offset >> 1;
2142	2144
r23498	r23499
2151	2153	{
2152	2154	ide_reg_latch &= 0x00ff;
2153	2155	ide_reg_latch |= (UINT16)(data) << 8;
2154		ide_bus_w(device, 0, reg, ide_reg_latch);
	2156	m_ide->ide_bus_w(0, reg, ide_reg_latch);
2155	2157	}
2156	2158	}
2157	2159	else
2158	2160	{
2159	2161	if (offset & 1)
2160	2162	fatalerror("tlcs_ide0_w: %02X, %02X, odd offset\n", offset, data);
2161		ide_bus_w(device, 0, reg, data);
	2163	m_ide->ide_bus_w(0, reg, data);
2162	2164	}
2163	2165	}
2164	2166
2165	2167	READ8_MEMBER(taitotz_state::tlcs_ide1_r)
2166	2168	{
2167		device_t *device = machine().device("ide");
2168	2169	//static UINT16 ide_reg_latch;
2169	2170	int reg = offset >> 1;
2170	2171
r23498	r23499
2173	2174
2174	2175	if ((offset & 1) == 0)
2175	2176	{
2176		UINT8 d = ide_bus_r(device, 1, reg);
	2177	UINT8 d = m_ide->ide_bus_r(1, reg);
2177	2178	d &= ~0x2;      // Type Zero doesn't like the index bit. It's defined as vendor-specific, so it probably shouldn't be up...
2178	2179	// The status check explicitly checks for 0x50 (drive ready, seek complete).
2179	2180	return d;
r23498	r23499
2181	2182	else
2182	2183	{
2183	2184	//fatalerror("tlcs_ide1_r: %02X, odd offset\n", offset);
2184		UINT8 d = ide_bus_r(device, 1, reg);
	2185	UINT8 d = m_ide->ide_bus_r(1, reg);
2185	2186	d &= ~0x2;
2186	2187	return d;
2187	2188	}
r23498	r23499
2189	2190
2190	2191	WRITE8_MEMBER(taitotz_state::tlcs_ide1_w)
2191	2192	{
2192		device_t *device = machine().device("ide");
2193	2193	static UINT16 ide_reg_latch;
2194	2194	int reg = offset >> 1;
2195	2195
r23498	r23499
2205	2205	{
2206	2206	ide_reg_latch &= 0x00ff;
2207	2207	ide_reg_latch |= (UINT16)(data) << 16;
2208		ide_bus_w(device, 1, reg, ide_reg_latch);
	2208	m_ide->ide_bus_w(1, reg, ide_reg_latch);
2209	2209	}
2210	2210	}
2211	2211
r23498	r23499
2541	2541
2542	2542	void taitotz_state::machine_reset()
2543	2543	{
2544		machine().device("ide")->reset();
2545
2546	2544	if (m_hdd_serial_number != NULL)
2547	2545	{
2548		set_ide_drive_serial_number(machine().device("ide"), 0, m_hdd_serial_number);
	2546	set_ide_drive_serial_number(m_ide, 0, m_hdd_serial_number);
2549	2547	}
2550	2548	}
2551	2549

trunk/src/mame/drivers/twinkle.c

r23498	r23499
247	247	: driver_device(mconfig, type, tag),
248	248	m_am53cf96(*this, "scsi:am53cf96"),
249	249	m_maincpu(*this, "maincpu"),
250		m_audiocpu(*this, "audiocpu") { }
	250	m_audiocpu(*this, "audiocpu"),
	251	m_ide(*this, "ide")
	252	{
	253	}
251	254
252	255	required_device<am53cf96_device> m_am53cf96;
253	256
r23498	r23499
276	279	DECLARE_DRIVER_INIT(twinkle);
277	280	required_device<cpu_device> m_maincpu;
278	281	required_device<cpu_device> m_audiocpu;
	282	required_device<ide_controller_device> m_ide;
279	283	};
280	284
281	285	/* RTC */
r23498	r23499
645	649
646	650	READ16_MEMBER(twinkle_state::twinkle_ide_r)
647	651	{
648		device_t *device = machine().device("ide");
649	652	if (offset == 0)
650	653	{
651		return ide_controller_r(device, offset+0x1f0, 2);
	654	return m_ide->ide_controller_r(0x1f0 + offset, 2);
652	655	}
653	656	else
654	657	{
655		return ide_controller_r(device, offset+0x1f0, 1);
	658	return m_ide->ide_controller_r(0x1f0 + offset, 1);
656	659	}
657	660	}
658	661
659	662	WRITE16_MEMBER(twinkle_state::twinkle_ide_w)
660	663	{
661		device_t *device = machine().device("ide");
662		ide_controller_w(device, offset+0x1f0, 1, data);
	664	m_ide->ide_controller_w(0x1f0 + offset, 1, data);
663	665	}
664	666
665	667	/*

trunk/src/mame/drivers/cobra.c

r23498	r23499
608	608	m_subcpu(*this, "subcpu"),
609	609	m_gfxcpu(*this, "gfxcpu"),
610	610	m_gfx_pagetable(*this, "pagetable"),
611		m_k001604(*this, "k001604")
	611	m_k001604(*this, "k001604"),
	612	m_ide(*this, "ide")
612	613	{ }
613	614
614	615	required_device<cpu_device> m_maincpu;
r23498	r23499
616	617	required_device<cpu_device> m_gfxcpu;
617	618	required_shared_ptr<UINT64> m_gfx_pagetable;
618	619	required_device<k001604_device> m_k001604;
	620	required_device<ide_controller_device> m_ide;
619	621
620	622	DECLARE_READ64_MEMBER(main_comram_r);
621	623	DECLARE_WRITE64_MEMBER(main_comram_w);
r23498	r23499
1814	1816
1815	1817	READ32_MEMBER(cobra_state::sub_ata0_r)
1816	1818	{
1817		device_t *device = machine().device("ide");
1818	1819	UINT32 r = 0;
1819	1820
1820	1821	if (ACCESSING_BITS_16_31)
1821	1822	{
1822		UINT16 v = ide_bus_r(device, 0, (offset << 1) + 0);
	1823	UINT16 v = m_ide->ide_bus_r(0, (offset << 1) + 0);
1823	1824	r |= ((v << 8) | (v >> 8)) << 16;
1824	1825	}
1825	1826	if (ACCESSING_BITS_0_15)
1826	1827	{
1827		UINT16 v = ide_bus_r(device, 0, (offset << 1) + 1);
	1828	UINT16 v = m_ide->ide_bus_r(0, (offset << 1) + 1);
1828	1829	r |= ((v << 8) | (v >> 8)) << 0;
1829	1830	}
1830	1831
r23498	r23499
1833	1834
1834	1835	WRITE32_MEMBER(cobra_state::sub_ata0_w)
1835	1836	{
1836		device_t *device = machine().device("ide");
1837
1838	1837	if (ACCESSING_BITS_16_31)
1839	1838	{
1840	1839	UINT16 d = ((data >> 24) & 0xff) | ((data >> 8) & 0xff00);
1841		ide_bus_w(device, 0, (offset << 1) + 0, d);
	1840	m_ide->ide_bus_w(0, (offset << 1) + 0, d);
1842	1841	}
1843	1842	if (ACCESSING_BITS_0_15)
1844	1843	{
1845	1844	UINT16 d = ((data >> 8) & 0xff) | ((data << 8) & 0xff00);
1846		ide_bus_w(device, 0, (offset << 1) + 1, d);
	1845	m_ide->ide_bus_w(0, (offset << 1) + 1, d);
1847	1846	}
1848	1847	}
1849	1848
1850	1849	READ32_MEMBER(cobra_state::sub_ata1_r)
1851	1850	{
1852		device_t *device = machine().device("ide");
1853	1851	UINT32 r = 0;
1854	1852
1855	1853	if (ACCESSING_BITS_16_31)
1856	1854	{
1857		UINT16 v = ide_bus_r(device, 1, (offset << 1) + 0);
	1855	UINT16 v = m_ide->ide_bus_r(1, (offset << 1) + 0);
1858	1856	r |= ((v << 8) | (v >> 8)) << 16;
1859	1857	}
1860	1858	if (ACCESSING_BITS_0_15)
1861	1859	{
1862		UINT16 v = ide_bus_r(device, 1, (offset << 1) + 1);
	1860	UINT16 v = m_ide->ide_bus_r(1, (offset << 1) + 1);
1863	1861	r |= ((v << 8) | (v >> 8)) << 0;
1864	1862	}
1865	1863
r23498	r23499
1868	1866
1869	1867	WRITE32_MEMBER(cobra_state::sub_ata1_w)
1870	1868	{
1871		device_t *device = machine().device("ide");
1872
1873	1869	if (ACCESSING_BITS_16_31)
1874	1870	{
1875	1871	UINT16 d = ((data >> 24) & 0xff) | ((data >> 8) & 0xff00);
1876		ide_bus_w(device, 1, (offset << 1) + 0, d);
	1872	m_ide->ide_bus_w(1, (offset << 1) + 0, d);
1877	1873	}
1878	1874	if (ACCESSING_BITS_0_15)
1879	1875	{
1880	1876	UINT16 d = ((data >> 8) & 0xff) | ((data << 8) & 0xff00);
1881		ide_bus_w(device, 1, (offset << 1) + 1, d);
	1877	m_ide->ide_bus_w(1, (offset << 1) + 1, d);
1882	1878	}
1883	1879	}
1884	1880
r23498	r23499
3195	3191	{
3196	3192	m_sub_interrupt = 0xff;
3197	3193
3198		ide_controller_device *ide = (ide_controller_device *) machine().device("ide");
3199		UINT8 *ide_features = ide->ide_get_features(0);
	3194	UINT8 *ide_features = m_ide->ide_get_features(0);
3200	3195
3201	3196	// Cobra expects these settings or the BIOS fails
3202	3197	ide_features[51*2+0] = 0;           /* 51: PIO data transfer cycle timing mode */

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