trunk/src/emu/machine/mcf5206e.c
| r22648 | r22649 | |
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| 59 | 59 | AM_RANGE(0x1e4, 0x1e7) AM_READWRITE8(MFDR_r, MFDR_w, 0xffffffff) |
| 60 | 60 | AM_RANGE(0x1e8, 0x1eb) AM_READWRITE8(MBCR_r, MBCR_w, 0xffffffff) |
| 61 | 61 | AM_RANGE(0x1ec, 0x1ef) AM_READWRITE8(MBSR_r, MBSR_w, 0xffffffff) |
| 62 | AM_RANGE(0x1f0, 0x1f3) AM_READWRITE8(MBDR_r, MBDR_w, 0xffffffff) |
| 62 | 63 | ADDRESS_MAP_END |
| 63 | 64 | |
| 64 | 65 | |
| r22648 | r22649 | |
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| 528 | 529 | |
| 529 | 530 | READ8_MEMBER( mcf5206e_peripheral_device::MBSR_r) |
| 530 | 531 | { |
| 531 | | static int hack = 0x00; |
| 532 | int hack = 0x00; |
| 532 | 533 | |
| 533 | 534 | switch (offset) |
| 534 | 535 | { |
| r22648 | r22649 | |
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| 536 | 537 | { |
| 537 | 538 | hack ^= (machine().rand()&0xff); |
| 538 | 539 | debuglog("%s: MBSR_r\n", this->machine().describe_context()); |
| 539 | | return m_MBSR | hack; // will loop on this after a while |
| 540 | return m_MBSR ^ hack; // will loop on this after a while |
| 540 | 541 | } |
| 541 | 542 | case 1: |
| 542 | 543 | case 2: |
| r22648 | r22649 | |
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| 567 | 568 | |
| 568 | 569 | |
| 569 | 570 | |
| 571 | |
| 572 | READ8_MEMBER( mcf5206e_peripheral_device::MBDR_r) |
| 573 | { |
| 574 | int hack = 0x00; |
| 575 | |
| 576 | switch (offset) |
| 577 | { |
| 578 | case 0: |
| 579 | { |
| 580 | hack ^= (machine().rand()&0xff); |
| 581 | debuglog("%s: MBDR_r\n", this->machine().describe_context()); |
| 582 | return m_MBDR ^ hack; |
| 583 | } |
| 584 | case 1: |
| 585 | case 2: |
| 586 | case 3: |
| 587 | debuglog("%s: invalid MBDR_r %d\n", this->machine().describe_context(), offset); |
| 588 | return 0; |
| 589 | } |
| 590 | |
| 591 | return 0; |
| 592 | } |
| 593 | |
| 594 | WRITE8_MEMBER( mcf5206e_peripheral_device::MBDR_w) |
| 595 | { |
| 596 | switch (offset) |
| 597 | { |
| 598 | case 0: |
| 599 | m_MBDR = data; |
| 600 | debuglog("%s: MBDR_w %02x\n", this->machine().describe_context(), data); |
| 601 | break; |
| 602 | case 1: |
| 603 | case 2: |
| 604 | case 3: |
| 605 | debuglog("%s: invalid MBDR_w %d, %02x\n", this->machine().describe_context(), offset, data); |
| 606 | break; |
| 607 | |
| 608 | } |
| 609 | } |
| 610 | |
| 611 | |
| 612 | |
| 570 | 613 | READ16_MEMBER( mcf5206e_peripheral_device::IMR_r) |
| 571 | 614 | { |
| 572 | 615 | switch (offset) |
| r22648 | r22649 | |
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| 614 | 657 | // technically we should do the vector check in the IRQ callback as well as various checks based on the IRQ masks before asserting the interrupt |
| 615 | 658 | if (ICR & 0x80) // AVEC |
| 616 | 659 | { |
| 617 | | m_cpu->set_input_line((ICR&0x1c)>>2, HOLD_LINE); |
| 660 | if (!(m_IMR & 0x0200)) m_cpu->set_input_line((ICR&0x1c)>>2, HOLD_LINE); |
| 618 | 661 | } |
| 619 | 662 | |
| 620 | 663 | debuglog("timer1_callback\n"); |
| r22648 | r22649 | |
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| 903 | 946 | |
| 904 | 947 | m_IMR = 0x3FFE; |
| 905 | 948 | |
| 949 | m_MFDR = 0x00; |
| 906 | 950 | m_MBCR = 0x00; |
| 907 | 951 | m_MBSR = 0x00; |
| 952 | m_MBDR = 0x00; |
| 908 | 953 | } |
| 909 | 954 | |
| 910 | 955 | /* |
| r22648 | r22649 | |
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| 1025 | 1070 | $1E4*- MFDR 8 M-Bus Frequency Divider Register 00 R/W |
| 1026 | 1071 | $1E8*- MBCR 8 M-Bus Control Register 00 R/W |
| 1027 | 1072 | $1EC*- MBSR 8 M-Bus Status Register 00 R/W |
| 1028 | | $1F0 MBDR 8 M-Bus Data I/O Register 00 R/W |
| 1073 | $1F0*- MBDR 8 M-Bus Data I/O Register 00 R/W |
| 1029 | 1074 | ------------ DMA Controller ----------- |
| 1030 | 1075 | $200 DMASAR0 32 Source Address Register 0 00 R/W |
| 1031 | 1076 | $204 DMADAR0 32 Destination Address Register 0 00 R/W |