MAME SVN History

199869 Revisions

r21565 Monday 4th March, 2013 at 13:29:33 UTC by Nathan Woods
Rewrite of 6809/6309/konamicpu cores. 6809 should be cycle exact based on the 6809 datasheet. Inferred 6309 cycle exact timings. Not sure about the Konami timings; they are definitly different from the previous core but the previous timings were a guess. Get ready for regressions...

[src/emu]	emucore.h
[src/emu/cpu]	cpu.mak ~~hd6309~~
[src/emu/cpu/konami]	~~knmidasm.c~~ ~~konami.c~~ ~~konami.h~~
[src/emu/cpu/m6809]	6309dasm.c* 6809dasm.c ~~6809ops.c~~ ~~6809tbl.c~~ ~~6809tbl.h~~ base6x09.ops* hd6309.c* hd6309.h* hd6309.ops* knmidasm.c* konami.c* konami.h* konami.ops* m6809.c m6809.h m6809.ops* m6809inl.h* m6809make.py*
[src/mame/drivers]	88games.c ajax.c aliens.c battlnts.c bladestl.c blockhl.c chinagat.c chqflag.c combatsc.c contra.c crimfght.c ddragon.c dec8.c fastlane.c flkatck.c gbusters.c hcastle.c itech8.c labyrunr.c lethal.c mainevt.c parodius.c rockrage.c rollerg.c simpsons.c surpratk.c thunderx.c vendetta.c
[src/mame/machine]	ajax.c simpsons.c
[src/mess/drivers]	coco3.c

trunk/src/mame/drivers/surpratk.c
r21564	r21565
9	9	***************************************************************************/
10	10
11	11	#include "emu.h"
12		#include "cpu/~~kona~~mi/konami.h" /* for the callback and the firq irq definition */
	12	#include "cpu/m6809/konami.h" /* for the callback and the firq irq definition */
13	13	#include "video/konicdev.h"
14	14	#include "sound/2151intf.h"
15	15	#include "includes/konamipt.h"

trunk/src/mame/drivers/88games.c
r21564	r21565
5	5	***************************************************************************/
6	6
7	7	#include "emu.h"
8		#include "cpu/~~kona~~mi/konami.h"
	8	#include "cpu/m6809/konami.h"
9	9	#include "cpu/z80/z80.h"
10	10	#include "video/konicdev.h"
11	11	#include "sound/2151intf.h"

trunk/src/mame/drivers/gbusters.c
r21564	r21565
9	9
10	10	#include "emu.h"
11	11	#include "cpu/z80/z80.h"
12		#include "cpu/~~kona~~mi/konami.h" /* for the callback and the firq irq definition */
	12	#include "cpu/m6809/konami.h" /* for the callback and the firq irq definition */
13	13	#include "video/konicdev.h"
14	14	#include "sound/2151intf.h"
15	15	#include "sound/k007232.h"

trunk/src/mame/drivers/thunderx.c
r21564	r21565
14	14
15	15	#include "emu.h"
16	16	#include "cpu/z80/z80.h"
17		#include "cpu/~~kona~~mi/konami.h" /* for the callback and the firq irq definition */
	17	#include "cpu/m6809/konami.h" /* for the callback and the firq irq definition */
18	18	#include "video/konicdev.h"
19	19	#include "sound/2151intf.h"
20	20	#include "sound/k007232.h"

trunk/src/mame/drivers/mainevt.c
r21564	r21565
22	22
23	23	#include "emu.h"
24	24	#include "cpu/z80/z80.h"
25		#include "cpu/hd6309/hd6309.h"
	25	#include "cpu/m6809/hd6309.h"
26	26	#include "video/konicdev.h"
27	27	#include "cpu/m6809/m6809.h"
28	28	#include "sound/2151intf.h"

trunk/src/mame/drivers/itech8.c
r21564	r21565
497	497	#include "emu.h"
498	498	#include "cpu/z80/z80.h"
499	499	#include "cpu/m68000/m68000.h"
500		#include "cpu/hd6309/hd6309.h"
	500	#include "cpu/m6809/hd6309.h"
501	501	#include "cpu/m6809/m6809.h"
502	502	#include "machine/6821pia.h"
503	503	#include "machine/6522via.h"

trunk/src/mame/drivers/battlnts.c
r21564	r21565
11	11	***************************************************************************/
12	12
13	13	#include "emu.h"
14		#include "cpu/hd6309/hd6309.h"
	14	#include "cpu/m6809/hd6309.h"
15	15	#include "cpu/z80/z80.h"
16	16	#include "sound/3812intf.h"
17	17	#include "video/konicdev.h"

trunk/src/mame/drivers/ddragon.c
r21564	r21565
69	69	***************************************************************************/
70	70
71	71	#include "emu.h"
72		#include "cpu/hd6309/hd6309.h"
	72	#include "cpu/m6809/hd6309.h"
73	73	#include "cpu/m6800/m6800.h"
74	74	#include "cpu/m6805/m6805.h"
75	75	#include "cpu/m6809/m6809.h"

trunk/src/mame/drivers/simpsons.c
r21564	r21565
67	67	***************************************************************************/
68	68
69	69	#include "emu.h"
70		#include "cpu/~~kona~~mi/konami.h" /* for the callback and the firq irq definition */
	70	#include "cpu/m6809/konami.h" /* for the callback and the firq irq definition */
71	71	#include "cpu/z80/z80.h"
72	72	#include "video/konicdev.h"
73	73	#include "machine/eeprom.h"

trunk/src/mame/drivers/chqflag.c
r21564	r21565
14	14
15	15	#include "emu.h"
16	16	#include "cpu/z80/z80.h"
17		#include "cpu/~~kona~~mi/konami.h"
	17	#include "cpu/m6809/konami.h"
18	18	#include "video/konicdev.h"
19	19	#include "sound/2151intf.h"
20	20	#include "sound/k007232.h"

trunk/src/mame/drivers/dec8.c
r21564	r21565
40	40	***************************************************************************/
41	41
42	42	#include "emu.h"
43		#include "cpu/hd6309/hd6309.h"
	43	#include "cpu/m6809/hd6309.h"
44	44	#include "cpu/m6809/m6809.h"
45	45	#include "cpu/m6502/m6502.h"
46	46	#include "cpu/mcs51/mcs51.h"

trunk/src/mame/drivers/ajax.c
r21564	r21565
13	13	#include "emu.h"
14	14	#include "cpu/z80/z80.h"
15	15	#include "cpu/m6809/m6809.h"
16		#include "cpu/~~kona~~mi/konami.h"
	16	#include "cpu/m6809/konami.h"
17	17	#include "video/konicdev.h"
18	18	#include "sound/2151intf.h"
19	19	#include "sound/k007232.h"

trunk/src/mame/drivers/lethal.c
r21564	r21565
161	161	#include "emu.h"
162	162	#include "video/konicdev.h"
163	163	#include "cpu/m6809/m6809.h"
164		#include "cpu/hd6309/hd6309.h"
	164	#include "cpu/m6809/hd6309.h"
165	165	#include "cpu/z80/z80.h"
166	166	#include "machine/eeprom.h"
167	167	#include "sound/k054539.h"

trunk/src/mame/drivers/bladestl.c
r21564	r21565
28	28
29	29	#include "emu.h"
30	30	#include "cpu/m6809/m6809.h"
31		#include "cpu/hd6309/hd6309.h"
	31	#include "cpu/m6809/hd6309.h"
32	32	#include "sound/2203intf.h"
33	33	#include "sound/upd7759.h"
34	34	#include "video/konicdev.h"

trunk/src/mame/drivers/contra.c
r21564	r21565
17	17	***************************************************************************/
18	18
19	19	#include "emu.h"
20		#include "cpu/hd6309/hd6309.h"
	20	#include "cpu/m6809/hd6309.h"
21	21	#include "cpu/m6809/m6809.h"
22	22	#include "sound/2151intf.h"
23	23	#include "video/konicdev.h"

trunk/src/mame/drivers/parodius.c
r21564	r21565
8	8
9	9	#include "emu.h"
10	10	#include "cpu/z80/z80.h"
11		#include "cpu/~~kona~~mi/konami.h" /* for the callback and the firq irq definition */
	11	#include "cpu/m6809/konami.h" /* for the callback and the firq irq definition */
12	12	#include "video/konicdev.h"
13	13	#include "sound/2151intf.h"
14	14	#include "sound/k053260.h"

trunk/src/mame/drivers/combatsc.c
r21564	r21565
120	120	***************************************************************************/
121	121
122	122	#include "emu.h"
123		#include "cpu/hd6309/hd6309.h"
	123	#include "cpu/m6809/hd6309.h"
124	124	#include "cpu/z80/z80.h"
125	125	#include "sound/2203intf.h"
126	126	#include "sound/upd7759.h"

trunk/src/mame/drivers/rockrage.c
r21564	r21565
49	49
50	50	#include "emu.h"
51	51	#include "cpu/m6809/m6809.h"
52		#include "cpu/hd6309/hd6309.h"
	52	#include "cpu/m6809/hd6309.h"
53	53	#include "sound/2151intf.h"
54	54	#include "sound/vlm5030.h"
55	55	#include "video/konicdev.h"

trunk/src/mame/drivers/fastlane.c
r21564	r21565
10	10	***************************************************************************/
11	11
12	12	#include "emu.h"
13		#include "cpu/hd6309/hd6309.h"
	13	#include "cpu/m6809/hd6309.h"
14	14	#include "sound/k007232.h"
15	15	#include "video/konicdev.h"
16	16	#include "includes/konamipt.h"

trunk/src/mame/drivers/vendetta.c
r21564	r21565
90	90	#include "cpu/z80/z80.h"
91	91	#include "video/konicdev.h"
92	92	#include "machine/k053252.h"
93		#include "cpu/~~kona~~mi/konami.h" /* for the callback and the firq irq definition */
	93	#include "cpu/m6809/konami.h" /* for the callback and the firq irq definition */
94	94	#include "machine/eeprom.h"
95	95	#include "sound/2151intf.h"
96	96	#include "sound/k053260.h"

trunk/src/mame/drivers/aliens.c
r21564	r21565
9	9
10	10	#include "emu.h"
11	11	#include "cpu/z80/z80.h"
12		#include "cpu/~~kona~~mi/konami.h" /* for the callback and the firq irq definition */
	12	#include "cpu/m6809/konami.h" /* for the callback and the firq irq definition */
13	13	#include "sound/k007232.h"
14	14	#include "sound/2151intf.h"
15	15	#include "video/konicdev.h"

trunk/src/mame/drivers/blockhl.c
r21564	r21565
21	21
22	22	#include "emu.h"
23	23	#include "cpu/z80/z80.h"
24		#include "cpu/~~kona~~mi/konami.h" /* for the callback and the firq irq definition */
	24	#include "cpu/m6809/konami.h" /* for the callback and the firq irq definition */
25	25	#include "video/konicdev.h"
26	26	#include "sound/2151intf.h"
27	27	#include "includes/konamipt.h"

trunk/src/mame/drivers/crimfght.c
r21564	r21565
13	13
14	14	#include "emu.h"
15	15	#include "cpu/z80/z80.h"
16		#include "cpu/~~kona~~mi/konami.h" /* for the callback and the firq irq definition */
	16	#include "cpu/m6809/konami.h" /* for the callback and the firq irq definition */
17	17	#include "video/konicdev.h"
18	18	#include "sound/2151intf.h"
19	19	#include "sound/k007232.h"

trunk/src/mame/drivers/labyrunr.c
r21564	r21565
9	9	***************************************************************************/
10	10
11	11	#include "emu.h"
12		#include "cpu/hd6309/hd6309.h"
	12	#include "cpu/m6809/hd6309.h"
13	13	#include "sound/2203intf.h"
14	14	#include "video/konicdev.h"
15	15	#include "includes/konamipt.h"

trunk/src/mame/drivers/chinagat.c
r21564	r21565
70	70
71	71
72	72	#include "emu.h"
73		#include "cpu/hd6309/hd6309.h"
	73	#include "cpu/m6809/hd6309.h"
74	74	#include "cpu/m6809/m6809.h"
75	75	#include "cpu/z80/z80.h"
76	76	#include "cpu/mcs48/mcs48.h"

trunk/src/mame/drivers/rollerg.c
r21564	r21565
14	14	#include "cpu/z80/z80.h"
15	15	#include "video/konicdev.h"
16	16	#include "machine/k053252.h"
17		#include "cpu/~~kona~~mi/konami.h" /* for the callback and the firq irq definition */
	17	#include "cpu/m6809/konami.h" /* for the callback and the firq irq definition */
18	18	#include "sound/3812intf.h"
19	19	#include "sound/k053260.h"
20	20	#include "includes/rollerg.h"

trunk/src/mame/drivers/hcastle.c
r21564	r21565
7	7	***************************************************************************/
8	8
9	9	#include "emu.h"
10		#include "cpu/~~kona~~mi/konami.h"
	10	#include "cpu/m6809/konami.h"
11	11	#include "cpu/z80/z80.h"
12	12	#include "sound/3812intf.h"
13	13	#include "sound/k007232.h"

trunk/src/mame/drivers/flkatck.c
r21564	r21565
12	12
13	13	#include "emu.h"
14	14	#include "cpu/z80/z80.h"
15		#include "cpu/hd6309/hd6309.h"
	15	#include "cpu/m6809/hd6309.h"
16	16	#include "sound/2151intf.h"
17	17	#include "sound/k007232.h"
18	18	#include "video/konicdev.h"

trunk/src/mame/machine/simpsons.c
r21564	r21565
1	1	#include "emu.h"
2	2	#include "video/konicdev.h"
3		#include "cpu/~~kona~~mi/konami.h"
	3	#include "cpu/m6809/konami.h"
4	4	#include "machine/eeprom.h"
5	5	#include "sound/k053260.h"
6	6	#include "includes/simpsons.h"

trunk/src/mame/machine/ajax.c
r21564	r21565
10	10	#include "emu.h"
11	11	#include "cpu/m6809/m6809.h"
12	12	#include "cpu/z80/z80.h"
13		#include "cpu/~~kona~~mi/konami.h"
	13	#include "cpu/m6809/konami.h"
14	14	#include "video/konicdev.h"
15	15	#include "includes/ajax.h"
16	16

trunk/src/emu/emucore.h
r21564	r21565
116	116	};
117	117
118	118
	119	// PAIR16 is a 16-bit extension of a PAIR
	120	union PAIR16
	121	{
	122	#ifdef LSB_FIRST
	123	struct { UINT8 l,h; } b;
	124	struct { INT8 l,h; } sb;
	125	#else
	126	struct { UINT8 h,l; } b;
	127	struct { INT8 h,l; } sb;
	128	#endif
	129	UINT16 w;
	130	INT16 sw;
	131	};
	132
	133
119	134	// PAIR64 is a 64-bit extension of a PAIR
120	135	union PAIR64
121	136	{

trunk/src/emu/cpu/konami/knmidasm.c
r21564	r21565
1		#include "emu.h"
2		#include "debugger.h"
3		#include "konami.h"
4
5		#ifndef TRUE
6		#define TRUE -1
7		#define FALSE 0
8		#endif
9
10		/*
11
12		0x08 leax indexed
13		0x09 leay indexed (not confirmed)
14		0x0a leau indexed
15		0x0b leas indexed (not confirmed)
16
17		0x0c pushs xx
18		0x0d pushu xx (not confirmed)
19		0x0e pulls xx
20		0x0f pulls xx (not confirmed)
21
22		0x10 lda xx
23		0x11 ldb xx
24		0x12 lda indexed
25		0x13 ldb indexed
26
27		0x14 adda xx
28		0x15 addb xx (not confirmed)
29		0x16 adda indexed (not confirmed)
30		0x17 addb indexed
31
32		0x18 adca xx
33		0x19 adcb xx (not confirmed)
34		0x1a adca indexed (not confirmed)
35		0x1b adcb indexed (not confirmed)
36
37		0x1c suba xx
38		0x1d subb xx
39		0x1e suba indexed
40		0x1f subb indexed
41
42		0x20 sbca xx
43		0x21 sbcb xx
44		0x22 sbca indexed
45		0x23 sbcb indexed
46
47		0x24 anda xx
48		0x25 andb xx
49		0x26 anda indexed
50		0x27 andb indexed
51
52		0x28 bita xx
53		0x29 bitb xx
54		0x2a bita indexed
55		0x2b bitb indexed
56
57		0x2c eora xx
58		0x2d eorb xx
59		0x2e eora indexed
60		0x2f eorb indexed
61
62		0x30 ora xx
63		0x31 orb xx
64		0x32 ora indexed
65		0x33 orb indexed
66
67		0x34 cmpa xx
68		0x35 cmpb xx
69		0x36 cmpa indexed
70		0x37 cmpb indexed
71
72		CUSTOM OPCODE: Set Address lines 16-23
73		--------------------------------------
74		0x38 setlines xx
75		0x39 setlines indexed
76
77		The eight bits taken as parameter set address lines 16 to 23.
78
79
80		0x3a sta indexed
81		0x3b stb indexed
82		0x3c andcc
83		0x3d orcc
84
85		0x3e exg xx
86		0x3f tfr xx
87
88		0x40 ldd xx xx
89		0x41 ldd indexed
90		0x42 ldx xx xx
91		0x43 ldx indexed
92		0x44 ldy xx xx
93		0x45 ldy indexed (not confirmed)
94		0x46 ldu xx xx
95		0x47 ldu indexed
96		0x48 lds xx xx
97		0x49 lds indexed (not confirmed)
98
99		0x4a cmpd xx xx
100		0x4b cmpd indexed
101		0x4c cmpx xx xx
102		0x4d cmpx indexed
103		0x4e cmpy xx xx (not confirmed)
104		0x4f cmpy indexed (not confirmed)
105		0x50 cmpu xx xx (not confirmed)
106		0x51 cmpu indexed (not confirmed)
107		0x52 cmps xx xx (not confirmed)
108		0x53 cmps indexed (not confirmed)
109
110		0x54 addd xx xx
111		0x55 addd indexed (not confirmed)
112		0x56 subd xx xx
113		0x57 subd indexed (not confirmed)
114
115		0x58 std indexed
116		0x59 stx indexed
117		0x5a sty indexed
118		0x5b stu indexed
119		0x5c sts indexed (not confirmed)
120
121
122		BRANCH OPCODE TABLE :
123		---------------------
124
125		Opcode M6809 Konami
126		BRA 20 60
127		BRN 21 70
128		BHI 22 61
129		BLS 23 71
130		BCC 24 62
131		BCS 25 72
132		BNE 26 63
133		BEQ 27 73
134		BVC 28 64
135		BVS 29 74
136		BPL 2a 65
137		BMI 2b 75
138		BGE 2c 66
139		BLT 2d 76
140		BGT 2e 67
141		BLE 2f 77
142
143		Long versions of the branchs are the number + 8.
144
145		0x80 clra
146		0x81 clrb
147		0x82 clr indexed
148
149		0x83 coma
150		0x84 comb
151		0x85 com indexed
152
153		0x86 nega (not confirmed)
154		0x87 negb (not confirmed)
155		0x88 neg indexed (not confirmed)
156
157		0x89 inca
158		0x8a incb (not confirmed)
159		0x8b inc indexed
160
161		0x8c deca
162		0x8d decb
163		0x8e dec indexed
164
165		0x8f rts
166
167		0x90 tsta (not confirmed)
168		0x91 tstb (not confirmed)
169		0x92 tst indexed (not confirmed)
170
171		0x93 lsra
172		0x94 lsrb
173		0x95 lsr indexed
174
175		0x96 rora
176		0x97 rorb
177		0x98 ror indexed
178
179		0x99 asra
180		0x9a asrb
181		0x9b asr indexed
182
183		0x9c asla
184		0x9d aslb
185		0x9e asl indexed
186
187		0x9f rti
188
189		0xa0 rola
190		0xa1 rolb
191		0xa2 rol indexed
192
193		0xa3 lsrw indexed ( not confirmed )
194		0xa4 rorw indexed ( not confirmed )
195		0xa5 asrw indexed ( not confirmed )
196		0xa6 aslw indexed ( not confirmed )
197		0xa7 rolw indexed ( not confirmed )
198
199		0xa8 jmp indexed
200		0xa9 jsr indexed
201		0xaa bsr xx
202		0xab lbsr xx xx
203		0xac decb,jnz xx
204		0xad decx,jnz xx
205		0xae nop
206
207		0xb0 abx
208		0xb1 daa
209		0xb2 sex
210
211		0xb3 mul
212
213		0xb4 lmul x:y = x * y
214
215		0xb5 divx x = ( x / b ), b = ( x % b )
216
217		CUSTOM OPCODE: BlockMove (y,x,u):
218		---------------------------------
219		0xb6 bmove y,x,u
220
221		y = pointer to source address
222		x = pointer to destination address
223		u = bytes to move
224
225		One byte is copied at a time and x and y get incremented for each access.
226
227		CUSTOM OPCODE: Move (y,x,u):
228		---------------------------------
229		0xb7 move y,x,u
230
231		y = pointer to source address
232		x = pointer to destination address
233		u = counter
234
235		Copy ONE byte, increment x and y, decrement u.
236
237		0xb8 lsrd xx
238		0xb9 lsrd indexed
239		0xba rord xx ( not confirmed )
240		0xbb rord indexed ( not confirmed )
241		0xbc asrd xx ( not confirmed )
242		0xbd asrd indexed ( not confirmed )
243		0xbe asld xx
244		0xbf asld indexed ( not confirmed )
245		0xc0 rold xx ( not confirmed )
246		0xc1 rold indexed ( not confirmed )
247
248		0xc2 clrd
249		0xc3 clrw indexed ( clears an entire word ) ( not confirmed )
250
251		0xc4 negd (not confirmed )
252		0xc5 negw indexed
253
254		0xc6 incd (not confirmed )
255		0xc7 incw indexed
256
257		0xc8 decd (not confirmed )
258		0xc9 decw indexed
259
260		0xca tstd
261		0xcb tstw indexed
262
263		0xcc absa
264		0xcd absb
265		0xce absd
266
267		CUSTOM OPCODE: BlockSet (a,x,u):
268		---------------------------------
269		0xcf bset a,x,u
270
271		a = source data
272		x = pointer to destination address
273		u = bytes to move
274
275		One byte is copied at a time and x get incremented for each access.
276
277		CUSTOM OPCODE: BlockSet (d,x,u): (not confirmed)
278		--------------------------------
279		0xd0 bset d,x,u
280
281		d = source data
282		x = pointer to destination address
283		u = bytes to move/2
284
285		Two bytes are copied at a time and x get incremented twice for each access.
286
287		*/
288
289		static unsigned byte_count;
290		static unsigned local_pc;
291		static unsigned flags;
292
293		static const unsigned char *opram_ptr;
294
295		static unsigned char get_next_byte( void ) {
296		return opram_ptr[byte_count++];
297		}
298
299		/* Table for indexed operations */
300		static const char index_reg[8][3] = {
301		"?", /* 0 - extended mode */
302		"?", /* 1 */
303		"x", /* 2 */
304		"y", /* 3 */
305		"?", /* 4 - direct page */
306		"u", /* 5 */
307		"s", /* 6 */
308		"pc" /* 7 - pc */
309		};
310
311		/* Table for tfr/exg operations */
312		static const char tfrexg_reg[8][3] = {
313		"a", /* 0 */
314		"b", /* 1 */
315		"x", /* 2 */
316		"y", /* 3 */
317		"s", /* 4 */
318		"u", /* 5 */
319		"?", /* 6 */
320		"?", /* 7 */
321		};
322
323		/* Table for stack S operations */
324		static const char stack_reg_s[8][3] = {
325		"cc",
326		"a",
327		"b",
328		"dp",
329		"x",
330		"y",
331		"u",
332		"pc"
333		};
334
335		/* Table for stack U operations */
336		static const char stack_reg_u[8][3] = {
337		"cc",
338		"a",
339		"b",
340		"dp",
341		"x",
342		"y",
343		"s",
344		"pc"
345		};
346
347		static void calc_indexed( unsigned char mode, char *buf ) {
348		char buf2[30];
349		int idx, type;
350
351		idx = ( mode >> 4 ) & 7;
352		type = mode & 0x0f;
353
354		/* special modes */
355		if ( mode & 0x80 ) {
356		if ( type & 8 ) { /* indirect */
357		switch ( type & 7 ) {
358		case 0x00: /* register a */
359		sprintf( buf2, "[a,%s]", index_reg[idx] );
360		break;
361
362		case 0x01: /* register b */
363		sprintf( buf2, "[b,%s]", index_reg[idx] );
364		break;
365
366		case 0x04: /* direct - mode */
367		sprintf( buf2, "[$%02x]", get_next_byte() );
368		break;
369
370		case 0x07: /* register d */
371		sprintf( buf2, "[d,%s]", index_reg[idx] );
372		break;
373
374		default:
375		sprintf( buf2, "[?,%s]", index_reg[idx] );
376		break;
377		}
378		} else {
379		switch ( type & 7 ) {
380		case 0x00: /* register a */
381		sprintf( buf2, "a,%s", index_reg[idx] );
382		break;
383
384		case 0x01: /* register b */
385		sprintf( buf2, "b,%s", index_reg[idx] );
386		break;
387
388		case 0x04: /* direct - mode */
389		sprintf( buf2, "$%02x", get_next_byte() );
390		break;
391
392		case 0x07: /* register d */
393		sprintf( buf2, "d,%s", index_reg[idx] );
394		break;
395
396		default:
397		sprintf( buf2, "????,%s", index_reg[idx] );
398		break;
399		}
400		}
401		} else {
402		if ( type & 8 ) { /* indirect */
403		switch ( type & 7 ) {
404		case 0: /* auto increment */
405		sprintf( buf2, "[,%s+]", index_reg[idx] );
406		break;
407
408		case 1: /* auto increment double */
409		sprintf( buf2, "[,%s++]", index_reg[idx] );
410		break;
411
412		case 2: /* auto decrement */
413		sprintf( buf2, "[,-%s]", index_reg[idx] );
414		break;
415
416		case 3: /* auto decrement double */
417		sprintf( buf2, "[,--%s]", index_reg[idx] );
418		break;
419
420		case 4: /* post byte offset */
421		{
422		int val = get_next_byte();
423
424		if ( val & 0x80 )
425		sprintf( buf2, "[#$-%02x,%s]", 0x100 - val, index_reg[idx] );
426		else
427		sprintf( buf2, "[#$%02x,%s]", val, index_reg[idx] );
428		}
429		break;
430
431		case 5: /* post word offset */
432		{
433		int val = get_next_byte() << 8;
434
435		val \|= get_next_byte();
436
437		if ( val & 0x8000 )
438		sprintf( buf2, "[#$-%04x,%s]", 0x10000 - val, index_reg[idx] );
439		else
440		sprintf( buf2, "[#$%04x,%s]", val, index_reg[idx] );
441		}
442		break;
443
444		case 6: /* simple */
445		sprintf( buf2, "[,%s]", index_reg[idx] );
446		break;
447
448		case 7: /* extended */
449		{
450		int val = get_next_byte() << 8;
451
452		val \|= get_next_byte();
453
454		sprintf( buf2, "[$%04x]", val );
455		}
456		break;
457		}
458		} else {
459		switch ( type & 7 ) {
460		case 0: /* auto increment */
461		sprintf( buf2, ",%s+", index_reg[idx] );
462		break;
463
464		case 1: /* auto increment double */
465		sprintf( buf2, ",%s++", index_reg[idx] );
466		break;
467
468		case 2: /* auto decrement */
469		sprintf( buf2, ",-%s", index_reg[idx] );
470		break;
471
472		case 3: /* auto decrement double */
473		sprintf( buf2, ",--%s", index_reg[idx] );
474		break;
475
476		case 4: /* post byte offset */
477		{
478		int val = get_next_byte();
479
480		if ( val & 0x80 )
481		sprintf( buf2, "#$-%02x,%s", 0x100 - val , index_reg[idx] );
482		else
483		sprintf( buf2, "#$%02x,%s", val, index_reg[idx] );
484		}
485		break;
486
487		case 5: /* post word offset */
488		{
489		int val = get_next_byte() << 8;
490
491		val \|= get_next_byte();
492
493		if ( val & 0x8000 )
494		sprintf( buf2, "#$-%04x,%s", 0x10000 - val, index_reg[idx] );
495		else
496		sprintf( buf2, "#$%04x,%s", val, index_reg[idx] );
497		}
498		break;
499
500		case 6: /* simple */
501		sprintf( buf2, ",%s", index_reg[idx] );
502		break;
503
504		case 7: /* extended */
505		{
506		int val = get_next_byte() << 8;
507
508		val \|= get_next_byte();
509
510		sprintf( buf2, "$%04x", val );
511		}
512		break;
513
514		}
515		}
516		}
517
518		strcat( buf, buf2 );
519		}
520
521		static void do_relative( char *buf ) {
522		char buf2[30];
523		signed char offs = ( signed char )get_next_byte();
524
525		sprintf( buf2, "$%04x (%d)", local_pc + byte_count + offs, (int)offs );
526
527		strcat( buf, buf2 );
528		}
529
530		static void do_relative_word( char *buf ) {
531		char buf2[30];
532		signed short offs;
533		int val = get_next_byte() << 8;
534
535		val \|= get_next_byte();
536
537		offs = ( signed short )val;
538
539		sprintf( buf2, "$%04x (%d)", local_pc + byte_count + offs, (int)offs );
540
541		strcat( buf, buf2 );
542		}
543
544		static void do_addressing( char *buf ) {
545		unsigned char mode = get_next_byte();
546
547		calc_indexed( mode, buf );
548		}
549
550		/*********************************************************************************
551
552		Opcodes
553
554		*********************************************************************************/
555
556		static void illegal( char *buf ) {
557		sprintf( buf, "illegal/unknown " );
558
559		}
560
561		static void leax( char *buf ) {
562		sprintf( buf, "leax " );
563		do_addressing( buf );
564		}
565
566		static void leay( char *buf ) {
567		sprintf( buf, "leay " );
568		do_addressing( buf );
569		}
570
571		static void leau( char *buf ) {
572		sprintf( buf, "leau " );
573		do_addressing( buf );
574		}
575
576		static void leas( char *buf ) {
577		sprintf( buf, "leas " );
578		do_addressing( buf );
579		}
580
581		static void lda( char *buf ) {
582		sprintf( buf, "lda #$%02x", get_next_byte() );
583		}
584
585		static void ldb( char *buf ) {
586		sprintf( buf, "ldb #$%02x", get_next_byte() );
587		}
588
589		static void lda2( char *buf ) {
590		sprintf( buf, "lda " );
591		do_addressing( buf );
592		}
593
594		static void ldb2( char *buf ) {
595		sprintf( buf, "ldb " );
596		do_addressing( buf );
597		}
598
599		static void adda( char *buf ) {
600		sprintf( buf, "adda #$%02x", get_next_byte() );
601		}
602
603		static void addb( char *buf ) {
604		sprintf( buf, "addb #$%02x", get_next_byte() );
605		}
606
607		static void adda2( char *buf ) {
608		sprintf( buf, "adda " );
609		do_addressing( buf );
610		}
611
612		static void addb2( char *buf ) {
613		sprintf( buf, "addb " );
614		do_addressing( buf );
615		}
616
617		static void suba( char *buf ) {
618		sprintf( buf, "suba #$%02x", get_next_byte() );
619		}
620
621		static void subb( char *buf ) {
622		sprintf( buf, "subb #$%02x", get_next_byte() );
623		}
624
625		static void suba2( char *buf ) {
626		sprintf( buf, "suba " );
627		do_addressing( buf );
628		}
629
630		static void subb2( char *buf ) {
631		sprintf( buf, "subb " );
632		do_addressing( buf );
633		}
634
635		static void sbca( char *buf ) {
636		sprintf( buf, "sbca #$%02x", get_next_byte() );
637		}
638
639		static void sbcb( char *buf ) {
640		sprintf( buf, "sbcb #$%02x", get_next_byte() );
641		}
642
643		static void sbca2( char *buf ) {
644		sprintf( buf, "sbca " );
645		do_addressing( buf );
646		}
647
648		static void sbcb2( char *buf ) {
649		sprintf( buf, "sbcb " );
650		do_addressing( buf );
651		}
652
653		static void adca( char *buf ) {
654		sprintf( buf, "adca #$%02x", get_next_byte() );
655		}
656
657		static void adca2( char *buf ) {
658		sprintf( buf, "adca " );
659		do_addressing( buf );
660		}
661
662		static void adcb2( char *buf ) {
663		sprintf( buf, "adcb " );
664		do_addressing( buf );
665		}
666
667		static void adcb( char *buf ) {
668		sprintf( buf, "adcb #$%02x", get_next_byte() );
669		}
670
671		static void anda( char *buf ) {
672		sprintf( buf, "anda #$%02x", get_next_byte() );
673		}
674
675		static void andb( char *buf ) {
676		sprintf( buf, "andb #$%02x", get_next_byte() );
677		}
678
679		static void anda2( char *buf ) {
680		sprintf( buf, "anda " );
681		do_addressing( buf );
682		}
683
684		static void andb2( char *buf ) {
685		sprintf( buf, "andb " );
686		do_addressing( buf );
687		}
688
689		static void bita( char *buf ) {
690		sprintf( buf, "bita #$%02x", get_next_byte() );
691		}
692
693		static void bitb( char *buf ) {
694		sprintf( buf, "bitb #$%02x", get_next_byte() );
695		}
696
697		static void bita2( char *buf ) {
698		sprintf( buf, "bita " );
699		do_addressing( buf );
700		}
701
702		static void bitb2( char *buf ) {
703		sprintf( buf, "bitb " );
704		do_addressing( buf );
705		}
706
707		static void eora( char *buf ) {
708		sprintf( buf, "eora #$%02x", get_next_byte() );
709		}
710
711		static void eorb( char *buf ) {
712		sprintf( buf, "eorb #$%02x", get_next_byte() );
713		}
714
715		static void eora2( char *buf ) {
716		sprintf( buf, "eora " );
717		do_addressing( buf );
718		}
719
720		static void eorb2( char *buf ) {
721		sprintf( buf, "eorb " );
722		do_addressing( buf );
723		}
724
725		static void ora( char *buf ) {
726		sprintf( buf, "ora #$%02x", get_next_byte() );
727		}
728
729		static void orb( char *buf ) {
730		sprintf( buf, "orb #$%02x", get_next_byte() );
731		}
732
733		static void ora2( char *buf ) {
734		sprintf( buf, "ora " );
735		do_addressing( buf );
736		}
737
738		static void orb2( char *buf ) {
739		sprintf( buf, "orb " );
740		do_addressing( buf );
741		}
742
743		static void cmpa( char *buf ) {
744		sprintf( buf, "cmpa #$%02x", get_next_byte() );
745		}
746
747		static void cmpb( char *buf ) {
748		sprintf( buf, "cmpb #$%02x", get_next_byte() );
749		}
750
751		static void cmpa2( char *buf ) {
752		sprintf( buf, "cmpa " );
753		do_addressing( buf );
754		}
755
756		static void cmpb2( char *buf ) {
757		sprintf( buf, "cmpb " );
758		do_addressing( buf );
759		}
760
761		static void setlines( char *buf ) {
762		sprintf( buf, "setlines #$%02x", get_next_byte() );
763		}
764
765		static void setlines2( char *buf ) {
766		sprintf( buf, "setlines " );
767		do_addressing( buf );
768		}
769
770		static void sta2( char *buf ) {
771		sprintf( buf, "sta " );
772		do_addressing( buf );
773		}
774
775		static void stb2( char *buf ) {
776		sprintf( buf, "stb " );
777		do_addressing( buf );
778		}
779
780		static void ldd( char *buf ) {
781		int val = get_next_byte() << 8;
782
783		val \|= get_next_byte();
784
785		sprintf( buf, "ldd #$%04x", val );
786		}
787
788		static void ldd2( char *buf ) {
789		sprintf( buf, "ldd " );
790		do_addressing( buf );
791		}
792
793		static void ldx( char *buf ) {
794		int val = get_next_byte() << 8;
795
796		val \|= get_next_byte();
797
798		sprintf( buf, "ldx #$%04x", val );
799		}
800
801		static void ldx2( char *buf ) {
802		sprintf( buf, "ldx " );
803		do_addressing( buf );
804		}
805
806		static void ldy( char *buf ) {
807		int val = get_next_byte() << 8;
808
809		val \|= get_next_byte();
810
811		sprintf( buf, "ldy #$%04x", val );
812		}
813
814		static void ldy2( char *buf ) {
815		sprintf( buf, "ldy " );
816		do_addressing( buf );
817		}
818
819		static void ldu( char *buf ) {
820		int val = get_next_byte() << 8;
821
822		val \|= get_next_byte();
823
824		sprintf( buf, "ldu #$%04x", val );
825		}
826
827		static void ldu2( char *buf ) {
828		sprintf( buf, "ldu " );
829		do_addressing( buf );
830		}
831
832		static void lds( char *buf ) {
833		int val = get_next_byte() << 8;
834
835		val \|= get_next_byte();
836
837		sprintf( buf, "lds #$%04x", val );
838		}
839
840		static void lds2( char *buf ) {
841		sprintf( buf, "lds " );
842		do_addressing( buf );
843		}
844
845		static void cmpd( char *buf ) {
846		int val = get_next_byte() << 8;
847
848		val \|= get_next_byte();
849
850		sprintf( buf, "cmpd #$%04x", val );
851		}
852
853		static void cmpd2( char *buf ) {
854		sprintf( buf, "cmpd " );
855		do_addressing( buf );
856		}
857
858		static void cmpx( char *buf ) {
859		int val = get_next_byte() << 8;
860
861		val \|= get_next_byte();
862
863		sprintf( buf, "cmpx #$%04x", val );
864		}
865
866		static void cmpx2( char *buf ) {
867		sprintf( buf, "cmpx " );
868		do_addressing( buf );
869		}
870
871		static void cmpy( char *buf ) {
872		int val = get_next_byte() << 8;
873
874		val \|= get_next_byte();
875
876		sprintf( buf, "cmpy #$%04x", val );
877		}
878
879		static void cmpy2( char *buf ) {
880		sprintf( buf, "cmpy " );
881		do_addressing( buf );
882		}
883
884		static void cmpu( char *buf ) {
885		int val = get_next_byte() << 8;
886
887		val \|= get_next_byte();
888
889		sprintf( buf, "cmpu #$%04x", val );
890		}
891
892		static void cmpu2( char *buf ) {
893		sprintf( buf, "cmpu " );
894		do_addressing( buf );
895		}
896
897		static void cmps( char *buf ) {
898		int val = get_next_byte() << 8;
899
900		val \|= get_next_byte();
901
902		sprintf( buf, "cmps #$%04x", val );
903		}
904
905		static void cmps2( char *buf ) {
906		sprintf( buf, "cmps " );
907		do_addressing( buf );
908		}
909
910		static void addd2( char *buf ) {
911		sprintf( buf, "addd " );
912		do_addressing( buf );
913		}
914
915		static void subd2( char *buf ) {
916		sprintf( buf, "subd " );
917		do_addressing( buf );
918		}
919
920		static void std2( char *buf ) {
921		sprintf( buf, "std " );
922		do_addressing( buf );
923		}
924
925		static void stx2( char *buf ) {
926		sprintf( buf, "stx " );
927		do_addressing( buf );
928		}
929
930		static void sty2( char *buf ) {
931		sprintf( buf, "sty " );
932		do_addressing( buf );
933		}
934
935		static void stu2( char *buf ) {
936		sprintf( buf, "stu " );
937		do_addressing( buf );
938		}
939
940		static void sts2( char *buf ) {
941		sprintf( buf, "sts " );
942		do_addressing( buf );
943		}
944
945		static void bra( char *buf ) {
946		sprintf( buf, "bra " );
947		do_relative( buf );
948		}
949
950		static void lbra( char *buf ) {
951		sprintf( buf, "lbra " );
952		do_relative_word( buf );
953		}
954
955		static void brn( char *buf ) {
956		sprintf( buf, "brn " );
957		do_relative( buf );
958		}
959
960		static void lbrn( char *buf ) {
961		sprintf( buf, "lbrn " );
962		do_relative_word( buf );
963		}
964
965		static void bhi( char *buf ) {
966		sprintf( buf, "bhi " );
967		do_relative( buf );
968		}
969
970		static void lbhi( char *buf ) {
971		sprintf( buf, "lbhi " );
972		do_relative_word( buf );
973		}
974
975		static void bls( char *buf ) {
976		sprintf( buf, "bls " );
977		do_relative( buf );
978		}
979
980		static void lbls( char *buf ) {
981		sprintf( buf, "lbls " );
982		do_relative_word( buf );
983		}
984
985		static void bcc( char *buf ) {
986		sprintf( buf, "bcc " );
987		do_relative( buf );
988		}
989
990		static void lbcc( char *buf ) {
991		sprintf( buf, "lbcc " );
992		do_relative_word( buf );
993		}
994
995		static void bcs( char *buf ) {
996		sprintf( buf, "bcs " );
997		do_relative( buf );
998		}
999
1000		static void lbcs( char *buf ) {
1001		sprintf( buf, "lbcs " );
1002		do_relative_word( buf );
1003		}
1004
1005		static void bne( char *buf ) {
1006		sprintf( buf, "bne " );
1007		do_relative( buf );
1008		}
1009
1010		static void lbne( char *buf ) {
1011		sprintf( buf, "lbne " );
1012		do_relative_word( buf );
1013		}
1014
1015		static void beq( char *buf ) {
1016		sprintf( buf, "beq " );
1017		do_relative( buf );
1018		}
1019
1020		static void lbeq( char *buf ) {
1021		sprintf( buf, "lbeq " );
1022		do_relative_word( buf );
1023		}
1024
1025		static void bvc( char *buf ) {
1026		sprintf( buf, "bvc " );
1027		do_relative( buf );
1028		}
1029
1030		static void lbvc( char *buf ) {
1031		sprintf( buf, "lbvc " );
1032		do_relative_word( buf );
1033		}
1034
1035		static void bvs( char *buf ) {
1036		sprintf( buf, "bvs " );
1037		do_relative( buf );
1038		}
1039
1040		static void lbvs( char *buf ) {
1041		sprintf( buf, "lbvs " );
1042		do_relative_word( buf );
1043		}
1044
1045		static void bpl( char *buf ) {
1046		sprintf( buf, "bpl " );
1047		do_relative( buf );
1048		}
1049
1050		static void lbpl( char *buf ) {
1051		sprintf( buf, "lbpl " );
1052		do_relative_word( buf );
1053		}
1054
1055		static void bmi( char *buf ) {
1056		sprintf( buf, "bmi " );
1057		do_relative( buf );
1058		}
1059
1060		static void lbmi( char *buf ) {
1061		sprintf( buf, "lbmi " );
1062		do_relative_word( buf );
1063		}
1064
1065		static void bge( char *buf ) {
1066		sprintf( buf, "bge " );
1067		do_relative( buf );
1068		}
1069
1070		static void lbge( char *buf ) {
1071		sprintf( buf, "lbge " );
1072		do_relative_word( buf );
1073		}
1074
1075		static void blt( char *buf ) {
1076		sprintf( buf, "blt " );
1077		do_relative( buf );
1078		}
1079
1080		static void lblt( char *buf ) {
1081		sprintf( buf, "lblt " );
1082		do_relative_word( buf );
1083		}
1084
1085		static void bgt( char *buf ) {
1086		sprintf( buf, "bgt " );
1087		do_relative( buf );
1088		}
1089
1090		static void lbgt( char *buf ) {
1091		sprintf( buf, "lbgt " );
1092		do_relative_word( buf );
1093		}
1094
1095		static void ble( char *buf ) {
1096		sprintf( buf, "ble " );
1097		do_relative( buf );
1098		}
1099
1100		static void lble( char *buf ) {
1101		sprintf( buf, "lble " );
1102		do_relative_word( buf );
1103		}
1104
1105		static void clra( char *buf ) {
1106		sprintf( buf, "clra" );
1107		}
1108
1109		static void clrb( char *buf ) {
1110		sprintf( buf, "clrb" );
1111		}
1112
1113		static void clrd( char *buf ) {
1114		sprintf( buf, "clrd" );
1115		}
1116
1117		static void clrw( char *buf ) {
1118		sprintf( buf, "clrw " );
1119		do_addressing( buf );
1120		}
1121
1122		static void negd( char *buf ) {
1123		sprintf( buf, "negd" );
1124		}
1125
1126		static void negw( char *buf ) {
1127		sprintf( buf, "negw" );
1128		do_addressing( buf );
1129		}
1130
1131		static void incd( char *buf ) {
1132		sprintf( buf, "incd" );
1133		}
1134
1135		static void incw( char *buf ) {
1136		sprintf( buf, "incw " );
1137		do_addressing( buf );
1138		}
1139
1140		static void decd( char *buf ) {
1141		sprintf( buf, "decd" );
1142		}
1143
1144		static void decw( char *buf ) {
1145		sprintf( buf, "decw " );
1146		do_addressing( buf );
1147		}
1148
1149		static void tstd( char *buf ) {
1150		sprintf( buf, "tstd " );
1151		}
1152
1153		static void tstw( char *buf ) {
1154		sprintf( buf, "tstw " );
1155		do_addressing( buf );
1156		}
1157
1158		static void clr2( char *buf ) {
1159		sprintf( buf, "clr " );
1160		do_addressing( buf );
1161		}
1162
1163		static void coma( char *buf ) {
1164		sprintf( buf, "coma" );
1165		}
1166
1167		static void comb( char *buf ) {
1168		sprintf( buf, "comb" );
1169		}
1170
1171		static void com2( char *buf ) {
1172		sprintf( buf, "com " );
1173		do_addressing( buf );
1174		}
1175
1176		static void nega( char *buf ) {
1177		sprintf( buf, "nega" );
1178		}
1179
1180		static void negb( char *buf ) {
1181		sprintf( buf, "negb" );
1182		}
1183
1184		static void neg2( char *buf ) {
1185		sprintf( buf, "neg " );
1186		do_addressing( buf );
1187		}
1188
1189		static void inca( char *buf ) {
1190		sprintf( buf, "inca" );
1191		}
1192
1193		static void incb( char *buf ) {
1194		sprintf( buf, "incb" );
1195		}
1196
1197		static void inc2( char *buf ) {
1198		sprintf( buf, "inc " );
1199		do_addressing( buf );
1200		}
1201
1202		static void deca( char *buf ) {
1203		sprintf( buf, "deca" );
1204		}
1205
1206		static void decb( char *buf ) {
1207		sprintf( buf, "decb" );
1208		}
1209
1210		static void dec2( char *buf ) {
1211		sprintf( buf, "dec " );
1212		do_addressing( buf );
1213		}
1214
1215		static void rts( char *buf ) {
1216		sprintf( buf, "rts" );
1217		flags = DASMFLAG_STEP_OUT;
1218		}
1219
1220		static void asla( char *buf ) {
1221		sprintf( buf, "asla" );
1222		}
1223
1224		static void aslb( char *buf ) {
1225		sprintf( buf, "aslb" );
1226		}
1227
1228		static void asl2( char *buf ) {
1229		sprintf( buf, "asl " );
1230		do_addressing( buf );
1231		}
1232
1233		static void rora( char *buf ) {
1234		sprintf( buf, "rora" );
1235		}
1236
1237		static void rorb( char *buf ) {
1238		sprintf( buf, "rorb" );
1239		}
1240
1241		static void ror2( char *buf ) {
1242		sprintf( buf, "ror " );
1243		do_addressing( buf );
1244		}
1245
1246		static void rti( char *buf ) {
1247		sprintf( buf, "rti" );
1248		flags = DASMFLAG_STEP_OUT;
1249		}
1250
1251		static void jsr2( char *buf ) {
1252		sprintf( buf, "jsr " );
1253		do_addressing( buf );
1254		flags = DASMFLAG_STEP_OVER;
1255		}
1256
1257		static void jmp2( char *buf ) {
1258		sprintf( buf, "jmp " );
1259		do_addressing( buf );
1260		}
1261
1262		static void bsr( char *buf ) {
1263		sprintf( buf, "bsr " );
1264		do_relative( buf );
1265		flags = DASMFLAG_STEP_OVER;
1266		}
1267
1268		static void lbsr( char *buf ) {
1269		sprintf( buf, "lbsr " );
1270		do_relative_word( buf );
1271		flags = DASMFLAG_STEP_OVER;
1272		}
1273
1274		static void decbjnz( char *buf ) {
1275		sprintf( buf, "decb,jnz " );
1276		do_relative( buf );
1277		flags = DASMFLAG_STEP_OVER;
1278		}
1279
1280		static void decxjnz( char *buf ) {
1281		sprintf( buf, "decx,jnz " );
1282		do_relative( buf );
1283		flags = DASMFLAG_STEP_OVER;
1284		}
1285
1286		static void addd( char *buf ) {
1287		int val = get_next_byte() << 8;
1288
1289		val \|= get_next_byte();
1290
1291		sprintf( buf, "addd #$%04x", val );
1292		}
1293
1294		static void subd( char *buf ) {
1295		int val = get_next_byte() << 8;
1296
1297		val \|= get_next_byte();
1298
1299		sprintf( buf, "subd #$%04x", val );
1300		}
1301
1302		static void tsta( char *buf ) {
1303		sprintf( buf, "tsta" );
1304		}
1305
1306		static void tstb( char *buf ) {
1307		sprintf( buf, "tstb" );
1308		}
1309
1310		static void tst2( char *buf ) {
1311		sprintf( buf, "tst " );
1312		do_addressing( buf );
1313		}
1314
1315		static void lsra( char *buf ) {
1316		sprintf( buf, "lsra" );
1317		}
1318
1319		static void lsrb( char *buf ) {
1320		sprintf( buf, "lsrb" );
1321		}
1322
1323		static void lsr2( char *buf ) {
1324		sprintf( buf, "lsr " );
1325		do_addressing( buf );
1326		}
1327
1328		static void asra( char *buf ) {
1329		sprintf( buf, "asra" );
1330		}
1331
1332		static void asrb( char *buf ) {
1333		sprintf( buf, "asrb" );
1334		}
1335
1336		static void asr2( char *buf ) {
1337		sprintf( buf, "asr " );
1338		do_addressing( buf );
1339		}
1340
1341		static void abx( char *buf ) {
1342		sprintf( buf, "abx" );
1343		}
1344
1345		static void sex( char *buf ) {
1346		sprintf( buf, "sex" );
1347		}
1348
1349		static void daa( char *buf ) {
1350		sprintf( buf, "daa" );
1351		}
1352
1353		static void mul( char *buf ) {
1354		sprintf( buf, "mul" );
1355		}
1356
1357		static void lmul( char *buf ) {
1358		sprintf( buf, "lmul" );
1359		}
1360
1361		static void divx( char *buf ) {
1362		sprintf( buf, "div x,b" );
1363		}
1364
1365		static void andcc( char *buf ) {
1366		sprintf( buf, "andcc #$%02x", get_next_byte() );
1367		}
1368
1369		static void orcc( char *buf ) {
1370		sprintf( buf, "orcc #$%02x", get_next_byte() );
1371		}
1372
1373		static void pushs( char *buf ) {
1374		int mask = get_next_byte(), i;
1375
1376		sprintf( buf, "pushs " );
1377
1378		for ( i = 0; i < 8; i++ ) {
1379		if ( ( mask >> i ) & 1 ) {
1380		strcat( buf, stack_reg_s[i] );
1381		mask &= ~( 1 << i );
1382		if ( mask )
1383		strcat( buf, "," );
1384		else
1385		return;
1386		}
1387		}
1388		}
1389
1390		static void pushu( char *buf ) {
1391		int mask = get_next_byte(), i;
1392
1393		sprintf( buf, "pushu " );
1394
1395		for ( i = 0; i < 8; i++ ) {
1396		if ( ( mask >> i ) & 1 ) {
1397		strcat( buf, stack_reg_u[i] );
1398		mask &= ~( 1 << i );
1399		if ( mask )
1400		strcat( buf, "," );
1401		else
1402		return;
1403		}
1404		}
1405		}
1406
1407		static void pulls( char *buf ) {
1408		int mask = get_next_byte(), i;
1409
1410		sprintf( buf, "pulls " );
1411
1412		for ( i = 0; i < 8; i++ ) {
1413		if ( ( mask >> i ) & 1 ) {
1414		strcat( buf, stack_reg_s[i] );
1415		if (i == 7)
1416		flags = DASMFLAG_STEP_OUT;
1417		mask &= ~( 1 << i );
1418		if ( mask )
1419		strcat( buf, "," );
1420		else
1421		return;
1422		}
1423		}
1424		}
1425
1426		static void pullu( char *buf ) {
1427		int mask = get_next_byte(), i;
1428
1429		sprintf( buf, "pullu " );
1430
1431		for ( i = 0; i < 8; i++ ) {
1432		if ( ( mask >> i ) & 1 ) {
1433		strcat( buf, stack_reg_s[i] );
1434		mask &= ~( 1 << i );
1435		if ( mask )
1436		strcat( buf, "," );
1437		else
1438		return;
1439		}
1440		}
1441		}
1442
1443		static void rola( char *buf ) {
1444		sprintf( buf, "rola" );
1445		}
1446
1447		static void rolb( char *buf ) {
1448		sprintf( buf, "rolb" );
1449		}
1450
1451		static void rol2( char *buf ) {
1452		sprintf( buf, "rol " );
1453		do_addressing( buf );
1454		}
1455
1456		static void bmove( char *buf ) {
1457		sprintf( buf, "bmove y,x,u" );
1458		}
1459
1460		static void move( char *buf ) {
1461		sprintf( buf, "move y,x,u" );
1462		}
1463
1464		static void bset( char *buf ) {
1465		sprintf( buf, "bset a,x,u" );
1466		}
1467
1468		static void bset2( char *buf ) {
1469		sprintf( buf, "bset d,x,u" );
1470		}
1471
1472		static void nop( char *buf ) {
1473		sprintf( buf, "nop" );
1474		}
1475
1476		static void tfr( char *buf ) {
1477		int mask = get_next_byte();
1478
1479		sprintf( buf, "tfr " );
1480
1481		strcat( buf, tfrexg_reg[ mask & 0x07 ] );
1482		strcat( buf, "," );
1483		strcat( buf, tfrexg_reg[ ( mask >> 4 ) & 0x07 ] );
1484		}
1485
1486		static void exg( char *buf ) {
1487		int mask = get_next_byte();
1488
1489		sprintf( buf, "exg " );
1490
1491		strcat( buf, tfrexg_reg[ mask & 0x07 ] );
1492		strcat( buf, "," );
1493		strcat( buf, tfrexg_reg[ ( mask >> 4 ) & 0x07 ] );
1494		}
1495
1496		static void lsrd( char *buf ) {
1497		sprintf( buf, "lsrd #$%02x", get_next_byte() );
1498		}
1499
1500		static void lsrd2( char *buf ) {
1501		sprintf( buf, "lsrd " );
1502		do_addressing( buf );
1503		}
1504
1505		static void rord( char *buf ) {
1506		sprintf( buf, "rord #$%02x", get_next_byte() );
1507		}
1508
1509		static void rord2( char *buf ) {
1510		sprintf( buf, "rord " );
1511		do_addressing( buf );
1512		}
1513
1514		static void asrd( char *buf ) {
1515		sprintf( buf, "asrd #$%02x", get_next_byte() );
1516		}
1517
1518		static void asrd2( char *buf ) {
1519		sprintf( buf, "asrd " );
1520		do_addressing( buf );
1521		}
1522
1523		static void asld( char *buf ) {
1524		sprintf( buf, "asld #$%02x", get_next_byte() );
1525		}
1526
1527		static void asld2( char *buf ) {
1528		sprintf( buf, "asld " );
1529		do_addressing( buf );
1530		}
1531
1532		static void rold( char *buf ) {
1533		sprintf( buf, "rold #$%02x", get_next_byte() );
1534		}
1535
1536		static void rold2( char *buf ) {
1537		sprintf( buf, "rold " );
1538		do_addressing( buf );
1539		}
1540
1541		static void lsrw( char *buf ) {
1542		sprintf( buf, "lsrw " );
1543		do_addressing( buf );
1544		}
1545
1546		static void rorw( char *buf ) {
1547		sprintf( buf, "lsrw " );
1548		do_addressing( buf );
1549		}
1550
1551		static void asrw( char *buf ) {
1552		sprintf( buf, "asrw " );
1553		do_addressing( buf );
1554		}
1555
1556		static void aslw( char *buf ) {
1557		sprintf( buf, "aslw " );
1558		do_addressing( buf );
1559		}
1560
1561		static void rolw( char *buf ) {
1562		sprintf( buf, "rolw " );
1563		do_addressing( buf );
1564		}
1565
1566		static void absa( char *buf ) {
1567		sprintf( buf, "absa" );
1568		}
1569
1570		static void absb( char *buf ) {
1571		sprintf( buf, "absb" );
1572		}
1573
1574		static void absd( char *buf ) {
1575		sprintf( buf, "absd" );
1576		}
1577
1578		/*********************************************************************************
1579
1580		Opcode Table
1581
1582		*********************************************************************************/
1583
1584		struct konami_opcode_def {
1585		void (decode)( char buf );
1586		int confirmed;
1587		};
1588
1589		static const konami_opcode_def op_table[256] = {
1590		/* 00 */ { illegal, 0 },
1591		/* 01 */ { illegal, 0 },
1592		/* 02 */ { illegal, 0 },
1593		/* 03 */ { illegal, 0 },
1594		/* 04 */ { illegal, 0 },
1595		/* 05 */ { illegal, 0 },
1596		/* 06 */ { illegal, 0 },
1597		/* 07 */ { illegal, 0 },
1598		/* 08 */ { leax, 1 },
1599		/* 09 */ { leay, 1 },
1600		/* 0a */ { leau, 1 },
1601		/* 0b */ { leas, 0 },
1602		/* 0c */ { pushs, 1 },
1603		/* 0d */ { pushu, 0 },
1604		/* 0e */ { pulls, 1 },
1605		/* 0f */ { pullu, 0 },
1606
1607		/* 10 */ { lda, 1 },
1608		/* 11 */ { ldb, 1 },
1609		/* 12 */ { lda2, 1 },
1610		/* 13 */ { ldb2, 1 },
1611		/* 14 */ { adda, 1 },
1612		/* 15 */ { addb, 1 },
1613		/* 16 */ { adda2, 1 },
1614		/* 17 */ { addb2, 1 },
1615		/* 18 */ { adca, 1 },
1616		/* 19 */ { adcb, 1 },
1617		/* 1a */ { adca2, 1 },
1618		/* 1b */ { adcb2, 1 },
1619		/* 1c */ { suba, 1 },
1620		/* 1d */ { subb, 1 },
1621		/* 1e */ { suba2, 1 },
1622		/* 1f */ { subb2, 1 },
1623
1624		/* 20 */ { sbca, 0 },
1625		/* 21 */ { sbcb, 0 },
1626		/* 22 */ { sbca2, 0 },
1627		/* 23 */ { sbcb2, 0 },
1628		/* 24 */ { anda, 1 },
1629		/* 25 */ { andb, 1 },
1630		/* 26 */ { anda2, 1 },
1631		/* 27 */ { andb2, 1 },
1632		/* 28 */ { bita, 0 },
1633		/* 29 */ { bitb, 0 },
1634		/* 2a */ { bita2, 0 },
1635		/* 2b */ { bitb2, 0 },
1636		/* 2c */ { eora, 0 },
1637		/* 2d */ { eorb, 0 },
1638		/* 2e */ { eora2, 0 },
1639		/* 2f */ { eorb2, 0 },
1640
1641		/* 30 */ { ora, 1 },
1642		/* 31 */ { orb, 1 },
1643		/* 32 */ { ora2, 1 },
1644		/* 33 */ { orb2, 1 },
1645		/* 34 */ { cmpa, 1 },
1646		/* 35 */ { cmpb, 1 },
1647		/* 36 */ { cmpa2, 1 },
1648		/* 37 */ { cmpb2, 1 },
1649		/* 38 */ { setlines, 0 },
1650		/* 39 */ { setlines2, 0 },
1651		/* 3a */ { sta2, 1 },
1652		/* 3b */ { stb2, 1 },
1653		/* 3c */ { andcc, 1 },
1654		/* 3d */ { orcc, 0 },
1655		/* 3e */ { exg, 0 },
1656		/* 3f */ { tfr, 0 },
1657
1658		/* 40 */ { ldd, 1 },
1659		/* 41 */ { ldd2, 1 },
1660		/* 42 */ { ldx, 1 },
1661		/* 43 */ { ldx2, 1 },
1662		/* 44 */ { ldy, 1 },
1663		/* 45 */ { ldy2, 1 },
1664		/* 46 */ { ldu, 1 },
1665		/* 47 */ { ldu2, 1 },
1666		/* 48 */ { lds, 1 },
1667		/* 49 */ { lds2, 1 },
1668		/* 4a */ { cmpd, 1 },
1669		/* 4b */ { cmpd2, 1 },
1670		/* 4c */ { cmpx, 1 },
1671		/* 4d */ { cmpx2, 1 },
1672		/* 4e */ { cmpy, 1 },
1673		/* 4f */ { cmpy2, 1 },
1674
1675		/* 50 */ { cmpu, 1 },
1676		/* 51 */ { cmpu2, 1 },
1677		/* 52 */ { cmps, 1 },
1678		/* 53 */ { cmps2, 1 },
1679		/* 54 */ { addd, 0 },
1680		/* 55 */ { addd2, 0 },
1681		/* 56 */ { subd, 1 },
1682		/* 57 */ { subd2, 0 },
1683		/* 58 */ { std2, 1 },
1684		/* 59 */ { stx2, 1 },
1685		/* 5a */ { sty2, 1 },
1686		/* 5b */ { stu2, 1 },
1687		/* 5c */ { sts2, 1 },
1688		/* 5d */ { illegal, 0 },
1689		/* 5e */ { illegal, 0 },
1690		/* 5f */ { illegal, 0 },
1691
1692		/* 60 */ { bra, 1 },
1693		/* 61 */ { bhi, 1 },
1694		/* 62 */ { bcc, 1 },
1695		/* 63 */ { bne, 1 },
1696		/* 64 */ { bvc, 1 },
1697		/* 65 */ { bpl, 1 },
1698		/* 66 */ { bge, 1 },
1699		/* 67 */ { bgt, 1 },
1700		/* 68 */ { lbra, 1 },
1701		/* 69 */ { lbhi, 1 },
1702		/* 6a */ { lbcc, 1 },
1703		/* 6b */ { lbne, 1 },
1704		/* 6c */ { lbvc, 1 },
1705		/* 6d */ { lbpl, 1 },
1706		/* 6e */ { lbge, 1 },
1707		/* 6f */ { lbgt, 1 },
1708
1709		/* 70 */ { brn, 1 },
1710		/* 71 */ { bls, 1 },
1711		/* 72 */ { bcs, 1 },
1712		/* 73 */ { beq, 1 },
1713		/* 74 */ { bvs, 1 },
1714		/* 75 */ { bmi, 1 },
1715		/* 76 */ { blt, 1 },
1716		/* 77 */ { ble, 1 },
1717		/* 78 */ { lbrn, 1 },
1718		/* 79 */ { lbls, 1 },
1719		/* 7a */ { lbcs, 1 },
1720		/* 7b */ { lbeq, 1 },
1721		/* 7c */ { lbvs, 1 },
1722		/* 7d */ { lbmi, 1 },
1723		/* 7e */ { lblt, 1 },
1724		/* 7f */ { lble, 1 },
1725
1726		/* 80 */ { clra, 1 },
1727		/* 81 */ { clrb, 1 },
1728		/* 82 */ { clr2, 1 },
1729		/* 83 */ { coma, 1 },
1730		/* 84 */ { comb, 0 },
1731		/* 85 */ { com2, 0 },
1732		/* 86 */ { nega, 0 },
1733		/* 87 */ { negb, 0 },
1734		/* 88 */ { neg2, 0 },
1735		/* 89 */ { inca, 1 },
1736		/* 8a */ { incb, 1 },
1737		/* 8b */ { inc2, 1 },
1738		/* 8c */ { deca, 1 },
1739		/* 8d */ { decb, 1 },
1740		/* 8e */ { dec2, 1 },
1741		/* 8f */ { rts, 1 },
1742
1743		/* 90 */ { tsta, 0 },
1744		/* 91 */ { tstb, 0 },
1745		/* 92 */ { tst2, 0 },
1746		/* 93 */ { lsra, 1 },
1747		/* 94 */ { lsrb, 1 },
1748		/* 95 */ { lsr2, 0 },
1749		/* 96 */ { rora, 0 },
1750		/* 97 */ { rorb, 0 },
1751		/* 98 */ { ror2, 0 },
1752		/* 99 */ { asra, 0 },
1753		/* 9a */ { asrb, 0 },
1754		/* 9b */ { asr2, 0 },
1755		/* 9c */ { asla, 1 },
1756		/* 9d */ { aslb, 1 },
1757		/* 9e */ { asl2, 0 },
1758		/* 9f */ { rti, 1 },
1759
1760		/* a0 */ { rola, 1 },
1761		/* a1 */ { rolb, 0 },
1762		/* a2 */ { rol2, 0 },
1763		/* a3 */ { lsrw, 0 },
1764		/* a4 */ { rorw, 0 },
1765		/* a5 */ { asrw, 0 },
1766		/* a6 */ { aslw, 0 },
1767		/* a7 */ { rolw, 0 },
1768		/* a8 */ { jmp2, 1 },
1769		/* a9 */ { jsr2, 1 },
1770		/* aa */ { bsr, 1 },
1771		/* ab */ { lbsr, 1 },
1772		/* ac */ { decbjnz, 0 },
1773		/* ad */ { decxjnz, 0 },
1774		/* ae */ { nop, 0 },
1775		/* af */ { illegal, 0 },
1776
1777		/* b0 */ { abx, 0 },
1778		/* b1 */ { daa, 0 },
1779		/* b2 */ { sex, 0 },
1780		/* b3 */ { mul, 1 },
1781		/* b4 */ { lmul, 0 },
1782		/* b5 */ { divx, 0 },
1783		/* b6 */ { bmove, 1 },
1784		/* b7 */ { move, 0 },
1785		/* b8 */ { lsrd, 0 },
1786		/* b9 */ { lsrd2, 0 },
1787		/* ba */ { rord, 0 },
1788		/* bb */ { rord2, 0 },
1789		/* bc */ { asrd, 0 },
1790		/* bd */ { asrd2, 0 },
1791		/* be */ { asld, 0 },
1792		/* bf */ { asld2, 0 },
1793
1794		/* c0 */ { rold, 0 },
1795		/* c1 */ { rold2, 0 },
1796		/* c2 */ { clrd, 1 },
1797		/* c3 */ { clrw, 0 },
1798		/* c4 */ { negd, 0 },
1799		/* c5 */ { negw, 0 },
1800		/* c6 */ { incd, 0 },
1801		/* c7 */ { incw, 0 },
1802		/* c8 */ { decd, 0 },
1803		/* c9 */ { decw, 0 },
1804		/* ca */ { tstd, 0 },
1805		/* cb */ { tstw, 0 },
1806		/* cc */ { absa, 0 },
1807		/* cd */ { absb, 0 },
1808		/* ce */ { absd, 0 },
1809		/* cf */ { bset, 0 },
1810
1811		/* d0 */ { bset2, 0 },
1812		/* d1 */ { illegal, 0 },
1813		/* d2 */ { illegal, 0 },
1814		/* d3 */ { illegal, 0 },
1815		/* d4 */ { illegal, 0 },
1816		/* d5 */ { illegal, 0 },
1817		/* d6 */ { illegal, 0 },
1818		/* d7 */ { illegal, 0 },
1819		/* d8 */ { illegal, 0 },
1820		/* d9 */ { illegal, 0 },
1821		/* da */ { illegal, 0 },
1822		/* db */ { illegal, 0 },
1823		/* dc */ { illegal, 0 },
1824		/* dd */ { illegal, 0 },
1825		/* de */ { illegal, 0 },
1826		/* df */ { illegal, 0 },
1827
1828		/* e0 */ { illegal, 0 },
1829		/* e1 */ { illegal, 0 },
1830		/* e2 */ { illegal, 0 },
1831		/* e3 */ { illegal, 0 },
1832		/* e4 */ { illegal, 0 },
1833		/* e5 */ { illegal, 0 },
1834		/* e6 */ { illegal, 0 },
1835		/* e7 */ { illegal, 0 },
1836		/* e8 */ { illegal, 0 },
1837		/* e9 */ { illegal, 0 },
1838		/* ea */ { illegal, 0 },
1839		/* eb */ { illegal, 0 },
1840		/* ec */ { illegal, 0 },
1841		/* ed */ { illegal, 0 },
1842		/* ee */ { illegal, 0 },
1843		/* ef */ { illegal, 0 },
1844
1845		/* f0 */ { illegal, 0 },
1846		/* f1 */ { illegal, 0 },
1847		/* f2 */ { illegal, 0 },
1848		/* f3 */ { illegal, 0 },
1849		/* f4 */ { illegal, 0 },
1850		/* f5 */ { illegal, 0 },
1851		/* f6 */ { illegal, 0 },
1852		/* f7 */ { illegal, 0 },
1853		/* f8 */ { illegal, 0 },
1854		/* f9 */ { illegal, 0 },
1855		/* fa */ { illegal, 0 },
1856		/* fb */ { illegal, 0 },
1857		/* fc */ { illegal, 0 },
1858		/* fd */ { illegal, 0 },
1859		/* fe */ { illegal, 0 },
1860		/* ff */ { illegal, 0 }
1861		};
1862
1863		CPU_DISASSEMBLE( konami )
1864		{
1865		buffer[0] = '\0';
1866
1867		local_pc = pc;
1868		byte_count = 1;
1869		opram_ptr = opram;
1870		flags = 0;
1871
1872		(op_table[*oprom].decode)( buffer );
1873
1874		return byte_count \| flags \| DASMFLAG_SUPPORTED;
1875		}

trunk/src/emu/cpu/konami/konami.h
r21564	r21565
1		/* konami: Portable Konami cpu emulator ****************************************/
2
3		#pragma once
4
5		#ifndef __KONAMI_H__
6		#define __KONAMI_H__
7
8
9		typedef void (konami_set_lines_func)(device_t device, int lines);
10
11		enum
12		{
13		KONAMI_PC=1, KONAMI_S, KONAMI_CC ,KONAMI_A, KONAMI_B, KONAMI_U, KONAMI_X, KONAMI_Y,
14		KONAMI_DP
15		};
16
17		#define KONAMI_SETLINES_CALLBACK(name) void name(device_t *device, int lines)
18
19		#define KONAMI_IRQ_LINE 0 /* IRQ line number */
20		#define KONAMI_FIRQ_LINE 1 /* FIRQ line number */
21
22		/* PUBLIC FUNCTIONS */
23		DECLARE_LEGACY_CPU_DEVICE(KONAMI, konami);
24
25		CPU_DISASSEMBLE( konami );
26
27		void konami_configure_set_lines(device_t *device, konami_set_lines_func func);
28
29
30		#endif /* __KONAMI_H__ */

trunk/src/emu/cpu/konami/konami.c
r21564	r21565
1		/* konami: Portable Konami cpu emulator ****************************************
2
3		Copyright Nicola Salmoria and the MAME Team
4
5		Based on M6809 cpu core copyright John Butler
6
7		References:
8
9		6809 Simulator V09, By L.C. Benschop, Eidnhoven The Netherlands.
10
11		m6809: Portable 6809 emulator, DS (6809 code in MAME, derived from
12		the 6809 Simulator V09)
13
14		6809 Microcomputer Programming & Interfacing with Experiments"
15		by Andrew C. Staugaard, Jr.; Howard W. Sams & Co., Inc.
16
17		System dependencies: UINT16 must be 16 bit unsigned int
18		UINT8 must be 8 bit unsigned int
19		UINT32 must be more than 16 bits
20		arrays up to 65536 bytes must be supported
21		machine must be twos complement
22
23		History:
24		991022 HJB:
25		Tried to improve speed: Using bit7 of cycles1 as flag for multi
26		byte opcodes is gone, those opcodes now instead go through opcode2().
27		Inlined fetch_effective_address() into that function as well.
28		Got rid of the slow/fast flags for stack (S and U) memory accesses.
29		Minor changes to use 32 bit values as arguments to memory functions
30		and added defines for that purpose (e.g. X = 16bit XD = 32bit).
31
32		990720 EHC:
33		Created this file
34
35		*****************************************************************************/
36
37		#include "emu.h"
38		#include "debugger.h"
39		#include "konami.h"
40
41		#define VERBOSE 0
42
43		#define LOG(x) do { if (VERBOSE) logerror x; } while (0)
44
45		/* Konami Registers */
46		struct konami_state
47		{
48		PAIR pc; /* Program counter */
49		PAIR ppc; /* Previous program counter */
50		PAIR d; /* Accumulator a and b */
51		PAIR dp; /* Direct Page register (page in MSB) */
52		PAIR u, s; /* Stack pointers */
53		PAIR x, y; /* Index registers */
54		PAIR ea;
55		UINT8 cc;
56		UINT8 ireg;
57		UINT8 irq_state[2];
58		device_irq_acknowledge_callback irq_callback;
59		UINT8 int_state; /* SYNC and CWAI flags */
60		UINT8 nmi_state;
61		UINT8 nmi_pending;
62		int icount;
63		legacy_cpu_device *device;
64		address_space *program;
65		direct_read_data *direct;
66		konami_set_lines_func setlines_callback;
67		};
68
69		INLINE konami_state get_safe_token(device_t device)
70		{
71		assert(device != NULL);
72		assert(device->type() == KONAMI);
73		return (konami_state )downcast<legacy_cpu_device >(device)->token();
74		}
75
76		/* flag bits in the cc register */
77		#define CC_C 0x01 /* Carry */
78		#define CC_V 0x02 /* Overflow */
79		#define CC_Z 0x04 /* Zero */
80		#define CC_N 0x08 /* Negative */
81		#define CC_II 0x10 /* Inhibit IRQ */
82		#define CC_H 0x20 /* Half (auxiliary) carry */
83		#define CC_IF 0x40 /* Inhibit FIRQ */
84		#define CC_E 0x80 /* entire state pushed */
85
86		/* Konami registers */
87		#define pPPC cpustate->ppc
88		#define pPC cpustate->pc
89		#define pU cpustate->u
90		#define pS cpustate->s
91		#define pX cpustate->x
92		#define pY cpustate->y
93		#define pD cpustate->d
94
95		#define PPC cpustate->ppc.w.l
96		#define PC cpustate->pc.w.l
97		#define PCD cpustate->pc.d
98		#define U cpustate->u.w.l
99		#define UD cpustate->u.d
100		#define S cpustate->s.w.l
101		#define SD cpustate->s.d
102		#define X cpustate->x.w.l
103		#define XD cpustate->x.d
104		#define Y cpustate->y.w.l
105		#define YD cpustate->y.d
106		#define D cpustate->d.w.l
107		#define A cpustate->d.b.h
108		#define B cpustate->d.b.l
109		#define DP cpustate->dp.b.h
110		#define DPD cpustate->dp.d
111		#define CC cpustate->cc
112
113		#define EAB cpustate->ea.b.l
114		#define EA cpustate->ea.w.l
115		#define EAD cpustate->ea.d
116
117		#define KONAMI_CWAI 8 /* set when CWAI is waiting for an interrupt */
118		#define KONAMI_SYNC 16 /* set when SYNC is waiting for an interrupt */
119		#define KONAMI_LDS 32 /* set when LDS occurred at least once */
120
121		#define RM(cs,Addr) (cs)->program->read_byte(Addr)
122		#define WM(cs,Addr,Value) (cs)->program->write_byte(Addr,Value)
123		#define ROP(cs,Addr) (cs)->direct->read_decrypted_byte(Addr)
124		#define ROP_ARG(cs,Addr) (cs)->direct->read_raw_byte(Addr)
125
126		#define SIGNED(a) (UINT16)(INT16)(INT8)(a)
127
128		/* macros to access memory */
129		#define IMMBYTE(cs,b) { b = ROP_ARG(cs,PCD); PC++; }
130		#define IMMWORD(cs,w) { w.d = (ROP_ARG(cs,PCD)<<8) \| ROP_ARG(cs,PCD+1); PC += 2; }
131
132		#define PUSHBYTE(cs,b) --S; WM(cs,SD,b)
133		#define PUSHWORD(cs,w) --S; WM(cs,SD,w.b.l); --S; WM(cs,SD,w.b.h)
134		#define PULLBYTE(cs,b) b=RM(cs,SD); S++
135		#define PULLWORD(cs,w) w=RM(cs,SD)<<8; S++; w\|=RM(cs,SD); S++
136
137		#define PSHUBYTE(cs,b) --U; WM(cs,UD,b);
138		#define PSHUWORD(cs,w) --U; WM(cs,UD,w.b.l); --U; WM(cs,UD,w.b.h)
139		#define PULUBYTE(cs,b) b=RM(cs,UD); U++
140		#define PULUWORD(cs,w) w=RM(cs,UD)<<8; U++; w\|=RM(cs,UD); U++
141
142		#define CLR_HNZVC CC&=~(CC_H\|CC_N\|CC_Z\|CC_V\|CC_C)
143		#define CLR_NZV CC&=~(CC_N\|CC_Z\|CC_V)
144		#define CLR_NZ CC&=~(CC_N\|CC_Z)
145		#define CLR_HNZC CC&=~(CC_H\|CC_N\|CC_Z\|CC_C)
146		#define CLR_NZVC CC&=~(CC_N\|CC_Z\|CC_V\|CC_C)
147		#define CLR_Z CC&=~(CC_Z)
148		#define CLR_NZC CC&=~(CC_N\|CC_Z\|CC_C)
149		#define CLR_ZC CC&=~(CC_Z\|CC_C)
150
151		/* macros for CC -- CC bits affected should be reset before calling */
152		#define SET_Z(a) if(!a)SEZ
153		#define SET_Z8(a) SET_Z((UINT8)a)
154		#define SET_Z16(a) SET_Z((UINT16)a)
155		#define SET_N8(a) CC\|=((a&0x80)>>4)
156		#define SET_N16(a) CC\|=((a&0x8000)>>12)
157		#define SET_H(a,b,r) CC\|=(((a^b^r)&0x10)<<1)
158		#define SET_C8(a) CC\|=((a&0x100)>>8)
159		#define SET_C16(a) CC\|=((a&0x10000)>>16)
160		#define SET_V8(a,b,r) CC\|=(((a^b^r^(r>>1))&0x80)>>6)
161		#define SET_V16(a,b,r) CC\|=(((a^b^r^(r>>1))&0x8000)>>14)
162
163		static const UINT8 flags8i[256]= /* increment */
164		{
165		CC_Z,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
166		0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
167		0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
168		0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
169		0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
170		0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
171		0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
172		0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
173		CC_N\|CC_V,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,
174		CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,
175		CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,
176		CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,
177		CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,
178		CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,
179		CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,
180		CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N
181		};
182		static const UINT8 flags8d[256]= /* decrement */
183		{
184		CC_Z,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
185		0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
186		0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
187		0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
188		0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
189		0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
190		0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
191		0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,CC_V,
192		CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,
193		CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,
194		CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,
195		CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,
196		CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,
197		CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,
198		CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,
199		CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N
200		};
201		#define SET_FLAGS8I(a) {CC\|=flags8i[(a)&0xff];}
202		#define SET_FLAGS8D(a) {CC\|=flags8d[(a)&0xff];}
203
204		/* combos */
205		#define SET_NZ8(a) {SET_N8(a);SET_Z(a);}
206		#define SET_NZ16(a) {SET_N16(a);SET_Z(a);}
207		#define SET_FLAGS8(a,b,r) {SET_N8(r);SET_Z8(r);SET_V8(a,b,r);SET_C8(r);}
208		#define SET_FLAGS16(a,b,r) {SET_N16(r);SET_Z16(r);SET_V16(a,b,r);SET_C16(r);}
209
210		/* macros for addressing modes (postbytes have their own code) */
211		#define DIRECT(cs) EAD = DPD; IMMBYTE(cs,EAB)
212		#define IMM8(cs) EAD = PCD; PC++
213		#define IMM16(cs) EAD = PCD; PC+=2
214		#define EXTENDED(cs) IMMWORD(cs,(cs)->ea)
215
216		/* macros to set status flags */
217		#if defined(SEC)
218		#undef SEC
219		#endif
220		#define SEC CC\|=CC_C
221		#define CLC CC&=~CC_C
222		#define SEZ CC\|=CC_Z
223		#define CLZ CC&=~CC_Z
224		#define SEN CC\|=CC_N
225		#define CLN CC&=~CC_N
226		#define SEV CC\|=CC_V
227		#define CLV CC&=~CC_V
228		#define SEH CC\|=CC_H
229		#define CLH CC&=~CC_H
230
231		/* macros for convenience */
232		#define DIRBYTE(cs,b) DIRECT(cs); b=RM(cs,EAD)
233		#define DIRWORD(cs,w) DIRECT(cs); w.d=RM16(cs,EAD)
234		#define EXTBYTE(cs,b) EXTENDED(cs); b=RM(cs,EAD)
235		#define EXTWORD(cs,w) EXTENDED(cs); w.d=RM16(cs,EAD)
236
237		/* macros for branch instructions */
238		#define BRANCH(cs,f) { \
239		UINT8 t; \
240		IMMBYTE(cs,t); \
241		if( f ) \
242		{ \
243		PC += SIGNED(t); \
244		} \
245		}
246
247		#define LBRANCH(cs,f) { \
248		PAIR t; \
249		IMMWORD(cs,t); \
250		if( f ) \
251		{ \
252		cpustate->icount -= 1; \
253		PC += t.w.l; \
254		} \
255		}
256
257		#define NXORV ((CC&CC_N)^((CC&CC_V)<<2))
258
259		/* macros for setting/getting registers in TFR/EXG instructions */
260		#define GETREG(val,reg) \
261		switch(reg) { \
262		case 0: val = A; break; \
263		case 1: val = B; break; \
264		case 2: val = X; break; \
265		case 3: val = Y; break; \
266		case 4: val = S; break; /* ? */ \
267		case 5: val = U; break; \
268		default: val = 0xff; logerror("Unknown TFR/EXG idx at PC:%04x\n", PC ); break; \
269		}
270
271		#define SETREG(val,reg) \
272		switch(reg) { \
273		case 0: A = val; break; \
274		case 1: B = val; break; \
275		case 2: X = val; break; \
276		case 3: Y = val; break; \
277		case 4: S = val; break; /* ? */ \
278		case 5: U = val; break; \
279		default: logerror("Unknown TFR/EXG idx at PC:%04x\n", PC ); break; \
280		}
281
282		/* opcode timings */
283		static const UINT8 cycles1[] =
284		{
285		/* 0 1 2 3 4 5 6 7 8 9 A B C D E F */
286		/0/ 1, 1, 1, 1, 1, 1, 1, 1, 4, 4, 4, 4, 5, 5, 5, 5,
287		/1/ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
288		/2/ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
289		/3/ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 7, 6,
290		/4/ 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 4, 4, 3, 3, 4, 4,
291		/5/ 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 1, 1, 1,
292		/6/ 3, 3, 3, 3, 3, 3, 3, 3, 5, 5, 5, 5, 5, 5, 5, 5,
293		/7/ 3, 3, 3, 3, 3, 3, 3, 3, 5, 5, 5, 5, 5, 5, 5, 5,
294		/8/ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 5,
295		/9/ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 6,
296		/A/ 2, 2, 2, 4, 4, 4, 4, 4, 2, 2, 2, 2, 3, 3, 2, 1,
297		/B/ 3, 2, 2,11,22,11, 2, 4, 3, 3, 3, 3, 3, 3, 3, 3,
298		/C/ 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 3, 2,
299		/D/ 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
300		/E/ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
301		/F/ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1
302		};
303
304		INLINE UINT32 RM16( konami_state *cpustate, UINT32 Addr )
305		{
306		UINT32 result = RM(cpustate, Addr) << 8;
307		return result \| RM(cpustate, (Addr+1)&0xffff);
308		}
309
310		INLINE void WM16( konami_state cpustate, UINT32 Addr, PAIR p )
311		{
312		WM(cpustate, Addr, p->b.h );
313		WM(cpustate, (Addr+1)&0xffff, p->b.l );
314		}
315
316
317		static void check_irq_lines(konami_state *cpustate)
318		{
319		if (cpustate->nmi_pending && (cpustate->int_state & KONAMI_LDS))
320		{
321		cpustate->nmi_pending = FALSE;
322
323		/* state already saved by CWAI? */
324		if (cpustate->int_state & KONAMI_CWAI)
325		{
326		cpustate->int_state &= ~KONAMI_CWAI;
327		cpustate->icount -= 7;
328		}
329		else
330		{
331		CC \|= CC_E; /* save entire state */
332		PUSHWORD(cpustate, pPC);
333		PUSHWORD(cpustate, pU);
334		PUSHWORD(cpustate, pY);
335		PUSHWORD(cpustate, pX);
336		PUSHBYTE(cpustate, DP);
337		PUSHBYTE(cpustate, B);
338		PUSHBYTE(cpustate, A);
339		PUSHBYTE(cpustate, CC);
340		cpustate->icount -= 19;
341		}
342		CC \|= CC_IF \| CC_II; /* inhibit FIRQ and IRQ */
343		PCD = RM16(cpustate, 0xfffc);
344		(void)(*cpustate->irq_callback)(cpustate->device, INPUT_LINE_NMI);
345		}
346
347		else if (cpustate->irq_state[KONAMI_FIRQ_LINE] !=CLEAR_LINE && !(CC & CC_IF))
348		{
349		/* fast IRQ */
350		/* state already saved by CWAI? */
351		if (cpustate->int_state & KONAMI_CWAI)
352		{
353		cpustate->int_state &= ~KONAMI_CWAI; /* clear CWAI */
354		cpustate->icount -= 7;
355		}
356		else
357		{
358		CC &= ~CC_E; /* save 'short' state */
359		PUSHWORD(cpustate, pPC);
360		PUSHBYTE(cpustate, CC);
361		cpustate->icount -= 10;
362		}
363		CC \|= CC_IF \| CC_II; /* inhibit FIRQ and IRQ */
364		PCD = RM16(cpustate, 0xfff6);
365		(void)(*cpustate->irq_callback)(cpustate->device, KONAMI_FIRQ_LINE);
366		}
367
368		else if (cpustate->irq_state[KONAMI_IRQ_LINE] != CLEAR_LINE && !(CC & CC_II))
369		{
370		/* standard IRQ */
371		/* state already saved by CWAI? */
372		if (cpustate->int_state & KONAMI_CWAI)
373		{
374		cpustate->int_state &= ~KONAMI_CWAI; /* clear CWAI flag */
375		cpustate->icount -= 7;
376		}
377		else
378		{
379		CC \|= CC_E; /* save entire state */
380		PUSHWORD(cpustate, pPC);
381		PUSHWORD(cpustate, pU);
382		PUSHWORD(cpustate, pY);
383		PUSHWORD(cpustate, pX);
384		PUSHBYTE(cpustate, DP);
385		PUSHBYTE(cpustate, B);
386		PUSHBYTE(cpustate, A);
387		PUSHBYTE(cpustate, CC);
388		cpustate->icount -= 19;
389		}
390		CC \|= CC_II; /* inhibit IRQ */
391		PCD = RM16(cpustate, 0xfff8);
392		(void)(*cpustate->irq_callback)(cpustate->device, KONAMI_IRQ_LINE);
393		}
394		}
395
396
397		/****************************************************************************/
398		/* Reset registers to their initial values */
399		/****************************************************************************/
400		static CPU_INIT( konami )
401		{
402		konami_state *cpustate = get_safe_token(device);
403
404		cpustate->irq_callback = irqcallback;
405		cpustate->device = device;
406		cpustate->program = &device->space(AS_PROGRAM);
407		cpustate->direct = &cpustate->program->direct();
408
409		device->save_item(NAME(PC));
410		device->save_item(NAME(U));
411		device->save_item(NAME(S));
412		device->save_item(NAME(X));
413		device->save_item(NAME(Y));
414		device->save_item(NAME(D));
415		device->save_item(NAME(DP));
416		device->save_item(NAME(CC));
417		device->save_item(NAME(cpustate->int_state));
418		device->save_item(NAME(cpustate->nmi_state));
419		device->save_item(NAME(cpustate->nmi_pending));
420		device->save_item(NAME(cpustate->irq_state[0]));
421		device->save_item(NAME(cpustate->irq_state[1]));
422		}
423
424		static CPU_RESET( konami )
425		{
426		konami_state *cpustate = get_safe_token(device);
427
428		cpustate->int_state = 0;
429		cpustate->nmi_state = CLEAR_LINE;
430		cpustate->nmi_pending = FALSE;
431		cpustate->irq_state[0] = CLEAR_LINE;
432		cpustate->irq_state[1] = CLEAR_LINE;
433
434		DPD = 0; /* Reset direct page register */
435
436		CC \|= CC_II; /* IRQ disabled */
437		CC \|= CC_IF; /* FIRQ disabled */
438
439		PCD = RM16(cpustate, 0xfffe);
440		}
441
442		static CPU_EXIT( konami )
443		{
444		}
445
446		/* Generate interrupts */
447		/****************************************************************************
448		* Set IRQ line state
449		****************************************************************************/
450		static void set_irq_line(konami_state *cpustate, int irqline, int state)
451		{
452		if (state != CLEAR_LINE)
453		cpustate->int_state &= ~KONAMI_SYNC;
454
455		if (irqline == INPUT_LINE_NMI)
456		{
457		if (cpustate->nmi_state == CLEAR_LINE && state != CLEAR_LINE)
458		cpustate->nmi_pending = TRUE;
459		cpustate->nmi_state = state;
460		}
461		else if (irqline < ARRAY_LENGTH(cpustate->irq_state))
462		cpustate->irq_state[irqline] = state;
463		}
464
465		/* includes the static function prototypes and the master opcode table */
466		#include "konamtbl.c"
467
468		/* includes the actual opcode implementations */
469		#include "konamops.c"
470
471		/* execute instructions on this CPU until icount expires */
472		static CPU_EXECUTE( konami )
473		{
474		konami_state *cpustate = get_safe_token(device);
475
476		check_irq_lines(cpustate);
477
478		if( cpustate->int_state & (KONAMI_CWAI \| KONAMI_SYNC) )
479		{
480		cpustate->icount = 0;
481		}
482		else
483		{
484		do
485		{
486		UINT8 ireg;
487
488		pPPC = pPC;
489
490		debugger_instruction_hook(device, PCD);
491
492		cpustate->ireg = ireg = ROP(cpustate, PCD);
493		PC++;
494
495		(*konami_main[ireg])(cpustate);
496
497		cpustate->icount -= cycles1[ireg];
498
499		} while( cpustate->icount > 0 );
500		}
501		}
502
503
504		void konami_configure_set_lines(device_t *device, konami_set_lines_func func)
505		{
506		konami_state *cpustate = get_safe_token(device);
507		cpustate->setlines_callback = func;
508		}
509
510
511		/**************************************************************************
512		* Generic set_info
513		**************************************************************************/
514
515		static CPU_SET_INFO( konami )
516		{
517		konami_state *cpustate = get_safe_token(device);
518		switch (state)
519		{
520		/* --- the following bits of info are set as 64-bit signed integers --- */
521		case CPUINFO_INT_INPUT_STATE + KONAMI_IRQ_LINE: set_irq_line(cpustate, KONAMI_IRQ_LINE, info->i); break;
522		case CPUINFO_INT_INPUT_STATE + KONAMI_FIRQ_LINE:set_irq_line(cpustate, KONAMI_FIRQ_LINE, info->i); break;
523		case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: set_irq_line(cpustate, INPUT_LINE_NMI, info->i); break;
524
525		case CPUINFO_INT_PC:
526		case CPUINFO_INT_REGISTER + KONAMI_PC: PC = info->i; break;
527		case CPUINFO_INT_SP:
528		case CPUINFO_INT_REGISTER + KONAMI_S: S = info->i; break;
529		case CPUINFO_INT_REGISTER + KONAMI_CC: CC = info->i; break;
530		case CPUINFO_INT_REGISTER + KONAMI_U: U = info->i; break;
531		case CPUINFO_INT_REGISTER + KONAMI_A: A = info->i; break;
532		case CPUINFO_INT_REGISTER + KONAMI_B: B = info->i; break;
533		case CPUINFO_INT_REGISTER + KONAMI_X: X = info->i; break;
534		case CPUINFO_INT_REGISTER + KONAMI_Y: Y = info->i; break;
535		case CPUINFO_INT_REGISTER + KONAMI_DP: DP = info->i; break;
536		}
537		}
538
539
540
541		/**************************************************************************
542		* Generic get_info
543		**************************************************************************/
544
545		CPU_GET_INFO( konami )
546		{
547		konami_state *cpustate = (device != NULL && device->token() != NULL) ? get_safe_token(device) : NULL;
548		switch (state)
549		{
550		/* --- the following bits of info are returned as 64-bit signed integers --- */
551		case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(konami_state); break;
552		case CPUINFO_INT_INPUT_LINES: info->i = 2; break;
553		case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0; break;
554		case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_BIG; break;
555		case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break;
556		case CPUINFO_INT_CLOCK_DIVIDER: info->i = 1; break;
557		case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 1; break;
558		case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 4; break;
559		case CPUINFO_INT_MIN_CYCLES: info->i = 1; break;
560		case CPUINFO_INT_MAX_CYCLES: info->i = 13; break;
561
562		case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM: info->i = 8; break;
563		case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 16; break;
564		case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = 0; break;
565		case CPUINFO_INT_DATABUS_WIDTH + AS_DATA: info->i = 0; break;
566		case CPUINFO_INT_ADDRBUS_WIDTH + AS_DATA: info->i = 0; break;
567		case CPUINFO_INT_ADDRBUS_SHIFT + AS_DATA: info->i = 0; break;
568		case CPUINFO_INT_DATABUS_WIDTH + AS_IO: info->i = 0; break;
569		case CPUINFO_INT_ADDRBUS_WIDTH + AS_IO: info->i = 0; break;
570		case CPUINFO_INT_ADDRBUS_SHIFT + AS_IO: info->i = 0; break;
571
572		case CPUINFO_INT_INPUT_STATE + KONAMI_IRQ_LINE: info->i = cpustate->irq_state[KONAMI_IRQ_LINE]; break;
573		case CPUINFO_INT_INPUT_STATE + KONAMI_FIRQ_LINE:info->i = cpustate->irq_state[KONAMI_FIRQ_LINE]; break;
574		case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: info->i = cpustate->nmi_state; break;
575
576		case CPUINFO_INT_PREVIOUSPC: info->i = PPC; break;
577
578		case CPUINFO_INT_PC:
579		case CPUINFO_INT_REGISTER + KONAMI_PC: info->i = PC; break;
580		case CPUINFO_INT_SP:
581		case CPUINFO_INT_REGISTER + KONAMI_S: info->i = S; break;
582		case CPUINFO_INT_REGISTER + KONAMI_CC: info->i = CC; break;
583		case CPUINFO_INT_REGISTER + KONAMI_U: info->i = U; break;
584		case CPUINFO_INT_REGISTER + KONAMI_A: info->i = A; break;
585		case CPUINFO_INT_REGISTER + KONAMI_B: info->i = B; break;
586		case CPUINFO_INT_REGISTER + KONAMI_X: info->i = X; break;
587		case CPUINFO_INT_REGISTER + KONAMI_Y: info->i = Y; break;
588		case CPUINFO_INT_REGISTER + KONAMI_DP: info->i = DP; break;
589
590		/* --- the following bits of info are returned as pointers to data or functions --- */
591		case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(konami); break;
592		case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(konami); break;
593		case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(konami); break;
594		case CPUINFO_FCT_EXIT: info->exit = CPU_EXIT_NAME(konami); break;
595		case CPUINFO_FCT_EXECUTE: info->execute = CPU_EXECUTE_NAME(konami); break;
596		case CPUINFO_FCT_BURN: info->burn = NULL; break;
597		case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(konami);break;
598		case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &cpustate->icount; break;
599
600		/* --- the following bits of info are returned as NULL-terminated strings --- */
601		case CPUINFO_STR_NAME: strcpy(info->s, "KONAMI"); break;
602		case CPUINFO_STR_FAMILY: strcpy(info->s, "KONAMI 5000x"); break;
603		case CPUINFO_STR_VERSION: strcpy(info->s, "1.0"); break;
604		case CPUINFO_STR_SOURCE_FILE: strcpy(info->s, __FILE__); break;
605		case CPUINFO_STR_CREDITS: strcpy(info->s, "Copyright Nicola Salmoria and the MAME Team"); break;
606
607		case CPUINFO_STR_FLAGS:
608		sprintf(info->s, "%c%c%c%c%c%c%c%c",
609		cpustate->cc & 0x80 ? 'E':'.',
610		cpustate->cc & 0x40 ? 'F':'.',
611		cpustate->cc & 0x20 ? 'H':'.',
612		cpustate->cc & 0x10 ? 'I':'.',
613		cpustate->cc & 0x08 ? 'N':'.',
614		cpustate->cc & 0x04 ? 'Z':'.',
615		cpustate->cc & 0x02 ? 'V':'.',
616		cpustate->cc & 0x01 ? 'C':'.');
617		break;
618
619		case CPUINFO_STR_REGISTER + KONAMI_PC: sprintf(info->s, "PC:%04X", cpustate->pc.w.l); break;
620		case CPUINFO_STR_REGISTER + KONAMI_S: sprintf(info->s, "S:%04X", cpustate->s.w.l); break;
621		case CPUINFO_STR_REGISTER + KONAMI_CC: sprintf(info->s, "CC:%02X", cpustate->cc); break;
622		case CPUINFO_STR_REGISTER + KONAMI_U: sprintf(info->s, "U:%04X", cpustate->u.w.l); break;
623		case CPUINFO_STR_REGISTER + KONAMI_A: sprintf(info->s, "A:%02X", cpustate->d.b.h); break;
624		case CPUINFO_STR_REGISTER + KONAMI_B: sprintf(info->s, "B:%02X", cpustate->d.b.l); break;
625		case CPUINFO_STR_REGISTER + KONAMI_X: sprintf(info->s, "X:%04X", cpustate->x.w.l); break;
626		case CPUINFO_STR_REGISTER + KONAMI_Y: sprintf(info->s, "Y:%04X", cpustate->y.w.l); break;
627		case CPUINFO_STR_REGISTER + KONAMI_DP: sprintf(info->s, "DP:%02X", cpustate->dp.b.h); break;
628		}
629		}
630
631		DEFINE_LEGACY_CPU_DEVICE(KONAMI, konami);

trunk/src/emu/cpu/m6809/6809ops.c
r21564	r21565
1		/*
2
3		HNZVC
4
5		? = undefined
6		* = affected
7		- = unaffected
8		0 = cleared
9		1 = set
10		# = CCr directly affected by instruction
11		@ = special - carry set if bit 7 is set
12
13		*/
14
15		#define OP_HANDLER(_name) void m6809_base_device::_name()
16
17		OP_HANDLER( illegal )
18		{
19		logerror("M6809: illegal opcode at %04x\n",PC);
20		}
21
22		void m6809_base_device::IIError()
23		{
24		illegal(); // Vector to Trap handler
25		}
26
27		/* $00 NEG direct ?**** */
28		OP_HANDLER( neg_di )
29		{
30		UINT16 r,t;
31		DIRBYTE(t);
32		r = -t;
33		CLR_NZVC;
34		SET_FLAGS8(0,t,r);
35		WM(EAD,r);
36		}
37
38		/* $01 ILLEGAL, same as $00 */
39
40		/* $02 ILLEGAL, same as $03 */
41
42		/* $03 COM direct -*01 /
43		OP_HANDLER( com_di )
44		{
45		UINT8 t;
46		DIRBYTE(t);
47		t = ~t;
48		CLR_NZV;
49		SET_NZ8(t);
50		SEC;
51		WM(EAD,t);
52		}
53
54		/* $04 LSR direct -0- */
55		OP_HANDLER( lsr_di )
56		{
57		UINT8 t;
58		DIRBYTE(t);
59		CLR_NZC;
60		CC \|= (t & CC_C);
61		t >>= 1;
62		SET_Z8(t);
63		WM(EAD,t);
64		}
65
66		/* $05 ILLEGAL, same as $04 */
67
68		/* $06 ROR direct -*- */
69		OP_HANDLER( ror_di )
70		{
71		UINT8 t,r;
72		DIRBYTE(t);
73		r= (CC & CC_C) << 7;
74		CLR_NZC;
75		CC \|= (t & CC_C);
76		r \|= t>>1;
77		SET_NZ8(r);
78		WM(EAD,r);
79		}
80
81		/* $07 ASR direct ?*- */
82		OP_HANDLER( asr_di )
83		{
84		UINT8 t;
85		DIRBYTE(t);
86		CLR_NZC;
87		CC \|= (t & CC_C);
88		t = (t & 0x80) \| (t >> 1);
89		SET_NZ8(t);
90		WM(EAD,t);
91		}
92
93		/* $08 ASL direct ?**** */
94		OP_HANDLER( asl_di )
95		{
96		UINT16 t,r;
97		DIRBYTE(t);
98		r = t << 1;
99		CLR_NZVC;
100		SET_FLAGS8(t,t,r);
101		WM(EAD,r);
102		}
103
104		/* $09 ROL direct -**** */
105		OP_HANDLER( rol_di )
106		{
107		UINT16 t,r;
108		DIRBYTE(t);
109		r = (CC & CC_C) \| (t << 1);
110		CLR_NZVC;
111		SET_FLAGS8(t,t,r);
112		WM(EAD,r);
113		}
114
115		/* $0A DEC direct -**- /
116		OP_HANDLER( dec_di )
117		{
118		UINT8 t;
119		DIRBYTE(t);
120		--t;
121		CLR_NZV;
122		SET_FLAGS8D(t);
123		WM(EAD,t);
124		}
125
126		/* $0B ILLEGAL, same as $0A */
127
128		/* $OC INC direct -**- /
129		OP_HANDLER( inc_di )
130		{
131		UINT8 t;
132		DIRBYTE(t);
133		++t;
134		CLR_NZV;
135		SET_FLAGS8I(t);
136		WM(EAD,t);
137		}
138
139		/* $OD TST direct -*0- /
140		OP_HANDLER( tst_di )
141		{
142		UINT8 t;
143		DIRBYTE(t);
144		CLR_NZV;
145		SET_NZ8(t);
146		}
147
148		/* $0E JMP direct ----- */
149		OP_HANDLER( jmp_di )
150		{
151		DIRECT;
152		PCD = EAD;
153		}
154
155		/* $0F CLR direct -0100 */
156		OP_HANDLER( clr_di )
157		{
158		DIRECT;
159		(void)RM(EAD);
160		WM(EAD,0);
161		CLR_NZVC;
162		SEZ;
163		}
164
165		/* $10 FLAG */
166
167		/* $11 FLAG */
168
169		/* $12 NOP inherent ----- */
170		OP_HANDLER( nop )
171		{
172		;
173		}
174
175		/* $13 SYNC inherent ----- */
176		OP_HANDLER( sync )
177		{
178		/* SYNC stops processing instructions until an interrupt request happens. */
179		/* This doesn't require the corresponding interrupt to be enabled: if it */
180		/* is disabled, execution continues with the next instruction. */
181		m_int_state \|= M6809_SYNC; /* HJB 990227 */
182		check_irq_lines();
183		/* if M6809_SYNC has not been cleared by check_irq_lines(),
184		* stop execution until the interrupt lines change. */
185		if( m_int_state & M6809_SYNC )
186		if (m_icount > 0) m_icount = 0;
187		}
188
189		/* $14 ILLEGAL */
190
191		/* $15 ILLEGAL */
192
193		/* $16 LBRA relative ----- */
194		OP_HANDLER( lbra )
195		{
196		IMMWORD(EAP);
197		PC += EA;
198		}
199
200		/* $17 LBSR relative ----- */
201		OP_HANDLER( lbsr )
202		{
203		IMMWORD(EAP);
204		PUSHWORD(pPC);
205		PC += EA;
206		}
207
208		/* $18 ILLEGAL */
209
210		/* $19 DAA inherent (A) -*0 */
211		OP_HANDLER( daa )
212		{
213		UINT8 msn, lsn;
214		UINT16 t, cf = 0;
215		msn = A & 0xf0; lsn = A & 0x0f;
216		if( lsn>0x09 \|\| CC & CC_H) cf \|= 0x06;
217		if( msn>0x80 && lsn>0x09 ) cf \|= 0x60;
218		if( msn>0x90 \|\| CC & CC_C) cf \|= 0x60;
219		t = cf + A;
220		CLR_NZV; /* keep carry from previous operation */
221		SET_NZ8((UINT8)t); SET_C8(t);
222		A = t;
223		}
224
225		/* $1A ORCC immediate ##### */
226		OP_HANDLER( orcc )
227		{
228		UINT8 t;
229		IMMBYTE(t);
230		CC \|= t;
231		check_irq_lines(); /* HJB 990116 */
232		}
233
234		/* $1B ILLEGAL */
235
236		/* $1C ANDCC immediate ##### */
237		OP_HANDLER( andcc )
238		{
239		UINT8 t;
240		IMMBYTE(t);
241		CC &= t;
242		check_irq_lines(); /* HJB 990116 */
243		}
244
245		/* $1D SEX inherent -*-- /
246		OP_HANDLER( sex )
247		{
248		UINT16 t;
249		t = SIGNED(B);
250		D = t;
251		// CLR_NZV; Tim Lindner 20020905: verified that V flag is not affected
252		CLR_NZ;
253		SET_NZ16(t);
254		}
255
256		/* $1E EXG inherent ----- */
257		OP_HANDLER( exg )
258		{
259		UINT16 t1,t2;
260		UINT8 tb;
261
262		IMMBYTE(tb);
263		if( (tb^(tb>>4)) & 0x08 ) /* HJB 990225: mixed 8/16 bit case? */
264		{
265		/* transfer $ff to both registers */
266		t1 = t2 = 0xff;
267		}
268		else
269		{
270		switch(tb>>4) {
271		case 0: t1 = D; break;
272		case 1: t1 = X; break;
273		case 2: t1 = Y; break;
274		case 3: t1 = U; break;
275		case 4: t1 = S; break;
276		case 5: t1 = PC; break;
277		case 8: t1 = A; break;
278		case 9: t1 = B; break;
279		case 10: t1 = CC; break;
280		case 11: t1 = DP; break;
281		default: t1 = 0xff;
282		}
283		switch(tb&15) {
284		case 0: t2 = D; break;
285		case 1: t2 = X; break;
286		case 2: t2 = Y; break;
287		case 3: t2 = U; break;
288		case 4: t2 = S; break;
289		case 5: t2 = PC; break;
290		case 8: t2 = A; break;
291		case 9: t2 = B; break;
292		case 10: t2 = CC; break;
293		case 11: t2 = DP; break;
294		default: t2 = 0xff;
295		}
296		}
297		switch(tb>>4) {
298		case 0: D = t2; break;
299		case 1: X = t2; break;
300		case 2: Y = t2; break;
301		case 3: U = t2; break;
302		case 4: S = t2; break;
303		case 5: PC = t2; break;
304		case 8: A = t2; break;
305		case 9: B = t2; break;
306		case 10: CC = t2; break;
307		case 11: DP = t2; break;
308		}
309		switch(tb&15) {
310		case 0: D = t1; break;
311		case 1: X = t1; break;
312		case 2: Y = t1; break;
313		case 3: U = t1; break;
314		case 4: S = t1; break;
315		case 5: PC = t1; break;
316		case 8: A = t1; break;
317		case 9: B = t1; break;
318		case 10: CC = t1; break;
319		case 11: DP = t1; break;
320		}
321		}
322
323		/* $1F TFR inherent ----- */
324		OP_HANDLER( tfr )
325		{
326		UINT8 tb;
327		UINT16 t;
328
329		IMMBYTE(tb);
330		if( (tb^(tb>>4)) & 0x08 ) /* HJB 990225: mixed 8/16 bit case? */
331		{
332		/* transfer $ff to register */
333		t = 0xff;
334		}
335		else
336		{
337		switch(tb>>4) {
338		case 0: t = D; break;
339		case 1: t = X; break;
340		case 2: t = Y; break;
341		case 3: t = U; break;
342		case 4: t = S; break;
343		case 5: t = PC; break;
344		case 8: t = A; break;
345		case 9: t = B; break;
346		case 10: t = CC; break;
347		case 11: t = DP; break;
348		default: t = 0xff;
349		}
350		}
351		switch(tb&15) {
352		case 0: D = t; break;
353		case 1: X = t; break;
354		case 2: Y = t; break;
355		case 3: U = t; break;
356		case 4: S = t; break;
357		case 5: PC = t; break;
358		case 8: A = t; break;
359		case 9: B = t; break;
360		case 10: CC = t; break;
361		case 11: DP = t; break;
362		}
363		}
364
365		/* $20 BRA relative ----- */
366		OP_HANDLER( bra )
367		{
368		UINT8 t;
369		IMMBYTE(t);
370		PC += SIGNED(t);
371		}
372
373		/* $21 BRN relative ----- */
374		static UINT8 m6809_brn_t; // hack around GCC 4.6 error because we need the side effects of IMMBYTE
375		OP_HANDLER( brn )
376		{
377		IMMBYTE(m6809_brn_t);
378		}
379
380		/* $1021 LBRN relative ----- */
381		OP_HANDLER( lbrn )
382		{
383		IMMWORD(EAP);
384		}
385
386		/* $22 BHI relative ----- */
387		OP_HANDLER( bhi )
388		{
389		BRANCH( !(CC & (CC_Z\|CC_C)) );
390		}
391
392		/* $1022 LBHI relative ----- */
393		OP_HANDLER( lbhi )
394		{
395		LBRANCH( !(CC & (CC_Z\|CC_C)) );
396		}
397
398		/* $23 BLS relative ----- */
399		OP_HANDLER( bls )
400		{
401		BRANCH( (CC & (CC_Z\|CC_C)) );
402		}
403
404		/* $1023 LBLS relative ----- */
405		OP_HANDLER( lbls )
406		{
407		LBRANCH( (CC&(CC_Z\|CC_C)) );
408		}
409
410		/* $24 BCC relative ----- */
411		OP_HANDLER( bcc )
412		{
413		BRANCH( !(CC&CC_C) );
414		}
415
416		/* $1024 LBCC relative ----- */
417		OP_HANDLER( lbcc )
418		{
419		LBRANCH( !(CC&CC_C) );
420		}
421
422		/* $25 BCS relative ----- */
423		OP_HANDLER( bcs )
424		{
425		BRANCH( (CC&CC_C) );
426		}
427
428		/* $1025 LBCS relative ----- */
429		OP_HANDLER( lbcs )
430		{
431		LBRANCH( (CC&CC_C) );
432		}
433
434		/* $26 BNE relative ----- */
435		OP_HANDLER( bne )
436		{
437		BRANCH( !(CC&CC_Z) );
438		}
439
440		/* $1026 LBNE relative ----- */
441		OP_HANDLER( lbne )
442		{
443		LBRANCH( !(CC&CC_Z) );
444		}
445
446		/* $27 BEQ relative ----- */
447		OP_HANDLER( beq )
448		{
449		BRANCH( (CC&CC_Z) );
450		}
451
452		/* $1027 LBEQ relative ----- */
453		OP_HANDLER( lbeq )
454		{
455		LBRANCH( (CC&CC_Z) );
456		}
457
458		/* $28 BVC relative ----- */
459		OP_HANDLER( bvc )
460		{
461		BRANCH( !(CC&CC_V) );
462		}
463
464		/* $1028 LBVC relative ----- */
465		OP_HANDLER( lbvc )
466		{
467		LBRANCH( !(CC&CC_V) );
468		}
469
470		/* $29 BVS relative ----- */
471		OP_HANDLER( bvs )
472		{
473		BRANCH( (CC&CC_V) );
474		}
475
476		/* $1029 LBVS relative ----- */
477		OP_HANDLER( lbvs )
478		{
479		LBRANCH( (CC&CC_V) );
480		}
481
482		/* $2A BPL relative ----- */
483		OP_HANDLER( bpl )
484		{
485		BRANCH( !(CC&CC_N) );
486		}
487
488		/* $102A LBPL relative ----- */
489		OP_HANDLER( lbpl )
490		{
491		LBRANCH( !(CC&CC_N) );
492		}
493
494		/* $2B BMI relative ----- */
495		OP_HANDLER( bmi )
496		{
497		BRANCH( (CC&CC_N) );
498		}
499
500		/* $102B LBMI relative ----- */
501		OP_HANDLER( lbmi )
502		{
503		LBRANCH( (CC&CC_N) );
504		}
505
506		/* $2C BGE relative ----- */
507		OP_HANDLER( bge )
508		{
509		BRANCH( !NXORV );
510		}
511
512		/* $102C LBGE relative ----- */
513		OP_HANDLER( lbge )
514		{
515		LBRANCH( !NXORV );
516		}
517
518		/* $2D BLT relative ----- */
519		OP_HANDLER( blt )
520		{
521		BRANCH( NXORV );
522		}
523
524		/* $102D LBLT relative ----- */
525		OP_HANDLER( lblt )
526		{
527		LBRANCH( NXORV );
528		}
529
530		/* $2E BGT relative ----- */
531		OP_HANDLER( bgt )
532		{
533		BRANCH( !(NXORV \|\| (CC&CC_Z)) );
534		}
535
536		/* $102E LBGT relative ----- */
537		OP_HANDLER( lbgt )
538		{
539		LBRANCH( !(NXORV \|\| (CC&CC_Z)) );
540		}
541
542		/* $2F BLE relative ----- */
543		OP_HANDLER( ble )
544		{
545		BRANCH( (NXORV \|\| (CC&CC_Z)) );
546		}
547
548		/* $102F LBLE relative ----- */
549		OP_HANDLER( lble )
550		{
551		LBRANCH( (NXORV \|\| (CC&CC_Z)) );
552		}
553
554		/* $30 LEAX indexed ---- /
555		OP_HANDLER( leax )
556		{
557		fetch_effective_address();
558		X = EA;
559		CLR_Z;
560		SET_Z(X);
561		}
562
563		/* $31 LEAY indexed ---- /
564		OP_HANDLER( leay )
565		{
566		fetch_effective_address();
567		Y = EA;
568		CLR_Z;
569		SET_Z(Y);
570		}
571
572		/* $32 LEAS indexed ----- */
573		OP_HANDLER( leas )
574		{
575		fetch_effective_address();
576		S = EA;
577		m_int_state \|= M6809_LDS;
578		}
579
580		/* $33 LEAU indexed ----- */
581		OP_HANDLER( leau )
582		{
583		fetch_effective_address();
584		U = EA;
585		}
586
587		/* $34 PSHS inherent ----- */
588		OP_HANDLER( pshs )
589		{
590		UINT8 t;
591		IMMBYTE(t);
592		if( t&0x80 ) { PUSHWORD(pPC); m_icount -= 2; }
593		if( t&0x40 ) { PUSHWORD(pU); m_icount -= 2; }
594		if( t&0x20 ) { PUSHWORD(pY); m_icount -= 2; }
595		if( t&0x10 ) { PUSHWORD(pX); m_icount -= 2; }
596		if( t&0x08 ) { PUSHBYTE(DP); m_icount -= 1; }
597		if( t&0x04 ) { PUSHBYTE(B); m_icount -= 1; }
598		if( t&0x02 ) { PUSHBYTE(A); m_icount -= 1; }
599		if( t&0x01 ) { PUSHBYTE(CC); m_icount -= 1; }
600		}
601
602		/* 35 PULS inherent ----- */
603		OP_HANDLER( puls )
604		{
605		UINT8 t;
606		IMMBYTE(t);
607		if( t&0x01 ) { PULLBYTE(CC); m_icount -= 1; }
608		if( t&0x02 ) { PULLBYTE(A); m_icount -= 1; }
609		if( t&0x04 ) { PULLBYTE(B); m_icount -= 1; }
610		if( t&0x08 ) { PULLBYTE(DP); m_icount -= 1; }
611		if( t&0x10 ) { PULLWORD(XD); m_icount -= 2; }
612		if( t&0x20 ) { PULLWORD(YD); m_icount -= 2; }
613		if( t&0x40 ) { PULLWORD(UD); m_icount -= 2; }
614		if( t&0x80 ) { PULLWORD(PCD); m_icount -= 2; }
615
616		/* HJB 990225: moved check after all PULLs */
617		if( t&0x01 ) { check_irq_lines(); }
618		}
619
620		/* $36 PSHU inherent ----- */
621		OP_HANDLER( pshu )
622		{
623		UINT8 t;
624		IMMBYTE(t);
625		if( t&0x80 ) { PSHUWORD(pPC); m_icount -= 2; }
626		if( t&0x40 ) { PSHUWORD(pS); m_icount -= 2; }
627		if( t&0x20 ) { PSHUWORD(pY); m_icount -= 2; }
628		if( t&0x10 ) { PSHUWORD(pX); m_icount -= 2; }
629		if( t&0x08 ) { PSHUBYTE(DP); m_icount -= 1; }
630		if( t&0x04 ) { PSHUBYTE(B); m_icount -= 1; }
631		if( t&0x02 ) { PSHUBYTE(A); m_icount -= 1; }
632		if( t&0x01 ) { PSHUBYTE(CC); m_icount -= 1; }
633		}
634
635		/* 37 PULU inherent ----- */
636		OP_HANDLER( pulu )
637		{
638		UINT8 t;
639		IMMBYTE(t);
640		if( t&0x01 ) { PULUBYTE(CC); m_icount -= 1; }
641		if( t&0x02 ) { PULUBYTE(A); m_icount -= 1; }
642		if( t&0x04 ) { PULUBYTE(B); m_icount -= 1; }
643		if( t&0x08 ) { PULUBYTE(DP); m_icount -= 1; }
644		if( t&0x10 ) { PULUWORD(XD); m_icount -= 2; }
645		if( t&0x20 ) { PULUWORD(YD); m_icount -= 2; }
646		if( t&0x40 ) { PULUWORD(SD); m_icount -= 2; }
647		if( t&0x80 ) { PULUWORD(PCD); m_icount -= 2; }
648
649		/* HJB 990225: moved check after all PULLs */
650		if( t&0x01 ) { check_irq_lines(); }
651		}
652
653		/* $38 ILLEGAL */
654
655		/* $39 RTS inherent ----- */
656		OP_HANDLER( rts )
657		{
658		PULLWORD(PCD);
659		}
660
661		/* $3A ABX inherent ----- */
662		OP_HANDLER( abx )
663		{
664		X += B;
665		}
666
667		/* $3B RTI inherent ##### */
668		OP_HANDLER( rti )
669		{
670		UINT8 t;
671		PULLBYTE(CC);
672		t = CC & CC_E; /* HJB 990225: entire state saved? */
673		if(t)
674		{
675		m_icount -= 9;
676		PULLBYTE(A);
677		PULLBYTE(B);
678		PULLBYTE(DP);
679		PULLWORD(XD);
680		PULLWORD(YD);
681		PULLWORD(UD);
682		}
683		PULLWORD(PCD);
684		check_irq_lines(); /* HJB 990116 */
685		}
686
687		/* $3C CWAI inherent ----1 */
688		OP_HANDLER( cwai )
689		{
690		UINT8 t;
691		IMMBYTE(t);
692		CC &= t;
693		/*
694		* CWAI stacks the entire machine state on the hardware stack,
695		* then waits for an interrupt; when the interrupt is taken
696		* later, the state is not saved again after CWAI.
697		*/
698		CC \|= CC_E; /* HJB 990225: save entire state */
699		PUSHWORD(pPC);
700		PUSHWORD(pU);
701		PUSHWORD(pY);
702		PUSHWORD(pX);
703		PUSHBYTE(DP);
704		PUSHBYTE(B);
705		PUSHBYTE(A);
706		PUSHBYTE(CC);
707		m_int_state \|= M6809_CWAI; /* HJB 990228 */
708		check_irq_lines(); /* HJB 990116 */
709		if( m_int_state & M6809_CWAI )
710		if( m_icount > 0 )
711		m_icount = 0;
712		}
713
714		/* $3D MUL inherent ---@ /
715		OP_HANDLER( mul )
716		{
717		UINT16 t;
718		t = A * B;
719		CLR_ZC; SET_Z16(t); if(t&0x80) SEC;
720		D = t;
721		}
722
723		/* $3E ILLEGAL */
724
725		/* $3F SWI (SWI2 SWI3) absolute indirect ----- */
726		OP_HANDLER( swi )
727		{
728		CC \|= CC_E; /* HJB 980225: save entire state */
729		PUSHWORD(pPC);
730		PUSHWORD(pU);
731		PUSHWORD(pY);
732		PUSHWORD(pX);
733		PUSHBYTE(DP);
734		PUSHBYTE(B);
735		PUSHBYTE(A);
736		PUSHBYTE(CC);
737		CC \|= CC_IF \| CC_II; /* inhibit FIRQ and IRQ */
738		PCD=RM16(0xfffa);
739		}
740
741		/* $103F SWI2 absolute indirect ----- */
742		OP_HANDLER( swi2 )
743		{
744		CC \|= CC_E; /* HJB 980225: save entire state */
745		PUSHWORD(pPC);
746		PUSHWORD(pU);
747		PUSHWORD(pY);
748		PUSHWORD(pX);
749		PUSHBYTE(DP);
750		PUSHBYTE(B);
751		PUSHBYTE(A);
752		PUSHBYTE(CC);
753		PCD = RM16(0xfff4);
754		}
755
756		/* $113F SWI3 absolute indirect ----- */
757		OP_HANDLER( swi3 )
758		{
759		CC \|= CC_E; /* HJB 980225: save entire state */
760		PUSHWORD(pPC);
761		PUSHWORD(pU);
762		PUSHWORD(pY);
763		PUSHWORD(pX);
764		PUSHBYTE(DP);
765		PUSHBYTE(B);
766		PUSHBYTE(A);
767		PUSHBYTE(CC);
768		PCD = RM16(0xfff2);
769		}
770
771		/* $40 NEGA inherent ?**** */
772		OP_HANDLER( nega )
773		{
774		UINT16 r;
775		r = -A;
776		CLR_NZVC;
777		SET_FLAGS8(0,A,r);
778		A = r;
779		}
780
781		/* $41 ILLEGAL, same as $40 */
782
783		/* $42 ILLEGAL, same as $43 */
784
785		/* $43 COMA inherent -*01 /
786		OP_HANDLER( coma )
787		{
788		A = ~A;
789		CLR_NZV;
790		SET_NZ8(A);
791		SEC;
792		}
793
794		/* $44 LSRA inherent -0- */
795		OP_HANDLER( lsra )
796		{
797		CLR_NZC;
798		CC \|= (A & CC_C);
799		A >>= 1;
800		SET_Z8(A);
801		}
802
803		/* $45 ILLEGAL, same as $44 */
804
805		/* $46 RORA inherent -*- */
806		OP_HANDLER( rora )
807		{
808		UINT8 r;
809		r = (CC & CC_C) << 7;
810		CLR_NZC;
811		CC \|= (A & CC_C);
812		r \|= A >> 1;
813		SET_NZ8(r);
814		A = r;
815		}
816
817		/* $47 ASRA inherent ?*- */
818		OP_HANDLER( asra )
819		{
820		CLR_NZC;
821		CC \|= (A & CC_C);
822		A = (A & 0x80) \| (A >> 1);
823		SET_NZ8(A);
824		}
825
826		/* $48 ASLA inherent ?**** */
827		OP_HANDLER( asla )
828		{
829		UINT16 r;
830		r = A << 1;
831		CLR_NZVC;
832		SET_FLAGS8(A,A,r);
833		A = r;
834		}
835
836		/* $49 ROLA inherent -**** */
837		OP_HANDLER( rola )
838		{
839		UINT16 t,r;
840		t = A;
841		r = (CC & CC_C) \| (t<<1);
842		CLR_NZVC; SET_FLAGS8(t,t,r);
843		A = r;
844		}
845
846		/* $4A DECA inherent -**- /
847		OP_HANDLER( deca )
848		{
849		--A;
850		CLR_NZV;
851		SET_FLAGS8D(A);
852		}
853
854		/* $4B ILLEGAL, same as $4A */
855
856		/* $4C INCA inherent -**- /
857		OP_HANDLER( inca )
858		{
859		++A;
860		CLR_NZV;
861		SET_FLAGS8I(A);
862		}
863
864		/* $4D TSTA inherent -*0- /
865		OP_HANDLER( tsta )
866		{
867		CLR_NZV;
868		SET_NZ8(A);
869		}
870
871		/* $4E ILLEGAL, same as $4F */
872
873		/* $4F CLRA inherent -0100 */
874		OP_HANDLER( clra )
875		{
876		A = 0;
877		CLR_NZVC; SEZ;
878		}
879
880		/* $50 NEGB inherent ?**** */
881		OP_HANDLER( negb )
882		{
883		UINT16 r;
884		r = -B;
885		CLR_NZVC;
886		SET_FLAGS8(0,B,r);
887		B = r;
888		}
889
890		/* $51 ILLEGAL, same as $50 */
891
892		/* $52 ILLEGAL, same as $53 */
893
894		/* $53 COMB inherent -*01 /
895		OP_HANDLER( comb )
896		{
897		B = ~B;
898		CLR_NZV;
899		SET_NZ8(B);
900		SEC;
901		}
902
903		/* $54 LSRB inherent -0- */
904		OP_HANDLER( lsrb )
905		{
906		CLR_NZC;
907		CC \|= (B & CC_C);
908		B >>= 1;
909		SET_Z8(B);
910		}
911
912		/* $55 ILLEGAL, same as $54 */
913
914		/* $56 RORB inherent -*- */
915		OP_HANDLER( rorb )
916		{
917		UINT8 r;
918		r = (CC & CC_C) << 7;
919		CLR_NZC;
920		CC \|= (B & CC_C);
921		r \|= B >> 1;
922		SET_NZ8(r);
923		B = r;
924		}
925
926		/* $57 ASRB inherent ?*- */
927		OP_HANDLER( asrb )
928		{
929		CLR_NZC;
930		CC \|= (B & CC_C);
931		B= (B & 0x80) \| (B >> 1);
932		SET_NZ8(B);
933		}
934
935		/* $58 ASLB inherent ?**** */
936		OP_HANDLER( aslb )
937		{
938		UINT16 r;
939		r = B << 1;
940		CLR_NZVC;
941		SET_FLAGS8(B,B,r);
942		B = r;
943		}
944
945		/* $59 ROLB inherent -**** */
946		OP_HANDLER( rolb )
947		{
948		UINT16 t,r;
949		t = B;
950		r = CC & CC_C;
951		r \|= t << 1;
952		CLR_NZVC;
953		SET_FLAGS8(t,t,r);
954		B = r;
955		}
956
957		/* $5A DECB inherent -**- /
958		OP_HANDLER( decb )
959		{
960		--B;
961		CLR_NZV;
962		SET_FLAGS8D(B);
963		}
964
965		/* $5B ILLEGAL, same as $5A */
966
967		/* $5C INCB inherent -**- /
968		OP_HANDLER( incb )
969		{
970		++B;
971		CLR_NZV;
972		SET_FLAGS8I(B);
973		}
974
975		/* $5D TSTB inherent -*0- /
976		OP_HANDLER( tstb )
977		{
978		CLR_NZV;
979		SET_NZ8(B);
980		}
981
982		/* $5E ILLEGAL, same as $5F */
983
984		/* $5F CLRB inherent -0100 */
985		OP_HANDLER( clrb )
986		{
987		B = 0;
988		CLR_NZVC; SEZ;
989		}
990
991		/* $60 NEG indexed ?**** */
992		OP_HANDLER( neg_ix )
993		{
994		UINT16 r,t;
995		fetch_effective_address();
996		t = RM(EAD);
997		r=-t;
998		CLR_NZVC;
999		SET_FLAGS8(0,t,r);
1000		WM(EAD,r);
1001		}
1002
1003		/* $61 ILLEGAL, same as $60 */
1004
1005		/* $62 ILLEGAL, same as $63 */
1006
1007		/* $63 COM indexed -*01 /
1008		OP_HANDLER( com_ix )
1009		{
1010		UINT8 t;
1011		fetch_effective_address();
1012		t = ~RM(EAD);
1013		CLR_NZV;
1014		SET_NZ8(t);
1015		SEC;
1016		WM(EAD,t);
1017		}
1018
1019		/* $64 LSR indexed -0- */
1020		OP_HANDLER( lsr_ix )
1021		{
1022		UINT8 t;
1023		fetch_effective_address();
1024		t=RM(EAD);
1025		CLR_NZC;
1026		CC \|= (t & CC_C);
1027		t>>=1; SET_Z8(t);
1028		WM(EAD,t);
1029		}
1030
1031		/* $65 ILLEGAL, same as $64 */
1032
1033		/* $66 ROR indexed -*- */
1034		OP_HANDLER( ror_ix )
1035		{
1036		UINT8 t,r;
1037		fetch_effective_address();
1038		t=RM(EAD);
1039		r = (CC & CC_C) << 7;
1040		CLR_NZC;
1041		CC \|= (t & CC_C);
1042		r \|= t>>1; SET_NZ8(r);
1043		WM(EAD,r);
1044		}
1045
1046		/* $67 ASR indexed ?*- */
1047		OP_HANDLER( asr_ix )
1048		{
1049		UINT8 t;
1050		fetch_effective_address();
1051		t=RM(EAD);
1052		CLR_NZC;
1053		CC \|= (t & CC_C);
1054		t=(t&0x80)\|(t>>1);
1055		SET_NZ8(t);
1056		WM(EAD,t);
1057		}
1058
1059		/* $68 ASL indexed ?**** */
1060		OP_HANDLER( asl_ix )
1061		{
1062		UINT16 t,r;
1063		fetch_effective_address();
1064		t=RM(EAD);
1065		r = t << 1;
1066		CLR_NZVC;
1067		SET_FLAGS8(t,t,r);
1068		WM(EAD,r);
1069		}
1070
1071		/* $69 ROL indexed -**** */
1072		OP_HANDLER( rol_ix )
1073		{
1074		UINT16 t,r;
1075		fetch_effective_address();
1076		t=RM(EAD);
1077		r = CC & CC_C;
1078		r \|= t << 1;
1079		CLR_NZVC;
1080		SET_FLAGS8(t,t,r);
1081		WM(EAD,r);
1082		}
1083
1084		/* $6A DEC indexed -**- /
1085		OP_HANDLER( dec_ix )
1086		{
1087		UINT8 t;
1088		fetch_effective_address();
1089		t = RM(EAD) - 1;
1090		CLR_NZV; SET_FLAGS8D(t);
1091		WM(EAD,t);
1092		}
1093
1094		/* $6B ILLEGAL, same as $6A */
1095
1096		/* $6C INC indexed -**- /
1097		OP_HANDLER( inc_ix )
1098		{
1099		UINT8 t;
1100		fetch_effective_address();
1101		t = RM(EAD) + 1;
1102		CLR_NZV; SET_FLAGS8I(t);
1103		WM(EAD,t);
1104		}
1105
1106		/* $6D TST indexed -*0- /
1107		OP_HANDLER( tst_ix )
1108		{
1109		UINT8 t;
1110		fetch_effective_address();
1111		t = RM(EAD);
1112		CLR_NZV;
1113		SET_NZ8(t);
1114		}
1115
1116		/* $6E JMP indexed ----- */
1117		OP_HANDLER( jmp_ix )
1118		{
1119		fetch_effective_address();
1120		PCD = EAD;
1121		}
1122
1123		/* $6F CLR indexed -0100 */
1124		OP_HANDLER( clr_ix )
1125		{
1126		fetch_effective_address();
1127		(void)RM(EAD);
1128		WM(EAD,0);
1129		CLR_NZVC; SEZ;
1130		}
1131
1132		/* $70 NEG extended ?**** */
1133		OP_HANDLER( neg_ex )
1134		{
1135		UINT16 r,t;
1136		EXTBYTE(t); r=-t;
1137		CLR_NZVC; SET_FLAGS8(0,t,r);
1138		WM(EAD,r);
1139		}
1140
1141		/* $71 ILLEGAL, same as $70 */
1142
1143		/* $72 ILLEGAL, same as $73 */
1144
1145		/* $73 COM extended -*01 /
1146		OP_HANDLER( com_ex )
1147		{
1148		UINT8 t;
1149		EXTBYTE(t); t = ~t;
1150		CLR_NZV; SET_NZ8(t); SEC;
1151		WM(EAD,t);
1152		}
1153
1154		/* $74 LSR extended -0- */
1155		OP_HANDLER( lsr_ex )
1156		{
1157		UINT8 t;
1158		EXTBYTE(t); CLR_NZC; CC \|= (t & CC_C);
1159		t>>=1; SET_Z8(t);
1160		WM(EAD,t);
1161		}
1162
1163		/* $75 ILLEGAL, same as $74 */
1164
1165		/* $76 ROR extended -*- */
1166		OP_HANDLER( ror_ex )
1167		{
1168		UINT8 t,r;
1169		EXTBYTE(t); r=(CC & CC_C) << 7;
1170		CLR_NZC; CC \|= (t & CC_C);
1171		r \|= t>>1; SET_NZ8(r);
1172		WM(EAD,r);
1173		}
1174
1175		/* $77 ASR extended ?*- */
1176		OP_HANDLER( asr_ex )
1177		{
1178		UINT8 t;
1179		EXTBYTE(t); CLR_NZC; CC \|= (t & CC_C);
1180		t=(t&0x80)\|(t>>1);
1181		SET_NZ8(t);
1182		WM(EAD,t);
1183		}
1184
1185		/* $78 ASL extended ?**** */
1186		OP_HANDLER( asl_ex )
1187		{
1188		UINT16 t,r;
1189		EXTBYTE(t); r=t<<1;
1190		CLR_NZVC; SET_FLAGS8(t,t,r);
1191		WM(EAD,r);
1192		}
1193
1194		/* $79 ROL extended -**** */
1195		OP_HANDLER( rol_ex )
1196		{
1197		UINT16 t,r;
1198		EXTBYTE(t); r = (CC & CC_C) \| (t << 1);
1199		CLR_NZVC; SET_FLAGS8(t,t,r);
1200		WM(EAD,r);
1201		}
1202
1203		/* $7A DEC extended -**- /
1204		OP_HANDLER( dec_ex )
1205		{
1206		UINT8 t;
1207		EXTBYTE(t); --t;
1208		CLR_NZV; SET_FLAGS8D(t);
1209		WM(EAD,t);
1210		}
1211
1212		/* $7B ILLEGAL, same as $7A */
1213
1214		/* $7C INC extended -**- /
1215		OP_HANDLER( inc_ex )
1216		{
1217		UINT8 t;
1218		EXTBYTE(t); ++t;
1219		CLR_NZV; SET_FLAGS8I(t);
1220		WM(EAD,t);
1221		}
1222
1223		/* $7D TST extended -*0- /
1224		OP_HANDLER( tst_ex )
1225		{
1226		UINT8 t;
1227		EXTBYTE(t); CLR_NZV; SET_NZ8(t);
1228		}
1229
1230		/* $7E JMP extended ----- */
1231		OP_HANDLER( jmp_ex )
1232		{
1233		EXTENDED;
1234		PCD = EAD;
1235		}
1236
1237		/* $7F CLR extended -0100 */
1238		OP_HANDLER( clr_ex )
1239		{
1240		EXTENDED;
1241		(void)RM(EAD);
1242		WM(EAD,0);
1243		CLR_NZVC; SEZ;
1244		}
1245
1246		/* $80 SUBA immediate ?**** */
1247		OP_HANDLER( suba_im )
1248		{
1249		UINT16 t,r;
1250		IMMBYTE(t);
1251		r = A - t;
1252		CLR_NZVC;
1253		SET_FLAGS8(A,t,r);
1254		A = r;
1255		}
1256
1257		/* $81 CMPA immediate ?**** */
1258		OP_HANDLER( cmpa_im )
1259		{
1260		UINT16 t,r;
1261		IMMBYTE(t);
1262		r = A - t;
1263		CLR_NZVC;
1264		SET_FLAGS8(A,t,r);
1265		}
1266
1267		/* $82 SBCA immediate ?**** */
1268		OP_HANDLER( sbca_im )
1269		{
1270		UINT16 t,r;
1271		IMMBYTE(t);
1272		r = A - t - (CC & CC_C);
1273		CLR_NZVC;
1274		SET_FLAGS8(A,t,r);
1275		A = r;
1276		}
1277
1278		/* $83 SUBD (CMPD CMPU) immediate -**** */
1279		OP_HANDLER( subd_im )
1280		{
1281		UINT32 r,d;
1282		PAIR b;
1283		IMMWORD(b);
1284		d = D;
1285		r = d - b.d;
1286		CLR_NZVC;
1287		SET_FLAGS16(d,b.d,r);
1288		D = r;
1289		}
1290
1291		/* $1083 CMPD immediate -**** */
1292		OP_HANDLER( cmpd_im )
1293		{
1294		UINT32 r,d;
1295		PAIR b;
1296		IMMWORD(b);
1297		d = D;
1298		r = d - b.d;
1299		CLR_NZVC;
1300		SET_FLAGS16(d,b.d,r);
1301		}
1302
1303		/* $1183 CMPU immediate -**** */
1304		OP_HANDLER( cmpu_im )
1305		{
1306		UINT32 r, d;
1307		PAIR b;
1308		IMMWORD(b);
1309		d = U;
1310		r = d - b.d;
1311		CLR_NZVC;
1312		SET_FLAGS16(d,b.d,r);
1313		}
1314
1315		/* $84 ANDA immediate -*0- /
1316		OP_HANDLER( anda_im )
1317		{
1318		UINT8 t;
1319		IMMBYTE(t);
1320		A &= t;
1321		CLR_NZV;
1322		SET_NZ8(A);
1323		}
1324
1325		/* $85 BITA immediate -*0- /
1326		OP_HANDLER( bita_im )
1327		{
1328		UINT8 t,r;
1329		IMMBYTE(t);
1330		r = A & t;
1331		CLR_NZV;
1332		SET_NZ8(r);
1333		}
1334
1335		/* $86 LDA immediate -*0- /
1336		OP_HANDLER( lda_im )
1337		{
1338		IMMBYTE(A);
1339		CLR_NZV;
1340		SET_NZ8(A);
1341		}
1342
1343		/* is this a legal instruction? */
1344		/* $87 STA immediate -*0- /
1345		OP_HANDLER( sta_im )
1346		{
1347		CLR_NZV;
1348		SET_NZ8(A);
1349		IMM8;
1350		WM(EAD,A);
1351		}
1352
1353		/* $88 EORA immediate -*0- /
1354		OP_HANDLER( eora_im )
1355		{
1356		UINT8 t;
1357		IMMBYTE(t);
1358		A ^= t;
1359		CLR_NZV;
1360		SET_NZ8(A);
1361		}
1362
1363		/* $89 ADCA immediate ***** */
1364		OP_HANDLER( adca_im )
1365		{
1366		UINT16 t,r;
1367		IMMBYTE(t);
1368		r = A + t + (CC & CC_C);
1369		CLR_HNZVC;
1370		SET_FLAGS8(A,t,r);
1371		SET_H(A,t,r);
1372		A = r;
1373		}
1374
1375		/* $8A ORA immediate -*0- /
1376		OP_HANDLER( ora_im )
1377		{
1378		UINT8 t;
1379		IMMBYTE(t);
1380		A \|= t;
1381		CLR_NZV;
1382		SET_NZ8(A);
1383		}
1384
1385		/* $8B ADDA immediate ***** */
1386		OP_HANDLER( adda_im )
1387		{
1388		UINT16 t,r;
1389		IMMBYTE(t);
1390		r = A + t;
1391		CLR_HNZVC;
1392		SET_FLAGS8(A,t,r);
1393		SET_H(A,t,r);
1394		A = r;
1395		}
1396
1397		/* $8C CMPX (CMPY CMPS) immediate -**** */
1398		OP_HANDLER( cmpx_im )
1399		{
1400		UINT32 r,d;
1401		PAIR b;
1402		IMMWORD(b);
1403		d = X;
1404		r = d - b.d;
1405		CLR_NZVC;
1406		SET_FLAGS16(d,b.d,r);
1407		}
1408
1409		/* $108C CMPY immediate -**** */
1410		OP_HANDLER( cmpy_im )
1411		{
1412		UINT32 r,d;
1413		PAIR b;
1414		IMMWORD(b);
1415		d = Y;
1416		r = d - b.d;
1417		CLR_NZVC;
1418		SET_FLAGS16(d,b.d,r);
1419		}
1420
1421		/* $118C CMPS immediate -**** */
1422		OP_HANDLER( cmps_im )
1423		{
1424		UINT32 r,d;
1425		PAIR b;
1426		IMMWORD(b);
1427		d = S;
1428		r = d - b.d;
1429		CLR_NZVC;
1430		SET_FLAGS16(d,b.d,r);
1431		}
1432
1433		/* $8D BSR ----- */
1434		OP_HANDLER( bsr )
1435		{
1436		UINT8 t;
1437		IMMBYTE(t);
1438		PUSHWORD(pPC);
1439		PC += SIGNED(t);
1440		}
1441
1442		/* $8E LDX (LDY) immediate -*0- /
1443		OP_HANDLER( ldx_im )
1444		{
1445		IMMWORD(pX);
1446		CLR_NZV;
1447		SET_NZ16(X);
1448		}
1449
1450		/* $108E LDY immediate -*0- /
1451		OP_HANDLER( ldy_im )
1452		{
1453		IMMWORD(pY);
1454		CLR_NZV;
1455		SET_NZ16(Y);
1456		}
1457
1458		/* is this a legal instruction? */
1459		/* $8F STX (STY) immediate -*0- /
1460		OP_HANDLER( stx_im )
1461		{
1462		CLR_NZV;
1463		SET_NZ16(X);
1464		IMM16;
1465		WM16(EAD,&pX);
1466		}
1467
1468		/* is this a legal instruction? */
1469		/* $108F STY immediate -*0- /
1470		OP_HANDLER( sty_im )
1471		{
1472		CLR_NZV;
1473		SET_NZ16(Y);
1474		IMM16;
1475		WM16(EAD,&pY);
1476		}
1477
1478		/* $90 SUBA direct ?**** */
1479		OP_HANDLER( suba_di )
1480		{
1481		UINT16 t,r;
1482		DIRBYTE(t);
1483		r = A - t;
1484		CLR_NZVC;
1485		SET_FLAGS8(A,t,r);
1486		A = r;
1487		}
1488
1489		/* $91 CMPA direct ?**** */
1490		OP_HANDLER( cmpa_di )
1491		{
1492		UINT16 t,r;
1493		DIRBYTE(t);
1494		r = A - t;
1495		CLR_NZVC;
1496		SET_FLAGS8(A,t,r);
1497		}
1498
1499		/* $92 SBCA direct ?**** */
1500		OP_HANDLER( sbca_di )
1501		{
1502		UINT16 t,r;
1503		DIRBYTE(t);
1504		r = A - t - (CC & CC_C);
1505		CLR_NZVC;
1506		SET_FLAGS8(A,t,r);
1507		A = r;
1508		}
1509
1510		/* $93 SUBD (CMPD CMPU) direct -**** */
1511		OP_HANDLER( subd_di )
1512		{
1513		UINT32 r,d;
1514		PAIR b;
1515		DIRWORD(b);
1516		d = D;
1517		r = d - b.d;
1518		CLR_NZVC;
1519		SET_FLAGS16(d,b.d,r);
1520		D = r;
1521		}
1522
1523		/* $1093 CMPD direct -**** */
1524		OP_HANDLER( cmpd_di )
1525		{
1526		UINT32 r,d;
1527		PAIR b;
1528		DIRWORD(b);
1529		d = D;
1530		r = d - b.d;
1531		CLR_NZVC;
1532		SET_FLAGS16(d,b.d,r);
1533		}
1534
1535		/* $1193 CMPU direct -**** */
1536		OP_HANDLER( cmpu_di )
1537		{
1538		UINT32 r,d;
1539		PAIR b;
1540		DIRWORD(b);
1541		d = U;
1542		r = d - b.d;
1543		CLR_NZVC;
1544		SET_FLAGS16(U,b.d,r);
1545		}
1546
1547		/* $94 ANDA direct -*0- /
1548		OP_HANDLER( anda_di )
1549		{
1550		UINT8 t;
1551		DIRBYTE(t);
1552		A &= t;
1553		CLR_NZV;
1554		SET_NZ8(A);
1555		}
1556
1557		/* $95 BITA direct -*0- /
1558		OP_HANDLER( bita_di )
1559		{
1560		UINT8 t,r;
1561		DIRBYTE(t);
1562		r = A & t;
1563		CLR_NZV;
1564		SET_NZ8(r);
1565		}
1566
1567		/* $96 LDA direct -*0- /
1568		OP_HANDLER( lda_di )
1569		{
1570		DIRBYTE(A);
1571		CLR_NZV;
1572		SET_NZ8(A);
1573		}
1574
1575		/* $97 STA direct -*0- /
1576		OP_HANDLER( sta_di )
1577		{
1578		CLR_NZV;
1579		SET_NZ8(A);
1580		DIRECT;
1581		WM(EAD,A);
1582		}
1583
1584		/* $98 EORA direct -*0- /
1585		OP_HANDLER( eora_di )
1586		{
1587		UINT8 t;
1588		DIRBYTE(t);
1589		A ^= t;
1590		CLR_NZV;
1591		SET_NZ8(A);
1592		}
1593
1594		/* $99 ADCA direct ***** */
1595		OP_HANDLER( adca_di )
1596		{
1597		UINT16 t,r;
1598		DIRBYTE(t);
1599		r = A + t + (CC & CC_C);
1600		CLR_HNZVC;
1601		SET_FLAGS8(A,t,r);
1602		SET_H(A,t,r);
1603		A = r;
1604		}
1605
1606		/* $9A ORA direct -*0- /
1607		OP_HANDLER( ora_di )
1608		{
1609		UINT8 t;
1610		DIRBYTE(t);
1611		A \|= t;
1612		CLR_NZV;
1613		SET_NZ8(A);
1614		}
1615
1616		/* $9B ADDA direct ***** */
1617		OP_HANDLER( adda_di )
1618		{
1619		UINT16 t,r;
1620		DIRBYTE(t);
1621		r = A + t;
1622		CLR_HNZVC;
1623		SET_FLAGS8(A,t,r);
1624		SET_H(A,t,r);
1625		A = r;
1626		}
1627
1628		/* $9C CMPX (CMPY CMPS) direct -**** */
1629		OP_HANDLER( cmpx_di )
1630		{
1631		UINT32 r,d;
1632		PAIR b;
1633		DIRWORD(b);
1634		d = X;
1635		r = d - b.d;
1636		CLR_NZVC;
1637		SET_FLAGS16(d,b.d,r);
1638		}
1639
1640		/* $109C CMPY direct -**** */
1641		OP_HANDLER( cmpy_di )
1642		{
1643		UINT32 r,d;
1644		PAIR b;
1645		DIRWORD(b);
1646		d = Y;
1647		r = d - b.d;
1648		CLR_NZVC;
1649		SET_FLAGS16(d,b.d,r);
1650		}
1651
1652		/* $119C CMPS direct -**** */
1653		OP_HANDLER( cmps_di )
1654		{
1655		UINT32 r,d;
1656		PAIR b;
1657		DIRWORD(b);
1658		d = S;
1659		r = d - b.d;
1660		CLR_NZVC;
1661		SET_FLAGS16(d,b.d,r);
1662		}
1663
1664		/* $9D JSR direct ----- */
1665		OP_HANDLER( jsr_di )
1666		{
1667		DIRECT;
1668		PUSHWORD(pPC);
1669		PCD = EAD;
1670		}
1671
1672		/* $9E LDX (LDY) direct -*0- /
1673		OP_HANDLER( ldx_di )
1674		{
1675		DIRWORD(pX);
1676		CLR_NZV;
1677		SET_NZ16(X);
1678		}
1679
1680		/* $109E LDY direct -*0- /
1681		OP_HANDLER( ldy_di )
1682		{
1683		DIRWORD(pY);
1684		CLR_NZV;
1685		SET_NZ16(Y);
1686		}
1687
1688		/* $9F STX (STY) direct -*0- /
1689		OP_HANDLER( stx_di )
1690		{
1691		CLR_NZV;
1692		SET_NZ16(X);
1693		DIRECT;
1694		WM16(EAD,&pX);
1695		}
1696
1697		/* $109F STY direct -*0- /
1698		OP_HANDLER( sty_di )
1699		{
1700		CLR_NZV;
1701		SET_NZ16(Y);
1702		DIRECT;
1703		WM16(EAD,&pY);
1704		}
1705
1706		/* $a0 SUBA indexed ?**** */
1707		OP_HANDLER( suba_ix )
1708		{
1709		UINT16 t,r;
1710		fetch_effective_address();
1711		t = RM(EAD);
1712		r = A - t;
1713		CLR_NZVC;
1714		SET_FLAGS8(A,t,r);
1715		A = r;
1716		}
1717
1718		/* $a1 CMPA indexed ?**** */
1719		OP_HANDLER( cmpa_ix )
1720		{
1721		UINT16 t,r;
1722		fetch_effective_address();
1723		t = RM(EAD);
1724		r = A - t;
1725		CLR_NZVC;
1726		SET_FLAGS8(A,t,r);
1727		}
1728
1729		/* $a2 SBCA indexed ?**** */
1730		OP_HANDLER( sbca_ix )
1731		{
1732		UINT16 t,r;
1733		fetch_effective_address();
1734		t = RM(EAD);
1735		r = A - t - (CC & CC_C);
1736		CLR_NZVC;
1737		SET_FLAGS8(A,t,r);
1738		A = r;
1739		}
1740
1741		/* $a3 SUBD (CMPD CMPU) indexed -**** */
1742		OP_HANDLER( subd_ix )
1743		{
1744		UINT32 r,d;
1745		PAIR b;
1746		fetch_effective_address();
1747		b.d=RM16(EAD);
1748		d = D;
1749		r = d - b.d;
1750		CLR_NZVC;
1751		SET_FLAGS16(d,b.d,r);
1752		D = r;
1753		}
1754
1755		/* $10a3 CMPD indexed -**** */
1756		OP_HANDLER( cmpd_ix )
1757		{
1758		UINT32 r,d;
1759		PAIR b;
1760		fetch_effective_address();
1761		b.d=RM16(EAD);
1762		d = D;
1763		r = d - b.d;
1764		CLR_NZVC;
1765		SET_FLAGS16(d,b.d,r);
1766		}
1767
1768		/* $11a3 CMPU indexed -**** */
1769		OP_HANDLER( cmpu_ix )
1770		{
1771		UINT32 r;
1772		PAIR b;
1773		fetch_effective_address();
1774		b.d=RM16(EAD);
1775		r = U - b.d;
1776		CLR_NZVC;
1777		SET_FLAGS16(U,b.d,r);
1778		}
1779
1780		/* $a4 ANDA indexed -*0- /
1781		OP_HANDLER( anda_ix )
1782		{
1783		fetch_effective_address();
1784		A &= RM(EAD);
1785		CLR_NZV;
1786		SET_NZ8(A);
1787		}
1788
1789		/* $a5 BITA indexed -*0- /
1790		OP_HANDLER( bita_ix )
1791		{
1792		UINT8 r;
1793		fetch_effective_address();
1794		r = A & RM(EAD);
1795		CLR_NZV;
1796		SET_NZ8(r);
1797		}
1798
1799		/* $a6 LDA indexed -*0- /
1800		OP_HANDLER( lda_ix )
1801		{
1802		fetch_effective_address();
1803		A = RM(EAD);
1804		CLR_NZV;
1805		SET_NZ8(A);
1806		}
1807
1808		/* $a7 STA indexed -*0- /
1809		OP_HANDLER( sta_ix )
1810		{
1811		fetch_effective_address();
1812		CLR_NZV;
1813		SET_NZ8(A);
1814		WM(EAD,A);
1815		}
1816
1817		/* $a8 EORA indexed -*0- /
1818		OP_HANDLER( eora_ix )
1819		{
1820		fetch_effective_address();
1821		A ^= RM(EAD);
1822		CLR_NZV;
1823		SET_NZ8(A);
1824		}
1825
1826		/* $a9 ADCA indexed ***** */
1827		OP_HANDLER( adca_ix )
1828		{
1829		UINT16 t,r;
1830		fetch_effective_address();
1831		t = RM(EAD);
1832		r = A + t + (CC & CC_C);
1833		CLR_HNZVC;
1834		SET_FLAGS8(A,t,r);
1835		SET_H(A,t,r);
1836		A = r;
1837		}
1838
1839		/* $aA ORA indexed -*0- /
1840		OP_HANDLER( ora_ix )
1841		{
1842		fetch_effective_address();
1843		A \|= RM(EAD);
1844		CLR_NZV;
1845		SET_NZ8(A);
1846		}
1847
1848		/* $aB ADDA indexed ***** */
1849		OP_HANDLER( adda_ix )
1850		{
1851		UINT16 t,r;
1852		fetch_effective_address();
1853		t = RM(EAD);
1854		r = A + t;
1855		CLR_HNZVC;
1856		SET_FLAGS8(A,t,r);
1857		SET_H(A,t,r);
1858		A = r;
1859		}
1860
1861		/* $aC CMPX (CMPY CMPS) indexed -**** */
1862		OP_HANDLER( cmpx_ix )
1863		{
1864		UINT32 r,d;
1865		PAIR b;
1866		fetch_effective_address();
1867		b.d=RM16(EAD);
1868		d = X;
1869		r = d - b.d;
1870		CLR_NZVC;
1871		SET_FLAGS16(d,b.d,r);
1872		}
1873
1874		/* $10aC CMPY indexed -**** */
1875		OP_HANDLER( cmpy_ix )
1876		{
1877		UINT32 r,d;
1878		PAIR b;
1879		fetch_effective_address();
1880		b.d=RM16(EAD);
1881		d = Y;
1882		r = d - b.d;
1883		CLR_NZVC;
1884		SET_FLAGS16(d,b.d,r);
1885		}
1886
1887		/* $11aC CMPS indexed -**** */
1888		OP_HANDLER( cmps_ix )
1889		{
1890		UINT32 r,d;
1891		PAIR b;
1892		fetch_effective_address();
1893		b.d=RM16(EAD);
1894		d = S;
1895		r = d - b.d;
1896		CLR_NZVC;
1897		SET_FLAGS16(d,b.d,r);
1898		}
1899
1900		/* $aD JSR indexed ----- */
1901		OP_HANDLER( jsr_ix )
1902		{
1903		fetch_effective_address();
1904		PUSHWORD(pPC);
1905		PCD = EAD;
1906		}
1907
1908		/* $aE LDX (LDY) indexed -*0- /
1909		OP_HANDLER( ldx_ix )
1910		{
1911		fetch_effective_address();
1912		X=RM16(EAD);
1913		CLR_NZV;
1914		SET_NZ16(X);
1915		}
1916
1917		/* $10aE LDY indexed -*0- /
1918		OP_HANDLER( ldy_ix )
1919		{
1920		fetch_effective_address();
1921		Y=RM16(EAD);
1922		CLR_NZV;
1923		SET_NZ16(Y);
1924		}
1925
1926		/* $aF STX (STY) indexed -*0- /
1927		OP_HANDLER( stx_ix )
1928		{
1929		fetch_effective_address();
1930		CLR_NZV;
1931		SET_NZ16(X);
1932		WM16(EAD,&pX);
1933		}
1934
1935		/* $10aF STY indexed -*0- /
1936		OP_HANDLER( sty_ix )
1937		{
1938		fetch_effective_address();
1939		CLR_NZV;
1940		SET_NZ16(Y);
1941		WM16(EAD,&pY);
1942		}
1943
1944		/* $b0 SUBA extended ?**** */
1945		OP_HANDLER( suba_ex )
1946		{
1947		UINT16 t,r;
1948		EXTBYTE(t);
1949		r = A - t;
1950		CLR_NZVC;
1951		SET_FLAGS8(A,t,r);
1952		A = r;
1953		}
1954
1955		/* $b1 CMPA extended ?**** */
1956		OP_HANDLER( cmpa_ex )
1957		{
1958		UINT16 t,r;
1959		EXTBYTE(t);
1960		r = A - t;
1961		CLR_NZVC;
1962		SET_FLAGS8(A,t,r);
1963		}
1964
1965		/* $b2 SBCA extended ?**** */
1966		OP_HANDLER( sbca_ex )
1967		{
1968		UINT16 t,r;
1969		EXTBYTE(t);
1970		r = A - t - (CC & CC_C);
1971		CLR_NZVC;
1972		SET_FLAGS8(A,t,r);
1973		A = r;
1974		}
1975
1976		/* $b3 SUBD (CMPD CMPU) extended -**** */
1977		OP_HANDLER( subd_ex )
1978		{
1979		UINT32 r,d;
1980		PAIR b;
1981		EXTWORD(b);
1982		d = D;
1983		r = d - b.d;
1984		CLR_NZVC;
1985		SET_FLAGS16(d,b.d,r);
1986		D = r;
1987		}
1988
1989		/* $10b3 CMPD extended -**** */
1990		OP_HANDLER( cmpd_ex )
1991		{
1992		UINT32 r,d;
1993		PAIR b;
1994		EXTWORD(b);
1995		d = D;
1996		r = d - b.d;
1997		CLR_NZVC;
1998		SET_FLAGS16(d,b.d,r);
1999		}
2000
2001		/* $11b3 CMPU extended -**** */
2002		OP_HANDLER( cmpu_ex )
2003		{
2004		UINT32 r,d;
2005		PAIR b;
2006		EXTWORD(b);
2007		d = U;
2008		r = d - b.d;
2009		CLR_NZVC;
2010		SET_FLAGS16(d,b.d,r);
2011		}
2012
2013		/* $b4 ANDA extended -*0- /
2014		OP_HANDLER( anda_ex )
2015		{
2016		UINT8 t;
2017		EXTBYTE(t);
2018		A &= t;
2019		CLR_NZV;
2020		SET_NZ8(A);
2021		}
2022
2023		/* $b5 BITA extended -*0- /
2024		OP_HANDLER( bita_ex )
2025		{
2026		UINT8 t,r;
2027		EXTBYTE(t);
2028		r = A & t;
2029		CLR_NZV; SET_NZ8(r);
2030		}
2031
2032		/* $b6 LDA extended -*0- /
2033		OP_HANDLER( lda_ex )
2034		{
2035		EXTBYTE(A);
2036		CLR_NZV;
2037		SET_NZ8(A);
2038		}
2039
2040		/* $b7 STA extended -*0- /
2041		OP_HANDLER( sta_ex )
2042		{
2043		CLR_NZV;
2044		SET_NZ8(A);
2045		EXTENDED;
2046		WM(EAD,A);
2047		}
2048
2049		/* $b8 EORA extended -*0- /
2050		OP_HANDLER( eora_ex )
2051		{
2052		UINT8 t;
2053		EXTBYTE(t);
2054		A ^= t;
2055		CLR_NZV;
2056		SET_NZ8(A);
2057		}
2058
2059		/* $b9 ADCA extended ***** */
2060		OP_HANDLER( adca_ex )
2061		{
2062		UINT16 t,r;
2063		EXTBYTE(t);
2064		r = A + t + (CC & CC_C);
2065		CLR_HNZVC;
2066		SET_FLAGS8(A,t,r);
2067		SET_H(A,t,r);
2068		A = r;
2069		}
2070
2071		/* $bA ORA extended -*0- /
2072		OP_HANDLER( ora_ex )
2073		{
2074		UINT8 t;
2075		EXTBYTE(t);
2076		A \|= t;
2077		CLR_NZV;
2078		SET_NZ8(A);
2079		}
2080
2081		/* $bB ADDA extended ***** */
2082		OP_HANDLER( adda_ex )
2083		{
2084		UINT16 t,r;
2085		EXTBYTE(t);
2086		r = A + t;
2087		CLR_HNZVC;
2088		SET_FLAGS8(A,t,r);
2089		SET_H(A,t,r);
2090		A = r;
2091		}
2092
2093		/* $bC CMPX (CMPY CMPS) extended -**** */
2094		OP_HANDLER( cmpx_ex )
2095		{
2096		UINT32 r,d;
2097		PAIR b;
2098		EXTWORD(b);
2099		d = X;
2100		r = d - b.d;
2101		CLR_NZVC;
2102		SET_FLAGS16(d,b.d,r);
2103		}
2104
2105		/* $10bC CMPY extended -**** */
2106		OP_HANDLER( cmpy_ex )
2107		{
2108		UINT32 r,d;
2109		PAIR b;
2110		EXTWORD(b);
2111		d = Y;
2112		r = d - b.d;
2113		CLR_NZVC;
2114		SET_FLAGS16(d,b.d,r);
2115		}
2116
2117		/* $11bC CMPS extended -**** */
2118		OP_HANDLER( cmps_ex )
2119		{
2120		UINT32 r,d;
2121		PAIR b;
2122		EXTWORD(b);
2123		d = S;
2124		r = d - b.d;
2125		CLR_NZVC;
2126		SET_FLAGS16(d,b.d,r);
2127		}
2128
2129		/* $bD JSR extended ----- */
2130		OP_HANDLER( jsr_ex )
2131		{
2132		EXTENDED;
2133		PUSHWORD(pPC);
2134		PCD = EAD;
2135		}
2136
2137		/* $bE LDX (LDY) extended -*0- /
2138		OP_HANDLER( ldx_ex )
2139		{
2140		EXTWORD(pX);
2141		CLR_NZV;
2142		SET_NZ16(X);
2143		}
2144
2145		/* $10bE LDY extended -*0- /
2146		OP_HANDLER( ldy_ex )
2147		{
2148		EXTWORD(pY);
2149		CLR_NZV;
2150		SET_NZ16(Y);
2151		}
2152
2153		/* $bF STX (STY) extended -*0- /
2154		OP_HANDLER( stx_ex )
2155		{
2156		CLR_NZV;
2157		SET_NZ16(X);
2158		EXTENDED;
2159		WM16(EAD,&pX);
2160		}
2161
2162		/* $10bF STY extended -*0- /
2163		OP_HANDLER( sty_ex )
2164		{
2165		CLR_NZV;
2166		SET_NZ16(Y);
2167		EXTENDED;
2168		WM16(EAD,&pY);
2169		}
2170
2171		/* $c0 SUBB immediate ?**** */
2172		OP_HANDLER( subb_im )
2173		{
2174		UINT16 t,r;
2175		IMMBYTE(t);
2176		r = B - t;
2177		CLR_NZVC;
2178		SET_FLAGS8(B,t,r);
2179		B = r;
2180		}
2181
2182		/* $c1 CMPB immediate ?**** */
2183		OP_HANDLER( cmpb_im )
2184		{
2185		UINT16 t,r;
2186		IMMBYTE(t);
2187		r = B - t;
2188		CLR_NZVC; SET_FLAGS8(B,t,r);
2189		}
2190
2191		/* $c2 SBCB immediate ?**** */
2192		OP_HANDLER( sbcb_im )
2193		{
2194		UINT16 t,r;
2195		IMMBYTE(t);
2196		r = B - t - (CC & CC_C);
2197		CLR_NZVC;
2198		SET_FLAGS8(B,t,r);
2199		B = r;
2200		}
2201
2202		/* $c3 ADDD immediate -**** */
2203		OP_HANDLER( addd_im )
2204		{
2205		UINT32 r,d;
2206		PAIR b;
2207		IMMWORD(b);
2208		d = D;
2209		r = d + b.d;
2210		CLR_NZVC;
2211		SET_FLAGS16(d,b.d,r);
2212		D = r;
2213		}
2214
2215		/* $c4 ANDB immediate -*0- /
2216		OP_HANDLER( andb_im )
2217		{
2218		UINT8 t;
2219		IMMBYTE(t);
2220		B &= t;
2221		CLR_NZV;
2222		SET_NZ8(B);
2223		}
2224
2225		/* $c5 BITB immediate -*0- /
2226		OP_HANDLER( bitb_im )
2227		{
2228		UINT8 t,r;
2229		IMMBYTE(t);
2230		r = B & t;
2231		CLR_NZV;
2232		SET_NZ8(r);
2233		}
2234
2235		/* $c6 LDB immediate -*0- /
2236		OP_HANDLER( ldb_im )
2237		{
2238		IMMBYTE(B);
2239		CLR_NZV;
2240		SET_NZ8(B);
2241		}
2242
2243		/* is this a legal instruction? */
2244		/* $c7 STB immediate -*0- /
2245		OP_HANDLER( stb_im )
2246		{
2247		CLR_NZV;
2248		SET_NZ8(B);
2249		IMM8;
2250		WM(EAD,B);
2251		}
2252
2253		/* $c8 EORB immediate -*0- /
2254		OP_HANDLER( eorb_im )
2255		{
2256		UINT8 t;
2257		IMMBYTE(t);
2258		B ^= t;
2259		CLR_NZV;
2260		SET_NZ8(B);
2261		}
2262
2263		/* $c9 ADCB immediate ***** */
2264		OP_HANDLER( adcb_im )
2265		{
2266		UINT16 t,r;
2267		IMMBYTE(t);
2268		r = B + t + (CC & CC_C);
2269		CLR_HNZVC;
2270		SET_FLAGS8(B,t,r);
2271		SET_H(B,t,r);
2272		B = r;
2273		}
2274
2275		/* $cA ORB immediate -*0- /
2276		OP_HANDLER( orb_im )
2277		{
2278		UINT8 t;
2279		IMMBYTE(t);
2280		B \|= t;
2281		CLR_NZV;
2282		SET_NZ8(B);
2283		}
2284
2285		/* $cB ADDB immediate ***** */
2286		OP_HANDLER( addb_im )
2287		{
2288		UINT16 t,r;
2289		IMMBYTE(t);
2290		r = B + t;
2291		CLR_HNZVC;
2292		SET_FLAGS8(B,t,r);
2293		SET_H(B,t,r);
2294		B = r;
2295		}
2296
2297		/* $cC LDD immediate -*0- /
2298		OP_HANDLER( ldd_im )
2299		{
2300		IMMWORD(pD);
2301		CLR_NZV;
2302		SET_NZ16(D);
2303		}
2304
2305		/* is this a legal instruction? */
2306		/* $cD STD immediate -*0- /
2307		OP_HANDLER( std_im )
2308		{
2309		CLR_NZV;
2310		SET_NZ16(D);
2311		IMM16;
2312		WM16(EAD,&pD);
2313		}
2314
2315		/* $cE LDU (LDS) immediate -*0- /
2316		OP_HANDLER( ldu_im )
2317		{
2318		IMMWORD(pU);
2319		CLR_NZV;
2320		SET_NZ16(U);
2321		}
2322
2323		/* $10cE LDS immediate -*0- /
2324		OP_HANDLER( lds_im )
2325		{
2326		IMMWORD(pS);
2327		CLR_NZV;
2328		SET_NZ16(S);
2329		m_int_state \|= M6809_LDS;
2330		}
2331
2332		/* is this a legal instruction? */
2333		/* $cF STU (STS) immediate -*0- /
2334		OP_HANDLER( stu_im )
2335		{
2336		CLR_NZV;
2337		SET_NZ16(U);
2338		IMM16;
2339		WM16(EAD,&pU);
2340		}
2341
2342		/* is this a legal instruction? */
2343		/* $10cF STS immediate -*0- /
2344		OP_HANDLER( sts_im )
2345		{
2346		CLR_NZV;
2347		SET_NZ16(S);
2348		IMM16;
2349		WM16(EAD,&pS);
2350		}
2351
2352		/* $d0 SUBB direct ?**** */
2353		OP_HANDLER( subb_di )
2354		{
2355		UINT16 t,r;
2356		DIRBYTE(t);
2357		r = B - t;
2358		CLR_NZVC;
2359		SET_FLAGS8(B,t,r);
2360		B = r;
2361		}
2362
2363		/* $d1 CMPB direct ?**** */
2364		OP_HANDLER( cmpb_di )
2365		{
2366		UINT16 t,r;
2367		DIRBYTE(t);
2368		r = B - t;
2369		CLR_NZVC;
2370		SET_FLAGS8(B,t,r);
2371		}
2372
2373		/* $d2 SBCB direct ?**** */
2374		OP_HANDLER( sbcb_di )
2375		{
2376		UINT16 t,r;
2377		DIRBYTE(t);
2378		r = B - t - (CC & CC_C);
2379		CLR_NZVC;
2380		SET_FLAGS8(B,t,r);
2381		B = r;
2382		}
2383
2384		/* $d3 ADDD direct -**** */
2385		OP_HANDLER( addd_di )
2386		{
2387		UINT32 r,d;
2388		PAIR b;
2389		DIRWORD(b);
2390		d = D;
2391		r = d + b.d;
2392		CLR_NZVC;
2393		SET_FLAGS16(d,b.d,r);
2394		D = r;
2395		}
2396
2397		/* $d4 ANDB direct -*0- /
2398		OP_HANDLER( andb_di )
2399		{
2400		UINT8 t;
2401		DIRBYTE(t);
2402		B &= t;
2403		CLR_NZV;
2404		SET_NZ8(B);
2405		}
2406
2407		/* $d5 BITB direct -*0- /
2408		OP_HANDLER( bitb_di )
2409		{
2410		UINT8 t,r;
2411		DIRBYTE(t);
2412		r = B & t;
2413		CLR_NZV;
2414		SET_NZ8(r);
2415		}
2416
2417		/* $d6 LDB direct -*0- /
2418		OP_HANDLER( ldb_di )
2419		{
2420		DIRBYTE(B);
2421		CLR_NZV;
2422		SET_NZ8(B);
2423		}
2424
2425		/* $d7 STB direct -*0- /
2426		OP_HANDLER( stb_di )
2427		{
2428		CLR_NZV;
2429		SET_NZ8(B);
2430		DIRECT;
2431		WM(EAD,B);
2432		}
2433
2434		/* $d8 EORB direct -*0- /
2435		OP_HANDLER( eorb_di )
2436		{
2437		UINT8 t;
2438		DIRBYTE(t);
2439		B ^= t;
2440		CLR_NZV;
2441		SET_NZ8(B);
2442		}
2443
2444		/* $d9 ADCB direct ***** */
2445		OP_HANDLER( adcb_di )
2446		{
2447		UINT16 t,r;
2448		DIRBYTE(t);
2449		r = B + t + (CC & CC_C);
2450		CLR_HNZVC;
2451		SET_FLAGS8(B,t,r);
2452		SET_H(B,t,r);
2453		B = r;
2454		}
2455
2456		/* $dA ORB direct -*0- /
2457		OP_HANDLER( orb_di )
2458		{
2459		UINT8 t;
2460		DIRBYTE(t);
2461		B \|= t;
2462		CLR_NZV;
2463		SET_NZ8(B);
2464		}
2465
2466		/* $dB ADDB direct ***** */
2467		OP_HANDLER( addb_di )
2468		{
2469		UINT16 t,r;
2470		DIRBYTE(t);
2471		r = B + t;
2472		CLR_HNZVC;
2473		SET_FLAGS8(B,t,r);
2474		SET_H(B,t,r);
2475		B = r;
2476		}
2477
2478		/* $dC LDD direct -*0- /
2479		OP_HANDLER( ldd_di )
2480		{
2481		DIRWORD(pD);
2482		CLR_NZV;
2483		SET_NZ16(D);
2484		}
2485
2486		/* $dD STD direct -*0- /
2487		OP_HANDLER( std_di )
2488		{
2489		CLR_NZV;
2490		SET_NZ16(D);
2491		DIRECT;
2492		WM16(EAD,&pD);
2493		}
2494
2495		/* $dE LDU (LDS) direct -*0- /
2496		OP_HANDLER( ldu_di )
2497		{
2498		DIRWORD(pU);
2499		CLR_NZV;
2500		SET_NZ16(U);
2501		}
2502
2503		/* $10dE LDS direct -*0- /
2504		OP_HANDLER( lds_di )
2505		{
2506		DIRWORD(pS);
2507		CLR_NZV;
2508		SET_NZ16(S);
2509		m_int_state \|= M6809_LDS;
2510		}
2511
2512		/* $dF STU (STS) direct -*0- /
2513		OP_HANDLER( stu_di )
2514		{
2515		CLR_NZV;
2516		SET_NZ16(U);
2517		DIRECT;
2518		WM16(EAD,&pU);
2519		}
2520
2521		/* $10dF STS direct -*0- /
2522		OP_HANDLER( sts_di )
2523		{
2524		CLR_NZV;
2525		SET_NZ16(S);
2526		DIRECT;
2527		WM16(EAD,&pS);
2528		}
2529
2530		/* $e0 SUBB indexed ?**** */
2531		OP_HANDLER( subb_ix )
2532		{
2533		UINT16 t,r;
2534		fetch_effective_address();
2535		t = RM(EAD);
2536		r = B - t;
2537		CLR_NZVC;
2538		SET_FLAGS8(B,t,r);
2539		B = r;
2540		}
2541
2542		/* $e1 CMPB indexed ?**** */
2543		OP_HANDLER( cmpb_ix )
2544		{
2545		UINT16 t,r;
2546		fetch_effective_address();
2547		t = RM(EAD);
2548		r = B - t;
2549		CLR_NZVC;
2550		SET_FLAGS8(B,t,r);
2551		}
2552
2553		/* $e2 SBCB indexed ?**** */
2554		OP_HANDLER( sbcb_ix )
2555		{
2556		UINT16 t,r;
2557		fetch_effective_address();
2558		t = RM(EAD);
2559		r = B - t - (CC & CC_C);
2560		CLR_NZVC;
2561		SET_FLAGS8(B,t,r);
2562		B = r;
2563		}
2564
2565		/* $e3 ADDD indexed -**** */
2566		OP_HANDLER( addd_ix )
2567		{
2568		UINT32 r,d;
2569		PAIR b;
2570		fetch_effective_address();
2571		b.d=RM16(EAD);
2572		d = D;
2573		r = d + b.d;
2574		CLR_NZVC;
2575		SET_FLAGS16(d,b.d,r);
2576		D = r;
2577		}
2578
2579		/* $e4 ANDB indexed -*0- /
2580		OP_HANDLER( andb_ix )
2581		{
2582		fetch_effective_address();
2583		B &= RM(EAD);
2584		CLR_NZV;
2585		SET_NZ8(B);
2586		}
2587
2588		/* $e5 BITB indexed -*0- /
2589		OP_HANDLER( bitb_ix )
2590		{
2591		UINT8 r;
2592		fetch_effective_address();
2593		r = B & RM(EAD);
2594		CLR_NZV;
2595		SET_NZ8(r);
2596		}
2597
2598		/* $e6 LDB indexed -*0- /
2599		OP_HANDLER( ldb_ix )
2600		{
2601		fetch_effective_address();
2602		B = RM(EAD);
2603		CLR_NZV;
2604		SET_NZ8(B);
2605		}
2606
2607		/* $e7 STB indexed -*0- /
2608		OP_HANDLER( stb_ix )
2609		{
2610		fetch_effective_address();
2611		CLR_NZV;
2612		SET_NZ8(B);
2613		WM(EAD,B);
2614		}
2615
2616		/* $e8 EORB indexed -*0- /
2617		OP_HANDLER( eorb_ix )
2618		{
2619		fetch_effective_address();
2620		B ^= RM(EAD);
2621		CLR_NZV;
2622		SET_NZ8(B);
2623		}
2624
2625		/* $e9 ADCB indexed ***** */
2626		OP_HANDLER( adcb_ix )
2627		{
2628		UINT16 t,r;
2629		fetch_effective_address();
2630		t = RM(EAD);
2631		r = B + t + (CC & CC_C);
2632		CLR_HNZVC;
2633		SET_FLAGS8(B,t,r);
2634		SET_H(B,t,r);
2635		B = r;
2636		}
2637
2638		/* $eA ORB indexed -*0- /
2639		OP_HANDLER( orb_ix )
2640		{
2641		fetch_effective_address();
2642		B \|= RM(EAD);
2643		CLR_NZV;
2644		SET_NZ8(B);
2645		}
2646
2647		/* $eB ADDB indexed ***** */
2648		OP_HANDLER( addb_ix )
2649		{
2650		UINT16 t,r;
2651		fetch_effective_address();
2652		t = RM(EAD);
2653		r = B + t;
2654		CLR_HNZVC;
2655		SET_FLAGS8(B,t,r);
2656		SET_H(B,t,r);
2657		B = r;
2658		}
2659
2660		/* $eC LDD indexed -*0- /
2661		OP_HANDLER( ldd_ix )
2662		{
2663		fetch_effective_address();
2664		D=RM16(EAD);
2665		CLR_NZV; SET_NZ16(D);
2666		}
2667
2668		/* $eD STD indexed -*0- /
2669		OP_HANDLER( std_ix )
2670		{
2671		fetch_effective_address();
2672		CLR_NZV;
2673		SET_NZ16(D);
2674		WM16(EAD,&pD);
2675		}
2676
2677		/* $eE LDU (LDS) indexed -*0- /
2678		OP_HANDLER( ldu_ix )
2679		{
2680		fetch_effective_address();
2681		U=RM16(EAD);
2682		CLR_NZV;
2683		SET_NZ16(U);
2684		}
2685
2686		/* $10eE LDS indexed -*0- /
2687		OP_HANDLER( lds_ix )
2688		{
2689		fetch_effective_address();
2690		S=RM16(EAD);
2691		CLR_NZV;
2692		SET_NZ16(S);
2693		m_int_state \|= M6809_LDS;
2694		}
2695
2696		/* $eF STU (STS) indexed -*0- /
2697		OP_HANDLER( stu_ix )
2698		{
2699		fetch_effective_address();
2700		CLR_NZV;
2701		SET_NZ16(U);
2702		WM16(EAD,&pU);
2703		}
2704
2705		/* $10eF STS indexed -*0- /
2706		OP_HANDLER( sts_ix )
2707		{
2708		fetch_effective_address();
2709		CLR_NZV;
2710		SET_NZ16(S);
2711		WM16(EAD,&pS);
2712		}
2713
2714		/* $f0 SUBB extended ?**** */
2715		OP_HANDLER( subb_ex )
2716		{
2717		UINT16 t,r;
2718		EXTBYTE(t);
2719		r = B - t;
2720		CLR_NZVC;
2721		SET_FLAGS8(B,t,r);
2722		B = r;
2723		}
2724
2725		/* $f1 CMPB extended ?**** */
2726		OP_HANDLER( cmpb_ex )
2727		{
2728		UINT16 t,r;
2729		EXTBYTE(t);
2730		r = B - t;
2731		CLR_NZVC;
2732		SET_FLAGS8(B,t,r);
2733		}
2734
2735		/* $f2 SBCB extended ?**** */
2736		OP_HANDLER( sbcb_ex )
2737		{
2738		UINT16 t,r;
2739		EXTBYTE(t);
2740		r = B - t - (CC & CC_C);
2741		CLR_NZVC;
2742		SET_FLAGS8(B,t,r);
2743		B = r;
2744		}
2745
2746		/* $f3 ADDD extended -**** */
2747		OP_HANDLER( addd_ex )
2748		{
2749		UINT32 r,d;
2750		PAIR b;
2751		EXTWORD(b);
2752		d = D;
2753		r = d + b.d;
2754		CLR_NZVC;
2755		SET_FLAGS16(d,b.d,r);
2756		D = r;
2757		}
2758
2759		/* $f4 ANDB extended -*0- /
2760		OP_HANDLER( andb_ex )
2761		{
2762		UINT8 t;
2763		EXTBYTE(t);
2764		B &= t;
2765		CLR_NZV;
2766		SET_NZ8(B);
2767		}
2768
2769		/* $f5 BITB extended -*0- /
2770		OP_HANDLER( bitb_ex )
2771		{
2772		UINT8 t,r;
2773		EXTBYTE(t);
2774		r = B & t;
2775		CLR_NZV;
2776		SET_NZ8(r);
2777		}
2778
2779		/* $f6 LDB extended -*0- /
2780		OP_HANDLER( ldb_ex )
2781		{
2782		EXTBYTE(B);
2783		CLR_NZV;
2784		SET_NZ8(B);
2785		}
2786
2787		/* $f7 STB extended -*0- /
2788		OP_HANDLER( stb_ex )
2789		{
2790		CLR_NZV;
2791		SET_NZ8(B);
2792		EXTENDED;
2793		WM(EAD,B);
2794		}
2795
2796		/* $f8 EORB extended -*0- /
2797		OP_HANDLER( eorb_ex )
2798		{
2799		UINT8 t;
2800		EXTBYTE(t);
2801		B ^= t;
2802		CLR_NZV;
2803		SET_NZ8(B);
2804		}
2805
2806		/* $f9 ADCB extended ***** */
2807		OP_HANDLER( adcb_ex )
2808		{
2809		UINT16 t,r;
2810		EXTBYTE(t);
2811		r = B + t + (CC & CC_C);
2812		CLR_HNZVC;
2813		SET_FLAGS8(B,t,r);
2814		SET_H(B,t,r);
2815		B = r;
2816		}
2817
2818		/* $fA ORB extended -*0- /
2819		OP_HANDLER( orb_ex )
2820		{
2821		UINT8 t;
2822		EXTBYTE(t);
2823		B \|= t;
2824		CLR_NZV;
2825		SET_NZ8(B);
2826		}
2827
2828		/* $fB ADDB extended ***** */
2829		OP_HANDLER( addb_ex )
2830		{
2831		UINT16 t,r;
2832		EXTBYTE(t);
2833		r = B + t;
2834		CLR_HNZVC;
2835		SET_FLAGS8(B,t,r);
2836		SET_H(B,t,r);
2837		B = r;
2838		}
2839
2840		/* $fC LDD extended -*0- /
2841		OP_HANDLER( ldd_ex )
2842		{
2843		EXTWORD(pD);
2844		CLR_NZV;
2845		SET_NZ16(D);
2846		}
2847
2848		/* $fD STD extended -*0- /
2849		OP_HANDLER( std_ex )
2850		{
2851		CLR_NZV;
2852		SET_NZ16(D);
2853		EXTENDED;
2854		WM16(EAD,&pD);
2855		}
2856
2857		/* $fE LDU (LDS) extended -*0- /
2858		OP_HANDLER( ldu_ex )
2859		{
2860		EXTWORD(pU);
2861		CLR_NZV;
2862		SET_NZ16(U);
2863		}
2864
2865		/* $10fE LDS extended -*0- /
2866		OP_HANDLER( lds_ex )
2867		{
2868		EXTWORD(pS);
2869		CLR_NZV;
2870		SET_NZ16(S);
2871		m_int_state \|= M6809_LDS;
2872		}
2873
2874		/* $fF STU (STS) extended -*0- /
2875		OP_HANDLER( stu_ex )
2876		{
2877		CLR_NZV;
2878		SET_NZ16(U);
2879		EXTENDED;
2880		WM16(EAD,&pU);
2881		}
2882
2883		/* $10fF STS extended -*0- /
2884		OP_HANDLER( sts_ex )
2885		{
2886		CLR_NZV;
2887		SET_NZ16(S);
2888		EXTENDED;
2889		WM16(EAD,&pS);
2890		}
2891
2892		/* $10xx opcodes */
2893		OP_HANDLER( pref10 )
2894		{
2895		UINT8 ireg2 = m_encrypt_only_first_byte ? ROP_ARG(PCD) : ROP(PCD);
2896		PC++;
2897		switch( ireg2 )
2898		{
2899		case 0x21: lbrn(); m_icount-=5; break;
2900		case 0x22: lbhi(); m_icount-=5; break;
2901		case 0x23: lbls(); m_icount-=5; break;
2902		case 0x24: lbcc(); m_icount-=5; break;
2903		case 0x25: lbcs(); m_icount-=5; break;
2904		case 0x26: lbne(); m_icount-=5; break;
2905		case 0x27: lbeq(); m_icount-=5; break;
2906		case 0x28: lbvc(); m_icount-=5; break;
2907		case 0x29: lbvs(); m_icount-=5; break;
2908		case 0x2a: lbpl(); m_icount-=5; break;
2909		case 0x2b: lbmi(); m_icount-=5; break;
2910		case 0x2c: lbge(); m_icount-=5; break;
2911		case 0x2d: lblt(); m_icount-=5; break;
2912		case 0x2e: lbgt(); m_icount-=5; break;
2913		case 0x2f: lble(); m_icount-=5; break;
2914
2915		case 0x3f: swi2(); m_icount-=20; break;
2916
2917		case 0x83: cmpd_im(); m_icount-=5; break;
2918		case 0x8c: cmpy_im(); m_icount-=5; break;
2919		case 0x8e: ldy_im(); m_icount-=4; break;
2920		case 0x8f: sty_im(); m_icount-=4; break;
2921
2922		case 0x93: cmpd_di(); m_icount-=7; break;
2923		case 0x9c: cmpy_di(); m_icount-=7; break;
2924		case 0x9e: ldy_di(); m_icount-=6; break;
2925		case 0x9f: sty_di(); m_icount-=6; break;
2926
2927		case 0xa3: cmpd_ix(); m_icount-=7; break;
2928		case 0xac: cmpy_ix(); m_icount-=7; break;
2929		case 0xae: ldy_ix(); m_icount-=6; break;
2930		case 0xaf: sty_ix(); m_icount-=6; break;
2931
2932		case 0xb3: cmpd_ex(); m_icount-=8; break;
2933		case 0xbc: cmpy_ex(); m_icount-=8; break;
2934		case 0xbe: ldy_ex(); m_icount-=7; break;
2935		case 0xbf: sty_ex(); m_icount-=7; break;
2936
2937		case 0xce: lds_im(); m_icount-=4; break;
2938		case 0xcf: sts_im(); m_icount-=4; break;
2939
2940		case 0xde: lds_di(); m_icount-=6; break;
2941		case 0xdf: sts_di(); m_icount-=6; break;
2942
2943		case 0xee: lds_ix(); m_icount-=6; break;
2944		case 0xef: sts_ix(); m_icount-=6; break;
2945
2946		case 0xfe: lds_ex(); m_icount-=7; break;
2947		case 0xff: sts_ex(); m_icount-=7; break;
2948
2949		default: IIError(); break;
2950		}
2951		}
2952
2953		/* $11xx opcodes */
2954		OP_HANDLER( pref11 )
2955		{
2956		UINT8 ireg2 = m_encrypt_only_first_byte ? ROP_ARG(PCD) : ROP(PCD);
2957		PC++;
2958		switch( ireg2 )
2959		{
2960		case 0x3f: swi3(); m_icount-=20; break;
2961
2962		case 0x83: cmpu_im(); m_icount-=5; break;
2963		case 0x8c: cmps_im(); m_icount-=5; break;
2964
2965		case 0x93: cmpu_di(); m_icount-=7; break;
2966		case 0x9c: cmps_di(); m_icount-=7; break;
2967
2968		case 0xa3: cmpu_ix(); m_icount-=7; break;
2969		case 0xac: cmps_ix(); m_icount-=7; break;
2970
2971		case 0xb3: cmpu_ex(); m_icount-=8; break;
2972		case 0xbc: cmps_ex(); m_icount-=8; break;
2973
2974		default: IIError(); break;
2975		}
2976		}

trunk/src/emu/cpu/m6809/6809tbl.c
r21564	r21565
1		const UINT8 m6809_base_device::m_flags8i[256] = /* increment */
2		{
3		CC_Z, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
4		0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
5		0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
6		0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
7		0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
8		0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
9		0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
10		0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
11		CC_N\|CC_V,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,
12		CC_N, CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,
13		CC_N, CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,
14		CC_N, CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,
15		CC_N, CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,
16		CC_N, CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,
17		CC_N, CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,
18		CC_N, CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N
19		};
20
21		const UINT8 m6809_base_device::m_flags8d[256] = /* decrement */
22		{
23		CC_Z,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
24		0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
25		0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
26		0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
27		0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
28		0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
29		0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
30		0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,CC_V,
31		CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,
32		CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,
33		CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,
34		CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,
35		CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,
36		CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,
37		CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,
38		CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N
39		};
40
41		/* FIXME: Cycles differ slighly from hd6309 emulation */
42		const UINT8 m6809_base_device::m_index_cycle_em[256] = { /* Index Loopup cycle counts */
43		/* 0xX0, 0xX1, 0xX2, 0xX3, 0xX4, 0xX5, 0xX6, 0xX7, 0xX8, 0xX9, 0xXA, 0xXB, 0xXC, 0xXD, 0xXE, 0xXF */
44
45		/* 0x0X */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
46		/* 0x1X */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
47		/* 0x2X */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
48		/* 0x3X */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
49		/* 0x4X */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
50		/* 0x5X */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
51		/* 0x6X */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
52		/* 0x7X */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
53		/* 0x8X */ 2, 3, 2, 3, 0, 1, 1, 0, 1, 4, 0, 4, 1, 5, 0, 5,
54		/* 0x9X */ 5, 6, 5, 6, 3, 4, 4, 0, 4, 7, 0, 7, 4, 8, 0, 8,
55		/* 0xAX */ 2, 3, 2, 3, 0, 1, 1, 0, 1, 4, 0, 4, 1, 5, 0, 5,
56		/* 0xBX */ 5, 6, 5, 6, 3, 4, 4, 0, 4, 7, 0, 7, 4, 8, 0, 8,
57		/* 0xCX */ 2, 3, 2, 3, 0, 1, 1, 0, 1, 4, 0, 4, 1, 5, 0, 3,
58		/* 0xDX */ 5, 6, 5, 6, 3, 4, 4, 0, 4, 7, 0, 7, 4, 8, 0, 8,
59		/* 0xEX */ 2, 3, 2, 3, 0, 1, 1, 0, 1, 4, 0, 4, 1, 5, 0, 5,
60		/* 0xFX */ 4, 6, 5, 6, 3, 4, 4, 0, 4, 7, 0, 7, 4, 8, 0, 8
61		};
62
63		/* timings for 1-byte opcodes */
64		const UINT8 m6809_base_device::m_cycles1[256] =
65		{
66		/* 0 1 2 3 4 5 6 7 8 9 A B C D E F */
67		/0/ 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 3, 6,
68		/1/ 0, 0, 2, 4, 2, 2, 5, 9, 2, 2, 3, 2, 3, 2, 8, 6,
69		/2/ 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
70		/3/ 4, 4, 4, 4, 5, 5, 5, 5, 2, 5, 3, 6,20,11, 2,19,
71		/4/ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
72		/5/ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
73		/6/ 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 3, 6,
74		/7/ 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 4, 7,
75		/8/ 2, 2, 2, 4, 2, 2, 2, 2, 2, 2, 2, 2, 4, 7, 3, 2,
76		/9/ 4, 4, 4, 6, 4, 4, 4, 4, 4, 4, 4, 4, 6, 7, 5, 5,
77		/A/ 4, 4, 4, 6, 4, 4, 4, 4, 4, 4, 4, 4, 6, 7, 5, 5,
78		/B/ 5, 5, 5, 7, 5, 5, 5, 5, 5, 5, 5, 5, 7, 8, 6, 6,
79		/C/ 2, 2, 2, 4, 2, 2, 2, 2, 2, 2, 2, 2, 3, 2, 3, 3,
80		/D/ 4, 4, 4, 6, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 5, 5,
81		/E/ 4, 4, 4, 6, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 5, 5,
82		/F/ 5, 5, 5, 7, 5, 5, 5, 5, 5, 5, 5, 5, 6, 6, 6, 6
83		};

trunk/src/emu/cpu/m6809/6809tbl.h
r21564	r21565
1		void abx();
2		void adca_di();
3		void adca_ex();
4		void adca_im();
5		void adca_ix();
6		void adcb_di();
7		void adcb_ex();
8		void adcb_im();
9		void adcb_ix();
10		void adda_di();
11		void adda_ex();
12		void adda_im();
13		void adda_ix();
14		void addb_di();
15		void addb_ex();
16		void addb_im();
17		void addb_ix();
18		void addd_di();
19		void addd_ex();
20		void addd_im();
21		void addd_ix();
22		void anda_di();
23		void anda_ex();
24		void anda_im();
25		void anda_ix();
26		void andb_di();
27		void andb_ex();
28		void andb_im();
29		void andb_ix();
30		void andcc();
31		void asla();
32		void aslb();
33		void asl_di();
34		void asl_ex();
35		void asl_ix();
36		void asra();
37		void asrb();
38		void asr_di();
39		void asr_ex();
40		void asr_ix();
41		void bcc();
42		void bcs();
43		void beq();
44		void bge();
45		void bgt();
46		void bhi();
47		void bita_di();
48		void bita_ex();
49		void bita_im();
50		void bita_ix();
51		void bitb_di();
52		void bitb_ex();
53		void bitb_im();
54		void bitb_ix();
55		void ble();
56		void bls();
57		void blt();
58		void bmi();
59		void bne();
60		void bpl();
61		void bra();
62		void brn();
63		void bsr();
64		void bvc();
65		void bvs();
66		void clra();
67		void clrb();
68		void clr_di();
69		void clr_ex();
70		void clr_ix();
71		void cmpa_di();
72		void cmpa_ex();
73		void cmpa_im();
74		void cmpa_ix();
75		void cmpb_di();
76		void cmpb_ex();
77		void cmpb_im();
78		void cmpb_ix();
79		void cmpd_di();
80		void cmpd_ex();
81		void cmpd_im();
82		void cmpd_ix();
83		void cmps_di();
84		void cmps_ex();
85		void cmps_im();
86		void cmps_ix();
87		void cmpu_di();
88		void cmpu_ex();
89		void cmpu_im();
90		void cmpu_ix();
91		void cmpx_di();
92		void cmpx_ex();
93		void cmpx_im();
94		void cmpx_ix();
95		void cmpy_di();
96		void cmpy_ex();
97		void cmpy_im();
98		void cmpy_ix();
99		void coma();
100		void comb();
101		void com_di();
102		void com_ex();
103		void com_ix();
104		void cwai();
105		void daa();
106		void deca();
107		void decb();
108		void dec_di();
109		void dec_ex();
110		void dec_ix();
111		void eora_di();
112		void eora_ex();
113		void eora_im();
114		void eora_ix();
115		void eorb_di();
116		void eorb_ex();
117		void eorb_im();
118		void eorb_ix();
119		void exg();
120		void illegal();
121		void inca();
122		void incb();
123		void inc_di();
124		void inc_ex();
125		void inc_ix();
126		void jmp_di();
127		void jmp_ex();
128		void jmp_ix();
129		void jsr_di();
130		void jsr_ex();
131		void jsr_ix();
132		void lbcc();
133		void lbcs();
134		void lbeq();
135		void lbge();
136		void lbgt();
137		void lbhi();
138		void lble();
139		void lbls();
140		void lblt();
141		void lbmi();
142		void lbne();
143		void lbpl();
144		void lbra();
145		void lbrn();
146		void lbsr();
147		void lbvc();
148		void lbvs();
149		void lda_di();
150		void lda_ex();
151		void lda_im();
152		void lda_ix();
153		void ldb_di();
154		void ldb_ex();
155		void ldb_im();
156		void ldb_ix();
157		void ldd_di();
158		void ldd_ex();
159		void ldd_im();
160		void ldd_ix();
161		void lds_di();
162		void lds_ex();
163		void lds_im();
164		void lds_ix();
165		void ldu_di();
166		void ldu_ex();
167		void ldu_im();
168		void ldu_ix();
169		void ldx_di();
170		void ldx_ex();
171		void ldx_im();
172		void ldx_ix();
173		void ldy_di();
174		void ldy_ex();
175		void ldy_im();
176		void ldy_ix();
177		void leas();
178		void leau();
179		void leax();
180		void leay();
181		void lsra();
182		void lsrb();
183		void lsr_di();
184		void lsr_ex();
185		void lsr_ix();
186		void mul();
187		void nega();
188		void negb();
189		void neg_di();
190		void neg_ex();
191		void neg_ix();
192		void nop();
193		void ora_di();
194		void ora_ex();
195		void ora_im();
196		void ora_ix();
197		void orb_di();
198		void orb_ex();
199		void orb_im();
200		void orb_ix();
201		void orcc();
202		void pref10();
203		void pref11();
204		void pshs();
205		void pshu();
206		void puls();
207		void pulu();
208		void rola();
209		void rolb();
210		void rol_di();
211		void rol_ex();
212		void rol_ix();
213		void rora();
214		void rorb();
215		void ror_di();
216		void ror_ex();
217		void ror_ix();
218		void rti();
219		void rts();
220		void sbca_di();
221		void sbca_ex();
222		void sbca_im();
223		void sbca_ix();
224		void sbcb_di();
225		void sbcb_ex();
226		void sbcb_im();
227		void sbcb_ix();
228		void sex();
229		void sta_di();
230		void sta_ex();
231		void sta_im();
232		void sta_ix();
233		void stb_di();
234		void stb_ex();
235		void stb_im();
236		void stb_ix();
237		void std_di();
238		void std_ex();
239		void std_im();
240		void std_ix();
241		void sts_di();
242		void sts_ex();
243		void sts_im();
244		void sts_ix();
245		void stu_di();
246		void stu_ex();
247		void stu_im();
248		void stu_ix();
249		void stx_di();
250		void stx_ex();
251		void stx_im();
252		void stx_ix();
253		void sty_di();
254		void sty_ex();
255		void sty_im();
256		void sty_ix();
257		void suba_di();
258		void suba_ex();
259		void suba_im();
260		void suba_ix();
261		void subb_di();
262		void subb_ex();
263		void subb_im();
264		void subb_ix();
265		void subd_di();
266		void subd_ex();
267		void subd_im();
268		void subd_ix();
269		void swi2();
270		void swi3();
271		void swi();
272		void sync();
273		void tfr();
274		void tsta();
275		void tstb();
276		void tst_di();
277		void tst_ex();
278		void tst_ix();

trunk/src/emu/cpu/m6809/m6809make.py
r0	r21565
	1	#!/usr/bin/python
	2
	3	import sys
	4	import logging
	5	import fileinput
	6	import re
	7
	8	# Initial state
	9	state = 1
	10	text = ""
	11	dispatch_to_states = { "MAIN" : 0 }
	12	states_to_dispatch = { 0 : "MAIN" }
	13
	14	# Get lines
	15	lines = []
	16	rawlines = re.split('(\n\|; *\n?)', sys.stdin.read())
	17	count = 0
	18	while count < len(rawlines)-1:
	19	line = rawlines[count+0] + rawlines[count+1]
	20	lines.append(line)
	21	count = count + 2
	22
	23	count = 0
	24	while count < len(lines):
	25	# Retrieve this line
	26	line = lines[count]
	27
	28	# Retrieve the whitespace
	29	whitespace = line[:len(line) - len(line.lstrip())]
	30
	31	# Check to see if the next line is a return
	32	next_line_is_return = (count + 1 == len(lines)) or lines[count+1].strip() == "return;"
	33
	34	# Check to see if the next line is a dispatch followed by return
	35	next_line_is_dispatch_and_return = (count + 1 < len(lines)) and re.match('([A-Za-z0-9\t ]+\:)\s\%', lines[count+1]) and lines[count+2].strip() == "return;"
	36
	37	if re.match('([A-Za-z0-9\t ]+\:)\s\%', line):
	38	# This is a dispatch - find the '%'
	39	percent_pos = line.find("%")
	40	dispatch = line[percent_pos+1:].strip("\t\n; ")
	41
	42	# Do we have a label?
	43	label = line[:percent_pos].strip()
	44	if (label != ""):
	45	text += whitespace + label + "\n"
	46	whitespace = whitespace + "\t"
	47
	48	# Create the goto command
	49	if (dispatch[-1:] == "*"):
	50	goto_command = "if (is_register_register_op_16_bit()) goto %s16; else goto %s8;\n" %(dispatch[:-1], dispatch[:-1])
	51	else:
	52	goto_command = "goto %s;\n" % dispatch
	53
	54	# Are we right before a 'return'?
	55	if next_line_is_return:
	56	text += whitespace + goto_command
	57	count = count + 1 # Skip the return
	58	elif next_line_is_dispatch_and_return:
	59	# We are followed by a dispatch/return combo; identify the next dispatch
	60	percent_pos = lines[count+1].find("%")
	61	next_dispatch = lines[count+1][percent_pos+1:].strip("\t\n; ")
	62
	63	# If there is no state number associated with the next dispatch, make one
	64	if not dispatch_to_states.has_key(next_dispatch):
	65	dispatch_to_states[next_dispatch] = state
	66	states_to_dispatch[state] = next_dispatch
	67	state = state + 1
	68
	69	text += whitespace + "push_state(%s);\t// %s\n" % (dispatch_to_states[next_dispatch], next_dispatch)
	70	text += whitespace + goto_command
	71	count = count + 2 # Skip the dispatch/return
	72
	73	else:
	74	# Normal dispatch
	75	text += whitespace + "push_state(%s);\n" % (state)
	76	text += whitespace + goto_command
	77	text += "state_%s:\n" % (state)
	78	state = state + 1
	79	else:
	80	# "Normal" code
	81	# Is there an '@' here?
	82	check_icount = line.lstrip().startswith("@")
	83	if check_icount:
	84	line = line.replace("@", "", 1)
	85
	86	# Output the line
	87	text += line
	88
	89	# If we have to decrement the icount, output more info
	90	if check_icount and not next_line_is_return:
	91	text += whitespace + "if (UNEXPECTED(m_icount <= 0)) { push_state(%s); return; }\n" % (state)
	92	text += "state_%s:\n" % (state)
	93	state = state + 1
	94
	95	# Advance to next line
	96	count = count + 1
	97
	98	# Output the case labels
	99	for i in range(0, state):
	100	print "\tcase %d: goto %s;" % (i, states_to_dispatch[i] if states_to_dispatch.has_key(i) else "state_%s" % str(i))
	101
	102	# Output a default case
	103	print "\tdefault:"
	104	print "\t\tfatalerror(\"Unexpected state\");"
	105	print "\t\tbreak;"
	106	print
	107
	108	# Finally output the text
	109	print text

Property changes on: trunk/src/emu/cpu/m6809/m6809make.py
Added: svn:eol-style + native Added: svn:mime-type + text/plain

trunk/src/emu/cpu/m6809/m6809.h
r21564	r21565
1		/* ~~m6809: Portable 6809 emulator~~ ****************************************/
	1	/*********************************************************************
2	2
	3	m6809.h
	4
	5	Portable Motorola 6809 emulator
	6
	7	**********************************************************************/
	8
3	9	#pragma once
4	10
5	11	#ifndef __M6809_H__
6	12	#define __M6809_H__
7	13
	14
8	15	//**************************************************************************
9	16	// INTERFACE CONFIGURATION MACROS
10	17	//**************************************************************************
11	18
12	19	#define MCFG_CPU_M6809_CONFIG(_config) \
13	20	m6809_base_device::static_set_config(*device, _config);
	21
	22
14	23	//**************************************************************************
15	24	// TYPE DEFINITIONS
16	25	//**************************************************************************
r21564	r21565
37	46	{
38	47	public:
39	48	// construction/destruction
40		m6809_base_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock, const device_type type, int divider);
	49	m6809_base_device(const machine_config &mconfig, const char name, const char tag, device_t *owner, UINT32 clock, const device_type type, int divider);
41	50
42	51	// inline configuration helpers
43	52	static void static_set_config(device_t &device, const m6809_config &config);
r21564	r21565
46	55	// device-level overrides
47	56	virtual void device_start();
48	57	virtual void device_reset();
	58	virtual void device_pre_save();
	59	virtual void device_post_load();
49	60
50	61	// device_execute_interface overrides
51	62	virtual UINT32 execute_min_cycles() const;
r21564	r21565
66	77
67	78	// device_state_interface overrides
68	79	virtual void state_string_export(const device_state_entry &entry, astring &string);
	80
	81	// addressing modes
	82	static const int ADDRESSING_MODE_IMMEDIATE = 0;
	83	static const int ADDRESSING_MODE_EA = 1;
	84	static const int ADDRESSING_MODE_REGISTER_A = 2;
	85	static const int ADDRESSING_MODE_REGISTER_B = 3;
	86	static const int ADDRESSING_MODE_REGISTER_D = 4;
69	87
70		private:
71		UINT32 RM16(UINT32 addr);
72		void WM16(UINT32 addr, PAIR *p);
	88	// register transfer
	89	struct exgtfr_register
	90	{
	91	UINT8 byte_value;
	92	UINT16 word_value;
	93	};
73	94
74		void IIError();
75		void fetch_effective_address();
	95	// flag bits in the cc register
	96	static const UINT8 CC_C = 0x01; // Carry
	97	static const UINT8 CC_V = 0x02; // Overflow
	98	static const UINT8 CC_Z = 0x04; // Zero
	99	static const UINT8 CC_N = 0x08; // Negative
	100	static const UINT8 CC_I = 0x10; // Inhibit IRQ
	101	static const UINT8 CC_H = 0x20; // Half (auxiliary) carry
	102	static const UINT8 CC_F = 0x40; // Inhibit FIRQ
	103	static const UINT8 CC_E = 0x80; // Entire state pushed
76	104
77		void check_irq_lines();
78		void set_irq_line(int irqline, int state);
79		void update_state();
	105	// flag combinations
	106	static const UINT8 CC_VC = CC_V \| CC_C;
	107	static const UINT8 CC_ZC = CC_Z \| CC_C;
	108	static const UINT8 CC_NZ = CC_N \| CC_Z;
	109	static const UINT8 CC_NZC = CC_N \| CC_Z \| CC_C;
	110	static const UINT8 CC_NZV = CC_N \| CC_Z \| CC_V;
	111	static const UINT8 CC_NZVC = CC_N \| CC_Z \| CC_V \| CC_C;
	112	static const UINT8 CC_HNZVC = CC_H \| CC_N \| CC_Z \| CC_V \| CC_C;
80	113
81		offs_t disassemble(char buffer, offs_t pc, const UINT8 oprom, const UINT8 *opram, int options);
	114	// interrupt vectors
	115	static const UINT16 VECTOR_SWI3 = 0xFFF2;
	116	static const UINT16 VECTOR_SWI2 = 0xFFF4;
	117	static const UINT16 VECTOR_FIRQ = 0xFFF6;
	118	static const UINT16 VECTOR_IRQ = 0xFFF8;
	119	static const UINT16 VECTOR_SWI = 0xFFFA;
	120	static const UINT16 VECTOR_NMI = 0xFFFC;
	121	static const UINT16 VECTOR_RESET_FFFE = 0xFFFE;
82	122
83		#include "6809tbl.h"
	123	// CPU registers
	124	PAIR16 m_pc; // program counter
	125	PAIR16 m_ppc; // previous program counter
	126	PAIR16 m_d; // accumulator a and b
	127	PAIR16 m_x, m_y; // index registers
	128	PAIR16 m_u, m_s; // stack pointers
	129	UINT8 m_dp; // direct page register
	130	UINT8 m_cc;
	131	PAIR16 m_temp;
	132	UINT8 m_opcode;
84	133
85		// opcode/condition tables
86		static const UINT8 m_flags8i[256];
87		static const UINT8 m_flags8d[256];
88		static const UINT8 m_index_cycle_em[256];
89		static const UINT8 m_cycles1[256];
	134	// other internal state
	135	bool m_nmi_line;
	136	bool m_nmi_asserted;
	137	bool m_firq_line;
	138	bool m_irq_line;
	139	bool m_lds_encountered;
	140	int m_icount;
	141	int m_addressing_mode;
	142	PAIR16 m_ea; // effective address
90	143
91		typedef void (m6809_base_device::*ophandler)();
	144	// eat cycles
	145	ATTR_FORCE_INLINE void eat(int cycles) { m_icount -= cycles; }
	146	void eat_remaining();
92	147
93		ophandler m_opcode[256];
	148	// read a byte from given memory location
	149	ATTR_FORCE_INLINE UINT8 read_memory(UINT16 address) { eat(1); return m_program->read_byte(address); }
94	150
95		static const ophandler s_opcodetable[256];
	151	// write a byte to given memory location
	152	ATTR_FORCE_INLINE void write_memory(UINT16 address, UINT8 data) { eat(1); m_program->write_byte(address, data); }
96	153
97		protected:
98		const char *m_tag;
	154	// read_opcode() is like read_memory() except it is used for reading opcodes. In the case of a system
	155	// with memory mapped I/O, this function can be used to greatly speed up emulation.
	156	ATTR_FORCE_INLINE UINT8 read_opcode(UINT16 address) { eat(1); return m_direct->read_decrypted_byte(address); }
99	157
100		// address spaces
101		const address_space_config m_program_config;
	158	// read_opcode_arg() is identical to read_opcode() except it is used for reading opcode arguments. This
	159	// difference can be used to support systems that use different encoding mechanisms for opcodes
	160	// and opcode arguments.
	161	ATTR_FORCE_INLINE UINT8 read_opcode_arg(UINT16 address) { eat(1); return m_direct->read_raw_byte(address); }
102	162
103		// CPU registers
104		PAIR m_pc; /* Program counter */
105		PAIR m_ppc; /* Previous program counter */
106		PAIR m_d; /* Accumulator a and b */
107		PAIR m_dp; /* Direct Page register (page in MSB) */
108		PAIR m_u, m_s; /* Stack pointers */
109		PAIR m_x, m_y; /* Index registers */
110		UINT8 m_cc;
111		UINT8 m_ireg; /* First opcode */
112		UINT8 m_irq_state[2];
	163	// read_opcode() and bump the program counter
	164	ATTR_FORCE_INLINE UINT8 read_opcode() { return read_opcode(m_pc.w++); }
	165	ATTR_FORCE_INLINE UINT8 read_opcode_arg() { return read_opcode_arg(m_pc.w++); }
113	166
114		int m_extra_cycles; /* cycles used up by interrupts */
	167	// state stack - implemented as a UINT32
	168	void push_state(UINT8 state) { m_state = (m_state << 8) \| state; }
	169	UINT8 pop_state() { UINT8 result = (UINT8) m_state; m_state >>= 8; return result; }
	170	void reset_state() { m_state = 0; }
115	171
116		PAIR m_ea; /* effective address */
	172	// effective address reading/writing
	173	UINT8 read_ea() { return read_memory(m_ea.w); }
	174	void write_ea(UINT8 data) { write_memory(m_ea.w, data); }
	175	void set_ea(UINT16 ea) { m_ea.w = ea; m_addressing_mode = ADDRESSING_MODE_EA; }
	176	void set_ea_h(UINT8 ea_h) { m_ea.b.h = ea_h; }
	177	void set_ea_l(UINT8 ea_l) { m_ea.b.l = ea_l; m_addressing_mode = ADDRESSING_MODE_EA; }
117	178
118		// other internal states
119		int m_icount;
120		UINT8 m_int_state; /* SYNC and CWAI flags */
121		UINT8 m_nmi_state;
122		int m_clock_divider;
	179	// operand reading/writing
	180	UINT8 read_operand();
	181	UINT8 read_operand(int ordinal);
	182	void write_operand(UINT8 data);
	183	void write_operand(int ordinal, UINT8 data);
123	184
	185	// delay loops
	186	void burn_any_delay_loops();
	187
	188	// instructions
	189	void daa();
	190	void mul();
	191
	192	// miscellaneous
	193	void nop() { }
	194	template<class T> T rotate_right(T value);
	195	template<class T> UINT32 rotate_left(T value);
	196	void set_a() { m_addressing_mode = ADDRESSING_MODE_REGISTER_A; }
	197	void set_b() { m_addressing_mode = ADDRESSING_MODE_REGISTER_B; }
	198	void set_d() { m_addressing_mode = ADDRESSING_MODE_REGISTER_D; }
	199	void set_imm() { m_addressing_mode = ADDRESSING_MODE_IMMEDIATE; }
	200	void set_regop8(UINT8 &reg) { m_reg8 = ® m_reg16 = NULL; }
	201	void set_regop16(PAIR16 &reg) { m_reg16 = ® m_reg8 = NULL; }
	202	UINT8 &regop8() { assert(m_reg8 != NULL); return *m_reg8; }
	203	PAIR16 &regop16() { assert(m_reg16 != NULL); return *m_reg16; }
	204	bool is_register_register_op_16_bit() { return m_reg16 != NULL; }
	205	bool add8_sets_h() { return false; }
	206	bool hd6309_native_mode() { return false; }
	207
	208	// index reg
	209	UINT16 &ireg();
	210
	211	// flags
	212	template<class T> T set_flags(UINT8 mask, T a, T b, UINT32 r);
	213	template<class T> T set_flags(UINT8 mask, T r);
	214
	215	// branch conditions
	216	ATTR_FORCE_INLINE bool cond_hi() { return !(m_cc & CC_ZC); } // BHI/BLS
	217	ATTR_FORCE_INLINE bool cond_cc() { return !(m_cc & CC_C); } // BCC/BCS
	218	ATTR_FORCE_INLINE bool cond_ne() { return !(m_cc & CC_Z); } // BNE/BEQ
	219	ATTR_FORCE_INLINE bool cond_vc() { return !(m_cc & CC_V); } // BVC/BVS
	220	ATTR_FORCE_INLINE bool cond_pl() { return !(m_cc & CC_N); } // BPL/BMI
	221	ATTR_FORCE_INLINE bool cond_ge() { return (m_cc & CC_N ? true : false) == (m_cc & CC_V ? true : false); } // BGE/BLT
	222	ATTR_FORCE_INLINE bool cond_gt() { return cond_ge() && !(m_cc & CC_Z); } // BGT/BLE
	223	ATTR_FORCE_INLINE void set_cond(bool cond) { m_cond = cond; }
	224	ATTR_FORCE_INLINE bool branch_taken() { return m_cond; }
	225
	226	// interrupt registers
	227	bool firq_saves_entire_state() { return false; }
	228	UINT16 partial_state_registers() { return 0x81; }
	229	UINT16 entire_state_registers() { return 0xFF; }
	230
	231	// miscellaneous
	232	exgtfr_register read_exgtfr_register(UINT8 reg);
	233	void write_exgtfr_register(UINT8 reg, exgtfr_register value);
	234	bool is_register_addressing_mode();
	235	bool is_ea_addressing_mode() { return m_addressing_mode == ADDRESSING_MODE_EA; }
	236	UINT16 get_pending_interrupt();
	237	UINT16 check_pending_interrupt();
	238	void log_illegal();
	239
	240	private:
124	241	// address spaces
125		address_space *m_program;
126		direct_read_data *m_direct;
	242	const address_space_config m_program_config;
	243	address_space * m_program;
	244	direct_read_data * m_direct;
	245
	246	// other state
	247	UINT32 m_state;
	248	int m_reg;
	249	UINT8 * m_reg8;
	250	PAIR16 * m_reg16;
	251	bool m_cond;
	252
	253	// incidentals
	254	int m_clock_divider;
	255
	256	// functions
	257	void execute_one();
	258	const char *inputnum_string(int inputnum);
127	259	};
128	260
129	261	// ======================> m6809_device
r21564	r21565
132	264	{
133	265	public:
134	266	// construction/destruction
135		m6809_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
136		: m6809_base_device(mconfig, tag, owner, clock, M6809, 1) { }
	267	m6809_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
137	268	};
138	269
139	270	// ======================> m6809e_device
r21564	r21565
142	273	{
143	274	public:
144	275	// construction/destruction
145		m6809e_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
146		: m6809_base_device(mconfig, tag, owner, clock, M6809E, 4) { }
	276	m6809e_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
147	277	};
148	278
149	279	enum
150	280	{
151		M6809_PC=1, M6809_S, M6809_CC ,M6809_A, M6809_B, M6809_U, M6809_X, M6809_Y,
	281	M6809_PC=1, M6809_S, M6809_CC ,M6809_A, M6809_B, M6809_D, M6809_U, M6809_X, M6809_Y,
152	282	M6809_DP
153	283	};
154	284
r21564	r21565
157	287
158	288	/* M6809e has LIC line to indicate opcode/data fetch */
159	289
160
161		CPU_DISASSEMBLE( m6809 );
162
163	290	#endif /* __M6809_H__ */

trunk/src/emu/cpu/m6809/m6809inl.h
r0	r21565
	1	/*********************************************************************
	2
	3	m6809inl.h
	4
	5	Portable 6809 emulator - Inline functions for the purposes of
	6	optimization
	7
	8	**********************************************************************/
	9
	10	#include "m6809.h"
	11
	12	//-------------------------------------------------
	13	// rotate_right
	14	//-------------------------------------------------
	15
	16	template<class T>
	17	inline ATTR_FORCE_INLINE T m6809_base_device::rotate_right(T value)
	18	{
	19	bool new_carry = (value & 1) ? true : false;
	20	value = value >> 1;
	21
	22	T high_bit = ((T) 1) << (sizeof(T) * 8 - 1);
	23	if (m_cc & CC_C)
	24	value \|= high_bit;
	25	else
	26	value &= ~high_bit;
	27
	28	if (new_carry)
	29	m_cc \|= CC_C;
	30	else
	31	m_cc &= ~CC_C;
	32	return value;
	33	}
	34
	35
	36	//-------------------------------------------------
	37	// rotate_left
	38	//-------------------------------------------------
	39
	40	template<class T>
	41	inline ATTR_FORCE_INLINE UINT32 m6809_base_device::rotate_left(T value)
	42	{
	43	T high_bit = ((T) 1) << (sizeof(T) * 8 - 1);
	44	bool new_carry = (value & high_bit) ? true : false;
	45
	46	UINT32 new_value = value;
	47	new_value <<= 1;
	48
	49	if (m_cc & CC_C)
	50	new_value \|= 1;
	51	else
	52	new_value &= ~1;
	53
	54	if (new_carry)
	55	m_cc \|= CC_C;
	56	else
	57	m_cc &= ~CC_C;
	58	return new_value;
	59	}
	60
	61
	62	//-------------------------------------------------
	63	// read_operand
	64	//-------------------------------------------------
	65
	66	inline ATTR_FORCE_INLINE UINT8 m6809_base_device::read_operand()
	67	{
	68	switch(m_addressing_mode)
	69	{
	70	case ADDRESSING_MODE_EA: return read_memory(m_ea.w);
	71	case ADDRESSING_MODE_IMMEDIATE: return read_opcode_arg();
	72	case ADDRESSING_MODE_REGISTER_A: return m_d.b.h;
	73	case ADDRESSING_MODE_REGISTER_B: return m_d.b.l;
	74	default: fatalerror("Unexpected"); return 0x00;
	75	}
	76	}
	77
	78
	79	//-------------------------------------------------
	80	// read_operand
	81	//-------------------------------------------------
	82
	83	inline ATTR_FORCE_INLINE UINT8 m6809_base_device::read_operand(int ordinal)
	84	{
	85	switch(m_addressing_mode)
	86	{
	87	case ADDRESSING_MODE_EA: return read_memory(m_ea.w + ordinal);
	88	case ADDRESSING_MODE_IMMEDIATE: return read_opcode_arg();
	89	default: fatalerror("Unexpected"); return 0x00;
	90	}
	91	}
	92
	93
	94	//-------------------------------------------------
	95	// write_operand
	96	//-------------------------------------------------
	97
	98	inline ATTR_FORCE_INLINE void m6809_base_device::write_operand(UINT8 data)
	99	{
	100	switch(m_addressing_mode)
	101	{
	102	case ADDRESSING_MODE_IMMEDIATE: /* do nothing */ break;
	103	case ADDRESSING_MODE_EA: write_memory(m_ea.w, data); break;
	104	case ADDRESSING_MODE_REGISTER_A: m_d.b.h = data; break;
	105	case ADDRESSING_MODE_REGISTER_B: m_d.b.l = data; break;
	106	default: fatalerror("Unexpected"); break;
	107	}
	108	}
	109
	110
	111	//-------------------------------------------------
	112	// write_operand
	113	//-------------------------------------------------
	114
	115	inline ATTR_FORCE_INLINE void m6809_base_device::write_operand(int ordinal, UINT8 data)
	116	{
	117	switch(m_addressing_mode)
	118	{
	119	case ADDRESSING_MODE_IMMEDIATE: /* do nothing */ break;
	120	case ADDRESSING_MODE_EA: write_memory(m_ea.w + ordinal, data); break;
	121	default: fatalerror("Unexpected"); break;
	122	}
	123	}
	124
	125
	126	//-------------------------------------------------
	127	// burn_any_delay_loops - optimization for delay
	128	// loops
	129	//-------------------------------------------------
	130
	131	inline ATTR_FORCE_INLINE void m6809_base_device::burn_any_delay_loops()
	132	{
	133	if ((m_opcode == 0x26)
	134	&& !(m_cc & CC_Z)
	135	&& !(machine().debug_flags & DEBUG_FLAG_CALL_HOOK)
	136	&& (read_opcode_arg(m_pc.w) == 0xFC)
	137	&& (read_opcode(m_pc.w - 3) == 0x30)
	138	&& (read_opcode_arg(m_pc.w - 2) == 0x1F))
	139	{
	140	// LEAX -1,X ; BNE *
	141	UINT16 burned_loops = MIN((int) m_x.w - 1, m_icount / 8);
	142	m_x.w -= burned_loops;
	143	eat(burned_loops * 8);
	144	}
	145	}
	146
	147
	148	//-------------------------------------------------
	149	// read_exgtfr_register
	150	//-------------------------------------------------
	151
	152	inline ATTR_FORCE_INLINE m6809_base_device::exgtfr_register m6809_base_device::read_exgtfr_register(UINT8 reg)
	153	{
	154	exgtfr_register result;
	155	result.byte_value = 0xFF;
	156	result.word_value = 0x00FF;
	157
	158	switch(reg & 0x0F)
	159	{
	160	case 0: result.word_value = m_d.w; break; // D
	161	case 1: result.word_value = m_x.w; break; // X
	162	case 2: result.word_value = m_y.w; break; // Y
	163	case 3: result.word_value = m_u.w; break; // U
	164	case 4: result.word_value = m_s.w; break; // S
	165	case 5: result.word_value = m_pc.w; break; // PC
	166	case 8: result.byte_value = m_d.b.h; break; // A
	167	case 9: result.byte_value = m_d.b.l; break; // B
	168	case 10: result.byte_value = m_cc; break; // CC
	169	case 11: result.byte_value = m_dp; break; // DP
	170	}
	171	return result;
	172	}
	173
	174
	175	//-------------------------------------------------
	176	// write_exgtfr_register
	177	//-------------------------------------------------
	178
	179	inline ATTR_FORCE_INLINE void m6809_base_device::write_exgtfr_register(UINT8 reg, m6809_base_device::exgtfr_register value)
	180	{
	181	switch(reg & 0x0F)
	182	{
	183	case 0: m_d.w = value.word_value; break; // D
	184	case 1: m_x.w = value.word_value; break; // X
	185	case 2: m_y.w = value.word_value; break; // Y
	186	case 3: m_u.w = value.word_value; break; // U
	187	case 4: m_s.w = value.word_value; break; // S
	188	case 5: m_pc.w = value.word_value; break; // PC
	189	case 8: m_d.b.h = value.byte_value; break; // A
	190	case 9: m_d.b.l = value.byte_value; break; // B
	191	case 10: m_cc = value.byte_value; break; // CC
	192	case 11: m_dp = value.byte_value; break; // DP
	193	}
	194	}
	195
	196
	197	//-------------------------------------------------
	198	// daa - decimal arithmetic adjustment instruction
	199	//-------------------------------------------------
	200
	201	inline ATTR_FORCE_INLINE void m6809_base_device::daa()
	202	{
	203	UINT16 t, cf = 0;
	204	UINT8 msn = m_d.b.h & 0xf0;
	205	UINT8 lsn = m_d.b.l & 0x0f;
	206
	207	// compute the carry
	208	if (lsn > 0x09 \|\| m_cc & CC_H) cf \|= 0x06;
	209	if (msn > 0x80 && lsn > 0x09 ) cf \|= 0x60;
	210	if (msn > 0x90 \|\| m_cc & CC_C) cf \|= 0x60;
	211
	212	// calculate the result
	213	t = m_d.b.h + cf;
	214
	215	m_cc &= ~CC_V;
	216	if (t & 0x0100) // keep carry from previous operation
	217	m_cc \|= CC_C;
	218
	219	// and put it back into A
	220	m_d.b.h = set_flags(CC_NZ, (UINT8) t);
	221	}
	222
	223
	224	//-------------------------------------------------
	225	// mul
	226	//-------------------------------------------------
	227
	228	inline ATTR_FORCE_INLINE void m6809_base_device::mul()
	229	{
	230	// perform multiply
	231	UINT16 result = ((UINT16) m_d.b.h) * ((UINT16) m_d.b.l);
	232
	233	// set result and Z flag
	234	m_d.w = set_flags(CC_Z, result);
	235
	236	// set C flag
	237	if (m_d.w & 0x0080)
	238	m_cc \|= CC_C;
	239	else
	240	m_cc &= ~CC_C;
	241	}
	242
	243
	244	//-------------------------------------------------
	245	// ireg
	246	//-------------------------------------------------
	247
	248	inline ATTR_FORCE_INLINE UINT16 &m6809_base_device::ireg()
	249	{
	250	switch(m_opcode & 0x60)
	251	{
	252	case 0x00: return m_x.w;
	253	case 0x20: return m_y.w;
	254	case 0x40: return m_u.w;
	255	case 0x60: return m_s.w;
	256	default:
	257	fatalerror("Unexpected");
	258	return m_x.w;
	259	}
	260	}
	261
	262
	263	//-------------------------------------------------
	264	// set_flags
	265	//-------------------------------------------------
	266
	267	template<class T>
	268	inline T m6809_base_device::set_flags(UINT8 mask, T a, T b, UINT32 r)
	269	{
	270	T hi_bit = (T) (1 << (sizeof(T) * 8 - 1));
	271
	272	m_cc &= ~mask;
	273	if (mask & CC_H)
	274	m_cc \|= ((a ^ b ^ r) & 0x10) ? CC_H : 0;
	275	if (mask & CC_N)
	276	m_cc \|= (r & hi_bit) ? CC_N : 0;
	277	if (mask & CC_Z)
	278	m_cc \|= (((T)r) == 0) ? CC_Z : 0;
	279	if (mask & CC_V)
	280	m_cc \|= ((a ^ b ^ r ^ (r >> 1)) & hi_bit) ? CC_V : 0;
	281	if (mask & CC_C)
	282	m_cc \|= (r & (hi_bit << 1)) ? CC_C : 0;
	283	return (T) r;
	284	}
	285
	286
	287	//-------------------------------------------------
	288	// set_flags
	289	//-------------------------------------------------
	290
	291	template<class T>
	292	inline T m6809_base_device::set_flags(UINT8 mask, T r)
	293	{
	294	return set_flags(mask, (T)0, r, r);
	295	}
	296
	297
	298	//-------------------------------------------------
	299	// eat_remaining
	300	//-------------------------------------------------
	301
	302	inline void m6809_base_device::eat_remaining()
	303	{
	304	// we do this in order to be nice to people debugging
	305	UINT16 real_pc = m_pc.w;
	306
	307	eat(m_icount);
	308
	309	m_pc.w = m_ppc.w;
	310	debugger_instruction_hook(this, m_pc.w);
	311	m_pc.w = real_pc;
	312	}
	313
	314
	315
	316	//-------------------------------------------------
	317	// is_register_addressing_mode
	318	//-------------------------------------------------
	319
	320	inline bool m6809_base_device::is_register_addressing_mode()
	321	{
	322	return (m_addressing_mode != ADDRESSING_MODE_IMMEDIATE)
	323	&& (m_addressing_mode != ADDRESSING_MODE_EA);
	324	}
	325
	326
	327
	328	//-------------------------------------------------
	329	// get_pending_interrupt
	330	//-------------------------------------------------
	331
	332	inline UINT16 m6809_base_device::get_pending_interrupt()
	333	{
	334	UINT16 result;
	335	if (m_nmi_asserted)
	336	result = VECTOR_NMI;
	337	else if (!(m_cc & CC_F) && m_firq_line)
	338	result = VECTOR_FIRQ;
	339	else if (!(m_cc & CC_I) && m_irq_line)
	340	result = VECTOR_IRQ;
	341	else
	342	result = 0;
	343	return result;
	344	}
	345
	346
	347
	348	//-------------------------------------------------
	349	// check_pending_interrupt
	350	//-------------------------------------------------
	351
	352	inline UINT16 m6809_base_device::check_pending_interrupt()
	353	{
	354	UINT16 result = get_pending_interrupt();
	355
	356	// check_pending_interrupt() will also invoke the IRQ
	357	// callback for FIRQ and IRQ interrupts
	358	//
	359	// I'm not sure why this is necessary; neither the 6809, 6309
	360	// nor (presumably) Konami had any interrupt acknowledge lines so
	361	// it isn't clear what this is reflecting
	362	switch(result)
	363	{
	364	case VECTOR_FIRQ:
	365	standard_irq_callback(M6809_FIRQ_LINE);
	366	break;
	367	case VECTOR_IRQ:
	368	standard_irq_callback(M6809_IRQ_LINE);
	369	break;
	370	}
	371
	372	return result;
	373	}

Property changes on: trunk/src/emu/cpu/m6809/m6809inl.h
Added: svn:mime-type + text/plain Added: svn:eol-style + native

trunk/src/emu/cpu/m6809/6809dasm.c
r21564	r21565
18	18	#include "emu.h"
19	19	#include "debugger.h"
20	20	#include "m6809.h"
	21	#include "m6809inl.h"
21	22
22	23	// Opcode structure
23	24	struct opcodeinfo
r21564	r21565
363	364	"A", "B", "CC", "DP", "inv", "inv", "inv", "inv"
364	365	};
365	366
366		offs_t m6809_disassemble(~~legacy_cpu_device device,~~ char buffer, offs_t pc, const UINT8 oprom, const UINT8 opram, int options, m6809_base_device *m6809)
	367	offs_t m6809_disassemble(char buffer, offs_t pc, const UINT8 oprom, const UINT8 opram, int options, m6809_base_device m6809)
367	368	{
368	369	UINT8 opcode, mode, pb, pbm, reg;
369	370	const UINT8 *operandarray;
r21564	r21565
621	622
622	623	return p \| flags \| DASMFLAG_SUPPORTED;
623	624	}
624
625		CPU_DISASSEMBLE( m6809 )
626		{
627		return m6809_disassemble(device, buffer, pc, oprom, opram, options, NULL);
628		}
629
630		offs_t m6809_base_device::disassemble(char buffer, offs_t pc, const UINT8 oprom, const UINT8 *opram, int options)
631		{
632		return m6809_disassemble(NULL, buffer, pc, oprom, opram, options, this);
633		}

trunk/src/emu/cpu/m6809/hd6309.ops
r0	r21565
	1	MAIN:
	2	// check interrupt lines
	3	switch(check_pending_interrupt())
	4	{
	5	case VECTOR_NMI: goto NMI;
	6	case VECTOR_FIRQ: goto FIRQ;
	7	case VECTOR_IRQ: goto IRQ;
	8	}
	9
	10	// debugger hook
	11	m_ppc = m_pc;
	12	debugger_instruction_hook(this, m_pc.w);
	13
	14	// opcode fetch
	15	@m_opcode = read_opcode();
	16
	17	// burn delay loops
	18	burn_any_delay_loops();
	19
	20	// dispatch opcode
	21	switch(m_opcode)
	22	{
	23	case 0x00: %DIRECT; %NEG8; return;
	24	case 0x01: %IMM_IM; %DIRECT; %OIM; return;
	25	case 0x02: %IMM_IM; %DIRECT; %AIM; return;
	26	case 0x03: %DIRECT; %COM8; return;
	27	case 0x04: %DIRECT; %LSR8; return;
	28	case 0x05: %IMM_IM; %DIRECT; %EIM; return;
	29	case 0x06: %DIRECT; %ROR8; return;
	30	case 0x07: %DIRECT; %ASR8; return;
	31	case 0x08: %DIRECT; %ASL8; return;
	32	case 0x09: %DIRECT; %ROL8; return;
	33	case 0x0A: %DIRECT; %DEC8; return;
	34	case 0x0B: %IMM_IM; %DIRECT; %TIM; return;
	35	case 0x0C: %DIRECT; %INC8; return;
	36	case 0x0D: %DIRECT; %TST8; return;
	37	case 0x0E: %DIRECT; %JMP; return;
	38	case 0x0F: %DIRECT; %CLR8; return;
	39
	40	case 0x10: %DISPATCH10; return;
	41	case 0x11: %DISPATCH11; return;
	42	case 0x12: %NOP; return;
	43	case 0x13: %SYNC; return;
	44	case 0x14: %SEXW; return;
	45	case 0x16: set_cond(true); %LBRANCH; return;
	46	case 0x17: %LBSR; return;
	47	case 0x19: %DAA; return;
	48	case 0x1A: set_imm(); %ORCC; return;
	49	case 0x1C: set_imm(); %ANDCC; return;
	50	case 0x1D: %SEX; return;
	51	case 0x1E: %EXG; return;
	52	case 0x1F: %TFR; return;
	53
	54	case 0x20: set_cond(true); %BRANCH; return;
	55	case 0x21: set_cond(false); %BRANCH; return;
	56	case 0x22: set_cond(cond_hi()); %BRANCH; return;
	57	case 0x23: set_cond(!cond_hi()); %BRANCH; return;
	58	case 0x24: set_cond(cond_cc()); %BRANCH; return;
	59	case 0x25: set_cond(!cond_cc()); %BRANCH; return;
	60	case 0x26: set_cond(cond_ne()); %BRANCH; return;
	61	case 0x27: set_cond(!cond_ne()); %BRANCH; return;
	62	case 0x28: set_cond(cond_vc()); %BRANCH; return;
	63	case 0x29: set_cond(!cond_vc()); %BRANCH; return;
	64	case 0x2A: set_cond(cond_pl()); %BRANCH; return;
	65	case 0x2B: set_cond(!cond_pl()); %BRANCH; return;
	66	case 0x2C: set_cond(cond_ge()); %BRANCH; return;
	67	case 0x2D: set_cond(!cond_ge()); %BRANCH; return;
	68	case 0x2E: set_cond(cond_gt()); %BRANCH; return;
	69	case 0x2F: set_cond(!cond_gt()); %BRANCH; return;
	70
	71	case 0x30: set_regop16(m_x); %INDEXED; %LEA_xy; return;
	72	case 0x31: set_regop16(m_y); %INDEXED; %LEA_xy; return;
	73	case 0x32: set_regop16(m_s); %INDEXED; %LEA_us; return;
	74	case 0x33: set_regop16(m_u); %INDEXED; %LEA_us; return;
	75	case 0x34: %PSHS; return;
	76	case 0x35: %PULS; return;
	77	case 0x36: %PSHU; return;
	78	case 0x37: %PULU; return;
	79	case 0x39: %RTS; return;
	80	case 0x3A: %ABX; return;
	81	case 0x3B: %RTI; return;
	82	case 0x3C: %CWAI; return;
	83	case 0x3D: %MUL; return;
	84	case 0x3F: %SWI; return;
	85
	86	case 0x40: set_a(); %NEG8; return;
	87	case 0x43: set_a(); %COM8; return;
	88	case 0x44: set_a(); %LSR8; return;
	89	case 0x46: set_a(); %ROR8; return;
	90	case 0x47: set_a(); %ASR8; return;
	91	case 0x48: set_a(); %ASL8; return;
	92	case 0x49: set_a(); %ROL8; return;
	93	case 0x4A: set_a(); %DEC8; return;
	94	case 0x4C: set_a(); %INC8; return;
	95	case 0x4D: set_a(); %TST8; return;
	96	case 0x4F: set_a(); %CLR8; return;
	97
	98	case 0x50: set_b(); %NEG8; return;
	99	case 0x53: set_b(); %COM8; return;
	100	case 0x54: set_b(); %LSR8; return;
	101	case 0x56: set_b(); %ROR8; return;
	102	case 0x57: set_b(); %ASR8; return;
	103	case 0x58: set_b(); %ASL8; return;
	104	case 0x59: set_b(); %ROL8; return;
	105	case 0x5A: set_b(); %DEC8; return;
	106	case 0x5C: set_b(); %INC8; return;
	107	case 0x5D: set_b(); %TST8; return;
	108	case 0x5F: set_b(); %CLR8; return;
	109
	110	case 0x60: %INDEXED; %NEG8; return;
	111	case 0x61: %IMM_IM; %INDEXED; %OIM; return;
	112	case 0x62: %IMM_IM; %INDEXED; %AIM; return;
	113	case 0x63: %INDEXED; %COM8; return;
	114	case 0x64: %INDEXED; %LSR8; return;
	115	case 0x65: %IMM_IM; %INDEXED; %EIM; return;
	116	case 0x66: %INDEXED; %ROR8; return;
	117	case 0x67: %INDEXED; %ASR8; return;
	118	case 0x68: %INDEXED; %ASL8; return;
	119	case 0x69: %INDEXED; %ROL8; return;
	120	case 0x6A: %INDEXED; %DEC8; return;
	121	case 0x6B: %IMM_IM; %INDEXED; %TIM; return;
	122	case 0x6C: %INDEXED; %INC8; return;
	123	case 0x6D: %INDEXED; %TST8; return;
	124	case 0x6E: %INDEXED; %JMP; return;
	125	case 0x6F: %INDEXED; %CLR8; return;
	126
	127	case 0x70: %EXTENDED; %NEG8; return;
	128	case 0x71: %IMM_IM; %EXTENDED; %OIM; return;
	129	case 0x72: %IMM_IM; %EXTENDED; %AIM; return;
	130	case 0x73: %EXTENDED; %COM8; return;
	131	case 0x74: %EXTENDED; %LSR8; return;
	132	case 0x75: %IMM_IM; %EXTENDED; %EIM; return;
	133	case 0x76: %EXTENDED; %ROR8; return;
	134	case 0x77: %EXTENDED; %ASR8; return;
	135	case 0x78: %EXTENDED; %ASL8; return;
	136	case 0x79: %EXTENDED; %ROL8; return;
	137	case 0x7A: %EXTENDED; %DEC8; return;
	138	case 0x7B: %IMM_IM; %EXTENDED; %TIM; return;
	139	case 0x7C: %EXTENDED; %INC8; return;
	140	case 0x7D: %EXTENDED; %TST8; return;
	141	case 0x7E: %EXTENDED; %JMP; return;
	142	case 0x7F: %EXTENDED; %CLR8; return;
	143
	144	case 0x80: set_regop8(m_d.b.h); set_imm(); %SUB8; return;
	145	case 0x81: set_regop8(m_d.b.h); set_imm(); %CMP8; return;
	146	case 0x82: set_regop8(m_d.b.h); set_imm(); %SBC8; return;
	147	case 0x83: set_regop16(m_d); set_imm(); %SUB16; return;
	148	case 0x84: set_regop8(m_d.b.h); set_imm(); %AND8; return;
	149	case 0x85: set_regop8(m_d.b.h); set_imm(); %BIT8; return;
	150	case 0x86: set_regop8(m_d.b.h); set_imm(); %LD8; return;
	151	case 0x88: set_regop8(m_d.b.h); set_imm(); %EOR8; return;
	152	case 0x89: set_regop8(m_d.b.h); set_imm(); %ADC8; return;
	153	case 0x8A: set_regop8(m_d.b.h); set_imm(); %OR8; return;
	154	case 0x8B: set_regop8(m_d.b.h); set_imm(); %ADD8; return;
	155	case 0x8C: set_regop16(m_x); set_imm(); %CMP16; return;
	156	case 0x8D: %BSR; return;
	157	case 0x8E: set_regop16(m_x); set_imm(); %LD16; return;
	158
	159	case 0x90: set_regop8(m_d.b.h); %DIRECT; %SUB8; return;
	160	case 0x91: set_regop8(m_d.b.h); %DIRECT; %CMP8; return;
	161	case 0x92: set_regop8(m_d.b.h); %DIRECT; %SBC8; return;
	162	case 0x93: set_regop16(m_d); %DIRECT; %SUB16; return;
	163	case 0x94: set_regop8(m_d.b.h); %DIRECT; %AND8; return;
	164	case 0x95: set_regop8(m_d.b.h); %DIRECT; %BIT8; return;
	165	case 0x96: set_regop8(m_d.b.h); %DIRECT; %LD8; return;
	166	case 0x97: set_regop8(m_d.b.h); %DIRECT; %ST8; return;
	167	case 0x98: set_regop8(m_d.b.h); %DIRECT; %EOR8; return;
	168	case 0x99: set_regop8(m_d.b.h); %DIRECT; %ADC8; return;
	169	case 0x9A: set_regop8(m_d.b.h); %DIRECT; %OR8; return;
	170	case 0x9B: set_regop8(m_d.b.h); %DIRECT; %ADD8; return;
	171	case 0x9C: set_regop16(m_x); %DIRECT; %CMP16; return;
	172	case 0x9D: %DIRECT; %JSR; return;
	173	case 0x9E: set_regop16(m_x); %DIRECT; %LD16; return;
	174	case 0x9F: set_regop16(m_x); %DIRECT; %ST16; return;
	175
	176	case 0xA0: set_regop8(m_d.b.h); %INDEXED; %SUB8; return;
	177	case 0xA1: set_regop8(m_d.b.h); %INDEXED; %CMP8; return;
	178	case 0xA2: set_regop8(m_d.b.h); %INDEXED; %SBC8; return;
	179	case 0xA3: set_regop16(m_d); %INDEXED; %SUB16; return;
	180	case 0xA4: set_regop8(m_d.b.h); %INDEXED; %AND8; return;
	181	case 0xA5: set_regop8(m_d.b.h); %INDEXED; %BIT8; return;
	182	case 0xA6: set_regop8(m_d.b.h); %INDEXED; %LD8; return;
	183	case 0xA7: set_regop8(m_d.b.h); %INDEXED; %ST8; return;
	184	case 0xA8: set_regop8(m_d.b.h); %INDEXED; %EOR8; return;
	185	case 0xA9: set_regop8(m_d.b.h); %INDEXED; %ADC8; return;
	186	case 0xAA: set_regop8(m_d.b.h); %INDEXED; %OR8; return;
	187	case 0xAB: set_regop8(m_d.b.h); %INDEXED; %ADD8; return;
	188	case 0xAC: set_regop16(m_x); %INDEXED; %CMP16; return;
	189	case 0xAD: %INDEXED; %JSR_ind; return;
	190	case 0xAE: set_regop16(m_x); %INDEXED; %LD16; return;
	191	case 0xAF: set_regop16(m_x); %INDEXED; %ST16; return;
	192
	193	case 0xB0: set_regop8(m_d.b.h); %EXTENDED; %SUB8; return;
	194	case 0xB1: set_regop8(m_d.b.h); %EXTENDED; %CMP8; return;
	195	case 0xB2: set_regop8(m_d.b.h); %EXTENDED; %SBC8; return;
	196	case 0xB3: set_regop16(m_d); %EXTENDED; %SUB16; return;
	197	case 0xB4: set_regop8(m_d.b.h); %EXTENDED; %AND8; return;
	198	case 0xB5: set_regop8(m_d.b.h); %EXTENDED; %BIT8; return;
	199	case 0xB6: set_regop8(m_d.b.h); %EXTENDED; %LD8; return;
	200	case 0xB7: set_regop8(m_d.b.h); %EXTENDED; %ST8; return;
	201	case 0xB8: set_regop8(m_d.b.h); %EXTENDED; %EOR8; return;
	202	case 0xB9: set_regop8(m_d.b.h); %EXTENDED; %ADC8; return;
	203	case 0xBA: set_regop8(m_d.b.h); %EXTENDED; %OR8; return;
	204	case 0xBB: set_regop8(m_d.b.h); %EXTENDED; %ADD8; return;
	205	case 0xBC: set_regop16(m_x); %EXTENDED; %CMP16; return;
	206	case 0xBD: %EXTENDED; %JSR; return;
	207	case 0xBE: set_regop16(m_x); %EXTENDED; %LD16; return;
	208	case 0xBF: set_regop16(m_x); %EXTENDED; %ST16; return;
	209
	210	case 0xC0: set_regop8(m_d.b.l); set_imm(); %SUB8; return;
	211	case 0xC1: set_regop8(m_d.b.l); set_imm(); %CMP8; return;
	212	case 0xC2: set_regop8(m_d.b.l); set_imm(); %SBC8; return;
	213	case 0xC3: set_regop16(m_d); set_imm(); %ADD16; return;
	214	case 0xC4: set_regop8(m_d.b.l); set_imm(); %AND8; return;
	215	case 0xC5: set_regop8(m_d.b.l); set_imm(); %BIT8; return;
	216	case 0xC6: set_regop8(m_d.b.l); set_imm(); %LD8; return;
	217	case 0xC8: set_regop8(m_d.b.l); set_imm(); %EOR8; return;
	218	case 0xC9: set_regop8(m_d.b.l); set_imm(); %ADC8; return;
	219	case 0xCA: set_regop8(m_d.b.l); set_imm(); %OR8; return;
	220	case 0xCB: set_regop8(m_d.b.l); set_imm(); %ADD8; return;
	221	case 0xCC: set_regop16(m_d); set_imm(); %LD16; return;
	222	case 0xCD: set_imm(); %LDQ; return;
	223	case 0xCE: set_regop16(m_u); set_imm(); %LD16; return;
	224
	225	case 0xD0: set_regop8(m_d.b.l); %DIRECT; %SUB8; return;
	226	case 0xD1: set_regop8(m_d.b.l); %DIRECT; %CMP8; return;
	227	case 0xD2: set_regop8(m_d.b.l); %DIRECT; %SBC8; return;
	228	case 0xD3: set_regop16(m_d); %DIRECT; %ADD16; return;
	229	case 0xD4: set_regop8(m_d.b.l); %DIRECT; %AND8; return;
	230	case 0xD5: set_regop8(m_d.b.l); %DIRECT; %BIT8; return;
	231	case 0xD6: set_regop8(m_d.b.l); %DIRECT; %LD8; return;
	232	case 0xD7: set_regop8(m_d.b.l); %DIRECT; %ST8; return;
	233	case 0xD8: set_regop8(m_d.b.l); %DIRECT; %EOR8; return;
	234	case 0xD9: set_regop8(m_d.b.l); %DIRECT; %ADC8; return;
	235	case 0xDA: set_regop8(m_d.b.l); %DIRECT; %OR8; return;
	236	case 0xDB: set_regop8(m_d.b.l); %DIRECT; %ADD8; return;
	237	case 0xDC: set_regop16(m_d); %DIRECT; %LD16; return;
	238	case 0xDD: set_regop16(m_d); %DIRECT; %ST16; return;
	239	case 0xDE: set_regop16(m_u); %DIRECT; %LD16; return;
	240	case 0xDF: set_regop16(m_u); %DIRECT; %ST16; return;
	241
	242	case 0xE0: set_regop8(m_d.b.l); %INDEXED; %SUB8; return;
	243	case 0xE1: set_regop8(m_d.b.l); %INDEXED; %CMP8; return;
	244	case 0xE2: set_regop8(m_d.b.l); %INDEXED; %SBC8; return;
	245	case 0xE3: set_regop16(m_d); %INDEXED; %ADD16; return;
	246	case 0xE4: set_regop8(m_d.b.l); %INDEXED; %AND8; return;
	247	case 0xE5: set_regop8(m_d.b.l); %INDEXED; %BIT8; return;
	248	case 0xE6: set_regop8(m_d.b.l); %INDEXED; %LD8; return;
	249	case 0xE7: set_regop8(m_d.b.l); %INDEXED; %ST8; return;
	250	case 0xE8: set_regop8(m_d.b.l); %INDEXED; %EOR8; return;
	251	case 0xE9: set_regop8(m_d.b.l); %INDEXED; %ADC8; return;
	252	case 0xEA: set_regop8(m_d.b.l); %INDEXED; %OR8; return;
	253	case 0xEB: set_regop8(m_d.b.l); %INDEXED; %ADD8; return;
	254	case 0xEC: set_regop16(m_d); %INDEXED; %LD16; return;
	255	case 0xED: set_regop16(m_d); %INDEXED; %ST16; return;
	256	case 0xEE: set_regop16(m_u); %INDEXED; %LD16; return;
	257	case 0xEF: set_regop16(m_u); %INDEXED; %ST16; return;
	258
	259	case 0xF0: set_regop8(m_d.b.l); %EXTENDED; %SUB8; return;
	260	case 0xF1: set_regop8(m_d.b.l); %EXTENDED; %CMP8; return;
	261	case 0xF2: set_regop8(m_d.b.l); %EXTENDED; %SBC8; return;
	262	case 0xF3: set_regop16(m_d); %EXTENDED; %ADD16; return;
	263	case 0xF4: set_regop8(m_d.b.l); %EXTENDED; %AND8; return;
	264	case 0xF5: set_regop8(m_d.b.l); %EXTENDED; %BIT8; return;
	265	case 0xF6: set_regop8(m_d.b.l); %EXTENDED; %LD8; return;
	266	case 0xF7: set_regop8(m_d.b.l); %EXTENDED; %ST8; return;
	267	case 0xF8: set_regop8(m_d.b.l); %EXTENDED; %EOR8; return;
	268	case 0xF9: set_regop8(m_d.b.l); %EXTENDED; %ADC8; return;
	269	case 0xFA: set_regop8(m_d.b.l); %EXTENDED; %OR8; return;
	270	case 0xFB: set_regop8(m_d.b.l); %EXTENDED; %ADD8; return;
	271	case 0xFC: set_regop16(m_d); %EXTENDED; %LD16; return;
	272	case 0xFD: set_regop16(m_d); %EXTENDED; %ST16; return;
	273	case 0xFE: set_regop16(m_u); %EXTENDED; %LD16; return;
	274	case 0xFF: set_regop16(m_u); %EXTENDED; %ST16; return;
	275	default: %ILLEGAL; return;
	276	}
	277	return;
	278
	279	DISPATCH10:
	280	@m_opcode = read_opcode();
	281	switch(m_opcode)
	282	{
	283	case 0x20: set_cond(true); %LBRANCH; return;
	284	case 0x21: set_cond(false); %LBRANCH; return;
	285	case 0x22: set_cond(cond_hi()); %LBRANCH; return;
	286	case 0x23: set_cond(!cond_hi()); %LBRANCH; return;
	287	case 0x24: set_cond(cond_cc()); %LBRANCH; return;
	288	case 0x25: set_cond(!cond_cc()); %LBRANCH; return;
	289	case 0x26: set_cond(cond_ne()); %LBRANCH; return;
	290	case 0x27: set_cond(!cond_ne()); %LBRANCH; return;
	291	case 0x28: set_cond(cond_vc()); %LBRANCH; return;
	292	case 0x29: set_cond(!cond_vc()); %LBRANCH; return;
	293	case 0x2A: set_cond(cond_pl()); %LBRANCH; return;
	294	case 0x2B: set_cond(!cond_pl()); %LBRANCH; return;
	295	case 0x2C: set_cond(cond_ge()); %LBRANCH; return;
	296	case 0x2D: set_cond(!cond_ge()); %LBRANCH; return;
	297	case 0x2E: set_cond(cond_gt()); %LBRANCH; return;
	298	case 0x2F: set_cond(!cond_gt()); %LBRANCH; return;
	299
	300	case 0x30: register_register_op(); %ADD*; return;
	301	case 0x31: register_register_op(); %ADC*; return;
	302	case 0x32: register_register_op(); %SUB*; return;
	303	case 0x33: register_register_op(); %SBC*; return;
	304	case 0x34: register_register_op(); %AND*; return;
	305	case 0x35: register_register_op(); %OR*; return;
	306	case 0x36: register_register_op(); %EOR*; return;
	307	case 0x37: register_register_op(); %CMP*; return;
	308	case 0x38: %PSHSW; return;
	309	case 0x39: %PULSW; return;
	310	case 0x3A: %PSHUW; return;
	311	case 0x3B: %PULUW; return;
	312	case 0x3F: %SWI2; return;
	313
	314	case 0x40: set_d(); %NEG16; return;
	315	case 0x43: set_d(); %COM16; return;
	316	case 0x44: set_d(); %LSR16; return;
	317	case 0x46: set_d(); %ROR16; return;
	318	case 0x47: set_d(); %ASR16; return;
	319	case 0x48: set_d(); %ASL16; return;
	320	case 0x49: set_d(); %ROL16; return;
	321	case 0x4A: set_d(); %DEC16; return;
	322	case 0x4C: set_d(); %INC16; return;
	323	case 0x4D: set_d(); %TST16; return;
	324	case 0x4F: set_d(); %CLR16; return;
	325
	326	case 0x50: set_w(); %NEG16; return;
	327	case 0x53: set_w(); %COM16; return;
	328	case 0x54: set_w(); %LSR16; return;
	329	case 0x56: set_w(); %ROR16; return;
	330	case 0x57: set_w(); %ASR16; return;
	331	case 0x58: set_w(); %ASL16; return;
	332	case 0x59: set_w(); %ROL16; return;
	333	case 0x5A: set_w(); %DEC16; return;
	334	case 0x5C: set_w(); %INC16; return;
	335	case 0x5D: set_w(); %TST16; return;
	336	case 0x5F: set_w(); %CLR16; return;
	337
	338	case 0x80: set_regop16(m_w); set_imm(); %SUB16; return;
	339	case 0x81: set_regop16(m_w); set_imm(); %CMP16; return;
	340	case 0x82: set_regop16(m_d); set_imm(); %SBC16; return;
	341	case 0x83: set_regop16(m_d); set_imm(); %CMP16; return;
	342	case 0x84: set_regop16(m_d); set_imm(); %AND16; return;
	343	case 0x85: set_regop16(m_d); set_imm(); %BIT16; return;
	344	case 0x86: set_regop16(m_w); set_imm(); %LD16; return;
	345	case 0x88: set_regop16(m_d); set_imm(); %EOR16; return;
	346	case 0x89: set_regop16(m_d); set_imm(); %ADC16; return;
	347	case 0x8A: set_regop16(m_d); set_imm(); %OR16; return;
	348	case 0x8B: set_regop16(m_w); set_imm(); %ADD16; return;
	349	case 0x8C: set_regop16(m_y); set_imm(); %CMP16; return;
	350	case 0x8E: set_regop16(m_y); set_imm(); %LD16; return;
	351
	352	case 0x90: set_regop16(m_w); %DIRECT; %SUB16; return;
	353	case 0x91: set_regop16(m_w); %DIRECT; %CMP16; return;
	354	case 0x92: set_regop16(m_d); %DIRECT; %SBC16; return;
	355	case 0x93: set_regop16(m_d); %DIRECT; %CMP16; return;
	356	case 0x94: set_regop16(m_d); %DIRECT; %AND16; return;
	357	case 0x95: set_regop16(m_d); %DIRECT; %BIT16; return;
	358	case 0x96: set_regop16(m_w); %DIRECT; %LD16; return;
	359	case 0x97: set_regop16(m_w); %DIRECT; %ST16; return;
	360	case 0x98: set_regop16(m_d); %DIRECT; %EOR16; return;
	361	case 0x99: set_regop16(m_d); %DIRECT; %ADC16; return;
	362	case 0x9A: set_regop16(m_d); %DIRECT; %OR16; return;
	363	case 0x9B: set_regop16(m_w); %DIRECT; %ADD16; return;
	364	case 0x9C: set_regop16(m_y); %DIRECT; %CMP16; return;
	365	case 0x9E: set_regop16(m_y); %DIRECT; %LD16; return;
	366	case 0x9F: set_regop16(m_y); %DIRECT; %ST16; return;
	367
	368	case 0xA0: set_regop16(m_w); %INDEXED; %SUB16; return;
	369	case 0xA1: set_regop16(m_w); %INDEXED; %CMP16; return;
	370	case 0xA2: set_regop16(m_d); %INDEXED; %SBC16; return;
	371	case 0xA3: set_regop16(m_d); %INDEXED; %CMP16; return;
	372	case 0xA4: set_regop16(m_d); %INDEXED; %AND16; return;
	373	case 0xA5: set_regop16(m_d); %INDEXED; %BIT16; return;
	374	case 0xA6: set_regop16(m_w); %INDEXED; %LD16; return;
	375	case 0xA7: set_regop16(m_w); %INDEXED; %ST16; return;
	376	case 0xA8: set_regop16(m_d); %INDEXED; %EOR16; return;
	377	case 0xA9: set_regop16(m_d); %INDEXED; %ADC16; return;
	378	case 0xAA: set_regop16(m_d); %INDEXED; %OR16; return;
	379	case 0xAB: set_regop16(m_w); %INDEXED; %ADD16; return;
	380	case 0xAC: set_regop16(m_y); %INDEXED; %CMP16; return;
	381	case 0xAE: set_regop16(m_y); %INDEXED; %LD16; return;
	382	case 0xAF: set_regop16(m_y); %INDEXED; %ST16; return;
	383
	384	case 0xB0: set_regop16(m_w); %EXTENDED; %SUB16; return;
	385	case 0xB1: set_regop16(m_w); %EXTENDED; %CMP16; return;
	386	case 0xB2: set_regop16(m_d); %EXTENDED; %SBC16; return;
	387	case 0xB3: set_regop16(m_d); %EXTENDED; %CMP16; return;
	388	case 0xB4: set_regop16(m_d); %EXTENDED; %AND16; return;
	389	case 0xB5: set_regop16(m_d); %EXTENDED; %BIT16; return;
	390	case 0xB6: set_regop16(m_w); %EXTENDED; %LD16; return;
	391	case 0xB7: set_regop16(m_w); %EXTENDED; %ST16; return;
	392	case 0xB8: set_regop16(m_d); %EXTENDED; %EOR16; return;
	393	case 0xB9: set_regop16(m_d); %EXTENDED; %ADC16; return;
	394	case 0xBA: set_regop16(m_d); %EXTENDED; %OR16; return;
	395	case 0xBB: set_regop16(m_w); %EXTENDED; %ADD16; return;
	396	case 0xBC: set_regop16(m_y); %EXTENDED; %CMP16; return;
	397	case 0xBE: set_regop16(m_y); %EXTENDED; %LD16; return;
	398	case 0xBF: set_regop16(m_y); %EXTENDED; %ST16; return;
	399
	400	case 0xCE: set_regop16(m_s); set_imm(); %LD16; return;
	401	case 0xDC: %DIRECT; %LDQ; return;
	402	case 0xDD: %DIRECT; %STQ; return;
	403	case 0xDE: set_regop16(m_s); %DIRECT; %LD16; return;
	404	case 0xDF: set_regop16(m_s); %DIRECT; %ST16; return;
	405	case 0xEC: %INDEXED; %LDQ; return;
	406	case 0xED: %INDEXED; %STQ; return;
	407	case 0xEE: set_regop16(m_s); %INDEXED; %LD16; return;
	408	case 0xEF: set_regop16(m_s); %INDEXED; %ST16; return;
	409	case 0xFC: %EXTENDED; %LDQ; return;
	410	case 0xFD: %EXTENDED; %STQ; return;
	411	case 0xFE: set_regop16(m_s); %EXTENDED; %LD16; return;
	412	case 0xFF: set_regop16(m_s); %EXTENDED; %ST16; return;
	413
	414	default: %ILLEGAL; return;
	415	}
	416	return;
	417
	418	DISPATCH11:
	419	@m_opcode = read_opcode();
	420	switch(m_opcode)
	421	{
	422	case 0x30: %BAND; return;
	423	case 0x31: %BIAND; return;
	424	case 0x32: %BOR; return;
	425	case 0x33: %BIOR; return;
	426	case 0x34: %BEOR; return;
	427	case 0x35: %BIEOR; return;
	428	case 0x36: %LDBT; return;
	429	case 0x37: %STBT; return;
	430	case 0x38: %TFM; return;
	431	case 0x39: %TFM; return;
	432	case 0x3A: %TFM; return;
	433	case 0x3B: %TFM; return;
	434	case 0x3C: set_regop8(m_md); set_imm(); %BIT8; return;
	435	case 0x3D: set_regop8(m_md); set_imm(); %LD8; return;
	436	case 0x3F: %SWI3; return;
	437
	438	case 0x43: set_e(); %COM8; return;
	439	case 0x4A: set_e(); %DEC8; return;
	440	case 0x4C: set_e(); %INC8; return;
	441	case 0x4D: set_e(); %TST8; return;
	442	case 0x4F: set_e(); %CLR8; return;
	443
	444	case 0x53: set_f(); %COM8; return;
	445	case 0x5A: set_f(); %DEC8; return;
	446	case 0x5C: set_f(); %INC8; return;
	447	case 0x5D: set_f(); %TST8; return;
	448	case 0x5F: set_f(); %CLR8; return;
	449
	450	case 0x80: set_regop8(m_w.b.h); set_imm(); %SUB8; return;
	451	case 0x81: set_regop8(m_w.b.h); set_imm(); %CMP8; return;
	452	case 0x83: set_regop16(m_u); set_imm(); %CMP16; return;
	453	case 0x86: set_regop8(m_w.b.h); set_imm(); %LD8; return;
	454	case 0x8B: set_regop8(m_w.b.h); set_imm(); %ADD8; return;
	455	case 0x8C: set_regop16(m_s); set_imm(); %CMP16; return;
	456	case 0x8D: set_imm(); %DIVD; return;
	457	case 0x8E: set_imm(); %DIVQ; return;
	458	case 0x8F: set_imm(); %MULD; return;
	459
	460	case 0x90: set_regop8(m_w.b.h); %DIRECT; %SUB8; return;
	461	case 0x91: set_regop8(m_w.b.h); %DIRECT; %CMP8; return;
	462	case 0x93: set_regop16(m_u); %DIRECT; %CMP16; return;
	463	case 0x96: set_regop8(m_w.b.h); %DIRECT; %LD8; return;
	464	case 0x97: set_regop8(m_w.b.h); %DIRECT; %ST8; return;
	465	case 0x9B: set_regop8(m_w.b.h); %DIRECT; %ADD8; return;
	466	case 0x9C: set_regop16(m_s); %DIRECT; %CMP16; return;
	467	case 0x9D: %DIRECT; %DIVD; return;
	468	case 0x9E: %DIRECT; %DIVQ; return;
	469	case 0x9F: %DIRECT; %MULD; return;
	470
	471	case 0xA0: set_regop8(m_w.b.h); %INDEXED; %SUB8; return;
	472	case 0xA1: set_regop8(m_w.b.h); %INDEXED; %CMP8; return;
	473	case 0xA3: set_regop16(m_u); %INDEXED; %CMP16; return;
	474	case 0xA6: set_regop8(m_w.b.h); %INDEXED; %LD8; return;
	475	case 0xA7: set_regop8(m_w.b.h); %INDEXED; %ST8; return;
	476	case 0xAB: set_regop8(m_w.b.h); %INDEXED; %ADD8; return;
	477	case 0xAC: set_regop16(m_s); %INDEXED; %CMP16; return;
	478	case 0xAD: %INDEXED; %DIVD; return;
	479	case 0xAE: %INDEXED; %DIVQ; return;
	480	case 0xAF: %INDEXED; %MULD; return;
	481
	482	case 0xB0: set_regop8(m_w.b.h); %EXTENDED; %SUB8; return;
	483	case 0xB1: set_regop8(m_w.b.h); %EXTENDED; %CMP8; return;
	484	case 0xB3: set_regop16(m_u); %EXTENDED; %CMP16; return;
	485	case 0xB6: set_regop8(m_w.b.h); %EXTENDED; %LD8; return;
	486	case 0xB7: set_regop8(m_w.b.h); %EXTENDED; %ST8; return;
	487	case 0xBB: set_regop8(m_w.b.h); %EXTENDED; %ADD8; return;
	488	case 0xBC: set_regop16(m_s); %EXTENDED; %CMP16; return;
	489	case 0xBD: %EXTENDED; %DIVD; return;
	490	case 0xBE: %EXTENDED; %DIVQ; return;
	491	case 0xBF: %EXTENDED; %MULD; return;
	492
	493	case 0xC0: set_regop8(m_w.b.l); set_imm(); %SUB8; return;
	494	case 0xC1: set_regop8(m_w.b.l); set_imm(); %CMP8; return;
	495	case 0xC6: set_regop8(m_w.b.l); set_imm(); %LD8; return;
	496	case 0xCB: set_regop8(m_w.b.l); set_imm(); %ADD8; return;
	497
	498	case 0xD0: set_regop8(m_w.b.l); %DIRECT; %SUB8; return;
	499	case 0xD1: set_regop8(m_w.b.l); %DIRECT; %CMP8; return;
	500	case 0xD6: set_regop8(m_w.b.l); %DIRECT; %LD8; return;
	501	case 0xD7: set_regop8(m_w.b.l); %DIRECT; %ST8; return;
	502	case 0xDB: set_regop8(m_w.b.l); %DIRECT; %ADD8; return;
	503
	504	case 0xE0: set_regop8(m_w.b.l); %INDEXED; %SUB8; return;
	505	case 0xE1: set_regop8(m_w.b.l); %INDEXED; %CMP8; return;
	506	case 0xE6: set_regop8(m_w.b.l); %INDEXED; %LD8; return;
	507	case 0xE7: set_regop8(m_w.b.l); %INDEXED; %ST8; return;
	508	case 0xEB: set_regop8(m_w.b.l); %INDEXED; %ADD8; return;
	509
	510	case 0xF0: set_regop8(m_w.b.l); %EXTENDED; %SUB8; return;
	511	case 0xF1: set_regop8(m_w.b.l); %EXTENDED; %CMP8; return;
	512	case 0xF6: set_regop8(m_w.b.l); %EXTENDED; %LD8; return;
	513	case 0xF7: set_regop8(m_w.b.l); %EXTENDED; %ST8; return;
	514	case 0xFB: set_regop8(m_w.b.l); %EXTENDED; %ADD8; return;
	515
	516	default: %ILLEGAL; return;
	517	}
	518	return;
	519
	520	#include "base6x09.ops"
	521
	522	PUSH_REGISTERS:
	523	if (m_temp.w & 0x80)
	524	{
	525	@write_memory(--regop16().w, m_pc.b.l);
	526	@write_memory(--regop16().w, m_pc.b.h);
	527	nop();
	528	}
	529	if (m_temp.w & 0x40)
	530	{
	531	@write_memory(--regop16().w, (&regop16() == &m_s) ? m_u.b.l : m_s.b.l);
	532	@write_memory(--regop16().w, (&regop16() == &m_s) ? m_u.b.h : m_s.b.h);
	533	nop();
	534	}
	535	if (m_temp.w & 0x20)
	536	{
	537	@write_memory(--regop16().w, m_y.b.l);
	538	@write_memory(--regop16().w, m_y.b.h);
	539	nop();
	540	}
	541	if (m_temp.w & 0x10)
	542	{
	543	@write_memory(--regop16().w, m_x.b.l);
	544	@write_memory(--regop16().w, m_x.b.h);
	545	nop();
	546	}
	547	if (m_temp.w & 0x08)
	548	{
	549	@write_memory(--regop16().w, m_dp);
	550	nop();
	551	}
	552	if (m_temp.w & 0x200)
	553	{
	554	@write_memory(--regop16().w, m_w.b.l);
	555	nop();
	556	}
	557	if (m_temp.w & 0x100)
	558	{
	559	@write_memory(--regop16().w, m_w.b.h);
	560	nop();
	561	}
	562	if (m_temp.w & 0x04)
	563	{
	564	@write_memory(--regop16().w, m_d.b.l);
	565	nop();
	566	}
	567	if (m_temp.w & 0x02)
	568	{
	569	@write_memory(--regop16().w, m_d.b.h);
	570	nop();
	571	}
	572	if (m_temp.w & 0x01)
	573	{
	574	@write_memory(--regop16().w, m_cc);
	575	nop();
	576	}
	577	return;
	578
	579	PULL_REGISTERS:
	580	if (m_temp.w & 0x01)
	581	{
	582	@m_cc = read_memory(regop16().w++);
	583	nop();
	584	}
	585	if (m_temp.w & 0x02)
	586	{
	587	@m_d.b.h = read_memory(regop16().w++);
	588	nop();
	589	}
	590	if (m_temp.w & 0x04)
	591	{
	592	@m_d.b.l = read_memory(regop16().w++);
	593	nop();
	594	}
	595	if (m_temp.w & 0x100)
	596	{
	597	@m_w.b.h = read_memory(regop16().w++);
	598	nop();
	599	}
	600	if (m_temp.w & 0x200)
	601	{
	602	@m_w.b.l = read_memory(regop16().w++);
	603	nop();
	604	}
	605	if (m_temp.w & 0x08)
	606	{
	607	@m_dp = read_memory(regop16().w++);
	608	nop();
	609	}
	610	if (m_temp.w & 0x10)
	611	{
	612	@m_x.b.h = read_memory(regop16().w++);
	613	@m_x.b.l = read_memory(regop16().w++);
	614	nop();
	615	}
	616	if (m_temp.w & 0x20)
	617	{
	618	@m_y.b.h = read_memory(regop16().w++);
	619	@m_y.b.l = read_memory(regop16().w++);
	620	nop();
	621	}
	622	if (m_temp.w & 0x40)
	623	{
	624	@(&regop16() == &m_s ? m_u : m_s).b.h = read_memory(regop16().w++);
	625	@(&regop16() == &m_s ? m_u : m_s).b.l = read_memory(regop16().w++);
	626	nop();
	627	}
	628	if (m_temp.w & 0x80)
	629	{
	630	@m_pc.b.h = read_memory(regop16().w++);
	631	@m_pc.b.l = read_memory(regop16().w++);
	632	nop();
	633	}
	634	@eat(1);
	635	return;
	636
	637	INDEXED:
	638	@m_opcode = read_opcode_arg();
	639	if (m_opcode & 0x80)
	640	{
	641	switch(m_opcode & 0x7F)
	642	{
	643	case 0x00: case 0x20: case 0x40: case 0x60:
	644	m_temp.w = ireg();
	645	ireg()++;
	646	eat((hd6309_native_mode() && !(m_opcode & 0x10)) ? 2 : 3);
	647	break;
	648
	649	case 0x01: case 0x21: case 0x41: case 0x61:
	650	case 0x11: case 0x31: case 0x51: case 0x71:
	651	m_temp.w = ireg();
	652	ireg() += 2;
	653	eat((hd6309_native_mode() && !(m_opcode & 0x10)) ? 3 : 4);
	654	break;
	655
	656	case 0x02: case 0x22: case 0x42: case 0x62:
	657	ireg()--;
	658	m_temp.w = ireg();
	659	eat((hd6309_native_mode() && !(m_opcode & 0x10)) ? 2 : 3);
	660	break;
	661
	662	case 0x03: case 0x23: case 0x43: case 0x63:
	663	case 0x13: case 0x33: case 0x53: case 0x73:
	664	ireg() -= 2;
	665	m_temp.w = ireg();
	666	eat((hd6309_native_mode() && !(m_opcode & 0x10)) ? 3 : 4);
	667	break;
	668
	669	case 0x04: case 0x24: case 0x44: case 0x64:
	670	case 0x14: case 0x34: case 0x54: case 0x74:
	671	m_temp.w = ireg();
	672	eat(1);
	673	break;
	674
	675	case 0x05: case 0x25: case 0x45: case 0x65:
	676	case 0x15: case 0x35: case 0x55: case 0x75:
	677	m_temp.w = ireg() + (INT8) m_d.b.l;
	678	eat(2);
	679	break;
	680
	681	case 0x06: case 0x26: case 0x46: case 0x66:
	682	case 0x16: case 0x36: case 0x56: case 0x76:
	683	m_temp.w = ireg() + (INT8) m_d.b.h;
	684	eat(2);
	685	break;
	686
	687	case 0x08: case 0x28: case 0x48: case 0x68:
	688	case 0x18: case 0x38: case 0x58: case 0x78:
	689	@m_temp.w = ireg() + (INT8) read_opcode_arg();
	690	eat(1);
	691	break;
	692
	693	case 0x09: case 0x29: case 0x49: case 0x69:
	694	case 0x19: case 0x39: case 0x59: case 0x79:
	695	@m_temp.b.h = read_opcode_arg();
	696	@m_temp.b.l = read_opcode_arg();
	697	m_temp.w = ireg() + m_temp.w;
	698	eat(hd6309_native_mode() ? 2 : 3);
	699	break;
	700
	701	case 0x0B: case 0x2B: case 0x4B: case 0x6B:
	702	case 0x1B: case 0x3B: case 0x5B: case 0x7B:
	703	m_temp.w = ireg() + m_d.w;
	704	eat((hd6309_native_mode() && !(m_opcode & 0x10)) ? 3 : 5);
	705	break;
	706
	707	case 0x0C: case 0x2C: case 0x4C: case 0x6C:
	708	case 0x1C: case 0x3C: case 0x5C: case 0x7C:
	709	@m_temp.b.l = read_opcode_arg();
	710	m_temp.w = m_pc.w + (INT8) m_temp.b.l;
	711	eat(1);
	712	break;
	713
	714	case 0x0D: case 0x2D: case 0x4D: case 0x6D:
	715	case 0x1D: case 0x3D: case 0x5D: case 0x7D:
	716	@m_temp.b.h = read_opcode_arg();
	717	@m_temp.b.l = read_opcode_arg();
	718	m_temp.w = m_pc.w + (INT16) m_temp.w;
	719	eat((hd6309_native_mode() && !(m_opcode & 0x10)) ? 2 : 4);
	720	break;
	721
	722	case 0x1F: case 0x3F: case 0x5F: case 0x7F:
	723	@m_temp.b.h = read_opcode_arg();
	724	@m_temp.b.l = read_opcode_arg();
	725	eat(1);
	726	break;
	727
	728	case 0x07: case 0x27: case 0x47: case 0x67:
	729	case 0x17: case 0x37: case 0x57: case 0x77:
	730	// 6309 specific mode
	731	m_temp.w = ireg() + (INT8) m_w.b.h;
	732	eat(2);
	733	break;
	734
	735	case 0x0A: case 0x2A: case 0x4A: case 0x6A:
	736	case 0x1A: case 0x3A: case 0x5A: case 0x7A:
	737	// 6309 specific mode
	738	m_temp.w = ireg() + (INT8) m_w.b.l;
	739	eat(2);
	740	break;
	741
	742	case 0x0E: case 0x2E: case 0x4E: case 0x6E:
	743	case 0x1E: case 0x3E: case 0x5E: case 0x7E:
	744	// 6309 specific mode
	745	m_temp.w = ireg() + m_w.w;
	746	eat((hd6309_native_mode() && !(m_opcode & 0x10)) ? 2 : 5);
	747	break;
	748
	749	case 0x0F:
	750	// 6309 specific mode
	751	m_temp.w = m_w.w;
	752	eat(1);
	753	break;
	754
	755	case 0x2F:
	756	// 6309 specific mode
	757	@m_temp.b.h = read_opcode_arg();
	758	@m_temp.b.l = read_opcode_arg();
	759	m_temp.w = m_w.w + m_temp.w;
	760	eat(hd6309_native_mode() ? 1 : 5);
	761	break;
	762
	763	case 0x4F:
	764	// 6309 specific mode
	765	m_temp.w = m_w.w;
	766	m_w.w += 2;
	767	eat((hd6309_native_mode() && !(m_opcode & 0x10)) ? 2 : 4);
	768	break;
	769
	770	case 0x6F:
	771	// 6309 specific mode
	772	m_w.w -= 2;
	773	m_temp.w = m_w.w;
	774	eat((hd6309_native_mode() && !(m_opcode & 0x10)) ? 2 : 4);
	775	break;
	776
	777	default:
	778	goto ILLEGAL;
	779	}
	780
	781	// indirect mode
	782	if (m_opcode & 0x10)
	783	{
	784	set_ea(m_temp.w);
	785	@m_temp.b.h = read_operand(0);
	786	@m_temp.b.l = read_operand(1);
	787	eat(1);
	788	}
	789	}
	790	else
	791	{
	792	// 5-bit offset
	793	m_temp.w = ireg() + (INT8) ((m_opcode & 0x0F) \| (m_opcode & 0x10 ? 0xF0 : 0x00));
	794	eat(2);
	795	}
	796	@set_ea(m_temp.w);
	797	return;
	798
	799	ILLEGAL:
	800	m_md \|= 0x40; // illegal op flag
	801	set_ea(VECTOR_ILLEGAL);
	802	goto SOFTWARE_INTERRUPT;
	803
	804	DIVIDE_BY_ZERO:
	805	m_md \|= 0x80; // divide by zero flag
	806	set_ea(VECTOR_ILLEGAL);
	807	goto SOFTWARE_INTERRUPT;
	808
	809	IMM_IM:
	810	@m_temp_im = read_opcode_arg();
	811	return;
	812
	813	JSR_ind:
	814	// this is dubious, but the old core did this
	815	eat(hd6309_native_mode() ? -1 : 0);
	816	goto JSR;
	817
	818	LDQ:
	819	@m_d.b.h = read_operand(0);
	820	@m_d.b.l = read_operand(1);
	821	@m_w.b.h = read_operand(2);
	822	@m_w.b.l = read_operand(3);
	823	set_flags<UINT32>(CC_NZV, get_q());
	824	return;
	825
	826	STQ:
	827	@write_operand(0, m_d.b.h);
	828	@write_operand(1, m_d.b.l);
	829	@write_operand(2, m_w.b.h);
	830	@write_operand(3, m_w.b.l);
	831	set_flags<UINT32>(CC_NZV, get_q());
	832	return;
	833
	834	OIM:
	835	@m_temp.b.l = read_operand();
	836	m_cc &= ~CC_V;
	837	m_temp.b.l = set_flags(CC_NZ, (UINT8)0, m_temp.b.l, m_temp.b.l \| m_temp_im);
	838	@eat(1); // this is just a guess
	839	@write_operand(m_temp.b.l);
	840	return;
	841
	842	AIM:
	843	@m_temp.b.l = read_operand();
	844	m_cc &= ~CC_V;
	845	m_temp.b.l = set_flags(CC_NZ, (UINT8)0, m_temp.b.l, m_temp.b.l & m_temp_im);
	846	@eat(1); // this is just a guess
	847	@write_operand(m_temp.b.l);
	848	return;
	849
	850	EIM:
	851	@m_temp.b.l = read_operand();
	852	m_cc &= ~CC_V;
	853	m_temp.b.l = set_flags(CC_NZ, (UINT8)0, m_temp.b.l, m_temp.b.l ^ m_temp_im);
	854	@eat(1); // this is just a guess
	855	@write_operand(m_temp.b.l);
	856	return;
	857
	858	TIM:
	859	@m_temp.b.l = read_operand();
	860	m_cc &= ~CC_V;
	861	m_temp.b.l = set_flags(CC_NZ, (UINT8)0, m_temp.b.l, m_temp.b.l & m_temp_im);
	862	@eat(2); // this is just a guess
	863	return;
	864
	865	TFM:
	866	// The TFM instruction takes up 6 CPU cycles, plus 3 CPU cycles
	867	// for each byte transferred. At least three of these are spent
	868	// reading the opcodes (00010001 001110xx xxxxxxxx).
	869	//
	870	// The old (pre-0.149) core allowed interrupts to interrupt
	871	// execution of the transfer by implementing a transfer as an
	872	// operation that executed one transfer, and bumped the program
	873	// counter back. However, some documentation suggests that TFM
	874	// was abortable, so we now have a get_pending_interrupt() call
	875	// here.
	876	//
	877	// Lastly, I have no information on the precise sub-instruction timing
	878	// here; the timings of the reads and writes are really just a guess.
	879	@m_temp.b.l = read_opcode_arg();
	880
	881	while (m_w.w != 0x0000)
	882	{
	883	// TFM is abortable - we need to check for a pending interrupt
	884	if (get_pending_interrupt() != 0)
	885	{
	886	m_pc.w -= 3;
	887	return;
	888	}
	889
	890	if (!tfr_read(m_opcode, m_temp.b.l, m_temp.b.h))
	891	goto ILLEGAL;
	892	@eat(0);
	893
	894	if (!tfr_write(m_opcode, m_temp.b.l, m_temp.b.h))
	895	goto ILLEGAL;
	896	@eat(1);
	897
	898	m_w.w--;
	899	}
	900
	901	// Not sure if this sub instruction timing is accurate either
	902	@eat(3);
	903	return;
	904
	905	COM16:
	906	m_temp.b.h = read_operand(0);
	907	m_temp.b.l = read_operand(1);
	908	m_cc &= ~CC_V;
	909	m_cc \|= CC_C;
	910	m_temp.w = set_flags(CC_NZ, (UINT16) ~m_temp.w);
	911	eat(hd6309_native_mode() ? 0 : 1);
	912	write_operand(0, m_temp.b.h);
	913	write_operand(1, m_temp.b.l);
	914	return;
	915
	916	ADC16:
	917	@m_temp.b.h = read_operand(0);
	918	@m_temp.b.l = read_operand(1);
	919	regop16().w = set_flags(CC_NZVC, regop16().w, m_temp.w, regop16().w + m_temp.w + (m_cc & CC_C ? 1 : 0));
	920	eat(hd6309_native_mode() ? 0 : 1);
	921	return;
	922
	923	SBC16:
	924	@m_temp.b.h = read_operand(0);
	925	@m_temp.b.l = read_operand(1);
	926	regop16().w = set_flags(CC_NZVC, regop16().w, m_temp.w, regop16().w - m_temp.w - (m_cc & CC_C ? 1 : 0));
	927	eat(hd6309_native_mode() ? 0 : 1);
	928	return;
	929
	930	AND16:
	931	@m_temp.b.h = read_operand(0);
	932	@m_temp.b.l = read_operand(1);
	933	m_cc &= ~CC_V;
	934	regop16().w = set_flags(CC_NZ, (UINT16)0, regop16().w, regop16().w & m_temp.w);
	935	return;
	936
	937	BIT16:
	938	@m_temp.b.h = read_operand(0);
	939	@m_temp.b.l = read_operand(1);
	940	m_cc &= ~CC_V;
	941	set_flags(CC_NZ, (UINT16)0, regop16().w, regop16().w & m_temp.w);
	942	return;
	943
	944	OR16:
	945	@m_temp.b.h = read_operand(0);
	946	@m_temp.b.l = read_operand(1);
	947	m_cc &= ~CC_V;
	948	regop16().w = set_flags(CC_NZ, (UINT16)0, regop16().w, regop16().w \| m_temp.w);
	949	return;
	950
	951	EOR16:
	952	@m_temp.b.h = read_operand(0);
	953	@m_temp.b.l = read_operand(1);
	954	m_cc &= ~CC_V;
	955	regop16().w = set_flags(CC_NZ, (UINT16)0, regop16().w, regop16().w ^ m_temp.w);
	956	return;
	957
	958	PSHSW:
	959	m_temp.w = 0x300; // PSHS W
	960	eat(2);
	961	set_regop16(m_s);
	962	goto PUSH_REGISTERS;
	963
	964	PULSW:
	965	m_temp.w = 0x300; // PULS W
	966	eat(2);
	967	set_regop16(m_s);
	968	goto PULL_REGISTERS;
	969
	970	PSHUW:
	971	m_temp.w = 0x300; // PSHU W
	972	eat(2);
	973	set_regop16(m_u);
	974	goto PUSH_REGISTERS;
	975
	976	PULUW:
	977	m_temp.w = 0x300; // PULU W
	978	eat(2);
	979	set_regop16(m_u);
	980	goto PULL_REGISTERS;
	981
	982	BAND:
	983	%IMM_IM;
	984	%DIRECT;
	985	@m_temp.b.l = read_operand();
	986	bittest_set(bittest_dest() && bittest_source());
	987	return;
	988
	989	BIAND:
	990	%IMM_IM;
	991	%DIRECT;
	992	@m_temp.b.l = read_operand();
	993	bittest_set(bittest_dest() && !bittest_source());
	994	return;
	995
	996	BOR:
	997	%IMM_IM;
	998	%DIRECT;
	999	@m_temp.b.l = read_operand();
	1000	bittest_set(bittest_dest() \|\| bittest_source());
	1001	return;
	1002
	1003	BIOR:
	1004	%IMM_IM;
	1005	%DIRECT;
	1006	@m_temp.b.l = read_operand();
	1007	bittest_set(bittest_dest() \|\| !bittest_source());
	1008	return;
	1009
	1010	BEOR:
	1011	%IMM_IM;
	1012	%DIRECT;
	1013	@m_temp.b.l = read_operand();
	1014	bittest_set(bittest_dest() != bittest_source());
	1015	return;
	1016
	1017	BIEOR:
	1018	%IMM_IM;
	1019	%DIRECT;
	1020	@m_temp.b.l = read_operand();
	1021	bittest_set(bittest_dest() != !bittest_source());
	1022	return;
	1023
	1024	LDBT:
	1025	%IMM_IM;
	1026	%DIRECT;
	1027	@m_temp.b.l = read_operand();
	1028	bittest_set(bittest_source());
	1029	return;
	1030
	1031	STBT:
	1032	%IMM_IM;
	1033	%DIRECT;
	1034	@m_temp.b.l = read_operand();
	1035	if (bittest_source())
	1036	m_temp.b.l \|= (1 << ((m_temp_im >> 0) & 0x07));
	1037	else
	1038	m_temp.b.l &= ~(1 << ((m_temp_im >> 0) & 0x07));
	1039	@eat(2);
	1040	write_operand(m_temp.b.l);
	1041	return;
	1042
	1043	MULD:
	1044	@m_temp.b.h = read_operand(0);
	1045	@m_temp.b.l = read_operand(1);
	1046	muld();
	1047	{
	1048	PAIR result;
	1049	result.d = ((INT16) m_d.w) * ((INT16) m_temp.w);
	1050	m_d.w = set_flags<UINT16>(CC_NZ, result.w.h);
	1051	m_w.w = result.w.l;
	1052	m_cc &= ~CC_VC;
	1053	}
	1054	return;
	1055
	1056	DIVQ:
	1057	@m_temp.b.h = read_operand(0);
	1058	@m_temp.b.l = read_operand(1);
	1059	if (!divq())
	1060	goto DIVIDE_BY_ZERO;
	1061	return;
	1062
	1063	DIVD:
	1064	@m_temp.b.l = read_operand();
	1065	if (!divd())
	1066	goto DIVIDE_BY_ZERO;
	1067	return;
	1068
	1069	SEXW:
	1070	m_d.w = set_flags<UINT16>(CC_N, (m_w.w & 0x8000) ? 0xFFFF : 0x0000);
	1071	if ((m_d.w == 0x0000) && (m_w.w == 0x0000))
	1072	m_cc \|= CC_Z;
	1073	else
	1074	m_cc &= ~CC_Z;
	1075	return;

Property changes on: trunk/src/emu/cpu/m6809/hd6309.ops
Added: svn:mime-type + text/plain Added: svn:eol-style + native

trunk/src/emu/cpu/m6809/konami.ops
r0	r21565
	1	MAIN:
	2	// check interrupt lines
	3	switch(check_pending_interrupt())
	4	{
	5	case VECTOR_NMI: goto NMI;
	6	case VECTOR_FIRQ: goto FIRQ;
	7	case VECTOR_IRQ: goto IRQ;
	8	}
	9
	10	// debugger hook
	11	m_ppc = m_pc;
	12	debugger_instruction_hook(this, m_pc.w);
	13
	14	// opcode fetch
	15	@m_opcode = read_opcode();
	16
	17	// dispatch opcode
	18	switch(m_opcode)
	19	{
	20	case 0x08: set_regop16(m_x); %INDEXED; %LEA_xy; return;
	21	case 0x09: set_regop16(m_y); %INDEXED; %LEA_xy; return;
	22	case 0x0A: set_regop16(m_u); %INDEXED; %LEA_us; return;
	23	case 0x0B: set_regop16(m_s); %INDEXED; %LEA_us; return;
	24	case 0x0C: %PSHS; return;
	25	case 0x0D: %PSHU; return;
	26	case 0x0E: %PULS; return;
	27	case 0x0F: %PULU; return;
	28
	29	case 0x10: set_regop8(m_d.b.h); set_imm(); %LD8; return;
	30	case 0x11: set_regop8(m_d.b.l); set_imm(); %LD8; return;
	31	case 0x12: set_regop8(m_d.b.h); %INDEXED; %LD8; return;
	32	case 0x13: set_regop8(m_d.b.l); %INDEXED; %LD8; return;
	33	case 0x14: set_regop8(m_d.b.h); set_imm(); %ADD8; return;
	34	case 0x15: set_regop8(m_d.b.l); set_imm(); %ADD8; return;
	35	case 0x16: set_regop8(m_d.b.h); %INDEXED; %ADD8; return;
	36	case 0x17: set_regop8(m_d.b.l); %INDEXED; %ADD8; return;
	37	case 0x18: set_regop8(m_d.b.h); set_imm(); %ADC8; return;
	38	case 0x19: set_regop8(m_d.b.l); set_imm(); %ADC8; return;
	39	case 0x1A: set_regop8(m_d.b.h); %INDEXED; %ADC8; return;
	40	case 0x1B: set_regop8(m_d.b.l); %INDEXED; %ADC8; return;
	41	case 0x1C: set_regop8(m_d.b.h); set_imm(); %SUB8; return;
	42	case 0x1D: set_regop8(m_d.b.l); set_imm(); %SUB8; return;
	43	case 0x1E: set_regop8(m_d.b.h); %INDEXED; %SUB8; return;
	44	case 0x1F: set_regop8(m_d.b.l); %INDEXED; %SUB8; return;
	45
	46	case 0x20: set_regop8(m_d.b.h); set_imm(); %SBC8; return;
	47	case 0x21: set_regop8(m_d.b.l); set_imm(); %SBC8; return;
	48	case 0x22: set_regop8(m_d.b.h); %INDEXED; %SBC8; return;
	49	case 0x23: set_regop8(m_d.b.l); %INDEXED; %SBC8; return;
	50	case 0x24: set_regop8(m_d.b.h); set_imm(); %AND8; return;
	51	case 0x25: set_regop8(m_d.b.l); set_imm(); %AND8; return;
	52	case 0x26: set_regop8(m_d.b.h); %INDEXED; %AND8; return;
	53	case 0x27: set_regop8(m_d.b.l); %INDEXED; %AND8; return;
	54	case 0x28: set_regop8(m_d.b.h); set_imm(); %BIT8; return;
	55	case 0x29: set_regop8(m_d.b.l); set_imm(); %BIT8; return;
	56	case 0x2A: set_regop8(m_d.b.h); %INDEXED; %BIT8; return;
	57	case 0x2B: set_regop8(m_d.b.l); %INDEXED; %BIT8; return;
	58	case 0x2C: set_regop8(m_d.b.h); set_imm(); %EOR8; return;
	59	case 0x2D: set_regop8(m_d.b.l); set_imm(); %EOR8; return;
	60	case 0x2E: set_regop8(m_d.b.h); %INDEXED; %EOR8; return;
	61	case 0x2F: set_regop8(m_d.b.l); %INDEXED; %EOR8; return;
	62
	63	case 0x30: set_regop8(m_d.b.h); set_imm(); %OR8; return;
	64	case 0x31: set_regop8(m_d.b.l); set_imm(); %OR8; return;
	65	case 0x32: set_regop8(m_d.b.h); %INDEXED; %OR8; return;
	66	case 0x33: set_regop8(m_d.b.l); %INDEXED; %OR8; return;
	67	case 0x34: set_regop8(m_d.b.h); set_imm(); %CMP8; return;
	68	case 0x35: set_regop8(m_d.b.l); set_imm(); %CMP8; return;
	69	case 0x36: set_regop8(m_d.b.h); %INDEXED; %CMP8; return;
	70	case 0x37: set_regop8(m_d.b.l); %INDEXED; %CMP8; return;
	71	case 0x38: set_imm(); %SETLINE; return;
	72	case 0x39: %INDEXED; %SETLINE; return;
	73	case 0x3A: set_regop8(m_d.b.h); %INDEXED; %ST8; return;
	74	case 0x3B: set_regop8(m_d.b.l); %INDEXED; %ST8; return;
	75	case 0x3C: set_imm(); %ANDCC; return;
	76	case 0x3D: set_imm(); %ORCC; return;
	77	case 0x3E: %EXG; return;
	78	case 0x3F: %TFR; return;
	79
	80	case 0x40: set_regop16(m_d); set_imm(); %LD16; return;
	81	case 0x41: set_regop16(m_d); %INDEXED; %LD16; return;
	82	case 0x42: set_regop16(m_x); set_imm(); %LD16; return;
	83	case 0x43: set_regop16(m_x); %INDEXED; %LD16; return;
	84	case 0x44: set_regop16(m_y); set_imm(); %LD16; return;
	85	case 0x45: set_regop16(m_y); %INDEXED; %LD16; return;
	86	case 0x46: set_regop16(m_u); set_imm(); %LD16; return;
	87	case 0x47: set_regop16(m_u); %INDEXED; %LD16; return;
	88	case 0x48: set_regop16(m_s); set_imm(); %LD16; return;
	89	case 0x49: set_regop16(m_s); %INDEXED; %LD16; return;
	90	case 0x4A: set_regop16(m_d); set_imm(); %CMP16; return;
	91	case 0x4B: set_regop16(m_d); %INDEXED; %CMP16; return;
	92	case 0x4C: set_regop16(m_x); set_imm(); %CMP16; return;
	93	case 0x4D: set_regop16(m_x); %INDEXED; %CMP16; return;
	94	case 0x4E: set_regop16(m_y); set_imm(); %CMP16; return;
	95	case 0x4F: set_regop16(m_y); %INDEXED; %CMP16; return;
	96
	97	case 0x50: set_regop16(m_u); set_imm(); %CMP16; return;
	98	case 0x51: set_regop16(m_u); %INDEXED; %CMP16; return;
	99	case 0x52: set_regop16(m_s); set_imm(); %CMP16; return;
	100	case 0x53: set_regop16(m_s); %INDEXED; %CMP16; return;
	101	case 0x54: set_regop16(m_d); set_imm(); %ADD16; return;
	102	case 0x55: set_regop16(m_d); %INDEXED; %ADD16; return;
	103	case 0x56: set_regop16(m_d); set_imm(); %SUB16; return;
	104	case 0x57: set_regop16(m_d); %INDEXED; %SUB16; return;
	105	case 0x58: set_regop16(m_d); %INDEXED; %ST16; return;
	106	case 0x59: set_regop16(m_x); %INDEXED; %ST16; return;
	107	case 0x5A: set_regop16(m_y); %INDEXED; %ST16; return;
	108	case 0x5B: set_regop16(m_u); %INDEXED; %ST16; return;
	109	case 0x5C: set_regop16(m_s); %INDEXED; %ST16; return;
	110
	111	case 0x60: set_cond(true); %BRANCH; return;
	112	case 0x61: set_cond(cond_hi()); %BRANCH; return;
	113	case 0x62: set_cond(cond_cc()); %BRANCH; return;
	114	case 0x63: set_cond(cond_ne()); %BRANCH; return;
	115	case 0x64: set_cond(cond_vc()); %BRANCH; return;
	116	case 0x65: set_cond(cond_pl()); %BRANCH; return;
	117	case 0x66: set_cond(cond_ge()); %BRANCH; return;
	118	case 0x67: set_cond(cond_gt()); %BRANCH; return;
	119	case 0x68: set_cond(true); %LBRANCH; return;
	120	case 0x69: set_cond(cond_hi()); %LBRANCH; return;
	121	case 0x6A: set_cond(cond_cc()); %LBRANCH; return;
	122	case 0x6B: set_cond(cond_ne()); %LBRANCH; return;
	123	case 0x6C: set_cond(cond_vc()); %LBRANCH; return;
	124	case 0x6D: set_cond(cond_pl()); %LBRANCH; return;
	125	case 0x6E: set_cond(cond_ge()); %LBRANCH; return;
	126	case 0x6F: set_cond(cond_gt()); %LBRANCH; return;
	127
	128	case 0x70: set_cond(false); %BRANCH; return;
	129	case 0x71: set_cond(!cond_hi()); %BRANCH; return;
	130	case 0x72: set_cond(!cond_cc()); %BRANCH; return;
	131	case 0x73: set_cond(!cond_ne()); %BRANCH; return;
	132	case 0x74: set_cond(!cond_vc()); %BRANCH; return;
	133	case 0x75: set_cond(!cond_pl()); %BRANCH; return;
	134	case 0x76: set_cond(!cond_ge()); %BRANCH; return;
	135	case 0x77: set_cond(!cond_gt()); %BRANCH; return;
	136	case 0x78: set_cond(false); %LBRANCH; return;
	137	case 0x79: set_cond(!cond_hi()); %LBRANCH; return;
	138	case 0x7A: set_cond(!cond_cc()); %LBRANCH; return;
	139	case 0x7B: set_cond(!cond_ne()); %LBRANCH; return;
	140	case 0x7C: set_cond(!cond_vc()); %LBRANCH; return;
	141	case 0x7D: set_cond(!cond_pl()); %LBRANCH; return;
	142	case 0x7E: set_cond(!cond_ge()); %LBRANCH; return;
	143	case 0x7F: set_cond(!cond_gt()); %LBRANCH; return;
	144
	145	case 0x80: set_a(); %CLR8; return;
	146	case 0x81: set_b(); %CLR8; return;
	147	case 0x82: %INDEXED; %CLR8; return;
	148	case 0x83: set_a(); %COM8; return;
	149	case 0x84: set_b(); %COM8; return;
	150	case 0x85: %INDEXED; %COM8; return;
	151	case 0x86: set_a(); %NEG8; return;
	152	case 0x87: set_b(); %NEG8; return;
	153	case 0x88: %INDEXED; %NEG8; return;
	154	case 0x89: set_a(); %INC8; return;
	155	case 0x8A: set_b(); %INC8; return;
	156	case 0x8B: %INDEXED; %INC8; return;
	157	case 0x8C: set_a(); %DEC8; return;
	158	case 0x8D: set_b(); %DEC8; return;
	159	case 0x8E: %INDEXED; %DEC8; return;
	160	case 0x8F: %RTS; return;
	161
	162	case 0x90: set_a(); %TST8; return;
	163	case 0x91: set_b(); %TST8; return;
	164	case 0x92: %INDEXED; %TST8; return;
	165	case 0x93: set_a(); %LSR8; return;
	166	case 0x94: set_b(); %LSR8; return;
	167	case 0x95: %INDEXED; %LSR8; return;
	168	case 0x96: set_a(); %ROR8; return;
	169	case 0x97: set_b(); %ROR8; return;
	170	case 0x98: %INDEXED; %ROR8; return;
	171	case 0x99: set_a(); %ASR8; return;
	172	case 0x9A: set_b(); %ASR8; return;
	173	case 0x9B: %INDEXED; %ASR8; return;
	174	case 0x9C: set_a(); %ASL8; return;
	175	case 0x9D: set_b(); %ASL8; return;
	176	case 0x9E: %INDEXED; %ASL8; return;
	177	case 0x9F: %RTI; return;
	178
	179	case 0xA0: set_a(); %ROL8; return;
	180	case 0xA1: set_b(); %ROL8; return;
	181	case 0xA2: %INDEXED; %ROL8; return;
	182	case 0xA3: %INDEXED; %LSR16; return;
	183	case 0xA4: %INDEXED; %ROR16; return;
	184	case 0xA5: %INDEXED; %ASR16; return;
	185	case 0xA6: %INDEXED; %ASL16; return;
	186	case 0xA7: %INDEXED; %ROL16; return;
	187	case 0xA8: %INDEXED; %JMP; return;
	188	case 0xA9: %INDEXED; %JSR; return;
	189	case 0xAA: %BSR; return;
	190	case 0xAB: %LBSR; return;
	191	case 0xAC: %DECBJNZ; return;
	192	case 0xAD: %DECXJNZ; return;
	193	case 0xAE: %NOP; return;
	194
	195	case 0xB0: %ABX; return;
	196	case 0xB1: %DAA; return;
	197	case 0xB2: %SEX; return;
	198	case 0xB3: %MUL; return;
	199	case 0xB4: %LMUL; return;
	200	case 0xB5: %DIVX; return;
	201	case 0xB6: %BMOVE; return;
	202	case 0xB7: %MOVE; return;
	203	case 0xB8: %LSRD; return;
	204	case 0xB9: %INDEXED; %LSRD; return;
	205	case 0xBA: %RORD; return;
	206	case 0xBB: %INDEXED; %RORD; return;
	207	case 0xBC: %ASRD; return;
	208	case 0xBD: %INDEXED; %ASRD; return;
	209	case 0xBE: %ASLD; return;
	210	case 0xBF: %INDEXED; %ASLD; return;
	211
	212	case 0xC0: %ROLD; return;
	213	case 0xC2: set_d(); %CLR16; return;
	214	case 0xC4: set_d(); %NEG16; return;
	215	case 0xC6: set_d(); %INC16; return;
	216	case 0xC8: set_d(); %DEC16; return;
	217	case 0xCA: set_d(); %TST16; return;
	218	case 0xCC: set_a(); %ABS8; return;
	219	case 0xCD: set_b(); %ABS8; return;
	220	case 0xCE: set_d(); %ABS16; return;
	221	case 0xCF: %BSET; return;
	222
	223	case 0xD0: %BSET2; return;
	224	default: %ILLEGAL; return;
	225	}
	226	return;
	227
	228	#include "base6x09.ops"
	229
	230	PUSH_REGISTERS:
	231	if (m_temp.w & 0x80)
	232	{
	233	@write_memory(--regop16().w, m_pc.b.l);
	234	@write_memory(--regop16().w, m_pc.b.h);
	235	nop();
	236	}
	237	if (m_temp.w & 0x40)
	238	{
	239	@write_memory(--regop16().w, (&regop16() == &m_s) ? m_u.b.l : m_s.b.l);
	240	@write_memory(--regop16().w, (&regop16() == &m_s) ? m_u.b.h : m_s.b.h);
	241	nop();
	242	}
	243	if (m_temp.w & 0x20)
	244	{
	245	@write_memory(--regop16().w, m_y.b.l);
	246	@write_memory(--regop16().w, m_y.b.h);
	247	nop();
	248	}
	249	if (m_temp.w & 0x10)
	250	{
	251	@write_memory(--regop16().w, m_x.b.l);
	252	@write_memory(--regop16().w, m_x.b.h);
	253	nop();
	254	}
	255	if (m_temp.w & 0x08)
	256	{
	257	@write_memory(--regop16().w, m_dp);
	258	nop();
	259	}
	260	if (m_temp.w & 0x04)
	261	{
	262	@write_memory(--regop16().w, m_d.b.l);
	263	nop();
	264	}
	265	if (m_temp.w & 0x02)
	266	{
	267	@write_memory(--regop16().w, m_d.b.h);
	268	nop();
	269	}
	270	if (m_temp.w & 0x01)
	271	{
	272	@write_memory(--regop16().w, m_cc);
	273	nop();
	274	}
	275	return;
	276
	277	PULL_REGISTERS:
	278	if (m_temp.w & 0x01)
	279	{
	280	@m_cc = read_memory(regop16().w++);
	281	nop();
	282	}
	283	if (m_temp.w & 0x02)
	284	{
	285	@m_d.b.h = read_memory(regop16().w++);
	286	nop();
	287	}
	288	if (m_temp.w & 0x04)
	289	{
	290	@m_d.b.l = read_memory(regop16().w++);
	291	nop();
	292	}
	293	if (m_temp.w & 0x08)
	294	{
	295	@m_dp = read_memory(regop16().w++);
	296	nop();
	297	}
	298	if (m_temp.w & 0x10)
	299	{
	300	@m_x.b.h = read_memory(regop16().w++);
	301	@m_x.b.l = read_memory(regop16().w++);
	302	nop();
	303	}
	304	if (m_temp.w & 0x20)
	305	{
	306	@m_y.b.h = read_memory(regop16().w++);
	307	@m_y.b.l = read_memory(regop16().w++);
	308	nop();
	309	}
	310	if (m_temp.w & 0x40)
	311	{
	312	@(&regop16() == &m_s ? m_u : m_s).b.h = read_memory(regop16().w++);
	313	@(&regop16() == &m_s ? m_u : m_s).b.l = read_memory(regop16().w++);
	314	nop();
	315	}
	316	if (m_temp.w & 0x80)
	317	{
	318	@m_pc.b.h = read_memory(regop16().w++);
	319	@m_pc.b.l = read_memory(regop16().w++);
	320	nop();
	321	}
	322	@eat(1);
	323	return;
	324
	325	INDEXED:
	326	@m_opcode = read_opcode_arg();
	327	switch(m_opcode & 0xF7)
	328	{
	329	case 0x07:
	330	// extended addressing mode
	331	@m_temp.b.h = read_opcode_arg();
	332	@m_temp.b.l = read_opcode_arg();
	333	break;
	334
	335	case 0x20: case 0x30: case 0x50: case 0x60: case 0x70:
	336	// auto increment
	337	m_temp.w = ireg();
	338	ireg()++;
	339	eat(2);
	340	break;
	341
	342	case 0x21: case 0x31: case 0x51: case 0x61: case 0x71:
	343	// double auto increment
	344	m_temp.w = ireg();
	345	ireg() += 2;
	346	eat(3);
	347	break;
	348
	349	case 0x22: case 0x32: case 0x52: case 0x62: case 0x72:
	350	// auto decrement
	351	ireg()--;
	352	m_temp.w = ireg();
	353	eat(2);
	354	break;
	355
	356	case 0x23: case 0x33: case 0x53: case 0x63: case 0x73:
	357	// double auto decrement
	358	ireg() -= 2;
	359	m_temp.w = ireg();
	360	eat(3);
	361	break;
	362
	363	case 0x24: case 0x34: case 0x54: case 0x64: case 0x74:
	364	// postbyte offset
	365	@m_temp.b.l = read_opcode_arg();
	366	m_temp.w = ireg() + (INT8) m_temp.b.l;
	367	eat(1);
	368	break;
	369
	370	case 0x25: case 0x35: case 0x55: case 0x65: case 0x75:
	371	// postword offset
	372	@m_temp.b.h = read_opcode_arg();
	373	@m_temp.b.l = read_opcode_arg();
	374	m_temp.w = ireg() + (INT16) m_temp.w;
	375	eat(2);
	376	break;
	377
	378	case 0x26: case 0x36: case 0x56: case 0x66: case 0x76:
	379	m_temp.w = ireg();
	380	break;
	381
	382	case 0xC4:
	383	// direct addressing mode
	384	m_temp.b.h = m_dp;
	385	@m_temp.b.l = read_opcode_arg();
	386	break;
	387
	388	case 0xA0: case 0xB0: case 0xD0: case 0xE0: case 0xF0:
	389	// relative to register A
	390	m_temp.w = ireg() + (INT8) m_d.b.h;
	391	@eat(1);
	392	break;
	393
	394	case 0xA1: case 0xB1: case 0xD1: case 0xE1: case 0xF1:
	395	// relative to register B
	396	m_temp.w = ireg() + (INT8) m_d.b.l;
	397	@eat(1);
	398	break;
	399
	400	case 0xA7: case 0xB7: case 0xD7: case 0xE7: case 0xF7:
	401	// relative to register D
	402	m_temp.w = ireg() + (INT16) m_d.w;
	403	@eat(4);
	404	break;
	405
	406	default:
	407	logerror("KONAMI: Unknown/Invalid postbyte at PC = %04x\n", m_pc.w - 1);
	408	m_temp.w = 0;
	409	break;
	410	}
	411
	412	if (m_opcode & 0x08)
	413	{
	414	// indirect mode
	415	set_ea(m_temp.w);
	416	@m_temp.b.h = read_operand(0);
	417	@m_temp.b.l = read_operand(1);
	418	nop();
	419	}
	420
	421	set_ea(m_temp.w);
	422	return;
	423
	424	SETLINE:
	425	@set_lines(read_operand());
	426	return;
	427
	428	MOVE:
	429	@m_temp.b.l = read_memory(m_y.w++);
	430	@write_memory(m_x.w++, m_temp.b.l);
	431	m_u.w--;
	432	return;
	433
	434	BMOVE:
	435	// BMOVE does not appear to be interruptable, at least judging from the
	436	// old implementation
	437	while(m_u.w != 0)
	438	{
	439	@m_temp.b.l = read_memory(m_y.w++);
	440	@write_memory(m_x.w++, m_temp.b.l);
	441	m_u.w--;
	442	}
	443	return;
	444
	445	BSET:
	446	// BSET does not appear to be interruptable, at least judging from the
	447	// old implementation
	448	while(m_u.w != 0)
	449	{
	450	@eat(1);
	451	@write_memory(m_x.w++, m_d.b.h);
	452	m_u.w--;
	453	}
	454	return;
	455
	456	BSET2:
	457	// BSET2 does not appear to be interruptable, at least judging from the
	458	// old implementation
	459	while(m_u.w != 0)
	460	{
	461	@eat(1);
	462	@write_memory(m_x.w++, m_d.b.h);
	463	@write_memory(m_x.w++, m_d.b.l);
	464	m_u.w--;
	465	}
	466	return;
	467
	468	DECXJNZ:
	469	// not sure if this affects V?
	470	m_x.w = set_flags<UINT16>(CC_NZV, m_x.w, 1, m_x.w - 1);
	471	@eat(1);
	472	set_cond(cond_ne());
	473	goto BRANCH;
	474
	475	DECBJNZ:
	476	// not sure if this affects V?
	477	m_d.b.l = set_flags<UINT8>(CC_NZV, m_d.b.l, 1, m_d.b.l - 1);
	478	@eat(1);
	479	set_cond(cond_ne());
	480	goto BRANCH;
	481
	482	LSRD:
	483	@m_temp.b.l = read_operand();
	484	if (m_temp.b.l != 0x00)
	485	{
	486	// set C condition code
	487	if (m_d.w & safe_shift_left(1, m_temp.b.l))
	488	m_cc \|= CC_C;
	489	else
	490	m_cc &= ~CC_C;
	491
	492	m_d.w = set_flags<UINT16>(CC_NZ, safe_shift_right<UINT16>(m_d.w, m_temp.b.l));
	493	}
	494	eat(1);
	495	return;
	496
	497	ASLD:
	498	@m_temp.b.l = read_operand();
	499	if (m_temp.b.l != 0x00)
	500	{
	501	// set C condition code
	502	if (m_d.w & safe_shift_right(0x10000, m_temp.b.l))
	503	m_cc \|= CC_C;
	504	else
	505	m_cc &= ~CC_C;
	506
	507	m_d.w = set_flags<UINT16>(CC_NZV, safe_shift_left<INT16>(m_d.w, m_temp.b.l));
	508	}
	509	eat(1);
	510	return;
	511
	512	ASRD:
	513	@m_temp.b.l = read_operand();
	514	if (m_temp.b.l != 0x00)
	515	{
	516	// set C condition code
	517	if (m_d.w & safe_shift_left(1, m_temp.b.l))
	518	m_cc \|= CC_C;
	519	else
	520	m_cc &= ~CC_C;
	521
	522	m_d.w = set_flags<UINT16>(CC_NZ, safe_shift_right<INT16>(m_d.w, m_temp.b.l));
	523	}
	524	eat(1);
	525	return;
	526
	527	ROLD:
	528	@m_temp.b.l = read_operand();
	529
	530	// doing this as a loop is lame
	531	while(m_temp.b.l--)
	532	m_temp.w = set_flags<UINT16>(CC_NZ, rotate_left(m_temp.w));
	533
	534	eat(1);
	535	return;
	536
	537	RORD:
	538	@m_temp.b.l = read_operand();
	539
	540	// doing this as a loop is lame
	541	while(m_temp.b.l--)
	542	m_temp.w = set_flags<UINT16>(CC_NZ, rotate_right(m_temp.w));
	543
	544	eat(1);
	545	return;
	546
	547	ABS8:
	548	@m_temp.b.l = read_operand();
	549	m_temp.b.l = set_flags<UINT8>(CC_NZVC, 0, m_temp.b.l, ((INT8) m_temp.b.l) >= 0 ? m_temp.b.l : -m_temp.b.l);
	550	@eat(1);
	551	write_operand(m_temp.b.l);
	552	return;
	553
	554	ABS16:
	555	@m_temp.b.h = read_operand(0);
	556	@m_temp.b.l = read_operand(1);
	557	m_temp.w = set_flags<UINT16>(CC_NZVC, 0, m_temp.w, ((INT8) m_temp.w) >= 0 ? m_temp.w : -m_temp.w);
	558	@eat(1);
	559	@write_operand(0, m_temp.b.h);
	560	write_operand(1, m_temp.b.l);
	561	return;
	562
	563	LMUL:
	564	lmul();
	565	eat(21);
	566	return;
	567
	568	DIVX:
	569	divx();
	570	eat(10);
	571	return;
	572
	573	ILLEGAL:
	574	log_illegal();
	575	return;

Property changes on: trunk/src/emu/cpu/m6809/konami.ops
Added: svn:eol-style + native Added: svn:mime-type + text/plain

trunk/src/emu/cpu/m6809/hd6309.c
r0	r21565
	1	/*********************************************************************
	2
	3	hd6309.c
	4
	5	Copyright John Butler
	6	Copyright Tim Lindner
	7
	8	References:
	9
	10	HD63B09EP Technical Reference Guide, by Chet Simpson with addition
	11	by Alan Dekok
	12	6809 Simulator V09, By L.C. Benschop, Eidnhoven The Netherlands.
	13
	14	m6809: Portable 6809 emulator, DS (6809 code in MAME, derived from
	15	the 6809 Simulator V09)
	16
	17	6809 Microcomputer Programming & Interfacing with Experiments"
	18	by Andrew C. Staugaard, Jr.; Howard W. Sams & Co., Inc.
	19
	20	System dependencies: UINT16 must be 16 bit unsigned int
	21	UINT8 must be 8 bit unsigned int
	22	UINT32 must be more than 16 bits
	23	arrays up to 65536 bytes must be supported
	24	machine must be twos complement
	25
	26	History:
	27
	28	March 2013 NPW:
	29	Rewrite of 6809/6309/Konami CPU; attempted to make cycle exact.
	30
	31	070614 ZV:
	32	Fixed N flag setting in DIV overflow
	33
	34	991026 HJB:
	35	Fixed missing calls to cpu_changepc() for the TFR and EXG ocpodes.
	36	Replaced m6809_slapstic checks by a macro (CHANGE_PC). ESB still
	37	needs the tweaks.
	38
	39	991024 HJB:
	40	Tried to improve speed: Using bit7 of cycles1/2 as flag for multi
	41	byte opcodes is gone, those opcodes now call fetch_effective_address().
	42	Got rid of the slow/fast flags for stack (S and U) memory accesses.
	43	Minor changes to use 32 bit values as arguments to memory functions
	44	and added defines for that purpose (e.g. X = 16bit XD = 32bit).
	45
	46	990312 HJB:
	47	Added bugfixes according to Aaron's findings.
	48	Reset only sets CC_II and CC_IF, DP to zero and PC from reset vector.
	49	990311 HJB:
	50	Added _info functions. Now uses static m6808_Regs struct instead
	51	of single statics. Changed the 16 bit registers to use the generic
	52	PAIR union. Registers defined using macros. Split the core into
	53	four execution loops for M6802, M6803, M6808 and HD63701.
	54	TST, TSTA and TSTB opcodes reset carry flag.
	55	Modified the read/write stack handlers to push LSB first then MSB
	56	and pull MSB first then LSB.
	57
	58	990228 HJB:
	59	Changed the interrupt handling again. Now interrupts are taken
	60	either right at the moment the lines are asserted or whenever
	61	an interrupt is enabled and the corresponding line is still
	62	asserted. That way the pending_interrupts checks are not
	63	needed anymore. However, the CWAI and SYNC flags still need
	64	some flags, so I changed the name to 'int_state'.
	65	This core also has the code for the old interrupt system removed.
	66
	67	990225 HJB:
	68	Cleaned up the code here and there, added some comments.
	69	Slightly changed the SAR opcodes (similiar to other CPU cores).
	70	Added symbolic names for the flag bits.
	71	Changed the way CWAI/Interrupt() handle CPU state saving.
	72	A new flag M6809_STATE in pending_interrupts is used to determine
	73	if a state save is needed on interrupt entry or already done by CWAI.
	74	Added M6809_IRQ_LINE and M6809_FIRQ_LINE defines to m6809.h
	75	Moved the internal interrupt_pending flags from m6809.h to m6809.c
	76	Changed CWAI cycles2[0x3c] to be 2 (plus all or at least 19 if
	77	CWAI actually pushes the entire state).
	78	Implemented undocumented TFR/EXG for undefined source and mixed 8/16
	79	bit transfers (they should transfer/exchange the constant $ff).
	80	Removed unused jmp/jsr _slap functions from 6809ops.c,
	81	m6809_slapstick check moved into the opcode functions.
	82
	83	000809 TJL:
	84	Started converting m6809 into hd6309
	85
	86	001217 TJL:
	87	Finished:
	88	All opcodes
	89	Dual Timing
	90	To Do:
	91	Verify new DIV opcodes.
	92
	93	070805 TJL:
	94	Fixed ADDR and ADCR opcodes not to clear the H condition code. Fixed ANDR,
	95	EORR, ORR, ADDR, ADCR, SBCR, and SUBR to evaluate condition codes after
	96	the destination register was set. Fixed BITMD opcode to only effect the Z
	97	condition code. Fixed BITMD opcode to clear only tested flags. Fixed EXG
	98	and TFR register promotion and demotion. Fixed illegal instruction handler
	99	to not set I and F condition codes. Credit to Darren Atkinson for the
	100	discovery of these bugs.
	101
	102	090907 TJL:
	103	The SEXW instruction is clearing the Overflow flag (V). It should not do
	104	that. When an invalid source or destination register is specified for
	105	the TFM instructions, real hardware invokes the Illegal Instruction
	106	trap, whereas the emulator simply ignores the instruction. Credit to
	107	Darren Atkinson for the discovery of these bugs.
	108
	109	*****************************************************************************/
	110
	111	#include "emu.h"
	112	#include "debugger.h"
	113	#include "hd6309.h"
	114	#include "m6809inl.h"
	115
	116
	117	//**************************************************************************
	118	// DEVICE INTERFACE
	119	//**************************************************************************
	120
	121	const device_type HD6309 = &device_creator<hd6309_device>;
	122
	123
	124	//-------------------------------------------------
	125	// hd6309_device - constructor
	126	//-------------------------------------------------
	127
	128	hd6309_device::hd6309_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
	129	: m6809_base_device(mconfig, "HD6309", tag, owner, clock, HD6309, 4)
	130	{
	131	}
	132
	133
	134	//-------------------------------------------------
	135	// device_start - device-specific startup
	136	//-------------------------------------------------
	137
	138	void hd6309_device::device_start()
	139	{
	140	super::device_start();
	141
	142	// register our state for the debugger
	143	state_add(HD6309_E, "E", m_w.b.h).mask(0xff);
	144	state_add(HD6309_F, "F", m_w.b.l).mask(0xff);
	145	state_add(HD6309_W, "W", m_w.w).mask(0xffff);
	146	state_add(HD6309_V, "V", m_w.w).mask(0xffff);
	147	state_add(HD6309_MD, "MD", m_md).mask(0xff);
	148
	149	// initialize variables
	150	m_w.w = 0x0000;
	151	m_v.w = 0x0000;
	152	m_md = 0x00;
	153	m_temp_im = 0x00;
	154
	155	// setup regtable
	156	save_item(NAME(m_w.w));
	157	save_item(NAME(m_v.w));
	158	save_item(NAME(m_md));
	159	save_item(NAME(m_temp_im));
	160	}
	161
	162
	163
	164	//-------------------------------------------------
	165	// device_reset - device-specific reset
	166	//-------------------------------------------------
	167
	168	void hd6309_device::device_reset()
	169	{
	170	super::device_reset();
	171
	172	// initialize variables
	173	m_md = 0x00;
	174	}
	175
	176
	177
	178	//-------------------------------------------------
	179	// disasm_min_opcode_bytes - return the length
	180	// of the shortest instruction, in bytes
	181	//-------------------------------------------------
	182
	183	UINT32 hd6309_device::disasm_min_opcode_bytes() const
	184	{
	185	return 1;
	186	}
	187
	188
	189
	190	//-------------------------------------------------
	191	// disasm_max_opcode_bytes - return the length
	192	// of the longest instruction, in bytes
	193	//-------------------------------------------------
	194
	195	UINT32 hd6309_device::disasm_max_opcode_bytes() const
	196	{
	197	return 5;
	198	}
	199
	200
	201
	202	//-------------------------------------------------
	203	// disasm_disassemble - call the disassembly
	204	// helper function
	205	//-------------------------------------------------
	206
	207	offs_t hd6309_device::disasm_disassemble(char buffer, offs_t pc, const UINT8 oprom, const UINT8 *opram, UINT32 options)
	208	{
	209	extern offs_t hd6309_disassemble(char buffer, offs_t pc, const UINT8 oprom, const UINT8 *opram, UINT32 options);
	210	return hd6309_disassemble(buffer, pc, oprom, opram, options);
	211	}
	212
	213
	214
	215	//-------------------------------------------------
	216	// read_operand
	217	//-------------------------------------------------
	218
	219	ATTR_FORCE_INLINE UINT8 hd6309_device::read_operand()
	220	{
	221	switch(m_addressing_mode)
	222	{
	223	case ADDRESSING_MODE_EA: return read_memory(m_ea.w);
	224	case ADDRESSING_MODE_IMMEDIATE: return read_opcode_arg();
	225	case ADDRESSING_MODE_REGISTER_A: return m_d.b.h;
	226	case ADDRESSING_MODE_REGISTER_B: return m_d.b.l;
	227	case ADDRESSING_MODE_REGISTER_E: return m_w.b.h;
	228	case ADDRESSING_MODE_REGISTER_F: return m_w.b.l;
	229	default: fatalerror("Unexpected"); return 0x00;
	230	}
	231	}
	232
	233
	234	//-------------------------------------------------
	235	// read_operand
	236	//-------------------------------------------------
	237
	238	ATTR_FORCE_INLINE UINT8 hd6309_device::read_operand(int ordinal)
	239	{
	240	switch(m_addressing_mode)
	241	{
	242	case ADDRESSING_MODE_EA: return read_memory(m_ea.w + ordinal);
	243	case ADDRESSING_MODE_IMMEDIATE: return read_opcode_arg();
	244	case ADDRESSING_MODE_REGISTER_D: return (ordinal & 1) ? m_d.b.l : m_d.b.h;
	245	case ADDRESSING_MODE_REGISTER_W: return (ordinal & 1) ? m_w.b.l : m_w.b.h;
	246	case ADDRESSING_MODE_REGISTER_X: return (ordinal & 1) ? m_x.b.l : m_x.b.h;
	247	case ADDRESSING_MODE_REGISTER_Y: return (ordinal & 1) ? m_y.b.l : m_y.b.h;
	248	case ADDRESSING_MODE_REGISTER_U: return (ordinal & 1) ? m_u.b.l : m_u.b.h;
	249	case ADDRESSING_MODE_REGISTER_S: return (ordinal & 1) ? m_s.b.l : m_s.b.h;
	250	case ADDRESSING_MODE_REGISTER_V: return (ordinal & 1) ? m_v.b.l : m_v.b.h;
	251	case ADDRESSING_MODE_REGISTER_PC: return (ordinal & 1) ? m_pc.b.l : m_pc.b.h;
	252	case ADDRESSING_MODE_ZERO: return 0x00;
	253	default: fatalerror("Unexpected"); return 0x00;
	254	}
	255	}
	256
	257
	258	//-------------------------------------------------
	259	// write_operand
	260	//-------------------------------------------------
	261
	262	ATTR_FORCE_INLINE void hd6309_device::write_operand(UINT8 data)
	263	{
	264	switch(m_addressing_mode)
	265	{
	266	case ADDRESSING_MODE_EA: write_memory(m_ea.w, data); break;
	267	case ADDRESSING_MODE_REGISTER_A: m_d.b.h = data; break;
	268	case ADDRESSING_MODE_REGISTER_B: m_d.b.l = data; break;
	269	case ADDRESSING_MODE_REGISTER_E: m_w.b.h = data; break;
	270	case ADDRESSING_MODE_REGISTER_F: m_w.b.l = data; break;
	271	case ADDRESSING_MODE_ZERO: break;
	272	default: fatalerror("Unexpected"); break;
	273	}
	274	}
	275
	276
	277	//-------------------------------------------------
	278	// write_operand
	279	//-------------------------------------------------
	280
	281	ATTR_FORCE_INLINE void hd6309_device::write_operand(int ordinal, UINT8 data)
	282	{
	283	switch(m_addressing_mode)
	284	{
	285	case ADDRESSING_MODE_EA: write_memory(m_ea.w + ordinal, data); break;
	286	case ADDRESSING_MODE_REGISTER_D: *((ordinal & 1) ? &m_d.b.l : &m_d.b.h) = data; break;
	287	case ADDRESSING_MODE_REGISTER_W: *((ordinal & 1) ? &m_w.b.l : &m_w.b.h) = data; break;
	288	case ADDRESSING_MODE_REGISTER_X: *((ordinal & 1) ? &m_x.b.l : &m_x.b.h) = data; break;
	289	case ADDRESSING_MODE_REGISTER_Y: *((ordinal & 1) ? &m_y.b.l : &m_y.b.h) = data; break;
	290	case ADDRESSING_MODE_REGISTER_U: *((ordinal & 1) ? &m_u.b.l : &m_u.b.h) = data; break;
	291	case ADDRESSING_MODE_REGISTER_S: *((ordinal & 1) ? &m_s.b.l : &m_s.b.h) = data; break;
	292	case ADDRESSING_MODE_REGISTER_V: *((ordinal & 1) ? &m_v.b.l : &m_v.b.h) = data; break;
	293	case ADDRESSING_MODE_REGISTER_PC: *((ordinal & 1) ? &m_pc.b.l : &m_pc.b.h) = data; break;
	294	case ADDRESSING_MODE_ZERO: break;
	295	default: fatalerror("Unexpected"); break;
	296	}
	297	}
	298
	299
	300	//-------------------------------------------------
	301	// bittest_register
	302	//-------------------------------------------------
	303
	304	ATTR_FORCE_INLINE UINT8 &hd6309_device::bittest_register()
	305	{
	306	switch(m_temp_im & 0xC0)
	307	{
	308	case 0x00: return m_cc;
	309	case 0x40: return m_d.b.h;
	310	case 0x80: return m_d.b.l;
	311	default: return m_temp.b.l;
	312	}
	313	}
	314
	315
	316	//-------------------------------------------------
	317	// bittest_source
	318	//-------------------------------------------------
	319
	320	ATTR_FORCE_INLINE bool hd6309_device::bittest_source()
	321	{
	322	return (m_temp.b.l & (1 << ((m_temp_im >> 3) & 0x07))) ? true : false;
	323	}
	324
	325
	326	//-------------------------------------------------
	327	// bittest_dest
	328	//-------------------------------------------------
	329
	330	ATTR_FORCE_INLINE bool hd6309_device::bittest_dest()
	331	{
	332	return (bittest_register() & (1 << ((m_temp_im >> 0) & 0x07))) ? true : false;
	333	}
	334
	335
	336	//-------------------------------------------------
	337	// bittest_set
	338	//-------------------------------------------------
	339
	340	ATTR_FORCE_INLINE void hd6309_device::bittest_set(bool result)
	341	{
	342	if (result)
	343	bittest_register() \|= (1 << ((m_temp_im >> 0) & 0x07));
	344	else
	345	bittest_register() &= ~(1 << ((m_temp_im >> 0) & 0x07));
	346	eat(4);
	347	}
	348
	349
	350	//-------------------------------------------------
	351	// read_exgtfr_register
	352	//-------------------------------------------------
	353
	354	ATTR_FORCE_INLINE m6809_base_device::exgtfr_register hd6309_device::read_exgtfr_register(UINT8 reg)
	355	{
	356	UINT16 value = 0;
	357
	358	switch(reg & 0x0F)
	359	{
	360	case 0: value = m_d.w; break; // D
	361	case 1: value = m_x.w; break; // X
	362	case 2: value = m_y.w; break; // Y
	363	case 3: value = m_u.w; break; // U
	364	case 4: value = m_s.w; break; // S
	365	case 5: value = m_pc.w; break; // PC
	366	case 6: value = m_w.w; break; // W
	367	case 7: value = m_v.w; break; // V
	368	case 8: value = ((UINT16) m_d.b.h) << 8 \| m_d.b.h; break; // A
	369	case 9: value = ((UINT16) m_d.b.l) << 8 \| m_d.b.l; break; // B
	370	case 10: value = ((UINT16) m_cc) << 8 \| m_cc; break; // CC
	371	case 11: value = ((UINT16) m_dp) << 8 \| m_dp; break; // DP
	372	case 12: value = 0; break; // 0
	373	case 13: value = 0; break; // 0
	374	case 14: value = ((UINT16) m_w.b.h) << 8 \| m_w.b.h; break; // E
	375	case 15: value = ((UINT16) m_w.b.l) << 8 \| m_w.b.l; break; // F
	376	default:
	377	fatalerror("Should not reach here");
	378	break;
	379	}
	380
	381	exgtfr_register result;
	382	result.byte_value = (UINT8)value;
	383	result.word_value = value;
	384	return result;
	385	}
	386
	387
	388
	389	//-------------------------------------------------
	390	// write_exgtfr_register
	391	//-------------------------------------------------
	392
	393	ATTR_FORCE_INLINE void hd6309_device::write_exgtfr_register(UINT8 reg, m6809_base_device::exgtfr_register value)
	394	{
	395	switch(reg & 0x0F)
	396	{
	397	case 0: m_d.w = value.word_value; break; // D
	398	case 1: m_x.w = value.word_value; break; // X
	399	case 2: m_y.w = value.word_value; break; // Y
	400	case 3: m_u.w = value.word_value; break; // U
	401	case 4: m_s.w = value.word_value; break; // S
	402	case 5: m_pc.w = value.word_value; break; // PC
	403	case 6: m_w.w = value.word_value; break; // W
	404	case 7: m_v.w = value.word_value; break; // V
	405	case 8: m_d.b.h = (UINT8) (value.word_value >> 8); break; // A
	406	case 9: m_d.b.l = (UINT8) (value.word_value >> 0); break; // B
	407	case 10: m_cc = (UINT8) (value.word_value >> 0); break; // CC
	408	case 11: m_dp = (UINT8) (value.word_value >> 8); break; // DP
	409	case 12: break; // 0
	410	case 13: break; // 0
	411	case 14: m_w.b.h = (UINT8) (value.word_value >> 8); break; // E
	412	case 15: m_w.b.l = (UINT8) (value.word_value >> 0); break; // F
	413	default:
	414	fatalerror("Should not reach here");
	415	break;
	416	}
	417	}
	418
	419
	420
	421	//-------------------------------------------------
	422	// tfr_read
	423	//-------------------------------------------------
	424
	425	ATTR_FORCE_INLINE bool hd6309_device::tfr_read(UINT8 opcode, UINT8 arg, UINT8 &data)
	426	{
	427	PAIR16 *reg;
	428
	429	switch(arg & 0xF0)
	430	{
	431	case 0x00: reg = &m_d; break;
	432	case 0x10: reg = &m_x; break;
	433	case 0x20: reg = &m_y; break;
	434	case 0x30: reg = &m_u; break;
	435	case 0x40: reg = &m_s; break;
	436	default: return false;
	437	}
	438
	439	data = read_memory(reg->w);
	440
	441	switch(opcode & 0x03)
	442	{
	443	case 0x00: reg->w++; break; // TFM R0+,R1+
	444	case 0x01: reg->w--; break; // TFM R0-,R1-
	445	case 0x02: reg->w++; break; // TFM R0+,R1
	446	case 0x03: break; // TFM R0,R1+
	447	}
	448
	449	return true;
	450	}
	451
	452
	453
	454	//-------------------------------------------------
	455	// tfr_write
	456	//-------------------------------------------------
	457
	458	ATTR_FORCE_INLINE bool hd6309_device::tfr_write(UINT8 opcode, UINT8 arg, UINT8 data)
	459	{
	460	PAIR16 *reg;
	461
	462	switch(arg & 0x0F)
	463	{
	464	case 0x00: reg = &m_d; break;
	465	case 0x01: reg = &m_x; break;
	466	case 0x02: reg = &m_y; break;
	467	case 0x03: reg = &m_u; break;
	468	case 0x04: reg = &m_s; break;
	469	default: return false;
	470	}
	471
	472	write_memory(reg->w, data);
	473
	474	switch(opcode & 0x03)
	475	{
	476	case 0x00: reg->w++; break; // TFM R0+,R1+
	477	case 0x01: reg->w--; break; // TFM R0-,R1-
	478	case 0x02: break; // TFM R0+,R1
	479	case 0x03: reg->w++; break; // TFM R0,R1+
	480	}
	481
	482	return true;
	483	}
	484
	485
	486
	487	//-------------------------------------------------
	488	// register_register_op
	489	//-------------------------------------------------
	490
	491	void hd6309_device::register_register_op()
	492	{
	493	UINT8 operand = read_opcode_arg();
	494
	495	// if the 8/16 bit values are mismatched, we need to promote
	496	bool promote = ((operand & 0x80) ? true : false) != ((operand & 0x08) ? true : false);
	497
	498	// we're using m_temp as "register 0"
	499	m_temp.w = 0;
	500
	501	// set destination
	502	switch((operand >> 0) & 0x0F)
	503	{
	504	case 0: set_regop16(m_d); break; // D
	505	case 1: set_regop16(m_x); break; // X
	506	case 2: set_regop16(m_y); break; // Y
	507	case 3: set_regop16(m_u); break; // U
	508	case 4: set_regop16(m_s); break; // S
	509	case 5: set_regop16(m_pc); break; // PC
	510	case 6: set_regop16(m_w); break; // W
	511	case 7: set_regop16(m_v); break; // V
	512	case 8: if (promote) set_regop16(m_d); else set_regop8(m_d.b.h); break; // A
	513	case 9: if (promote) set_regop16(m_d); else set_regop8(m_d.b.l); break; // B
	514	case 10: if (promote) set_regop16(m_temp); else set_regop8(m_cc); break; // CC
	515	case 11: if (promote) set_regop16(m_temp); else set_regop8(m_dp); break; // DP
	516	case 12: if (promote) set_regop16(m_temp); else set_regop8(m_temp.b.l); break; // 0
	517	case 13: if (promote) set_regop16(m_temp); else set_regop8(m_temp.b.l); break; // 0
	518	case 14: if (promote) set_regop16(m_w); else set_regop8(m_w.b.h); break; // E
	519	case 15: if (promote) set_regop16(m_w); else set_regop8(m_w.b.l); break; // F
	520	default:
	521	fatalerror("Should not reach here");
	522	break;
	523	}
	524
	525	// set source
	526	switch((operand >> 4) & 0x0F)
	527	{
	528	case 0: m_addressing_mode = ADDRESSING_MODE_REGISTER_D; break; // D
	529	case 1: m_addressing_mode = ADDRESSING_MODE_REGISTER_X; break; // X
	530	case 2: m_addressing_mode = ADDRESSING_MODE_REGISTER_Y; break; // Y
	531	case 3: m_addressing_mode = ADDRESSING_MODE_REGISTER_U; break; // U
	532	case 4: m_addressing_mode = ADDRESSING_MODE_REGISTER_S; break; // S
	533	case 5: m_addressing_mode = ADDRESSING_MODE_REGISTER_PC; break; // PC
	534	case 6: m_addressing_mode = ADDRESSING_MODE_REGISTER_W; break; // W
	535	case 7: m_addressing_mode = ADDRESSING_MODE_REGISTER_V; break; // V
	536	case 8: m_addressing_mode = promote ? ADDRESSING_MODE_REGISTER_D : ADDRESSING_MODE_REGISTER_A; break; // A
	537	case 9: m_addressing_mode = promote ? ADDRESSING_MODE_REGISTER_D : ADDRESSING_MODE_REGISTER_B; break; // B
	538	case 10: m_addressing_mode = promote ? ADDRESSING_MODE_ZERO : ADDRESSING_MODE_REGISTER_CC; break; // CC
	539	case 11: m_addressing_mode = promote ? ADDRESSING_MODE_ZERO : ADDRESSING_MODE_REGISTER_DP; break; // DP
	540	case 12: m_addressing_mode = ADDRESSING_MODE_ZERO; break; // 0
	541	case 13: m_addressing_mode = ADDRESSING_MODE_ZERO; break; // 0
	542	case 14: m_addressing_mode = promote ? ADDRESSING_MODE_REGISTER_W : ADDRESSING_MODE_REGISTER_E; break; // E
	543	case 15: m_addressing_mode = promote ? ADDRESSING_MODE_REGISTER_W : ADDRESSING_MODE_REGISTER_F; break; // F
	544	default:
	545	fatalerror("Should not reach here");
	546	break;
	547	}
	548
	549	// eat a single CPU cycle
	550	eat(1);
	551	}
	552
	553
	554	//-------------------------------------------------
	555	// get_q
	556	//-------------------------------------------------
	557
	558	UINT32 hd6309_device::get_q()
	559	{
	560	PAIR result;
	561	result.w.h = m_d.w;
	562	result.w.l = m_w.w;
	563	return result.d;
	564	}
	565
	566
	567	//-------------------------------------------------
	568	// put_q
	569	//-------------------------------------------------
	570
	571	void hd6309_device::put_q(UINT32 value)
	572	{
	573	PAIR pair;
	574	pair.d = value;
	575	m_d.w = pair.w.h;
	576	m_w.w = pair.w.l;
	577	}
	578
	579
	580	//-------------------------------------------------
	581	// muld - (Q := D * operand)
	582	//-------------------------------------------------
	583
	584	void hd6309_device::muld()
	585	{
	586	UINT32 result;
	587	result = ((INT16) m_d.w) * ((INT16) m_temp.w);
	588	put_q(set_flags<UINT32>(CC_NZ, result));
	589	m_cc &= ~CC_VC;
	590	}
	591
	592
	593	//-------------------------------------------------
	594	// divq - (D := Q / operand; W := Q % operand)
	595	//-------------------------------------------------
	596
	597	bool hd6309_device::divq()
	598	{
	599	INT32 result;
	600
	601	// check for divide by zero
	602	if (m_temp.w == 0)
	603	return false;
	604
	605	INT32 q = get_q();
	606	INT32 old_q = q;
	607
	608	// do the divide/modulo
	609	result = q / (INT16) m_temp.w;
	610	m_d.w = q % (INT16) m_temp.w;
	611
	612	// set NZ condition codes
	613	m_w.w = set_flags<UINT16>(CC_NZ, result);
	614
	615	// set C condition code
	616	if (m_w.w & 0x0001)
	617	m_cc \|= CC_C;
	618	else
	619	m_cc &= ~CC_C;
	620
	621	if ((result > 32768) \|\| (result < -32767))
	622	{
	623	// soft overflow
	624	m_cc \|= CC_V;
	625
	626	if ((result > 65536 ) \|\| (result < -65535 ))
	627	{
	628	// hard overflow - division is aborted
	629	if (old_q < 0)
	630	m_cc \|= CC_N;
	631	else if (old_q == 0 )
	632	m_cc \|= CC_Z;
	633
	634	m_temp.w = abs(m_temp.w);
	635	put_q(old_q);
	636	}
	637	}
	638	else
	639	{
	640	// no overflow
	641	m_cc &= ~CC_V;
	642	}
	643
	644	return true;
	645	}
	646
	647
	648	//-------------------------------------------------
	649	// divd - (D := D / operand; W := D % operand)
	650	//-------------------------------------------------
	651
	652	bool hd6309_device::divd()
	653	{
	654	// check for divide by zero
	655	if (m_temp.b.l == 0)
	656	return false;
	657
	658	INT16 old_d = m_d.w;
	659	INT16 result;
	660
	661	// do the divide/modulo
	662	result = ((INT16) m_d.w) / (INT8) m_temp.b.l;
	663	m_d.b.h = ((INT16) m_d.w) % (INT8) m_temp.b.l;
	664
	665	// set NZ condition codes
	666	m_d.b.l = set_flags<UINT8>(CC_NZ, result);
	667
	668	// set C condition code
	669	if (m_d.b.l & 0x01)
	670	m_cc \|= CC_C;
	671	else
	672	m_cc &= ~CC_C;
	673
	674	if ((result > 128) \|\| (result < -127))
	675	{
	676	// soft overflow
	677	m_cc \|= CC_V;
	678
	679	if ((result > 256 ) \|\| (result < -255 ))
	680	{
	681	// hard overflow - division is aborted
	682	set_flags<UINT16>(CC_NZ, old_d);
	683	m_d.w = abs(old_d);
	684	}
	685	}
	686	else
	687	{
	688	// no overflow
	689	m_cc &= ~CC_V;
	690	}
	691
	692	return true;
	693	}
	694
	695
	696	//-------------------------------------------------
	697	// execute_one - try to execute a single instruction
	698	//-------------------------------------------------
	699
	700	ATTR_FORCE_INLINE void hd6309_device::execute_one()
	701	{
	702	switch(pop_state())
	703	{
	704	#include "cpu/m6809/hd6309.inc"
	705	}
	706	}
	707
	708
	709	//-------------------------------------------------
	710	// execute_run - execute a timeslice's worth of
	711	// opcodes
	712	//-------------------------------------------------
	713
	714	void hd6309_device::execute_run()
	715	{
	716	do
	717	{
	718	execute_one();
	719	} while(m_icount > 0);
	720	}

Property changes on: trunk/src/emu/cpu/m6809/hd6309.c
Added: svn:mime-type + text/plain Added: svn:eol-style + native

trunk/src/emu/cpu/m6809/konami.c
r0	r21565
	1	/*********************************************************************
	2
	3	konami.c
	4
	5	Portable Konami cpu emulator
	6
	7	Copyright Nicola Salmoria and the MAME Team
	8
	9	Based on M6809 cpu core copyright John Butler
	10
	11	References:
	12
	13	6809 Simulator V09, By L.C. Benschop, Eidnhoven The Netherlands.
	14
	15	m6809: Portable 6809 emulator, DS (6809 code in MAME, derived from
	16	the 6809 Simulator V09)
	17
	18	6809 Microcomputer Programming & Interfacing with Experiments"
	19	by Andrew C. Staugaard, Jr.; Howard W. Sams & Co., Inc.
	20
	21	System dependencies: UINT16 must be 16 bit unsigned int
	22	UINT8 must be 8 bit unsigned int
	23	UINT32 must be more than 16 bits
	24	arrays up to 65536 bytes must be supported
	25	machine must be twos complement
	26
	27	History:
	28
	29	March 2013 NPW:
	30	Rewrite of 6809/6309/Konami CPU; overall core is now unified and
	31	supports mid-instruction timings.
	32
	33	Some of the instruction timings have changed with the new core; the
	34	old core had some nonsensical timings. For example (from scontra):
	35
	36	819A 3A 07 1F 8C STA $1f8C
	37
	38	Under the old core, this took four clock cycles, which is dubious
	39	because this instruction would have to do four opcode reads and one
	40	write. OGalibert says that the current timings are just a guess and
	41	nobody has done precise readings, so I'm replacing the old guesses
	42	with new guesses.
	43
	44	991022 HJB:
	45	Tried to improve speed: Using bit7 of cycles1 as flag for multi
	46	byte opcodes is gone, those opcodes now instead go through opcode2().
	47	Inlined fetch_effective_address() into that function as well.
	48	Got rid of the slow/fast flags for stack (S and U) memory accesses.
	49	Minor changes to use 32 bit values as arguments to memory functions
	50	and added defines for that purpose (e.g. X = 16bit XD = 32bit).
	51
	52	990720 EHC:
	53	Created this file
	54
	55	*****************************************************************************/
	56
	57	#include "emu.h"
	58	#include "debugger.h"
	59	#include "konami.h"
	60	#include "m6809inl.h"
	61
	62
	63	//**************************************************************************
	64	// PARAMETERS
	65	//**************************************************************************
	66
	67	// turn off 'unreferenced label' errors
	68	#ifdef __GNUC__
	69	#pragma GCC diagnostic ignored "-Wunused-label"
	70	#endif
	71	#ifdef _MSC_VER
	72	#pragma warning( disable : 4102 )
	73	#endif
	74
	75
	76	//**************************************************************************
	77	// DEVICE INTERFACE
	78	//**************************************************************************
	79
	80	const device_type KONAMI = &device_creator<konami_cpu_device>;
	81
	82
	83	//-------------------------------------------------
	84	// konami_cpu_device - constructor
	85	//-------------------------------------------------
	86
	87	konami_cpu_device::konami_cpu_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
	88	: m6809_base_device(mconfig, "KONAMI", tag, owner, clock, KONAMI, 1)
	89	{
	90	}
	91
	92
	93	//-------------------------------------------------
	94	// device_start - device-specific startup
	95	//-------------------------------------------------
	96
	97	void konami_cpu_device::device_start()
	98	{
	99	super::device_start();
	100
	101	// initialize variables
	102	m_set_lines = NULL;
	103	}
	104
	105
	106	//-------------------------------------------------
	107	// disasm_disassemble - call the disassembly
	108	// helper function
	109	//-------------------------------------------------
	110
	111	offs_t konami_cpu_device::disasm_disassemble(char buffer, offs_t pc, const UINT8 oprom, const UINT8 *opram, UINT32 options)
	112	{
	113	extern offs_t konami_cpu_disassemble(char buffer, offs_t pc, const UINT8 oprom, const UINT8 *opram, UINT32 options);
	114	return konami_cpu_disassemble(buffer, pc, oprom, opram, options);
	115	}
	116
	117
	118	//-------------------------------------------------
	119	// ireg
	120	//-------------------------------------------------
	121
	122	ATTR_FORCE_INLINE UINT16 &konami_cpu_device::ireg()
	123	{
	124	switch(m_opcode & 0x70)
	125	{
	126	case 0x20: return m_x.w;
	127	case 0x30: return m_y.w;
	128	case 0x50: return m_u.w;
	129	case 0x60: return m_s.w;
	130	case 0x70: return m_pc.w;
	131	default:
	132	fatalerror("Should not get here");
	133	return m_x.w;
	134	}
	135	}
	136
	137
	138	//-------------------------------------------------
	139	// safe_shift_right
	140	//-------------------------------------------------
	141
	142	template<class T> T konami_cpu_device::safe_shift_right(T value, UINT32 shift)
	143	{
	144	T result;
	145
	146	if (shift < (sizeof(T) * 8))
	147	result = value >> shift;
	148	else if (value < 0)
	149	result = (T) -1;
	150	else
	151	result = 0;
	152
	153	return result;
	154	}
	155
	156
	157	//-------------------------------------------------
	158	// safe_shift_left
	159	//-------------------------------------------------
	160
	161	template<class T> T konami_cpu_device::safe_shift_left(T value, UINT32 shift)
	162	{
	163	T result;
	164
	165	if (shift < (sizeof(T) * 8))
	166	result = value << shift;
	167	else
	168	result = 0;
	169
	170	return result;
	171	}
	172
	173
	174	//-------------------------------------------------
	175	// lmul
	176	//-------------------------------------------------
	177
	178	ATTR_FORCE_INLINE void konami_cpu_device::lmul()
	179	{
	180	PAIR result;
	181
	182	// do the multiply
	183	result.d = (UINT32)m_x.w * m_y.w;
	184
	185	// set the result registers
	186	m_x.w = result.w.h;
	187	m_y.w = result.w.l;
	188
	189	// set Z flag
	190	set_flags<UINT32>(CC_Z, result.d);
	191
	192	// set C flag
	193	if (result.d & 0x8000)
	194	m_cc \|= CC_C;
	195	else
	196	m_cc &= ~CC_C;
	197	}
	198
	199
	200	//-------------------------------------------------
	201	// divx
	202	//-------------------------------------------------
	203
	204	ATTR_FORCE_INLINE void konami_cpu_device::divx()
	205	{
	206	UINT16 result;
	207	UINT8 remainder;
	208
	209	if (m_d.b.l != 0)
	210	{
	211	result = m_x.w / m_d.b.l;
	212	remainder = m_x.w % m_d.b.l;
	213	}
	214	else
	215	{
	216	// divide by zero; not sure what happens
	217	result = 0;
	218	remainder = 0;
	219	}
	220
	221	// set results and Z flag
	222	m_x.w = set_flags<UINT16>(CC_Z, result);
	223	m_d.b.l = remainder;
	224
	225	// set C flag
	226	if (result & 0x0080)
	227	m_cc \|= CC_C;
	228	else
	229	m_cc &= ~CC_C;
	230	}
	231
	232
	233	//-------------------------------------------------
	234	// execute_one - try to execute a single instruction
	235	//-------------------------------------------------
	236
	237	void konami_cpu_device::set_lines(UINT8 data)
	238	{
	239	if (m_set_lines != NULL)
	240	(*m_set_lines)(this, data);
	241	}
	242
	243
	244	//-------------------------------------------------
	245	// execute_one - try to execute a single instruction
	246	//-------------------------------------------------
	247
	248	ATTR_FORCE_INLINE void konami_cpu_device::execute_one()
	249	{
	250	switch(pop_state())
	251	{
	252	#include "cpu/m6809/konami.inc"
	253	}
	254	}
	255
	256
	257	//-------------------------------------------------
	258	// execute_run - execute a timeslice's worth of
	259	// opcodes
	260	//-------------------------------------------------
	261
	262	void konami_cpu_device::execute_run()
	263	{
	264	do
	265	{
	266	execute_one();
	267	} while(m_icount > 0);
	268	}
	269
	270
	271	//-------------------------------------------------
	272	// konami_configure_set_lines
	273	//-------------------------------------------------
	274
	275	void konami_configure_set_lines(device_t *device, konami_set_lines_func func)
	276	{
	277	konami_cpu_device cpu = dynamic_cast<konami_cpu_device>(device);
	278	cpu->configure_set_lines(func);
	279	}

Property changes on: trunk/src/emu/cpu/m6809/konami.c
Added: svn:eol-style + native Added: svn:mime-type + text/plain

trunk/src/emu/cpu/m6809/base6x09.ops
r0	r21565
	1	NMI:
	2	m_nmi_asserted = false;
	3	m_cc \|= CC_E;
	4	set_regop16(m_s);
	5	m_temp.w = entire_state_registers();
	6	%PUSH_REGISTERS;
	7	m_cc \|= CC_I \| CC_F;
	8	set_ea(VECTOR_NMI);
	9	eat(1);
	10	goto INTERRUPT_VECTOR;
	11
	12	FIRQ:
	13	if (firq_saves_entire_state())
	14	{
	15	m_cc \|= CC_E;
	16	m_temp.w = entire_state_registers();
	17	}
	18	else
	19	{
	20	m_cc &= ~CC_E;
	21	m_temp.w = partial_state_registers();
	22	}
	23	set_regop16(m_s);
	24	%PUSH_REGISTERS;
	25	m_cc \|= CC_I \| CC_F;
	26	set_ea(VECTOR_FIRQ);
	27	eat(1);
	28	goto INTERRUPT_VECTOR;
	29
	30	IRQ:
	31	m_cc \|= CC_E;
	32	set_regop16(m_s);
	33	m_temp.w = entire_state_registers();
	34	%PUSH_REGISTERS;
	35	m_cc \|= CC_I;
	36	set_ea(VECTOR_IRQ);
	37	eat(1);
	38	goto INTERRUPT_VECTOR;
	39
	40	INTERRUPT_VECTOR:
	41	@eat(4);
	42	@m_pc.b.h = read_operand(0); // Not sure if this is cycle exact
	43	@m_pc.b.l = read_operand(1); // Not sure if this is cycle exact
	44	return;
	45
	46	NEG8:
	47	@m_temp.b.l = read_operand();
	48	m_temp.b.l = set_flags(CC_NZVC, (UINT8)0, m_temp.b.l, -m_temp.b.l);
	49	@eat(hd6309_native_mode() ? 0 : 1);
	50	@write_operand(m_temp.b.l);
	51	return;
	52
	53	COM8:
	54	@m_temp.b.l = read_operand();
	55	m_cc &= ~CC_V;
	56	m_cc \|= CC_C;
	57	m_temp.b.l = set_flags(CC_NZ, (UINT8) ~m_temp.b.l);
	58	@eat(hd6309_native_mode() ? 0 : 1);
	59	@write_operand(m_temp.b.l);
	60	return;
	61
	62	LSR8:
	63	@m_temp.b.l = read_operand();
	64	m_cc &= ~CC_C;
	65	m_cc \|= (m_temp.b.l & 1) ? CC_C : 0;
	66	m_temp.b.l = set_flags<UINT8>(CC_NZ, m_temp.b.l >> 1);
	67	@eat(hd6309_native_mode() ? 0 : 1);
	68	@write_operand(m_temp.b.l);
	69	return;
	70
	71	ROR8:
	72	@m_temp.b.l = read_operand();
	73	m_temp.b.l = set_flags<UINT8>(CC_NZ, rotate_right(m_temp.b.l));
	74	@eat(hd6309_native_mode() ? 0 : 1);
	75	@write_operand(m_temp.b.l);
	76	return;
	77
	78	ASR8:
	79	@m_temp.b.l = read_operand();
	80	m_cc &= ~CC_NZC;
	81	m_cc \|= (m_temp.b.l & 1) ? CC_C : 0;
	82	m_temp.b.l = set_flags<UINT8>(CC_NZ, ((INT8) m_temp.b.l) >> 1);
	83	@eat(hd6309_native_mode() ? 0 : 1);
	84	@write_operand(m_temp.b.l);
	85	return;
	86
	87	ASL8:
	88	@m_temp.b.l = read_operand();
	89	m_temp.b.l = set_flags<UINT8>(CC_NZVC, m_temp.b.l, m_temp.b.l, m_temp.b.l << 1);
	90	@eat(hd6309_native_mode() ? 0 : 1);
	91	@write_operand(m_temp.b.l);
	92	return;
	93
	94	ROL8:
	95	@m_temp.b.l = read_operand();
	96	m_temp.b.l = set_flags<UINT8>(CC_NZV, m_temp.b.l, m_temp.b.l, rotate_left(m_temp.b.l));
	97	@eat(hd6309_native_mode() ? 0 : 1);
	98	@write_operand(m_temp.b.l);
	99	return;
	100
	101	DEC8:
	102	@m_temp.b.l = read_operand();
	103	m_temp.b.l = set_flags<UINT8>(CC_NZV, m_temp.b.l, 1, m_temp.b.l - 1);
	104	@eat(hd6309_native_mode() && is_register_addressing_mode() ? 0 : 1);
	105	@write_operand(m_temp.b.l);
	106	return;
	107
	108	INC8:
	109	@m_temp.b.l = read_operand();
	110	m_temp.b.l = set_flags<UINT8>(CC_NZV, m_temp.b.l, 1, m_temp.b.l + 1);
	111	@eat(hd6309_native_mode() && is_register_addressing_mode() ? 0 : 1);
	112	@write_operand(m_temp.b.l);
	113	return;
	114
	115	TST8:
	116	@m_temp.b.l = read_operand();
	117	set_flags(CC_NZV, m_temp.b.l);
	118	eat(hd6309_native_mode() ? 0 : 1);
	119	eat(is_register_addressing_mode() ? 0 : 1);
	120	return;
	121
	122	JMP:
	123	m_pc.w = m_ea.w;
	124	return;
	125
	126	CLR8:
	127	@read_operand();
	128	m_cc &= ~CC_NZVC;
	129	m_cc \|= CC_Z;
	130	@eat(hd6309_native_mode() && is_register_addressing_mode() ? 0 : 1);
	131	@write_operand(0);
	132	return;
	133
	134	NEG16:
	135	m_temp.b.h = read_operand(0);
	136	m_temp.b.l = read_operand(1);
	137	m_temp.b.l = set_flags(CC_NZVC, (UINT16)0, m_temp.w, -m_temp.w);
	138	eat(hd6309_native_mode() ? 0 : 1);
	139	write_operand(0, m_temp.b.h);
	140	write_operand(1, m_temp.b.l);
	141	return;
	142
	143	LSR16:
	144	@m_temp.b.h = read_operand(0);
	145	@m_temp.b.l = read_operand(1);
	146	m_cc &= ~CC_C;
	147	m_cc \|= (m_temp.w & 1) ? CC_C : 0;
	148	m_temp.w = set_flags<UINT16>(CC_NZ, m_temp.w >> 1);
	149	@eat(hd6309_native_mode() ? 0 : 1);
	150	@write_operand(0, m_temp.b.h);
	151	write_operand(1, m_temp.b.l);
	152	return;
	153
	154	ROR16:
	155	@m_temp.b.h = read_operand(0);
	156	@m_temp.b.l = read_operand(1);
	157	m_temp.w = set_flags<UINT16>(CC_NZ, rotate_right(m_temp.w));
	158	@eat(hd6309_native_mode() ? 0 : 1);
	159	@write_operand(0, m_temp.b.h);
	160	write_operand(1, m_temp.b.l);
	161	return;
	162
	163	ASR16:
	164	@m_temp.b.h = read_operand(0);
	165	@m_temp.b.l = read_operand(1);
	166	m_cc &= ~CC_NZC;
	167	m_cc \|= (m_temp.b.l & 1) ? CC_C : 0;
	168	m_temp.w = set_flags<UINT16>(CC_NZ, ((INT16) m_temp.b.l) >> 1);
	169	@eat(hd6309_native_mode() ? 0 : 1);
	170	@write_operand(0, m_temp.b.h);
	171	write_operand(1, m_temp.b.l);
	172	return;
	173
	174	ASL16:
	175	@m_temp.b.h = read_operand(0);
	176	@m_temp.b.l = read_operand(1);
	177	m_temp.w = set_flags<UINT16>(CC_NZVC, m_temp.w, m_temp.w, m_temp.w << 1);
	178	@eat(hd6309_native_mode() ? 0 : 1);
	179	@write_operand(0, m_temp.b.h);
	180	write_operand(1, m_temp.b.l);
	181	return;
	182
	183	ROL16:
	184	@m_temp.b.h = read_operand(0);
	185	@m_temp.b.l = read_operand(1);
	186	m_temp.w = set_flags<UINT16>(CC_NZV, rotate_left(m_temp.w));
	187	@eat(hd6309_native_mode() ? 0 : 1);
	188	@write_operand(0, m_temp.b.h);
	189	write_operand(1, m_temp.b.l);
	190	return;
	191
	192	DEC16:
	193	m_temp.b.h = read_operand(0);
	194	m_temp.b.l = read_operand(1);
	195	m_temp.w = set_flags<UINT16>(CC_NZVC, m_temp.w, 1, m_temp.w - 1);
	196	eat(hd6309_native_mode() ? 0 : 1);
	197	write_operand(0, m_temp.b.h);
	198	write_operand(1, m_temp.b.l);
	199	return;
	200
	201	INC16:
	202	m_temp.b.h = read_operand(0);
	203	m_temp.b.l = read_operand(1);
	204	m_temp.w = set_flags<UINT16>(CC_NZVC, m_temp.w, 1, m_temp.w + 1);
	205	eat(hd6309_native_mode() ? 0 : 1);
	206	write_operand(0, m_temp.b.h);
	207	write_operand(1, m_temp.b.l);
	208	return;
	209
	210	TST16:
	211	m_temp.b.h = read_operand(0);
	212	m_temp.b.l = read_operand(1);
	213	set_flags(CC_NZV, m_temp.w);
	214	eat(hd6309_native_mode() ? 0 : 1);
	215	eat(is_register_addressing_mode() ? 0 : 1);
	216	return;
	217
	218	CLR16:
	219	eat(hd6309_native_mode() ? 0 : 1);
	220	m_cc &= ~CC_NZVC;
	221	m_cc \|= CC_Z;
	222	write_operand(0, 0x00);
	223	write_operand(1, 0x00);
	224	return;
	225
	226	SUB8:
	227	m_temp.b.l = read_operand();
	228	regop8() = set_flags(CC_NZVC, regop8(), m_temp.b.l, regop8() - m_temp.b.l);
	229	return;
	230
	231	CMP8:
	232	m_temp.b.l = read_operand();
	233	set_flags(CC_NZVC, regop8(), m_temp.b.l, regop8() - m_temp.b.l);
	234	return;
	235
	236	SBC8:
	237	m_temp.w = (UINT16)read_operand() + (m_cc & CC_C ? 1 : 0);
	238	regop8() = set_flags(CC_NZVC, regop8(), m_temp.b.l, regop8() - m_temp.w);
	239	return;
	240
	241	AND8:
	242	m_cc &= ~CC_V;
	243	regop8() = set_flags(CC_NZ, (UINT8)0, regop8(), regop8() & read_operand());
	244	return;
	245
	246	BIT8:
	247	m_cc &= ~CC_V;
	248	set_flags(CC_NZ, (UINT8)0, regop8(), regop8() & read_operand());
	249	return;
	250
	251	EOR8:
	252	m_cc &= ~CC_V;
	253	regop8() = set_flags(CC_NZ, (UINT8)0, regop8(), regop8() ^ read_operand());
	254	return;
	255
	256	ADC8:
	257	m_temp.w = (UINT16)read_operand() + (m_cc & CC_C ? 1 : 0);
	258	regop8() = set_flags(add8_sets_h() ? CC_HNZVC : CC_NZVC, regop8(), m_temp.b.l, regop8() + m_temp.w);
	259	return;
	260
	261	OR8:
	262	m_cc &= ~CC_V;
	263	regop8() = set_flags(CC_NZ, (UINT8)0, regop8(), regop8() \| read_operand());
	264	return;
	265
	266	ADD8:
	267	m_temp.b.l = read_operand();
	268	regop8() = set_flags(add8_sets_h() ? CC_HNZVC : CC_NZVC, regop8(), m_temp.b.l, regop8() + m_temp.b.l);
	269	return;
	270
	271	ADD16:
	272	@m_temp.b.h = read_operand(0);
	273	@m_temp.b.l = read_operand(1);
	274	regop16().w = set_flags(CC_NZVC, regop16().w, m_temp.w, regop16().w + m_temp.w);
	275	eat(hd6309_native_mode() ? 0 : 1);
	276	return;
	277
	278	SUB16:
	279	@m_temp.b.h = read_operand(0);
	280	@m_temp.b.l = read_operand(1);
	281	regop16().w = set_flags(CC_NZVC, regop16().w, m_temp.w, regop16().w - m_temp.w);
	282	eat(hd6309_native_mode() ? 0 : 1);
	283	return;
	284
	285	CMP16:
	286	@m_temp.b.h = read_operand(0);
	287	@m_temp.b.l = read_operand(1);
	288	set_flags(CC_NZVC, regop16().w, m_temp.w, regop16().w - m_temp.w);
	289	eat(hd6309_native_mode() ? 0 : 1);
	290	return;
	291
	292	LD8:
	293	regop8() = read_operand();
	294	set_flags(CC_NZV, regop8());
	295	return;
	296
	297	LD16:
	298	@regop16().b.h = read_operand(0);
	299	@regop16().b.l = read_operand(1);
	300	set_flags(CC_NZV, regop16().w);
	301	if (&regop16() == &m_s)
	302	m_lds_encountered = true;
	303	return;
	304
	305	ST8:
	306	write_ea(set_flags(CC_NZV, regop8()));
	307	return;
	308
	309	ST16:
	310	@write_operand(0, regop16().b.h);
	311	@write_operand(1, regop16().b.l);
	312	set_flags(CC_NZV, regop16().w);
	313	return;
	314
	315	NOP:
	316	eat(hd6309_native_mode() ? 0 : 1);
	317	return;
	318
	319	SYNC:
	320	// SYNC stops processing instructions until an interrupt request happens.
	321	// This doesn't require the corresponding interrupt to be enabled: if it
	322	// is disabled, execution continues with the next instruction.
	323	eat(3);
	324
	325	while(!m_nmi_asserted && !m_firq_line && !m_irq_line)
	326	{
	327	// massaging the PC this way makes the debugger's behavior more
	328	// intuitive
	329	m_pc.w--;
	330
	331	@eat_remaining();
	332
	333	// unmassage...
	334	m_pc.w++;
	335	}
	336	return;
	337
	338	DAA:
	339	daa();
	340	eat(hd6309_native_mode() ? 0 : 1);
	341	return;
	342
	343	ORCC:
	344	m_cc \|= read_operand();
	345	eat(hd6309_native_mode() ? 0 : 1);
	346	return;
	347
	348	ANDCC:
	349	m_cc &= read_operand();
	350	eat(1);
	351	return;
	352
	353	SEX:
	354	m_d.w = set_flags<UINT16>(CC_NZ, (INT8) m_d.b.l);
	355	eat(hd6309_native_mode() ? 0 : 1);
	356	return;
	357
	358	EXG:
	359	{
	360	UINT8 param = read_opcode_arg();
	361	exgtfr_register reg1 = read_exgtfr_register(param >> 4);
	362	exgtfr_register reg2 = read_exgtfr_register(param >> 0);
	363	write_exgtfr_register(param >> 4, reg2);
	364	write_exgtfr_register(param >> 0, reg1);
	365	}
	366	eat(hd6309_native_mode() ? 3 : 6);
	367	return;
	368
	369	TFR:
	370	{
	371	UINT8 param = read_opcode_arg();
	372	exgtfr_register reg = read_exgtfr_register(param >> 4);
	373	write_exgtfr_register(param >> 0, reg);
	374	}
	375	eat(hd6309_native_mode() ? 2 : 4);
	376	return;
	377
	378	BRANCH:
	379	@m_temp.b.l = read_opcode_arg();
	380	eat(1);
	381	if (branch_taken())
	382	{
	383	m_pc.w += (INT8) m_temp.b.l;
	384	}
	385	return;
	386
	387	LBRANCH:
	388	@m_temp.b.h = read_opcode_arg();
	389	@m_temp.b.l = read_opcode_arg();
	390	eat(1);
	391	if (branch_taken())
	392	{
	393	m_pc.w += m_temp.w;
	394	eat(hd6309_native_mode() ? 0 : 1);
	395	}
	396	return;
	397
	398	BSR:
	399	@m_temp.b.l = read_opcode_arg();
	400	m_ea.w = m_pc.w + (INT8) m_temp.b.l;
	401	@eat(hd6309_native_mode() ? 2 : 3);
	402	goto GOTO_SUBROUTINE;
	403
	404	LBSR:
	405	@m_temp.b.h = read_opcode_arg();
	406	@m_temp.b.l = read_opcode_arg();
	407	m_ea.w = m_pc.w + (INT16) m_temp.w;
	408	@eat(hd6309_native_mode() ? 2 : 4);
	409	goto GOTO_SUBROUTINE;
	410
	411	JSR:
	412	@eat(2);
	413	goto GOTO_SUBROUTINE;
	414
	415	GOTO_SUBROUTINE:
	416	@write_memory(--m_s.w, m_pc.b.l);
	417	@write_memory(--m_s.w, m_pc.b.h);
	418	m_pc = m_ea;
	419	return;
	420
	421	RTS:
	422	m_temp.w = 0x80; // RTS is equivalent to "PULS PC"
	423	eat(hd6309_native_mode() ? 0 : 1);
	424	set_regop16(m_s);
	425	goto PULL_REGISTERS;
	426
	427	ABX:
	428	m_x.w += m_d.b.l;
	429	eat(hd6309_native_mode() ? 0 : 2);
	430	return;
	431
	432	MUL:
	433	mul();
	434	eat(hd6309_native_mode() ? 9 : 10);
	435	return;
	436
	437	RTI:
	438	set_regop16(m_s);
	439	m_temp.w = 0x01; // PULS CC
	440	%PULL_REGISTERS;
	441	m_temp.w = ((m_cc & CC_E) ? entire_state_registers() : partial_state_registers()) & ~0x01;
	442	goto PULL_REGISTERS;
	443
	444	CWAI:
	445	@m_cc &= read_opcode_arg();
	446	@eat(2);
	447
	448	m_cc \|= CC_E;
	449	set_regop16(m_s);
	450	m_temp.w = entire_state_registers();
	451	%PUSH_REGISTERS;
	452
	453	while((m_ea.w = get_pending_interrupt()) == 0)
	454	{
	455	// massaging the PC this way makes the debugger's behavior more
	456	// intuitive
	457	m_pc.w -= 2;
	458
	459	@eat_remaining();
	460
	461	// unmassage...
	462	m_pc.w += 2;
	463	}
	464
	465	if (m_nmi_asserted)
	466	m_nmi_asserted = false;
	467
	468	m_cc \|= CC_I \| (m_ea.w != VECTOR_IRQ ? CC_F : 0);
	469	goto INTERRUPT_VECTOR;
	470
	471	LEA_xy:
	472	regop16().w = set_flags(CC_Z, m_ea.w);
	473	eat(1);
	474	return;
	475
	476	LEA_us:
	477	if (&regop16() == &m_s)
	478	m_lds_encountered = true;
	479	regop16().w = m_ea.w;
	480	eat(1);
	481	return;
	482
	483	PSHS:
	484	@m_temp.w = read_opcode_arg();
	485	@eat(hd6309_native_mode() ? 2 : 3);
	486	set_regop16(m_s);
	487	goto PUSH_REGISTERS;
	488
	489	PULS:
	490	@m_temp.w = read_opcode_arg();
	491	@eat(hd6309_native_mode() ? 1 : 2);
	492	set_regop16(m_s);
	493	goto PULL_REGISTERS;
	494
	495	PSHU:
	496	@m_temp.w = read_opcode_arg();
	497	@eat(hd6309_native_mode() ? 2 : 3);
	498	set_regop16(m_u);
	499	goto PUSH_REGISTERS;
	500
	501	PULU:
	502	@m_temp.w = read_opcode_arg();
	503	@eat(hd6309_native_mode() ? 1 : 2);
	504	set_regop16(m_u);
	505	goto PULL_REGISTERS;
	506
	507	SWI:
	508	// doesn't use SOFTWARE_INTERRUPT label because SWI will
	509	// inhibit IRQ/FIRQ
	510	set_ea(VECTOR_SWI);
	511	set_regop16(m_s);
	512	m_temp.w = entire_state_registers();
	513	%PUSH_REGISTERS;
	514	m_cc \|= CC_I \| CC_F;
	515	goto INTERRUPT_VECTOR;
	516
	517	SWI2:
	518	set_ea(VECTOR_SWI2);
	519	goto SOFTWARE_INTERRUPT;
	520
	521	SWI3:
	522	set_ea(VECTOR_SWI3);
	523	goto SOFTWARE_INTERRUPT;
	524
	525	SOFTWARE_INTERRUPT:
	526	// used for SWI2/SWI3 and illegal/div0 on 6309
	527	m_cc \|= CC_E;
	528	set_regop16(m_s);
	529	m_temp.w = entire_state_registers();
	530	%PUSH_REGISTERS;
	531	goto INTERRUPT_VECTOR;
	532
	533	DIRECT:
	534	@set_ea(((UINT16)m_dp << 8) \| read_opcode_arg());
	535	@eat(hd6309_native_mode() ? 0 : 1);
	536	return;
	537
	538	EXTENDED:
	539	@set_ea_h(read_opcode_arg());
	540	@set_ea_l(read_opcode_arg());
	541	@eat(hd6309_native_mode() ? 0 : 1);
	542	return;

Property changes on: trunk/src/emu/cpu/m6809/base6x09.ops
Added: svn:eol-style + native Added: svn:mime-type + text/plain

trunk/src/emu/cpu/m6809/hd6309.h
r0	r21565
	1	/*********************************************************************
	2
	3	hd6309.h
	4
	5	Portable Hitachi 6309 emulator
	6
	7	**********************************************************************/
	8
	9	#pragma once
	10
	11	#ifndef __HD6309_H__
	12	#define __HD6309_H__
	13
	14	#include "m6809.h"
	15
	16
	17	//**************************************************************************
	18	// TYPE DEFINITIONS
	19	//**************************************************************************
	20
	21	// device type definition
	22	extern const device_type HD6309;
	23
	24	// ======================> hd6309_device
	25
	26	class hd6309_device : public m6809_base_device
	27	{
	28	public:
	29	// construction/destruction
	30	hd6309_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
	31
	32	protected:
	33	// device-level overrides
	34	virtual void device_start();
	35	virtual void device_reset();
	36
	37	// device_execute_interface overrides
	38	virtual void execute_run();
	39
	40	// device_disasm_interface overrides
	41	virtual UINT32 disasm_min_opcode_bytes() const;
	42	virtual UINT32 disasm_max_opcode_bytes() const;
	43	virtual offs_t disasm_disassemble(char buffer, offs_t pc, const UINT8 oprom, const UINT8 *opram, UINT32 options);
	44
	45	private:
	46	typedef m6809_base_device super;
	47
	48	// addressing modes
	49	static const int ADDRESSING_MODE_REGISTER_E = 5;
	50	static const int ADDRESSING_MODE_REGISTER_F = 6;
	51	static const int ADDRESSING_MODE_REGISTER_W = 7;
	52	static const int ADDRESSING_MODE_REGISTER_X = 8;
	53	static const int ADDRESSING_MODE_REGISTER_Y = 9;
	54	static const int ADDRESSING_MODE_REGISTER_U = 10;
	55	static const int ADDRESSING_MODE_REGISTER_S = 11;
	56	static const int ADDRESSING_MODE_REGISTER_CC = 12;
	57	static const int ADDRESSING_MODE_REGISTER_DP = 13;
	58	static const int ADDRESSING_MODE_REGISTER_PC = 14;
	59	static const int ADDRESSING_MODE_REGISTER_V = 15;
	60	static const int ADDRESSING_MODE_ZERO = 16;
	61
	62	// interrupt vectors
	63	static const UINT16 VECTOR_ILLEGAL = 0xFFF0;
	64
	65	// CPU registers
	66	PAIR16 m_w;
	67	PAIR16 m_v;
	68	UINT8 m_md;
	69
	70	// other state
	71	UINT8 m_temp_im;
	72
	73	// operand reading/writing
	74	UINT8 read_operand();
	75	UINT8 read_operand(int ordinal);
	76	void write_operand(UINT8 data);
	77	void write_operand(int ordinal, UINT8 data);
	78
	79	// interrupt registers
	80	bool firq_saves_entire_state() { return m_md & 0x02; }
	81	UINT16 entire_state_registers() { return hd6309_native_mode() ? 0x3FF : 0xFF; }
	82
	83	// bit tests
	84	UINT8 &bittest_register();
	85	bool bittest_source();
	86	bool bittest_dest();
	87	void bittest_set(bool result);
	88
	89	// complex instructions
	90	void muld();
	91	bool divq();
	92	bool divd();
	93
	94	// the Q register
	95	UINT32 get_q();
	96	void put_q(UINT32 value);
	97
	98	// miscellaneous
	99	void set_e() { m_addressing_mode = ADDRESSING_MODE_REGISTER_E; }
	100	void set_f() { m_addressing_mode = ADDRESSING_MODE_REGISTER_F; }
	101	void set_w() { m_addressing_mode = ADDRESSING_MODE_REGISTER_W; }
	102	exgtfr_register read_exgtfr_register(UINT8 reg);
	103	void write_exgtfr_register(UINT8 reg, exgtfr_register value);
	104	bool tfr_read(UINT8 opcode, UINT8 arg, UINT8 &data);
	105	bool tfr_write(UINT8 opcode, UINT8 arg, UINT8 data);
	106	bool add8_sets_h() { return (m_opcode & 0xFE) != 0x30; }
	107	void register_register_op();
	108	bool hd6309_native_mode() { return m_md & 0x01; }
	109
	110	void execute_one();
	111	};
	112
	113	enum
	114	{
	115	HD6309_PC = M6809_PC,
	116	HD6309_S = M6809_S,
	117	HD6309_CC = M6809_CC,
	118	HD6309_A = M6809_A,
	119	HD6309_B = M6809_B,
	120	HD6309_D = M6809_D,
	121	HD6309_U = M6809_U,
	122	HD6309_X = M6809_X,
	123	HD6309_Y = M6809_Y,
	124	HD6309_DP = M6809_DP,
	125
	126	HD6309_E = 1000,
	127	HD6309_F,
	128	HD6309_W,
	129	HD6309_V,
	130	HD6309_MD
	131	};
	132
	133	#define HD6309_IRQ_LINE 0 /* IRQ line number */
	134	#define HD6309_FIRQ_LINE 1 /* FIRQ line number */
	135
	136	#endif // __HD6309_H__
	137

Property changes on: trunk/src/emu/cpu/m6809/hd6309.h
Added: svn:mime-type + text/plain Added: svn:eol-style + native

trunk/src/emu/cpu/m6809/m6809.ops
r0	r21565
	1	MAIN:
	2	// check interrupt lines
	3	switch(check_pending_interrupt())
	4	{
	5	case VECTOR_NMI: goto NMI;
	6	case VECTOR_FIRQ: goto FIRQ;
	7	case VECTOR_IRQ: goto IRQ;
	8	}
	9
	10	// debugger hook
	11	m_ppc = m_pc;
	12	debugger_instruction_hook(this, m_pc.w);
	13
	14	// opcode fetch
	15	@m_opcode = read_opcode();
	16
	17	// burn delay loops
	18	burn_any_delay_loops();
	19
	20	// dispatch opcode
	21	switch(m_opcode)
	22	{
	23	case 0x00: case 0x01: %DIRECT; %NEG8; return;
	24	case 0x03: case 0x02: %DIRECT; %COM8; return;
	25	case 0x04: case 0x05: %DIRECT; %LSR8; return;
	26	case 0x06: %DIRECT; %ROR8; return;
	27	case 0x07: %DIRECT; %ASR8; return;
	28	case 0x08: %DIRECT; %ASL8; return;
	29	case 0x09: %DIRECT; %ROL8; return;
	30	case 0x0A: case 0x0B: %DIRECT; %DEC8; return;
	31	case 0x0C: %DIRECT; %INC8; return;
	32	case 0x0D: %DIRECT; %TST8; return;
	33	case 0x0E: %DIRECT; %JMP; return;
	34	case 0x0F: %DIRECT; %CLR8; return;
	35
	36	case 0x10: %DISPATCH10; return;
	37	case 0x11: %DISPATCH11; return;
	38	case 0x12: %NOP; return;
	39	case 0x13: %SYNC; return;
	40	case 0x16: set_cond(true); %LBRANCH; return;
	41	case 0x17: %LBSR; return;
	42	case 0x19: %DAA; return;
	43	case 0x1A: set_imm(); %ORCC; return;
	44	case 0x1C: set_imm(); %ANDCC; return;
	45	case 0x1D: %SEX; return;
	46	case 0x1E: %EXG; return;
	47	case 0x1F: %TFR; return;
	48
	49	case 0x20: set_cond(true); %BRANCH; return;
	50	case 0x21: set_cond(false); %BRANCH; return;
	51	case 0x22: set_cond(cond_hi()); %BRANCH; return;
	52	case 0x23: set_cond(!cond_hi()); %BRANCH; return;
	53	case 0x24: set_cond(cond_cc()); %BRANCH; return;
	54	case 0x25: set_cond(!cond_cc()); %BRANCH; return;
	55	case 0x26: set_cond(cond_ne()); %BRANCH; return;
	56	case 0x27: set_cond(!cond_ne()); %BRANCH; return;
	57	case 0x28: set_cond(cond_vc()); %BRANCH; return;
	58	case 0x29: set_cond(!cond_vc()); %BRANCH; return;
	59	case 0x2A: set_cond(cond_pl()); %BRANCH; return;
	60	case 0x2B: set_cond(!cond_pl()); %BRANCH; return;
	61	case 0x2C: set_cond(cond_ge()); %BRANCH; return;
	62	case 0x2D: set_cond(!cond_ge()); %BRANCH; return;
	63	case 0x2E: set_cond(cond_gt()); %BRANCH; return;
	64	case 0x2F: set_cond(!cond_gt()); %BRANCH; return;
	65
	66	case 0x30: set_regop16(m_x); %INDEXED; %LEA_xy; return;
	67	case 0x31: set_regop16(m_y); %INDEXED; %LEA_xy; return;
	68	case 0x32: set_regop16(m_s); %INDEXED; %LEA_us; return;
	69	case 0x33: set_regop16(m_u); %INDEXED; %LEA_us; return;
	70	case 0x34: %PSHS; return;
	71	case 0x35: %PULS; return;
	72	case 0x36: %PSHU; return;
	73	case 0x37: %PULU; return;
	74	case 0x39: %RTS; return;
	75	case 0x3A: %ABX; return;
	76	case 0x3B: %RTI; return;
	77	case 0x3C: %CWAI; return;
	78	case 0x3D: %MUL; return;
	79	case 0x3F: %SWI; return;
	80
	81	case 0x40: case 0x41: set_a(); %NEG8; return;
	82	case 0x43: case 0x42: set_a(); %COM8; return;
	83	case 0x44: case 0x45: set_a(); %LSR8; return;
	84	case 0x46: set_a(); %ROR8; return;
	85	case 0x47: set_a(); %ASR8; return;
	86	case 0x48: set_a(); %ASL8; return;
	87	case 0x49: set_a(); %ROL8; return;
	88	case 0x4A: case 0x4B: set_a(); %DEC8; return;
	89	case 0x4C: set_a(); %INC8; return;
	90	case 0x4D: set_a(); %TST8; return;
	91	case 0x4E: set_a(); %JMP; return;
	92	case 0x4F: set_a(); %CLR8; return;
	93
	94	case 0x50: case 0x51: set_b(); %NEG8; return;
	95	case 0x53: case 0x52: set_b(); %COM8; return;
	96	case 0x54: case 0x55: set_b(); %LSR8; return;
	97	case 0x56: set_b(); %ROR8; return;
	98	case 0x57: set_b(); %ASR8; return;
	99	case 0x58: set_b(); %ASL8; return;
	100	case 0x59: set_b(); %ROL8; return;
	101	case 0x5A: case 0x5B: set_b(); %DEC8; return;
	102	case 0x5C: set_b(); %INC8; return;
	103	case 0x5D: set_b(); %TST8; return;
	104	case 0x5E: set_b(); %JMP; return;
	105	case 0x5F: set_b(); %CLR8; return;
	106
	107	case 0x60: case 0x61: %INDEXED; %NEG8; return;
	108	case 0x63: case 0x62: %INDEXED; %COM8; return;
	109	case 0x64: case 0x65: %INDEXED; %LSR8; return;
	110	case 0x66: %INDEXED; %ROR8; return;
	111	case 0x67: %INDEXED; %ASR8; return;
	112	case 0x68: %INDEXED; %ASL8; return;
	113	case 0x69: %INDEXED; %ROL8; return;
	114	case 0x6A: case 0x6B: %INDEXED; %DEC8; return;
	115	case 0x6C: %INDEXED; %INC8; return;
	116	case 0x6D: %INDEXED; %TST8; return;
	117	case 0x6E: %INDEXED; %JMP; return;
	118	case 0x6F: %INDEXED; %CLR8; return;
	119
	120	case 0x70: case 0x71: %EXTENDED; %NEG8; return;
	121	case 0x73: case 0x72: %EXTENDED; %COM8; return;
	122	case 0x74: case 0x75: %EXTENDED; %LSR8; return;
	123	case 0x76: %EXTENDED; %ROR8; return;
	124	case 0x77: %EXTENDED; %ASR8; return;
	125	case 0x78: %EXTENDED; %ASL8; return;
	126	case 0x79: %EXTENDED; %ROL8; return;
	127	case 0x7A: case 0x7B: %EXTENDED; %DEC8; return;
	128	case 0x7C: %EXTENDED; %INC8; return;
	129	case 0x7D: %EXTENDED; %TST8; return;
	130	case 0x7E: %EXTENDED; %JMP; return;
	131	case 0x7F: %EXTENDED; %CLR8; return;
	132
	133	case 0x80: set_regop8(m_d.b.h); set_imm(); %SUB8; return;
	134	case 0x81: set_regop8(m_d.b.h); set_imm(); %CMP8; return;
	135	case 0x82: set_regop8(m_d.b.h); set_imm(); %SBC8; return;
	136	case 0x83: set_regop16(m_d); set_imm(); %SUB16; return;
	137	case 0x84: set_regop8(m_d.b.h); set_imm(); %AND8; return;
	138	case 0x85: set_regop8(m_d.b.h); set_imm(); %BIT8; return;
	139	case 0x86: set_regop8(m_d.b.h); set_imm(); %LD8; return;
	140	case 0x87: set_regop8(m_d.b.h); set_imm(); %ST8; return;
	141	case 0x88: set_regop8(m_d.b.h); set_imm(); %EOR8; return;
	142	case 0x89: set_regop8(m_d.b.h); set_imm(); %ADC8; return;
	143	case 0x8A: set_regop8(m_d.b.h); set_imm(); %OR8; return;
	144	case 0x8B: set_regop8(m_d.b.h); set_imm(); %ADD8; return;
	145	case 0x8C: set_regop16(m_x); set_imm(); %CMP16; return;
	146	case 0x8D: %BSR; return;
	147	case 0x8E: set_regop16(m_x); set_imm(); %LD16; return;
	148	case 0x8F: set_regop16(m_x); set_imm(); %ST16; return;
	149
	150	case 0x90: set_regop8(m_d.b.h); %DIRECT; %SUB8; return;
	151	case 0x91: set_regop8(m_d.b.h); %DIRECT; %CMP8; return;
	152	case 0x92: set_regop8(m_d.b.h); %DIRECT; %SBC8; return;
	153	case 0x93: set_regop16(m_d); %DIRECT; %SUB16; return;
	154	case 0x94: set_regop8(m_d.b.h); %DIRECT; %AND8; return;
	155	case 0x95: set_regop8(m_d.b.h); %DIRECT; %BIT8; return;
	156	case 0x96: set_regop8(m_d.b.h); %DIRECT; %LD8; return;
	157	case 0x97: set_regop8(m_d.b.h); %DIRECT; %ST8; return;
	158	case 0x98: set_regop8(m_d.b.h); %DIRECT; %EOR8; return;
	159	case 0x99: set_regop8(m_d.b.h); %DIRECT; %ADC8; return;
	160	case 0x9A: set_regop8(m_d.b.h); %DIRECT; %OR8; return;
	161	case 0x9B: set_regop8(m_d.b.h); %DIRECT; %ADD8; return;
	162	case 0x9C: set_regop16(m_x); %DIRECT; %CMP16; return;
	163	case 0x9D: %DIRECT; %JSR; return;
	164	case 0x9E: set_regop16(m_x); %DIRECT; %LD16; return;
	165	case 0x9F: set_regop16(m_x); %DIRECT; %ST16; return;
	166
	167	case 0xA0: set_regop8(m_d.b.h); %INDEXED; %SUB8; return;
	168	case 0xA1: set_regop8(m_d.b.h); %INDEXED; %CMP8; return;
	169	case 0xA2: set_regop8(m_d.b.h); %INDEXED; %SBC8; return;
	170	case 0xA3: set_regop16(m_d); %INDEXED; %SUB16; return;
	171	case 0xA4: set_regop8(m_d.b.h); %INDEXED; %AND8; return;
	172	case 0xA5: set_regop8(m_d.b.h); %INDEXED; %BIT8; return;
	173	case 0xA6: set_regop8(m_d.b.h); %INDEXED; %LD8; return;
	174	case 0xA7: set_regop8(m_d.b.h); %INDEXED; %ST8; return;
	175	case 0xA8: set_regop8(m_d.b.h); %INDEXED; %EOR8; return;
	176	case 0xA9: set_regop8(m_d.b.h); %INDEXED; %ADC8; return;
	177	case 0xAA: set_regop8(m_d.b.h); %INDEXED; %OR8; return;
	178	case 0xAB: set_regop8(m_d.b.h); %INDEXED; %ADD8; return;
	179	case 0xAC: set_regop16(m_x); %INDEXED; %CMP16; return;
	180	case 0xAD: %INDEXED; %JSR; return;
	181	case 0xAE: set_regop16(m_x); %INDEXED; %LD16; return;
	182	case 0xAF: set_regop16(m_x); %INDEXED; %ST16; return;
	183
	184	case 0xB0: set_regop8(m_d.b.h); %EXTENDED; %SUB8; return;
	185	case 0xB1: set_regop8(m_d.b.h); %EXTENDED; %CMP8; return;
	186	case 0xB2: set_regop8(m_d.b.h); %EXTENDED; %SBC8; return;
	187	case 0xB3: set_regop16(m_d); %EXTENDED; %SUB16; return;
	188	case 0xB4: set_regop8(m_d.b.h); %EXTENDED; %AND8; return;
	189	case 0xB5: set_regop8(m_d.b.h); %EXTENDED; %BIT8; return;
	190	case 0xB6: set_regop8(m_d.b.h); %EXTENDED; %LD8; return;
	191	case 0xB7: set_regop8(m_d.b.h); %EXTENDED; %ST8; return;
	192	case 0xB8: set_regop8(m_d.b.h); %EXTENDED; %EOR8; return;
	193	case 0xB9: set_regop8(m_d.b.h); %EXTENDED; %ADC8; return;
	194	case 0xBA: set_regop8(m_d.b.h); %EXTENDED; %OR8; return;
	195	case 0xBB: set_regop8(m_d.b.h); %EXTENDED; %ADD8; return;
	196	case 0xBC: set_regop16(m_x); %EXTENDED; %CMP16; return;
	197	case 0xBD: %EXTENDED; %JSR; return;
	198	case 0xBE: set_regop16(m_x); %EXTENDED; %LD16; return;
	199	case 0xBF: set_regop16(m_x); %EXTENDED; %ST16; return;
	200
	201	case 0xC0: set_regop8(m_d.b.l); set_imm(); %SUB8; return;
	202	case 0xC1: set_regop8(m_d.b.l); set_imm(); %CMP8; return;
	203	case 0xC2: set_regop8(m_d.b.l); set_imm(); %SBC8; return;
	204	case 0xC3: set_regop16(m_d); set_imm(); %ADD16; return;
	205	case 0xC4: set_regop8(m_d.b.l); set_imm(); %AND8; return;
	206	case 0xC5: set_regop8(m_d.b.l); set_imm(); %BIT8; return;
	207	case 0xC6: set_regop8(m_d.b.l); set_imm(); %LD8; return;
	208	case 0xC7: set_regop8(m_d.b.l); set_imm(); %ST8; return;
	209	case 0xC8: set_regop8(m_d.b.l); set_imm(); %EOR8; return;
	210	case 0xC9: set_regop8(m_d.b.l); set_imm(); %ADC8; return;
	211	case 0xCA: set_regop8(m_d.b.l); set_imm(); %OR8; return;
	212	case 0xCB: set_regop8(m_d.b.l); set_imm(); %ADD8; return;
	213	case 0xCC: set_regop16(m_d); set_imm(); %LD16; return;
	214	case 0xCD: set_regop16(m_d); set_imm(); %ST16; return;
	215	case 0xCE: set_regop16(m_u); set_imm(); %LD16; return;
	216	case 0xCF: set_regop16(m_u); set_imm(); %ST16; return;
	217
	218	case 0xD0: set_regop8(m_d.b.l); %DIRECT; %SUB8; return;
	219	case 0xD1: set_regop8(m_d.b.l); %DIRECT; %CMP8; return;
	220	case 0xD2: set_regop8(m_d.b.l); %DIRECT; %SBC8; return;
	221	case 0xD3: set_regop16(m_d); %DIRECT; %ADD16; return;
	222	case 0xD4: set_regop8(m_d.b.l); %DIRECT; %AND8; return;
	223	case 0xD5: set_regop8(m_d.b.l); %DIRECT; %BIT8; return;
	224	case 0xD6: set_regop8(m_d.b.l); %DIRECT; %LD8; return;
	225	case 0xD7: set_regop8(m_d.b.l); %DIRECT; %ST8; return;
	226	case 0xD8: set_regop8(m_d.b.l); %DIRECT; %EOR8; return;
	227	case 0xD9: set_regop8(m_d.b.l); %DIRECT; %ADC8; return;
	228	case 0xDA: set_regop8(m_d.b.l); %DIRECT; %OR8; return;
	229	case 0xDB: set_regop8(m_d.b.l); %DIRECT; %ADD8; return;
	230	case 0xDC: set_regop16(m_d); %DIRECT; %LD16; return;
	231	case 0xDD: set_regop16(m_d); %DIRECT; %ST16; return;
	232	case 0xDE: set_regop16(m_u); %DIRECT; %LD16; return;
	233	case 0xDF: set_regop16(m_u); %DIRECT; %ST16; return;
	234
	235	case 0xE0: set_regop8(m_d.b.l); %INDEXED; %SUB8; return;
	236	case 0xE1: set_regop8(m_d.b.l); %INDEXED; %CMP8; return;
	237	case 0xE2: set_regop8(m_d.b.l); %INDEXED; %SBC8; return;
	238	case 0xE3: set_regop16(m_d); %INDEXED; %ADD16; return;
	239	case 0xE4: set_regop8(m_d.b.l); %INDEXED; %AND8; return;
	240	case 0xE5: set_regop8(m_d.b.l); %INDEXED; %BIT8; return;
	241	case 0xE6: set_regop8(m_d.b.l); %INDEXED; %LD8; return;
	242	case 0xE7: set_regop8(m_d.b.l); %INDEXED; %ST8; return;
	243	case 0xE8: set_regop8(m_d.b.l); %INDEXED; %EOR8; return;
	244	case 0xE9: set_regop8(m_d.b.l); %INDEXED; %ADC8; return;
	245	case 0xEA: set_regop8(m_d.b.l); %INDEXED; %OR8; return;
	246	case 0xEB: set_regop8(m_d.b.l); %INDEXED; %ADD8; return;
	247	case 0xEC: set_regop16(m_d); %INDEXED; %LD16; return;
	248	case 0xED: set_regop16(m_d); %INDEXED; %ST16; return;
	249	case 0xEE: set_regop16(m_u); %INDEXED; %LD16; return;
	250	case 0xEF: set_regop16(m_u); %INDEXED; %ST16; return;
	251
	252	case 0xF0: set_regop8(m_d.b.l); %EXTENDED; %SUB8; return;
	253	case 0xF1: set_regop8(m_d.b.l); %EXTENDED; %CMP8; return;
	254	case 0xF2: set_regop8(m_d.b.l); %EXTENDED; %SBC8; return;
	255	case 0xF3: set_regop16(m_d); %EXTENDED; %ADD16; return;
	256	case 0xF4: set_regop8(m_d.b.l); %EXTENDED; %AND8; return;
	257	case 0xF5: set_regop8(m_d.b.l); %EXTENDED; %BIT8; return;
	258	case 0xF6: set_regop8(m_d.b.l); %EXTENDED; %LD8; return;
	259	case 0xF7: set_regop8(m_d.b.l); %EXTENDED; %ST8; return;
	260	case 0xF8: set_regop8(m_d.b.l); %EXTENDED; %EOR8; return;
	261	case 0xF9: set_regop8(m_d.b.l); %EXTENDED; %ADC8; return;
	262	case 0xFA: set_regop8(m_d.b.l); %EXTENDED; %OR8; return;
	263	case 0xFB: set_regop8(m_d.b.l); %EXTENDED; %ADD8; return;
	264	case 0xFC: set_regop16(m_d); %EXTENDED; %LD16; return;
	265	case 0xFD: set_regop16(m_d); %EXTENDED; %ST16; return;
	266	case 0xFE: set_regop16(m_u); %EXTENDED; %LD16; return;
	267	case 0xFF: set_regop16(m_u); %EXTENDED; %ST16; return;
	268	default: %ILLEGAL; return;
	269	}
	270	return;
	271
	272	DISPATCH10:
	273	@m_opcode = read_opcode();
	274	switch(m_opcode)
	275	{
	276	case 0x20: set_cond(true); %LBRANCH; return;
	277	case 0x21: set_cond(false); %LBRANCH; return;
	278	case 0x22: set_cond(cond_hi()); %LBRANCH; return;
	279	case 0x23: set_cond(!cond_hi()); %LBRANCH; return;
	280	case 0x24: set_cond(cond_cc()); %LBRANCH; return;
	281	case 0x25: set_cond(!cond_cc()); %LBRANCH; return;
	282	case 0x26: set_cond(cond_ne()); %LBRANCH; return;
	283	case 0x27: set_cond(!cond_ne()); %LBRANCH; return;
	284	case 0x28: set_cond(cond_vc()); %LBRANCH; return;
	285	case 0x29: set_cond(!cond_vc()); %LBRANCH; return;
	286	case 0x2A: set_cond(cond_pl()); %LBRANCH; return;
	287	case 0x2B: set_cond(!cond_pl()); %LBRANCH; return;
	288	case 0x2C: set_cond(cond_ge()); %LBRANCH; return;
	289	case 0x2D: set_cond(!cond_ge()); %LBRANCH; return;
	290	case 0x2E: set_cond(cond_gt()); %LBRANCH; return;
	291	case 0x2F: set_cond(!cond_gt()); %LBRANCH; return;
	292
	293	case 0x3F: %SWI2; return;
	294
	295	case 0x83: set_regop16(m_d); set_imm(); %CMP16; return;
	296	case 0x8C: set_regop16(m_y); set_imm(); %CMP16; return;
	297	case 0x8E: set_regop16(m_y); set_imm(); %LD16; return;
	298	case 0x8F: set_regop16(m_y); set_imm(); %ST16; return;
	299	case 0x93: set_regop16(m_d); %DIRECT; %CMP16; return;
	300	case 0x9C: set_regop16(m_y); %DIRECT; %CMP16; return;
	301	case 0x9E: set_regop16(m_y); %DIRECT; %LD16; return;
	302	case 0x9F: set_regop16(m_y); %DIRECT; %ST16; return;
	303	case 0xA3: set_regop16(m_d); %INDEXED; %CMP16; return;
	304	case 0xAC: set_regop16(m_y); %INDEXED; %CMP16; return;
	305	case 0xAE: set_regop16(m_y); %INDEXED; %LD16; return;
	306	case 0xAF: set_regop16(m_y); %INDEXED; %ST16; return;
	307	case 0xB3: set_regop16(m_d); %EXTENDED; %CMP16; return;
	308	case 0xBC: set_regop16(m_y); %EXTENDED; %CMP16; return;
	309	case 0xBE: set_regop16(m_y); %EXTENDED; %LD16; return;
	310	case 0xBF: set_regop16(m_y); %EXTENDED; %ST16; return;
	311
	312	case 0xCE: set_regop16(m_s); set_imm(); %LD16; return;
	313	case 0xCF: set_regop16(m_s); set_imm(); %ST16; return;
	314	case 0xDE: set_regop16(m_s); %DIRECT; %LD16; return;
	315	case 0xDF: set_regop16(m_s); %DIRECT; %ST16; return;
	316	case 0xEE: set_regop16(m_s); %INDEXED; %LD16; return;
	317	case 0xEF: set_regop16(m_s); %INDEXED; %ST16; return;
	318	case 0xFE: set_regop16(m_s); %EXTENDED; %LD16; return;
	319	case 0xFF: set_regop16(m_s); %EXTENDED; %ST16; return;
	320
	321	default: %ILLEGAL; return;
	322	}
	323	return;
	324
	325	DISPATCH11:
	326	@m_opcode = read_opcode();
	327	switch(m_opcode)
	328	{
	329	case 0x3F: %SWI3; return;
	330	case 0x83: set_regop16(m_u); set_imm(); %CMP16; return;
	331	case 0x8C: set_regop16(m_s); set_imm(); %CMP16; return;
	332	case 0x93: set_regop16(m_u); %DIRECT; %CMP16; return;
	333	case 0x9C: set_regop16(m_s); %DIRECT; %CMP16; return;
	334	case 0xA3: set_regop16(m_u); %INDEXED; %CMP16; return;
	335	case 0xAC: set_regop16(m_s); %INDEXED; %CMP16; return;
	336	case 0xB3: set_regop16(m_u); %EXTENDED; %CMP16; return;
	337	case 0xBC: set_regop16(m_s); %EXTENDED; %CMP16; return;
	338
	339	default: %ILLEGAL; return;
	340	}
	341	return;
	342
	343	#include "base6x09.ops"
	344
	345	PUSH_REGISTERS:
	346	if (m_temp.w & 0x80)
	347	{
	348	@write_memory(--regop16().w, m_pc.b.l);
	349	@write_memory(--regop16().w, m_pc.b.h);
	350	nop();
	351	}
	352	if (m_temp.w & 0x40)
	353	{
	354	@write_memory(--regop16().w, (&regop16() == &m_s) ? m_u.b.l : m_s.b.l);
	355	@write_memory(--regop16().w, (&regop16() == &m_s) ? m_u.b.h : m_s.b.h);
	356	nop();
	357	}
	358	if (m_temp.w & 0x20)
	359	{
	360	@write_memory(--regop16().w, m_y.b.l);
	361	@write_memory(--regop16().w, m_y.b.h);
	362	nop();
	363	}
	364	if (m_temp.w & 0x10)
	365	{
	366	@write_memory(--regop16().w, m_x.b.l);
	367	@write_memory(--regop16().w, m_x.b.h);
	368	nop();
	369	}
	370	if (m_temp.w & 0x08)
	371	{
	372	@write_memory(--regop16().w, m_dp);
	373	nop();
	374	}
	375	if (m_temp.w & 0x04)
	376	{
	377	@write_memory(--regop16().w, m_d.b.l);
	378	nop();
	379	}
	380	if (m_temp.w & 0x02)
	381	{
	382	@write_memory(--regop16().w, m_d.b.h);
	383	nop();
	384	}
	385	if (m_temp.w & 0x01)
	386	{
	387	@write_memory(--regop16().w, m_cc);
	388	nop();
	389	}
	390	return;
	391
	392	PULL_REGISTERS:
	393	if (m_temp.w & 0x01)
	394	{
	395	@m_cc = read_memory(regop16().w++);
	396	nop();
	397	}
	398	if (m_temp.w & 0x02)
	399	{
	400	@m_d.b.h = read_memory(regop16().w++);
	401	nop();
	402	}
	403	if (m_temp.w & 0x04)
	404	{
	405	@m_d.b.l = read_memory(regop16().w++);
	406	nop();
	407	}
	408	if (m_temp.w & 0x08)
	409	{
	410	@m_dp = read_memory(regop16().w++);
	411	nop();
	412	}
	413	if (m_temp.w & 0x10)
	414	{
	415	@m_x.b.h = read_memory(regop16().w++);
	416	@m_x.b.l = read_memory(regop16().w++);
	417	nop();
	418	}
	419	if (m_temp.w & 0x20)
	420	{
	421	@m_y.b.h = read_memory(regop16().w++);
	422	@m_y.b.l = read_memory(regop16().w++);
	423	nop();
	424	}
	425	if (m_temp.w & 0x40)
	426	{
	427	@(&regop16() == &m_s ? m_u : m_s).b.h = read_memory(regop16().w++);
	428	@(&regop16() == &m_s ? m_u : m_s).b.l = read_memory(regop16().w++);
	429	nop();
	430	}
	431	if (m_temp.w & 0x80)
	432	{
	433	@m_pc.b.h = read_memory(regop16().w++);
	434	@m_pc.b.l = read_memory(regop16().w++);
	435	nop();
	436	}
	437	@eat(1);
	438	return;
	439
	440	INDEXED:
	441	@m_opcode = read_opcode_arg();
	442	if (m_opcode & 0x80)
	443	{
	444	switch(m_opcode & 0x7F)
	445	{
	446	case 0x00: case 0x20: case 0x40: case 0x60:
	447	case 0x10: case 0x30: case 0x50: case 0x70:
	448	m_temp.w = ireg();
	449	ireg()++;
	450	eat(3);
	451	break;
	452
	453	case 0x01: case 0x21: case 0x41: case 0x61:
	454	case 0x11: case 0x31: case 0x51: case 0x71:
	455	m_temp.w = ireg();
	456	ireg() += 2;
	457	eat(4);
	458	break;
	459
	460	case 0x02: case 0x22: case 0x42: case 0x62:
	461	case 0x12: case 0x32: case 0x52: case 0x72:
	462	ireg()--;
	463	m_temp.w = ireg();
	464	eat(3);
	465	break;
	466
	467	case 0x03: case 0x23: case 0x43: case 0x63:
	468	case 0x13: case 0x33: case 0x53: case 0x73:
	469	ireg() -= 2;
	470	m_temp.w = ireg();
	471	eat(4);
	472	break;
	473
	474	case 0x04: case 0x24: case 0x44: case 0x64:
	475	case 0x14: case 0x34: case 0x54: case 0x74:
	476	m_temp.w = ireg();
	477	eat(1);
	478	break;
	479
	480	case 0x05: case 0x25: case 0x45: case 0x65:
	481	case 0x15: case 0x35: case 0x55: case 0x75:
	482	m_temp.w = ireg() + (INT8) m_d.b.l;
	483	eat(2);
	484	break;
	485
	486	case 0x06: case 0x26: case 0x46: case 0x66:
	487	case 0x16: case 0x36: case 0x56: case 0x76:
	488	m_temp.w = ireg() + (INT8) m_d.b.h;
	489	eat(2);
	490	break;
	491
	492	case 0x08: case 0x28: case 0x48: case 0x68:
	493	case 0x18: case 0x38: case 0x58: case 0x78:
	494	@m_temp.w = ireg() + (INT8) read_opcode_arg();
	495	eat(1);
	496	break;
	497
	498	case 0x09: case 0x29: case 0x49: case 0x69:
	499	case 0x19: case 0x39: case 0x59: case 0x79:
	500	@m_temp.b.h = read_opcode_arg();
	501	@m_temp.b.l = read_opcode_arg();
	502	m_temp.w = ireg() + m_temp.w;
	503	eat(3);
	504	break;
	505
	506	case 0x0B: case 0x2B: case 0x4B: case 0x6B:
	507	case 0x1B: case 0x3B: case 0x5B: case 0x7B:
	508	m_temp.w = ireg() + m_d.w;
	509	eat(5);
	510	break;
	511
	512	case 0x0C: case 0x2C: case 0x4C: case 0x6C:
	513	case 0x1C: case 0x3C: case 0x5C: case 0x7C:
	514	@m_temp.b.l = read_opcode_arg();
	515	m_temp.w = m_pc.w + (INT8) m_temp.b.l;
	516	eat(1);
	517	break;
	518
	519	case 0x0D: case 0x2D: case 0x4D: case 0x6D:
	520	case 0x1D: case 0x3D: case 0x5D: case 0x7D:
	521	@m_temp.b.h = read_opcode_arg();
	522	@m_temp.b.l = read_opcode_arg();
	523	m_temp.w = m_pc.w + (INT16) m_temp.w;
	524	eat(4);
	525	break;
	526
	527	case 0x0F: case 0x2F: case 0x4F: case 0x6F:
	528	case 0x1F: case 0x3F: case 0x5F: case 0x7F:
	529	@m_temp.b.h = read_opcode_arg();
	530	@m_temp.b.l = read_opcode_arg();
	531	eat(1);
	532	break;
	533
	534	default:
	535	m_temp.w = 0x0000;
	536	break;
	537	}
	538
	539	// indirect mode
	540	if (m_opcode & 0x10)
	541	{
	542	set_ea(m_temp.w);
	543	@m_temp.b.h = read_operand(0);
	544	@m_temp.b.l = read_operand(1);
	545	eat(1);
	546	}
	547	}
	548	else
	549	{
	550	// 5-bit offset
	551	m_temp.w = ireg() + (INT8) ((m_opcode & 0x0F) \| (m_opcode & 0x10 ? 0xF0 : 0x00));
	552	eat(2);
	553	}
	554	@set_ea(m_temp.w);
	555	return;
	556
	557	ILLEGAL:
	558	log_illegal();
	559	return;

Property changes on: trunk/src/emu/cpu/m6809/m6809.ops
Added: svn:eol-style + native Added: svn:mime-type + text/plain

trunk/src/emu/cpu/m6809/m6809.c
r21564	r21565
19	19	machine must be twos complement
20	20
21	21	History:
	22
	23	March 2013 NPW:
	24	Rewrite of 6809/6309/Konami CPU; attempted to make cycle exact.
	25
22	26	991026 HJB:
23	27	Fixed missing calls to cpu_changepc() for the TFR and EXG ocpodes.
24	28	Replaced m6809_slapstic checks by a macro (CHANGE_PC). ESB still
r21564	r21565
73	77	#include "emu.h"
74	78	#include "debugger.h"
75	79	#include "m6809.h"
	80	#include "m6809inl.h"
76	81
77		#define VERBOSE 0
78	82
79		#define LOG(x) do { if (VERBOSE) logerror x; } while (0)
	83	//**************************************************************************
	84	// PARAMETERS
	85	//**************************************************************************
80	86
81		/* flag bits in the cc register */
82		#define CC_C 0x01 /* Carry */
83		#define CC_V 0x02 /* Overflow */
84		#define CC_Z 0x04 /* Zero */
85		#define CC_N 0x08 /* Negative */
86		#define CC_II 0x10 /* Inhibit IRQ */
87		#define CC_H 0x20 /* Half (auxiliary) carry */
88		#define CC_IF 0x40 /* Inhibit FIRQ */
89		#define CC_E 0x80 /* entire state pushed */
	87	#define LOG_INTERRUPTS 1
90	88
91		#define pPPC m_ppc
92		#define pPC m_pc
93		#define pU m_u
94		#define pS m_s
95		#define pX m_x
96		#define pY m_y
97		#define pD m_d
98
99		#define PPC m_ppc.w.l
100		#define PC m_pc.w.l
101		#define PCD m_pc.d
102		#define U m_u.w.l
103		#define UD m_u.d
104		#define S m_s.w.l
105		#define SD m_s.d
106		#define X m_x.w.l
107		#define XD m_x.d
108		#define Y m_y.w.l
109		#define YD m_y.d
110		#define D m_d.w.l
111		#define A m_d.b.h
112		#define B m_d.b.l
113		#define DP m_dp.b.h
114		#define DPD m_dp.d
115		#define CC m_cc
116
117		#define EA m_ea.w.l
118		#define EAD m_ea.d
119		#define EAP m_ea
120
121		#define M6809_CWAI 8 /* set when CWAI is waiting for an interrupt */
122		#define M6809_SYNC 16 /* set when SYNC is waiting for an interrupt */
123		#define M6809_LDS 32 /* set when LDS occurred at least once */
124
125
126		/****************************************************************************/
127		/* Read a byte from given memory location */
128		/****************************************************************************/
129		#define RM(addr) ((unsigned)m_program->read_byte(addr))
130
131		/****************************************************************************/
132		/* Write a byte to given memory location */
133		/****************************************************************************/
134		#define WM(Addr,Value) (m_program->write_byte(Addr,Value))
135
136		/**************************************************************************/
137		/* ROP() is identical to RM16() except it is used for reading opcodes. In */
138		/* the case of a system with memory mapped I/O, this function can be used */
139		/* to greatly speed up emulation. */
140		/**************************************************************************/
141		#define ROP(Addr) ((unsigned)m_direct->read_decrypted_byte(Addr))
142
143		/************************************************************************/
144		/* ROP_ARG() is identical to ROP() except it is used for reading opcode */
145		/* arguments. This difference can be used to support systems that use */
146		/* different encoding mechanisms for opcodes and opcode arguments. */
147		/************************************************************************/
148		#define ROP_ARG(addr) ((unsigned)m_direct->read_raw_byte(addr))
149
150		/* macros to access memory */
151		#define IMMBYTE(b) b = ROP_ARG(PCD); PC++
152		#define IMMWORD(w) w.d = (ROP_ARG(PCD)<<8) \| ROP_ARG((PCD+1)&0xffff); PC+=2
153
154		#define PUSHBYTE(b) --S; WM(SD,b)
155		#define PUSHWORD(w) --S; WM(SD,w.b.l); --S; WM(SD,w.b.h)
156		#define PULLBYTE(b) b = RM(SD); S++
157		#define PULLWORD(w) w = RM(SD)<<8; S++; w \|= RM(SD); S++
158
159		#define PSHUBYTE(b) --U; WM(UD,b);
160		#define PSHUWORD(w) --U; WM(UD,w.b.l); --U; WM(UD,w.b.h)
161		#define PULUBYTE(b) b = RM(UD); U++
162		#define PULUWORD(w) w = RM(UD)<<8; U++; w \|= RM(UD); U++
163
164		#define CLR_HNZVC CC&=~(CC_H\|CC_N\|CC_Z\|CC_V\|CC_C)
165		#define CLR_NZV CC&=~(CC_N\|CC_Z\|CC_V)
166		#define CLR_NZ CC&=~(CC_N\|CC_Z)
167		#define CLR_HNZC CC&=~(CC_H\|CC_N\|CC_Z\|CC_C)
168		#define CLR_NZVC CC&=~(CC_N\|CC_Z\|CC_V\|CC_C)
169		#define CLR_Z CC&=~(CC_Z)
170		#define CLR_NZC CC&=~(CC_N\|CC_Z\|CC_C)
171		#define CLR_ZC CC&=~(CC_Z\|CC_C)
172
173		/* macros for CC -- CC bits affected should be reset before calling */
174		#define SET_Z(a) if(!a)SEZ
175		#define SET_Z8(a) SET_Z((UINT8)a)
176		#define SET_Z16(a) SET_Z((UINT16)a)
177		#define SET_N8(a) CC\|=((a&0x80)>>4)
178		#define SET_N16(a) CC\|=((a&0x8000)>>12)
179		#define SET_H(a,b,r) CC\|=(((a^b^r)&0x10)<<1)
180		#define SET_C8(a) CC\|=((a&0x100)>>8)
181		#define SET_C16(a) CC\|=((a&0x10000)>>16)
182		#define SET_V8(a,b,r) CC\|=(((a^b^r^(r>>1))&0x80)>>6)
183		#define SET_V16(a,b,r) CC\|=(((a^b^r^(r>>1))&0x8000)>>14)
184
185		#define SET_FLAGS8I(a) {CC\|=m_flags8i[(a)&0xff];}
186		#define SET_FLAGS8D(a) {CC\|=m_flags8d[(a)&0xff];}
187
188		/* combos */
189		#define SET_NZ8(a) {SET_N8(a);SET_Z(a);}
190		#define SET_NZ16(a) {SET_N16(a);SET_Z(a);}
191		#define SET_FLAGS8(a,b,r) {SET_N8(r);SET_Z8(r);SET_V8(a,b,r);SET_C8(r);}
192		#define SET_FLAGS16(a,b,r) {SET_N16(r);SET_Z16(r);SET_V16(a,b,r);SET_C16(r);}
193
194		#define NXORV ((CC&CC_N)^((CC&CC_V)<<2))
195
196		/* for treating an unsigned byte as a signed word */
197		#define SIGNED(b) ((UINT16)(b&0x80?b\|0xff00:b))
198
199		/* macros for addressing modes (postbytes have their own code) */
200		#define DIRECT EAD = DPD; IMMBYTE(m_ea.b.l)
201		#define IMM8 EAD = PCD; PC++
202		#define IMM16 EAD = PCD; PC+=2
203		#define EXTENDED IMMWORD(EAP)
204
205		/* macros to set status flags */
206		#if defined(SEC)
207		#undef SEC
	89	// turn off 'unreferenced label' errors
	90	#ifdef __GNUC__
	91	#pragma GCC diagnostic ignored "-Wunused-label"
208	92	#endif
209		#define SEC CC\|=CC_C
210		#define CLC CC&=~CC_C
211		#define SEZ CC\|=CC_Z
212		#define CLZ CC&=~CC_Z
213		#define SEN CC\|=CC_N
214		#define CLN CC&=~CC_N
215		#define SEV CC\|=CC_V
216		#define CLV CC&=~CC_V
217		#define SEH CC\|=CC_H
218		#define CLH CC&=~CC_H
	93	#ifdef _MSC_VER
	94	#pragma warning( disable : 4102 )
	95	#endif
219	96
220		/* macros for convenience */
221		#define DIRBYTE(b) {DIRECT;b=RM(EAD);}
222		#define DIRWORD(w) {DIRECT;w.d=RM16(EAD);}
223		#define EXTBYTE(b) {EXTENDED;b=RM(EAD);}
224		#define EXTWORD(w) {EXTENDED;w.d=RM16(EAD);}
	97	//**************************************************************************
	98	// DEVICE INTERFACE
	99	//**************************************************************************
225	100
226		/* macros for branch instructions */
227		#define BRANCH(f) { \
228		UINT8 t; \
229		IMMBYTE(t); \
230		if( f ) \
231		{ \
232		PC += SIGNED(t); \
233		} \
234		}
	101	const device_type M6809 = &device_creator<m6809_device>;
	102	const device_type M6809E = &device_creator<m6809e_device>;
235	103
236		#define LBRANCH(f) { \
237		PAIR t; \
238		IMMWORD(t); \
239		if( f ) \
240		{ \
241		m_icount -= 1; \
242		PC += t.w.l; \
243		} \
244		}
245	104
246		/* macros for setting/getting registers in TFR/EXG instructions */
	105	//-------------------------------------------------
	106	// m6809_base_device - constructor
	107	//-------------------------------------------------
247	108
248		UINT32 m6809_base_device::RM16(UINT32 addr)
	109	m6809_base_device::m6809_base_device(const machine_config &mconfig, const char name, const char tag, device_t *owner, UINT32 clock, const device_type type, int divider)
	110	: cpu_device(mconfig, type, name, tag, owner, clock),
	111	m_program_config("program", ENDIANNESS_BIG, 8, 16),
	112	m_clock_divider(divider)
249	113	{
250		UINT32 result = RM(addr) << 8;
251		return result \| RM((addr+1)&0xffff);
252	114	}
253	115
254		void m6809_base_device::WM16(UINT32 addr, PAIR *p)
255		{
256		WM(addr, p->b.h);
257		WM((addr+1)&0xffff, p->b.l);
258		}
259	116
260		void m6809_base_device::update_state()
261		{
262		/* compatibility with 6309 */
263		}
264
265		void m6809_base_device::check_irq_lines()
266		{
267		if( m_irq_state[M6809_IRQ_LINE] != CLEAR_LINE \|\|
268		m_irq_state[M6809_FIRQ_LINE] != CLEAR_LINE )
269		m_int_state &= ~M6809_SYNC; /* clear SYNC flag */
270		if( m_irq_state[M6809_FIRQ_LINE]!=CLEAR_LINE && !(CC & CC_IF) )
271		{
272		/* fast IRQ */
273		/* HJB 990225: state already saved by CWAI? */
274		if( m_int_state & M6809_CWAI )
275		{
276		m_int_state &= ~M6809_CWAI; /* clear CWAI */
277		m_extra_cycles += 7; /* subtract +7 cycles */
278		}
279		else
280		{
281		CC &= ~CC_E; /* save 'short' state */
282		PUSHWORD(pPC);
283		PUSHBYTE(CC);
284		m_extra_cycles += 10; /* subtract +10 cycles */
285		}
286		CC \|= CC_IF \| CC_II; /* inhibit FIRQ and IRQ */
287		PCD=RM16(0xfff6);
288		standard_irq_callback(M6809_FIRQ_LINE);
289		}
290		else
291		if( m_irq_state[M6809_IRQ_LINE]!=CLEAR_LINE && !(CC & CC_II) )
292		{
293		/* standard IRQ */
294		/* HJB 990225: state already saved by CWAI? */
295		if( m_int_state & M6809_CWAI )
296		{
297		m_int_state &= ~M6809_CWAI; /* clear CWAI flag */
298		m_extra_cycles += 7; /* subtract +7 cycles */
299		}
300		else
301		{
302		CC \|= CC_E; /* save entire state */
303		PUSHWORD(pPC);
304		PUSHWORD(pU);
305		PUSHWORD(pY);
306		PUSHWORD(pX);
307		PUSHBYTE(DP);
308		PUSHBYTE(B);
309		PUSHBYTE(A);
310		PUSHBYTE(CC);
311		m_extra_cycles += 19; /* subtract +19 cycles */
312		}
313		CC \|= CC_II; /* inhibit IRQ */
314		PCD=RM16(0xfff8);
315		standard_irq_callback(M6809_IRQ_LINE);
316		}
317		}
318
319
320	117	//-------------------------------------------------
321	118	// static_set_config - set the configuration
322	119	// structure
r21564	r21565
329	126	static_set_static_config(device, &config);
330	127	}
331	128
332		//**************************************************************************
333		// DEVICE INTERFACE
334		//**************************************************************************
335	129
336		const device_type M6809 = &device_creator<m6809_device>;
337		const device_type M6809E = &device_creator<m6809e_device>;
338
339	130	//-------------------------------------------------
340		// ~~m6809_base_~~device - cons~~tru~~ctor
	131	// device_start - device-specific startup
341	132	//-------------------------------------------------
342	133
343		m6809_base_device::m6809_base_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock, const device_type type, int divider)
344		: cpu_device(mconfig, type, "M6809", tag, owner, clock),
345		m_program_config("program", ENDIANNESS_BIG, 8, 16),
346		m_clock_divider(divider)
347		{
348		// build the opcode table
349		for (int op = 0; op < 256; op++)
350		m_opcode[op] = s_opcodetable[op];
351		}
352
353
354		//**************************************************************************
355		// STATIC OPCODE TABLES
356		//**************************************************************************
357
358		const m6809_base_device::ophandler m6809_base_device::s_opcodetable[256] =
359		{
360		// 0xX0/4/8/C, 0xX1/5/9/D, 0xX2/6/A/E, 0xX3/7/B/F
361
362		/* 0x0X */ &m6809_base_device::neg_di, &m6809_base_device::neg_di, &m6809_base_device::com_di, &m6809_base_device::com_di,
363		&m6809_base_device::lsr_di, &m6809_base_device::lsr_di, &m6809_base_device::ror_di, &m6809_base_device::asr_di,
364		&m6809_base_device::asl_di, &m6809_base_device::rol_di, &m6809_base_device::dec_di, &m6809_base_device::dec_di,
365		&m6809_base_device::inc_di, &m6809_base_device::tst_di, &m6809_base_device::jmp_di, &m6809_base_device::clr_di,
366
367		/* 0x1X */ &m6809_base_device::pref10, &m6809_base_device::pref11, &m6809_base_device::nop, &m6809_base_device::sync,
368		&m6809_base_device::illegal,&m6809_base_device::illegal,&m6809_base_device::lbra, &m6809_base_device::lbsr,
369		&m6809_base_device::illegal,&m6809_base_device::daa, &m6809_base_device::orcc, &m6809_base_device::illegal,
370		&m6809_base_device::andcc, &m6809_base_device::sex, &m6809_base_device::exg, &m6809_base_device::tfr,
371
372		/* 0x2X */ &m6809_base_device::bra, &m6809_base_device::brn, &m6809_base_device::bhi, &m6809_base_device::bls,
373		&m6809_base_device::bcc, &m6809_base_device::bcs, &m6809_base_device::bne, &m6809_base_device::beq,
374		&m6809_base_device::bvc, &m6809_base_device::bvs, &m6809_base_device::bpl, &m6809_base_device::bmi,
375		&m6809_base_device::bge, &m6809_base_device::blt, &m6809_base_device::bgt, &m6809_base_device::ble,
376
377		/* 0x3X */ &m6809_base_device::leax, &m6809_base_device::leay, &m6809_base_device::leas, &m6809_base_device::leau,
378		&m6809_base_device::pshs, &m6809_base_device::puls, &m6809_base_device::pshu, &m6809_base_device::pulu,
379		&m6809_base_device::illegal,&m6809_base_device::rts, &m6809_base_device::abx, &m6809_base_device::rti,
380		&m6809_base_device::cwai, &m6809_base_device::mul, &m6809_base_device::illegal,&m6809_base_device::swi,
381
382		/* 0x4X */ &m6809_base_device::nega, &m6809_base_device::nega, &m6809_base_device::coma, &m6809_base_device::coma,
383		&m6809_base_device::lsra, &m6809_base_device::lsra, &m6809_base_device::rora, &m6809_base_device::asra,
384		&m6809_base_device::asla, &m6809_base_device::rola, &m6809_base_device::deca, &m6809_base_device::deca,
385		&m6809_base_device::inca, &m6809_base_device::tsta, &m6809_base_device::clra, &m6809_base_device::clra,
386
387		/* 0x5X */ &m6809_base_device::negb, &m6809_base_device::negb, &m6809_base_device::comb, &m6809_base_device::comb,
388		&m6809_base_device::lsrb, &m6809_base_device::lsrb, &m6809_base_device::rorb, &m6809_base_device::asrb,
389		&m6809_base_device::aslb, &m6809_base_device::rolb, &m6809_base_device::decb, &m6809_base_device::decb,
390		&m6809_base_device::incb, &m6809_base_device::tstb, &m6809_base_device::clrb, &m6809_base_device::clrb,
391
392		/* 0x6X */ &m6809_base_device::neg_ix, &m6809_base_device::neg_ix, &m6809_base_device::com_ix, &m6809_base_device::com_ix,
393		&m6809_base_device::lsr_ix, &m6809_base_device::lsr_ix, &m6809_base_device::ror_ix, &m6809_base_device::asr_ix,
394		&m6809_base_device::asl_ix, &m6809_base_device::rol_ix, &m6809_base_device::dec_ix, &m6809_base_device::dec_ix,
395		&m6809_base_device::inc_ix, &m6809_base_device::tst_ix, &m6809_base_device::jmp_ix, &m6809_base_device::clr_ix,
396
397		/* 0x7X */ &m6809_base_device::neg_ex, &m6809_base_device::neg_ex, &m6809_base_device::com_ex, &m6809_base_device::com_ex,
398		&m6809_base_device::lsr_ex, &m6809_base_device::lsr_ex, &m6809_base_device::ror_ex, &m6809_base_device::asr_ex,
399		&m6809_base_device::asl_ex, &m6809_base_device::rol_ex, &m6809_base_device::dec_ex, &m6809_base_device::dec_ex,
400		&m6809_base_device::inc_ex, &m6809_base_device::tst_ex, &m6809_base_device::jmp_ex, &m6809_base_device::clr_ex,
401
402		/* 0x8X */ &m6809_base_device::suba_im,&m6809_base_device::cmpa_im,&m6809_base_device::sbca_im,&m6809_base_device::subd_im,
403		&m6809_base_device::anda_im,&m6809_base_device::bita_im,&m6809_base_device::lda_im, &m6809_base_device::sta_im,
404		&m6809_base_device::eora_im,&m6809_base_device::adca_im,&m6809_base_device::ora_im, &m6809_base_device::adda_im,
405		&m6809_base_device::cmpx_im,&m6809_base_device::bsr, &m6809_base_device::ldx_im, &m6809_base_device::stx_im,
406
407		/* 0x9X */ &m6809_base_device::suba_di,&m6809_base_device::cmpa_di,&m6809_base_device::sbca_di,&m6809_base_device::subd_di,
408		&m6809_base_device::anda_di,&m6809_base_device::bita_di,&m6809_base_device::lda_di, &m6809_base_device::sta_di,
409		&m6809_base_device::eora_di,&m6809_base_device::adca_di,&m6809_base_device::ora_di, &m6809_base_device::adda_di,
410		&m6809_base_device::cmpx_di,&m6809_base_device::jsr_di, &m6809_base_device::ldx_di, &m6809_base_device::stx_di,
411
412		/* 0xAX */ &m6809_base_device::suba_ix,&m6809_base_device::cmpa_ix,&m6809_base_device::sbca_ix,&m6809_base_device::subd_ix,
413		&m6809_base_device::anda_ix,&m6809_base_device::bita_ix,&m6809_base_device::lda_ix, &m6809_base_device::sta_ix,
414		&m6809_base_device::eora_ix,&m6809_base_device::adca_ix,&m6809_base_device::ora_ix, &m6809_base_device::adda_ix,
415		&m6809_base_device::cmpx_ix,&m6809_base_device::jsr_ix, &m6809_base_device::ldx_ix, &m6809_base_device::stx_ix,
416
417		/* 0xBX */ &m6809_base_device::suba_ex,&m6809_base_device::cmpa_ex,&m6809_base_device::sbca_ex,&m6809_base_device::subd_ex,
418		&m6809_base_device::anda_ex,&m6809_base_device::bita_ex,&m6809_base_device::lda_ex, &m6809_base_device::sta_ex,
419		&m6809_base_device::eora_ex,&m6809_base_device::adca_ex,&m6809_base_device::ora_ex, &m6809_base_device::adda_ex,
420		&m6809_base_device::cmpx_ex,&m6809_base_device::jsr_ex, &m6809_base_device::ldx_ex, &m6809_base_device::stx_ex,
421
422		/* 0xCX */ &m6809_base_device::subb_im,&m6809_base_device::cmpb_im,&m6809_base_device::sbcb_im,&m6809_base_device::addd_im,
423		&m6809_base_device::andb_im,&m6809_base_device::bitb_im,&m6809_base_device::ldb_im, &m6809_base_device::stb_im,
424		&m6809_base_device::eorb_im,&m6809_base_device::adcb_im,&m6809_base_device::orb_im, &m6809_base_device::addb_im,
425		&m6809_base_device::ldd_im, &m6809_base_device::std_im, &m6809_base_device::ldu_im, &m6809_base_device::stu_im,
426
427		/* 0xDX */ &m6809_base_device::subb_di,&m6809_base_device::cmpb_di,&m6809_base_device::sbcb_di,&m6809_base_device::addd_di,
428		&m6809_base_device::andb_di,&m6809_base_device::bitb_di,&m6809_base_device::ldb_di, &m6809_base_device::stb_di,
429		&m6809_base_device::eorb_di,&m6809_base_device::adcb_di,&m6809_base_device::orb_di, &m6809_base_device::addb_di,
430		&m6809_base_device::ldd_di, &m6809_base_device::std_di, &m6809_base_device::ldu_di, &m6809_base_device::stu_di,
431
432		/* 0xEX */ &m6809_base_device::subb_ix,&m6809_base_device::cmpb_ix,&m6809_base_device::sbcb_ix,&m6809_base_device::addd_ix,
433		&m6809_base_device::andb_ix,&m6809_base_device::bitb_ix,&m6809_base_device::ldb_ix, &m6809_base_device::stb_ix,
434		&m6809_base_device::eorb_ix,&m6809_base_device::adcb_ix,&m6809_base_device::orb_ix, &m6809_base_device::addb_ix,
435		&m6809_base_device::ldd_ix, &m6809_base_device::std_ix, &m6809_base_device::ldu_ix, &m6809_base_device::stu_ix,
436
437		/* 0xFX */ &m6809_base_device::subb_ex,&m6809_base_device::cmpb_ex,&m6809_base_device::sbcb_ex,&m6809_base_device::addd_ex,
438		&m6809_base_device::andb_ex,&m6809_base_device::bitb_ex,&m6809_base_device::ldb_ex, &m6809_base_device::stb_ex,
439		&m6809_base_device::eorb_ex,&m6809_base_device::adcb_ex,&m6809_base_device::orb_ex, &m6809_base_device::addb_ex,
440		&m6809_base_device::ldd_ex, &m6809_base_device::std_ex, &m6809_base_device::ldu_ex, &m6809_base_device::stu_ex
441		};
442
443
444		/****************************************************************************/
445		/* Reset registers to their initial values */
446		/****************************************************************************/
447	134	void m6809_base_device::device_start()
448	135	{
449		/* default configuration */
	136	// default configuration
450	137	static const m6809_config default_config =
451	138	{
452	139	false
r21564	r21565
462	149
463	150	// register our state for the debugger
464	151	astring tempstr;
465		state_add(STATE_GENPC, "GENPC", m_pc.w.l).noshow();
	152	state_add(STATE_GENPC, "GENPC", m_pc.w).noshow();
	153	state_add(STATE_GENPCBASE, "GENPCBASE", m_ppc.w).noshow();
466	154	state_add(STATE_GENFLAGS, "GENFLAGS", m_cc).callimport().callexport().formatstr("%8s").noshow();
467		state_add(M6809_PC, "PC", m_pc.w.l).mask(0xffff);
468		state_add(M6809_S, "S", m_s.w.l).mask(0xffff);
	155	state_add(M6809_PC, "PC", m_pc.w).mask(0xffff);
	156	state_add(M6809_S, "S", m_s.w).mask(0xffff);
469	157	state_add(M6809_CC, "CC", m_cc).mask(0xff);
470		state_add(M6809_U, "U", m_u.w.l).mask(0xffff);
471		state_add(M6809_A, "A", m_d.b.h).mask(0xff);
472		state_add(M6809_B, "B", m_d.b.l).mask(0xff);
473		state_add(M6809_X, "X", m_x.w.l).mask(0xffff);
474		state_add(M6809_Y, "Y", m_y.w.l).mask(0xffff);
475		state_add(M6809_DP, "DP", m_dp.w.l).mask(0xffff);
476
	158	state_add(M6809_U, "U", m_u.w).mask(0xffff);
	159	state_add(M6809_A, "A", m_d.b.h).mask(0xff);
	160	state_add(M6809_B, "B", m_d.b.l).mask(0xff);
	161	state_add(M6809_X, "X", m_x.w).mask(0xffff);
	162	state_add(M6809_Y, "Y", m_y.w).mask(0xffff);
	163	state_add(M6809_DP, "DP", m_dp).mask(0xff);
	164
477	165	// initialize variables
478	166	m_cc = 0;
479		m_pc.d = 0;
480		m_s.d = 0;
481		m_u.d = 0;
482		m_d.d = 0;
483		m_x.d = 0;
484		m_y.d = 0;
485		m_dp.d = 0;
	167	m_pc.w = 0;
	168	m_s.w = 0;
	169	m_u.w = 0;
	170	m_d.w = 0;
	171	m_x.w = 0;
	172	m_y.w = 0;
	173	m_dp = 0;
	174	m_reg = 0;
	175	m_reg8 = NULL;
	176	m_reg16 = NULL;
486	177
487	178	// setup regtable
488		save_item(NAME(PC));
489		save_item(NAME(PPC));
490		save_item(NAME(D));
491		save_item(NAME(DP));
492		save_item(NAME(U));
493		save_item(NAME(S));
494		save_item(NAME(X));
495		save_item(NAME(Y));
496		save_item(NAME(CC));
497		save_item(NAME(m_irq_state));
498		save_item(NAME(m_int_state));
499		save_item(NAME(m_nmi_state));
	179	save_item(NAME(m_pc.w));
	180	save_item(NAME(m_ppc.w));
	181	save_item(NAME(m_d.w));
	182	save_item(NAME(m_dp));
	183	save_item(NAME(m_u.w));
	184	save_item(NAME(m_s.w));
	185	save_item(NAME(m_x.w));
	186	save_item(NAME(m_y.w));
	187	save_item(NAME(m_cc));
	188	save_item(NAME(m_nmi_asserted));
	189	save_item(NAME(m_nmi_line));
	190	save_item(NAME(m_firq_line));
	191	save_item(NAME(m_irq_line));
	192	save_item(NAME(m_lds_encountered));
	193	save_item(NAME(m_state));
	194	save_item(NAME(m_ea.w));
	195	save_item(NAME(m_addressing_mode));
	196	save_item(NAME(m_reg));
	197	save_item(NAME(m_cond));
500	198
501	199	// set our instruction counter
502	200	m_icountptr = &m_icount;
503	201	m_icount = 0;
504		m_extra_cycles = 0;
505	202	}
506	203
507		/****************************************************************************/
508		/* Reset registers to their initial values */
509		/****************************************************************************/
	204
	205
	206	//-------------------------------------------------
	207	// device_reset - device-specific reset
	208	//-------------------------------------------------
	209
510	210	void m6809_base_device::device_reset()
511	211	{
512		m_int_state = 0;
513		m_nmi_state = CLEAR_LINE;
514		m_irq_state[0] = CLEAR_LINE;
515		m_irq_state[1] = CLEAR_LINE;
	212	m_nmi_line = false;
	213	m_nmi_asserted = false;
	214	m_firq_line = false;
	215	m_irq_line = false;
	216	m_lds_encountered = false;
516	217
517		~~DPD~~ = 0; /* Reset direct page register */
	218	m_dp = 0x00; // reset direct page register
518	219
519		CC \|= CC_II; /* IRQ disabled */
520		CC \|= CC_IF; /* FIRQ disabled */
	220	m_cc \|= CC_I; // IRQ disabled
	221	m_cc \|= CC_F; // FIRQ disabled
521	222
522		PCD = RM16(0xfffe);
523		update_state();
	223	m_pc.b.h = m_direct->read_decrypted_byte(VECTOR_RESET_FFFE + 0);
	224	m_pc.b.l = m_direct->read_decrypted_byte(VECTOR_RESET_FFFE + 1);
	225
	226	// reset sub-instruction state
	227	reset_state();
524	228	}
525	229
526	230
	231
527	232	//-------------------------------------------------
	233	// device_pre_save - device-specific pre-save
	234	//-------------------------------------------------
	235
	236	void m6809_base_device::device_pre_save()
	237	{
	238	if (m_reg8 == &m_d.b.h)
	239	m_reg = M6809_A;
	240	else if (m_reg8 == &m_d.b.l)
	241	m_reg = M6809_B;
	242	else if (m_reg16 == &m_d)
	243	m_reg = M6809_D;
	244	else if (m_reg16 == &m_x)
	245	m_reg = M6809_X;
	246	else if (m_reg16 == &m_y)
	247	m_reg = M6809_Y;
	248	else if (m_reg16 == &m_u)
	249	m_reg = M6809_U;
	250	else if (m_reg16 == &m_s)
	251	m_reg = M6809_S;
	252	else
	253	m_reg = 0;
	254	}
	255
	256
	257	//-------------------------------------------------
	258	// device_post_load - device-specific post-load
	259	//-------------------------------------------------
	260
	261	void m6809_base_device::device_post_load()
	262	{
	263	m_reg8 = NULL;
	264	m_reg16 = NULL;
	265
	266	switch(m_reg)
	267	{
	268	case M6809_A:
	269	set_regop8(m_d.b.h);
	270	break;
	271	case M6809_B:
	272	set_regop8(m_d.b.h);
	273	break;
	274	case M6809_D:
	275	set_regop16(m_d);
	276	break;
	277	case M6809_X:
	278	set_regop16(m_x);
	279	break;
	280	case M6809_Y:
	281	set_regop16(m_y);
	282	break;
	283	case M6809_U:
	284	set_regop16(m_u);
	285	break;
	286	case M6809_S:
	287	set_regop16(m_s);
	288	break;
	289	}
	290	}
	291
	292
	293	//-------------------------------------------------
528	294	// memory_space_config - return the configuration
529	295	// of the specified address space, or NULL if
530	296	// the space doesn't exist
r21564	r21565
593	359
594	360	offs_t m6809_base_device::disasm_disassemble(char buffer, offs_t pc, const UINT8 oprom, const UINT8 *opram, UINT32 options)
595	361	{
596		extern CPU_DISASSEMBLE( m6809 );
597		return disassemble(buffer, pc, oprom, opram, 0);
	362	extern offs_t m6809_disassemble(char buffer, offs_t pc, const UINT8 oprom, const UINT8 opram, int options, m6809_base_device m6809);
	363	return m6809_disassemble(buffer, pc, oprom, opram, options, this);
598	364	}
599	365
600	366
601	367	//**************************************************************************
602		// IRQ HANDLING
603		//**************************************************************************
604
605		void m6809_base_device::set_irq_line(int irqline, int state)
606		{
607		if (irqline == INPUT_LINE_NMI)
608		{
609		if (m_nmi_state == state) return;
610		m_nmi_state = state;
611		LOG(("M6809 '%s' set_irq_line (NMI) %d\n", m_tag, state));
612		if( state == CLEAR_LINE ) return;
613
614		/* if the stack was not yet initialized */
615		if( !(m_int_state & M6809_LDS) ) return;
616
617		m_int_state &= ~M6809_SYNC;
618		/* HJB 990225: state already saved by CWAI? */
619		if( m_int_state & M6809_CWAI )
620		{
621		m_int_state &= ~M6809_CWAI;
622		m_extra_cycles += 7; /* subtract +7 cycles next time */
623		}
624		else
625		{
626		CC \|= CC_E; /* save entire state */
627		PUSHWORD(pPC);
628		PUSHWORD(pU);
629		PUSHWORD(pY);
630		PUSHWORD(pX);
631		PUSHBYTE(DP);
632		PUSHBYTE(B);
633		PUSHBYTE(A);
634		PUSHBYTE(CC);
635		m_extra_cycles += 19; /* subtract +19 cycles next time */
636		}
637		CC \|= CC_IF \| CC_II; /* inhibit FIRQ and IRQ */
638		PCD = RM16(0xfffc);
639		}
640		else if (irqline < 2)
641		{
642		LOG(("M6809 '%s' set_irq_line %d, %d\n", m_tag, irqline, state));
643		m_irq_state[irqline] = state;
644		if (state == CLEAR_LINE) return;
645		check_irq_lines();
646		}
647		}
648
649		/****************************************************************************
650		* includes the actual opcode implementations
651		****************************************************************************/
652		#include "6809tbl.c"
653
654		#include "6809ops.c"
655
656		//**************************************************************************
657	368	// CORE EXECUTION LOOP
658	369	//**************************************************************************
659	370
r21564	r21565
686	397
687	398	UINT32 m6809_base_device::execute_min_cycles() const
688	399	{
689		return 2;
	400	return 1;
690	401	}
691	402
692	403
r21564	r21565
719	430
720	431	void m6809_base_device::execute_set_input(int inputnum, int state)
721	432	{
	433	if (LOG_INTERRUPTS)
	434	logerror("%s: inputnum=%s state=%d totalcycles=%d\n", machine().describe_context(), inputnum_string(inputnum), state, (int) attotime_to_clocks(machine().time()));
	435
722	436	switch(inputnum)
723	437	{
	438	case INPUT_LINE_NMI:
	439	// NMI is edge triggered
	440	m_nmi_asserted = m_nmi_asserted \|\| ((state != CLEAR_LINE) && !m_nmi_line && m_lds_encountered);
	441	m_nmi_line = (state != CLEAR_LINE);
	442	break;
	443
724	444	case M6809_FIRQ_LINE:
725		set_irq_line(M6809_FIRQ_LINE, state);
	445	// FIRQ is line triggered
	446	m_firq_line = (state != CLEAR_LINE);
726	447	break;
	448
727	449	case M6809_IRQ_LINE:
728		set_irq_line(M6809_IRQ_LINE, state);
	450	// IRQ is line triggered
	451	m_irq_line = (state != CLEAR_LINE);
729	452	break;
730		case INPUT_LINE_NMI:
731		set_irq_line(INPUT_LINE_NMI, state);
732		break;
733	453	}
734	454	}
735	455
736	456
737	457	//-------------------------------------------------
738		// execute_run - execute a timeslice's worth of
739		// opcodes
	458	// inputnum_string
740	459	//-------------------------------------------------
741	460
742		void m6809_base_device::~~exec~~ute_run()
	461	const char *m6809_base_device::inputnum_string(int inputnum)
743	462	{
744		m_icount -= m_extra_cycles;
745		m_extra_cycles = 0;
746
747		check_irq_lines();
748
749		if (m_int_state & (M6809_CWAI \| M6809_SYNC))
	463	switch(inputnum)
750	464	{
751		debugger_instruction_hook(this, PCD);
752		m_icount = 0;
	465	case INPUT_LINE_NMI: return "NMI";
	466	case M6809_FIRQ_LINE: return "FIRQ";
	467	case M6809_IRQ_LINE: return "IRQ";
	468	default: return "???";
753	469	}
754		else
755		{
756		do
757		{
758		pPPC = pPC;
	470	}
759	471
760		debugger_instruction_hook(this, PCD);
761	472
762		m_ireg = ROP(PCD);
763		PC++;
764		(this->*m_opcode[m_ireg])();
765		m_icount -= m_cycles1[m_ireg];
	473	//-------------------------------------------------
	474	// log_illegal - used to log hits to illegal
	475	// instructions (except for HD6309 which traps)
	476	//-------------------------------------------------
766	477
767		} while( m_icount > 0 );
768
769		m_icount -= m_extra_cycles;
770		m_extra_cycles = 0;
771		}
	478	void m6809_base_device::log_illegal()
	479	{
	480	logerror("%s: illegal opcode at %04x\n", machine().describe_context(), (unsigned) m_pc.w);
772	481	}
773	482
774		void m6809_base_device::fetch_effective_address()
775		{
776		UINT8 postbyte = ROP_ARG(PCD);
777		PC++;
778	483
779		switch(postbyte)
	484	//-------------------------------------------------
	485	// execute_one - try to execute a single instruction
	486	//-------------------------------------------------
	487
	488	ATTR_FORCE_INLINE void m6809_base_device::execute_one()
	489	{
	490	switch(pop_state())
780	491	{
781		case 0x00: EA=X; break;
782		case 0x01: EA=X+1; break;
783		case 0x02: EA=X+2; break;
784		case 0x03: EA=X+3; break;
785		case 0x04: EA=X+4; break;
786		case 0x05: EA=X+5; break;
787		case 0x06: EA=X+6; break;
788		case 0x07: EA=X+7; break;
789		case 0x08: EA=X+8; break;
790		case 0x09: EA=X+9; break;
791		case 0x0a: EA=X+10; break;
792		case 0x0b: EA=X+11; break;
793		case 0x0c: EA=X+12; break;
794		case 0x0d: EA=X+13; break;
795		case 0x0e: EA=X+14; break;
796		case 0x0f: EA=X+15; break;
	492	#include "cpu/m6809/m6809.inc"
	493	}
	494	}
797	495
798		case 0x10: EA=X-16; break;
799		case 0x11: EA=X-15; break;
800		case 0x12: EA=X-14; break;
801		case 0x13: EA=X-13; break;
802		case 0x14: EA=X-12; break;
803		case 0x15: EA=X-11; break;
804		case 0x16: EA=X-10; break;
805		case 0x17: EA=X-9; break;
806		case 0x18: EA=X-8; break;
807		case 0x19: EA=X-7; break;
808		case 0x1a: EA=X-6; break;
809		case 0x1b: EA=X-5; break;
810		case 0x1c: EA=X-4; break;
811		case 0x1d: EA=X-3; break;
812		case 0x1e: EA=X-2; break;
813		case 0x1f: EA=X-1; break;
814	496
815		case 0x20: EA=Y; break;
816		case 0x21: EA=Y+1; break;
817		case 0x22: EA=Y+2; break;
818		case 0x23: EA=Y+3; break;
819		case 0x24: EA=Y+4; break;
820		case 0x25: EA=Y+5; break;
821		case 0x26: EA=Y+6; break;
822		case 0x27: EA=Y+7; break;
823		case 0x28: EA=Y+8; break;
824		case 0x29: EA=Y+9; break;
825		case 0x2a: EA=Y+10; break;
826		case 0x2b: EA=Y+11; break;
827		case 0x2c: EA=Y+12; break;
828		case 0x2d: EA=Y+13; break;
829		case 0x2e: EA=Y+14; break;
830		case 0x2f: EA=Y+15; break;
	497	//-------------------------------------------------
	498	// execute_run - execute a timeslice's worth of
	499	// opcodes
	500	//-------------------------------------------------
831	501
832		case 0x30: EA=Y-16; break;
833		case 0x31: EA=Y-15; break;
834		case 0x32: EA=Y-14; break;
835		case 0x33: EA=Y-13; break;
836		case 0x34: EA=Y-12; break;
837		case 0x35: EA=Y-11; break;
838		case 0x36: EA=Y-10; break;
839		case 0x37: EA=Y-9; break;
840		case 0x38: EA=Y-8; break;
841		case 0x39: EA=Y-7; break;
842		case 0x3a: EA=Y-6; break;
843		case 0x3b: EA=Y-5; break;
844		case 0x3c: EA=Y-4; break;
845		case 0x3d: EA=Y-3; break;
846		case 0x3e: EA=Y-2; break;
847		case 0x3f: EA=Y-1; break;
	502	void m6809_base_device::execute_run()
	503	{
	504	do
	505	{
	506	execute_one();
	507	} while(m_icount > 0);
	508	}
848	509
849		case 0x40: EA=U; break;
850		case 0x41: EA=U+1; break;
851		case 0x42: EA=U+2; break;
852		case 0x43: EA=U+3; break;
853		case 0x44: EA=U+4; break;
854		case 0x45: EA=U+5; break;
855		case 0x46: EA=U+6; break;
856		case 0x47: EA=U+7; break;
857		case 0x48: EA=U+8; break;
858		case 0x49: EA=U+9; break;
859		case 0x4a: EA=U+10; break;
860		case 0x4b: EA=U+11; break;
861		case 0x4c: EA=U+12; break;
862		case 0x4d: EA=U+13; break;
863		case 0x4e: EA=U+14; break;
864		case 0x4f: EA=U+15; break;
865	510
866		case 0x50: EA=U-16; break;
867		case 0x51: EA=U-15; break;
868		case 0x52: EA=U-14; break;
869		case 0x53: EA=U-13; break;
870		case 0x54: EA=U-12; break;
871		case 0x55: EA=U-11; break;
872		case 0x56: EA=U-10; break;
873		case 0x57: EA=U-9; break;
874		case 0x58: EA=U-8; break;
875		case 0x59: EA=U-7; break;
876		case 0x5a: EA=U-6; break;
877		case 0x5b: EA=U-5; break;
878		case 0x5c: EA=U-4; break;
879		case 0x5d: EA=U-3; break;
880		case 0x5e: EA=U-2; break;
881		case 0x5f: EA=U-1; break;
882	511
883		case 0x60: EA=S; break;
884		case 0x61: EA=S+1; break;
885		case 0x62: EA=S+2; break;
886		case 0x63: EA=S+3; break;
887		case 0x64: EA=S+4; break;
888		case 0x65: EA=S+5; break;
889		case 0x66: EA=S+6; break;
890		case 0x67: EA=S+7; break;
891		case 0x68: EA=S+8; break;
892		case 0x69: EA=S+9; break;
893		case 0x6a: EA=S+10; break;
894		case 0x6b: EA=S+11; break;
895		case 0x6c: EA=S+12; break;
896		case 0x6d: EA=S+13; break;
897		case 0x6e: EA=S+14; break;
898		case 0x6f: EA=S+15; break;
	512	//-------------------------------------------------
	513	// m6809_device
	514	//-------------------------------------------------
899	515
900		case 0x70: EA=S-16; break;
901		case 0x71: EA=S-15; break;
902		case 0x72: EA=S-14; break;
903		case 0x73: EA=S-13; break;
904		case 0x74: EA=S-12; break;
905		case 0x75: EA=S-11; break;
906		case 0x76: EA=S-10; break;
907		case 0x77: EA=S-9; break;
908		case 0x78: EA=S-8; break;
909		case 0x79: EA=S-7; break;
910		case 0x7a: EA=S-6; break;
911		case 0x7b: EA=S-5; break;
912		case 0x7c: EA=S-4; break;
913		case 0x7d: EA=S-3; break;
914		case 0x7e: EA=S-2; break;
915		case 0x7f: EA=S-1; break;
	516	m6809_device::m6809_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
	517	: m6809_base_device(mconfig, "M6809", tag, owner, clock, M6809, 1)
	518	{
	519	}
916	520
917		case 0x80: EA=X; X++; break;
918		case 0x81: EA=X; X+=2; break;
919		case 0x82: X--; EA=X; break;
920		case 0x83: X-=2; EA=X; break;
921		case 0x84: EA=X; break;
922		case 0x85: EA=X+SIGNED(B); break;
923		case 0x86: EA=X+SIGNED(A); break;
924		case 0x87: EA=0; break; /* ILLEGAL*/
925		case 0x88: IMMBYTE(EA); EA=X+SIGNED(EA); break;
926		case 0x89: IMMWORD(EAP); EA+=X; break;
927		case 0x8a: EA=0; break; /* IIError*/
928		case 0x8b: EA=X+D; break;
929		case 0x8c: IMMBYTE(EA); EA=PC+SIGNED(EA); break;
930		case 0x8d: IMMWORD(EAP); EA+=PC; break;
931		case 0x8e: EA=0; break; /* ILLEGAL*/
932		case 0x8f: IMMWORD(EAP); break;
933	521
934		case 0x90: EA=X; X++; EAD=RM16(EAD); break; /* Indirect ,R+ not in my specs */
935		case 0x91: EA=X; X+=2; EAD=RM16(EAD); break;
936		case 0x92: X--; EA=X; EAD=RM16(EAD); break;
937		case 0x93: X-=2; EA=X; EAD=RM16(EAD); break;
938		case 0x94: EA=X; EAD=RM16(EAD); break;
939		case 0x95: EA=X+SIGNED(B); EAD=RM16(EAD); break;
940		case 0x96: EA=X+SIGNED(A); EAD=RM16(EAD); break;
941		case 0x97: EA=0; break; /* ILLEGAL*/
942		case 0x98: IMMBYTE(EA); EA=X+SIGNED(EA); EAD=RM16(EAD); break;
943		case 0x99: IMMWORD(EAP); EA+=X; EAD=RM16(EAD); break;
944		case 0x9a: EA=0; break; /* ILLEGAL*/
945		case 0x9b: EA=X+D; EAD=RM16(EAD); break;
946		case 0x9c: IMMBYTE(EA); EA=PC+SIGNED(EA); EAD=RM16(EAD); break;
947		case 0x9d: IMMWORD(EAP); EA+=PC; EAD=RM16(EAD); break;
948		case 0x9e: EA=0; break; /* ILLEGAL*/
949		case 0x9f: IMMWORD(EAP); EAD=RM16(EAD); break;
950	522
951		case 0xa0: EA=Y; Y++; break;
952		case 0xa1: EA=Y; Y+=2; break;
953		case 0xa2: Y--; EA=Y; break;
954		case 0xa3: Y-=2; EA=Y; break;
955		case 0xa4: EA=Y; break;
956		case 0xa5: EA=Y+SIGNED(B); break;
957		case 0xa6: EA=Y+SIGNED(A); break;
958		case 0xa7: EA=0; break; /* ILLEGAL*/
959		case 0xa8: IMMBYTE(EA); EA=Y+SIGNED(EA); break;
960		case 0xa9: IMMWORD(EAP); EA+=Y; break;
961		case 0xaa: EA=0; break; /* ILLEGAL*/
962		case 0xab: EA=Y+D; break;
963		case 0xac: IMMBYTE(EA); EA=PC+SIGNED(EA); break;
964		case 0xad: IMMWORD(EAP); EA+=PC; break;
965		case 0xae: EA=0; break; /* ILLEGAL*/
966		case 0xaf: IMMWORD(EAP); break;
	523	//-------------------------------------------------
	524	// m6809e_device
	525	//-------------------------------------------------
967	526
968		case 0xb0: EA=Y; Y++; EAD=RM16(EAD); break;
969		case 0xb1: EA=Y; Y+=2; EAD=RM16(EAD); break;
970		case 0xb2: Y--; EA=Y; EAD=RM16(EAD); break;
971		case 0xb3: Y-=2; EA=Y; EAD=RM16(EAD); break;
972		case 0xb4: EA=Y; EAD=RM16(EAD); break;
973		case 0xb5: EA=Y+SIGNED(B); EAD=RM16(EAD); break;
974		case 0xb6: EA=Y+SIGNED(A); EAD=RM16(EAD); break;
975		case 0xb7: EA=0; break; /* ILLEGAL*/
976		case 0xb8: IMMBYTE(EA); EA=Y+SIGNED(EA); EAD=RM16(EAD); break;
977		case 0xb9: IMMWORD(EAP); EA+=Y; EAD=RM16(EAD); break;
978		case 0xba: EA=0; break; /* ILLEGAL*/
979		case 0xbb: EA=Y+D; EAD=RM16(EAD); break;
980		case 0xbc: IMMBYTE(EA); EA=PC+SIGNED(EA); EAD=RM16(EAD); break;
981		case 0xbd: IMMWORD(EAP); EA+=PC; EAD=RM16(EAD); break;
982		case 0xbe: EA=0; break; /* ILLEGAL*/
983		case 0xbf: IMMWORD(EAP); EAD=RM16(EAD); break;
984
985		case 0xc0: EA=U; U++; break;
986		case 0xc1: EA=U; U+=2; break;
987		case 0xc2: U--; EA=U; break;
988		case 0xc3: U-=2; EA=U; break;
989		case 0xc4: EA=U; break;
990		case 0xc5: EA=U+SIGNED(B); break;
991		case 0xc6: EA=U+SIGNED(A); break;
992		case 0xc7: EA=0; break; /ILLEGAL/
993		case 0xc8: IMMBYTE(EA); EA=U+SIGNED(EA); break;
994		case 0xc9: IMMWORD(EAP); EA+=U; break;
995		case 0xca: EA=0; break; /ILLEGAL/
996		case 0xcb: EA=U+D; break;
997		case 0xcc: IMMBYTE(EA); EA=PC+SIGNED(EA); break;
998		case 0xcd: IMMWORD(EAP); EA+=PC; break;
999		case 0xce: EA=0; break; /ILLEGAL/
1000		case 0xcf: IMMWORD(EAP); break;
1001
1002		case 0xd0: EA=U; U++; EAD=RM16(EAD); break;
1003		case 0xd1: EA=U; U+=2; EAD=RM16(EAD); break;
1004		case 0xd2: U--; EA=U; EAD=RM16(EAD); break;
1005		case 0xd3: U-=2; EA=U; EAD=RM16(EAD); break;
1006		case 0xd4: EA=U; EAD=RM16(EAD); break;
1007		case 0xd5: EA=U+SIGNED(B); EAD=RM16(EAD); break;
1008		case 0xd6: EA=U+SIGNED(A); EAD=RM16(EAD); break;
1009		case 0xd7: EA=0; break; /ILLEGAL/
1010		case 0xd8: IMMBYTE(EA); EA=U+SIGNED(EA); EAD=RM16(EAD); break;
1011		case 0xd9: IMMWORD(EAP); EA+=U; EAD=RM16(EAD); break;
1012		case 0xda: EA=0; break; /ILLEGAL/
1013		case 0xdb: EA=U+D; EAD=RM16(EAD); break;
1014		case 0xdc: IMMBYTE(EA); EA=PC+SIGNED(EA); EAD=RM16(EAD); break;
1015		case 0xdd: IMMWORD(EAP); EA+=PC; EAD=RM16(EAD); break;
1016		case 0xde: EA=0; break; /ILLEGAL/
1017		case 0xdf: IMMWORD(EAP); EAD=RM16(EAD); break;
1018
1019		case 0xe0: EA=S; S++; break;
1020		case 0xe1: EA=S; S+=2; break;
1021		case 0xe2: S--; EA=S; break;
1022		case 0xe3: S-=2; EA=S; break;
1023		case 0xe4: EA=S; break;
1024		case 0xe5: EA=S+SIGNED(B); break;
1025		case 0xe6: EA=S+SIGNED(A); break;
1026		case 0xe7: EA=0; break; /ILLEGAL/
1027		case 0xe8: IMMBYTE(EA); EA=S+SIGNED(EA); break;
1028		case 0xe9: IMMWORD(EAP); EA+=S; break;
1029		case 0xea: EA=0; break; /ILLEGAL/
1030		case 0xeb: EA=S+D; break;
1031		case 0xec: IMMBYTE(EA); EA=PC+SIGNED(EA); break;
1032		case 0xed: IMMWORD(EAP); EA+=PC; break;
1033		case 0xee: EA=0; break; /ILLEGAL/
1034		case 0xef: IMMWORD(EAP); break;
1035
1036		case 0xf0: EA=S; S++; EAD=RM16(EAD); break;
1037		case 0xf1: EA=S; S+=2; EAD=RM16(EAD); break;
1038		case 0xf2: S--; EA=S; EAD=RM16(EAD); break;
1039		case 0xf3: S-=2; EA=S; EAD=RM16(EAD); break;
1040		case 0xf4: EA=S; EAD=RM16(EAD); break;
1041		case 0xf5: EA=S+SIGNED(B); EAD=RM16(EAD); break;
1042		case 0xf6: EA=S+SIGNED(A); EAD=RM16(EAD); break;
1043		case 0xf7: EA=0; break; /ILLEGAL/
1044		case 0xf8: IMMBYTE(EA); EA=S+SIGNED(EA); EAD=RM16(EAD); break;
1045		case 0xf9: IMMWORD(EAP); EA+=S; EAD=RM16(EAD); break;
1046		case 0xfa: EA=0; break; /ILLEGAL/
1047		case 0xfb: EA=S+D; EAD=RM16(EAD); break;
1048		case 0xfc: IMMBYTE(EA); EA=PC+SIGNED(EA); EAD=RM16(EAD); break;
1049		case 0xfd: IMMWORD(EAP); EA+=PC; EAD=RM16(EAD); break;
1050		case 0xfe: EA=0; break; /ILLEGAL/
1051		case 0xff: IMMWORD(EAP); EAD=RM16(EAD); break;
1052		}
1053		m_icount -= m_index_cycle_em[postbyte];
	527	m6809e_device::m6809e_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
	528	: m6809_base_device(mconfig, "M6809E", tag, owner, clock, M6809E, 4)
	529	{
1054	530	}

trunk/src/emu/cpu/m6809/knmidasm.c
r0	r21565
	1	#include "emu.h"
	2	#include "debugger.h"
	3	#include "konami.h"
	4
	5	#ifndef TRUE
	6	#define TRUE -1
	7	#define FALSE 0
	8	#endif
	9
	10	/*
	11
	12	0x08 leax indexed
	13	0x09 leay indexed (not confirmed)
	14	0x0a leau indexed
	15	0x0b leas indexed (not confirmed)
	16
	17	0x0c pushs xx
	18	0x0d pushu xx (not confirmed)
	19	0x0e pulls xx
	20	0x0f pulls xx (not confirmed)
	21
	22	0x10 lda xx
	23	0x11 ldb xx
	24	0x12 lda indexed
	25	0x13 ldb indexed
	26
	27	0x14 adda xx
	28	0x15 addb xx (not confirmed)
	29	0x16 adda indexed (not confirmed)
	30	0x17 addb indexed
	31
	32	0x18 adca xx
	33	0x19 adcb xx (not confirmed)
	34	0x1a adca indexed (not confirmed)
	35	0x1b adcb indexed (not confirmed)
	36
	37	0x1c suba xx
	38	0x1d subb xx
	39	0x1e suba indexed
	40	0x1f subb indexed
	41
	42	0x20 sbca xx
	43	0x21 sbcb xx
	44	0x22 sbca indexed
	45	0x23 sbcb indexed
	46
	47	0x24 anda xx
	48	0x25 andb xx
	49	0x26 anda indexed
	50	0x27 andb indexed
	51
	52	0x28 bita xx
	53	0x29 bitb xx
	54	0x2a bita indexed
	55	0x2b bitb indexed
	56
	57	0x2c eora xx
	58	0x2d eorb xx
	59	0x2e eora indexed
	60	0x2f eorb indexed
	61
	62	0x30 ora xx
	63	0x31 orb xx
	64	0x32 ora indexed
	65	0x33 orb indexed
	66
	67	0x34 cmpa xx
	68	0x35 cmpb xx
	69	0x36 cmpa indexed
	70	0x37 cmpb indexed
	71
	72	CUSTOM OPCODE: Set Address lines 16-23
	73	--------------------------------------
	74	0x38 setlines xx
	75	0x39 setlines indexed
	76
	77	The eight bits taken as parameter set address lines 16 to 23.
	78
	79
	80	0x3a sta indexed
	81	0x3b stb indexed
	82	0x3c andcc
	83	0x3d orcc
	84
	85	0x3e exg xx
	86	0x3f tfr xx
	87
	88	0x40 ldd xx xx
	89	0x41 ldd indexed
	90	0x42 ldx xx xx
	91	0x43 ldx indexed
	92	0x44 ldy xx xx
	93	0x45 ldy indexed (not confirmed)
	94	0x46 ldu xx xx
	95	0x47 ldu indexed
	96	0x48 lds xx xx
	97	0x49 lds indexed (not confirmed)
	98
	99	0x4a cmpd xx xx
	100	0x4b cmpd indexed
	101	0x4c cmpx xx xx
	102	0x4d cmpx indexed
	103	0x4e cmpy xx xx (not confirmed)
	104	0x4f cmpy indexed (not confirmed)
	105	0x50 cmpu xx xx (not confirmed)
	106	0x51 cmpu indexed (not confirmed)
	107	0x52 cmps xx xx (not confirmed)
	108	0x53 cmps indexed (not confirmed)
	109
	110	0x54 addd xx xx
	111	0x55 addd indexed (not confirmed)
	112	0x56 subd xx xx
	113	0x57 subd indexed (not confirmed)
	114
	115	0x58 std indexed
	116	0x59 stx indexed
	117	0x5a sty indexed
	118	0x5b stu indexed
	119	0x5c sts indexed (not confirmed)
	120
	121
	122	BRANCH OPCODE TABLE :
	123	---------------------
	124
	125	Opcode M6809 Konami
	126	BRA 20 60
	127	BRN 21 70
	128	BHI 22 61
	129	BLS 23 71
	130	BCC 24 62
	131	BCS 25 72
	132	BNE 26 63
	133	BEQ 27 73
	134	BVC 28 64
	135	BVS 29 74
	136	BPL 2a 65
	137	BMI 2b 75
	138	BGE 2c 66
	139	BLT 2d 76
	140	BGT 2e 67
	141	BLE 2f 77
	142
	143	Long versions of the branchs are the number + 8.
	144
	145	0x80 clra
	146	0x81 clrb
	147	0x82 clr indexed
	148
	149	0x83 coma
	150	0x84 comb
	151	0x85 com indexed
	152
	153	0x86 nega (not confirmed)
	154	0x87 negb (not confirmed)
	155	0x88 neg indexed (not confirmed)
	156
	157	0x89 inca
	158	0x8a incb (not confirmed)
	159	0x8b inc indexed
	160
	161	0x8c deca
	162	0x8d decb
	163	0x8e dec indexed
	164
	165	0x8f rts
	166
	167	0x90 tsta (not confirmed)
	168	0x91 tstb (not confirmed)
	169	0x92 tst indexed (not confirmed)
	170
	171	0x93 lsra
	172	0x94 lsrb
	173	0x95 lsr indexed
	174
	175	0x96 rora
	176	0x97 rorb
	177	0x98 ror indexed
	178
	179	0x99 asra
	180	0x9a asrb
	181	0x9b asr indexed
	182
	183	0x9c asla
	184	0x9d aslb
	185	0x9e asl indexed
	186
	187	0x9f rti
	188
	189	0xa0 rola
	190	0xa1 rolb
	191	0xa2 rol indexed
	192
	193	0xa3 lsrw indexed ( not confirmed )
	194	0xa4 rorw indexed ( not confirmed )
	195	0xa5 asrw indexed ( not confirmed )
	196	0xa6 aslw indexed ( not confirmed )
	197	0xa7 rolw indexed ( not confirmed )
	198
	199	0xa8 jmp indexed
	200	0xa9 jsr indexed
	201	0xaa bsr xx
	202	0xab lbsr xx xx
	203	0xac decb,jnz xx
	204	0xad decx,jnz xx
	205	0xae nop
	206
	207	0xb0 abx
	208	0xb1 daa
	209	0xb2 sex
	210
	211	0xb3 mul
	212
	213	0xb4 lmul x:y = x * y
	214
	215	0xb5 divx x = ( x / b ), b = ( x % b )
	216
	217	CUSTOM OPCODE: BlockMove (y,x,u):
	218	---------------------------------
	219	0xb6 bmove y,x,u
	220
	221	y = pointer to source address
	222	x = pointer to destination address
	223	u = bytes to move
	224
	225	One byte is copied at a time and x and y get incremented for each access.
	226
	227	CUSTOM OPCODE: Move (y,x,u):
	228	---------------------------------
	229	0xb7 move y,x,u
	230
	231	y = pointer to source address
	232	x = pointer to destination address
	233	u = counter
	234
	235	Copy ONE byte, increment x and y, decrement u.
	236
	237	0xb8 lsrd xx
	238	0xb9 lsrd indexed
	239	0xba rord xx ( not confirmed )
	240	0xbb rord indexed ( not confirmed )
	241	0xbc asrd xx ( not confirmed )
	242	0xbd asrd indexed ( not confirmed )
	243	0xbe asld xx
	244	0xbf asld indexed ( not confirmed )
	245	0xc0 rold xx ( not confirmed )
	246	0xc1 rold indexed ( not confirmed )
	247
	248	0xc2 clrd
	249	0xc3 clrw indexed ( clears an entire word ) ( not confirmed )
	250
	251	0xc4 negd (not confirmed )
	252	0xc5 negw indexed
	253
	254	0xc6 incd (not confirmed )
	255	0xc7 incw indexed
	256
	257	0xc8 decd (not confirmed )
	258	0xc9 decw indexed
	259
	260	0xca tstd
	261	0xcb tstw indexed
	262
	263	0xcc absa
	264	0xcd absb
	265	0xce absd
	266
	267	CUSTOM OPCODE: BlockSet (a,x,u):
	268	---------------------------------
	269	0xcf bset a,x,u
	270
	271	a = source data
	272	x = pointer to destination address
	273	u = bytes to move
	274
	275	One byte is copied at a time and x get incremented for each access.
	276
	277	CUSTOM OPCODE: BlockSet (d,x,u): (not confirmed)
	278	--------------------------------
	279	0xd0 bset d,x,u
	280
	281	d = source data
	282	x = pointer to destination address
	283	u = bytes to move/2
	284
	285	Two bytes are copied at a time and x get incremented twice for each access.
	286
	287	*/
	288
	289	static unsigned byte_count;
	290	static unsigned local_pc;
	291	static unsigned flags;
	292
	293	static const unsigned char *opram_ptr;
	294
	295	static unsigned char get_next_byte( void ) {
	296	return opram_ptr[byte_count++];
	297	}
	298
	299	/* Table for indexed operations */
	300	static const char index_reg[8][3] = {
	301	"?", /* 0 - extended mode */
	302	"?", /* 1 */
	303	"x", /* 2 */
	304	"y", /* 3 */
	305	"?", /* 4 - direct page */
	306	"u", /* 5 */
	307	"s", /* 6 */
	308	"pc" /* 7 - pc */
	309	};
	310
	311	/* Table for tfr/exg operations */
	312	static const char tfrexg_reg[8][3] = {
	313	"a", /* 0 */
	314	"b", /* 1 */
	315	"x", /* 2 */
	316	"y", /* 3 */
	317	"s", /* 4 */
	318	"u", /* 5 */
	319	"?", /* 6 */
	320	"?", /* 7 */
	321	};
	322
	323	/* Table for stack S operations */
	324	static const char stack_reg_s[8][3] = {
	325	"cc",
	326	"a",
	327	"b",
	328	"dp",
	329	"x",
	330	"y",
	331	"u",
	332	"pc"
	333	};
	334
	335	/* Table for stack U operations */
	336	static const char stack_reg_u[8][3] = {
	337	"cc",
	338	"a",
	339	"b",
	340	"dp",
	341	"x",
	342	"y",
	343	"s",
	344	"pc"
	345	};
	346
	347	static void calc_indexed( unsigned char mode, char *buf ) {
	348	char buf2[30];
	349	int idx, type;
	350
	351	idx = ( mode >> 4 ) & 7;
	352	type = mode & 0x0f;
	353
	354	/* special modes */
	355	if ( mode & 0x80 ) {
	356	if ( type & 8 ) { /* indirect */
	357	switch ( type & 7 ) {
	358	case 0x00: /* register a */
	359	sprintf( buf2, "[a,%s]", index_reg[idx] );
	360	break;
	361
	362	case 0x01: /* register b */
	363	sprintf( buf2, "[b,%s]", index_reg[idx] );
	364	break;
	365
	366	case 0x04: /* direct - mode */
	367	sprintf( buf2, "[$%02x]", get_next_byte() );
	368	break;
	369
	370	case 0x07: /* register d */
	371	sprintf( buf2, "[d,%s]", index_reg[idx] );
	372	break;
	373
	374	default:
	375	sprintf( buf2, "[?,%s]", index_reg[idx] );
	376	break;
	377	}
	378	} else {
	379	switch ( type & 7 ) {
	380	case 0x00: /* register a */
	381	sprintf( buf2, "a,%s", index_reg[idx] );
	382	break;
	383
	384	case 0x01: /* register b */
	385	sprintf( buf2, "b,%s", index_reg[idx] );
	386	break;
	387
	388	case 0x04: /* direct - mode */
	389	sprintf( buf2, "$%02x", get_next_byte() );
	390	break;
	391
	392	case 0x07: /* register d */
	393	sprintf( buf2, "d,%s", index_reg[idx] );
	394	break;
	395
	396	default:
	397	sprintf( buf2, "????,%s", index_reg[idx] );
	398	break;
	399	}
	400	}
	401	} else {
	402	if ( type & 8 ) { /* indirect */
	403	switch ( type & 7 ) {
	404	case 0: /* auto increment */
	405	sprintf( buf2, "[,%s+]", index_reg[idx] );
	406	break;
	407
	408	case 1: /* auto increment double */
	409	sprintf( buf2, "[,%s++]", index_reg[idx] );
	410	break;
	411
	412	case 2: /* auto decrement */
	413	sprintf( buf2, "[,-%s]", index_reg[idx] );
	414	break;
	415
	416	case 3: /* auto decrement double */
	417	sprintf( buf2, "[,--%s]", index_reg[idx] );
	418	break;
	419
	420	case 4: /* post byte offset */
	421	{
	422	int val = get_next_byte();
	423
	424	if ( val & 0x80 )
	425	sprintf( buf2, "[#$-%02x,%s]", 0x100 - val, index_reg[idx] );
	426	else
	427	sprintf( buf2, "[#$%02x,%s]", val, index_reg[idx] );
	428	}
	429	break;
	430
	431	case 5: /* post word offset */
	432	{
	433	int val = get_next_byte() << 8;
	434
	435	val \|= get_next_byte();
	436
	437	if ( val & 0x8000 )
	438	sprintf( buf2, "[#$-%04x,%s]", 0x10000 - val, index_reg[idx] );
	439	else
	440	sprintf( buf2, "[#$%04x,%s]", val, index_reg[idx] );
	441	}
	442	break;
	443
	444	case 6: /* simple */
	445	sprintf( buf2, "[,%s]", index_reg[idx] );
	446	break;
	447
	448	case 7: /* extended */
	449	{
	450	int val = get_next_byte() << 8;
	451
	452	val \|= get_next_byte();
	453
	454	sprintf( buf2, "[$%04x]", val );
	455	}
	456	break;
	457	}
	458	} else {
	459	switch ( type & 7 ) {
	460	case 0: /* auto increment */
	461	sprintf( buf2, ",%s+", index_reg[idx] );
	462	break;
	463
	464	case 1: /* auto increment double */
	465	sprintf( buf2, ",%s++", index_reg[idx] );
	466	break;
	467
	468	case 2: /* auto decrement */
	469	sprintf( buf2, ",-%s", index_reg[idx] );
	470	break;
	471
	472	case 3: /* auto decrement double */
	473	sprintf( buf2, ",--%s", index_reg[idx] );
	474	break;
	475
	476	case 4: /* post byte offset */
	477	{
	478	int val = get_next_byte();
	479
	480	if ( val & 0x80 )
	481	sprintf( buf2, "#$-%02x,%s", 0x100 - val , index_reg[idx] );
	482	else
	483	sprintf( buf2, "#$%02x,%s", val, index_reg[idx] );
	484	}
	485	break;
	486
	487	case 5: /* post word offset */
	488	{
	489	int val = get_next_byte() << 8;
	490
	491	val \|= get_next_byte();
	492
	493	if ( val & 0x8000 )
	494	sprintf( buf2, "#$-%04x,%s", 0x10000 - val, index_reg[idx] );
	495	else
	496	sprintf( buf2, "#$%04x,%s", val, index_reg[idx] );
	497	}
	498	break;
	499
	500	case 6: /* simple */
	501	sprintf( buf2, ",%s", index_reg[idx] );
	502	break;
	503
	504	case 7: /* extended */
	505	{
	506	int val = get_next_byte() << 8;
	507
	508	val \|= get_next_byte();
	509
	510	sprintf( buf2, "$%04x", val );
	511	}
	512	break;
	513
	514	}
	515	}
	516	}
	517
	518	strcat( buf, buf2 );
	519	}
	520
	521	static void do_relative( char *buf ) {
	522	char buf2[30];
	523	signed char offs = ( signed char )get_next_byte();
	524
	525	sprintf( buf2, "$%04x (%d)", local_pc + byte_count + offs, (int)offs );
	526
	527	strcat( buf, buf2 );
	528	}
	529
	530	static void do_relative_word( char *buf ) {
	531	char buf2[30];
	532	signed short offs;
	533	int val = get_next_byte() << 8;
	534
	535	val \|= get_next_byte();
	536
	537	offs = ( signed short )val;
	538
	539	sprintf( buf2, "$%04x (%d)", local_pc + byte_count + offs, (int)offs );
	540
	541	strcat( buf, buf2 );
	542	}
	543
	544	static void do_addressing( char *buf ) {
	545	unsigned char mode = get_next_byte();
	546
	547	calc_indexed( mode, buf );
	548	}
	549
	550	/*********************************************************************************
	551
	552	Opcodes
	553
	554	*********************************************************************************/
	555
	556	static void illegal( char *buf ) {
	557	sprintf( buf, "illegal/unknown " );
	558
	559	}
	560
	561	static void leax( char *buf ) {
	562	sprintf( buf, "leax " );
	563	do_addressing( buf );
	564	}
	565
	566	static void leay( char *buf ) {
	567	sprintf( buf, "leay " );
	568	do_addressing( buf );
	569	}
	570
	571	static void leau( char *buf ) {
	572	sprintf( buf, "leau " );
	573	do_addressing( buf );
	574	}
	575
	576	static void leas( char *buf ) {
	577	sprintf( buf, "leas " );
	578	do_addressing( buf );
	579	}
	580
	581	static void lda( char *buf ) {
	582	sprintf( buf, "lda #$%02x", get_next_byte() );
	583	}
	584
	585	static void ldb( char *buf ) {
	586	sprintf( buf, "ldb #$%02x", get_next_byte() );
	587	}
	588
	589	static void lda2( char *buf ) {
	590	sprintf( buf, "lda " );
	591	do_addressing( buf );
	592	}
	593
	594	static void ldb2( char *buf ) {
	595	sprintf( buf, "ldb " );
	596	do_addressing( buf );
	597	}
	598
	599	static void adda( char *buf ) {
	600	sprintf( buf, "adda #$%02x", get_next_byte() );
	601	}
	602
	603	static void addb( char *buf ) {
	604	sprintf( buf, "addb #$%02x", get_next_byte() );
	605	}
	606
	607	static void adda2( char *buf ) {
	608	sprintf( buf, "adda " );
	609	do_addressing( buf );
	610	}
	611
	612	static void addb2( char *buf ) {
	613	sprintf( buf, "addb " );
	614	do_addressing( buf );
	615	}
	616
	617	static void suba( char *buf ) {
	618	sprintf( buf, "suba #$%02x", get_next_byte() );
	619	}
	620
	621	static void subb( char *buf ) {
	622	sprintf( buf, "subb #$%02x", get_next_byte() );
	623	}
	624
	625	static void suba2( char *buf ) {
	626	sprintf( buf, "suba " );
	627	do_addressing( buf );
	628	}
	629
	630	static void subb2( char *buf ) {
	631	sprintf( buf, "subb " );
	632	do_addressing( buf );
	633	}
	634
	635	static void sbca( char *buf ) {
	636	sprintf( buf, "sbca #$%02x", get_next_byte() );
	637	}
	638
	639	static void sbcb( char *buf ) {
	640	sprintf( buf, "sbcb #$%02x", get_next_byte() );
	641	}
	642
	643	static void sbca2( char *buf ) {
	644	sprintf( buf, "sbca " );
	645	do_addressing( buf );
	646	}
	647
	648	static void sbcb2( char *buf ) {
	649	sprintf( buf, "sbcb " );
	650	do_addressing( buf );
	651	}
	652
	653	static void adca( char *buf ) {
	654	sprintf( buf, "adca #$%02x", get_next_byte() );
	655	}
	656
	657	static void adca2( char *buf ) {
	658	sprintf( buf, "adca " );
	659	do_addressing( buf );
	660	}
	661
	662	static void adcb2( char *buf ) {
	663	sprintf( buf, "adcb " );
	664	do_addressing( buf );
	665	}
	666
	667	static void adcb( char *buf ) {
	668	sprintf( buf, "adcb #$%02x", get_next_byte() );
	669	}
	670
	671	static void anda( char *buf ) {
	672	sprintf( buf, "anda #$%02x", get_next_byte() );
	673	}
	674
	675	static void andb( char *buf ) {
	676	sprintf( buf, "andb #$%02x", get_next_byte() );
	677	}
	678
	679	static void anda2( char *buf ) {
	680	sprintf( buf, "anda " );
	681	do_addressing( buf );
	682	}
	683
	684	static void andb2( char *buf ) {
	685	sprintf( buf, "andb " );
	686	do_addressing( buf );
	687	}
	688
	689	static void bita( char *buf ) {
	690	sprintf( buf, "bita #$%02x", get_next_byte() );
	691	}
	692
	693	static void bitb( char *buf ) {
	694	sprintf( buf, "bitb #$%02x", get_next_byte() );
	695	}
	696
	697	static void bita2( char *buf ) {
	698	sprintf( buf, "bita " );
	699	do_addressing( buf );
	700	}
	701
	702	static void bitb2( char *buf ) {
	703	sprintf( buf, "bitb " );
	704	do_addressing( buf );
	705	}
	706
	707	static void eora( char *buf ) {
	708	sprintf( buf, "eora #$%02x", get_next_byte() );
	709	}
	710
	711	static void eorb( char *buf ) {
	712	sprintf( buf, "eorb #$%02x", get_next_byte() );
	713	}
	714
	715	static void eora2( char *buf ) {
	716	sprintf( buf, "eora " );
	717	do_addressing( buf );
	718	}
	719
	720	static void eorb2( char *buf ) {
	721	sprintf( buf, "eorb " );
	722	do_addressing( buf );
	723	}
	724
	725	static void ora( char *buf ) {
	726	sprintf( buf, "ora #$%02x", get_next_byte() );
	727	}
	728
	729	static void orb( char *buf ) {
	730	sprintf( buf, "orb #$%02x", get_next_byte() );
	731	}
	732
	733	static void ora2( char *buf ) {
	734	sprintf( buf, "ora " );
	735	do_addressing( buf );
	736	}
	737
	738	static void orb2( char *buf ) {
	739	sprintf( buf, "orb " );
	740	do_addressing( buf );
	741	}
	742
	743	static void cmpa( char *buf ) {
	744	sprintf( buf, "cmpa #$%02x", get_next_byte() );
	745	}
	746
	747	static void cmpb( char *buf ) {
	748	sprintf( buf, "cmpb #$%02x", get_next_byte() );
	749	}
	750
	751	static void cmpa2( char *buf ) {
	752	sprintf( buf, "cmpa " );
	753	do_addressing( buf );
	754	}
	755
	756	static void cmpb2( char *buf ) {
	757	sprintf( buf, "cmpb " );
	758	do_addressing( buf );
	759	}
	760
	761	static void setlines( char *buf ) {
	762	sprintf( buf, "setlines #$%02x", get_next_byte() );
	763	}
	764
	765	static void setlines2( char *buf ) {
	766	sprintf( buf, "setlines " );
	767	do_addressing( buf );
	768	}
	769
	770	static void sta2( char *buf ) {
	771	sprintf( buf, "sta " );
	772	do_addressing( buf );
	773	}
	774
	775	static void stb2( char *buf ) {
	776	sprintf( buf, "stb " );
	777	do_addressing( buf );
	778	}
	779
	780	static void ldd( char *buf ) {
	781	int val = get_next_byte() << 8;
	782
	783	val \|= get_next_byte();
	784
	785	sprintf( buf, "ldd #$%04x", val );
	786	}
	787
	788	static void ldd2( char *buf ) {
	789	sprintf( buf, "ldd " );
	790	do_addressing( buf );
	791	}
	792
	793	static void ldx( char *buf ) {
	794	int val = get_next_byte() << 8;
	795
	796	val \|= get_next_byte();
	797
	798	sprintf( buf, "ldx #$%04x", val );
	799	}
	800
	801	static void ldx2( char *buf ) {
	802	sprintf( buf, "ldx " );
	803	do_addressing( buf );
	804	}
	805
	806	static void ldy( char *buf ) {
	807	int val = get_next_byte() << 8;
	808
	809	val \|= get_next_byte();
	810
	811	sprintf( buf, "ldy #$%04x", val );
	812	}
	813
	814	static void ldy2( char *buf ) {
	815	sprintf( buf, "ldy " );
	816	do_addressing( buf );
	817	}
	818
	819	static void ldu( char *buf ) {
	820	int val = get_next_byte() << 8;
	821
	822	val \|= get_next_byte();
	823
	824	sprintf( buf, "ldu #$%04x", val );
	825	}
	826
	827	static void ldu2( char *buf ) {
	828	sprintf( buf, "ldu " );
	829	do_addressing( buf );
	830	}
	831
	832	static void lds( char *buf ) {
	833	int val = get_next_byte() << 8;
	834
	835	val \|= get_next_byte();
	836
	837	sprintf( buf, "lds #$%04x", val );
	838	}
	839
	840	static void lds2( char *buf ) {
	841	sprintf( buf, "lds " );
	842	do_addressing( buf );
	843	}
	844
	845	static void cmpd( char *buf ) {
	846	int val = get_next_byte() << 8;
	847
	848	val \|= get_next_byte();
	849
	850	sprintf( buf, "cmpd #$%04x", val );
	851	}
	852
	853	static void cmpd2( char *buf ) {
	854	sprintf( buf, "cmpd " );
	855	do_addressing( buf );
	856	}
	857
	858	static void cmpx( char *buf ) {
	859	int val = get_next_byte() << 8;
	860
	861	val \|= get_next_byte();
	862
	863	sprintf( buf, "cmpx #$%04x", val );
	864	}
	865
	866	static void cmpx2( char *buf ) {
	867	sprintf( buf, "cmpx " );
	868	do_addressing( buf );
	869	}
	870
	871	static void cmpy( char *buf ) {
	872	int val = get_next_byte() << 8;
	873
	874	val \|= get_next_byte();
	875
	876	sprintf( buf, "cmpy #$%04x", val );
	877	}
	878
	879	static void cmpy2( char *buf ) {
	880	sprintf( buf, "cmpy " );
	881	do_addressing( buf );
	882	}
	883
	884	static void cmpu( char *buf ) {
	885	int val = get_next_byte() << 8;
	886
	887	val \|= get_next_byte();
	888
	889	sprintf( buf, "cmpu #$%04x", val );
	890	}
	891
	892	static void cmpu2( char *buf ) {
	893	sprintf( buf, "cmpu " );
	894	do_addressing( buf );
	895	}
	896
	897	static void cmps( char *buf ) {
	898	int val = get_next_byte() << 8;
	899
	900	val \|= get_next_byte();
	901
	902	sprintf( buf, "cmps #$%04x", val );
	903	}
	904
	905	static void cmps2( char *buf ) {
	906	sprintf( buf, "cmps " );
	907	do_addressing( buf );
	908	}
	909
	910	static void addd2( char *buf ) {
	911	sprintf( buf, "addd " );
	912	do_addressing( buf );
	913	}
	914
	915	static void subd2( char *buf ) {
	916	sprintf( buf, "subd " );
	917	do_addressing( buf );
	918	}
	919
	920	static void std2( char *buf ) {
	921	sprintf( buf, "std " );
	922	do_addressing( buf );
	923	}
	924
	925	static void stx2( char *buf ) {
	926	sprintf( buf, "stx " );
	927	do_addressing( buf );
	928	}
	929
	930	static void sty2( char *buf ) {
	931	sprintf( buf, "sty " );
	932	do_addressing( buf );
	933	}
	934
	935	static void stu2( char *buf ) {
	936	sprintf( buf, "stu " );
	937	do_addressing( buf );
	938	}
	939
	940	static void sts2( char *buf ) {
	941	sprintf( buf, "sts " );
	942	do_addressing( buf );
	943	}
	944
	945	static void bra( char *buf ) {
	946	sprintf( buf, "bra " );
	947	do_relative( buf );
	948	}
	949
	950	static void lbra( char *buf ) {
	951	sprintf( buf, "lbra " );
	952	do_relative_word( buf );
	953	}
	954
	955	static void brn( char *buf ) {
	956	sprintf( buf, "brn " );
	957	do_relative( buf );
	958	}
	959
	960	static void lbrn( char *buf ) {
	961	sprintf( buf, "lbrn " );
	962	do_relative_word( buf );
	963	}
	964
	965	static void bhi( char *buf ) {
	966	sprintf( buf, "bhi " );
	967	do_relative( buf );
	968	}
	969
	970	static void lbhi( char *buf ) {
	971	sprintf( buf, "lbhi " );
	972	do_relative_word( buf );
	973	}
	974
	975	static void bls( char *buf ) {
	976	sprintf( buf, "bls " );
	977	do_relative( buf );
	978	}
	979
	980	static void lbls( char *buf ) {
	981	sprintf( buf, "lbls " );
	982	do_relative_word( buf );
	983	}
	984
	985	static void bcc( char *buf ) {
	986	sprintf( buf, "bcc " );
	987	do_relative( buf );
	988	}
	989
	990	static void lbcc( char *buf ) {
	991	sprintf( buf, "lbcc " );
	992	do_relative_word( buf );
	993	}
	994
	995	static void bcs( char *buf ) {
	996	sprintf( buf, "bcs " );
	997	do_relative( buf );
	998	}
	999
	1000	static void lbcs( char *buf ) {
	1001	sprintf( buf, "lbcs " );
	1002	do_relative_word( buf );
	1003	}
	1004
	1005	static void bne( char *buf ) {
	1006	sprintf( buf, "bne " );
	1007	do_relative( buf );
	1008	}
	1009
	1010	static void lbne( char *buf ) {
	1011	sprintf( buf, "lbne " );
	1012	do_relative_word( buf );
	1013	}
	1014
	1015	static void beq( char *buf ) {
	1016	sprintf( buf, "beq " );
	1017	do_relative( buf );
	1018	}
	1019
	1020	static void lbeq( char *buf ) {
	1021	sprintf( buf, "lbeq " );
	1022	do_relative_word( buf );
	1023	}
	1024
	1025	static void bvc( char *buf ) {
	1026	sprintf( buf, "bvc " );
	1027	do_relative( buf );
	1028	}
	1029
	1030	static void lbvc( char *buf ) {
	1031	sprintf( buf, "lbvc " );
	1032	do_relative_word( buf );
	1033	}
	1034
	1035	static void bvs( char *buf ) {
	1036	sprintf( buf, "bvs " );
	1037	do_relative( buf );
	1038	}
	1039
	1040	static void lbvs( char *buf ) {
	1041	sprintf( buf, "lbvs " );
	1042	do_relative_word( buf );
	1043	}
	1044
	1045	static void bpl( char *buf ) {
	1046	sprintf( buf, "bpl " );
	1047	do_relative( buf );
	1048	}
	1049
	1050	static void lbpl( char *buf ) {
	1051	sprintf( buf, "lbpl " );
	1052	do_relative_word( buf );
	1053	}
	1054
	1055	static void bmi( char *buf ) {
	1056	sprintf( buf, "bmi " );
	1057	do_relative( buf );
	1058	}
	1059
	1060	static void lbmi( char *buf ) {
	1061	sprintf( buf, "lbmi " );
	1062	do_relative_word( buf );
	1063	}
	1064
	1065	static void bge( char *buf ) {
	1066	sprintf( buf, "bge " );
	1067	do_relative( buf );
	1068	}
	1069
	1070	static void lbge( char *buf ) {
	1071	sprintf( buf, "lbge " );
	1072	do_relative_word( buf );
	1073	}
	1074
	1075	static void blt( char *buf ) {
	1076	sprintf( buf, "blt " );
	1077	do_relative( buf );
	1078	}
	1079
	1080	static void lblt( char *buf ) {
	1081	sprintf( buf, "lblt " );
	1082	do_relative_word( buf );
	1083	}
	1084
	1085	static void bgt( char *buf ) {
	1086	sprintf( buf, "bgt " );
	1087	do_relative( buf );
	1088	}
	1089
	1090	static void lbgt( char *buf ) {
	1091	sprintf( buf, "lbgt " );
	1092	do_relative_word( buf );
	1093	}
	1094
	1095	static void ble( char *buf ) {
	1096	sprintf( buf, "ble " );
	1097	do_relative( buf );
	1098	}
	1099
	1100	static void lble( char *buf ) {
	1101	sprintf( buf, "lble " );
	1102	do_relative_word( buf );
	1103	}
	1104
	1105	static void clra( char *buf ) {
	1106	sprintf( buf, "clra" );
	1107	}
	1108
	1109	static void clrb( char *buf ) {
	1110	sprintf( buf, "clrb" );
	1111	}
	1112
	1113	static void clrd( char *buf ) {
	1114	sprintf( buf, "clrd" );
	1115	}
	1116
	1117	static void clrw( char *buf ) {
	1118	sprintf( buf, "clrw " );
	1119	do_addressing( buf );
	1120	}
	1121
	1122	static void negd( char *buf ) {
	1123	sprintf( buf, "negd" );
	1124	}
	1125
	1126	static void negw( char *buf ) {
	1127	sprintf( buf, "negw" );
	1128	do_addressing( buf );
	1129	}
	1130
	1131	static void incd( char *buf ) {
	1132	sprintf( buf, "incd" );
	1133	}
	1134
	1135	static void incw( char *buf ) {
	1136	sprintf( buf, "incw " );
	1137	do_addressing( buf );
	1138	}
	1139
	1140	static void decd( char *buf ) {
	1141	sprintf( buf, "decd" );
	1142	}
	1143
	1144	static void decw( char *buf ) {
	1145	sprintf( buf, "decw " );
	1146	do_addressing( buf );
	1147	}
	1148
	1149	static void tstd( char *buf ) {
	1150	sprintf( buf, "tstd " );
	1151	}
	1152
	1153	static void tstw( char *buf ) {
	1154	sprintf( buf, "tstw " );
	1155	do_addressing( buf );
	1156	}
	1157
	1158	static void clr2( char *buf ) {
	1159	sprintf( buf, "clr " );
	1160	do_addressing( buf );
	1161	}
	1162
	1163	static void coma( char *buf ) {
	1164	sprintf( buf, "coma" );
	1165	}
	1166
	1167	static void comb( char *buf ) {
	1168	sprintf( buf, "comb" );
	1169	}
	1170
	1171	static void com2( char *buf ) {
	1172	sprintf( buf, "com " );
	1173	do_addressing( buf );
	1174	}
	1175
	1176	static void nega( char *buf ) {
	1177	sprintf( buf, "nega" );
	1178	}
	1179
	1180	static void negb( char *buf ) {
	1181	sprintf( buf, "negb" );
	1182	}
	1183
	1184	static void neg2( char *buf ) {
	1185	sprintf( buf, "neg " );
	1186	do_addressing( buf );
	1187	}
	1188
	1189	static void inca( char *buf ) {
	1190	sprintf( buf, "inca" );
	1191	}
	1192
	1193	static void incb( char *buf ) {
	1194	sprintf( buf, "incb" );
	1195	}
	1196
	1197	static void inc2( char *buf ) {
	1198	sprintf( buf, "inc " );
	1199	do_addressing( buf );
	1200	}
	1201
	1202	static void deca( char *buf ) {
	1203	sprintf( buf, "deca" );
	1204	}
	1205
	1206	static void decb( char *buf ) {
	1207	sprintf( buf, "decb" );
	1208	}
	1209
	1210	static void dec2( char *buf ) {
	1211	sprintf( buf, "dec " );
	1212	do_addressing( buf );
	1213	}
	1214
	1215	static void rts( char *buf ) {
	1216	sprintf( buf, "rts" );
	1217	flags = DASMFLAG_STEP_OUT;
	1218	}
	1219
	1220	static void asla( char *buf ) {
	1221	sprintf( buf, "asla" );
	1222	}
	1223
	1224	static void aslb( char *buf ) {
	1225	sprintf( buf, "aslb" );
	1226	}
	1227
	1228	static void asl2( char *buf ) {
	1229	sprintf( buf, "asl " );
	1230	do_addressing( buf );
	1231	}
	1232
	1233	static void rora( char *buf ) {
	1234	sprintf( buf, "rora" );
	1235	}
	1236
	1237	static void rorb( char *buf ) {
	1238	sprintf( buf, "rorb" );
	1239	}
	1240
	1241	static void ror2( char *buf ) {
	1242	sprintf( buf, "ror " );
	1243	do_addressing( buf );
	1244	}
	1245
	1246	static void rti( char *buf ) {
	1247	sprintf( buf, "rti" );
	1248	flags = DASMFLAG_STEP_OUT;
	1249	}
	1250
	1251	static void jsr2( char *buf ) {
	1252	sprintf( buf, "jsr " );
	1253	do_addressing( buf );
	1254	flags = DASMFLAG_STEP_OVER;
	1255	}
	1256
	1257	static void jmp2( char *buf ) {
	1258	sprintf( buf, "jmp " );
	1259	do_addressing( buf );
	1260	}
	1261
	1262	static void bsr( char *buf ) {
	1263	sprintf( buf, "bsr " );
	1264	do_relative( buf );
	1265	flags = DASMFLAG_STEP_OVER;
	1266	}
	1267
	1268	static void lbsr( char *buf ) {
	1269	sprintf( buf, "lbsr " );
	1270	do_relative_word( buf );
	1271	flags = DASMFLAG_STEP_OVER;
	1272	}
	1273
	1274	static void decbjnz( char *buf ) {
	1275	sprintf( buf, "decb,jnz " );
	1276	do_relative( buf );
	1277	flags = DASMFLAG_STEP_OVER;
	1278	}
	1279
	1280	static void decxjnz( char *buf ) {
	1281	sprintf( buf, "decx,jnz " );
	1282	do_relative( buf );
	1283	flags = DASMFLAG_STEP_OVER;
	1284	}
	1285
	1286	static void addd( char *buf ) {
	1287	int val = get_next_byte() << 8;
	1288
	1289	val \|= get_next_byte();
	1290
	1291	sprintf( buf, "addd #$%04x", val );
	1292	}
	1293
	1294	static void subd( char *buf ) {
	1295	int val = get_next_byte() << 8;
	1296
	1297	val \|= get_next_byte();
	1298
	1299	sprintf( buf, "subd #$%04x", val );
	1300	}
	1301
	1302	static void tsta( char *buf ) {
	1303	sprintf( buf, "tsta" );
	1304	}
	1305
	1306	static void tstb( char *buf ) {
	1307	sprintf( buf, "tstb" );
	1308	}
	1309
	1310	static void tst2( char *buf ) {
	1311	sprintf( buf, "tst " );
	1312	do_addressing( buf );
	1313	}
	1314
	1315	static void lsra( char *buf ) {
	1316	sprintf( buf, "lsra" );
	1317	}
	1318
	1319	static void lsrb( char *buf ) {
	1320	sprintf( buf, "lsrb" );
	1321	}
	1322
	1323	static void lsr2( char *buf ) {
	1324	sprintf( buf, "lsr " );
	1325	do_addressing( buf );
	1326	}
	1327
	1328	static void asra( char *buf ) {
	1329	sprintf( buf, "asra" );
	1330	}
	1331
	1332	static void asrb( char *buf ) {
	1333	sprintf( buf, "asrb" );
	1334	}
	1335
	1336	static void asr2( char *buf ) {
	1337	sprintf( buf, "asr " );
	1338	do_addressing( buf );
	1339	}
	1340
	1341	static void abx( char *buf ) {
	1342	sprintf( buf, "abx" );
	1343	}
	1344
	1345	static void sex( char *buf ) {
	1346	sprintf( buf, "sex" );
	1347	}
	1348
	1349	static void daa( char *buf ) {
	1350	sprintf( buf, "daa" );
	1351	}
	1352
	1353	static void mul( char *buf ) {
	1354	sprintf( buf, "mul" );
	1355	}
	1356
	1357	static void lmul( char *buf ) {
	1358	sprintf( buf, "lmul" );
	1359	}
	1360
	1361	static void divx( char *buf ) {
	1362	sprintf( buf, "div x,b" );
	1363	}
	1364
	1365	static void andcc( char *buf ) {
	1366	sprintf( buf, "andcc #$%02x", get_next_byte() );
	1367	}
	1368
	1369	static void orcc( char *buf ) {
	1370	sprintf( buf, "orcc #$%02x", get_next_byte() );
	1371	}
	1372
	1373	static void pushs( char *buf ) {
	1374	int mask = get_next_byte(), i;
	1375
	1376	sprintf( buf, "pushs " );
	1377
	1378	for ( i = 0; i < 8; i++ ) {
	1379	if ( ( mask >> i ) & 1 ) {
	1380	strcat( buf, stack_reg_s[i] );
	1381	mask &= ~( 1 << i );
	1382	if ( mask )
	1383	strcat( buf, "," );
	1384	else
	1385	return;
	1386	}
	1387	}
	1388	}
	1389
	1390	static void pushu( char *buf ) {
	1391	int mask = get_next_byte(), i;
	1392
	1393	sprintf( buf, "pushu " );
	1394
	1395	for ( i = 0; i < 8; i++ ) {
	1396	if ( ( mask >> i ) & 1 ) {
	1397	strcat( buf, stack_reg_u[i] );
	1398	mask &= ~( 1 << i );
	1399	if ( mask )
	1400	strcat( buf, "," );
	1401	else
	1402	return;
	1403	}
	1404	}
	1405	}
	1406
	1407	static void pulls( char *buf ) {
	1408	int mask = get_next_byte(), i;
	1409
	1410	sprintf( buf, "pulls " );
	1411
	1412	for ( i = 0; i < 8; i++ ) {
	1413	if ( ( mask >> i ) & 1 ) {
	1414	strcat( buf, stack_reg_s[i] );
	1415	if (i == 7)
	1416	flags = DASMFLAG_STEP_OUT;
	1417	mask &= ~( 1 << i );
	1418	if ( mask )
	1419	strcat( buf, "," );
	1420	else
	1421	return;
	1422	}
	1423	}
	1424	}
	1425
	1426	static void pullu( char *buf ) {
	1427	int mask = get_next_byte(), i;
	1428
	1429	sprintf( buf, "pullu " );
	1430
	1431	for ( i = 0; i < 8; i++ ) {
	1432	if ( ( mask >> i ) & 1 ) {
	1433	strcat( buf, stack_reg_s[i] );
	1434	mask &= ~( 1 << i );
	1435	if ( mask )
	1436	strcat( buf, "," );
	1437	else
	1438	return;
	1439	}
	1440	}
	1441	}
	1442
	1443	static void rola( char *buf ) {
	1444	sprintf( buf, "rola" );
	1445	}
	1446
	1447	static void rolb( char *buf ) {
	1448	sprintf( buf, "rolb" );
	1449	}
	1450
	1451	static void rol2( char *buf ) {
	1452	sprintf( buf, "rol " );
	1453	do_addressing( buf );
	1454	}
	1455
	1456	static void bmove( char *buf ) {
	1457	sprintf( buf, "bmove y,x,u" );
	1458	}
	1459
	1460	static void move( char *buf ) {
	1461	sprintf( buf, "move y,x,u" );
	1462	}
	1463
	1464	static void bset( char *buf ) {
	1465	sprintf( buf, "bset a,x,u" );
	1466	}
	1467
	1468	static void bset2( char *buf ) {
	1469	sprintf( buf, "bset d,x,u" );
	1470	}
	1471
	1472	static void nop( char *buf ) {
	1473	sprintf( buf, "nop" );
	1474	}
	1475
	1476	static void tfr( char *buf ) {
	1477	int mask = get_next_byte();
	1478
	1479	sprintf( buf, "tfr " );
	1480
	1481	strcat( buf, tfrexg_reg[ mask & 0x07 ] );
	1482	strcat( buf, "," );
	1483	strcat( buf, tfrexg_reg[ ( mask >> 4 ) & 0x07 ] );
	1484	}
	1485
	1486	static void exg( char *buf ) {
	1487	int mask = get_next_byte();
	1488
	1489	sprintf( buf, "exg " );
	1490
	1491	strcat( buf, tfrexg_reg[ mask & 0x07 ] );
	1492	strcat( buf, "," );
	1493	strcat( buf, tfrexg_reg[ ( mask >> 4 ) & 0x07 ] );
	1494	}
	1495
	1496	static void lsrd( char *buf ) {
	1497	sprintf( buf, "lsrd #$%02x", get_next_byte() );
	1498	}
	1499
	1500	static void lsrd2( char *buf ) {
	1501	sprintf( buf, "lsrd " );
	1502	do_addressing( buf );
	1503	}
	1504
	1505	static void rord( char *buf ) {
	1506	sprintf( buf, "rord #$%02x", get_next_byte() );
	1507	}
	1508
	1509	static void rord2( char *buf ) {
	1510	sprintf( buf, "rord " );
	1511	do_addressing( buf );
	1512	}
	1513
	1514	static void asrd( char *buf ) {
	1515	sprintf( buf, "asrd #$%02x", get_next_byte() );
	1516	}
	1517
	1518	static void asrd2( char *buf ) {
	1519	sprintf( buf, "asrd " );
	1520	do_addressing( buf );
	1521	}
	1522
	1523	static void asld( char *buf ) {
	1524	sprintf( buf, "asld #$%02x", get_next_byte() );
	1525	}
	1526
	1527	static void asld2( char *buf ) {
	1528	sprintf( buf, "asld " );
	1529	do_addressing( buf );
	1530	}
	1531
	1532	static void rold( char *buf ) {
	1533	sprintf( buf, "rold #$%02x", get_next_byte() );
	1534	}
	1535
	1536	static void rold2( char *buf ) {
	1537	sprintf( buf, "rold " );
	1538	do_addressing( buf );
	1539	}
	1540
	1541	static void lsrw( char *buf ) {
	1542	sprintf( buf, "lsrw " );
	1543	do_addressing( buf );
	1544	}
	1545
	1546	static void rorw( char *buf ) {
	1547	sprintf( buf, "lsrw " );
	1548	do_addressing( buf );
	1549	}
	1550
	1551	static void asrw( char *buf ) {
	1552	sprintf( buf, "asrw " );
	1553	do_addressing( buf );
	1554	}
	1555
	1556	static void aslw( char *buf ) {
	1557	sprintf( buf, "aslw " );
	1558	do_addressing( buf );
	1559	}
	1560
	1561	static void rolw( char *buf ) {
	1562	sprintf( buf, "rolw " );
	1563	do_addressing( buf );
	1564	}
	1565
	1566	static void absa( char *buf ) {
	1567	sprintf( buf, "absa" );
	1568	}
	1569
	1570	static void absb( char *buf ) {
	1571	sprintf( buf, "absb" );
	1572	}
	1573
	1574	static void absd( char *buf ) {
	1575	sprintf( buf, "absd" );
	1576	}
	1577
	1578	/*********************************************************************************
	1579
	1580	Opcode Table
	1581
	1582	*********************************************************************************/
	1583
	1584	struct konami_opcode_def {
	1585	void (decode)( char buf );
	1586	int confirmed;
	1587	};
	1588
	1589	static const konami_opcode_def op_table[256] = {
	1590	/* 00 */ { illegal, 0 },
	1591	/* 01 */ { illegal, 0 },
	1592	/* 02 */ { illegal, 0 },
	1593	/* 03 */ { illegal, 0 },
	1594	/* 04 */ { illegal, 0 },
	1595	/* 05 */ { illegal, 0 },
	1596	/* 06 */ { illegal, 0 },
	1597	/* 07 */ { illegal, 0 },
	1598	/* 08 */ { leax, 1 },
	1599	/* 09 */ { leay, 1 },
	1600	/* 0a */ { leau, 1 },
	1601	/* 0b */ { leas, 0 },
	1602	/* 0c */ { pushs, 1 },
	1603	/* 0d */ { pushu, 0 },
	1604	/* 0e */ { pulls, 1 },
	1605	/* 0f */ { pullu, 0 },
	1606
	1607	/* 10 */ { lda, 1 },
	1608	/* 11 */ { ldb, 1 },
	1609	/* 12 */ { lda2, 1 },
	1610	/* 13 */ { ldb2, 1 },
	1611	/* 14 */ { adda, 1 },
	1612	/* 15 */ { addb, 1 },
	1613	/* 16 */ { adda2, 1 },
	1614	/* 17 */ { addb2, 1 },
	1615	/* 18 */ { adca, 1 },
	1616	/* 19 */ { adcb, 1 },
	1617	/* 1a */ { adca2, 1 },
	1618	/* 1b */ { adcb2, 1 },
	1619	/* 1c */ { suba, 1 },
	1620	/* 1d */ { subb, 1 },
	1621	/* 1e */ { suba2, 1 },
	1622	/* 1f */ { subb2, 1 },
	1623
	1624	/* 20 */ { sbca, 0 },
	1625	/* 21 */ { sbcb, 0 },
	1626	/* 22 */ { sbca2, 0 },
	1627	/* 23 */ { sbcb2, 0 },
	1628	/* 24 */ { anda, 1 },
	1629	/* 25 */ { andb, 1 },
	1630	/* 26 */ { anda2, 1 },
	1631	/* 27 */ { andb2, 1 },
	1632	/* 28 */ { bita, 0 },
	1633	/* 29 */ { bitb, 0 },
	1634	/* 2a */ { bita2, 0 },
	1635	/* 2b */ { bitb2, 0 },
	1636	/* 2c */ { eora, 0 },
	1637	/* 2d */ { eorb, 0 },
	1638	/* 2e */ { eora2, 0 },
	1639	/* 2f */ { eorb2, 0 },
	1640
	1641	/* 30 */ { ora, 1 },
	1642	/* 31 */ { orb, 1 },
	1643	/* 32 */ { ora2, 1 },
	1644	/* 33 */ { orb2, 1 },
	1645	/* 34 */ { cmpa, 1 },
	1646	/* 35 */ { cmpb, 1 },
	1647	/* 36 */ { cmpa2, 1 },
	1648	/* 37 */ { cmpb2, 1 },
	1649	/* 38 */ { setlines, 0 },
	1650	/* 39 */ { setlines2, 0 },
	1651	/* 3a */ { sta2, 1 },
	1652	/* 3b */ { stb2, 1 },
	1653	/* 3c */ { andcc, 1 },
	1654	/* 3d */ { orcc, 0 },
	1655	/* 3e */ { exg, 0 },
	1656	/* 3f */ { tfr, 0 },
	1657
	1658	/* 40 */ { ldd, 1 },
	1659	/* 41 */ { ldd2, 1 },
	1660	/* 42 */ { ldx, 1 },
	1661	/* 43 */ { ldx2, 1 },
	1662	/* 44 */ { ldy, 1 },
	1663	/* 45 */ { ldy2, 1 },
	1664	/* 46 */ { ldu, 1 },
	1665	/* 47 */ { ldu2, 1 },
	1666	/* 48 */ { lds, 1 },
	1667	/* 49 */ { lds2, 1 },
	1668	/* 4a */ { cmpd, 1 },
	1669	/* 4b */ { cmpd2, 1 },
	1670	/* 4c */ { cmpx, 1 },
	1671	/* 4d */ { cmpx2, 1 },
	1672	/* 4e */ { cmpy, 1 },
	1673	/* 4f */ { cmpy2, 1 },
	1674
	1675	/* 50 */ { cmpu, 1 },
	1676	/* 51 */ { cmpu2, 1 },
	1677	/* 52 */ { cmps, 1 },
	1678	/* 53 */ { cmps2, 1 },
	1679	/* 54 */ { addd, 0 },
	1680	/* 55 */ { addd2, 0 },
	1681	/* 56 */ { subd, 1 },
	1682	/* 57 */ { subd2, 0 },
	1683	/* 58 */ { std2, 1 },
	1684	/* 59 */ { stx2, 1 },
	1685	/* 5a */ { sty2, 1 },
	1686	/* 5b */ { stu2, 1 },
	1687	/* 5c */ { sts2, 1 },
	1688	/* 5d */ { illegal, 0 },
	1689	/* 5e */ { illegal, 0 },
	1690	/* 5f */ { illegal, 0 },
	1691
	1692	/* 60 */ { bra, 1 },
	1693	/* 61 */ { bhi, 1 },
	1694	/* 62 */ { bcc, 1 },
	1695	/* 63 */ { bne, 1 },
	1696	/* 64 */ { bvc, 1 },
	1697	/* 65 */ { bpl, 1 },
	1698	/* 66 */ { bge, 1 },
	1699	/* 67 */ { bgt, 1 },
	1700	/* 68 */ { lbra, 1 },
	1701	/* 69 */ { lbhi, 1 },
	1702	/* 6a */ { lbcc, 1 },
	1703	/* 6b */ { lbne, 1 },
	1704	/* 6c */ { lbvc, 1 },
	1705	/* 6d */ { lbpl, 1 },
	1706	/* 6e */ { lbge, 1 },
	1707	/* 6f */ { lbgt, 1 },
	1708
	1709	/* 70 */ { brn, 1 },
	1710	/* 71 */ { bls, 1 },
	1711	/* 72 */ { bcs, 1 },
	1712	/* 73 */ { beq, 1 },
	1713	/* 74 */ { bvs, 1 },
	1714	/* 75 */ { bmi, 1 },
	1715	/* 76 */ { blt, 1 },
	1716	/* 77 */ { ble, 1 },
	1717	/* 78 */ { lbrn, 1 },
	1718	/* 79 */ { lbls, 1 },
	1719	/* 7a */ { lbcs, 1 },
	1720	/* 7b */ { lbeq, 1 },
	1721	/* 7c */ { lbvs, 1 },
	1722	/* 7d */ { lbmi, 1 },
	1723	/* 7e */ { lblt, 1 },
	1724	/* 7f */ { lble, 1 },
	1725
	1726	/* 80 */ { clra, 1 },
	1727	/* 81 */ { clrb, 1 },
	1728	/* 82 */ { clr2, 1 },
	1729	/* 83 */ { coma, 1 },
	1730	/* 84 */ { comb, 0 },
	1731	/* 85 */ { com2, 0 },
	1732	/* 86 */ { nega, 0 },
	1733	/* 87 */ { negb, 0 },
	1734	/* 88 */ { neg2, 0 },
	1735	/* 89 */ { inca, 1 },
	1736	/* 8a */ { incb, 1 },
	1737	/* 8b */ { inc2, 1 },
	1738	/* 8c */ { deca, 1 },
	1739	/* 8d */ { decb, 1 },
	1740	/* 8e */ { dec2, 1 },
	1741	/* 8f */ { rts, 1 },
	1742
	1743	/* 90 */ { tsta, 0 },
	1744	/* 91 */ { tstb, 0 },
	1745	/* 92 */ { tst2, 0 },
	1746	/* 93 */ { lsra, 1 },
	1747	/* 94 */ { lsrb, 1 },
	1748	/* 95 */ { lsr2, 0 },
	1749	/* 96 */ { rora, 0 },
	1750	/* 97 */ { rorb, 0 },
	1751	/* 98 */ { ror2, 0 },
	1752	/* 99 */ { asra, 0 },
	1753	/* 9a */ { asrb, 0 },
	1754	/* 9b */ { asr2, 0 },
	1755	/* 9c */ { asla, 1 },
	1756	/* 9d */ { aslb, 1 },
	1757	/* 9e */ { asl2, 0 },
	1758	/* 9f */ { rti, 1 },
	1759
	1760	/* a0 */ { rola, 1 },
	1761	/* a1 */ { rolb, 0 },
	1762	/* a2 */ { rol2, 0 },
	1763	/* a3 */ { lsrw, 0 },
	1764	/* a4 */ { rorw, 0 },
	1765	/* a5 */ { asrw, 0 },
	1766	/* a6 */ { aslw, 0 },
	1767	/* a7 */ { rolw, 0 },
	1768	/* a8 */ { jmp2, 1 },
	1769	/* a9 */ { jsr2, 1 },
	1770	/* aa */ { bsr, 1 },
	1771	/* ab */ { lbsr, 1 },
	1772	/* ac */ { decbjnz, 0 },
	1773	/* ad */ { decxjnz, 0 },
	1774	/* ae */ { nop, 0 },
	1775	/* af */ { illegal, 0 },
	1776
	1777	/* b0 */ { abx, 0 },
	1778	/* b1 */ { daa, 0 },
	1779	/* b2 */ { sex, 0 },
	1780	/* b3 */ { mul, 1 },
	1781	/* b4 */ { lmul, 0 },
	1782	/* b5 */ { divx, 0 },
	1783	/* b6 */ { bmove, 1 },
	1784	/* b7 */ { move, 0 },
	1785	/* b8 */ { lsrd, 0 },
	1786	/* b9 */ { lsrd2, 0 },
	1787	/* ba */ { rord, 0 },
	1788	/* bb */ { rord2, 0 },
	1789	/* bc */ { asrd, 0 },
	1790	/* bd */ { asrd2, 0 },
	1791	/* be */ { asld, 0 },
	1792	/* bf */ { asld2, 0 },
	1793
	1794	/* c0 */ { rold, 0 },
	1795	/* c1 */ { rold2, 0 },
	1796	/* c2 */ { clrd, 1 },
	1797	/* c3 */ { clrw, 0 },
	1798	/* c4 */ { negd, 0 },
	1799	/* c5 */ { negw, 0 },
	1800	/* c6 */ { incd, 0 },
	1801	/* c7 */ { incw, 0 },
	1802	/* c8 */ { decd, 0 },
	1803	/* c9 */ { decw, 0 },
	1804	/* ca */ { tstd, 0 },
	1805	/* cb */ { tstw, 0 },
	1806	/* cc */ { absa, 0 },
	1807	/* cd */ { absb, 0 },
	1808	/* ce */ { absd, 0 },
	1809	/* cf */ { bset, 0 },
	1810
	1811	/* d0 */ { bset2, 0 },
	1812	/* d1 */ { illegal, 0 },
	1813	/* d2 */ { illegal, 0 },
	1814	/* d3 */ { illegal, 0 },
	1815	/* d4 */ { illegal, 0 },
	1816	/* d5 */ { illegal, 0 },
	1817	/* d6 */ { illegal, 0 },
	1818	/* d7 */ { illegal, 0 },
	1819	/* d8 */ { illegal, 0 },
	1820	/* d9 */ { illegal, 0 },
	1821	/* da */ { illegal, 0 },
	1822	/* db */ { illegal, 0 },
	1823	/* dc */ { illegal, 0 },
	1824	/* dd */ { illegal, 0 },
	1825	/* de */ { illegal, 0 },
	1826	/* df */ { illegal, 0 },
	1827
	1828	/* e0 */ { illegal, 0 },
	1829	/* e1 */ { illegal, 0 },
	1830	/* e2 */ { illegal, 0 },
	1831	/* e3 */ { illegal, 0 },
	1832	/* e4 */ { illegal, 0 },
	1833	/* e5 */ { illegal, 0 },
	1834	/* e6 */ { illegal, 0 },
	1835	/* e7 */ { illegal, 0 },
	1836	/* e8 */ { illegal, 0 },
	1837	/* e9 */ { illegal, 0 },
	1838	/* ea */ { illegal, 0 },
	1839	/* eb */ { illegal, 0 },
	1840	/* ec */ { illegal, 0 },
	1841	/* ed */ { illegal, 0 },
	1842	/* ee */ { illegal, 0 },
	1843	/* ef */ { illegal, 0 },
	1844
	1845	/* f0 */ { illegal, 0 },
	1846	/* f1 */ { illegal, 0 },
	1847	/* f2 */ { illegal, 0 },
	1848	/* f3 */ { illegal, 0 },
	1849	/* f4 */ { illegal, 0 },
	1850	/* f5 */ { illegal, 0 },
	1851	/* f6 */ { illegal, 0 },
	1852	/* f7 */ { illegal, 0 },
	1853	/* f8 */ { illegal, 0 },
	1854	/* f9 */ { illegal, 0 },
	1855	/* fa */ { illegal, 0 },
	1856	/* fb */ { illegal, 0 },
	1857	/* fc */ { illegal, 0 },
	1858	/* fd */ { illegal, 0 },
	1859	/* fe */ { illegal, 0 },
	1860	/* ff */ { illegal, 0 }
	1861	};
	1862
	1863	offs_t konami_cpu_disassemble(char buffer, offs_t pc, const UINT8 oprom, const UINT8 *opram, UINT32 options)
	1864	{
	1865	buffer[0] = '\0';
	1866
	1867	local_pc = pc;
	1868	byte_count = 1;
	1869	opram_ptr = opram;
	1870	flags = 0;
	1871
	1872	(op_table[*oprom].decode)( buffer );
	1873
	1874	return byte_count \| flags \| DASMFLAG_SUPPORTED;
	1875	}

Property changes on: trunk/src/emu/cpu/m6809/knmidasm.c
Added: svn:mime-type + text/plain Added: svn:eol-style + native

trunk/src/emu/cpu/m6809/konami.h
r0	r21565
	1	/*********************************************************************
	2
	3	konami.h
	4
	5	Portable Konami CPU emulator
	6
	7	**********************************************************************/
	8
	9	#pragma once
	10
	11	#ifndef __KONAMI_CPU_H__
	12	#define __KONAMI_CPU_H__
	13
	14	#include "m6809.h"
	15
	16
	17	//**************************************************************************
	18	// TYPE DEFINITIONS
	19	//**************************************************************************
	20
	21	// callbacks
	22	typedef void (konami_set_lines_func)(device_t device, int lines);
	23	#define KONAMI_SETLINES_CALLBACK(name) void name(device_t *device, int lines)
	24
	25	// device type definition
	26	extern const device_type KONAMI;
	27
	28	// ======================> konami_cpu_device
	29
	30	class konami_cpu_device : public m6809_base_device
	31	{
	32	public:
	33	// construction/destruction
	34	konami_cpu_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
	35
	36	// configuration
	37	void configure_set_lines(konami_set_lines_func func) { m_set_lines = func; }
	38
	39	protected:
	40	// device-level overrides
	41	virtual void device_start();
	42
	43	// device_execute_interface overrides
	44	virtual void execute_run();
	45
	46	// device_disasm_interface overrides
	47	virtual offs_t disasm_disassemble(char buffer, offs_t pc, const UINT8 oprom, const UINT8 *opram, UINT32 options);
	48
	49	private:
	50	typedef m6809_base_device super;
	51
	52	// incidentals
	53	konami_set_lines_func m_set_lines;
	54
	55	// index reg
	56	UINT16 &ireg();
	57
	58	// instructions
	59	void lmul();
	60	void divx();
	61
	62	// miscellaneous
	63	template<class T> T safe_shift_right(T value, UINT32 shift);
	64	template<class T> T safe_shift_left(T value, UINT32 shift);
	65	void set_lines(UINT8 data);
	66	void execute_one();
	67	};
	68
	69	#define KONAMI_IRQ_LINE 0 /* IRQ line number */
	70	#define KONAMI_FIRQ_LINE 1 /* FIRQ line number */
	71
	72
	73	//**************************************************************************
	74	// FUNCTIONS
	75	//**************************************************************************
	76
	77	void konami_configure_set_lines(device_t *device, konami_set_lines_func func);
	78
	79	#endif /* __KONAMI_CPU_H__ */

Property changes on: trunk/src/emu/cpu/m6809/konami.h
Added: svn:mime-type + text/plain Added: svn:eol-style + native

trunk/src/emu/cpu/m6809/6309dasm.c
r0	r21565
	1	/*****************************************************************************
	2
	3	6309dasm.c - a 6309 opcode disassembler
	4	Version 1.0 5-AUG-2000
	5	Copyright Tim Lindner
	6
	7	Based on:
	8	6809dasm.c - a 6809 opcode disassembler
	9	Version 1.4 1-MAR-95
	10	Copyright Sean Riddle
	11
	12	Thanks to Franklin Bowen for bug fixes, ideas
	13
	14	Freely distributable on any medium given all copyrights are retained
	15	by the author and no charge greater than $7.00 is made for obtaining
	16	this software
	17
	18	Please send all bug reports, update ideas and data files to:
	19	tlindner@ix.netcom.com
	20
	21	*****************************************************************************/
	22
	23	#include "emu.h"
	24	#include "debugger.h"
	25	#include "hd6309.h"
	26
	27	// Opcode structure
	28	struct opcodeinfo
	29	{
	30	UINT8 opcode; // 8-bit opcode value
	31	UINT8 length; // Opcode length in bytes
	32	char name[6]; // Opcode name
	33	UINT8 mode; // Addressing mode
	34	unsigned flags; // Disassembly flags
	35	};
	36
	37	enum hd6309_addressing_modes
	38	{
	39	INH, // Inherent
	40	DIR, // Direct
	41	DIR_IM, // Direct in memory (6309 only)
	42	IND, // Indexed
	43	REL, // Relative (8 bit)
	44	LREL, // Long relative (16 bit)
	45	EXT, // Extended
	46	IMM, // Immediate
	47	IMM_RR, // Register-to-register
	48	IMM_BW, // Bitwise operations (6309 only)
	49	IMM_TFM, // Transfer from memory (6309 only)
	50	PG1, // Switch to page 1 opcodes
	51	PG2 // Switch to page 2 opcodes
	52	};
	53
	54	// Page 0 opcodes (single byte)
	55	static const opcodeinfo hd6309_pg0opcodes[] =
	56	{
	57	{ 0x00, 2, "NEG", DIR },
	58	{ 0x01, 3, "OIM", DIR_IM },
	59	{ 0x02, 3, "AIM", DIR_IM },
	60	{ 0x03, 2, "COM", DIR },
	61	{ 0x04, 2, "LSR", DIR },
	62	{ 0x05, 3, "EIM", DIR_IM },
	63	{ 0x06, 2, "ROR", DIR },
	64	{ 0x07, 2, "ASR", DIR },
	65	{ 0x08, 2, "ASL", DIR },
	66	{ 0x09, 2, "ROL", DIR },
	67	{ 0x0A, 2, "DEC", DIR },
	68	{ 0x0B, 3, "TIM", DIR_IM },
	69	{ 0x0C, 2, "INC", DIR },
	70	{ 0x0D, 2, "TST", DIR },
	71	{ 0x0E, 2, "JMP", DIR },
	72	{ 0x0F, 2, "CLR", DIR },
	73
	74	{ 0x10, 1, "page1", PG1 },
	75	{ 0x11, 1, "page2", PG2 },
	76	{ 0x12, 1, "NOP", INH },
	77	{ 0x13, 1, "SYNC", INH },
	78	{ 0x14, 1, "SEXW", INH },
	79	{ 0x16, 3, "LBRA", LREL },
	80	{ 0x17, 3, "LBSR", LREL , DASMFLAG_STEP_OVER },
	81	{ 0x19, 1, "DAA", INH },
	82	{ 0x1A, 2, "ORCC", IMM },
	83	{ 0x1C, 2, "ANDCC", IMM },
	84	{ 0x1D, 1, "SEX", INH },
	85	{ 0x1E, 2, "EXG", IMM_RR },
	86	{ 0x1F, 2, "TFR", IMM_RR },
	87
	88	{ 0x20, 2, "BRA", REL },
	89	{ 0x21, 2, "BRN", REL },
	90	{ 0x22, 2, "BHI", REL },
	91	{ 0x23, 2, "BLS", REL },
	92	{ 0x24, 2, "BCC", REL },
	93	{ 0x25, 2, "BCS", REL },
	94	{ 0x26, 2, "BNE", REL },
	95	{ 0x27, 2, "BEQ", REL },
	96	{ 0x28, 2, "BVC", REL },
	97	{ 0x29, 2, "BVS", REL },
	98	{ 0x2A, 2, "BPL", REL },
	99	{ 0x2B, 2, "BMI", REL },
	100	{ 0x2C, 2, "BGE", REL },
	101	{ 0x2D, 2, "BLT", REL },
	102	{ 0x2E, 2, "BGT", REL },
	103	{ 0x2F, 2, "BLE", REL },
	104
	105	{ 0x30, 2, "LEAX", IND },
	106	{ 0x31, 2, "LEAY", IND },
	107	{ 0x32, 2, "LEAS", IND },
	108	{ 0x33, 2, "LEAU", IND },
	109	{ 0x34, 2, "PSHS", INH },
	110	{ 0x35, 2, "PULS", INH },
	111	{ 0x36, 2, "PSHU", INH },
	112	{ 0x37, 2, "PULU", INH },
	113	{ 0x39, 1, "RTS", INH },
	114	{ 0x3A, 1, "ABX", INH },
	115	{ 0x3B, 1, "RTI", INH },
	116	{ 0x3C, 2, "CWAI", IMM },
	117	{ 0x3D, 1, "MUL", INH },
	118	{ 0x3F, 1, "SWI", INH },
	119
	120	{ 0x40, 1, "NEGA", INH },
	121	{ 0x43, 1, "COMA", INH },
	122	{ 0x44, 1, "LSRA", INH },
	123	{ 0x46, 1, "RORA", INH },
	124	{ 0x47, 1, "ASRA", INH },
	125	{ 0x48, 1, "ASLA", INH },
	126	{ 0x49, 1, "ROLA", INH },
	127	{ 0x4A, 1, "DECA", INH },
	128	{ 0x4C, 1, "INCA", INH },
	129	{ 0x4D, 1, "TSTA", INH },
	130	{ 0x4F, 1, "CLRA", INH },
	131
	132	{ 0x50, 1, "NEGB", INH },
	133	{ 0x53, 1, "COMB", INH },
	134	{ 0x54, 1, "LSRB", INH },
	135	{ 0x56, 1, "RORB", INH },
	136	{ 0x57, 1, "ASRB", INH },
	137	{ 0x58, 1, "ASLB", INH },
	138	{ 0x59, 1, "ROLB", INH },
	139	{ 0x5A, 1, "DECB", INH },
	140	{ 0x5C, 1, "INCB", INH },
	141	{ 0x5D, 1, "TSTB", INH },
	142	{ 0x5F, 1, "CLRB", INH },
	143
	144	{ 0x60, 2, "NEG", IND },
	145	{ 0x61, 3, "OIM", IND },
	146	{ 0x62, 3, "AIM", IND },
	147	{ 0x63, 2, "COM", IND },
	148	{ 0x64, 2, "LSR", IND },
	149	{ 0x65, 3, "EIM", IND },
	150	{ 0x66, 2, "ROR", IND },
	151	{ 0x67, 2, "ASR", IND },
	152	{ 0x68, 2, "ASL", IND },
	153	{ 0x69, 2, "ROL", IND },
	154	{ 0x6A, 2, "DEC", IND },
	155	{ 0x6B, 3, "TIM", IND },
	156	{ 0x6C, 2, "INC", IND },
	157	{ 0x6D, 2, "TST", IND },
	158	{ 0x6E, 2, "JMP", IND },
	159	{ 0x6F, 2, "CLR", IND },
	160
	161	{ 0x70, 3, "NEG", EXT },
	162	{ 0x71, 4, "OIM", EXT },
	163	{ 0x72, 4, "AIM", EXT },
	164	{ 0x73, 3, "COM", EXT },
	165	{ 0x74, 3, "LSR", EXT },
	166	{ 0x75, 4, "EIM", EXT },
	167	{ 0x76, 3, "ROR", EXT },
	168	{ 0x77, 3, "ASR", EXT },
	169	{ 0x78, 3, "ASL", EXT },
	170	{ 0x79, 3, "ROL", EXT },
	171	{ 0x7A, 3, "DEC", EXT },
	172	{ 0x7B, 4, "TIM", EXT },
	173	{ 0x7C, 3, "INC", EXT },
	174	{ 0x7D, 3, "TST", EXT },
	175	{ 0x7E, 3, "JMP", EXT },
	176	{ 0x7F, 3, "CLR", EXT },
	177
	178	{ 0x80, 2, "SUBA", IMM },
	179	{ 0x81, 2, "CMPA", IMM },
	180	{ 0x82, 2, "SBCA", IMM },
	181	{ 0x83, 3, "SUBD", IMM },
	182	{ 0x84, 2, "ANDA", IMM },
	183	{ 0x85, 2, "BITA", IMM },
	184	{ 0x86, 2, "LDA", IMM },
	185	{ 0x88, 2, "EORA", IMM },
	186	{ 0x89, 2, "ADCA", IMM },
	187	{ 0x8A, 2, "ORA", IMM },
	188	{ 0x8B, 2, "ADDA", IMM },
	189	{ 0x8C, 3, "CMPX", IMM },
	190	{ 0x8D, 2, "BSR", REL , DASMFLAG_STEP_OVER },
	191	{ 0x8E, 3, "LDX", IMM },
	192
	193	{ 0x90, 2, "SUBA", DIR },
	194	{ 0x91, 2, "CMPA", DIR },
	195	{ 0x92, 2, "SBCA", DIR },
	196	{ 0x93, 2, "SUBD", DIR },
	197	{ 0x94, 2, "ANDA", DIR },
	198	{ 0x95, 2, "BITA", DIR },
	199	{ 0x96, 2, "LDA", DIR },
	200	{ 0x97, 2, "STA", DIR },
	201	{ 0x98, 2, "EORA", DIR },
	202	{ 0x99, 2, "ADCA", DIR },
	203	{ 0x9A, 2, "ORA", DIR },
	204	{ 0x9B, 2, "ADDA", DIR },
	205	{ 0x9C, 2, "CMPX", DIR },
	206	{ 0x9D, 2, "JSR", DIR , DASMFLAG_STEP_OVER },
	207	{ 0x9E, 2, "LDX", DIR },
	208	{ 0x9F, 2, "STX", DIR },
	209
	210	{ 0xA0, 2, "SUBA", IND },
	211	{ 0xA1, 2, "CMPA", IND },
	212	{ 0xA2, 2, "SBCA", IND },
	213	{ 0xA3, 2, "SUBD", IND },
	214	{ 0xA4, 2, "ANDA", IND },
	215	{ 0xA5, 2, "BITA", IND },
	216	{ 0xA6, 2, "LDA", IND },
	217	{ 0xA7, 2, "STA", IND },
	218	{ 0xA8, 2, "EORA", IND },
	219	{ 0xA9, 2, "ADCA", IND },
	220	{ 0xAA, 2, "ORA", IND },
	221	{ 0xAB, 2, "ADDA", IND },
	222	{ 0xAC, 2, "CMPX", IND },
	223	{ 0xAD, 2, "JSR", IND , DASMFLAG_STEP_OVER },
	224	{ 0xAE, 2, "LDX", IND },
	225	{ 0xAF, 2, "STX", IND },
	226
	227	{ 0xB0, 3, "SUBA", EXT },
	228	{ 0xB1, 3, "CMPA", EXT },
	229	{ 0xB2, 3, "SBCA", EXT },
	230	{ 0xB3, 3, "SUBD", EXT },
	231	{ 0xB4, 3, "ANDA", EXT },
	232	{ 0xB5, 3, "BITA", EXT },
	233	{ 0xB6, 3, "LDA", EXT },
	234	{ 0xB7, 3, "STA", EXT },
	235	{ 0xB8, 3, "EORA", EXT },
	236	{ 0xB9, 3, "ADCA", EXT },
	237	{ 0xBA, 3, "ORA", EXT },
	238	{ 0xBB, 3, "ADDA", EXT },
	239	{ 0xBC, 3, "CMPX", EXT },
	240	{ 0xBD, 3, "JSR", EXT , DASMFLAG_STEP_OVER },
	241	{ 0xBE, 3, "LDX", EXT },
	242	{ 0xBF, 3, "STX", EXT },
	243
	244	{ 0xC0, 2, "SUBB", IMM },
	245	{ 0xC1, 2, "CMPB", IMM },
	246	{ 0xC2, 2, "SBCB", IMM },
	247	{ 0xC3, 3, "ADDD", IMM },
	248	{ 0xC4, 2, "ANDB", IMM },
	249	{ 0xC5, 2, "BITB", IMM },
	250	{ 0xC6, 2, "LDB", IMM },
	251	{ 0xC8, 2, "EORB", IMM },
	252	{ 0xC9, 2, "ADCB", IMM },
	253	{ 0xCA, 2, "ORB", IMM },
	254	{ 0xCB, 2, "ADDB", IMM },
	255	{ 0xCC, 3, "LDD", IMM },
	256	{ 0xCD, 5, "LDQ", IMM },
	257	{ 0xCE, 3, "LDU", IMM },
	258
	259	{ 0xD0, 2, "SUBB", DIR },
	260	{ 0xD1, 2, "CMPB", DIR },
	261	{ 0xD2, 2, "SBCB", DIR },
	262	{ 0xD3, 2, "ADDD", DIR },
	263	{ 0xD4, 2, "ANDB", DIR },
	264	{ 0xD5, 2, "BITB", DIR },
	265	{ 0xD6, 2, "LDB", DIR },
	266	{ 0xD7, 2, "STB", DIR },
	267	{ 0xD8, 2, "EORB", DIR },
	268	{ 0xD9, 2, "ADCB", DIR },
	269	{ 0xDA, 2, "ORB", DIR },
	270	{ 0xDB, 2, "ADDB", DIR },
	271	{ 0xDC, 2, "LDD", DIR },
	272	{ 0xDD, 2, "STD", DIR },
	273	{ 0xDE, 2, "LDU", DIR },
	274	{ 0xDF, 2, "STU", DIR },
	275
	276	{ 0xE0, 2, "SUBB", IND },
	277	{ 0xE1, 2, "CMPB", IND },
	278	{ 0xE2, 2, "SBCB", IND },
	279	{ 0xE3, 2, "ADDD", IND },
	280	{ 0xE4, 2, "ANDB", IND },
	281	{ 0xE5, 2, "BITB", IND },
	282	{ 0xE6, 2, "LDB", IND },
	283	{ 0xE7, 2, "STB", IND },
	284	{ 0xE8, 2, "EORB", IND },
	285	{ 0xE9, 2, "ADCB", IND },
	286	{ 0xEA, 2, "ORB", IND },
	287	{ 0xEB, 2, "ADDB", IND },
	288	{ 0xEC, 2, "LDD", IND },
	289	{ 0xED, 2, "STD", IND },
	290	{ 0xEE, 2, "LDU", IND },
	291	{ 0xEF, 2, "STU", IND },
	292
	293	{ 0xF0, 3, "SUBB", EXT },
	294	{ 0xF1, 3, "CMPB", EXT },
	295	{ 0xF2, 3, "SBCB", EXT },
	296	{ 0xF3, 3, "ADDD", EXT },
	297	{ 0xF4, 3, "ANDB", EXT },
	298	{ 0xF5, 3, "BITB", EXT },
	299	{ 0xF6, 3, "LDB", EXT },
	300	{ 0xF7, 3, "STB", EXT },
	301	{ 0xF8, 3, "EORB", EXT },
	302	{ 0xF9, 3, "ADCB", EXT },
	303	{ 0xFA, 3, "ORB", EXT },
	304	{ 0xFB, 3, "ADDB", EXT },
	305	{ 0xFC, 3, "LDD", EXT },
	306	{ 0xFD, 3, "STD", EXT },
	307	{ 0xFE, 3, "LDU", EXT },
	308	{ 0xFF, 3, "STU", EXT }
	309	};
	310
	311	// Page 1 opcodes (0x10 0x..)
	312	static const opcodeinfo hd6309_pg1opcodes[] =
	313	{
	314	{ 0x21, 4, "LBRN", LREL },
	315	{ 0x22, 4, "LBHI", LREL },
	316	{ 0x23, 4, "LBLS", LREL },
	317	{ 0x24, 4, "LBCC", LREL },
	318	{ 0x25, 4, "LBCS", LREL },
	319	{ 0x26, 4, "LBNE", LREL },
	320	{ 0x27, 4, "LBEQ", LREL },
	321	{ 0x28, 4, "LBVC", LREL },
	322	{ 0x29, 4, "LBVS", LREL },
	323	{ 0x2A, 4, "LBPL", LREL },
	324	{ 0x2B, 4, "LBMI", LREL },
	325	{ 0x2C, 4, "LBGE", LREL },
	326	{ 0x2D, 4, "LBLT", LREL },
	327	{ 0x2E, 4, "LBGT", LREL },
	328	{ 0x2F, 4, "LBLE", LREL },
	329
	330	{ 0x30, 3, "ADDR", IMM_RR },
	331	{ 0x31, 3, "ADCR", IMM_RR },
	332	{ 0x32, 3, "SUBR", IMM_RR },
	333	{ 0x33, 3, "SBCR", IMM_RR },
	334	{ 0x34, 3, "ANDR", IMM_RR },
	335	{ 0x35, 3, "ORR", IMM_RR },
	336	{ 0x36, 3, "EORR", IMM_RR },
	337	{ 0x37, 3, "CMPR", IMM_RR },
	338
	339	{ 0x38, 2, "PSHSW", INH },
	340	{ 0x39, 2, "PULSW", INH },
	341	{ 0x3A, 2, "PSHUW", INH },
	342	{ 0x3B, 2, "PULUW", INH },
	343
	344	{ 0x3F, 2, "SWI2", INH },
	345
	346	{ 0x40, 2, "NEGD", INH },
	347	{ 0x43, 2, "COMD", INH },
	348	{ 0x44, 2, "LSRD", INH },
	349	{ 0x46, 2, "RORD", INH },
	350	{ 0x47, 2, "ASRD", INH },
	351	{ 0x48, 2, "ASLD", INH },
	352	{ 0x49, 2, "ROLD", INH },
	353
	354	{ 0x4A, 2, "DECD", INH },
	355	{ 0x4C, 2, "INCD", INH },
	356	{ 0x4D, 2, "TSTD", INH },
	357	{ 0x4f, 2, "CLRD", INH },
	358
	359	{ 0x53, 2, "COMW", INH },
	360	{ 0x54, 2, "LSRW", INH },
	361	{ 0x56, 2, "RORW", INH },
	362	{ 0x59, 2, "ROLW", INH },
	363	{ 0x5A, 2, "DECW", INH },
	364	{ 0x5C, 2, "INCW", INH },
	365	{ 0x5D, 2, "TSTW", INH },
	366	{ 0x5F, 2, "CLRW", INH },
	367	{ 0x80, 4, "SUBW", IMM },
	368	{ 0x81, 4, "CMPW", IMM },
	369	{ 0x82, 4, "SBCD", IMM },
	370
	371	{ 0x83, 4, "CMPD", IMM },
	372
	373	{ 0x84, 4, "ANDD", IMM },
	374	{ 0x85, 4, "BITD", IMM },
	375	{ 0x86, 4, "LDW", IMM },
	376	{ 0x88, 4, "EORD", IMM },
	377	{ 0x89, 4, "ADCD", IMM },
	378	{ 0x8A, 4, "ORD", IMM },
	379	{ 0x8B, 4, "ADDW", IMM },
	380
	381	{ 0x8C, 4, "CMPY", IMM },
	382	{ 0x8E, 4, "LDY", IMM },
	383
	384	{ 0x90, 3, "SUBW", DIR },
	385	{ 0x91, 3, "CMPW", DIR },
	386	{ 0x92, 3, "SBCD", DIR },
	387
	388	{ 0x93, 3, "CMPD", DIR },
	389
	390	{ 0x94, 3, "ANDD", DIR },
	391	{ 0x95, 3, "BITD", DIR },
	392	{ 0x96, 3, "LDW", DIR },
	393	{ 0x97, 3, "STW", DIR },
	394	{ 0x98, 3, "EORD", DIR },
	395	{ 0x99, 3, "ADCD", DIR },
	396	{ 0x9A, 3, "ORD", DIR },
	397	{ 0x9B, 3, "ADDW", DIR },
	398
	399	{ 0x9C, 3, "CMPY", DIR },
	400	{ 0x9E, 3, "LDY", DIR },
	401	{ 0x9F, 3, "STY", DIR },
	402
	403	{ 0xA0, 3, "SUBW", IND },
	404	{ 0xA1, 3, "CMPW", IND },
	405	{ 0xA2, 3, "SBCD", IND },
	406
	407	{ 0xA3, 3, "CMPD", IND },
	408
	409	{ 0xA4, 3, "ANDD", IND },
	410	{ 0xA5, 3, "BITD", IND },
	411
	412	{ 0xA6, 3, "LDW", IND },
	413	{ 0xA7, 3, "STW", IND },
	414	{ 0xA8, 3, "EORD", IND },
	415	{ 0xA9, 3, "ADCD", IND },
	416	{ 0xAA, 3, "ORD", IND },
	417	{ 0xAB, 3, "ADDW", IND },
	418
	419	{ 0xAC, 3, "CMPY", IND },
	420	{ 0xAE, 3, "LDY", IND },
	421	{ 0xAF, 3, "STY", IND },
	422
	423	{ 0xB0, 4, "SUBW", EXT },
	424	{ 0xB1, 4, "CMPW", EXT },
	425	{ 0xB2, 4, "SBCD", EXT },
	426
	427	{ 0xB3, 4, "CMPD", EXT },
	428
	429	{ 0xB4, 4, "ANDD", EXT },
	430	{ 0xB5, 4, "BITD", EXT },
	431	{ 0xB6, 4, "LDW", EXT },
	432	{ 0xB7, 4, "STW", EXT },
	433	{ 0xB8, 4, "EORD", EXT },
	434	{ 0xB9, 4, "ADCD", EXT },
	435	{ 0xBA, 4, "ORD", EXT },
	436	{ 0xBB, 4, "ADDW", EXT },
	437
	438	{ 0xBC, 4, "CMPY", EXT },
	439	{ 0xBE, 4, "LDY", EXT },
	440	{ 0xBF, 4, "STY", EXT },
	441	{ 0xCE, 4, "LDS", IMM },
	442
	443	{ 0xDC, 3, "LDQ", DIR },
	444	{ 0xDD, 3, "STQ", DIR },
	445
	446	{ 0xDE, 3, "LDS", DIR },
	447	{ 0xDF, 3, "STS", DIR },
	448
	449	{ 0xEC, 3, "LDQ", IND },
	450	{ 0xED, 3, "STQ", IND },
	451	{ 0xEE, 3, "LDS", IND },
	452
	453	{ 0xEE, 3, "LDS", IND },
	454	{ 0xEF, 3, "STS", IND },
	455
	456	{ 0xFC, 4, "LDQ", EXT },
	457	{ 0xFD, 4, "STQ", EXT },
	458
	459	{ 0xFE, 4, "LDS", EXT },
	460	{ 0xFF, 4, "STS", EXT }
	461	};
	462
	463	// Page 2 opcodes (0x11 0x..)
	464	static const opcodeinfo hd6309_pg2opcodes[] =
	465	{
	466	{ 0x30, 4, "BAND", IMM_BW },
	467	{ 0x31, 4, "BIAND", IMM_BW },
	468	{ 0x32, 4, "BOR", IMM_BW },
	469	{ 0x33, 4, "BIOR", IMM_BW },
	470	{ 0x34, 4, "BEOR", IMM_BW },
	471	{ 0x35, 4, "BIEOR", IMM_BW },
	472
	473	{ 0x36, 4, "LDBT", IMM_BW },
	474	{ 0x37, 4, "STBT", IMM_BW },
	475
	476	{ 0x38, 3, "TFM", IMM_TFM },
	477	{ 0x39, 3, "TFM", IMM_TFM },
	478	{ 0x3A, 3, "TFM", IMM_TFM },
	479	{ 0x3B, 3, "TFM", IMM_TFM },
	480
	481	{ 0x3C, 3, "BITMD", IMM },
	482	{ 0x3D, 3, "LDMD", IMM },
	483
	484	{ 0x3F, 2, "SWI3", INH },
	485
	486	{ 0x43, 2, "COME", INH },
	487	{ 0x4A, 2, "DECE", INH },
	488	{ 0x4C, 2, "INCE", INH },
	489	{ 0x4D, 2, "TSTE", INH },
	490	{ 0x4F, 2, "CLRE", INH },
	491	{ 0x53, 2, "COMF", INH },
	492	{ 0x5A, 2, "DECF", INH },
	493	{ 0x5C, 2, "INCF", INH },
	494	{ 0x5D, 2, "TSTF", INH },
	495	{ 0x5F, 2, "CLRF", INH },
	496
	497	{ 0x80, 3, "SUBE", IMM },
	498	{ 0x81, 3, "CMPE", IMM },
	499
	500	{ 0x83, 4, "CMPU", IMM },
	501
	502	{ 0x86, 3, "LDE", IMM },
	503	{ 0x8b, 3, "ADDE", IMM },
	504
	505	{ 0x8C, 4, "CMPS", IMM },
	506
	507	{ 0x8D, 3, "DIVD", IMM },
	508	{ 0x8E, 4, "DIVQ", IMM },
	509	{ 0x8F, 4, "MULD", IMM },
	510	{ 0x90, 3, "SUBE", DIR },
	511	{ 0x91, 3, "CMPE", DIR },
	512
	513	{ 0x93, 3, "CMPU", DIR },
	514
	515	{ 0x96, 3, "LDE", DIR },
	516	{ 0x97, 3, "STE", DIR },
	517	{ 0x9B, 3, "ADDE", DIR },
	518
	519	{ 0x9C, 3, "CMPS", DIR },
	520
	521	{ 0x9D, 3, "DIVD", DIR },
	522	{ 0x9E, 3, "DIVQ", DIR },
	523	{ 0x9F, 3, "MULD", DIR },
	524
	525	{ 0xA0, 3, "SUBE", IND },
	526	{ 0xA1, 3, "CMPE", IND },
	527
	528	{ 0xA3, 3, "CMPU", IND },
	529
	530	{ 0xA6, 3, "LDE", IND },
	531	{ 0xA7, 3, "STE", IND },
	532	{ 0xAB, 3, "ADDE", IND },
	533
	534	{ 0xAC, 3, "CMPS", IND },
	535
	536	{ 0xAD, 3, "DIVD", IND },
	537	{ 0xAE, 3, "DIVQ", IND },
	538	{ 0xAF, 3, "MULD", IND },
	539	{ 0xB0, 4, "SUBE", EXT },
	540	{ 0xB1, 4, "CMPE", EXT },
	541
	542	{ 0xB3, 4, "CMPU", EXT },
	543
	544	{ 0xB6, 4, "LDE", EXT },
	545	{ 0xB7, 4, "STE", EXT },
	546
	547	{ 0xBB, 4, "ADDE", EXT },
	548	{ 0xBC, 4, "CMPS", EXT },
	549
	550	{ 0xBD, 4, "DIVD", EXT },
	551	{ 0xBE, 4, "DIVQ", EXT },
	552	{ 0xBF, 4, "MULD", EXT },
	553
	554	{ 0xC0, 3, "SUBF", IMM },
	555	{ 0xC1, 3, "CMPF", IMM },
	556	{ 0xC6, 3, "LDF", IMM },
	557	{ 0xCB, 3, "ADDF", IMM },
	558
	559	{ 0xD0, 3, "SUBF", DIR },
	560	{ 0xD1, 3, "CMPF", DIR },
	561	{ 0xD6, 3, "LDF", DIR },
	562	{ 0xD7, 3, "STF", DIR },
	563	{ 0xDB, 3, "ADDF", DIR },
	564
	565	{ 0xE0, 3, "SUBF", IND },
	566	{ 0xE1, 3, "CMPF", IND },
	567	{ 0xE6, 3, "LDF", IND },
	568	{ 0xE7, 3, "STF", IND },
	569	{ 0xEB, 3, "ADDF", IND },
	570
	571	{ 0xF0, 4, "SUBF", EXT },
	572	{ 0xF1, 4, "CMPF", EXT },
	573	{ 0xF6, 4, "LDF", EXT },
	574	{ 0xF7, 4, "STF", EXT },
	575	{ 0xFB, 4, "ADDF", EXT }
	576	};
	577
	578	static const opcodeinfo *const hd6309_pgpointers[3] =
	579	{
	580	hd6309_pg0opcodes, hd6309_pg1opcodes, hd6309_pg2opcodes
	581	};
	582
	583	static const int hd6309_numops[3] =
	584	{
	585	sizeof(hd6309_pg0opcodes) / sizeof(hd6309_pg0opcodes[0]),
	586	sizeof(hd6309_pg1opcodes) / sizeof(hd6309_pg1opcodes[0]),
	587	sizeof(hd6309_pg2opcodes) / sizeof(hd6309_pg2opcodes[0])
	588	};
	589
	590	static const char *const hd6309_regs[5] = { "X", "Y", "U", "S", "PC" };
	591
	592	static const char *const hd6309_btwregs[5] = { "CC", "A", "B", "inv" };
	593
	594	static const char *const hd6309_teregs[16] =
	595	{
	596	"D", "X", "Y", "U", "S", "PC", "W", "V",
	597	"A", "B", "CC", "DP", "0", "0", "E", "F"
	598	};
	599
	600	static const char *const hd6309_tfmregs[16] = {
	601	"D", "X", "Y", "U", "S", "inv", "inv", "inv",
	602	"inv", "inv", "inv", "inv", "inv", "inv", "inv", "inv"
	603	};
	604
	605	static const char *const tfm_s[] = { "%s+,%s+", "%s-,%s-", "%s+,%s", "%s,%s+" };
	606
	607	offs_t hd6309_disassemble(char buffer, offs_t pc, const UINT8 oprom, const UINT8 *opram, UINT32 options)
	608	{
	609	UINT8 opcode, mode, pb, pbm, reg;
	610	const UINT8 *operandarray;
	611	unsigned int ea, flags;
	612	int numoperands, offset, indirect;
	613
	614	int i, p = 0, page = 0, opcode_found = FALSE;
	615
	616	do
	617	{
	618	opcode = oprom[p++];
	619	for (i = 0; i < hd6309_numops[page]; i++)
	620	if (hd6309_pgpointers[page][i].opcode == opcode)
	621	break;
	622
	623	if (i < hd6309_numops[page])
	624	opcode_found = TRUE;
	625	else
	626	{
	627	strcpy(buffer, "Illegal Opcode");
	628	return p \| DASMFLAG_SUPPORTED;
	629	}
	630
	631	if (hd6309_pgpointers[page][i].mode >= PG1)
	632	{
	633	page = hd6309_pgpointers[page][i].mode - PG1 + 1;
	634	opcode_found = FALSE;
	635	}
	636	} while (!opcode_found);
	637
	638	if (page == 0)
	639	numoperands = hd6309_pgpointers[page][i].length - 1;
	640	else
	641	numoperands = hd6309_pgpointers[page][i].length - 2;
	642
	643	operandarray = &opram[p];
	644	p += numoperands;
	645	pc += p;
	646	mode = hd6309_pgpointers[page][i].mode;
	647	flags = hd6309_pgpointers[page][i].flags;
	648
	649	buffer += sprintf(buffer, "%-6s", hd6309_pgpointers[page][i].name);
	650
	651	switch (mode)
	652	{
	653	case INH:
	654	switch (opcode)
	655	{
	656	case 0x34: // PSHS
	657	case 0x36: // PSHU
	658	pb = operandarray[0];
	659	if (pb & 0x80)
	660	buffer += sprintf(buffer, "PC");
	661	if (pb & 0x40)
	662	buffer += sprintf(buffer, "%s%s", (pb&0x80)?",":"", (opcode==0x34)?"U":"S");
	663	if (pb & 0x20)
	664	buffer += sprintf(buffer, "%sY", (pb&0xc0)?",":"");
	665	if (pb & 0x10)
	666	buffer += sprintf(buffer, "%sX", (pb&0xe0)?",":"");
	667	if (pb & 0x08)
	668	buffer += sprintf(buffer, "%sDP", (pb&0xf0)?",":"");
	669	if (pb & 0x04)
	670	buffer += sprintf(buffer, "%sB", (pb&0xf8)?",":"");
	671	if (pb & 0x02)
	672	buffer += sprintf(buffer, "%sA", (pb&0xfc)?",":"");
	673	if (pb & 0x01)
	674	buffer += sprintf(buffer, "%sCC", (pb&0xfe)?",":"");
	675	break;
	676	case 0x35: // PULS
	677	case 0x37: // PULU
	678	pb = operandarray[0];
	679	if (pb & 0x01)
	680	buffer += sprintf(buffer, "CC");
	681	if (pb & 0x02)
	682	buffer += sprintf(buffer, "%sA", (pb&0x01)?",":"");
	683	if (pb & 0x04)
	684	buffer += sprintf(buffer, "%sB", (pb&0x03)?",":"");
	685	if (pb & 0x08)
	686	buffer += sprintf(buffer, "%sDP", (pb&0x07)?",":"");
	687	if (pb & 0x10)
	688	buffer += sprintf(buffer, "%sX", (pb&0x0f)?",":"");
	689	if (pb & 0x20)
	690	buffer += sprintf(buffer, "%sY", (pb&0x1f)?",":"");
	691	if (pb & 0x40)
	692	buffer += sprintf(buffer, "%s%s", (pb&0x3f)?",":"", (opcode==0x35)?"U":"S");
	693	if (pb & 0x80)
	694	buffer += sprintf(buffer, "%sPC ; (PUL? PC=RTS)", (pb&0x7f)?",":"");
	695	break;
	696	default:
	697	// No operands
	698	break;
	699	}
	700	break;
	701
	702	case DIR:
	703	ea = operandarray[0];
	704	buffer += sprintf(buffer, "$%02X", ea);
	705	break;
	706
	707	case DIR_IM:
	708	buffer += sprintf(buffer, "#$%02X,", operandarray[0]);
	709	buffer += sprintf(buffer, "$%02X", operandarray[1]);
	710	break;
	711
	712	case REL:
	713	offset = (INT8)operandarray[0];
	714	buffer += sprintf(buffer, "$%04X", (pc + offset) & 0xffff);
	715	break;
	716
	717	case LREL:
	718	offset = (INT16)((operandarray[0] << 8) + operandarray[1]);
	719	buffer += sprintf(buffer, "$%04X", (pc + offset) & 0xffff);
	720	break;
	721
	722	case EXT:
	723	if (numoperands == 3)
	724	{
	725	pb = operandarray[0];
	726	ea = (operandarray[1] << 8) + operandarray[2];
	727	buffer += sprintf(buffer, "#$%02X,$%04X", pb, ea);
	728	}
	729	else
	730	if (numoperands == 2)
	731	{
	732	ea = (operandarray[0] << 8) + operandarray[1];
	733	buffer += sprintf(buffer, "$%04X", ea);
	734	}
	735	break;
	736
	737	case IND:
	738	if (numoperands == 2)
	739	{
	740	buffer += sprintf(buffer, "#$%02X,", operandarray[0]);
	741	pb = operandarray[1];
	742	}
	743	else
	744	{
	745	pb = operandarray[0];
	746	}
	747
	748	reg = (pb >> 5) & 3;
	749	pbm = pb & 0x8f;
	750	indirect = ((pb & 0x90) == 0x90 )? TRUE : FALSE;
	751
	752	// open brackets if indirect
	753	if (indirect && pbm != 0x82)
	754	buffer += sprintf(buffer, "[");
	755
	756	switch (pbm)
	757	{
	758	case 0x80: // ,R+ or operations relative to W
	759	if (indirect)
	760	{
	761	switch (reg)
	762	{
	763	case 0x00:
	764	buffer += sprintf(buffer, ",W");
	765	break;
	766	case 0x01:
	767	offset = (INT16)((opram[p+0] << 8) + opram[p+1]);
	768	p += 2;
	769	buffer += sprintf(buffer, "%s", (offset < 0) ? "-" : "");
	770	buffer += sprintf(buffer, "$%04X,W", (offset < 0) ? -offset : offset);
	771	break;
	772	case 0x02:
	773	buffer += sprintf(buffer, ",W++");
	774	break;
	775	case 0x03:
	776	buffer += sprintf(buffer, ",--W");
	777	break;
	778	}
	779	}
	780	else
	781	buffer += sprintf(buffer, ",%s+", hd6309_regs[reg]);
	782	break;
	783
	784	case 0x81: // ,R++
	785	buffer += sprintf(buffer, ",%s++", hd6309_regs[reg]);
	786	break;
	787
	788	case 0x82: // ,-R
	789	if (indirect)
	790	strcpy(buffer, "Illegal Postbyte");
	791	else
	792	buffer += sprintf(buffer, ",-%s", hd6309_regs[reg]);
	793	break;
	794
	795	case 0x83: // ,--R
	796	buffer += sprintf(buffer, ",--%s", hd6309_regs[reg]);
	797	break;
	798
	799	case 0x84: // ,R
	800	buffer += sprintf(buffer, ",%s", hd6309_regs[reg]);
	801	break;
	802
	803	case 0x85: // (+/- B),R
	804	buffer += sprintf(buffer, "B,%s", hd6309_regs[reg]);
	805	break;
	806
	807	case 0x86: // (+/- A),R
	808	buffer += sprintf(buffer, "A,%s", hd6309_regs[reg]);
	809	break;
	810
	811	case 0x87: // (+/- E),R
	812	buffer += sprintf(buffer, "E,%s", hd6309_regs[reg]);
	813	break;
	814
	815	case 0x88: // (+/- 7 bit offset),R
	816	offset = (INT8)opram[p++];
	817	buffer += sprintf(buffer, "%s", (offset < 0) ? "-" : "");
	818	buffer += sprintf(buffer, "$%02X,", (offset < 0) ? -offset : offset);
	819	buffer += sprintf(buffer, "%s", hd6309_regs[reg]);
	820	break;
	821
	822	case 0x89: // (+/- 15 bit offset),R
	823	offset = (INT16)((opram[p+0] << 8) + opram[p+1]);
	824	p += 2;
	825	buffer += sprintf(buffer, "%s", (offset < 0) ? "-" : "");
	826	buffer += sprintf(buffer, "$%04X,", (offset < 0) ? -offset : offset);
	827	buffer += sprintf(buffer, "%s", hd6309_regs[reg]);
	828	break;
	829
	830	case 0x8a: // (+/- F),R
	831	buffer += sprintf(buffer, "F,%s", hd6309_regs[reg]);
	832	break;
	833
	834	case 0x8b: // (+/- D),R
	835	buffer += sprintf(buffer, "D,%s", hd6309_regs[reg]);
	836	break;
	837
	838	case 0x8c: // (+/- 7 bit offset),PC
	839	offset = (INT8)opram[p++];
	840	buffer += sprintf(buffer, "%s", (offset < 0) ? "-" : "");
	841	buffer += sprintf(buffer, "$%02X,PC", (offset < 0) ? -offset : offset);
	842	break;
	843
	844	case 0x8d: // (+/- 15 bit offset),PC
	845	offset = (INT16)((opram[p+0] << 8) + opram[p+1]);
	846	p += 2;
	847	buffer += sprintf(buffer, "%s", (offset < 0) ? "-" : "");
	848	buffer += sprintf(buffer, "$%04X,PC", (offset < 0) ? -offset : offset);
	849	break;
	850
	851	case 0x8e: // (+/- W),R
	852	buffer += sprintf(buffer, "W,%s", hd6309_regs[reg]);
	853	break;
	854
	855	case 0x8f: // address or operations relative to W
	856	if (indirect)
	857	{
	858	ea = (UINT16)((opram[p+0] << 8) + opram[p+1]);
	859	p += 2;
	860	buffer += sprintf(buffer, "$%04X", ea);
	861	break;
	862	}
	863	else
	864	{
	865	switch (reg)
	866	{
	867	case 0x00:
	868	buffer += sprintf(buffer, ",W");
	869	break;
	870	case 0x01:
	871	offset = (INT16)((opram[p+0] << 8) + opram[p+1]);
	872	p += 2;
	873	buffer += sprintf(buffer, "%s", (offset < 0) ? "-" : "");
	874	buffer += sprintf(buffer, "$%04X,W", (offset < 0) ? -offset : offset);
	875	break;
	876	case 0x02:
	877	buffer += sprintf(buffer, ",W++");
	878	break;
	879	case 0x03:
	880	buffer += sprintf(buffer, ",--W");
	881	break;
	882	}
	883	}
	884	break;
	885
	886	default: // (+/- 4 bit offset),R
	887	offset = pb & 0x1f;
	888	if (offset > 15)
	889	offset = offset - 32;
	890	buffer += sprintf(buffer, "%s", (offset < 0) ? "-" : "");
	891	buffer += sprintf(buffer, "$%X,", (offset < 0) ? -offset : offset);
	892	buffer += sprintf(buffer, "%s", hd6309_regs[reg]);
	893	break;
	894	}
	895
	896	// close brackets if indirect
	897	if (indirect && pbm != 0x82)
	898	buffer += sprintf(buffer, "]");
	899	break;
	900
	901	case IMM:
	902	if (numoperands == 4)
	903	{
	904	ea = (operandarray[0] << 24) + (operandarray[1] << 16) + (operandarray[2] << 8) + operandarray[3];
	905	buffer += sprintf(buffer, "#$%08X", ea);
	906	}
	907	else
	908	if (numoperands == 2)
	909	{
	910	ea = (operandarray[0] << 8) + operandarray[1];
	911	buffer += sprintf(buffer, "#$%04X", ea);
	912	}
	913	else
	914	if (numoperands == 1)
	915	{
	916	ea = operandarray[0];
	917	buffer += sprintf(buffer, "#$%02X", ea);
	918	}
	919	break;
	920
	921	case IMM_RR:
	922	pb = operandarray[0];
	923	buffer += sprintf(buffer, "%s,%s", hd6309_teregs[(pb >> 4) & 0xf], hd6309_teregs[pb & 0xf]);
	924	break;
	925
	926	case IMM_BW:
	927	pb = operandarray[0];
	928	buffer += sprintf(buffer, "%s,", hd6309_btwregs[((pb & 0xc0) >> 6)]);
	929	buffer += sprintf(buffer, "%d,", (pb & 0x38) >> 3);
	930	buffer += sprintf(buffer, "%d,", (pb & 0x07));
	931	buffer += sprintf(buffer, "$%02X", operandarray[1]);
	932	break;
	933
	934	case IMM_TFM:
	935	pb = operandarray[0];
	936	buffer += sprintf(buffer, tfm_s[opcode & 0x07], hd6309_tfmregs[(pb >> 4) & 0xf], hd6309_tfmregs[pb & 0xf]);
	937	break;
	938	}
	939
	940	return p \| flags \| DASMFLAG_SUPPORTED;
	941	}

Property changes on: trunk/src/emu/cpu/m6809/6309dasm.c
Added: svn:mime-type + text/plain Added: svn:eol-style + native

trunk/src/emu/cpu/cpu.mak
r21564	r21565
443	443
444	444
445	445	#-------------------------------------------------
446		# Hitachi 6309
447		#-------------------------------------------------
448
449		ifneq ($(filter HD6309,$(CPUS)),)
450		OBJDIRS += $(CPUOBJ)/hd6309
451		CPUOBJS += $(CPUOBJ)/hd6309/hd6309.o
452		DASMOBJS += $(CPUOBJ)/hd6309/6309dasm.o
453		endif
454
455		$(CPUOBJ)/hd6309/hd6309.o: $(CPUSRC)/hd6309/hd6309.c \
456		$(CPUSRC)/hd6309/hd6309.h \
457		$(CPUSRC)/hd6309/6309ops.c \
458		$(CPUSRC)/hd6309/6309tbl.c
459
460
461		#-------------------------------------------------
462	446	# Hitachi H8/30xx (16/32-bit H8/3xx series)
463	447	#-------------------------------------------------
464	448
r21564	r21565
834	818
835	819
836	820	#-------------------------------------------------
837		# Konami custom CPU (6809-based)
838		#-------------------------------------------------
839
840		ifneq ($(filter KONAMI,$(CPUS)),)
841		OBJDIRS += $(CPUOBJ)/konami
842		CPUOBJS += $(CPUOBJ)/konami/konami.o
843		DASMOBJS += $(CPUOBJ)/konami/knmidasm.o
844		endif
845
846		$(CPUOBJ)/konami/konami.o: $(CPUSRC)/konami/konami.c \
847		$(CPUSRC)/konami/konami.h \
848		$(CPUSRC)/konami/konamops.c \
849		$(CPUSRC)/konami/konamtbl.c
850
851
852
853		#-------------------------------------------------
854	821	# LH5801
855	822	#-------------------------------------------------
856	823
r21564	r21565
1229	1196
1230	1197	ifneq ($(filter M6809,$(CPUS)),)
1231	1198	OBJDIRS += $(CPUOBJ)/m6809
1232		CPUOBJS += $(CPUOBJ)/m6809/m6809.o
1233		DASMOBJS += $(CPUOBJ)/m6809/6809dasm.o
	1199	CPUOBJS += $(CPUOBJ)/m6809/m6809.o $(CPUOBJ)/m6809/hd6309.o $(CPUOBJ)/m6809/konami.o
	1200	DASMOBJS += $(CPUOBJ)/m6809/6809dasm.o $(CPUOBJ)/m6809/6309dasm.o $(CPUOBJ)/m6809/knmidasm.o
1234	1201	endif
1235	1202
1236	1203	$(CPUOBJ)/m6809/m6809.o: $(CPUSRC)/m6809/m6809.c \
1237	1204	$(CPUSRC)/m6809/m6809.h \
1238		$(CPUSRC)/m6809/6809ops.c \
1239		$(CPUSRC)/m6809/6809tbl.c
	1205	$(CPUSRC)/m6809/m6809inl.h \
	1206	$(CPUOBJ)/m6809/m6809.inc
1240	1207
	1208	$(CPUOBJ)/m6809/hd6309.o: $(CPUSRC)/m6809/hd6309.c \
	1209	$(CPUSRC)/m6809/hd6309.h \
	1210	$(CPUSRC)/m6809/m6809.h \
	1211	$(CPUSRC)/m6809/m6809inl.h \
	1212	$(CPUOBJ)/m6809/hd6309.inc
1241	1213
1242	1214
	1215	$(CPUOBJ)/m6809/konami.o: $(CPUSRC)/m6809/konami.c \
	1216	$(CPUSRC)/m6809/konami.h \
	1217	$(CPUSRC)/m6809/m6809.h \
	1218	$(CPUSRC)/m6809/m6809inl.h \
	1219	$(CPUOBJ)/m6809/konami.inc
	1220
	1221	$(CPUOBJ)/m6809/m6809.inc: $(CPUSRC)/m6809/m6809make.py $(CPUSRC)/m6809/m6809.ops $(CPUSRC)/m6809/base6x09.ops
	1222	@echo Generating m6809 source file...
	1223	@gcc -x c -P -E $(CPUSRC)/m6809/m6809.ops \| $(PYTHON) $(CPUSRC)/m6809/m6809make.py > $@
	1224
	1225	$(CPUOBJ)/m6809/hd6309.inc: $(CPUSRC)/m6809/m6809make.py $(CPUSRC)/m6809/hd6309.ops $(CPUSRC)/m6809/base6x09.ops
	1226	@echo Generating hd6309 source file...
	1227	@gcc -x c -P -E $(CPUSRC)/m6809/hd6309.ops \| $(PYTHON) $(CPUSRC)/m6809/m6809make.py > $@
	1228
	1229	$(CPUOBJ)/m6809/konami.inc: $(CPUSRC)/m6809/m6809make.py $(CPUSRC)/m6809/konami.ops $(CPUSRC)/m6809/base6x09.ops
	1230	@echo Generating konami source file...
	1231	@gcc -x c -P -E $(CPUSRC)/m6809/konami.ops \| $(PYTHON) $(CPUSRC)/m6809/m6809make.py > $@
	1232
	1233
	1234
1243	1235	#-------------------------------------------------
1244	1236	# Motorola 68HC11
1245	1237	#-------------------------------------------------

trunk/src/mess/drivers/coco3.c
r21564	r21565
12	12
13	13	#include "includes/coco3.h"
14	14	#include "cpu/m6809/m6809.h"
15		#include "cpu/hd6309/hd6309.h"
	15	#include "cpu/m6809/hd6309.h"
16	16	#include "coco3.lh"
17	17
18	18

199869 Revisions