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r21499 Friday 1st March, 2013 at 01:20:43 UTC by R. Belmont
(MESS) Reimplemented the NCR5380 SCSI controller using nscsi. [R. Belmont]
[src/mess]mess.mak
[src/mess/machine]ncr5380n.c* ncr5380n.h*

trunk/src/mess/machine/ncr5380n.c
r0r21499
1/*********************************************************************
2
3    ncr5380n.c
4
5    Implementation of the NCR 5380, aka the Zilog Z5380
6 
7    TODO:
8    - IRQs (Apple doesn't use 'em)
9    - Target mode
10 
11*********************************************************************/
12
13#include "emu.h"
14#include "ncr5380n.h"
15
16const device_type NCR5380N = &device_creator<ncr5380n_device>;
17
18DEVICE_ADDRESS_MAP_START(map, 8, ncr5380n_device)
19   AM_RANGE(0x0, 0x0) AM_READWRITE(scsidata_r, outdata_w)
20   AM_RANGE(0x1, 0x1) AM_READWRITE(icmd_r, icmd_w)
21   AM_RANGE(0x2, 0x2) AM_READWRITE(mode_r, mode_w)
22   AM_RANGE(0x3, 0x3) AM_READWRITE(command_r, command_w)
23   AM_RANGE(0x4, 0x4) AM_READWRITE(status_r, selenable_w)
24   AM_RANGE(0x5, 0x5) AM_READWRITE(busandstatus_r, startdmasend_w)
25   AM_RANGE(0x6, 0x6) AM_READWRITE(indata_r, startdmatargetrx_w)
26   AM_RANGE(0x7, 0x7) AM_READWRITE(resetparityirq_r, startdmainitrx_w)
27ADDRESS_MAP_END
28
29ncr5380n_device::ncr5380n_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
30      : nscsi_device(mconfig, NCR5380N, "5380 SCSI (new)", tag, owner, clock)
31{
32}
33
34void ncr5380n_device::device_start()
35{
36   save_item(NAME(m_tcommand));
37   save_item(NAME(m_icommand));
38   save_item(NAME(status));
39   save_item(NAME(istatus));
40   save_item(NAME(m_busstatus));
41   save_item(NAME(tcount));
42   save_item(NAME(mode));
43   save_item(NAME(irq));
44   save_item(NAME(drq));
45   save_item(NAME(clock_conv));
46   save_item(NAME(m_dmalatch));
47
48   m_irq_func.resolve(m_irq_cb, *this);
49   m_drq_func.resolve(m_drq_cb, *this);
50
51   tcount = 0;
52   status = 0;
53   bus_id = 0;
54   select_timeout = 0;
55   tm = timer_alloc(0);
56}
57
58void ncr5380n_device::device_reset()
59{
60   clock_conv = 2;
61   sync_period = 5;
62   sync_offset = 0;
63   seq = 0;
64   status = 0;
65   m_tcommand = 0;
66   m_icommand = 0;
67   istatus = 0;
68   m_busstatus = 0;
69   irq = false;
70   if(!m_irq_func.isnull())
71      m_irq_func(irq);
72   reset_soft();
73}
74
75void ncr5380n_device::device_config_complete()
76{
77   // inherit a copy of the static data
78   const ncr5380n_interface *intf = reinterpret_cast<const ncr5380n_interface *>(static_config());
79   if (intf != NULL)
80   {
81      *static_cast<ncr5380n_interface *>(this) = *intf;
82   }
83
84   // or initialize to defaults if none provided
85   else
86   {
87      memset(&m_irq_cb, 0, sizeof(m_irq_cb));
88      memset(&m_drq_cb, 0, sizeof(m_drq_cb));
89   }
90   m_shortname = "ncr5380";
91}
92
93void ncr5380n_device::reset_soft()
94{
95   state = IDLE;
96   scsi_bus->ctrl_w(scsi_refid, 0, S_ALL);   // clear any signals we're driving
97   scsi_bus->ctrl_wait(scsi_refid, S_ALL, S_ALL);
98   status = 0;
99   drq = false;
100   if(!m_drq_func.isnull())
101      m_drq_func(drq);
102   reset_disconnect();
103}
104
105void ncr5380n_device::reset_disconnect()
106{
107   mode = MODE_D;
108}
109
110//static int last_phase = -1;
111
112void ncr5380n_device::scsi_ctrl_changed()
113{
114   UINT32 ctrl = scsi_bus->ctrl_r();
115
116//   printf("scsi_ctrl_changed: lines now %x\n", ctrl);
117
118/*   if ((ctrl & (S_PHASE_MASK|S_SEL|S_BSY)) != last_phase)
119   {
120      printf("phase now %d, SEL %x BSY %x\n", ctrl & S_PHASE_MASK, ctrl & S_SEL, ctrl & S_BSY);
121      last_phase = (S_PHASE_MASK|S_SEL|S_BSY);
122   }*/
123
124   // recalculate phase match
125   m_busstatus &= ~BAS_PHASEMATCH;
126   if ((ctrl & S_PHASE_MASK) == (m_tcommand & S_PHASE_MASK))
127   {
128      m_busstatus |= BAS_PHASEMATCH;
129   }
130
131   if (m_mode & MODE_DMA)
132   {
133      // if BSY drops or the phase goes mismatch, that terminates the DMA
134      if ((!(ctrl & S_BSY)) || !(m_busstatus & BAS_PHASEMATCH))
135      {
136//         printf("BSY dropped or phase mismatch during DMA, ending DMA\n");
137         m_mode &= ~MODE_DMA;
138         m_busstatus |= BAS_ENDOFDMA;
139         drq_clear();
140      }
141   }
142
143   if(ctrl & S_RST) {
144      logerror("%s: scsi bus reset\n", tag());
145      return;
146   }
147
148   step(false);
149}
150
151void ncr5380n_device::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
152{
153   step(true);
154}
155
156void ncr5380n_device::step(bool timeout)
157{
158   UINT32 ctrl = scsi_bus->ctrl_r();
159   UINT32 data = scsi_bus->data_r();
160
161   if(0)
162      printf("%s: state=%d.%d %s\n",
163               tag(), state & STATE_MASK, (state & SUB_MASK) >> SUB_SHIFT,
164               timeout ? "timeout" : "change");
165
166   if(mode == MODE_I && !(ctrl & S_BSY)) {
167      state = IDLE;
168      reset_disconnect();
169      check_irq();
170   }
171   switch(state & SUB_MASK ? state & SUB_MASK : state & STATE_MASK) {
172   case IDLE:
173      break;
174
175   case ARB_COMPLETE << SUB_SHIFT: {
176      if(!timeout)
177         break;
178
179      int win;
180      for(win=7; win>=0 && !(data & (1<<win)); win--);
181//      printf("data %02x win %02x scsi_id %02x\n", data, win, scsi_id);
182      if(win != scsi_id) {
183         scsi_bus->data_w(scsi_refid, 0);
184         scsi_bus->ctrl_w(scsi_refid, 0, S_ALL);
185         fatalerror("need to wait for bus free\n");
186         break;
187      }
188
189      // arbitration no longer in progress
190      m_icommand &= ~IC_ARBITRATION;
191
192      state &= STATE_MASK;
193      step(true);
194      break;
195   }
196
197   case SEND_WAIT_SETTLE << SUB_SHIFT:
198      if(!timeout)
199         break;
200
201      state = (state & STATE_MASK) | (SEND_WAIT_REQ_0 << SUB_SHIFT);
202      step(false);
203      break;
204
205   case SEND_WAIT_REQ_0 << SUB_SHIFT:
206      if(ctrl & S_REQ)
207         break;
208      state = state & STATE_MASK;
209      scsi_bus->data_w(scsi_refid, 0);
210      scsi_bus->ctrl_w(scsi_refid, 0, S_ACK);
211      step(false);
212
213      // byte's done, ask for another if the target hasn't said otherwise
214      if (m_mode & MODE_DMA)
215      {
216         drq_set();
217      }
218      break;
219
220   case RECV_WAIT_REQ_1 << SUB_SHIFT:
221      if(!(ctrl & S_REQ))
222         break;
223
224      state = (state & STATE_MASK) | (RECV_WAIT_SETTLE << SUB_SHIFT);
225      delay_cycles(sync_period);
226      break;
227
228   case RECV_WAIT_SETTLE << SUB_SHIFT:
229      if(!timeout)
230         break;
231
232      m_dmalatch = scsi_bus->data_r();
233      drq_set();
234      scsi_bus->ctrl_w(scsi_refid, S_ACK, S_ACK);
235      state = (state & STATE_MASK) | (RECV_WAIT_REQ_0 << SUB_SHIFT);
236      step(false);
237      break;
238
239   case RECV_WAIT_REQ_0 << SUB_SHIFT:
240      if(ctrl & S_REQ)
241         break;
242      state = state & STATE_MASK;
243      step(false);
244      break;
245
246   default:
247      printf("%s: step() unexpected state %d.%d\n",
248               tag(),
249               state & STATE_MASK, (state & SUB_MASK) >> SUB_SHIFT);
250      exit(0);
251   }
252}
253
254void ncr5380n_device::send_byte()
255{
256   state = (state & STATE_MASK) | (SEND_WAIT_SETTLE << SUB_SHIFT);
257   scsi_bus->data_w(scsi_refid, m_dmalatch);
258
259   scsi_bus->ctrl_w(scsi_refid, S_ACK, S_ACK);
260   scsi_bus->ctrl_wait(scsi_refid, S_REQ, S_REQ);
261   delay_cycles(sync_period);
262}
263
264void ncr5380n_device::recv_byte()
265{
266   state = (state & STATE_MASK) | (RECV_WAIT_REQ_1 << SUB_SHIFT);
267   step(false);
268}
269
270void ncr5380n_device::function_bus_complete()
271{
272   state = IDLE;
273//   istatus |= I_FUNCTION|I_BUS;
274   check_irq();
275}
276
277void ncr5380n_device::function_complete()
278{
279   state = IDLE;
280//   istatus |= I_FUNCTION;
281   check_irq();
282}
283
284void ncr5380n_device::bus_complete()
285{
286   state = IDLE;
287//   istatus |= I_BUS;
288   check_irq();
289}
290
291void ncr5380n_device::delay(int cycles)
292{
293   if(!clock_conv)
294      return;
295   cycles *= clock_conv;
296   tm->adjust(clocks_to_attotime(cycles));
297}
298
299void ncr5380n_device::delay_cycles(int cycles)
300{
301   tm->adjust(clocks_to_attotime(cycles));
302}
303
304READ8_MEMBER(ncr5380n_device::scsidata_r)
305{
306   return scsi_bus->data_r();
307}
308
309WRITE8_MEMBER(ncr5380n_device::outdata_w)
310{
311   m_outdata = data;
312
313   // are we driving the data bus?
314   if (m_icommand & IC_DBUS)
315   {
316      scsi_bus->data_w(scsi_refid, data);
317   }
318}
319
320READ8_MEMBER(ncr5380n_device::icmd_r)
321{
322   return m_icommand;
323}
324
325WRITE8_MEMBER(ncr5380n_device::icmd_w)
326{
327   // asserting to drive the data bus?
328   if ((data & IC_DBUS) && !(m_icommand & IC_DBUS))
329   {
330//      printf("%s: driving data bus with %02x\n", tag(), m_outdata);
331      scsi_bus->data_w(scsi_refid, m_outdata);
332      delay(2);
333   }
334
335   // any control lines changing?
336   UINT8 mask = (data & IC_PHASEMASK) ^ (m_icommand & IC_PHASEMASK);
337   if (mask)
338   {
339      // translate data to nscsi
340      UINT8 newdata = 0;
341
342      newdata = (data & IC_RST ? S_RST : 0) |
343         (data & IC_ACK ? S_ACK : 0) |
344         (data & IC_BSY ? S_BSY : 0) |
345         (data & IC_SEL ? S_SEL : 0) |
346         (data & IC_ATN ? S_ATN : 0);
347
348//      printf("%s: changing control lines %04x\n", tag(), newdata);
349      scsi_bus->ctrl_w(scsi_refid, newdata, S_RST|S_ACK|S_BSY|S_SEL|S_ATN);
350   }
351
352   m_icommand = (data & IC_WRITEMASK);
353   delay(2);
354}
355
356READ8_MEMBER(ncr5380n_device::mode_r)
357{
358   return m_mode;
359}
360
361WRITE8_MEMBER(ncr5380n_device::mode_w)
362{
363//   printf("%s: mode_w %02x (%08x)\n", tag(), data, space.device().safe_pc());
364   // arbitration bit being set?
365   if ((data & MODE_ARBITRATE) && !(m_mode & MODE_ARBITRATE))
366   {
367      // if SEL is selected and the assert SEL bit in the initiator
368      // command register is clear, fail
369      if ((scsi_bus->ctrl_r() & S_SEL) && !(m_icommand & IC_SEL))
370      {
371//         printf("arbitration lost, ctrl = %x, m_icommand&IC_SEL = %x\n", scsi_bus->ctrl_r(), m_icommand & IC_SEL);
372         m_icommand &= ~IC_ARBITRATION;
373         m_icommand |= IC_ARBLOST;
374      }
375      else
376      {
377         seq = 0;
378//         state = DISC_SEL_ARBITRATION;
379         arbitrate();
380      }
381   }
382
383   m_mode = data;
384}
385
386READ8_MEMBER(ncr5380n_device::command_r)
387{
388//   logerror("%s: command_r %02x (%08x)\n", tag(), m_tcommand, space.device().safe_pc());
389   return m_tcommand;
390}
391
392WRITE8_MEMBER(ncr5380n_device::command_w)
393{
394//   printf("%s: command_w %02x (%08x)\n", tag(), data, space.device().safe_pc());
395   m_tcommand = data;
396
397   // recalculate phase match
398   m_busstatus &= ~BAS_PHASEMATCH;
399   if ((scsi_bus->ctrl_r() & S_PHASE_MASK) == (m_tcommand & S_PHASE_MASK))
400   {
401      m_busstatus |= BAS_PHASEMATCH;
402   }
403}
404
405void ncr5380n_device::arbitrate()
406{
407   m_icommand &= ~IC_ARBLOST;
408   m_icommand |= IC_ARBITRATION;
409   state = (state & STATE_MASK) | (ARB_COMPLETE << SUB_SHIFT);
410   scsi_bus->data_w(scsi_refid, m_outdata);
411   scsi_bus->ctrl_w(scsi_refid, S_BSY, S_BSY);
412   delay(11);
413}
414
415void ncr5380n_device::check_irq()
416{
417   #if 0
418   bool oldirq = irq;
419   irq = istatus != 0;
420   if(irq != oldirq && !m_irq_func.isnull())
421      m_irq_func(irq);
422   #endif
423}
424
425READ8_MEMBER(ncr5380n_device::status_r)
426{
427   UINT32 ctrl = scsi_bus->ctrl_r();
428   UINT8 res = status |
429      (ctrl & S_RST ? ST_RST : 0) |
430      (ctrl & S_BSY ? ST_BSY : 0) |
431      (ctrl & S_REQ ? ST_REQ : 0) |
432      (ctrl & S_MSG ? ST_MSG : 0) |
433      (ctrl & S_CTL ? ST_CD  : 0) |
434      (ctrl & S_INP ? ST_IO  : 0) |
435      (ctrl & S_SEL ? ST_SEL : 0);
436
437//   printf("%s: status_r %02x (%08x)\n", tag(), res, space.device().safe_pc());
438   return res;
439}
440
441WRITE8_MEMBER(ncr5380n_device::selenable_w)
442{
443}
444
445READ8_MEMBER(ncr5380n_device::busandstatus_r)
446{
447   UINT32 ctrl = scsi_bus->ctrl_r();
448   UINT8 res = m_busstatus |
449      (ctrl & S_ATN ? BAS_ATN : 0) |
450      (ctrl & S_ACK ? BAS_ACK : 0);
451
452//   printf("%s: busandstatus_r %02x (%08x)\n", tag(), res, space.device().safe_pc());
453
454   return res;
455}
456
457WRITE8_MEMBER(ncr5380n_device::startdmasend_w)
458{
459   printf("%02x to start dma send\n", data);
460   drq_set();
461}
462
463READ8_MEMBER(ncr5380n_device::indata_r)
464{
465   return 0;
466}
467
468WRITE8_MEMBER(ncr5380n_device::startdmatargetrx_w)
469{
470   printf("%02x to start dma target Rx\n", data);
471}
472
473READ8_MEMBER(ncr5380n_device::resetparityirq_r)
474{
475   return 0;
476}
477
478WRITE8_MEMBER(ncr5380n_device::startdmainitrx_w)
479{
480//   printf("%02x to start dma initiator Rx\n", data);
481   recv_byte();
482}
483
484void ncr5380n_device::dma_w(UINT8 val)
485{
486   // drop DRQ until we're ready for another byte
487   drq_clear();
488
489   if (m_mode & MODE_DMA)
490   {
491      m_dmalatch = val;
492      send_byte();
493   }
494}
495
496UINT8 ncr5380n_device::dma_r()
497{
498   // drop DRQ
499   drq_clear();
500
501   // set up to receive our next byte if still in DMA mode
502   scsi_bus->ctrl_w(scsi_refid, 0, S_ACK);
503   if (m_mode & MODE_DMA)
504   {
505      recv_byte();
506   }
507   return m_dmalatch;
508}
509
510void ncr5380n_device::drq_set()
511{
512   if(!drq)
513   {
514      drq = true;
515      m_busstatus |= BAS_DMAREQUEST;
516      if(!m_drq_func.isnull())
517         m_drq_func(drq);
518   }
519}
520
521void ncr5380n_device::drq_clear()
522{
523   if(drq)
524   {
525      drq = false;
526      m_busstatus &= ~BAS_DMAREQUEST;
527      if(!m_drq_func.isnull())
528         m_drq_func(drq);
529   }
530}
531
532READ8_MEMBER(ncr5380n_device::read)
533{
534   switch (offset & 7)
535   {
536      case 0:
537         return scsidata_r(space, offset);
538
539      case 1:
540         return icmd_r(space, offset);
541
542      case 2:
543         return mode_r(space, offset);
544
545      case 3:
546         return command_r(space, offset);
547
548      case 4:
549         return status_r(space, offset);
550
551      case 5:
552         return busandstatus_r(space, offset);
553
554      case 6:
555         return indata_r(space, offset);
556
557      case 7:
558         return resetparityirq_r(space, offset);
559   }
560
561   return 0xff;
562}
563
564WRITE8_MEMBER(ncr5380n_device::write)
565{
566   switch (offset & 7)
567   {
568      case 0:
569         outdata_w(space, offset, data);
570         break;
571
572      case 1:
573         icmd_w(space, offset, data);
574         break;
575
576      case 2:
577         mode_w(space, offset, data);
578         break;
579
580      case 3:
581         command_w(space, offset, data);
582         break;
583
584      case 4:
585         selenable_w(space, offset, data);
586         break;
587
588      case 5:
589         startdmasend_w(space, offset, data);
590         break;
591
592      case 6:
593         startdmatargetrx_w(space, offset, data);
594         break;
595
596      case 7:
597         startdmainitrx_w(space, offset, data);
598         break;
599   }
600}
601
Property changes on: trunk/src/mess/machine/ncr5380n.c
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trunk/src/mess/machine/ncr5380n.h
r0r21499
1/*********************************************************************
2
3    ncr5380n.c
4
5    Implementation of the NCR 5380
6
7*********************************************************************/
8
9#ifndef NCR5380_H
10#define NCR5380_H
11
12#include "machine/nscsi_bus.h"
13
14struct ncr5380n_interface
15{
16   devcb_write_line    m_irq_cb;
17   devcb_write_line    m_drq_cb;
18};
19
20class ncr5380n_device : public nscsi_device,
21                  public ncr5380n_interface
22{
23public:
24   ncr5380n_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
25
26   DECLARE_ADDRESS_MAP(map, 8);
27
28   DECLARE_READ8_MEMBER(scsidata_r);
29   DECLARE_WRITE8_MEMBER(outdata_w);
30   DECLARE_READ8_MEMBER(icmd_r);
31   DECLARE_WRITE8_MEMBER(icmd_w);
32   DECLARE_READ8_MEMBER(mode_r);
33   DECLARE_WRITE8_MEMBER(mode_w);
34   DECLARE_READ8_MEMBER(command_r);
35   DECLARE_WRITE8_MEMBER(command_w);
36   DECLARE_READ8_MEMBER(status_r);
37   DECLARE_WRITE8_MEMBER(selenable_w);
38   DECLARE_READ8_MEMBER(busandstatus_r);
39   DECLARE_WRITE8_MEMBER(startdmasend_w);
40   DECLARE_READ8_MEMBER(indata_r);
41   DECLARE_WRITE8_MEMBER(startdmatargetrx_w);
42   DECLARE_READ8_MEMBER(resetparityirq_r);
43   DECLARE_WRITE8_MEMBER(startdmainitrx_w);
44
45   DECLARE_READ8_MEMBER(read);
46   DECLARE_WRITE8_MEMBER(write);
47
48   virtual void scsi_ctrl_changed();
49
50   UINT8 dma_r();
51   void dma_w(UINT8 val);
52
53protected:
54   virtual void device_start();
55   virtual void device_reset();
56   virtual void device_config_complete();
57   virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
58
59private:
60   enum { MODE_D, MODE_T, MODE_I };
61   enum { IDLE };
62
63   enum {
64      // Bus initiated sequences
65      BUSINIT_SETTLE_DELAY = 1,
66      BUSINIT_ASSERT_BUS_SEL,
67      BUSINIT_MSG_OUT,
68      BUSINIT_RECV_BYTE,
69      BUSINIT_ASSERT_BUS_RESEL,
70      BUSINIT_WAIT_REQ,
71      BUSINIT_RECV_BYTE_NACK,
72
73      // Bus SCSI Reset
74      BUSRESET_WAIT_INT,
75      BUSRESET_RESET_BOARD,
76
77      // Disconnected state commands
78      DISC_SEL_ARBITRATION,
79      DISC_SEL_ATN_WAIT_REQ,
80      DISC_SEL_ATN_SEND_BYTE,
81      DISC_SEL_WAIT_REQ,
82      DISC_SEL_SEND_BYTE,
83      DISC_REC_ARBITRATION,
84      DISC_REC_MSG_IN,
85      DISC_REC_SEND_BYTE,
86      DISC_RESET,
87
88      // Command sequence
89      CMDSEQ_CMD_PHASE,
90      CMDSEQ_RECV_BYTE,
91
92      // Target commands
93      TARGET_SEND_BYTE,
94      TARGET_CMD_RECV_BYTE,
95      TARGET_MSG_RECV_BYTE,
96      TARGET_MSG_RECV_PAD,
97      TARGET_DISC_SEND_BYTE,
98      TARGET_DISC_MSG_IN,
99      TARGET_DISC_SEND_BYTE_2,
100
101      // Initiator commands
102      INIT_MSG_WAIT_REQ,
103      INIT_XFR,
104      INIT_XFR_SEND_BYTE,
105      INIT_XFR_SEND_PAD_WAIT_REQ,
106      INIT_XFR_SEND_PAD,
107      INIT_XFR_RECV_PAD_WAIT_REQ,
108      INIT_XFR_RECV_PAD,
109      INIT_XFR_RECV_BYTE_ACK,
110      INIT_XFR_RECV_BYTE_NACK,
111      INIT_XFR_WAIT_REQ,
112      INIT_CPT_RECV_BYTE_ACK,
113      INIT_CPT_RECV_WAIT_REQ,
114      INIT_CPT_RECV_BYTE_NACK,
115   };
116
117   enum {
118      // Arbitration
119      ARB_WAIT_BUS_FREE = 1,
120      ARB_COMPLETE,
121      ARB_ASSERT_SEL,
122      ARB_SET_DEST,
123      ARB_RELEASE_BUSY,
124      ARB_TIMEOUT_BUSY,
125      ARB_TIMEOUT_ABORT,
126      ARB_DESKEW_WAIT,
127
128      // Send/recieve byte
129      SEND_WAIT_SETTLE,
130      SEND_WAIT_REQ_0,
131      RECV_WAIT_REQ_1,
132      RECV_WAIT_SETTLE,
133      RECV_WAIT_REQ_0,
134   };
135
136   enum {
137      STATE_MASK = 0x00ff,
138      SUB_SHIFT  = 8,
139      SUB_MASK   = 0xff00,
140   };
141
142   enum { BUS_BUSY, BUS_FREE_WAIT, BUS_FREE };
143
144   enum {
145      ST_RST           = 0x80,
146      ST_BSY            = 0x40,
147      ST_REQ            = 0x20,
148      ST_MSG            = 0x10,
149      ST_CD             = 0x08,
150      ST_IO             = 0x04,
151      ST_SEL            = 0x02,
152      ST_DBP            = 0x01,
153
154      BAS_ENDOFDMA     = 0x80,
155      BAS_DMAREQUEST    = 0x40,
156      BAS_PARITYERROR   = 0x20,
157      BAS_IRQACTIVE     = 0x10,
158      BAS_PHASEMATCH    = 0x08,
159      BAS_BUSYERROR     = 0x04,
160      BAS_ATN           = 0x02,
161      BAS_ACK           = 0x01,
162
163      IC_RST           = 0x80,
164      IC_ARBITRATION     = 0x40,
165      IC_ARBLOST        = 0x20,
166      IC_ACK           = 0x10,
167      IC_BSY           = 0x08,
168      IC_SEL           = 0x04,
169      IC_ATN           = 0x02,
170      IC_DBUS           = 0x01,
171      IC_PHASEMASK     = 0x9e,
172      IC_WRITEMASK     = 0x9f,
173
174      MODE_BLOCKDMA     = 0x80,
175      MODE_TARGET        = 0x40,
176      MODE_PARITYCHK     = 0x20,
177      MODE_PARITYIRQ     = 0x10,
178      MODE_EOPIRQ        = 0x08,
179      MODE_BSYIRQ        = 0x04,
180      MODE_DMA        = 0x02,
181      MODE_ARBITRATE     = 0x01,
182   };
183
184   enum { DMA_NONE, DMA_IN, DMA_OUT };
185
186   emu_timer *tm;
187
188   UINT8 status, istatus, m_mode, m_outdata, m_busstatus, m_dmalatch;
189   UINT8 m_icommand, m_tcommand;
190   UINT8 clock_conv, sync_offset, sync_period, bus_id, select_timeout, seq;
191   UINT16 tcount;
192   int mode;
193   int state, xfr_phase;
194
195   bool irq, drq;
196
197   devcb_resolved_write_line   m_irq_func;
198   devcb_resolved_write_line   m_drq_func;
199
200   void drq_set();
201   void drq_clear();
202
203   void step(bool timeout);
204   void function_complete();
205   void function_bus_complete();
206   void bus_complete();
207
208   void arbitrate();
209   void check_irq();
210
211   void reset_soft();
212   void reset_disconnect();
213
214   void send_byte();
215   void recv_byte();
216
217   void delay(int cycles);
218   void delay_cycles(int cycles);
219};
220
221extern const device_type NCR5380N;
222
223#endif
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529529   $(MESS_MACHINE)/msm6222b.o  \
530530   $(MESS_MACHINE)/serial.o    \
531531   $(MESS_MACHINE)/ncr5380.o   \
532   $(MESS_MACHINE)/ncr5380n.o   \
532533   $(MESS_MACHINE)/ncr5390.o   \
533534   $(MESS_MACHINE)/pc_kbdc.o   \
534535   $(MESS_MACHINE)/pc_lpt.o    \

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