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r19317 Wednesday 5th December, 2012 at 01:50:09 UTC by Angelo Salese
Added GRCG capabilities
[src/mess/drivers]pc9801.c

trunk/src/mess/drivers/pc9801.c
r19316r19317
342342   UINT8 m_rom_bank;
343343   UINT8 m_fdc_ctrl;
344344   UINT32 m_ram_size;
345   UINT8 m_ex_video_ff[4];
345   UINT8 m_ex_video_ff[128];
346346   struct {
347347      UINT8 pal_entry;
348348      UINT8 r[16],g[16],b[16];
349349   }m_analog16;
350   struct {
351      UINT8 mode;
352      UINT8 tile[4], tile_index;
353   }m_grcg;
350354
351355   /* PC9821 specific */
352356   UINT8 m_analog256,m_analog256e;
r19316r19317
377381   DECLARE_WRITE8_MEMBER(pc9801_video_ff_w);
378382   DECLARE_READ8_MEMBER(pc9801_70_r);
379383   DECLARE_WRITE8_MEMBER(pc9801_70_w);
384   DECLARE_READ8_MEMBER(pc9801rs_70_r);
385   DECLARE_WRITE8_MEMBER(pc9801rs_70_w);
380386   DECLARE_READ8_MEMBER(pc9801_sasi_r);
381387   DECLARE_WRITE8_MEMBER(pc9801_sasi_w);
382388   DECLARE_READ8_MEMBER(pc9801_a0_r);
r19316r19317
391397   DECLARE_WRITE8_MEMBER(pc9801_gvram_w);
392398   DECLARE_READ8_MEMBER(pc9801_mouse_r);
393399   DECLARE_WRITE8_MEMBER(pc9801_mouse_w);
394//   DECLARE_READ8_MEMBER(pc9801rs_gvram_r);
395   DECLARE_WRITE8_MEMBER(pc9801rs_gvram_w);
400   DECLARE_READ8_MEMBER(pc9801rs_grcg_r);
401   DECLARE_WRITE8_MEMBER(pc9801rs_grcg_w);
396402   DECLARE_READ8_MEMBER(pc9801_opn_r);
397403   DECLARE_WRITE8_MEMBER(pc9801_opn_w);
398404   DECLARE_READ8_MEMBER(pc9801rs_wram_r);
r19316r19317
533539//   DECLARE_WRITE_LINE_MEMBER(pc9801rs_fdc_irq);
534540
535541   void pc9801_fdc_2hd_update_ready(floppy_image_device *, int);
542   inline UINT32 m_calc_grcg_addr(int i,UINT32 offset);
536543};
537544
538545
r19316r19317
10591066
10601067WRITE8_MEMBER(pc9801_state::pc9801_70_w)
10611068{
1062
10631069   if((offset & 1) == 0)
10641070   {
10651071      printf("Write to display register [%02x] %02x\n",offset+0x70,data);
r19316r19317
13701376   m_video_ram_2[offset+0x08000+m_vram_bank*0x20000] = data;
13711377}
13721378
1373WRITE8_MEMBER(pc9801_state::pc9801rs_gvram_w)
1379inline UINT32 pc9801_state::m_calc_grcg_addr(int i,UINT32 offset)
13741380{
1375   m_video_ram_2[offset+0+m_vram_bank*0x20000] = data;
1381   return (offset) + (((i+1)*0x8000) & 0x1ffff) + (m_vram_bank*0x20000);
13761382}
13771383
1384READ8_MEMBER(pc9801_state::pc9801rs_grcg_r)
1385{
1386   UINT8 res;
13781387
1388   if((m_grcg.mode & 0x80) == 0 || (m_grcg.mode & 0x40))
1389      res = m_video_ram_2[offset+0+m_vram_bank*0x20000];
1390   else
1391   {
1392      int i;
1393
1394      res = 0;
1395      for(i=0;i<4;i++)
1396      {
1397         if((m_grcg.mode & 1 << i) == 0)
1398            res |= (m_video_ram_2[m_calc_grcg_addr(i,offset)] ^ m_grcg.tile[i]);
1399      }
1400
1401      res ^= 0xff;
1402   }
1403
1404   return res;
1405}
1406
1407WRITE8_MEMBER(pc9801_state::pc9801rs_grcg_w)
1408{
1409   if((m_grcg.mode & 0x80) == 0)
1410      m_video_ram_2[offset+0+m_vram_bank*0x20000] = data;
1411   else
1412   {
1413      int i;
1414
1415      if(m_grcg.mode & 0x40) // RMW
1416      {
1417         for(i=0;i<4;i++)
1418         {
1419            if((m_grcg.mode & 1 << i) == 0)
1420            {
1421               m_video_ram_2[m_calc_grcg_addr(i,offset)] &= ~data;
1422               m_video_ram_2[m_calc_grcg_addr(i,offset)] |= m_grcg.tile[i] & data;
1423            }
1424         }
1425      }
1426      else // TDW
1427      {
1428         for(i=0;i<4;i++)
1429         {
1430            if((m_grcg.mode & 1 << i) == 0)
1431               m_video_ram_2[m_calc_grcg_addr(i,offset)] = m_grcg.tile[i];
1432         }
1433      }
1434   }
1435}
1436
1437
13791438READ8_MEMBER(pc9801_state::pc9801_opn_r)
13801439{
13811440   if((offset & 1) == 0)
r19316r19317
15421601   return pc9801_30_r(space,offset);
15431602}
15441603
1604READ8_MEMBER(pc9801_state::pc9801rs_70_r)
1605{
1606   if(offset == 0xc)
1607   {
1608      printf("GRCG mode R\n");
1609      return 0xff;
1610   }
1611   else if(offset == 0x0e)
1612   {
1613      printf("GRCG tile R\n");
1614      return 0xff;
1615   }
1616
1617   return    pc9801_70_r(space,offset);;
1618}
1619
1620WRITE8_MEMBER(pc9801_state::pc9801rs_70_w)
1621{
1622   if(offset == 0xc)
1623   {
1624//      printf("%02x GRCG MODE\n",data);
1625      m_grcg.mode = data;
1626      m_grcg.tile_index = 0;
1627      return;
1628   }
1629   else if(offset == 0x0e)
1630   {
1631//      printf("%02x GRCG TILE %02x\n",data,m_grcg.tile_index);
1632      m_grcg.tile[m_grcg.tile_index] = data;
1633      m_grcg.tile_index ++;
1634      m_grcg.tile_index &= 3;
1635      return;
1636   }
1637
1638   pc9801_70_w(space,offset,data);
1639}
1640
15451641READ8_MEMBER(pc9801_state::pc9801rs_memory_r)
15461642{
15471643   if(m_gate_a20 == 0)
r19316r19317
15511647   else if(offset >= 0x000a0000 && offset <= 0x000a3fff)                   { return pc9801_tvram_r(space,offset-0xa0000);        }
15521648   else if(offset >= 0x000a4000 && offset <= 0x000a4fff)                   { return pc9801rs_knjram_r(space,offset & 0xfff);     }
15531649   else if(offset >= 0x000a8000 && offset <= 0x000bffff)                   { return pc9801_gvram_r(space,offset-0xa8000);        }
1650   else if(offset >= 0x000e0000 && offset <= 0x000e7fff)                   { return pc9801rs_grcg_r(space,offset & 0x7fff);      }
15541651   else if(offset >= 0x000e0000 && offset <= 0x000fffff)                   { return pc9801rs_ipl_r(space,offset & 0x1ffff);      }
15551652   else if(offset >= 0x00100000 && offset <= 0x00100000+m_ram_size-1)      { return pc9801rs_ex_wram_r(space,offset-0x00100000); }
15561653   else if(offset >= 0xfffe0000 && offset <= 0xffffffff)                   { return pc9801rs_ipl_r(space,offset & 0x1ffff);      }
r19316r19317
15691666   else if(offset >= 0x000a0000 && offset <= 0x000a3fff)                   { pc9801_tvram_w(space,offset-0xa0000,data);           }
15701667   else if(offset >= 0x000a4000 && offset <= 0x000a4fff)                   { pc9801rs_knjram_w(space,offset & 0xfff,data);        }
15711668   else if(offset >= 0x000a8000 && offset <= 0x000bffff)                   { pc9801_gvram_w(space,offset-0xa8000,data);           }
1572   else if(offset >= 0x000e0000 && offset <= 0x000e7fff)                   { pc9801rs_gvram_w(space,offset & 0x7fff,data);        }
1669   else if(offset >= 0x000e0000 && offset <= 0x000e7fff)                   { pc9801rs_grcg_w(space,offset & 0x7fff,data);        }
15731670   else if(offset >= 0x00100000 && offset <= 0x00100000+m_ram_size-1)      { pc9801rs_ex_wram_w(space,offset-0x00100000,data);    }
15741671   //else
15751672   //  printf("%08x %08x\n",offset,data);
r19316r19317
16861783
16871784   if(offset == 2)
16881785   {
1689      if((data & 0xf8) == 0)
1786      m_ex_video_ff[(data & 0xfe) >> 1] = data & 1;
1787
1788      if(0)
16901789      {
1691         m_ex_video_ff[(data & 0x6) >> 1] = data & 1;
1692
1693         if(1)
1790         static const char *const ex_video_ff_regnames[] =
16941791         {
1695            static const char *const ex_video_ff_regnames[] =
1696            {
1697               "16 colors mode",   // 0
1698               "<unknown>",      // 1
1699               "EGC related",      // 2
1700               "<unknown>"         // 3
1701            };
1792            "16 colors mode",   // 0
1793            "<unknown>",      // 1
1794            "EGC related",      // 2
1795            "<unknown>"         // 3
1796         };
17021797
1703            printf("Write to extend video FF register %s -> %02x\n",ex_video_ff_regnames[(data & 0x06) >> 1],data & 1);
1704         }
1705         else
1706            printf("Write to extend video FF register %02x\n",data);
1798         printf("Write to extend video FF register %s -> %02x\n",ex_video_ff_regnames[(data & 0x06) >> 1],data & 1);
17071799      }
1800      //else
1801      //   printf("Write to extend video FF register %02x\n",data);
1802
17081803      return;
17091804   }
17101805
r19316r19317
17601855   AM_RANGE(0x0060, 0x0063) AM_READWRITE8(pc9801_60_r,        pc9801_60_w,        0xffffffff) //upd7220 character ports / <undefined>
17611856   AM_RANGE(0x0064, 0x0067) AM_WRITE8(pc9801_vrtc_mask_w, 0xffffffff)
17621857   AM_RANGE(0x0068, 0x006b) AM_WRITE8(pc9801rs_video_ff_w,0xffffffff) //mode FF / <undefined>
1763   AM_RANGE(0x0070, 0x007b) AM_READWRITE8(pc9801_70_r,        pc9801_70_w,        0xffffffff) //display registers "GRCG" / i8253 pit
1858   AM_RANGE(0x0070, 0x007f) AM_READWRITE8(pc9801rs_70_r,      pc9801rs_70_w,      0xffffffff) //display registers "GRCG" / i8253 pit
17641859   AM_RANGE(0x0080, 0x0083) AM_READWRITE8(pc9801_sasi_r,      pc9801_sasi_w,      0xffffffff) //HDD SASI interface / <undefined>
17651860   AM_RANGE(0x0090, 0x0097) AM_READWRITE8(pc9801rs_2hd_r,     pc9801rs_2hd_w,     0xffffffff)
17661861   AM_RANGE(0x00a0, 0x00af) AM_READWRITE8(pc9801_a0_r,        pc9801rs_a0_w,      0xffffffff) //upd7220 bitmap ports / display registers
r19316r19317
18181913   AM_RANGE(0x0060, 0x0063) AM_READWRITE8(pc9801_60_r,        pc9801_60_w,        0xffff) //upd7220 character ports / <undefined>
18191914   AM_RANGE(0x0064, 0x0067) AM_WRITE8(pc9801_vrtc_mask_w, 0xffff)
18201915   AM_RANGE(0x0068, 0x006b) AM_WRITE8(pc9801rs_video_ff_w,0xffff) //mode FF / <undefined>
1821   AM_RANGE(0x0070, 0x007b) AM_READWRITE8(pc9801_70_r,        pc9801_70_w,        0xffff) //display registers "GRCG" / i8253 pit
1916   AM_RANGE(0x0070, 0x007f) AM_READWRITE8(pc9801rs_70_r,      pc9801rs_70_w,      0xffff) //display registers "GRCG" / i8253 pit
18221917   AM_RANGE(0x0090, 0x0097) AM_READWRITE8(pc9801rs_2hd_r,     pc9801rs_2hd_w,     0xffff)
18231918   AM_RANGE(0x00a0, 0x00af) AM_READWRITE8(pc9801_a0_r,        pc9801rs_a0_w,      0xffff) //upd7220 bitmap ports / display registers
18241919   AM_RANGE(0x00bc, 0x00bf) AM_READWRITE8(pc9810rs_fdc_ctrl_r,pc9810rs_fdc_ctrl_w,0xffff)
r19316r19317
20892184   AM_RANGE(0x0060, 0x0063) AM_READWRITE8(pc9801_60_r,        pc9801_60_w,        0xffffffff) //upd7220 character ports / <undefined>
20902185   AM_RANGE(0x0064, 0x0067) AM_WRITE8(pc9801_vrtc_mask_w, 0xffffffff)
20912186   AM_RANGE(0x0068, 0x006b) AM_WRITE8(pc9821_video_ff_w,  0xffffffff) //mode FF / <undefined>
2092   AM_RANGE(0x0070, 0x007b) AM_READWRITE8(pc9801_70_r,        pc9801_70_w,        0xffffffff) //display registers "GRCG" / i8253 pit
2187   AM_RANGE(0x0070, 0x007f) AM_READWRITE8(pc9801rs_70_r,      pc9801rs_70_w,    0xffffffff) //display registers "GRCG" / i8253 pit
20932188//  AM_RANGE(0x0080, 0x0083) SASI interface / <undefined>
20942189   AM_RANGE(0x0090, 0x0097) AM_READWRITE8(pc9801rs_2hd_r,     pc9801rs_2hd_w,     0xffffffff)
20952190   AM_RANGE(0x00a0, 0x00af) AM_READWRITE8(pc9821_a0_r,        pc9821_a0_w,        0xffffffff) //upd7220 bitmap ports / display registers

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