trunk/src/mame/machine/megacdcd.c
| r19314 | r19315 | |
| 53 | 53 | } |
| 54 | 54 | |
| 55 | 55 | // HACK for DMA handling, this gets replaced |
| 56 | | void lc89510_temp_device::Fake_CDC_Do_DMA(int &dmacount, UINT8 *CDC_BUFFER, UINT16 &CDC_DMA_ADDR, UINT16 &CDC_DMA_ADDRC, UINT16 &destination ) |
| 56 | void lc89510_temp_device::Fake_CDC_Do_DMA(int &dmacount, UINT8 *CDC_BUFFER, UINT16 &SEGACD_DMA_ADDRESS, UINT16 &dma_addrc, UINT16 &destination ) |
| 57 | 57 | { |
| 58 | 58 | fatalerror("Fake_CDC_Do_DMA\n"); |
| 59 | 59 | } |
| r19314 | r19315 | |
| 439 | 439 | memset(CDC_BUFFER, 0x00, ((16 * 1024 * 2) + SECTOR_SIZE)); |
| 440 | 440 | LC8951UpdateHeader(); |
| 441 | 441 | |
| 442 | | CDC_DMA_ADDRC = CDC_DMACNT = CDC_PT = LC8951RegistersW[REG_W_SBOUT] = LC8951RegistersW[REG_W_IFCTRL] = LC8951RegistersW[REG_W_CTRL0] = LC8951RegistersW[REG_W_CTRL1] = |
| 442 | LC8951RegistersW[REG_W_DACL] = LC8951RegistersW[REG_W_DACH] = LC8951RegistersW[REG_W_DBCL] = LC8951RegistersW[REG_W_DBCH] = LC8951RegistersW[REG_W_PTH] = LC8951RegistersW[REG_W_PTL] = LC8951RegistersW[REG_W_SBOUT] = LC8951RegistersW[REG_W_IFCTRL] = LC8951RegistersW[REG_W_CTRL0] = LC8951RegistersW[REG_W_CTRL1] = |
| 443 | 443 | LC8951RegistersW[REG_W_CTRL2] = LC8951RegistersR[REG_R_HEAD1] = LC8951RegistersR[REG_R_HEAD2] = LC8951RegistersR[REG_R_HEAD3] = LC8951RegistersR[REG_R_STAT0] = LC8951RegistersR[REG_R_STAT1] = LC8951RegistersR[REG_R_STAT2] = CDC_DECODE = 0; |
| 444 | 444 | |
| 445 | 445 | LC8951RegistersR[REG_R_IFSTAT] = 0xFF; |
| 446 | | CDC_WA = SECTOR_SIZE * 2; |
| 446 | int wa = SECTOR_SIZE * 2; |
| 447 | LC8951RegistersW[REG_W_WAL] = wa & 0xff; LC8951RegistersW[REG_W_WAH] = (wa >> 8) &0xff; |
| 447 | 448 | LC8951RegistersR[REG_R_HEAD0] = 0x01; |
| 448 | 449 | LC8951RegistersR[REG_R_STAT3] = 0x80; |
| 449 | 450 | } |
| r19314 | r19315 | |
| 454 | 455 | CDD_Reset(); |
| 455 | 456 | CDC_Reset(); |
| 456 | 457 | |
| 457 | | CDC_REG0 = CDC_REG1 = CDC_DMA_ADDR = SCD_STATUS_CDC = CDD_DONE = 0; |
| 458 | CDC_REG0 = CDC_REG1 = SEGACD_DMA_ADDRESS = SCD_STATUS_CDC = CDD_DONE = 0; |
| 458 | 459 | } |
| 459 | 460 | |
| 460 | 461 | void lc89510_temp_device::CDC_End_Transfer(running_machine& machine) |
| r19314 | r19315 | |
| 487 | 488 | return; |
| 488 | 489 | } |
| 489 | 490 | |
| 490 | | if (CDC_DMACNT <= (rate * 2)) |
| 491 | int dma_count_register = LC8951RegistersW[REG_W_DBCL] | (LC8951RegistersW[REG_W_DBCH]<<8); |
| 492 | |
| 493 | if (dma_count_register <= (rate * 2)) |
| 491 | 494 | { |
| 492 | | length = (CDC_DMACNT + 1) >> 1; |
| 495 | length = (dma_count_register + 1) >> 1; |
| 493 | 496 | CDC_End_Transfer(machine); |
| 494 | 497 | } |
| 495 | 498 | else |
| r19314 | r19315 | |
| 498 | 501 | |
| 499 | 502 | int dmacount = length; |
| 500 | 503 | |
| 504 | UINT16 dma_addrc = LC8951RegistersW[REG_W_DACL] | (LC8951RegistersW[REG_W_DACH]<<8); |
| 505 | |
| 501 | 506 | // HACK |
| 502 | | segacd_dma_callback(dmacount, CDC_BUFFER, CDC_DMA_ADDR, CDC_DMA_ADDRC, destination ); |
| 507 | segacd_dma_callback(dmacount, CDC_BUFFER, SEGACD_DMA_ADDRESS, dma_addrc, destination ); |
| 503 | 508 | |
| 504 | 509 | |
| 505 | | CDC_DMA_ADDRC += length*2; |
| 510 | dma_addrc += length*2; |
| 511 | LC8951RegistersW[REG_W_DACL] = dma_addrc & 0xff; LC8951RegistersW[REG_W_DACH] = (dma_addrc >> 8) & 0xff; |
| 506 | 512 | |
| 507 | 513 | if (SCD_DMA_ENABLED) |
| 508 | | CDC_DMACNT -= length*2; |
| 514 | dma_count_register -= length*2; |
| 509 | 515 | else |
| 510 | | CDC_DMACNT = 0; |
| 516 | dma_count_register = 0; |
| 517 | |
| 518 | LC8951RegistersW[REG_W_DBCL] = dma_count_register & 0xff; LC8951RegistersW[REG_W_DBCH] = (dma_count_register>>8) & 0xff; |
| 519 | |
| 511 | 520 | } |
| 512 | 521 | |
| 513 | 522 | |
| r19314 | r19315 | |
| 521 | 530 | { |
| 522 | 531 | if (destination == type) |
| 523 | 532 | { |
| 524 | | CDC_DMACNT -= 2; |
| 533 | int dma_count_register = LC8951RegistersW[REG_W_DBCL] | (LC8951RegistersW[REG_W_DBCH]<<8); |
| 525 | 534 | |
| 526 | | if (CDC_DMACNT <= 0) |
| 535 | dma_count_register -= 2; |
| 536 | |
| 537 | if (dma_count_register <= 0) |
| 527 | 538 | { |
| 528 | | if (type==READ_SUB) CDC_DMACNT = 0; |
| 539 | if (type==READ_SUB) dma_count_register = 0; |
| 529 | 540 | |
| 530 | 541 | CDC_End_Transfer(machine); |
| 531 | 542 | } |
| 532 | 543 | |
| 533 | | UINT16 data = (CDC_BUFFER[CDC_DMA_ADDRC]<<8) | CDC_BUFFER[CDC_DMA_ADDRC+1]; |
| 534 | | CDC_DMA_ADDRC += 2; |
| 544 | LC8951RegistersW[REG_W_DBCL] = dma_count_register & 0xff; LC8951RegistersW[REG_W_DBCH] = (dma_count_register>>8) & 0xff; |
| 535 | 545 | |
| 546 | UINT16 dma_addrc = LC8951RegistersW[REG_W_DACL] | (LC8951RegistersW[REG_W_DACH]<<8); |
| 547 | |
| 548 | UINT16 data = (CDC_BUFFER[dma_addrc]<<8) | CDC_BUFFER[dma_addrc+1]; |
| 549 | dma_addrc += 2; |
| 550 | |
| 551 | LC8951RegistersW[REG_W_DACL] = dma_addrc & 0xff; LC8951RegistersW[REG_W_DACH] = (dma_addrc >> 8) & 0xff; |
| 552 | |
| 553 | |
| 536 | 554 | return data; |
| 537 | 555 | } |
| 538 | 556 | } |
| r19314 | r19315 | |
| 556 | 574 | |
| 557 | 575 | switch (reg) |
| 558 | 576 | { |
| 559 | | case REG_R_COMIN: ret = 0/*COMIN*/; break; |
| 560 | | case REG_R_IFSTAT: ret = LC8951RegistersR[REG_R_IFSTAT]; break; |
| 561 | | case REG_R_DBCL: ret = CDC_DMACNT & 0xff; break; |
| 562 | | case REG_R_DBCH: ret = (CDC_DMACNT >>8) & 0xff; break; |
| 563 | | case REG_R_HEAD0: ret = LC8951RegistersR[REG_R_HEAD0]; break; |
| 564 | | case REG_R_HEAD1: ret = LC8951RegistersR[REG_R_HEAD1]; break; |
| 565 | | case REG_R_HEAD2: ret = LC8951RegistersR[REG_R_HEAD2]; break; |
| 566 | | case REG_R_HEAD3: ret = LC8951RegistersR[REG_R_HEAD3]; break; |
| 567 | | case REG_R_PTL: ret = CDC_PT & 0xff; break; |
| 568 | | case REG_R_PTH: ret = (CDC_PT >>8) & 0xff; break; |
| 569 | | case REG_R_WAL: ret = CDC_WA & 0xff; break; |
| 570 | | case REG_R_WAH: ret = (CDC_WA >>8) & 0xff; break; |
| 571 | | case REG_R_STAT0: ret = LC8951RegistersR[REG_R_STAT0]; break; |
| 572 | | case REG_R_STAT1: ret = LC8951RegistersR[REG_R_STAT1]; break; |
| 573 | | case REG_R_STAT2: ret = LC8951RegistersR[REG_R_STAT2]; break; |
| 577 | case REG_R_COMIN: ret = 0/*COMIN*/; break; |
| 578 | case REG_R_IFSTAT: ret = LC8951RegistersR[REG_R_IFSTAT]; break; |
| 579 | case REG_R_DBCL: ret = LC8951RegistersW[REG_W_DBCL]; break; |
| 580 | case REG_R_DBCH: ret = LC8951RegistersW[REG_W_DBCH]; break; |
| 581 | case REG_R_HEAD0: ret = LC8951RegistersR[REG_R_HEAD0]; break; |
| 582 | case REG_R_HEAD1: ret = LC8951RegistersR[REG_R_HEAD1]; break; |
| 583 | case REG_R_HEAD2: ret = LC8951RegistersR[REG_R_HEAD2]; break; |
| 584 | case REG_R_HEAD3: ret = LC8951RegistersR[REG_R_HEAD3]; break; |
| 585 | case REG_R_PTL: ret = LC8951RegistersW[REG_W_PTL]; break; |
| 586 | case REG_R_PTH: ret = LC8951RegistersW[REG_W_PTH]; break; |
| 587 | case REG_R_WAL: ret = LC8951RegistersW[REG_W_WAL]; break; |
| 588 | case REG_R_WAH: ret = LC8951RegistersW[REG_W_WAH]; break; |
| 589 | case REG_R_STAT0: ret = LC8951RegistersR[REG_R_STAT0]; break; |
| 590 | case REG_R_STAT1: ret = LC8951RegistersR[REG_R_STAT1]; break; |
| 591 | case REG_R_STAT2: ret = LC8951RegistersR[REG_R_STAT2]; break; |
| 574 | 592 | case REG_R_STAT3: ret = LC8951RegistersR[REG_R_STAT3]; |
| 575 | 593 | |
| 576 | 594 | LC8951RegistersR[REG_R_IFSTAT] |= 0x20; |
| 577 | 595 | |
| 578 | | // ?? |
| 579 | 596 | if ((LC8951RegistersW[REG_W_CTRL0] & 0x80) && (LC8951RegistersW[REG_W_IFCTRL] & 0x20)) |
| 580 | 597 | { |
| 581 | 598 | if ((CDC_DECODE & decoderegs) == decoderegs) |
| r19314 | r19315 | |
| 607 | 624 | |
| 608 | 625 | if (!(LC8951RegistersW[REG_W_IFCTRL] & 0x02)) |
| 609 | 626 | { |
| 610 | | CDC_DMACNT = 0; |
| 627 | LC8951RegistersW[REG_W_DBCL] = 0; LC8951RegistersW[REG_W_DBCH] = 0; |
| 611 | 628 | STOP_CDC_DMA; |
| 612 | 629 | LC8951RegistersR[REG_R_IFSTAT] |= 0x08; |
| 613 | 630 | } |
| 614 | 631 | break; |
| 615 | 632 | |
| 616 | | case REG_W_DBCL: CDC_DMACNT = (CDC_DMACNT &~ 0x00ff) | (data & 0x00ff) << 0; break; |
| 617 | | case REG_W_DBCH: CDC_DMACNT = (CDC_DMACNT &~ 0xff00) | (data & 0x00ff) << 8; break; |
| 618 | | case REG_W_DACL: CDC_DMA_ADDRC = (CDC_DMA_ADDRC &~ 0x00ff) | (data & 0x00ff) << 0; break; |
| 619 | | case REG_W_DACH: CDC_DMA_ADDRC = (CDC_DMA_ADDRC &~ 0xff00) | (data & 0x00ff) << 8; break; |
| 633 | case REG_W_DBCL: LC8951RegistersW[REG_W_DBCL] = data; break; |
| 634 | case REG_W_DBCH: LC8951RegistersW[REG_W_DBCH] = data; break; |
| 635 | case REG_W_DACL: LC8951RegistersW[REG_W_DACL] = data; break; |
| 636 | case REG_W_DACH: LC8951RegistersW[REG_W_DACH] = data; break; |
| 620 | 637 | |
| 621 | 638 | case REG_W_DTTRG: |
| 622 | 639 | if (LC8951RegistersW[REG_W_IFCTRL] & 0x02) |
| r19314 | r19315 | |
| 628 | 645 | break; |
| 629 | 646 | |
| 630 | 647 | case REG_W_DTACK: LC8951RegistersR[REG_R_IFSTAT] |= 0x40; break; |
| 631 | | case REG_W_WAL: CDC_WA = (CDC_WA &~ 0x00ff) | (data & 0x00ff) << 0; break; |
| 632 | | case REG_W_WAH: CDC_WA = (CDC_WA &~ 0xff00) | (data & 0x00ff) << 8; break; |
| 648 | case REG_W_WAL: LC8951RegistersW[REG_W_WAL] = data; break; |
| 649 | case REG_W_WAH: LC8951RegistersW[REG_W_WAH] = data; break; |
| 633 | 650 | case REG_W_CTRL0: LC8951RegistersW[REG_W_CTRL0] = data; break; |
| 634 | 651 | case REG_W_CTRL1: LC8951RegistersW[REG_W_CTRL1] = data; break; |
| 635 | | case REG_W_PTL: CDC_PT = (CDC_PT &~ 0x00ff) | (data & 0x00ff) << 0; break; |
| 636 | | case REG_W_PTH: CDC_PT = (CDC_PT &~ 0xff00) | (data & 0x00ff) << 8; break; |
| 652 | case REG_W_PTL: LC8951RegistersW[REG_W_PTL] = data; break; |
| 653 | case REG_W_PTH: LC8951RegistersW[REG_W_PTH] = data; break; |
| 637 | 654 | case REG_W_CTRL2: LC8951RegistersW[REG_W_CTRL2] = data; break; |
| 638 | 655 | case REG_W_RESET: CDC_Reset(); break; |
| 639 | 656 | } |
| r19314 | r19315 | |
| 879 | 896 | |
| 880 | 897 | READ16_MEMBER( lc89510_temp_device::cdc_dmaaddr_r ) |
| 881 | 898 | { |
| 882 | | return CDC_DMA_ADDR; |
| 899 | return SEGACD_DMA_ADDRESS; |
| 883 | 900 | } |
| 884 | 901 | |
| 885 | 902 | WRITE16_MEMBER( lc89510_temp_device::cdc_dmaaddr_w ) |
| 886 | 903 | { |
| 887 | | COMBINE_DATA(&CDC_DMA_ADDR); |
| 904 | COMBINE_DATA(&SEGACD_DMA_ADDRESS); |
| 888 | 905 | } |
| 889 | 906 | |
| 890 | 907 | READ16_MEMBER( lc89510_temp_device::segacd_cdfader_r ) |
| r19314 | r19315 | |
| 1707 | 1724 | { |
| 1708 | 1725 | SCD_CURLBA++; |
| 1709 | 1726 | |
| 1710 | | CDC_WA += SECTOR_SIZE; |
| 1711 | | CDC_PT += SECTOR_SIZE; |
| 1727 | int pt = LC8951RegistersW[REG_W_PTL] | (LC8951RegistersW[REG_W_PTH] << 8); |
| 1728 | int wa = LC8951RegistersW[REG_W_WAL] | (LC8951RegistersW[REG_W_WAH] << 8); |
| 1712 | 1729 | |
| 1713 | | CDC_WA &= 0x7fff; |
| 1714 | | CDC_PT &= 0x7fff; |
| 1730 | wa += SECTOR_SIZE; |
| 1731 | pt += SECTOR_SIZE; |
| 1732 | |
| 1733 | wa &= 0x7fff; |
| 1734 | pt &= 0x7fff; |
| 1735 | |
| 1736 | LC8951RegistersW[REG_W_PTL] = pt & 0xff; LC8951RegistersW[REG_W_PTH] = (pt >> 8) &0xff; |
| 1737 | LC8951RegistersW[REG_W_WAL] = wa & 0xff; LC8951RegistersW[REG_W_WAH] = (wa >> 8) &0xff; |
| 1738 | |
| 1715 | 1739 | } |
| 1716 | 1740 | |
| 1717 | 1741 | int lc89510_temp_device::Read_LBA_To_Buffer(running_machine& machine) |
| r19314 | r19315 | |
| 1737 | 1761 | { |
| 1738 | 1762 | scd_advance_current_readpos(); |
| 1739 | 1763 | |
| 1740 | | memcpy(&CDC_BUFFER[CDC_PT + 4], SCD_BUFFER, 2048); |
| 1741 | | CDC_BUFFER[CDC_PT+0] = LC8951RegistersR[REG_R_HEAD0]; |
| 1742 | | CDC_BUFFER[CDC_PT+1] = LC8951RegistersR[REG_R_HEAD1]; |
| 1743 | | CDC_BUFFER[CDC_PT+2] = LC8951RegistersR[REG_R_HEAD2]; |
| 1744 | | CDC_BUFFER[CDC_PT+3] = LC8951RegistersR[REG_R_HEAD3]; |
| 1764 | int pt = LC8951RegistersW[REG_W_PTL] | (LC8951RegistersW[REG_W_PTH] << 8); |
| 1765 | |
| 1766 | memcpy(&CDC_BUFFER[pt + 4], SCD_BUFFER, 2048); |
| 1767 | CDC_BUFFER[pt+0] = LC8951RegistersR[REG_R_HEAD0]; |
| 1768 | CDC_BUFFER[pt+1] = LC8951RegistersR[REG_R_HEAD1]; |
| 1769 | CDC_BUFFER[pt+2] = LC8951RegistersR[REG_R_HEAD2]; |
| 1770 | CDC_BUFFER[pt+3] = LC8951RegistersR[REG_R_HEAD3]; |
| 1745 | 1771 | } |
| 1746 | 1772 | else |
| 1747 | 1773 | { |
| 1748 | | memcpy(&CDC_BUFFER[CDC_PT], SCD_BUFFER, SECTOR_SIZE); |
| 1774 | int pt = LC8951RegistersW[REG_W_PTL] | (LC8951RegistersW[REG_W_PTH] << 8); |
| 1775 | |
| 1776 | memcpy(&CDC_BUFFER[pt], SCD_BUFFER, SECTOR_SIZE); |
| 1749 | 1777 | } |
| 1750 | 1778 | } |
| 1751 | 1779 | |