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r19183 Wednesday 28th November, 2012 at 04:27:10 UTC by R. Belmont
h8 updates: [R. Belmont] - Preliminary H8S/2655 support - Fixed so RTE doesn't allow the PC to go outside the address space - Supported additional forms of BTST and BSET - Removed incorrect halt on BVC/BVS instructions

[src/emu/cpu/h83002]

h8.h h8_16.c h8disasm.c h8ops.h h8priv.h h8speriph.c

trunk/src/emu/cpu/h83002/h8disasm.c

r19182	r19183
1275	1275	sprintf(buffer, "%4.4x mov.b @%x, %s", opcode, data16, reg_names8[opcode & 0xf]);
1276	1276	size = 4;
1277	1277	break;
	1278	case 0x1:
	1279	data32=h8_mem_read16(2);
	1280	if (data32 & 0x8000)
	1281	{
	1282	data32 |= 0xffff0000;
	1283	}
	1284	data16=h8_mem_read16(4);
	1285	if ((data16 & 0xff00) == 0x7300)
	1286	{
	1287	sprintf(buffer, "%4.4x btst #%d, @%8.8x", opcode, (data16 >> 4) & 7, data32 & addr_mask);
	1288	}
	1289	else if ((data16 & 0xff0f) == 0x7000)
	1290	{
	1291	sprintf(buffer, "%4.4x bset #%d, @%8.8x", opcode, (data16 >> 4) & 7, data32 & addr_mask);
	1292	}
	1293	else if ((data16 & 0xff00) == 0x6300)
	1294	{
	1295	sprintf(buffer, "%4.4x btst %s, @%8.8x", opcode, reg_names8[(data16 >> 4) & 0xf], data32 & addr_mask);
	1296	}
	1297	else if ((data16 & 0xff0f) == 0x6000)
	1298	{
	1299	sprintf(buffer, "%4.4x bset %s, @%8.8x", opcode, reg_names8[(data16 >> 4) & 0xf], data32 & addr_mask);
	1300	}
	1301	else
	1302	{
	1303	sprintf(buffer, "%4.4x ???", opcode);
	1304	}
	1305	size = 6;
	1306	break;
1278	1307	case 0x2:
1279	1308	data32=h8_mem_read32(2);
1280	1309	sprintf(buffer, "%4.4x mov.b @%8.8x, %s", opcode, data32&addr_mask, reg_names8[opcode & 0xf]);

trunk/src/emu/cpu/h83002/h8.h

r19182	r19183
1	1	/***************************************************************************
2	2
3		h83002.h : Public constants and function defs for the H8/3002 emulator.
	3	h8.h : Public constants and function defs for the H8/300, H8/300H,
	4	H8/2000S, and H8/2600S family emulators.
4	5
5	6	****************************************************************************/
6	7
7	8	#pragma once
8	9
9		#ifndef __H83002_H__
10		#define __H83002_H__
	10	#ifndef __H8SERIES_H__
	11	#define __H8SERIES_H__
11	12
12	13
13	14	#define IFLAG  0x80
r19182	r19183
121	122	#define H8S_IO_ICRB   H8S_IO(0xFEC1)
122	123	#define H8S_IO_ICRC   H8S_IO(0xFEC2)
123	124
	125	#define H8S_IO_ISCRH  H8S_IO(0xFF2C)
	126	#define H8S_IO_ISCRL  H8S_IO(0xFF2D)
	127
124	128	// for H8S/2394
125	129	#define H8S_IO_IER    H8S_IO(0xFF2E)
126	130	#define H8S_IO_IFR    H8S_IO(0xFF2F)
r19182	r19183
133	137	#define H8S_IO_DTCEE  H8S_IO(0xFF34)
134	138	#define H8S_IO_DTCEF  H8S_IO(0xFF35)
135	139
	140	#define H8S_IO_SYSCR  H8S_IO(0xFF39)
	141
136	142	// port read registers
137	143	#define H8S_IO_PORT1  H8S_IO(0xFF50)
138	144	#define H8S_IO_PORT2  H8S_IO(0xFF51)
r19182	r19183
185	191	#define H8S_IO_SSR2   H8S_IO(0xFF8C)
186	192	#define H8S_IO_RDR2   H8S_IO(0xFF8D)
187	193	#define H8S_IO_SCMR2  H8S_IO(0xFF8E)
	194
	195	// ADC
	196	#define H8S_IO_ADCSR  H8S_IO(0xFFA0)
	197	#define H8S_IO_ADCR   H8S_IO(0xFFA1)
	198
188	199	// 8-bit timer (channel 0 & 1)
189	200	#define H8S_IO_TCR0   H8S_IO(0xFFB0)
190	201	#define H8S_IO_TCR1   H8S_IO(0xFFB1)
r19182	r19183
295	306	#define H8S_IO_DMABCRH H8S_IO(0xFF06)
296	307	#define H8S_IO_DMABCRL H8S_IO(0xFF07)
297	308
	309	#define H8S_IO_ADCSR   H8S_IO(0xFFA0)
	310
298	311	///////////
299	312	// PORTS //
300	313	///////////
r19182	r19183
417	430	DECLARE_LEGACY_CPU_DEVICE(H8S2246, h8s_2246);
418	431	DECLARE_LEGACY_CPU_DEVICE(H8S2323, h8s_2323);
419	432	DECLARE_LEGACY_CPU_DEVICE(H8S2394, h8s_2394);
	433	DECLARE_LEGACY_CPU_DEVICE(H8S2655, h8s_2655);
420	434
421		#endif /* __H83002_H__ */
	435	#endif /* __H8SERIES_H__ */

trunk/src/emu/cpu/h83002/h8priv.h

r19182	r19183
76	76	H8S2XXX_TPU tpu[6];
77	77	H8S2XXX_SCI sci[3];
78	78
	79	int tpu_max;
	80
79	81	UINT8 ddrs[H8_MAX_PORTS], drs[H8_MAX_PORTS], pcrs[H8_MAX_PORTS], odrs[H8_MAX_PORTS];
80	82
81	83	int mode_8bit;
r19182	r19183
122	124	UINT8 h8s2246_per_regs_read_8(h83xx_state *h8, int offset);
123	125	UINT8 h8s2323_per_regs_read_8(h83xx_state *h8, int offset);
124	126	UINT8 h8s2394_per_regs_read_8(h83xx_state *h8, int offset);
	127	UINT8 h8s2655_per_regs_read_8(h83xx_state *h8, int offset);
125	128
126	129	UINT16 h8s2241_per_regs_read_16(h83xx_state *h8, int offset);
127	130	UINT16 h8s2246_per_regs_read_16(h83xx_state *h8, int offset);
128	131	UINT16 h8s2323_per_regs_read_16(h83xx_state *h8, int offset);
129	132	UINT16 h8s2394_per_regs_read_16(h83xx_state *h8, int offset);
	133	UINT16 h8s2655_per_regs_read_16(h83xx_state *h8, int offset);
130	134
131	135	void h8s2241_per_regs_write_8(h83xx_state *h8, int offset, UINT8 data);
132	136	void h8s2246_per_regs_write_8(h83xx_state *h8, int offset, UINT8 data);
133	137	void h8s2323_per_regs_write_8(h83xx_state *h8, int offset, UINT8 data);
134	138	void h8s2394_per_regs_write_8(h83xx_state *h8, int offset, UINT8 data);
	139	void h8s2655_per_regs_write_8(h83xx_state *h8, int offset, UINT8 data);
135	140
136	141	void h8s2241_per_regs_write_16(h83xx_state *h8, int offset, UINT16 data);
137	142	void h8s2246_per_regs_write_16(h83xx_state *h8, int offset, UINT16 data);
138	143	void h8s2323_per_regs_write_16(h83xx_state *h8, int offset, UINT16 data);
139	144	void h8s2394_per_regs_write_16(h83xx_state *h8, int offset, UINT16 data);
	145	void h8s2655_per_regs_write_16(h83xx_state *h8, int offset, UINT16 data);
140	146
141	147	#endif /* __H8PRIV_H__ */

trunk/src/emu/cpu/h83002/h8_16.c

r19182	r19183
723	723	}
724	724	}
725	725
	726	static WRITE16_HANDLER( h8s2655_per_regs_w )
	727	{
	728	h83xx_state *h8 = get_safe_token(&space.device());
	729	if (mem_mask == 0xffff)
	730	{
	731	h8s2655_per_regs_write_16(h8, (offset << 1), data);
	732	}
	733	else if (mem_mask & 0xff00)
	734	{
	735	h8s2655_per_regs_write_8(h8, (offset << 1), (data >> 8) & 0xff);
	736	}
	737	else if (mem_mask == 0x00ff)
	738	{
	739	h8s2655_per_regs_write_8(h8, (offset << 1) + 1, data & 0xff);
	740	}
	741	}
	742
726	743	static READ16_HANDLER( h8s2241_per_regs_r )
727	744	{
728	745	h83xx_state *h8 = get_safe_token(&space.device());
r19182	r19183
795	812	return 0;
796	813	}
797	814
	815	static READ16_HANDLER( h8s2655_per_regs_r )
	816	{
	817	h83xx_state *h8 = get_safe_token(&space.device());
	818	if (mem_mask == 0xffff)
	819	{
	820	return h8s2655_per_regs_read_16(h8, (offset << 1));
	821	}
	822	else if (mem_mask == 0xff00)
	823	{
	824	return h8s2655_per_regs_read_8(h8, (offset << 1)) << 8;
	825	}
	826	else if (mem_mask == 0x00ff)
	827	{
	828	return h8s2655_per_regs_read_8(h8, (offset << 1) + 1);
	829	}
	830	return 0;
	831	}
	832
798	833	// On-board RAM and peripherals
799	834	static ADDRESS_MAP_START( h8_3002_internal_map, AS_PROGRAM, 16, legacy_cpu_device )
800	835	// 512B RAM
r19182	r19183
835	870	AM_RANGE( 0xFFFE40, 0xFFFFFF ) AM_READWRITE_LEGACY( h8s2394_per_regs_r, h8s2394_per_regs_w ) // internal i/o registers
836	871	ADDRESS_MAP_END
837	872
	873	static ADDRESS_MAP_START( h8s_2655_internal_map, AS_PROGRAM, 16, legacy_cpu_device )
	874	AM_RANGE( 0xFFEC00, 0xFFFBFF ) AM_RAM // on-chip ram
	875	AM_RANGE( 0xFFFE40, 0xFFFFFF ) AM_READWRITE_LEGACY( h8s2655_per_regs_r, h8s2655_per_regs_w ) // internal i/o registers
	876	ADDRESS_MAP_END
	877
838	878	CPU_GET_INFO( h8_3002 )
839	879	{
840	880	h83xx_state *h8 = (device != NULL && device->token() != NULL) ? get_safe_token(device) : NULL;
r19182	r19183
989	1029	}
990	1030	}
991	1031
	1032	CPU_GET_INFO( h8s_2655 )
	1033	{
	1034	switch (state)
	1035	{
	1036	case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_PROGRAM: info->internal_map16 = ADDRESS_MAP_NAME(h8s_2655_internal_map);  break;
	1037	case CPUINFO_FCT_SET_INFO:         info->setinfo = CPU_SET_INFO_NAME(h8s_2394);      break;
	1038	case CPUINFO_FCT_INIT:            info->init = CPU_INIT_NAME(h8s_2xxx);      break;
	1039	case CPUINFO_FCT_RESET:            info->reset= CPU_RESET_NAME(h8s_2xxx);         break;
	1040	case CPUINFO_STR_NAME:            strcpy(info->s, "H8S/2655");      break;
	1041	default:
	1042	CPU_GET_INFO_CALL(h8_3002);
	1043	}
	1044	}
	1045
992	1046	DEFINE_LEGACY_CPU_DEVICE(H83002, h8_3002);
993	1047	DEFINE_LEGACY_CPU_DEVICE(H83007, h8_3007);
994	1048	DEFINE_LEGACY_CPU_DEVICE(H83044, h8_3044);
r19182	r19183
997	1051	DEFINE_LEGACY_CPU_DEVICE(H8S2246, h8s_2246);
998	1052	DEFINE_LEGACY_CPU_DEVICE(H8S2323, h8s_2323);
999	1053	DEFINE_LEGACY_CPU_DEVICE(H8S2394, h8s_2394);
	1054	DEFINE_LEGACY_CPU_DEVICE(H8S2655, h8s_2655);
1000	1055

trunk/src/emu/cpu/h83002/h8ops.h

r19182	r19183
1		/*
2
3		H8/3xx: Unknown opcode (PC=1c966) 10f - not a valid H8 or H8S opcode, either bad dump or banked ROM
4		maygayep.c  ep_cfallc
5
6		H8/3xx: Unknown opcode (PC=6bfffefe) 230 - STMAC
7		coinmvga.c  cmkenosp
8
9		H8/3xx: Unknown opcode (PC=67fffefe) 230 - STMAC
10		coinmvga.c  cmkenospa
11
12		H8/3xx: Unknown opcode (PC=8f91) aeb - ADD.L ERs, ERd
13		maygayep.c  ep_hogmnc
14
15		H8/3xx: Unknown opcode (PC=20000) 6b6e - MOV.B @ERs, Rd
16		maygayep.c  ep_wordf
17
18		*/
19
20	1	static UINT32 udata32, address24;
21	2	static INT32 sdata32;
22	3	static UINT16 udata16, ext16;
r19182	r19183
1690	1671	h8_setreg32(h8, H8_SP, h8_getreg32(h8, H8_SP)+4);
1691	1672
1692	1673	// extended mode
1693		h8->pc = udata32;
	1674	h8->pc = udata32 & H8_ADDR_MASK;
1694	1675	}
1695	1676	// must do this last, because set_ccr() does a check_irq()
1696	1677	h8_set_ccr(h8, udata8);
r19182	r19183
1910	1891	H8_IFETCH_TIMING(1);
1911	1892	H8_BYTE_TIMING(1, address24);
1912	1893	break;
	1894	case 0x1:   // btst #xx, @aa:16 or btst Rn, @aa:16
	1895	sdata16 = h8_mem_read16(h8, h8->pc);
	1896	h8->pc += 2;
	1897	address24 = sdata16 & H8_ADDR_MASK;
	1898	udata16 = h8_mem_read16(h8, h8->pc);
	1899	h8->pc += 2;
	1900	udata8 = h8_mem_read8(address24);
	1901	if ((udata16 & 0xff00) == 0x7300)
	1902	{
	1903	h8_btst8(h8, (udata16 >> 4) & 0x7, udata8);
	1904	h8_mem_write8(address24, udata8);
	1905	}
	1906	else if ((udata16 & 0xff0f) == 0x7000)
	1907	{
	1908	h8_bset8(h8, (udata16 >> 4) & 0x7, udata8);
	1909	h8_mem_write8(address24, udata8);
	1910	}
	1911	else if ((udata16 & 0xff00) == 0x6300)
	1912	{
	1913	h8_btst8(h8, h8_getreg8(h8, (udata16 >> 4) & 0xf), udata8);
	1914	h8_mem_write8(address24, udata8);
	1915	}
	1916	else if ((udata16 & 0xff0f) == 0x6000)
	1917	{
	1918	h8_bset8(h8, h8_getreg8(h8, (udata16 >> 4) & 0xf), udata8);
	1919	h8_mem_write8(address24, udata8);
	1920	}
	1921	else
	1922	{
	1923	h8->h8err = 1;
	1924	}
	1925	H8_IFETCH_TIMING(3);
	1926	H8_BYTE_TIMING(1, address24);
	1927	break;
1913	1928	case 0x2:
1914	1929	address24=h8_mem_read32(h8, h8->pc);
1915	1930	h8->pc += 4;
r19182	r19183
4219	4234	if(h8->h8zflag == 1)taken = 1;
4220	4235	break;
4221	4236	case 8: // bvc V = 0
4222		h8->h8err = 1;
4223	4237	if(h8->h8vflag == 0)taken = 1;
4224	4238	break;
4225	4239	case 9: // bvs V = 1
4226		h8->h8err = 1;
4227	4240	if(h8->h8vflag == 1)taken = 1;
4228	4241	break;
4229	4242	case 0xa: // bpl N = 0

trunk/src/emu/cpu/h83002/h8speriph.c

r19182	r19183
8	8	H8S/2246
9	9	H8S/2323
10	10	H8S/2394
	11	H8S/2655
11	12	*/
12	13
13	14	#include "emu.h"
r19182	r19183
404	405
405	406	void h8s_periph_reset(h83xx_state *h8)
406	407	{
407		const int tpu_max = ((h8->device->type() == H8S2323) || (h8->device->type() == H8S2394)) ? 6 : 3;
	408	int tpu_max = h8->tpu_max;
	409	h8->tpu_max = tpu_max;
408	410	if ((h8->device->type() == H8S2241) || (h8->device->type() == H8S2246))
409	411	{
410	412	memcpy( h8->per_regs, H8S_RESET_H8S_IO_224x, sizeof( h8->per_regs));
411	413	}
412		else if ((h8->device->type() == H8S2323) || (h8->device->type() == H8S2394))
	414	else if ((h8->device->type() == H8S2323) || (h8->device->type() == H8S2394) || (h8->device->type() == H8S2655))
413	415	{
414	416	memcpy( h8->per_regs, H8S_RESET_H8S_IO_2323, sizeof( h8->per_regs));
415	417	}
416	418	for (int i = 0; i < 2; i++) h8s_tmr_x_reset( h8, i);
417		for (int i = 0; i < tpu_max; i++) h8s_tpu_x_reset( h8, i);
	419	for (int i = 0; i < tpu_max; i++) h8s_tpu_x_reset( h8, i );
418	420	}
419	421
420	422	/////////////////
r19182	r19183
659	661
660	662	void h8s_tpu_init(h83xx_state *h8)
661	663	{
662		const int tpu_max = ((h8->device->type() == H8S2323) || (h8->device->type() == H8S2394)) ? 6 : 3;
	664	const int tpu_max = ((h8->device->type() == H8S2323) || (h8->device->type() == H8S2394) || (h8->device->type() == H8S2655)) ? 6 : 3;
663	665	for (int i = 0; i < tpu_max; i++)
664	666	{
665	667	h8->tpu[i].timer = h8->device->machine().scheduler().timer_alloc(FUNC(h8s_tpu_callback), h8);
r19182	r19183
1128	1130
1129	1131	void h8s_tpu_write_tstr( h83xx_state *h8, UINT8 data)
1130	1132	{
1131		const int tpu_max = ((h8->device->type() == H8S2323) || (h8->device->type() == H8S2394)) ? 6 : 3;
	1133	const int tpu_max = h8->tpu_max;
1132	1134	UINT8 old_data = h8->per_regs[H8S_IO_TSTR];
1133	1135	int i;
1134	1136	h8->per_regs[H8S_IO_TSTR] = data;
r19182	r19183
1345	1347	case H8S_IO_DMABCRL :
1346	1348	{
1347	1349	h8->per_regs[offset] = data;
1348		if ((h8->device->type() == H8S2323) || (h8->device->type() == H8S2394))
	1350	if ((h8->device->type() == H8S2323) || (h8->device->type() == H8S2394) || (h8->device->type() == H8S2655))
1349	1351	{
1350	1352	if ((data & 0x40) && (data & 0x80))
1351	1353	{
r19182	r19183
1428	1430	break;
1429	1431
1430	1432	// ...
1431		#if 0
1432	1433	// TPU
1433	1434	case H8S_IO_TSTR  : h8s_tpu_write_tstr( h8, data); break;
1434	1435	// DMA
1435	1436	case H8S_IO_DMABCRL :
1436	1437	{
1437	1438	h8->per_regs[offset] = data;
1438		if ((h8->device->type() == H8S2323) || (h8->device->type() == H8S2394))
	1439	if ((h8->device->type() == H8S2323) || (h8->device->type() == H8S2394) || (h8->device->type() == H8S2655))
1439	1440	{
1440	1441	if ((data & 0x40) && (data & 0x80))
1441	1442	{
r19182	r19183
1458	1459	}
1459	1460	}
1460	1461	break;
1461		#endif
1462	1462	// ...
1463	1463	default :
1464	1464	{
1465		logerror("H8S: Unknown write %02x to I/O %x\n", data, offset);
1466	1465	h8->per_regs[offset] = data;
1467	1466	}
1468	1467	break;
r19182	r19183
1489	1488	case H8S_IO_TGR2A_H : h8s_tpu_x_write_tgra( h8, 2, data); break;
1490	1489	case H8S_IO_TGR2B_H : h8s_tpu_x_write_tgrb( h8, 2, data); break;
1491	1490	// TPU 3
1492		case H8S_IO_TCNT3_H : if ((h8->device->type() == H8S2323) || (h8->device->type() == H8S2394)) h8s_tpu_x_write_tcnt( h8, 3, data); break;
1493		case H8S_IO_TGR3A_H : if ((h8->device->type() == H8S2323) || (h8->device->type() == H8S2394)) h8s_tpu_x_write_tgra( h8, 3, data); break;
1494		case H8S_IO_TGR3B_H : if ((h8->device->type() == H8S2323) || (h8->device->type() == H8S2394)) h8s_tpu_x_write_tgrb( h8, 3, data); break;
1495		case H8S_IO_TGR3C_H : if ((h8->device->type() == H8S2323) || (h8->device->type() == H8S2394)) h8s_tpu_x_write_tgrc( h8, 3, data); break;
1496		case H8S_IO_TGR3D_H : if ((h8->device->type() == H8S2323) || (h8->device->type() == H8S2394)) h8s_tpu_x_write_tgrd( h8, 3, data); break;
	1491	case H8S_IO_TCNT3_H : if (h8->tpu_max == 6) h8s_tpu_x_write_tcnt( h8, 3, data); break;
	1492	case H8S_IO_TGR3A_H : if (h8->tpu_max == 6 ) h8s_tpu_x_write_tgra( h8, 3, data); break;
	1493	case H8S_IO_TGR3B_H : if (h8->tpu_max == 6 ) h8s_tpu_x_write_tgrb( h8, 3, data); break;
	1494	case H8S_IO_TGR3C_H : if (h8->tpu_max == 6 ) h8s_tpu_x_write_tgrc( h8, 3, data); break;
	1495	case H8S_IO_TGR3D_H : if (h8->tpu_max == 6 ) h8s_tpu_x_write_tgrd( h8, 3, data); break;
1497	1496	// TPU 4
1498		case H8S_IO_TCNT4_H : if ((h8->device->type() == H8S2323) || (h8->device->type() == H8S2394)) h8s_tpu_x_write_tcnt( h8, 4, data); break;
1499		case H8S_IO_TGR4A_H : if ((h8->device->type() == H8S2323) || (h8->device->type() == H8S2394)) h8s_tpu_x_write_tgra( h8, 4, data); break;
1500		case H8S_IO_TGR4B_H : if ((h8->device->type() == H8S2323) || (h8->device->type() == H8S2394)) h8s_tpu_x_write_tgrb( h8, 4, data); break;
	1497	case H8S_IO_TCNT4_H : if (h8->tpu_max == 6 ) h8s_tpu_x_write_tcnt( h8, 4, data); break;
	1498	case H8S_IO_TGR4A_H : if (h8->tpu_max == 6 ) h8s_tpu_x_write_tgra( h8, 4, data); break;
	1499	case H8S_IO_TGR4B_H : if (h8->tpu_max == 6 ) h8s_tpu_x_write_tgrb( h8, 4, data); break;
1501	1500	// TPU 5
1502		case H8S_IO_TCNT5_H : if ((h8->device->type() == H8S2323) || (h8->device->type() == H8S2394)) h8s_tpu_x_write_tcnt( h8, 5, data); break;
1503		case H8S_IO_TGR5A_H : if ((h8->device->type() == H8S2323) || (h8->device->type() == H8S2394)) h8s_tpu_x_write_tgra( h8, 5, data); break;
1504		case H8S_IO_TGR5B_H : if ((h8->device->type() == H8S2323) || (h8->device->type() == H8S2394)) h8s_tpu_x_write_tgrb( h8, 5, data); break;
	1501	case H8S_IO_TCNT5_H : if (h8->tpu_max == 6 ) h8s_tpu_x_write_tcnt( h8, 5, data); break;
	1502	case H8S_IO_TGR5A_H : if (h8->tpu_max == 6 ) h8s_tpu_x_write_tgra( h8, 5, data); break;
	1503	case H8S_IO_TGR5B_H : if (h8->tpu_max == 6 ) h8s_tpu_x_write_tgrb( h8, 5, data); break;
1505	1504	// ...
1506	1505	default :
1507	1506	{
r19182	r19183
1595	1594	}
1596	1595	break;
1597	1596
1598		#if 0
	1597	// ADCSR
	1598	case H8S_IO_ADCSR:   data = ADCSR_ADF; break;
	1599
1599	1600	// TMR 0
1600	1601	case H8S_IO_TCNT0 : data = h8s_tmr_x_read_tcnt( h8, 0); break;
1601	1602	// TMR 1
1602	1603	case H8S_IO_TCNT1 : data = h8s_tmr_x_read_tcnt( h8, 1); break;
1603		#endif
1604	1604	// ...
1605	1605	// default
1606		default : data = h8->per_regs[offset]; logerror("H8S: unhandled I/O read at %x\n", offset); break;
	1606	default : data = h8->per_regs[offset]; logerror("H8S: possibly unhandled I/O read at %x (PC=%x)\n", offset, h8->ppc); break;
1607	1607	}
1608	1608	verboselog( h8->device->machine(), 9, "%08X | %08X -> %02X\n", h8->ppc, H8S_IO_ADDR(offset), data);
1609	1609	return data;
r19182	r19183
1617	1617	case H8S_IO_TCNT0_H : data = h8s_tpu_x_read_tcnt( h8, 0); break;
1618	1618	case H8S_IO_TCNT1_H : data = h8s_tpu_x_read_tcnt( h8, 1); break;
1619	1619	case H8S_IO_TCNT2_H : data = h8s_tpu_x_read_tcnt( h8, 2); break;
1620		case H8S_IO_TCNT3_H : if ((h8->device->type() == H8S2323) || (h8->device->type() == H8S2394)) data = h8s_tpu_x_read_tcnt( h8, 3); break;
1621		case H8S_IO_TCNT4_H : if ((h8->device->type() == H8S2323) || (h8->device->type() == H8S2394)) data = h8s_tpu_x_read_tcnt( h8, 4); break;
1622		case H8S_IO_TCNT5_H : if ((h8->device->type() == H8S2323) || (h8->device->type() == H8S2394)) data = h8s_tpu_x_read_tcnt( h8, 5); break;
	1620	case H8S_IO_TCNT3_H : if (h8->tpu_max == 6) data = h8s_tpu_x_read_tcnt( h8, 3); break;
	1621	case H8S_IO_TCNT4_H : if (h8->tpu_max == 6) data = h8s_tpu_x_read_tcnt( h8, 4); break;
	1622	case H8S_IO_TCNT5_H : if (h8->tpu_max == 6) data = h8s_tpu_x_read_tcnt( h8, 5); break;
1623	1623	default :
1624	1624	{
1625	1625	UINT8 b[2];
r19182	r19183
1713	1713	return h8s_onchip_reg_read_16(h8, offset);
1714	1714	}
1715	1715
	1716	void h8s2655_per_regs_write_8(h83xx_state *h8, int offset, UINT8 data)
	1717	{
	1718	h8s_onchip_reg_write_8_ddr(h8, offset, data);
	1719	}
1716	1720
	1721	UINT8 h8s2655_per_regs_read_8(h83xx_state *h8, int offset)
	1722	{
	1723	return h8s_onchip_reg_read_8_ddr(h8, offset);
	1724	}
	1725
	1726	void h8s2655_per_regs_write_16(h83xx_state *h8, int offset, UINT16 data)
	1727	{
	1728	h8s_onchip_reg_write_16(h8, offset, data);
	1729	}
	1730
	1731	UINT16 h8s2655_per_regs_read_16(h83xx_state *h8, int offset)
	1732	{
	1733	return h8s_onchip_reg_read_16(h8, offset);
	1734	}
	1735

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