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r18715 Friday 26th October, 2012 at 02:47:23 UTC by Ryan Holtz
-avr8.c: Fixed register indexing for MULSU opcode. [MooglyGuy]

-avr8.c: Fixed register writeback for LD -Z and LD -Y opcodes. [MooglyGuy]

-craft.c: Preliminary video support, bad vsync and colors still. [MooglyGuy]
[src/emu/cpu/avr8]avr8.c avr8.h
[src/mess/drivers]craft.c

trunk/src/mess/drivers/craft.c
r18714r18715
2929#define verboselog(x,y,z,...)
3030#endif
3131
32#define MASTER_CLOCK 20000000
32#define MASTER_CLOCK    20000000
3333
34#define VISIBLE_CYCLES       480
35#define HSYNC_CYCLES       155
36#define LINE_CYCLES       (VISIBLE_CYCLES + HSYNC_CYCLES)
37#define VISIBLE_LINES      480
38#define VSYNC_LINES         45
39#define LINES_PER_FRAME      (VISIBLE_LINES + VSYNC_LINES)
40#define CYCLES_PER_FRAME   (LINES_PER_FRAME * LINE_CYCLES)
41#define PIXELS_PER_FRAME   (CYCLES_PER_FRAME)
42
3443/****************************************************\
3544* I/O defines                                        *
3645\****************************************************/
3746
3847#define AVR8_DDRD            (state->m_regs[AVR8_REGIDX_DDRD])
48#define AVR8_PORTC            (state->m_regs[AVR8_REGIDX_PORTC])
3949#define AVR8_DDRC            (state->m_regs[AVR8_REGIDX_DDRC])
4050#define AVR8_PORTB            (state->m_regs[AVR8_REGIDX_PORTB])
4151#define AVR8_DDRB            (state->m_regs[AVR8_REGIDX_DDRB])
r18714r18715
7282
7383   UINT8 m_regs[0x100];
7484    UINT8* m_eeprom;
85    UINT32 last_cycles;
7586
87    bool spi_pending;
88    UINT32 spi_start_cycle;
89
90    UINT8 m_pixels[PIXELS_PER_FRAME + LINE_CYCLES]; // Allocate one extra line for wrapping in the video update
91
7692    required_device<cpu_device> m_maincpu;
7793
7894   DECLARE_READ8_MEMBER(avr8_read);
r18714r18715
141157   }
142158}
143159
160static void avr8_video_update(running_machine &machine)
161{
162    craft_state *state = machine.driver_data<craft_state>();
163
164   UINT64 cycles = avr8_get_elapsed_cycles(state->m_maincpu);
165   UINT32 frame_cycles = (UINT32)(cycles % CYCLES_PER_FRAME);
166
167   if (state->last_cycles < frame_cycles)
168   {
169      for (UINT32 pixidx = state->last_cycles; pixidx < frame_cycles; pixidx++)
170      {
171         UINT8 value = AVR8_PORTC & 0x3f;
172         if (state->spi_pending)
173         {
174            if (pixidx >= state->spi_start_cycle && pixidx < (state->spi_start_cycle + 16))
175            {
176               UINT8 bitidx = 7 - ((pixidx - state->spi_start_cycle) >> 1);
177               value = ((state->m_regs[AVR8_REGIDX_SPDR] & (1 << bitidx)) ? value : 0x3f);
178               if (pixidx == (state->spi_start_cycle + 15))
179               {
180                  state->spi_pending = false;
181                  state->m_regs[AVR8_REGIDX_SPDR] = 0;
182               }
183            }
184         }
185         state->m_pixels[pixidx] = value;
186      }
187   }
188
189   state->last_cycles = frame_cycles;
190}
191
144192static void avr8_change_port(running_machine &machine, int reg, UINT8 data)
145193{
146194    craft_state *state = machine.driver_data<craft_state>();
r18714r18715
156204      //verboselog(machine, 0, "avr8_change_port: PORT%c lines %02x changed\n", avr8_reg_name[reg], changed);
157205   }
158206
159   if (reg == AVR8_REG_D) {
207   if (reg == AVR8_REG_C)
208   {
209      avr8_video_update(machine);
210
211      /*if (frame_cycles >= state->spi_start_cycle && frame_cycles < (state->spi_start_cycle + 16))
212      {
213         UINT8 bitidx = 7 - ((frame_cycles - state->spi_start_cycle) >> 1);
214         state->m_pixels[frame_cycles] = ((state->m_regs[AVR8_REGIDX_SPDR] & (1 << bitidx)) ? 0x3f : (data & 0x3f));
215      }
216      else
217      {
218         state->m_pixels[frame_cycles] = data & 0x3f;
219      }*/
220
221      AVR8_PORTC = data;
222   }
223
224   if (reg == AVR8_REG_D)
225   {
160226      UINT8 audio_sample = (data & 0x02) | ((data & 0xf4) >> 2);
161227
162228      state->dac->write_unsigned8(audio_sample << 2);
r18714r18715
289355         break;
290356
291357      case AVR8_REGIDX_SPDR:
292         // TODO
358         avr8_video_update(machine());
359         m_regs[offset] = data;
360         spi_pending = true;
361         spi_start_cycle = (UINT32)(avr8_get_elapsed_cycles(m_maincpu) % CYCLES_PER_FRAME);
293362         break;
294363
295364      case AVR8_REGIDX_EECR:
r18714r18715
363432
364433UINT32 craft_state::screen_update_craft(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
365434{
435   for(int y = 0; y < LINES_PER_FRAME; y++)
436   {
437      UINT32 *line = &bitmap.pix32(y);
438      for(int x = 0; x < LINE_CYCLES; x++)
439      {
440         UINT8 pixel = m_pixels[y * LINE_CYCLES + (x + HSYNC_CYCLES)];
441         UINT8 r = 0x55 * ((pixel & 0x30) >> 4);
442         UINT8 g = 0x55 * ((pixel & 0x0c) >> 2);
443         UINT8 b = 0x55 * (pixel & 0x03);
444         line[x] = 0xff000000 | (r << 16) | (g << 8) | b;
445
446         // Clear behind us
447         m_pixels[y * LINE_CYCLES + (x + HSYNC_CYCLES)] = 0;
448      }
449   }
366450    return 0;
367451}
368452
r18714r18715
395479
396480    /* video hardware */
397481    MCFG_SCREEN_ADD("screen", RASTER)
398    //MCFG_SCREEN_RAW_PARAMS( MASTER_CLOCK, 634, 0, 633, 525, 0, 481 )
399    MCFG_SCREEN_REFRESH_RATE(60.08)
400    MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(1395)) /* accurate */
401    MCFG_SCREEN_SIZE(634, 480)
402    MCFG_SCREEN_VISIBLE_AREA(0, 633, 0, 479)
482    MCFG_SCREEN_REFRESH_RATE(59.99)
483    MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(1429)) /* accurate */
484    MCFG_SCREEN_SIZE(635, 525)
485    MCFG_SCREEN_VISIBLE_AREA(0, 634, 0, 524)
403486   MCFG_SCREEN_UPDATE_DRIVER(craft_state, screen_update_craft)
404
405487    MCFG_PALETTE_LENGTH(0x1000)
406488
407489    /* sound hardware */
trunk/src/emu/cpu/avr8/avr8.c
r18714r18715
367367    return READ_IO_8(cpustate, sp);
368368}
369369
370UINT64 avr8_get_elapsed_cycles(device_t *device)
371{
372   return get_safe_token(device)->elapsed_cycles;
373}
374
370375/*****************************************************************************/
371376// Interrupts
372377
r18714r18715
429434   }
430435}
431436
432/*static void avr8_poll_interrupt(avr8_state *cpustate)
433{
434   for (int idx = 0; idx < AVR8_INTIDX_COUNT; idx++)
435   {
436      avr8_update_interrupt_internal(cpustate, idx);
437   }
438}*/
439
440437void avr8_update_interrupt(device_t *device, int source)
441438{
442439   avr8_state *cpustate = get_safe_token(device);
r18714r18715
10361033      case AVR8_REGIDX_TCNT1L:
10371034      case AVR8_REGIDX_TCNT1H:
10381035      case AVR8_REGIDX_GPIOR0:
1036      case AVR8_REGIDX_TCNT2:
10391037         *data = cpustate->r[offset];
10401038         return true;
10411039
r18714r18715
11001098
11011099   cpustate->interrupt_pending = false;
11021100
1101   cpustate->elapsed_cycles = 0;
1102
11031103   device->save_item(NAME(cpustate->pc));
11041104}
11051105
r18714r18715
11131113
11141114   cpustate->status = 0;
11151115    cpustate->pc = 0;
1116    cpustate->elapsed_cycles = 0;
11161117
11171118    cpustate->interrupt_pending = false;
11181119}
r18714r18715
11601161                        opcycles = 2;
11611162                        break;
11621163                    case 0x0300:    // MULSU Rd,Rr
1163                        sd = (INT8)cpustate->r[16 + RD4(op)] * (UINT8)cpustate->r[16 + RR4(op)];
1164                        sd = (INT8)cpustate->r[16 + RD3(op)] * (UINT8)cpustate->r[16 + RR3(op)];
11641165                        cpustate->r[1] = (sd >> 8) & 0x00ff;
11651166                        cpustate->r[0] = sd & 0x00ff;
11661167                        SREG_W(AVR8_SREG_C, (sd & 0x8000) ? 1 : 0);
r18714r18715
13931394                                pd = ZREG;
13941395                                pd--;
13951396                                cpustate->r[RD5(op)] = READ_IO_8(cpustate, pd);
1396                                cpustate->r[27] = (pd >> 8) & 0x00ff;
1397                                cpustate->r[26] = pd & 0x00ff;
1397                                cpustate->r[31] = (pd >> 8) & 0x00ff;
1398                                cpustate->r[30] = pd & 0x00ff;
13981399                                opcycles = 2;
13991400                                break;
14001401                            case 0x0004:    // LPM Rd,Z
r18714r18715
14291430                                pd = YREG;
14301431                                pd--;
14311432                                cpustate->r[RD5(op)] = READ_IO_8(cpustate, pd);
1432                                cpustate->r[27] = (pd >> 8) & 0x00ff;
1433                                cpustate->r[26] = pd & 0x00ff;
1433                                cpustate->r[29] = (pd >> 8) & 0x00ff;
1434                                cpustate->r[28] = pd & 0x00ff;
14341435                                opcycles = 2;
14351436                                break;
14361437                            case 0x000c:    // LD Rd,X
r18714r18715
19701971                        }
19711972                        else            // SBRC Rd, b
19721973                        {
1973                            if(!BIT(cpustate->r[RD5(op)], RR3(op)))
1974                            if(NOT(BIT(cpustate->r[RD5(op)], RR3(op))))
19741975                            {
19751976                                op = (UINT32)READ_PRG_16(cpustate, cpustate->pc++);
19761977                                cpustate->pc += avr8_is_long_opcode(op) ? 1 : 0;
r18714r18715
19861987
19871988        cpustate->icount -= opcycles;
19881989
1990      cpustate->elapsed_cycles += opcycles;
1991
19891992      avr8_timer_tick(cpustate, opcycles);
19901993    }
19911994}
trunk/src/emu/cpu/avr8/avr8.h
r18714r18715
4141   UINT16 timer2_prescale;
4242   UINT16 timer2_prescale_count;
4343
44   UINT64 elapsed_cycles;
45
4446   bool interrupt_pending;
4547};
4648
r18714r18715
301303DECLARE_LEGACY_CPU_DEVICE(ATMEGA644, atmega644);
302304
303305void avr8_update_interrupt(device_t *device, int source);
306UINT64 avr8_get_elapsed_cycles(device_t *device);
304307
305308CPU_DISASSEMBLE( avr8 );
306309

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