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r18714 Friday 26th October, 2012 at 01:12:21 UTC by smf
cleaned up the ide controller enough to change the irq to a DEVCB2 [smf]
[src/emu/machine]idectrl.c idectrl.h
[src/mame/audio]jaguar.c
[src/mame/drivers]atlantis.c calchase.c chihiro.c cobra.c djmain.c funkball.c gamecstl.c jaguar.c kinst.c mediagx.c midqslvr.c midvunit.c qdrmfgp.c queen.c savquest.c seattle.c taitogn.c taitotz.c taitowlf.c twinkle.c vegas.c viper.c voyager.c xtom3d.c zn.c
[src/mame/includes]djmain.h jaguar.h qdrmfgp.h
[src/mess/drivers]bebox.c
[src/mess/includes]bebox.h
[src/mess/machine]a2cffa.c bebox.c c64_ide64.c isa_ide.c isa_ide.h kc_d004.c
[src/mess/machine/ti99]tn_ide.c tn_ide.h

trunk/src/mame/audio/jaguar.c
r18713r18714
178178}
179179
180180
181void jaguar_state::external_int(device_t *device, int newstate)
181WRITE_LINE_MEMBER( jaguar_state::external_int )
182182{
183   jaguar_state &state = *device->machine().driver_data<jaguar_state>();
184   if (newstate != CLEAR_LINE)
185      state.m_gpu_irq_state |= 1;
183   if (state != CLEAR_LINE)
184      m_gpu_irq_state |= 1;
186185   else
187      state.m_gpu_irq_state &= ~1;
188   state.update_gpu_irq();
186      m_gpu_irq_state &= ~1;
187   update_gpu_irq();
189188}
190189
191190
trunk/src/mame/includes/djmain.h
r18713r18714
5555   virtual void video_start();
5656   UINT32 screen_update_djmain(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
5757   INTERRUPT_GEN_MEMBER(vb_interrupt);
58   DECLARE_WRITE_LINE_MEMBER(ide_interrupt);
5859};
5960
6061/*----------- defined in video/djmain.c -----------*/
trunk/src/mame/includes/qdrmfgp.h
r18713r18714
4242   INTERRUPT_GEN_MEMBER(qdrmfgp2_interrupt);
4343   TIMER_CALLBACK_MEMBER(gp2_timer_callback);
4444   TIMER_DEVICE_CALLBACK_MEMBER(qdrmfgp_interrupt);
45   DECLARE_WRITE_LINE_MEMBER(ide_interrupt);
46   DECLARE_WRITE_LINE_MEMBER(gp2_ide_interrupt);
4547};
4648
4749/*----------- defined in video/qdrmfgp.c -----------*/
trunk/src/mame/includes/jaguar.h
r18713r18714
209209
210210   static void gpu_cpu_int(device_t *device);
211211   static void dsp_cpu_int(device_t *device);
212   static void external_int(device_t *device, int state);
212   DECLARE_WRITE_LINE_MEMBER( external_int );
213213
214214   int quickload(device_image_interface &image, const char *file_type, int quickload_size);
215215   void cart_start();
trunk/src/mame/drivers/mediagx.c
r18713r18714
180180   DECLARE_WRITE_LINE_MEMBER(pc_dack2_w);
181181   DECLARE_WRITE_LINE_MEMBER(pc_dack3_w);
182182   DECLARE_WRITE_LINE_MEMBER(mediagx_pic8259_1_set_int_line);
183   DECLARE_WRITE_LINE_MEMBER(ide_interrupt);
183184   DECLARE_READ8_MEMBER(get_slave_ack);
184185   DECLARE_DRIVER_INIT(a51site4);
185186   virtual void machine_start();
r18713r18714
230231#define DC_CFIFO_DIAG         0x7c/4
231232
232233
233static void ide_interrupt(device_t *device, int state);
234234
235235
236236
r18713r18714
11631163   0
11641164};
11651165
1166static const ide_config ide_intf =
1167{
1168   ide_interrupt,
1169   NULL,
1170   0
1171};
1172
11731166static MACHINE_CONFIG_START( mediagx, mediagx_state )
11741167
11751168   /* basic machine hardware */
r18713r18714
11911184
11921185   MCFG_PIC8259_ADD( "pic8259_slave", mediagx_pic8259_2_config )
11931186
1194   MCFG_IDE_CONTROLLER_ADD("ide", ide_intf, ide_devices, "hdd", NULL, true)
1187   MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
1188   MCFG_IDE_CONTROLLER_IRQ_HANDLER(DEVWRITELINE(DEVICE_SELF_OWNER, mediagx_state, ide_interrupt))
11951189
11961190   MCFG_TIMER_DRIVER_ADD("sound_timer", mediagx_state, sound_timer_callback)
11971191
r18713r18714
12321226   pic8259_ir1_w(state->m_pic8259_1, _state);
12331227}
12341228
1235static void ide_interrupt(device_t *device, int _state)
1229WRITE_LINE_MEMBER( mediagx_state::ide_interrupt )
12361230{
1237   mediagx_state *state = device->machine().driver_data<mediagx_state>();
1238
1239   pic8259_ir6_w(state->m_pic8259_2, _state);
1231   pic8259_ir6_w(m_pic8259_2, state);
12401232}
12411233
12421234static int mediagx_get_out2(running_machine &machine)
trunk/src/mame/drivers/taitowlf.c
r18713r18714
7777   DECLARE_WRITE_LINE_MEMBER(pc_dack2_w);
7878   DECLARE_WRITE_LINE_MEMBER(pc_dack3_w);
7979   DECLARE_WRITE_LINE_MEMBER(taitowlf_pic8259_1_set_int_line);
80   DECLARE_WRITE_LINE_MEMBER(ide_interrupt);
8081   DECLARE_READ8_MEMBER(get_slave_ack);
8182   DECLARE_DRIVER_INIT(taitowlf);
8283   virtual void machine_start();
r18713r18714
114115}
115116#endif
116117
117static void ide_interrupt(device_t *device, int state);
118118
119
120119READ8_MEMBER(taitowlf_state::at_dma8237_2_r)
121120{
122121   device_t *device = machine().device("dma8237_2");
r18713r18714
628627}
629628#endif
630629
631static const ide_config ide_intf =
632{
633   ide_interrupt,
634   NULL,
635   0
636};
637
638630static MACHINE_CONFIG_START( taitowlf, taitowlf_state )
639631
640632   /* basic machine hardware */
r18713r18714
652644   MCFG_I8237_ADD( "dma8237_2", XTAL_14_31818MHz/3, dma8237_2_config )
653645   MCFG_PIC8259_ADD( "pic8259_1", taitowlf_pic8259_1_config )
654646   MCFG_PIC8259_ADD( "pic8259_2", taitowlf_pic8259_2_config )
655   MCFG_IDE_CONTROLLER_ADD("ide", ide_intf, ide_devices, "hdd", NULL, true)
647   MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
648   MCFG_IDE_CONTROLLER_IRQ_HANDLER(DEVWRITELINE(DEVICE_SELF_OWNER, taitowlf_state, ide_interrupt))
656649   MCFG_MC146818_ADD( "rtc", MC146818_STANDARD )
657650
658651   /* video hardware */
r18713r18714
681674   pic8259_ir1_w(drvstate->m_pic8259_1, state);
682675}
683676
684static void ide_interrupt(device_t *device, int state)
677WRITE_LINE_MEMBER(taitowlf_state::ide_interrupt)
685678{
686   taitowlf_state *drvstate = device->machine().driver_data<taitowlf_state>();
687   pic8259_ir6_w(drvstate->m_pic8259_2, state);
679   pic8259_ir6_w(m_pic8259_2, state);
688680}
689681
690682static int taitowlf_get_out2(running_machine &machine)
trunk/src/mame/drivers/funkball.c
r18713r18714
162162   DECLARE_READ8_MEMBER(io20_r);
163163   DECLARE_WRITE8_MEMBER(io20_w);
164164   DECLARE_WRITE_LINE_MEMBER(funkball_pic8259_1_set_int_line);
165   DECLARE_WRITE_LINE_MEMBER(ide_interrupt);
165166   virtual void machine_start();
166167   virtual void machine_reset();
167168   UINT32 screen_update_funkball(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
r18713r18714
11001101   return pic8259_acknowledge( state->m_pic8259_1);
11011102}
11021103
1103static void ide_interrupt(device_t *device, int state)
1104WRITE_LINE_MEMBER(funkball_state::ide_interrupt)
11041105{
1105   funkball_state *drvstate = device->machine().driver_data<funkball_state>();
1106   pic8259_ir6_w(drvstate->m_pic8259_2, state);
1106   pic8259_ir6_w(m_pic8259_2, state);
11071107}
11081108
11091109void funkball_state::machine_start()
r18713r18714
11411141   return 0;
11421142}
11431143
1144static const ide_config ide_intf =
1145{
1146   ide_interrupt,
1147   NULL,
1148   0
1149};
1150
11511144static const voodoo_config voodoo_intf =
11521145{
11531146   2, //               fbmem;
r18713r18714
11771170   MCFG_PCI_BUS_LEGACY_DEVICE(7, "voodoo_0", voodoo_0_pci_r, voodoo_0_pci_w)
11781171   MCFG_PCI_BUS_LEGACY_DEVICE(18, NULL, cx5510_pci_r, cx5510_pci_w)
11791172
1180   MCFG_IDE_CONTROLLER_ADD("ide", ide_intf, ide_devices, "hdd", NULL, true)
1173   MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
1174   MCFG_IDE_CONTROLLER_IRQ_HANDLER(DEVWRITELINE(DEVICE_SELF_OWNER, funkball_state, ide_interrupt))
11811175
11821176   /* video hardware */
11831177   MCFG_3DFX_VOODOO_1_ADD("voodoo_0", STD_VOODOO_1_CLOCK, voodoo_intf)
trunk/src/mame/drivers/viper.c
r18713r18714
19961996   mpc8240_interrupt(device->machine(), MPC8240_IRQ4);
19971997}
19981998
1999static void ide_interrupt(device_t *device, int state)
2000{
2001}
2002
20031999void viper_state::machine_start()
20042000{
20052001   ds2430_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(viper_state::ds2430_timer_callback),this));
r18713r18714
20172013
20182014void viper_state::machine_reset()
20192015{
2020   machine().device("ide")->reset();
2016   ide_controller_device *ide = (ide_controller_device *) machine().device("ide");
2017
2018   ide->reset();
20212019   mpc8240_epic_reset();
20222020
2023   UINT8 *ide_features = ide_get_features(machine().device("ide"), 0);
2021   UINT8 *ide_features = ide->ide_get_features(0);
20242022
20252023   // Viper expects these settings or the BIOS fails
20262024   ide_features[51*2+0] = 0;         /* 51: PIO data transfer cycle timing mode */
r18713r18714
20292027   ide_features[67*2+1] = 0x00;
20302028}
20312029
2032static const ide_config ide_intf =
2033{
2034   ide_interrupt,
2035   NULL,
2036   0
2037};
2038
20392030static const voodoo_config voodoo_intf =
20402031{
20412032   8, //               fbmem;
r18713r18714
20602051   MCFG_PCI_BUS_LEGACY_DEVICE(0, "mpc8240", mpc8240_pci_r, mpc8240_pci_w)
20612052   MCFG_PCI_BUS_LEGACY_DEVICE(12, "voodoo", voodoo3_pci_r, voodoo3_pci_w)
20622053
2063   MCFG_IDE_CONTROLLER_ADD("ide", ide_intf, ide_devices, "hdd", NULL, true)
2054   MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
2055
20642056   MCFG_3DFX_VOODOO_3_ADD("voodoo", STD_VOODOO_3_CLOCK, voodoo_intf)
20652057
20662058   /* video hardware */
trunk/src/mame/drivers/gamecstl.c
r18713r18714
114114   DECLARE_WRITE_LINE_MEMBER(pc_dack2_w);
115115   DECLARE_WRITE_LINE_MEMBER(pc_dack3_w);
116116   DECLARE_WRITE_LINE_MEMBER(gamecstl_pic8259_1_set_int_line);
117   DECLARE_WRITE_LINE_MEMBER(ide_interrupt);
117118   DECLARE_READ8_MEMBER(get_slave_ack);
118119   DECLARE_DRIVER_INIT(gamecstl);
119120   virtual void machine_start();
r18713r18714
123124};
124125
125126
126static void ide_interrupt(device_t *device, int state);
127
128
129127static const rgb_t cga_palette[16] =
130128{
131129   MAKE_RGB( 0x00, 0x00, 0x00 ), MAKE_RGB( 0x00, 0x00, 0xaa ), MAKE_RGB( 0x00, 0xaa, 0x00 ), MAKE_RGB( 0x00, 0xaa, 0xaa ),
r18713r18714
687685   }
688686};
689687
690static const ide_config ide_intf =
691{
692   ide_interrupt,
693   NULL,
694   0
695};
696
697688static MACHINE_CONFIG_START( gamecstl, gamecstl_state )
698689
699690   /* basic machine hardware */
r18713r18714
716707
717708   MCFG_PIC8259_ADD( "pic8259_2", gamecstl_pic8259_2_config )
718709
719   MCFG_IDE_CONTROLLER_ADD("ide", ide_intf, ide_devices, "hdd", NULL, true)
710   MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
711   MCFG_IDE_CONTROLLER_IRQ_HANDLER(DEVWRITELINE(DEVICE_SELF_OWNER, gamecstl_state, ide_interrupt))
720712
721713   MCFG_MC146818_ADD( "rtc", MC146818_STANDARD )
722714
r18713r18714
745737   pic8259_ir1_w(drvstate->m_pic8259_1, state);
746738}
747739
748static void ide_interrupt(device_t *device, int state)
740WRITE_LINE_MEMBER(gamecstl_state::ide_interrupt)
749741{
750   gamecstl_state *drvstate = device->machine().driver_data<gamecstl_state>();
751   pic8259_ir6_w(drvstate->m_pic8259_2, state);
742   pic8259_ir6_w(m_pic8259_2, state);
752743}
753744
754745static int gamecstl_get_out2(running_machine &machine)
trunk/src/mame/drivers/voyager.c
r18713r18714
6565   DECLARE_READ32_MEMBER(fdc_r);
6666   DECLARE_WRITE32_MEMBER(fdc_w);
6767   DECLARE_WRITE_LINE_MEMBER(voyager_pic8259_1_set_int_line);
68   DECLARE_WRITE_LINE_MEMBER(ide_interrupt);
6869   DECLARE_READ8_MEMBER(get_slave_ack);
6970   DECLARE_DRIVER_INIT(voyager);
7071   virtual void machine_start();
r18713r18714
7273};
7374
7475
75static void ide_interrupt(device_t *device, int state);
76
77
7876READ8_MEMBER(voyager_state::at_dma8237_2_r)
7977{
8078   device_t *device = machine().device("dma8237_2");
r18713r18714
742740   pic8259_ir1_w(drvstate->m_pic8259_1, state);
743741}
744742
745static void ide_interrupt(device_t *device, int state)
743WRITE_LINE_MEMBER(voyager_state::ide_interrupt)
746744{
747   voyager_state *drvstate = device->machine().driver_data<voyager_state>();
748   pic8259_ir6_w(drvstate->m_pic8259_2, state);
745   pic8259_ir6_w(m_pic8259_2, state);
749746}
750747
751748static int voyager_get_out2(running_machine &machine)
r18713r18714
765762   pic8259_ir1_w(drvstate->m_pic8259_1, state);
766763}
767764
768static const ide_config ide_intf =
769{
770   ide_interrupt,
771   NULL,
772   0
773};
774
775765static MACHINE_CONFIG_START( voyager, voyager_state )
776766   MCFG_CPU_ADD("maincpu", PENTIUM, 133000000) // actually AMD Duron CPU of unknown clock
777767   MCFG_CPU_PROGRAM_MAP(voyager_map)
r18713r18714
783773   MCFG_I8237_ADD( "dma8237_2", XTAL_14_31818MHz/3, dma8237_2_config )
784774   MCFG_PIC8259_ADD( "pic8259_1", voyager_pic8259_1_config )
785775   MCFG_PIC8259_ADD( "pic8259_2", voyager_pic8259_2_config )
786   MCFG_IDE_CONTROLLER_ADD("ide", ide_intf, ide_devices, "hdd", NULL, true)
776   MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
777   MCFG_IDE_CONTROLLER_IRQ_HANDLER(DEVWRITELINE(DEVICE_SELF_OWNER, voyager_state, ide_interrupt))
787778
788779   MCFG_MC146818_ADD( "rtc", MC146818_STANDARD )
789780   MCFG_PCI_BUS_LEGACY_ADD("pcibus", 0)
trunk/src/mame/drivers/kinst.c
r18713r18714
158158   DECLARE_WRITE32_MEMBER(kinst_ide_w);
159159   DECLARE_READ32_MEMBER(kinst_ide_extra_r);
160160   DECLARE_WRITE32_MEMBER(kinst_ide_extra_w);
161   DECLARE_WRITE_LINE_MEMBER(ide_interrupt);
161162   DECLARE_DRIVER_INIT(kinst);
162163   DECLARE_DRIVER_INIT(kinst2);
163164   virtual void machine_start();
r18713r18714
201202
202203void kinst_state::machine_reset()
203204{
204   device_t *ide = machine().device("ide");
205   UINT8 *features = ide_get_features(ide,0);
205   ide_controller_device *ide = (ide_controller_device *) machine().device("ide");
206   UINT8 *features = ide->ide_get_features(0);
206207
207208   if (strncmp(machine().system().name, "kinst2", 6) != 0)
208209   {
r18713r18714
290291}
291292
292293
293static void ide_interrupt(device_t *device, int state)
294WRITE_LINE_MEMBER(kinst_state::ide_interrupt)
294295{
295   device->machine().device("maincpu")->execute().set_input_line(1, state);
296   machine().device("maincpu")->execute().set_input_line(1, state);
296297}
297298
298299
r18713r18714
664665   16384            /* data cache size */
665666};
666667
667static const ide_config ide_intf =
668{
669   ide_interrupt,
670   NULL,
671   0
672};
673
674668static MACHINE_CONFIG_START( kinst, kinst_state )
675669
676670   /* basic machine hardware */
r18713r18714
680674   MCFG_CPU_VBLANK_INT_DRIVER("screen", kinst_state,  irq0_start)
681675
682676
683   MCFG_IDE_CONTROLLER_ADD("ide", ide_intf, ide_devices, "hdd", NULL, true)
677   MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
678   MCFG_IDE_CONTROLLER_IRQ_HANDLER(DEVWRITELINE(DEVICE_SELF_OWNER, kinst_state, ide_interrupt))
684679
685680   /* video hardware */
686681   MCFG_VIDEO_ATTRIBUTES(VIDEO_UPDATE_BEFORE_VBLANK)
trunk/src/mame/drivers/chihiro.c
r18713r18714
418418   DECLARE_READ8_MEMBER(get_slave_ack);
419419   DECLARE_WRITE_LINE_MEMBER(chihiro_pit8254_out0_changed);
420420   DECLARE_WRITE_LINE_MEMBER(chihiro_pit8254_out2_changed);
421   DECLARE_WRITE_LINE_MEMBER(ide_interrupt);
421422};
422423
423424/*
r18713r18714
14711472   ide_controller_w(chihiro_devs.ide, offset+0x01f0, size, data);
14721473}
14731474
1474static void ide_interrupt(device_t *device, int state)
1475WRITE_LINE_MEMBER(chihiro_state::ide_interrupt)
14751476{
1476   chihiro_state *chst=device->machine().driver_data<chihiro_state>();
1477   pic8259_ir6_w(chst->chihiro_devs.pic8259_2, state); // IRQ 14
1477   pic8259_ir6_w(chihiro_devs.pic8259_2, state); // IRQ 14
14781478}
14791479
14801480// ======================> ide_baseboard_device
r18713r18714
18231823   SLOT_INTERFACE("bb", IDE_BASEBOARD)
18241824SLOT_INTERFACE_END
18251825
1826static const ide_config ide_intf =
1827{
1828   ide_interrupt,
1829   "maincpu",
1830   AS_PROGRAM
1831};
1832
18331826static MACHINE_CONFIG_START( chihiro_base, chihiro_state )
18341827
18351828   /* basic machine hardware */
r18713r18714
18511844   MCFG_PIC8259_ADD( "pic8259_1", chihiro_pic8259_1_config )
18521845   MCFG_PIC8259_ADD( "pic8259_2", chihiro_pic8259_2_config )
18531846   MCFG_PIT8254_ADD( "pit8254", chihiro_pit8254_config )
1854   MCFG_IDE_CONTROLLER_ADD( "ide", ide_intf , ide_baseboard, NULL, "bb", true)
1847   MCFG_IDE_CONTROLLER_ADD( "ide", ide_baseboard, NULL, "bb", true)
1848   MCFG_IDE_CONTROLLER_IRQ_HANDLER(DEVWRITELINE(DEVICE_SELF_OWNER, chihiro_state, ide_interrupt))
1849   MCFG_IDE_CONTROLLER_BUS_MASTER("maincpu", AS_PROGRAM)
18551850
18561851   /* video hardware */
18571852   MCFG_SCREEN_ADD("screen", RASTER)
trunk/src/mame/drivers/queen.c
r18713r18714
107107   DECLARE_WRITE_LINE_MEMBER(pc_dack2_w);
108108   DECLARE_WRITE_LINE_MEMBER(pc_dack3_w);
109109   DECLARE_WRITE_LINE_MEMBER(queen_pic8259_1_set_int_line);
110   DECLARE_WRITE_LINE_MEMBER(ide_interrupt);
110111   virtual void machine_start();
111112   virtual void machine_reset();
112113};
r18713r18714
632633   return pic8259_acknowledge( state->m_pic8259_1);
633634}
634635
635static void ide_interrupt(device_t *device, int state)
636WRITE_LINE_MEMBER( queen_state::ide_interrupt )
636637{
637   queen_state *drvstate = device->machine().driver_data<queen_state>();
638   pic8259_ir6_w(drvstate->m_pic8259_2, state);
638   pic8259_ir6_w(m_pic8259_2, state);
639639}
640640
641641void queen_state::machine_start()
r18713r18714
670670
671671
672672
673static const ide_config ide_intf =
674{
675   ide_interrupt,
676   NULL,
677   0
678};
679
680673static MACHINE_CONFIG_START( queen, queen_state )
681674   MCFG_CPU_ADD("maincpu", PENTIUM, 533000000/16) // Celeron or Pentium 3, 533 Mhz
682675   MCFG_CPU_PROGRAM_MAP(queen_map)
r18713r18714
695688   MCFG_PCI_BUS_LEGACY_DEVICE(0, NULL, intel82439tx_pci_r, intel82439tx_pci_w)
696689   MCFG_PCI_BUS_LEGACY_DEVICE(7, NULL, intel82371ab_pci_r, intel82371ab_pci_w)
697690
698   MCFG_IDE_CONTROLLER_ADD("ide", ide_intf, ide_devices, "hdd", NULL, true)
691   MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
692   MCFG_IDE_CONTROLLER_IRQ_HANDLER(DEVWRITELINE(DEVICE_SELF_OWNER, queen_state, ide_interrupt))
699693
700694   /* video hardware */
701695   MCFG_FRAGMENT_ADD( pcvideo_vga )
trunk/src/mame/drivers/atlantis.c
r18713r18714
9595
9696/*************************************
9797 *
98 *  Interrupt handling
99 *
100 *************************************/
101
102static void ide_interrupt(device_t *device, int state)
103{
104}
105
106/*************************************
107 *
10898 *  Main CPU memory handlers
10999 *
110100 *************************************/
r18713r18714
142132   16384            /* data cache size */
143133};
144134
145static const ide_config ide_intf =
146{
147   ide_interrupt,
148   NULL,
149   0
150};
151
152135static MACHINE_CONFIG_START( mwskins, atlantis_state )
153136
154137   /* basic machine hardware */
r18713r18714
157140   MCFG_CPU_PROGRAM_MAP(main_map)
158141
159142
160   MCFG_IDE_CONTROLLER_ADD("ide", ide_intf, ide_devices, "hdd", NULL, true)
143   MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
161144
162145   /* video hardware */
163146   MCFG_VIDEO_ATTRIBUTES(VIDEO_UPDATE_BEFORE_VBLANK)
trunk/src/mame/drivers/taitotz.c
r18713r18714
530530   DECLARE_WRITE8_MEMBER(tlcs_ide0_w);
531531   DECLARE_READ8_MEMBER(tlcs_ide1_r);
532532   DECLARE_WRITE8_MEMBER(tlcs_ide1_w);
533   DECLARE_WRITE_LINE_MEMBER(ide_interrupt);
533534};
534535
535536
r18713r18714
24242425
24252426static void set_ide_drive_serial_number(device_t *device, int drive, const char *serial)
24262427{
2427   UINT8 *ide_features = ide_get_features(device, drive);
2428   ide_controller_device *ide = (ide_controller_device *) device;
2429   UINT8 *ide_features = ide->ide_get_features(drive);
24282430
24292431   for (int i=0; i < 20; i++)
24302432   {
r18713r18714
24592461   machine().device("iocpu")->execute().set_input_line(TLCS900_INT3, ASSERT_LINE);
24602462}
24612463
2462static void ide_interrupt(device_t *device, int state)
2464WRITE_LINE_MEMBER(taitotz_state::ide_interrupt)
24632465{
2464   device->machine().device("iocpu")->execute().set_input_line(TLCS900_INT2, state);
2466   machine().device("iocpu")->execute().set_input_line(TLCS900_INT2, state);
24652467}
24662468
24672469static const powerpc_config ppc603e_config =
r18713r18714
24792481   DEVCB_DRIVER_MEMBER(taitotz_state, tlcs900_port_write),
24802482};
24812483
2482static const ide_config ide_intf =
2483{
2484   ide_interrupt,
2485   NULL,
2486   0
2487};
2488
24892484static MACHINE_CONFIG_START( taitotz, taitotz_state )
24902485   /* IBM EMPPC603eBG-100 */
24912486   MCFG_CPU_ADD("maincpu", PPC603E, 100000000)
r18713r18714
25022497
25032498   MCFG_QUANTUM_TIME(attotime::from_hz(120))
25042499
2500   MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
2501   MCFG_IDE_CONTROLLER_IRQ_HANDLER(DEVWRITELINE(DEVICE_SELF_OWNER, taitotz_state, ide_interrupt))
25052502
2506   MCFG_IDE_CONTROLLER_ADD("ide", ide_intf, ide_devices, "hdd", NULL, true)
25072503   MCFG_NVRAM_ADD_0FILL("nvram")
25082504
25092505   MCFG_SCREEN_ADD("screen", RASTER)
trunk/src/mame/drivers/zn.c
r18713r18714
14711471      *2                  - Unpopulated DIP28 socket
14721472*/
14731473
1474static void atpsx_interrupt(device_t *device, int state)
1475{
1476   if (state)
1477   {
1478      psxirq_device *psxirq = (psxirq_device *) device->machine().device("maincpu:irq");
1479      psxirq->intin10(1);
1480   }
1481}
1482
14831474static void atpsx_dma_read( zn_state *state, UINT32 n_address, INT32 n_size )
14841475{
14851476   UINT32 *p_n_psxram = state->m_p_n_psxram;
r18713r18714
15311522   machine().device("ide")->reset();
15321523}
15331524
1534static const ide_config ide_intf =
1535{
1536   atpsx_interrupt,
1537   NULL,
1538   0
1539};
1540
15411525static MACHINE_CONFIG_DERIVED( coh1000w, zn1_2mb_vram )
15421526   MCFG_MACHINE_RESET_OVERRIDE(zn_state, coh1000w )
15431527
1544   MCFG_IDE_CONTROLLER_ADD("ide", ide_intf, ide_devices, "hdd", NULL, true)
1528   MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
1529   MCFG_IDE_CONTROLLER_IRQ_HANDLER(DEVWRITELINE("maincpu:irq", psxirq_device, intin10))
15451530   MCFG_PSX_DMA_CHANNEL_READ( "maincpu", 5, psx_dma_read_delegate( FUNC( atpsx_dma_read ), (zn_state *) owner ) )
15461531   MCFG_PSX_DMA_CHANNEL_WRITE( "maincpu", 5, psx_dma_write_delegate( FUNC( atpsx_dma_write ), (zn_state *) owner ) )
15471532MACHINE_CONFIG_END
r18713r18714
20432028      *         - Unpopulated DIP42 socket
20442029*/
20452030
2046static void jdredd_ide_interrupt(device_t *device, int state)
2047{
2048   if (state)
2049   {
2050      psxirq_device *psxirq = (psxirq_device *) device->machine().device("maincpu:irq");
2051      psxirq->intin10(1);
2052   }
2053}
2054
20552031READ32_MEMBER(zn_state::jdredd_idestat_r)
20562032{
20572033   device_t *device = machine().device("ide");
r18713r18714
22142190   MCFG_MACHINE_RESET_OVERRIDE(zn_state, coh1000a )
22152191MACHINE_CONFIG_END
22162192
2217static const ide_config jdredd_ide_intf =
2218{
2219   jdredd_ide_interrupt,
2220   NULL,
2221   0
2222};
2223
22242193static MACHINE_CONFIG_DERIVED( coh1000a_ide, zn1_2mb_vram )
22252194
22262195   MCFG_DEVICE_MODIFY( "gpu" )
r18713r18714
22282197
22292198   MCFG_MACHINE_RESET_OVERRIDE(zn_state, coh1000a )
22302199
2231   MCFG_IDE_CONTROLLER_ADD("ide", jdredd_ide_intf, ide_devices, "hdd", NULL, true)
2200   MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
2201   MCFG_IDE_CONTROLLER_IRQ_HANDLER(DEVWRITELINE("maincpu:irq", psxirq_device, intin10))
22322202MACHINE_CONFIG_END
22332203
22342204/*
trunk/src/mame/drivers/jaguar.c
r18713r18714
15641564   &jaguar_state::dsp_cpu_int
15651565};
15661566
1567static const ide_config ide_intf =
1568{
1569   &jaguar_state::external_int,
1570   NULL,
1571   0
1572};
1573
15741567static MACHINE_CONFIG_START( cojagr3k, jaguar_state )
15751568
15761569   /* basic machine hardware */
r18713r18714
15881581
15891582   MCFG_NVRAM_ADD_1FILL("nvram")
15901583
1591   MCFG_IDE_CONTROLLER_ADD("ide", ide_intf, ide_devices, "hdd", NULL, true)
1584   MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
1585   MCFG_IDE_CONTROLLER_IRQ_HANDLER(DEVWRITELINE(DEVICE_SELF_OWNER, jaguar_state, external_int))
15921586
15931587   /* video hardware */
15941588   MCFG_VIDEO_ATTRIBUTES(VIDEO_UPDATE_BEFORE_VBLANK)
trunk/src/mame/drivers/twinkle.c
r18713r18714
271271   DECLARE_WRITE16_MEMBER(shared_68k_w);
272272   DECLARE_READ16_MEMBER(twinkle_ide_r);
273273   DECLARE_WRITE16_MEMBER(twinkle_ide_w);
274   DECLARE_WRITE_LINE_MEMBER(ide_interrupt);
274275   DECLARE_DRIVER_INIT(twinkle);
275276};
276277
r18713r18714
656657
657658/* SPU board */
658659
659static void ide_interrupt(device_t *device, int state_)
660WRITE_LINE_MEMBER(twinkle_state::ide_interrupt)
660661{
661   twinkle_state *state = device->machine().driver_data<twinkle_state>();
662
663   if ((state_) && (state->m_spu_ctrl & 0x0400))
662   if ((state) && (m_spu_ctrl & 0x0400))
664663   {
665      device->machine().device("audiocpu")->execute().set_input_line(M68K_IRQ_6, ASSERT_LINE);
664      machine().device("audiocpu")->execute().set_input_line(M68K_IRQ_6, ASSERT_LINE);
666665   }
667666}
668667
r18713r18714
870869   DEVCB_NULL
871870};
872871
873static const ide_config ide_intf =
874{
875   ide_interrupt,
876   NULL,
877   0
878};
879
880872static MACHINE_CONFIG_START( twinkle, twinkle_state )
881873   /* basic machine hardware */
882874   MCFG_CPU_ADD( "maincpu", CXD8530CQ, XTAL_67_7376MHz )
r18713r18714
897889   MCFG_AM53CF96_ADD("scsi:am53cf96")
898890   MCFG_AM53CF96_IRQ_HANDLER(DEVWRITELINE("^maincpu:irq", psxirq_device, intin10))
899891
900   MCFG_IDE_CONTROLLER_ADD("ide", ide_intf, ide_devices, "hdd", NULL, true)
892   MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
893   MCFG_IDE_CONTROLLER_IRQ_HANDLER(DEVWRITELINE(DEVICE_SELF_OWNER, twinkle_state, ide_interrupt))
894
901895   MCFG_RTC65271_ADD("rtc", twinkle_rtc)
902896
903897   /* video hardware */
trunk/src/mame/drivers/cobra.c
r18713r18714
652652   DECLARE_READ64_MEMBER(gfx_fifo_r);
653653   DECLARE_WRITE64_MEMBER(gfx_buf_w);
654654
655   DECLARE_WRITE_LINE_MEMBER(ide_interrupt);
656
655657   cobra_renderer *m_renderer;
656658
657659   cobra_fifo *m_gfxfifo_in;
r18713r18714
31733175};
31743176
31753177
3176static void ide_interrupt(device_t *device, int state)
3178WRITE_LINE_MEMBER(cobra_state::ide_interrupt)
31773179{
3178   cobra_state *cobra = device->machine().driver_data<cobra_state>();
3179
31803180   if (state == CLEAR_LINE)
31813181   {
3182      cobra->m_sub_interrupt |= 0x80;
3182      m_sub_interrupt |= 0x80;
31833183   }
31843184   else
31853185   {
3186      cobra->m_sub_interrupt &= ~0x80;
3186      m_sub_interrupt &= ~0x80;
31873187   }
31883188}
31893189
r18713r18714
32003200
32013201void cobra_state::machine_reset()
32023202{
3203
32043203   m_sub_interrupt = 0xff;
32053204
3206   UINT8 *ide_features = ide_get_features(machine().device("ide"), 0);
3205   ide_controller_device *ide = (ide_controller_device *) machine().device("ide");
3206   UINT8 *ide_features = ide->ide_get_features(0);
32073207
32083208   // Cobra expects these settings or the BIOS fails
32093209   ide_features[51*2+0] = 0;         /* 51: PIO data transfer cycle timing mode */
r18713r18714
32233223   dmadac_set_frequency(&m_dmadac[1], 1, 44100);
32243224}
32253225
3226static const ide_config ide_intf =
3227{
3228   ide_interrupt,
3229   NULL,
3230   0
3231};
3232
32333226static MACHINE_CONFIG_START( cobra, cobra_state )
32343227
32353228   /* basic machine hardware */
r18713r18714
32513244   MCFG_PCI_BUS_LEGACY_ADD("pcibus", 0)
32523245   MCFG_PCI_BUS_LEGACY_DEVICE(0, NULL, mpc106_pci_r, mpc106_pci_w)
32533246
3254   MCFG_IDE_CONTROLLER_ADD("ide", ide_intf, ide_devices, "hdd", NULL, true)
3247   MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
3248   MCFG_IDE_CONTROLLER_IRQ_HANDLER(DEVWRITELINE(DEVICE_SELF_OWNER, cobra_state, ide_interrupt))
32553249
32563250   /* video hardware */
32573251
trunk/src/mame/drivers/vegas.c
r18713r18714
488488   int m_count;
489489   int m_dynamic_count;
490490   dynamic_address m_dynamic[MAX_DYNAMIC_ADDRESSES];
491   DECLARE_WRITE_LINE_MEMBER(ide_interrupt);
491492   DECLARE_DRIVER_INIT(gauntleg);
492493   DECLARE_DRIVER_INIT(cartfury);
493494   DECLARE_DRIVER_INIT(tenthdeg);
r18713r18714
514515 *************************************/
515516
516517
517static void ide_interrupt(device_t *device, int state);
518518static void remap_dynamic_addresses(running_machine &machine);
519519
520520
r18713r18714
747747
748748      case 0x14:      /* interrupt pending */
749749         if (data & 4)
750            ide_interrupt(space.machine().device("ide"), 0);
750            state->ide_interrupt(0);
751751         break;
752752   }
753753   if (LOG_PCI)
r18713r18714
12311231 *
12321232 *************************************/
12331233
1234static void ide_interrupt(device_t *device, int state)
1234WRITE_LINE_MEMBER(vegas_state::ide_interrupt)
12351235{
1236   vegas_state *drvstate = device->machine().driver_data<vegas_state>();
1237   drvstate->m_ide_irq_state = state;
1236   m_ide_irq_state = state;
12381237   if (state)
1239      drvstate->m_nile_irq_state |= 0x800;
1238      m_nile_irq_state |= 0x800;
12401239   else
1241      drvstate->m_nile_irq_state &= ~0x800;
1242   update_nile_irqs(device->machine());
1240      m_nile_irq_state &= ~0x800;
1241   update_nile_irqs(machine());
12431242}
12441243
12451244
r18713r18714
22212220   SYSTEM_CLOCK   /* system clock rate */
22222221};
22232222
2224static const ide_config ide_intf =
2225{
2226   ide_interrupt,
2227   "maincpu",
2228   AS_PROGRAM
2229};
2230
22312223static const smc91c9x_config ethernet_intf =
22322224{
22332225   ethernet_interrupt
r18713r18714
22532245
22542246   MCFG_M48T37_ADD("timekeeper")
22552247
2256   MCFG_IDE_CONTROLLER_ADD("ide", ide_intf, ide_devices, "hdd", NULL, true)
2248   MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
2249   MCFG_IDE_CONTROLLER_IRQ_HANDLER(DEVWRITELINE(DEVICE_SELF_OWNER, vegas_state, ide_interrupt))
2250   MCFG_IDE_CONTROLLER_BUS_MASTER("maincpu", AS_PROGRAM)
22572251
22582252   MCFG_SMC91C94_ADD("ethernet", ethernet_intf)
22592253
trunk/src/mame/drivers/qdrmfgp.c
r18713r18714
278278         m_maincpu->set_input_line(3, HOLD_LINE);
279279}
280280
281static void ide_interrupt(device_t *device, int state)
281WRITE_LINE_MEMBER(qdrmfgp_state::ide_interrupt)
282282{
283   qdrmfgp_state *drvstate = device->machine().driver_data<qdrmfgp_state>();
284   if (drvstate->m_control & 0x0008)
283   if (m_control & 0x0008)
285284   {
286285      if (state != CLEAR_LINE)
287         device->machine().device("maincpu")->execute().set_input_line(4, HOLD_LINE);
286         machine().device("maincpu")->execute().set_input_line(4, HOLD_LINE);
288287      else
289         device->machine().device("maincpu")->execute().set_input_line(4, CLEAR_LINE);
288         machine().device("maincpu")->execute().set_input_line(4, CLEAR_LINE);
290289   }
291290}
292291
r18713r18714
305304      device.execute().set_input_line(4, HOLD_LINE);
306305}
307306
308static void gp2_ide_interrupt(device_t *device, int state)
307WRITE_LINE_MEMBER(qdrmfgp_state::gp2_ide_interrupt)
309308{
310   qdrmfgp_state *drvstate = device->machine().driver_data<qdrmfgp_state>();
311   if (drvstate->m_control & 0x0010)
309   if (m_control & 0x0010)
312310   {
313311      if (state != CLEAR_LINE)
314312      {
315         if (drvstate->m_gp2_irq_control)
316            drvstate->m_gp2_irq_control = 0;
313         if (m_gp2_irq_control)
314            m_gp2_irq_control = 0;
317315         else
318            device->machine().device("maincpu")->execute().set_input_line(5, HOLD_LINE);
316            machine().device("maincpu")->execute().set_input_line(5, HOLD_LINE);
319317      }
320318      else
321319      {
322         device->machine().device("maincpu")->execute().set_input_line(5, CLEAR_LINE);
320         machine().device("maincpu")->execute().set_input_line(5, CLEAR_LINE);
323321      }
324322   }
325323}
r18713r18714
662660 *  Machine driver
663661 *
664662 *************************************/
665static const ide_config ide_intf =
666{
667   ide_interrupt,
668   NULL,
669   0
670};
671
672663static MACHINE_CONFIG_START( qdrmfgp, qdrmfgp_state )
673664
674665   /* basic machine hardware */
r18713r18714
679670   MCFG_MACHINE_START_OVERRIDE(qdrmfgp_state,qdrmfgp)
680671   MCFG_NVRAM_ADD_1FILL("nvram")
681672
682   MCFG_IDE_CONTROLLER_ADD("ide", ide_intf, ide_devices, "hdd", NULL, true)
673   MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
674   MCFG_IDE_CONTROLLER_IRQ_HANDLER(DEVWRITELINE(DEVICE_SELF_OWNER, qdrmfgp_state, ide_interrupt))
683675
684676   /* video hardware */
685677   MCFG_SCREEN_ADD("screen", RASTER)
r18713r18714
704696   MCFG_SOUND_ROUTE(1, "rspeaker", 1.0)
705697MACHINE_CONFIG_END
706698
707static const ide_config qdrmfgp2_ide_intf =
708{
709   gp2_ide_interrupt,
710   NULL,
711   0
712};
713699static MACHINE_CONFIG_START( qdrmfgp2, qdrmfgp_state )
714700
715701   /* basic machine hardware */
r18713r18714
720706   MCFG_MACHINE_START_OVERRIDE(qdrmfgp_state,qdrmfgp2)
721707   MCFG_NVRAM_ADD_1FILL("nvram")
722708
723   MCFG_IDE_CONTROLLER_ADD("ide", qdrmfgp2_ide_intf, ide_devices, "hdd", NULL, true)
709   MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
710   MCFG_IDE_CONTROLLER_IRQ_HANDLER(DEVWRITELINE(DEVICE_SELF_OWNER, qdrmfgp_state, gp2_ide_interrupt))
724711
725712   /* video hardware */
726713   MCFG_SCREEN_ADD("screen", RASTER)
trunk/src/mame/drivers/djmain.c
r18713r18714
411411}
412412
413413
414static void ide_interrupt(device_t *device, int state)
414WRITE_LINE_MEMBER( djmain_state::ide_interrupt )
415415{
416416   if (state != CLEAR_LINE)
417417   {
418418      //logerror("IDE interrupt asserted\n");
419      device->machine().device("maincpu")->execute().set_input_line(M68K_IRQ_1, HOLD_LINE);
419      device().machine().device("maincpu")->execute().set_input_line(M68K_IRQ_1, HOLD_LINE);
420420   }
421421   else
422422   {
423423      //logerror("IDE interrupt cleared\n");
424      device->machine().device("maincpu")->execute().set_input_line(M68K_IRQ_1, CLEAR_LINE);
424      device().machine().device("maincpu")->execute().set_input_line(M68K_IRQ_1, CLEAR_LINE);
425425   }
426426}
427427
r18713r18714
13971397
13981398void djmain_state::machine_start()
13991399{
1400   device_t *ide = machine().device("ide");
1400   ide_controller_device *ide = (ide_controller_device *) machine().device("ide");
14011401
14021402   if (ide != NULL && m_ide_master_password != NULL)
1403      ide_set_master_password(ide, m_ide_master_password);
1403      ide->ide_set_master_password(m_ide_master_password);
14041404   if (ide != NULL && m_ide_user_password != NULL)
1405      ide_set_user_password(ide, m_ide_user_password);
1405      ide->ide_set_user_password(m_ide_user_password);
14061406
14071407   state_save_register_global(machine(), m_sndram_bank);
14081408   state_save_register_global(machine(), m_pending_vb_int);
r18713r18714
14451445   djmain_tile_callback, "none"
14461446};
14471447
1448static const ide_config ide_intf =
1449{
1450   ide_interrupt,
1451   NULL,
1452   0
1453};
1454
14551448static MACHINE_CONFIG_START( djmain, djmain_state )
14561449
14571450   /* basic machine hardware */
r18713r18714
14621455   MCFG_CPU_VBLANK_INT_DRIVER("screen", djmain_state,  vb_interrupt)
14631456
14641457
1465   MCFG_IDE_CONTROLLER_ADD("ide", ide_intf, ide_devices, "hdd", NULL, true)
1458   MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
1459   MCFG_IDE_CONTROLLER_IRQ_HANDLER(DEVWRITELINE(DEVICE_SELF_OWNER, djmain_state, ide_interrupt))
14661460
14671461   /* video hardware */
14681462   MCFG_SCREEN_ADD("screen", RASTER)
trunk/src/mame/drivers/seattle.c
r18713r18714
479479   DECLARE_READ32_MEMBER(widget_r);
480480   DECLARE_WRITE32_MEMBER(widget_w);
481481   DECLARE_READ32_MEMBER(seattle_ide_r);
482   DECLARE_WRITE_LINE_MEMBER(ide_interrupt);
482483   DECLARE_DRIVER_INIT(sfrush);
483484   DECLARE_DRIVER_INIT(blitz2k);
484485   DECLARE_DRIVER_INIT(carnevil);
r18713r18714
619620 *
620621 *************************************/
621622
622static void ide_interrupt(device_t *device, int state)
623WRITE_LINE_MEMBER(seattle_state::ide_interrupt)
623624{
624   device->machine().device("maincpu")->execute().set_input_line(IDE_IRQ_NUM, state);
625   machine().device("maincpu")->execute().set_input_line(IDE_IRQ_NUM, state);
625626}
626627
627628
r18713r18714
25232524   SYSTEM_CLOCK   /* system clock rate */
25242525};
25252526
2526static const ide_config ide_intf =
2527{
2528   ide_interrupt,
2529   "maincpu",
2530   AS_PROGRAM
2531};
2532
25332527static const voodoo_config voodoo_intf =
25342528{
25352529   2, //               fbmem;
r18713r18714
25502544
25512545   MCFG_NVRAM_ADD_1FILL("nvram")
25522546
2553   MCFG_IDE_CONTROLLER_ADD("ide", ide_intf, ide_devices, "hdd", NULL, true)
2547   MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
2548   MCFG_IDE_CONTROLLER_IRQ_HANDLER(DEVWRITELINE(DEVICE_SELF_OWNER, seattle_state, ide_interrupt))
2549   MCFG_IDE_CONTROLLER_BUS_MASTER("maincpu", AS_PROGRAM)
25542550
25552551   MCFG_3DFX_VOODOO_1_ADD("voodoo", STD_VOODOO_1_CLOCK, voodoo_intf)
25562552
trunk/src/mame/drivers/savquest.c
r18713r18714
9292   DECLARE_WRITE_LINE_MEMBER(pc_dack2_w);
9393   DECLARE_WRITE_LINE_MEMBER(pc_dack3_w);
9494   DECLARE_WRITE_LINE_MEMBER(savquest_pic8259_1_set_int_line);
95   DECLARE_WRITE_LINE_MEMBER(ide_interrupt);
9596   virtual void machine_start();
9697   virtual void machine_reset();
9798};
r18713r18714
513514   return pic8259_acknowledge( state->m_pic8259_1);
514515}
515516
516static void ide_interrupt(device_t *device, int state)
517WRITE_LINE_MEMBER(savquest_state::ide_interrupt)
517518{
518   savquest_state *drvstate = device->machine().driver_data<savquest_state>();
519   pic8259_ir6_w(drvstate->m_pic8259_2, state);
519   pic8259_ir6_w(m_pic8259_2, state);
520520}
521521
522522void savquest_state::machine_start()
r18713r18714
536536   machine().root_device().membank("bank1")->set_base(machine().root_device().memregion("bios")->base() + 0x20000);
537537}
538538
539static const ide_config ide_intf =
540{
541   ide_interrupt,
542   NULL,
543   0
544};
545
546539static MACHINE_CONFIG_START( savquest, savquest_state )
547540   MCFG_CPU_ADD("maincpu", PENTIUM, 450000000)   // actually Pentium II 450
548541   MCFG_CPU_PROGRAM_MAP(savquest_map)
r18713r18714
561554   MCFG_PCI_BUS_LEGACY_DEVICE(0, NULL, intel82439tx_pci_r, intel82439tx_pci_w)
562555   MCFG_PCI_BUS_LEGACY_DEVICE(7, NULL, intel82371ab_pci_r, intel82371ab_pci_w)
563556
564   MCFG_IDE_CONTROLLER_ADD("ide", ide_intf, ide_devices, "hdd", NULL, true)
557   MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
558   MCFG_IDE_CONTROLLER_IRQ_HANDLER(DEVWRITELINE(DEVICE_SELF_OWNER, savquest_state, ide_interrupt))
565559
566560   /* video hardware */
567561   MCFG_FRAGMENT_ADD( pcvideo_vga )
trunk/src/mame/drivers/midqslvr.c
r18713r18714
9696   DECLARE_WRITE_LINE_MEMBER(pc_dack2_w);
9797   DECLARE_WRITE_LINE_MEMBER(pc_dack3_w);
9898   DECLARE_WRITE_LINE_MEMBER(midqslvr_pic8259_1_set_int_line);
99   DECLARE_WRITE_LINE_MEMBER(ide_interrupt);
99100   virtual void machine_start();
100101   virtual void machine_reset();
101102};
r18713r18714
649650   return pic8259_acknowledge( state->m_pic8259_1);
650651}
651652
652static void ide_interrupt(device_t *device, int state)
653WRITE_LINE_MEMBER(midqslvr_state::ide_interrupt)
653654{
654   midqslvr_state *drvstate = device->machine().driver_data<midqslvr_state>();
655   pic8259_ir6_w(drvstate->m_pic8259_2, state);
655   pic8259_ir6_w(m_pic8259_2, state);
656656}
657657
658658void midqslvr_state::machine_start()
r18713r18714
685685   machine().root_device().membank("video_bank2")->set_base(machine().root_device().memregion("video_bios")->base() + 0x4000);
686686}
687687
688static const ide_config ide_intf =
689{
690   ide_interrupt,
691   NULL,
692   0
693};
694
695688static MACHINE_CONFIG_START( midqslvr, midqslvr_state )
696689   MCFG_CPU_ADD("maincpu", PENTIUM, 333000000)   // actually Celeron 333
697690   MCFG_CPU_PROGRAM_MAP(midqslvr_map)
r18713r18714
710703   MCFG_PCI_BUS_LEGACY_DEVICE( 0, NULL, intel82439tx_pci_r, intel82439tx_pci_w)
711704   MCFG_PCI_BUS_LEGACY_DEVICE(31, NULL, intel82371ab_pci_r, intel82371ab_pci_w)
712705
713   MCFG_IDE_CONTROLLER_ADD("ide", ide_intf, ide_devices, "hdd", NULL, true)
706   MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
707   MCFG_IDE_CONTROLLER_IRQ_HANDLER(DEVWRITELINE(DEVICE_SELF_OWNER, midqslvr_state, ide_interrupt))
714708
715709   /* video hardware */
716710   MCFG_FRAGMENT_ADD( pcvideo_vga )
trunk/src/mame/drivers/calchase.c
r18713r18714
171171   DECLARE_WRITE16_MEMBER(calchase_dac_l_w);
172172   DECLARE_WRITE16_MEMBER(calchase_dac_r_w);
173173   DECLARE_WRITE_LINE_MEMBER(calchase_pic8259_1_set_int_line);
174   DECLARE_WRITE_LINE_MEMBER(ide_interrupt);
174175   DECLARE_READ8_MEMBER(get_slave_ack);
175176   DECLARE_DRIVER_INIT(calchase);
176177   virtual void machine_start();
r18713r18714
178179};
179180
180181
181static void ide_interrupt(device_t *device, int state);
182182
183183
184184READ8_MEMBER(calchase_state::at_dma8237_2_r)
r18713r18714
896896   pic8259_ir1_w(drvstate->m_pic8259_1, state);
897897}
898898
899static void ide_interrupt(device_t *device, int state)
899WRITE_LINE_MEMBER( calchase_state::ide_interrupt )
900900{
901   calchase_state *drvstate = device->machine().driver_data<calchase_state>();
902   pic8259_ir6_w(drvstate->m_pic8259_2, state);
901   pic8259_ir6_w(m_pic8259_2, state);
903902}
904903
905904static int calchase_get_out2(running_machine &machine)
r18713r18714
919918   pic8259_ir1_w(drvstate->m_pic8259_1, state);
920919}
921920
922static const ide_config ide_intf =
923{
924   ide_interrupt,
925   NULL,
926   0
927};
928
929921static MACHINE_CONFIG_START( calchase, calchase_state )
930922   MCFG_CPU_ADD("maincpu", PENTIUM, 133000000) // Cyrix 686MX-PR200 CPU
931923   MCFG_CPU_PROGRAM_MAP(calchase_map)
r18713r18714
937929   MCFG_I8237_ADD( "dma8237_2", XTAL_14_31818MHz/3, dma8237_2_config )
938930   MCFG_PIC8259_ADD( "pic8259_1", calchase_pic8259_1_config )
939931   MCFG_PIC8259_ADD( "pic8259_2", calchase_pic8259_2_config )
940   MCFG_IDE_CONTROLLER_ADD("ide", ide_intf, ide_devices, "hdd", NULL, true)
932   MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
933   MCFG_IDE_CONTROLLER_IRQ_HANDLER(DEVWRITELINE(DEVICE_SELF_OWNER, calchase_state, ide_interrupt))
941934
942935   MCFG_MC146818_ADD( "rtc", MC146818_STANDARD )
943936   MCFG_PCI_BUS_LEGACY_ADD("pcibus", 0)
trunk/src/mame/drivers/xtom3d.c
r18713r18714
113113   DECLARE_WRITE_LINE_MEMBER(pc_dack2_w);
114114   DECLARE_WRITE_LINE_MEMBER(pc_dack3_w);
115115   DECLARE_WRITE_LINE_MEMBER(xtom3d_pic8259_1_set_int_line);
116   DECLARE_WRITE_LINE_MEMBER(ide_interrupt);
116117   virtual void machine_start();
117118   virtual void machine_reset();
118119};
r18713r18714
641642   return pic8259_acknowledge( state->m_pic8259_1);
642643}
643644
644static void ide_interrupt(device_t *device, int state)
645WRITE_LINE_MEMBER(xtom3d_state::ide_interrupt)
645646{
646   xtom3d_state *drvstate = device->machine().driver_data<xtom3d_state>();
647   pic8259_ir6_w(drvstate->m_pic8259_2, state);
647   pic8259_ir6_w(m_pic8259_2, state);
648648}
649649
650650void xtom3d_state::machine_start()
r18713r18714
677677   machine().root_device().membank("video_bank2")->set_base(machine().root_device().memregion("video_bios")->base() + 0x4000);
678678}
679679
680static const ide_config ide_intf =
681{
682   ide_interrupt,
683   NULL,
684   0
685};
686
687680static MACHINE_CONFIG_START( xtom3d, xtom3d_state )
688681   MCFG_CPU_ADD("maincpu", PENTIUM, 450000000/16)   // actually Pentium II 450
689682   MCFG_CPU_PROGRAM_MAP(xtom3d_map)
r18713r18714
702695   MCFG_PCI_BUS_LEGACY_DEVICE(0, NULL, intel82439tx_pci_r, intel82439tx_pci_w)
703696   MCFG_PCI_BUS_LEGACY_DEVICE(7, NULL, intel82371ab_pci_r, intel82371ab_pci_w)
704697
705   MCFG_IDE_CONTROLLER_ADD("ide", ide_intf, ide_devices, "hdd", NULL, true)
698   MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
699   MCFG_IDE_CONTROLLER_IRQ_HANDLER(DEVWRITELINE(DEVICE_SELF_OWNER, xtom3d_state, ide_interrupt))
706700
707701   /* video hardware */
708702   MCFG_FRAGMENT_ADD( pcvideo_vga )
trunk/src/mame/drivers/taitogn.c
r18713r18714
405405         // Check for card reset
406406         if (!(data & 0x40))
407407         {
408            machine.device(":card")->reset();
408            ide_controller_device *card = (ide_controller_device *) machine.device(":card");
409
410            card->reset();
409411            state->m_locked = 0x1ff;
410            ide_set_gnet_readlock (machine.device(":card"), 1);
412            card->ide_set_gnet_readlock(1);
411413         }
412414      break;
413415
r18713r18714
490492         m_locked &= ~(1 << pos);
491493      else
492494         m_locked |= 1 << pos;
493      if (!m_locked) {
494         ide_set_gnet_readlock (machine().device(":card"), 0);
495      if (!m_locked)
496      {
497         ide_controller_device *card = (ide_controller_device *) machine().device(":card");
498         card->ide_set_gnet_readlock(0);
495499      }
496500   }
497501}
r18713r18714
889893   m_locked = 0x1ff;
890894   install_handlers(machine(), 0);
891895   m_control = 0;
892   machine().device(":card")->reset();
893   ide_set_gnet_readlock(machine().device(":card"), 1);
894896
897   ide_controller_device *card = (ide_controller_device *) machine().device(":card");
898   card->reset();
899   card->ide_set_gnet_readlock(1);
900
895901   // halt sound CPU since it has no valid program at start
896902   machine().device("mn10200")->execute().set_input_line(INPUT_LINE_RESET,ASSERT_LINE); /* MCU */
897903}
r18713r18714
930936ADDRESS_MAP_END
931937
932938
933static const ide_config ide_intf =
934{
935   NULL,
936   NULL,
937   0
938};
939
940939static MACHINE_CONFIG_START( coh3002t, taitogn_state )
941940   /* basic machine hardware */
942941   MCFG_CPU_ADD( "maincpu", CXD8661R, XTAL_100MHz )
r18713r18714
955954   MCFG_MACHINE_RESET_OVERRIDE(taitogn_state, coh3002t )
956955
957956   MCFG_AT28C16_ADD( "at28c16", 0 )
958   MCFG_IDE_CONTROLLER_ADD( "card", ide_intf, ide_devices, "hdd", NULL, true)
957   MCFG_IDE_CONTROLLER_ADD( "card", ide_devices, "hdd", NULL, true)
959958
960959   MCFG_MB3773_ADD("mb3773")
961960
trunk/src/mame/drivers/midvunit.c
r18713r18714
10371037   MCFG_FRAGMENT_ADD(dcs_audio_2k)
10381038MACHINE_CONFIG_END
10391039
1040static const ide_config ide_intf =
1041{
1042   NULL,
1043   NULL,
1044   0
1045};
1046
10471040static MACHINE_CONFIG_DERIVED( midvplus, midvcommon )
10481041
10491042   /* basic machine hardware */
r18713r18714
10551048   MCFG_DEVICE_REMOVE("nvram")
10561049   MCFG_NVRAM_HANDLER(midway_serial_pic2)
10571050
1058   MCFG_IDE_CONTROLLER_ADD("ide", ide_intf, ide_devices, "hdd", NULL, true)
1051   MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
10591052
10601053   /* sound hardware */
10611054   MCFG_FRAGMENT_ADD(dcs2_audio_2115)
trunk/src/emu/machine/idectrl.c
r18713r18714
4242#define IDE_STATUS_DRIVE_READY            0x40
4343#define IDE_STATUS_BUSY                  0x80
4444
45#define IDE_CONFIG_REGISTERS            0x10
46
4745#define BANK(b, v) (((v) << 4) | (b))
4846
4947#define IDE_BANK0_DATA                  BANK(0, 0)
r18713r18714
9997#define IDE_BUSMASTER_STATUS_IRQ         0x04
10098
10199
102
103/***************************************************************************
104    TYPE DEFINITIONS
105***************************************************************************/
106struct ide_device
100void ide_controller_device::signal_interrupt()
107101{
108   UINT16         cur_cylinder;
109   UINT8         cur_sector;
110   UINT8         cur_head;
111   UINT8         cur_head_reg;
112   UINT32         cur_lba;
113   ide_slot_device *slot;
114};
115
116
117struct ide_state
118{
119   device_t *device;
120
121   UINT8         adapter_control;
122   UINT8         status;
123   UINT8         error;
124   UINT8         command;
125   UINT8         interrupt_pending;
126   UINT8         precomp_offset;
127
128   UINT8         buffer[IDE_DISK_SECTOR_SIZE];
129   UINT16         buffer_offset;
130   UINT16         sector_count;
131
132   UINT16         block_count;
133   UINT16         sectors_until_int;
134   UINT8         verify_only;
135
136   UINT8         dma_active;
137   address_space *dma_space;
138   UINT8         dma_address_xor;
139   UINT8         dma_last_buffer;
140   offs_t         dma_address;
141   offs_t         dma_descriptor;
142   UINT32         dma_bytes_left;
143
144   UINT8         bus_master_command;
145   UINT8         bus_master_status;
146   UINT32         bus_master_descriptor;
147
148   UINT8         config_unknown;
149   UINT8         config_register[IDE_CONFIG_REGISTERS];
150   UINT8         config_register_num;
151
152   emu_timer *      last_status_timer;
153   emu_timer *      reset_timer;
154
155   UINT8         master_password_enable;
156   UINT8         user_password_enable;
157   const UINT8 *   master_password;
158   const UINT8 *   user_password;
159
160   UINT8         gnetreadlock;
161
162   UINT8         cur_drive;
163   ide_device      drive[2];
164};
165
166
167
168/***************************************************************************
169    FUNCTION PROTOTYPES
170***************************************************************************/
171
172static TIMER_CALLBACK( reset_callback );
173
174static void continue_read(ide_state *ide);
175static void read_sector_done(ide_state *ide);
176static TIMER_CALLBACK( read_sector_done_callback );
177static void read_first_sector(ide_state *ide);
178static void read_next_sector(ide_state *ide);
179
180static UINT32 ide_controller_read(device_t *device, int bank, offs_t offset, int size);
181static void ide_controller_write(device_t *device, int bank, offs_t offset, int size, UINT32 data);
182
183
184
185/***************************************************************************
186    INLINE FUNCTIONS
187***************************************************************************/
188
189/*-------------------------------------------------
190    get_safe_token - makes sure that the passed
191    in device is, in fact, an IDE controller
192-------------------------------------------------*/
193
194INLINE ide_state *get_safe_token(device_t *device)
195{
196   assert(device != NULL);
197   assert(device->type() == IDE_CONTROLLER);
198
199   return (ide_state *)downcast<ide_controller_device *>(device)->token();
200}
201
202
203INLINE void signal_interrupt(ide_state *ide)
204{
205   const ide_config *config = (const ide_config *)ide->device->static_config();
206
207102   LOG(("IDE interrupt assert\n"));
208103
209104   /* signal an interrupt */
210   if (config->interrupt != NULL)
211      (*config->interrupt)(ide->device, ASSERT_LINE);
212   ide->interrupt_pending = 1;
213   ide->bus_master_status |= IDE_BUSMASTER_STATUS_IRQ;
105   m_irq_handler(ASSERT_LINE);
106   interrupt_pending = 1;
107   bus_master_status |= IDE_BUSMASTER_STATUS_IRQ;
214108}
215109
216110
217INLINE void clear_interrupt(ide_state *ide)
111void ide_controller_device::clear_interrupt()
218112{
219   const ide_config *config = (const ide_config *)ide->device->static_config();
220
221113   LOG(("IDE interrupt clear\n"));
222114
223115   /* clear an interrupt */
224   if (config->interrupt != NULL)
225      (*config->interrupt)(ide->device, CLEAR_LINE);
226   ide->interrupt_pending = 0;
116   m_irq_handler(CLEAR_LINE);
117   interrupt_pending = 0;
227118}
228119
229120
r18713r18714
234125
235126static TIMER_CALLBACK( delayed_interrupt )
236127{
237   ide_state *ide = (ide_state *)ptr;
128   ide_controller_device *ide = (ide_controller_device *)ptr;
238129   ide->status &= ~IDE_STATUS_BUSY;
239   signal_interrupt(ide);
130   ide->signal_interrupt();
240131}
241132
242133
243134static TIMER_CALLBACK( delayed_interrupt_buffer_ready )
244135{
245   ide_state *ide = (ide_state *)ptr;
136   ide_controller_device *ide = (ide_controller_device *)ptr;
246137   ide->status &= ~IDE_STATUS_BUSY;
247138   ide->status |= IDE_STATUS_BUFFER_READY;
248   signal_interrupt(ide);
139   ide->signal_interrupt();
249140}
250141
251142
252INLINE void signal_delayed_interrupt(ide_state *ide, attotime time, int buffer_ready)
143void ide_controller_device::signal_delayed_interrupt(attotime time, int buffer_ready)
253144{
254145   /* clear buffer ready and set the busy flag */
255   ide->status &= ~IDE_STATUS_BUFFER_READY;
256   ide->status |= IDE_STATUS_BUSY;
146   status &= ~IDE_STATUS_BUFFER_READY;
147   status |= IDE_STATUS_BUSY;
257148
258149   /* set a timer */
259150   if (buffer_ready)
260      ide->device->machine().scheduler().timer_set(time, FUNC(delayed_interrupt_buffer_ready), 0, ide);
151      machine().scheduler().timer_set(time, FUNC(delayed_interrupt_buffer_ready), 0, this);
261152   else
262      ide->device->machine().scheduler().timer_set(time, FUNC(delayed_interrupt), 0, ide);
153      machine().scheduler().timer_set(time, FUNC(delayed_interrupt), 0, this);
263154}
264155
265156
r18713r18714
268159    INITIALIZATION AND RESET
269160***************************************************************************/
270161
271UINT8 *ide_get_features(device_t *device, int drive)
162UINT8 *ide_controller_device::ide_get_features(int _drive)
272163{
273   ide_state *ide = get_safe_token(device);
274   return ide->drive[drive].slot->get_features();
164   return drive[_drive].slot->get_features();
275165}
276166
277void ide_set_gnet_readlock(device_t *device, const UINT8 onoff)
167void ide_controller_device::ide_set_gnet_readlock(const UINT8 onoff)
278168{
279   ide_state *ide = get_safe_token(device);
280   ide->gnetreadlock = onoff;
169   gnetreadlock = onoff;
281170}
282171
283void ide_set_master_password(device_t *device, const UINT8 *password)
172void ide_controller_device::ide_set_master_password(const UINT8 *password)
284173{
285   ide_state *ide = get_safe_token(device);
286
287   ide->master_password = password;
288   ide->master_password_enable = (ide->master_password != NULL);
174   master_password = password;
175   master_password_enable = (master_password != NULL);
289176}
290177
291178
292void ide_set_user_password(device_t *device, const UINT8 *password)
179void ide_controller_device::ide_set_user_password(const UINT8 *password)
293180{
294   ide_state *ide = get_safe_token(device);
295
296   ide->user_password = password;
297   ide->user_password_enable = (ide->user_password != NULL);
181   user_password = password;
182   user_password_enable = (user_password != NULL);
298183}
299184
300185
r18713r18714
363248 *
364249 *************************************/
365250
366INLINE UINT32 lba_address(ide_state *ide)
251UINT32 ide_controller_device::lba_address()
367252{
368253   /* LBA direct? */
369   if (ide->drive[ide->cur_drive].cur_head_reg & 0x40)
370      return ide->drive[ide->cur_drive].cur_sector + ide->drive[ide->cur_drive].cur_cylinder * 256 + ide->drive[ide->cur_drive].cur_head * 16777216;
254   if (drive[cur_drive].cur_head_reg & 0x40)
255      return drive[cur_drive].cur_sector + drive[cur_drive].cur_cylinder * 256 + drive[cur_drive].cur_head * 16777216;
371256
372257   /* standard CHS */
373258   else
374      return (ide->drive[ide->cur_drive].cur_cylinder * ide->drive[ide->cur_drive].slot->get_heads() + ide->drive[ide->cur_drive].cur_head) * ide->drive[ide->cur_drive].slot->get_sectors() + ide->drive[ide->cur_drive].cur_sector - 1;
259      return (drive[cur_drive].cur_cylinder * drive[cur_drive].slot->get_heads() + drive[cur_drive].cur_head) * drive[cur_drive].slot->get_sectors() + drive[cur_drive].cur_sector - 1;
375260}
376261
377262
r18713r18714
382267 *
383268 *************************************/
384269
385INLINE void next_sector(ide_state *ide)
270void ide_controller_device::next_sector()
386271{
387272   /* LBA direct? */
388   if (ide->drive[ide->cur_drive].cur_head_reg & 0x40)
273   if (drive[cur_drive].cur_head_reg & 0x40)
389274   {
390      ide->drive[ide->cur_drive].cur_sector++;
391      if (ide->drive[ide->cur_drive].cur_sector == 0)
275      drive[cur_drive].cur_sector++;
276      if (drive[cur_drive].cur_sector == 0)
392277      {
393         ide->drive[ide->cur_drive].cur_cylinder++;
394         if (ide->drive[ide->cur_drive].cur_cylinder == 0)
395            ide->drive[ide->cur_drive].cur_head++;
278         drive[cur_drive].cur_cylinder++;
279         if (drive[cur_drive].cur_cylinder == 0)
280            drive[cur_drive].cur_head++;
396281      }
397282   }
398283
r18713r18714
400285   else
401286   {
402287      /* sectors are 1-based */
403      ide->drive[ide->cur_drive].cur_sector++;
404      if (ide->drive[ide->cur_drive].cur_sector > ide->drive[ide->cur_drive].slot->get_sectors())
288      drive[cur_drive].cur_sector++;
289      if (drive[cur_drive].cur_sector > drive[cur_drive].slot->get_sectors())
405290      {
406291         /* heads are 0 based */
407         ide->drive[ide->cur_drive].cur_sector = 1;
408         ide->drive[ide->cur_drive].cur_head++;
409         if (ide->drive[ide->cur_drive].cur_head >= ide->drive[ide->cur_drive].slot->get_heads())
292         drive[cur_drive].cur_sector = 1;
293         drive[cur_drive].cur_head++;
294         if (drive[cur_drive].cur_head >= drive[cur_drive].slot->get_heads())
410295         {
411            ide->drive[ide->cur_drive].cur_head = 0;
412            ide->drive[ide->cur_drive].cur_cylinder++;
296            drive[cur_drive].cur_head = 0;
297            drive[cur_drive].cur_cylinder++;
413298         }
414299      }
415300   }
416301
417   ide->drive[ide->cur_drive].cur_lba = lba_address(ide);
302   drive[cur_drive].cur_lba = lba_address();
418303}
419304
420305
r18713r18714
452337   m_features[ 2*2+0] = 0;                     /*  2: reserved */
453338   m_features[ 2*2+1] = 0;
454339   m_features[ 3*2+0] = m_num_heads & 0xff;      /*  3: logical heads */
455   m_features[ 3*2+1] = 0;/*ide->num_heads >> 8;*/
340   m_features[ 3*2+1] = 0;/*num_heads >> 8;*/
456341   m_features[ 4*2+0] = 0;                     /*  4: vendor specific (obsolete) */
457342   m_features[ 4*2+1] = 0;
458343   m_features[ 5*2+0] = 0;                     /*  5: vendor specific (obsolete) */
459344   m_features[ 5*2+1] = 0;
460345   m_features[ 6*2+0] = m_num_sectors & 0xff;   /*  6: logical sectors per logical track */
461   m_features[ 6*2+1] = 0;/*ide->num_sectors >> 8;*/
346   m_features[ 6*2+1] = 0;/*num_sectors >> 8;*/
462347   m_features[ 7*2+0] = 0;                     /*  7: vendor-specific */
463348   m_features[ 7*2+1] = 0;
464349   m_features[ 8*2+0] = 0;                     /*  8: vendor-specific */
r18713r18714
494379   m_features[54*2+0] = m_num_cylinders & 0xff;   /* 54: number of current logical cylinders */
495380   m_features[54*2+1] = m_num_cylinders >> 8;
496381   m_features[55*2+0] = m_num_heads & 0xff;      /* 55: number of current logical heads */
497   m_features[55*2+1] = 0;/*ide->num_heads >> 8;*/
382   m_features[55*2+1] = 0;/*num_heads >> 8;*/
498383   m_features[56*2+0] = m_num_sectors & 0xff;   /* 56: number of current logical sectors per track */
499   m_features[56*2+1] = 0;/*ide->num_sectors >> 8;*/
384   m_features[56*2+1] = 0;/*num_sectors >> 8;*/
500385   m_features[57*2+0] = sectors_per_track & 0xff;   /* 57-58: number of current logical sectors per track */
501386   m_features[57*2+1] = sectors_per_track >> 8;
502387   m_features[58*2+0] = sectors_per_track >> 16;
r18713r18714
603488
604489static TIMER_CALLBACK( security_error_done )
605490{
606   ide_state *ide = (ide_state *)ptr;
491   ide_controller_device *ide = (ide_controller_device *)ptr;
607492
608493   /* clear error state */
609494   ide->status &= ~IDE_STATUS_ERROR;
610495   ide->status |= IDE_STATUS_DRIVE_READY;
611496}
612497
613static void security_error(ide_state *ide)
498void ide_controller_device::security_error()
614499{
615500   /* set error state */
616   ide->status |= IDE_STATUS_ERROR;
617   ide->status &= ~IDE_STATUS_DRIVE_READY;
501   status |= IDE_STATUS_ERROR;
502   status &= ~IDE_STATUS_DRIVE_READY;
618503
619504   /* just set a timer and mark ourselves error */
620   ide->device->machine().scheduler().timer_set(TIME_SECURITY_ERROR, FUNC(security_error_done), 0, ide);
505   machine().scheduler().timer_set(TIME_SECURITY_ERROR, FUNC(security_error_done), 0, this);
621506}
622507
623508
r18713r18714
628513 *
629514 *************************************/
630515
631static void continue_read(ide_state *ide)
516void ide_controller_device::continue_read()
632517{
633518   /* reset the totals */
634   ide->buffer_offset = 0;
519   buffer_offset = 0;
635520
636521   /* clear the buffer ready and busy flag */
637   ide->status &= ~IDE_STATUS_BUFFER_READY;
638   ide->status &= ~IDE_STATUS_BUSY;
522   status &= ~IDE_STATUS_BUFFER_READY;
523   status &= ~IDE_STATUS_BUSY;
639524
640   if (ide->master_password_enable || ide->user_password_enable)
525   if (master_password_enable || user_password_enable)
641526   {
642      security_error(ide);
527      security_error();
643528
644      ide->sector_count = 0;
645      ide->bus_master_status &= ~IDE_BUSMASTER_STATUS_ACTIVE;
646      ide->dma_active = 0;
529      sector_count = 0;
530      bus_master_status &= ~IDE_BUSMASTER_STATUS_ACTIVE;
531      dma_active = 0;
647532
648533      return;
649534   }
650535
651536   /* if there is more data to read, keep going */
652   if (ide->sector_count > 0)
653      ide->sector_count--;
654   if (ide->sector_count > 0)
655      read_next_sector(ide);
537   if (sector_count > 0)
538      sector_count--;
539   if (sector_count > 0)
540      read_next_sector();
656541   else
657542   {
658      ide->bus_master_status &= ~IDE_BUSMASTER_STATUS_ACTIVE;
659      ide->dma_active = 0;
543      bus_master_status &= ~IDE_BUSMASTER_STATUS_ACTIVE;
544      dma_active = 0;
660545   }
661546}
662547
663548
664static void write_buffer_to_dma(ide_state *ide)
549void ide_controller_device::write_buffer_to_dma()
665550{
666551   int bytesleft = IDE_DISK_SECTOR_SIZE;
667   UINT8 *data = ide->buffer;
552   UINT8 *data = buffer;
668553
669//  LOG(("Writing sector to %08X\n", ide->dma_address));
554//  LOG(("Writing sector to %08X\n", dma_address));
670555
671556   /* loop until we've consumed all bytes */
672557   while (bytesleft--)
673558   {
674559      /* if we're out of space, grab the next descriptor */
675      if (ide->dma_bytes_left == 0)
560      if (dma_bytes_left == 0)
676561      {
677562         /* if we're out of buffer space, that's bad */
678         if (ide->dma_last_buffer)
563         if (dma_last_buffer)
679564         {
680565            LOG(("DMA Out of buffer space!\n"));
681566            return;
682567         }
683568
684569         /* fetch the address */
685         ide->dma_address = ide->dma_space->read_byte(ide->dma_descriptor++ ^ ide->dma_address_xor);
686         ide->dma_address |= ide->dma_space->read_byte(ide->dma_descriptor++ ^ ide->dma_address_xor) << 8;
687         ide->dma_address |= ide->dma_space->read_byte(ide->dma_descriptor++ ^ ide->dma_address_xor) << 16;
688         ide->dma_address |= ide->dma_space->read_byte(ide->dma_descriptor++ ^ ide->dma_address_xor) << 24;
689         ide->dma_address &= 0xfffffffe;
570         dma_address = dma_space->read_byte(dma_descriptor++ ^ dma_address_xor);
571         dma_address |= dma_space->read_byte(dma_descriptor++ ^ dma_address_xor) << 8;
572         dma_address |= dma_space->read_byte(dma_descriptor++ ^ dma_address_xor) << 16;
573         dma_address |= dma_space->read_byte(dma_descriptor++ ^ dma_address_xor) << 24;
574         dma_address &= 0xfffffffe;
690575
691576         /* fetch the length */
692         ide->dma_bytes_left = ide->dma_space->read_byte(ide->dma_descriptor++ ^ ide->dma_address_xor);
693         ide->dma_bytes_left |= ide->dma_space->read_byte(ide->dma_descriptor++ ^ ide->dma_address_xor) << 8;
694         ide->dma_bytes_left |= ide->dma_space->read_byte(ide->dma_descriptor++ ^ ide->dma_address_xor) << 16;
695         ide->dma_bytes_left |= ide->dma_space->read_byte(ide->dma_descriptor++ ^ ide->dma_address_xor) << 24;
696         ide->dma_last_buffer = (ide->dma_bytes_left >> 31) & 1;
697         ide->dma_bytes_left &= 0xfffe;
698         if (ide->dma_bytes_left == 0)
699            ide->dma_bytes_left = 0x10000;
577         dma_bytes_left = dma_space->read_byte(dma_descriptor++ ^ dma_address_xor);
578         dma_bytes_left |= dma_space->read_byte(dma_descriptor++ ^ dma_address_xor) << 8;
579         dma_bytes_left |= dma_space->read_byte(dma_descriptor++ ^ dma_address_xor) << 16;
580         dma_bytes_left |= dma_space->read_byte(dma_descriptor++ ^ dma_address_xor) << 24;
581         dma_last_buffer = (dma_bytes_left >> 31) & 1;
582         dma_bytes_left &= 0xfffe;
583         if (dma_bytes_left == 0)
584            dma_bytes_left = 0x10000;
700585
701//          LOG(("New DMA descriptor: address = %08X  bytes = %04X  last = %d\n", ide->dma_address, ide->dma_bytes_left, ide->dma_last_buffer));
586//          LOG(("New DMA descriptor: address = %08X  bytes = %04X  last = %d\n", dma_address, dma_bytes_left, dma_last_buffer));
702587      }
703588
704589      /* write the next byte */
705      ide->dma_space->write_byte(ide->dma_address++, *data++);
706      ide->dma_bytes_left--;
590      dma_space->write_byte(dma_address++, *data++);
591      dma_bytes_left--;
707592   }
708593}
709594
710595
711static void read_sector_done(ide_state *ide)
596void ide_controller_device::read_sector_done()
712597{
713   int lba = lba_address(ide), count = 0;
598   int lba = lba_address(), count = 0;
714599
715600   /* GNET readlock check */
716   if (ide->gnetreadlock) {
717      ide->status &= ~IDE_STATUS_ERROR;
718      ide->status &= ~IDE_STATUS_BUSY;
601   if (gnetreadlock) {
602      status &= ~IDE_STATUS_ERROR;
603      status &= ~IDE_STATUS_BUSY;
719604      return;
720605   }
721606   /* now do the read */
722   if (ide->drive[ide->cur_drive].slot) {
723      count = ide->drive[ide->cur_drive].slot->read_sector(lba, ide->buffer);
607   if (drive[cur_drive].slot) {
608      count = drive[cur_drive].slot->read_sector(lba, buffer);
724609   }
725610
726611   /* by default, mark the buffer ready and the seek complete */
727   if (!ide->verify_only)
728      ide->status |= IDE_STATUS_BUFFER_READY;
729   ide->status |= IDE_STATUS_SEEK_COMPLETE;
612   if (!verify_only)
613      status |= IDE_STATUS_BUFFER_READY;
614   status |= IDE_STATUS_SEEK_COMPLETE;
730615
731616   /* and clear the busy and error flags */
732   ide->status &= ~IDE_STATUS_ERROR;
733   ide->status &= ~IDE_STATUS_BUSY;
617   status &= ~IDE_STATUS_ERROR;
618   status &= ~IDE_STATUS_BUSY;
734619
735620   /* if we succeeded, advance to the next sector and set the nice bits */
736621   if (count == 1)
737622   {
738623      /* advance the pointers, unless this is the last sector */
739624      /* Gauntlet: Dark Legacy checks to make sure we stop on the last sector */
740      if (ide->sector_count != 1)
741         next_sector(ide);
625      if (sector_count != 1)
626         next_sector();
742627
743628      /* clear the error value */
744      ide->error = IDE_ERROR_NONE;
629      error = IDE_ERROR_NONE;
745630
746631      /* signal an interrupt */
747      if (!ide->verify_only)
748         ide->sectors_until_int--;
749      if (ide->sectors_until_int == 0 || ide->sector_count == 1)
632      if (!verify_only)
633         sectors_until_int--;
634      if (sectors_until_int == 0 || sector_count == 1)
750635      {
751         ide->sectors_until_int = ((ide->command == IDE_COMMAND_READ_MULTIPLE_BLOCK) ? ide->block_count : 1);
752         signal_interrupt(ide);
636         sectors_until_int = ((command == IDE_COMMAND_READ_MULTIPLE_BLOCK) ? block_count : 1);
637         signal_interrupt();
753638      }
754639
755640      /* handle DMA */
756      if (ide->dma_active)
757         write_buffer_to_dma(ide);
641      if (dma_active)
642         write_buffer_to_dma();
758643
759644      /* if we're just verifying or if we DMA'ed the data, we can read the next sector */
760      if (ide->verify_only || ide->dma_active)
761         continue_read(ide);
645      if (verify_only || dma_active)
646         continue_read();
762647   }
763648
764649   /* if we got an error, we need to report it */
765650   else
766651   {
767652      /* set the error flag and the error */
768      ide->status |= IDE_STATUS_ERROR;
769      ide->error = IDE_ERROR_BAD_SECTOR;
770      ide->bus_master_status |= IDE_BUSMASTER_STATUS_ERROR;
771      ide->bus_master_status &= ~IDE_BUSMASTER_STATUS_ACTIVE;
653      status |= IDE_STATUS_ERROR;
654      error = IDE_ERROR_BAD_SECTOR;
655      bus_master_status |= IDE_BUSMASTER_STATUS_ERROR;
656      bus_master_status &= ~IDE_BUSMASTER_STATUS_ACTIVE;
772657
773658      /* signal an interrupt */
774      signal_interrupt(ide);
659      signal_interrupt();
775660   }
776661}
777662
778663
779664static TIMER_CALLBACK( read_sector_done_callback )
780665{
781   read_sector_done((ide_state *)ptr);
666   ide_controller_device *ide = (ide_controller_device *)ptr;
667
668   ide->read_sector_done();
782669}
783670
784671
785static void read_first_sector(ide_state *ide)
672void ide_controller_device::read_first_sector()
786673{
787674   /* mark ourselves busy */
788   ide->status |= IDE_STATUS_BUSY;
675   status |= IDE_STATUS_BUSY;
789676
790677   /* just set a timer */
791   if (ide->command == IDE_COMMAND_READ_MULTIPLE_BLOCK)
678   if (command == IDE_COMMAND_READ_MULTIPLE_BLOCK)
792679   {
793      int new_lba = lba_address(ide);
680      int new_lba = lba_address();
794681      attotime seek_time;
795682
796      if (new_lba == ide->drive[ide->cur_drive].cur_lba || new_lba == ide->drive[ide->cur_drive].cur_lba + 1)
683      if (new_lba == drive[cur_drive].cur_lba || new_lba == drive[cur_drive].cur_lba + 1)
797684         seek_time = TIME_NO_SEEK_MULTISECTOR;
798685      else
799686         seek_time = TIME_SEEK_MULTISECTOR;
800687
801      ide->drive[ide->cur_drive].cur_lba = new_lba;
802      ide->device->machine().scheduler().timer_set(seek_time, FUNC(read_sector_done_callback), 0, ide);
688      drive[cur_drive].cur_lba = new_lba;
689      machine().scheduler().timer_set(seek_time, FUNC(read_sector_done_callback), 0, this);
803690   }
804691   else
805      ide->device->machine().scheduler().timer_set(TIME_PER_SECTOR, FUNC(read_sector_done_callback), 0, ide);
692      machine().scheduler().timer_set(TIME_PER_SECTOR, FUNC(read_sector_done_callback), 0, this);
806693}
807694
808695
809static void read_next_sector(ide_state *ide)
696void ide_controller_device::read_next_sector()
810697{
811698   /* mark ourselves busy */
812   ide->status |= IDE_STATUS_BUSY;
699   status |= IDE_STATUS_BUSY;
813700
814   if (ide->command == IDE_COMMAND_READ_MULTIPLE_BLOCK)
701   if (command == IDE_COMMAND_READ_MULTIPLE_BLOCK)
815702   {
816      if (ide->sectors_until_int != 1)
703      if (sectors_until_int != 1)
817704         /* make ready now */
818         read_sector_done(ide);
705         read_sector_done();
819706      else
820707         /* just set a timer */
821         ide->device->machine().scheduler().timer_set(attotime::from_usec(1), FUNC(read_sector_done_callback), 0, ide);
708         machine().scheduler().timer_set(attotime::from_usec(1), FUNC(read_sector_done_callback), 0, this);
822709   }
823710   else
824711      /* just set a timer */
825      ide->device->machine().scheduler().timer_set(TIME_PER_SECTOR, FUNC(read_sector_done_callback), 0, ide);
712      machine().scheduler().timer_set(TIME_PER_SECTOR, FUNC(read_sector_done_callback), 0, this);
826713}
827714
828715
r18713r18714
833720 *
834721 *************************************/
835722
836static void write_sector_done(ide_state *ide);
837723static TIMER_CALLBACK( write_sector_done_callback );
838724
839static void continue_write(ide_state *ide)
725void ide_controller_device::continue_write()
840726{
841727   /* reset the totals */
842   ide->buffer_offset = 0;
728   buffer_offset = 0;
843729
844730   /* clear the buffer ready flag */
845   ide->status &= ~IDE_STATUS_BUFFER_READY;
846   ide->status |= IDE_STATUS_BUSY;
731   status &= ~IDE_STATUS_BUFFER_READY;
732   status |= IDE_STATUS_BUSY;
847733
848   if (ide->command == IDE_COMMAND_WRITE_MULTIPLE_BLOCK)
734   if (command == IDE_COMMAND_WRITE_MULTIPLE_BLOCK)
849735   {
850      if (ide->sectors_until_int != 1)
736      if (sectors_until_int != 1)
851737      {
852738         /* ready to write now */
853         write_sector_done(ide);
739         write_sector_done();
854740      }
855741      else
856742      {
857743         /* set a timer to do the write */
858         ide->device->machine().scheduler().timer_set(TIME_PER_SECTOR, FUNC(write_sector_done_callback), 0, ide);
744         machine().scheduler().timer_set(TIME_PER_SECTOR, FUNC(write_sector_done_callback), 0, this);
859745      }
860746   }
861747   else
862748   {
863749      /* set a timer to do the write */
864      ide->device->machine().scheduler().timer_set(TIME_PER_SECTOR, FUNC(write_sector_done_callback), 0, ide);
750      machine().scheduler().timer_set(TIME_PER_SECTOR, FUNC(write_sector_done_callback), 0, this);
865751   }
866752}
867753
868754
869static void read_buffer_from_dma(ide_state *ide)
755void ide_controller_device::read_buffer_from_dma()
870756{
871757   int bytesleft = IDE_DISK_SECTOR_SIZE;
872   UINT8 *data = ide->buffer;
758   UINT8 *data = buffer;
873759
874//  LOG(("Reading sector from %08X\n", ide->dma_address));
760//  LOG(("Reading sector from %08X\n", dma_address));
875761
876762   /* loop until we've consumed all bytes */
877763   while (bytesleft--)
878764   {
879765      /* if we're out of space, grab the next descriptor */
880      if (ide->dma_bytes_left == 0)
766      if (dma_bytes_left == 0)
881767      {
882768         /* if we're out of buffer space, that's bad */
883         if (ide->dma_last_buffer)
769         if (dma_last_buffer)
884770         {
885771            LOG(("DMA Out of buffer space!\n"));
886772            return;
887773         }
888774
889775         /* fetch the address */
890         ide->dma_address = ide->dma_space->read_byte(ide->dma_descriptor++ ^ ide->dma_address_xor);
891         ide->dma_address |= ide->dma_space->read_byte(ide->dma_descriptor++ ^ ide->dma_address_xor) << 8;
892         ide->dma_address |= ide->dma_space->read_byte(ide->dma_descriptor++ ^ ide->dma_address_xor) << 16;
893         ide->dma_address |= ide->dma_space->read_byte(ide->dma_descriptor++ ^ ide->dma_address_xor) << 24;
894         ide->dma_address &= 0xfffffffe;
776         dma_address = dma_space->read_byte(dma_descriptor++ ^ dma_address_xor);
777         dma_address |= dma_space->read_byte(dma_descriptor++ ^ dma_address_xor) << 8;
778         dma_address |= dma_space->read_byte(dma_descriptor++ ^ dma_address_xor) << 16;
779         dma_address |= dma_space->read_byte(dma_descriptor++ ^ dma_address_xor) << 24;
780         dma_address &= 0xfffffffe;
895781
896782         /* fetch the length */
897         ide->dma_bytes_left = ide->dma_space->read_byte(ide->dma_descriptor++ ^ ide->dma_address_xor);
898         ide->dma_bytes_left |= ide->dma_space->read_byte(ide->dma_descriptor++ ^ ide->dma_address_xor) << 8;
899         ide->dma_bytes_left |= ide->dma_space->read_byte(ide->dma_descriptor++ ^ ide->dma_address_xor) << 16;
900         ide->dma_bytes_left |= ide->dma_space->read_byte(ide->dma_descriptor++ ^ ide->dma_address_xor) << 24;
901         ide->dma_last_buffer = (ide->dma_bytes_left >> 31) & 1;
902         ide->dma_bytes_left &= 0xfffe;
903         if (ide->dma_bytes_left == 0)
904            ide->dma_bytes_left = 0x10000;
783         dma_bytes_left = dma_space->read_byte(dma_descriptor++ ^ dma_address_xor);
784         dma_bytes_left |= dma_space->read_byte(dma_descriptor++ ^ dma_address_xor) << 8;
785         dma_bytes_left |= dma_space->read_byte(dma_descriptor++ ^ dma_address_xor) << 16;
786         dma_bytes_left |= dma_space->read_byte(dma_descriptor++ ^ dma_address_xor) << 24;
787         dma_last_buffer = (dma_bytes_left >> 31) & 1;
788         dma_bytes_left &= 0xfffe;
789         if (dma_bytes_left == 0)
790            dma_bytes_left = 0x10000;
905791
906//          LOG(("New DMA descriptor: address = %08X  bytes = %04X  last = %d\n", ide->dma_address, ide->dma_bytes_left, ide->dma_last_buffer));
792//          LOG(("New DMA descriptor: address = %08X  bytes = %04X  last = %d\n", dma_address, dma_bytes_left, dma_last_buffer));
907793      }
908794
909795      /* read the next byte */
910      *data++ = ide->dma_space->read_byte(ide->dma_address++);
911      ide->dma_bytes_left--;
796      *data++ = dma_space->read_byte(dma_address++);
797      dma_bytes_left--;
912798   }
913799}
914800
915801
916static void write_sector_done(ide_state *ide)
802void ide_controller_device::write_sector_done()
917803{
918   int lba = lba_address(ide), count = 0;
804   int lba = lba_address(), count = 0;
919805
920806   /* now do the write */
921   if (ide->drive[ide->cur_drive].slot) {
922      count = ide->drive[ide->cur_drive].slot->write_sector(lba, ide->buffer);
807   if (drive[cur_drive].slot) {
808      count = drive[cur_drive].slot->write_sector(lba, buffer);
923809   }
924810
925811   /* by default, mark the buffer ready and the seek complete */
926   ide->status |= IDE_STATUS_BUFFER_READY;
927   ide->status |= IDE_STATUS_SEEK_COMPLETE;
812   status |= IDE_STATUS_BUFFER_READY;
813   status |= IDE_STATUS_SEEK_COMPLETE;
928814
929815   /* and clear the busy adn error flags */
930   ide->status &= ~IDE_STATUS_ERROR;
931   ide->status &= ~IDE_STATUS_BUSY;
816   status &= ~IDE_STATUS_ERROR;
817   status &= ~IDE_STATUS_BUSY;
932818
933819   /* if we succeeded, advance to the next sector and set the nice bits */
934820   if (count == 1)
935821   {
936822      /* advance the pointers, unless this is the last sector */
937823      /* Gauntlet: Dark Legacy checks to make sure we stop on the last sector */
938      if (ide->sector_count != 1)
939         next_sector(ide);
824      if (sector_count != 1)
825         next_sector();
940826
941827      /* clear the error value */
942      ide->error = IDE_ERROR_NONE;
828      error = IDE_ERROR_NONE;
943829
944830      /* signal an interrupt */
945      if (--ide->sectors_until_int == 0 || ide->sector_count == 1)
831      if (--sectors_until_int == 0 || sector_count == 1)
946832      {
947         ide->sectors_until_int = ((ide->command == IDE_COMMAND_WRITE_MULTIPLE_BLOCK) ? ide->block_count : 1);
948         signal_interrupt(ide);
833         sectors_until_int = ((command == IDE_COMMAND_WRITE_MULTIPLE_BLOCK) ? block_count : 1);
834         signal_interrupt();
949835      }
950836
951837      /* signal an interrupt if there's more data needed */
952      if (ide->sector_count > 0)
953         ide->sector_count--;
954      if (ide->sector_count == 0)
955         ide->status &= ~IDE_STATUS_BUFFER_READY;
838      if (sector_count > 0)
839         sector_count--;
840      if (sector_count == 0)
841         status &= ~IDE_STATUS_BUFFER_READY;
956842
957843      /* keep going for DMA */
958      if (ide->dma_active && ide->sector_count != 0)
844      if (dma_active && sector_count != 0)
959845      {
960         read_buffer_from_dma(ide);
961         continue_write(ide);
846         read_buffer_from_dma();
847         continue_write();
962848      }
963849      else
964         ide->dma_active = 0;
850         dma_active = 0;
965851   }
966852
967853   /* if we got an error, we need to report it */
968854   else
969855   {
970856      /* set the error flag and the error */
971      ide->status |= IDE_STATUS_ERROR;
972      ide->error = IDE_ERROR_BAD_SECTOR;
973      ide->bus_master_status |= IDE_BUSMASTER_STATUS_ERROR;
974      ide->bus_master_status &= ~IDE_BUSMASTER_STATUS_ACTIVE;
857      status |= IDE_STATUS_ERROR;
858      error = IDE_ERROR_BAD_SECTOR;
859      bus_master_status |= IDE_BUSMASTER_STATUS_ERROR;
860      bus_master_status &= ~IDE_BUSMASTER_STATUS_ACTIVE;
975861
976862      /* signal an interrupt */
977      signal_interrupt(ide);
863      signal_interrupt();
978864   }
979865}
980866
981867
982868static TIMER_CALLBACK( write_sector_done_callback )
983869{
984   write_sector_done((ide_state *)ptr);
870   ide_controller_device *ide = (ide_controller_device *)ptr;
871   ide->write_sector_done();
985872}
986873
987874
r18713r18714
992879 *
993880 *************************************/
994881
995static void handle_command(ide_state *ide, UINT8 command)
882void ide_controller_device::handle_command(UINT8 _command)
996883{
997884   UINT8 key[5];
998885
999886   /* implicitly clear interrupts here */
1000   clear_interrupt(ide);
1001   ide->command = command;
887   clear_interrupt();
888   command = _command;
1002889   switch (command)
1003890   {
1004891      case IDE_COMMAND_READ_MULTIPLE:
1005892      case IDE_COMMAND_READ_MULTIPLE_NORETRY:
1006893         LOGPRINT(("IDE Read multiple: C=%d H=%d S=%d LBA=%d count=%d\n",
1007            ide->drive[ide->cur_drive].cur_cylinder, ide->drive[ide->cur_drive].cur_head, ide->drive[ide->cur_drive].cur_sector, lba_address(ide), ide->sector_count));
894            drive[cur_drive].cur_cylinder, drive[cur_drive].cur_head, drive[cur_drive].cur_sector, lba_address(), sector_count));
1008895
1009896         /* reset the buffer */
1010         ide->buffer_offset = 0;
1011         ide->sectors_until_int = 1;
1012         ide->dma_active = 0;
1013         ide->verify_only = 0;
897         buffer_offset = 0;
898         sectors_until_int = 1;
899         dma_active = 0;
900         verify_only = 0;
1014901
1015902         /* start the read going */
1016         read_first_sector(ide);
903         read_first_sector();
1017904         break;
1018905
1019906      case IDE_COMMAND_READ_MULTIPLE_BLOCK:
1020907         LOGPRINT(("IDE Read multiple block: C=%d H=%d S=%d LBA=%d count=%d\n",
1021            ide->drive[ide->cur_drive].cur_cylinder, ide->drive[ide->cur_drive].cur_head, ide->drive[ide->cur_drive].cur_sector, lba_address(ide), ide->sector_count));
908            drive[cur_drive].cur_cylinder, drive[cur_drive].cur_head, drive[cur_drive].cur_sector, lba_address(), sector_count));
1022909
1023910         /* reset the buffer */
1024         ide->buffer_offset = 0;
1025         ide->sectors_until_int = 1;
1026         ide->dma_active = 0;
1027         ide->verify_only = 0;
911         buffer_offset = 0;
912         sectors_until_int = 1;
913         dma_active = 0;
914         verify_only = 0;
1028915
1029916         /* start the read going */
1030         read_first_sector(ide);
917         read_first_sector();
1031918         break;
1032919
1033920      case IDE_COMMAND_VERIFY_MULTIPLE:
1034921      case IDE_COMMAND_VERIFY_NORETRY:
1035922         LOGPRINT(("IDE Read verify multiple with/without retries: C=%d H=%d S=%d LBA=%d count=%d\n",
1036            ide->drive[ide->cur_drive].cur_cylinder, ide->drive[ide->cur_drive].cur_head, ide->drive[ide->cur_drive].cur_sector, lba_address(ide), ide->sector_count));
923            drive[cur_drive].cur_cylinder, drive[cur_drive].cur_head, drive[cur_drive].cur_sector, lba_address(), sector_count));
1037924
1038925         /* reset the buffer */
1039         ide->buffer_offset = 0;
1040         ide->sectors_until_int = 1;
1041         ide->dma_active = 0;
1042         ide->verify_only = 1;
926         buffer_offset = 0;
927         sectors_until_int = 1;
928         dma_active = 0;
929         verify_only = 1;
1043930
1044931         /* start the read going */
1045         read_first_sector(ide);
932         read_first_sector();
1046933         break;
1047934
1048935      case IDE_COMMAND_READ_DMA:
1049936         LOGPRINT(("IDE Read multiple DMA: C=%d H=%d S=%d LBA=%d count=%d\n",
1050            ide->drive[ide->cur_drive].cur_cylinder, ide->drive[ide->cur_drive].cur_head, ide->drive[ide->cur_drive].cur_sector, lba_address(ide), ide->sector_count));
937            drive[cur_drive].cur_cylinder, drive[cur_drive].cur_head, drive[cur_drive].cur_sector, lba_address(), sector_count));
1051938
1052939         /* reset the buffer */
1053         ide->buffer_offset = 0;
1054         ide->sectors_until_int = ide->sector_count;
1055         ide->dma_active = 1;
1056         ide->verify_only = 0;
940         buffer_offset = 0;
941         sectors_until_int = sector_count;
942         dma_active = 1;
943         verify_only = 0;
1057944
1058945         /* start the read going */
1059         if (ide->bus_master_command & 1)
1060            read_first_sector(ide);
946         if (bus_master_command & 1)
947            read_first_sector();
1061948         break;
1062949
1063950      case IDE_COMMAND_WRITE_MULTIPLE:
1064951      case IDE_COMMAND_WRITE_MULTIPLE_NORETRY:
1065952         LOGPRINT(("IDE Write multiple: C=%d H=%d S=%d LBA=%d count=%d\n",
1066            ide->drive[ide->cur_drive].cur_cylinder, ide->drive[ide->cur_drive].cur_head, ide->drive[ide->cur_drive].cur_sector, lba_address(ide), ide->sector_count));
953            drive[cur_drive].cur_cylinder, drive[cur_drive].cur_head, drive[cur_drive].cur_sector, lba_address(), sector_count));
1067954
1068955         /* reset the buffer */
1069         ide->buffer_offset = 0;
1070         ide->sectors_until_int = 1;
1071         ide->dma_active = 0;
956         buffer_offset = 0;
957         sectors_until_int = 1;
958         dma_active = 0;
1072959
1073960         /* mark the buffer ready */
1074         ide->status |= IDE_STATUS_BUFFER_READY;
961         status |= IDE_STATUS_BUFFER_READY;
1075962         break;
1076963
1077964      case IDE_COMMAND_WRITE_MULTIPLE_BLOCK:
1078965         LOGPRINT(("IDE Write multiple block: C=%d H=%d S=%d LBA=%d count=%d\n",
1079            ide->drive[ide->cur_drive].cur_cylinder, ide->drive[ide->cur_drive].cur_head, ide->drive[ide->cur_drive].cur_sector, lba_address(ide), ide->sector_count));
966            drive[cur_drive].cur_cylinder, drive[cur_drive].cur_head, drive[cur_drive].cur_sector, lba_address(), sector_count));
1080967
1081968         /* reset the buffer */
1082         ide->buffer_offset = 0;
1083         ide->sectors_until_int = 1;
1084         ide->dma_active = 0;
969         buffer_offset = 0;
970         sectors_until_int = 1;
971         dma_active = 0;
1085972
1086973         /* mark the buffer ready */
1087         ide->status |= IDE_STATUS_BUFFER_READY;
974         status |= IDE_STATUS_BUFFER_READY;
1088975         break;
1089976
1090977      case IDE_COMMAND_WRITE_DMA:
1091978         LOGPRINT(("IDE Write multiple DMA: C=%d H=%d S=%d LBA=%d count=%d\n",
1092            ide->drive[ide->cur_drive].cur_cylinder, ide->drive[ide->cur_drive].cur_head, ide->drive[ide->cur_drive].cur_sector, lba_address(ide), ide->sector_count));
979            drive[cur_drive].cur_cylinder, drive[cur_drive].cur_head, drive[cur_drive].cur_sector, lba_address(), sector_count));
1093980
1094981         /* reset the buffer */
1095         ide->buffer_offset = 0;
1096         ide->sectors_until_int = ide->sector_count;
1097         ide->dma_active = 1;
982         buffer_offset = 0;
983         sectors_until_int = sector_count;
984         dma_active = 1;
1098985
1099986         /* start the read going */
1100         if (ide->bus_master_command & 1)
987         if (bus_master_command & 1)
1101988         {
1102            read_buffer_from_dma(ide);
1103            continue_write(ide);
989            read_buffer_from_dma();
990            continue_write();
1104991         }
1105992         break;
1106993
r18713r18714
1108995         LOGPRINT(("IDE Security Unlock\n"));
1109996
1110997         /* reset the buffer */
1111         ide->buffer_offset = 0;
1112         ide->sectors_until_int = 0;
1113         ide->dma_active = 0;
998         buffer_offset = 0;
999         sectors_until_int = 0;
1000         dma_active = 0;
11141001
11151002         /* mark the buffer ready */
1116         ide->status |= IDE_STATUS_BUFFER_READY;
1117         signal_interrupt(ide);
1003         status |= IDE_STATUS_BUFFER_READY;
1004         signal_interrupt();
11181005         break;
11191006
11201007      case IDE_COMMAND_GET_INFO:
11211008         LOGPRINT(("IDE Read features\n"));
11221009
11231010         /* reset the buffer */
1124         ide->buffer_offset = 0;
1125         ide->sector_count = 1;
1011         buffer_offset = 0;
1012         sector_count = 1;
11261013
11271014         /* build the features page */
1128         if (ide->drive[ide->cur_drive].slot->get_features()) {
1129            memcpy(ide->buffer, ide->drive[ide->cur_drive].slot->get_features(), sizeof(ide->buffer));
1015         if (drive[cur_drive].slot->get_features()) {
1016            memcpy(buffer, drive[cur_drive].slot->get_features(), sizeof(buffer));
11301017         }
11311018
11321019         /* indicate everything is ready */
1133         ide->status |= IDE_STATUS_BUFFER_READY;
1134         ide->status |= IDE_STATUS_SEEK_COMPLETE;
1135         ide->status |= IDE_STATUS_DRIVE_READY;
1020         status |= IDE_STATUS_BUFFER_READY;
1021         status |= IDE_STATUS_SEEK_COMPLETE;
1022         status |= IDE_STATUS_DRIVE_READY;
11361023
11371024         /* and clear the busy adn error flags */
1138         ide->status &= ~IDE_STATUS_ERROR;
1139         ide->status &= ~IDE_STATUS_BUSY;
1025         status &= ~IDE_STATUS_ERROR;
1026         status &= ~IDE_STATUS_BUSY;
11401027
11411028         /* clear the error too */
1142         ide->error = IDE_ERROR_NONE;
1029         error = IDE_ERROR_NONE;
11431030
11441031         /* signal an interrupt */
1145         signal_delayed_interrupt(ide, MINIMUM_COMMAND_TIME, 1);
1032         signal_delayed_interrupt(MINIMUM_COMMAND_TIME, 1);
11461033         break;
11471034
11481035      case IDE_COMMAND_DIAGNOSTIC:
1149         ide->error = IDE_ERROR_DEFAULT;
1036         error = IDE_ERROR_DEFAULT;
11501037
11511038         /* signal an interrupt */
1152         signal_delayed_interrupt(ide, MINIMUM_COMMAND_TIME, 0);
1039         signal_delayed_interrupt(MINIMUM_COMMAND_TIME, 0);
11531040         break;
11541041
11551042      case IDE_COMMAND_RECALIBRATE:
11561043         /* clear the error too */
1157         ide->error = IDE_ERROR_NONE;
1044         error = IDE_ERROR_NONE;
11581045         /* signal an interrupt */
1159         signal_delayed_interrupt(ide, MINIMUM_COMMAND_TIME, 0);
1046         signal_delayed_interrupt(MINIMUM_COMMAND_TIME, 0);
11601047         break;
11611048
11621049      case IDE_COMMAND_IDLE:
11631050         /* clear the error too */
1164         ide->error = IDE_ERROR_NONE;
1051         error = IDE_ERROR_NONE;
11651052
11661053         /* for timeout disabled value is 0 */
1167         ide->sector_count = 0;
1054         sector_count = 0;
11681055         /* signal an interrupt */
1169         signal_interrupt(ide);
1056         signal_interrupt();
11701057         break;
11711058
11721059      case IDE_COMMAND_SET_CONFIG:
1173         LOGPRINT(("IDE Set configuration (%d heads, %d sectors)\n", ide->drive[ide->cur_drive].cur_head + 1, ide->sector_count));
1174         ide->status &= ~IDE_STATUS_ERROR;
1175         ide->error = IDE_ERROR_NONE;
1176         ide->drive[ide->cur_drive].slot->set_geometry(ide->sector_count,ide->drive[ide->cur_drive].cur_head + 1);
1060         LOGPRINT(("IDE Set configuration (%d heads, %d sectors)\n", drive[cur_drive].cur_head + 1, sector_count));
1061         status &= ~IDE_STATUS_ERROR;
1062         error = IDE_ERROR_NONE;
1063         drive[cur_drive].slot->set_geometry(sector_count,drive[cur_drive].cur_head + 1);
11771064
11781065         /* signal an interrupt */
1179         signal_delayed_interrupt(ide, MINIMUM_COMMAND_TIME, 0);
1066         signal_delayed_interrupt(MINIMUM_COMMAND_TIME, 0);
11801067         break;
11811068
11821069      case IDE_COMMAND_UNKNOWN_F9:
r18713r18714
11841071         LOGPRINT(("IDE unknown command (F9)\n"));
11851072
11861073         /* signal an interrupt */
1187         signal_interrupt(ide);
1074         signal_interrupt();
11881075         break;
11891076
11901077      case IDE_COMMAND_SET_FEATURES:
1191         LOGPRINT(("IDE Set features (%02X %02X %02X %02X %02X)\n", ide->precomp_offset, ide->sector_count & 0xff, ide->drive[ide->cur_drive].cur_sector, ide->drive[ide->cur_drive].cur_cylinder & 0xff, ide->drive[ide->cur_drive].cur_cylinder >> 8));
1078         LOGPRINT(("IDE Set features (%02X %02X %02X %02X %02X)\n", precomp_offset, sector_count & 0xff, drive[cur_drive].cur_sector, drive[cur_drive].cur_cylinder & 0xff, drive[cur_drive].cur_cylinder >> 8));
11921079
11931080         /* signal an interrupt */
1194         signal_delayed_interrupt(ide, MINIMUM_COMMAND_TIME, 0);
1081         signal_delayed_interrupt(MINIMUM_COMMAND_TIME, 0);
11951082         break;
11961083
11971084      case IDE_COMMAND_SET_BLOCK_COUNT:
1198         LOGPRINT(("IDE Set block count (%02X)\n", ide->sector_count));
1085         LOGPRINT(("IDE Set block count (%02X)\n", sector_count));
11991086
1200         ide->block_count = ide->sector_count;
1087         block_count = sector_count;
12011088         // judge dredd wants 'drive ready' on this command
1202         ide->status |= IDE_STATUS_DRIVE_READY;
1089         status |= IDE_STATUS_DRIVE_READY;
12031090
12041091         /* signal an interrupt */
1205         signal_interrupt(ide);
1092         signal_interrupt();
12061093         break;
12071094
12081095      case IDE_COMMAND_TAITO_GNET_UNLOCK_1:
12091096         LOGPRINT(("IDE GNET Unlock 1\n"));
12101097
1211         ide->sector_count = 1;
1212         ide->status |= IDE_STATUS_DRIVE_READY;
1213         ide->status &= ~IDE_STATUS_ERROR;
1214         signal_interrupt(ide);
1098         sector_count = 1;
1099         status |= IDE_STATUS_DRIVE_READY;
1100         status &= ~IDE_STATUS_ERROR;
1101         signal_interrupt();
12151102         break;
12161103
12171104      case IDE_COMMAND_TAITO_GNET_UNLOCK_2:
12181105         LOGPRINT(("IDE GNET Unlock 2\n"));
12191106
12201107         /* reset the buffer */
1221         ide->buffer_offset = 0;
1222         ide->sectors_until_int = 0;
1223         ide->dma_active = 0;
1108         buffer_offset = 0;
1109         sectors_until_int = 0;
1110         dma_active = 0;
12241111
12251112         /* mark the buffer ready */
1226         ide->status |= IDE_STATUS_BUFFER_READY;
1227         signal_interrupt(ide);
1113         status |= IDE_STATUS_BUFFER_READY;
1114         signal_interrupt();
12281115         break;
12291116
12301117      case IDE_COMMAND_TAITO_GNET_UNLOCK_3:
12311118         LOGPRINT(("IDE GNET Unlock 3\n"));
12321119
12331120         /* key check */
1234         ide->drive[ide->cur_drive].slot->read_key(key);
1235         if ((ide->precomp_offset == key[0]) && (ide->sector_count == key[1]) && (ide->drive[ide->cur_drive].cur_sector == key[2]) && (ide->drive[ide->cur_drive].cur_cylinder == (((UINT16)key[4]<<8)|key[3])))
1121         drive[cur_drive].slot->read_key(key);
1122         if ((precomp_offset == key[0]) && (sector_count == key[1]) && (drive[cur_drive].cur_sector == key[2]) && (drive[cur_drive].cur_cylinder == (((UINT16)key[4]<<8)|key[3])))
12361123         {
1237            ide->gnetreadlock= 0;
1124            gnetreadlock= 0;
12381125         }
12391126
12401127         /* update flags */
1241         ide->status |= IDE_STATUS_DRIVE_READY;
1242         ide->status &= ~IDE_STATUS_ERROR;
1243         signal_interrupt(ide);
1128         status |= IDE_STATUS_DRIVE_READY;
1129         status &= ~IDE_STATUS_ERROR;
1130         signal_interrupt();
12441131         break;
12451132
12461133      case IDE_COMMAND_SEEK:
r18713r18714
12501137                so that implements actual seek
12511138            */
12521139         /* clear the error too */
1253         ide->error = IDE_ERROR_NONE;
1140         error = IDE_ERROR_NONE;
12541141
12551142         /* for timeout disabled value is 0 */
1256         ide->sector_count = 0;
1143         sector_count = 0;
12571144         /* signal an interrupt */
1258         signal_interrupt(ide);
1145         signal_interrupt();
12591146         break;
12601147
12611148
12621149      default:
12631150         LOGPRINT(("IDE unknown command (%02X)\n", command));
1264         ide->status |= IDE_STATUS_ERROR;
1265         ide->error = IDE_ERROR_UNKNOWN_COMMAND;
1266         signal_interrupt(ide);
1267         //debugger_break(ide->device->machine());
1151         status |= IDE_STATUS_ERROR;
1152         error = IDE_ERROR_UNKNOWN_COMMAND;
1153         signal_interrupt();
1154         //debugger_break(device->machine());
12681155         break;
12691156   }
12701157}
r18713r18714
12771164 *
12781165 *************************************/
12791166
1280static UINT32 ide_controller_read(device_t *device, int bank, offs_t offset, int size)
1167UINT32 ide_controller_device::ide_controller_read(int bank, offs_t offset, int size)
12811168{
1282   ide_state *ide = get_safe_token(device);
12831169   UINT32 result = 0;
12841170
12851171   /* logit */
12861172//  if (BANK(bank, offset) != IDE_BANK0_DATA && BANK(bank, offset) != IDE_BANK0_STATUS_COMMAND && BANK(bank, offset) != IDE_BANK1_STATUS_CONTROL)
1287      LOG(("%s:IDE read at %d:%X, size=%d\n", device->machine().describe_context(), bank, offset, size));
1173      LOG(("%s:IDE read at %d:%X, size=%d\n", machine().describe_context(), bank, offset, size));
12881174
1289   if (ide->drive[ide->cur_drive].slot->is_connected())
1175   if (drive[cur_drive].slot->is_connected())
12901176   {
1291      if (ide->drive[ide->cur_drive].slot->is_ready()) {
1292         ide->status |= IDE_STATUS_DRIVE_READY;
1177      if (drive[cur_drive].slot->is_ready()) {
1178         status |= IDE_STATUS_DRIVE_READY;
12931179      } else {
1294         ide->status &= ~IDE_STATUS_DRIVE_READY;
1180         status &= ~IDE_STATUS_DRIVE_READY;
12951181      }
12961182   }
12971183
r18713r18714
12991185   {
13001186      /* unknown config register */
13011187      case IDE_BANK2_CONFIG_UNK:
1302         return ide->config_unknown;
1188         return config_unknown;
13031189
13041190      /* active config register */
13051191      case IDE_BANK2_CONFIG_REGISTER:
1306         return ide->config_register_num;
1192         return config_register_num;
13071193
13081194      /* data from active config register */
13091195      case IDE_BANK2_CONFIG_DATA:
1310         if (ide->config_register_num < IDE_CONFIG_REGISTERS)
1311            return ide->config_register[ide->config_register_num];
1196         if (config_register_num < IDE_CONFIG_REGISTERS)
1197            return config_register[config_register_num];
13121198         return 0;
13131199
13141200      /* read data if there's data to be read */
13151201      case IDE_BANK0_DATA:
1316         if (ide->status & IDE_STATUS_BUFFER_READY)
1202         if (status & IDE_STATUS_BUFFER_READY)
13171203         {
13181204            /* fetch the correct amount of data */
1319            result = ide->buffer[ide->buffer_offset++];
1205            result = buffer[buffer_offset++];
13201206            if (size > 1)
1321               result |= ide->buffer[ide->buffer_offset++] << 8;
1207               result |= buffer[buffer_offset++] << 8;
13221208            if (size > 2)
13231209            {
1324               result |= ide->buffer[ide->buffer_offset++] << 16;
1325               result |= ide->buffer[ide->buffer_offset++] << 24;
1210               result |= buffer[buffer_offset++] << 16;
1211               result |= buffer[buffer_offset++] << 24;
13261212            }
13271213
13281214            /* if we're at the end of the buffer, handle it */
1329            if (ide->buffer_offset >= IDE_DISK_SECTOR_SIZE)
1215            if (buffer_offset >= IDE_DISK_SECTOR_SIZE)
13301216            {
1331               LOG(("%s:IDE completed PIO read\n", device->machine().describe_context()));
1332               continue_read(ide);
1333               ide->error = IDE_ERROR_DEFAULT;
1217               LOG(("%s:IDE completed PIO read\n", machine().describe_context()));
1218               continue_read();
1219               error = IDE_ERROR_DEFAULT;
13341220            }
13351221         }
13361222         break;
13371223
13381224      /* return the current error */
13391225      case IDE_BANK0_ERROR:
1340         return ide->error;
1226         return error;
13411227
13421228      /* return the current sector count */
13431229      case IDE_BANK0_SECTOR_COUNT:
1344         return ide->sector_count;
1230         return sector_count;
13451231
13461232      /* return the current sector */
13471233      case IDE_BANK0_SECTOR_NUMBER:
1348         return ide->drive[ide->cur_drive].cur_sector;
1234         return drive[cur_drive].cur_sector;
13491235
13501236      /* return the current cylinder LSB */
13511237      case IDE_BANK0_CYLINDER_LSB:
1352         return ide->drive[ide->cur_drive].cur_cylinder & 0xff;
1238         return drive[cur_drive].cur_cylinder & 0xff;
13531239
13541240      /* return the current cylinder MSB */
13551241      case IDE_BANK0_CYLINDER_MSB:
1356         return ide->drive[ide->cur_drive].cur_cylinder >> 8;
1242         return drive[cur_drive].cur_cylinder >> 8;
13571243
13581244      /* return the current head */
13591245      case IDE_BANK0_HEAD_NUMBER:
1360         return ide->drive[ide->cur_drive].cur_head_reg;
1246         return drive[cur_drive].cur_head_reg;
13611247
13621248      /* return the current status and clear any pending interrupts */
13631249      case IDE_BANK0_STATUS_COMMAND:
13641250      /* return the current status but don't clear interrupts */
13651251      case IDE_BANK1_STATUS_CONTROL:
1366         result = ide->status;
1367         if (ide->last_status_timer->elapsed() > TIME_PER_ROTATION)
1252         result = status;
1253         if (last_status_timer->elapsed() > TIME_PER_ROTATION)
13681254         {
13691255            result |= IDE_STATUS_HIT_INDEX;
1370            ide->last_status_timer->adjust(attotime::never);
1256            last_status_timer->adjust(attotime::never);
13711257         }
13721258
13731259         /* clear interrutps only when reading the real status */
13741260         if (BANK(bank, offset) == IDE_BANK0_STATUS_COMMAND)
13751261         {
1376            if (ide->interrupt_pending)
1377               clear_interrupt(ide);
1262            if (interrupt_pending)
1263               clear_interrupt();
13781264         }
13791265         break;
13801266
13811267      /* log anything else */
13821268      default:
1383         logerror("%s:unknown IDE read at %03X, size=%d\n", device->machine().describe_context(), offset, size);
1269         logerror("%s:unknown IDE read at %03X, size=%d\n", machine().describe_context(), offset, size);
13841270         break;
13851271   }
13861272
r18713r18714
13961282 *
13971283 *************************************/
13981284
1399static void ide_controller_write(device_t *device, int bank, offs_t offset, int size, UINT32 data)
1285void ide_controller_device::ide_controller_write(int bank, offs_t offset, int size, UINT32 data)
14001286{
1401   ide_state *ide = get_safe_token(device);
1402
14031287   /* logit */
14041288   if (BANK(bank, offset) != IDE_BANK0_DATA)
1405      LOG(("%s:IDE write to %d:%X = %08X, size=%d\n", device->machine().describe_context(), bank, offset, data, size));
1289      LOG(("%s:IDE write to %d:%X = %08X, size=%d\n", machine().describe_context(), bank, offset, data, size));
14061290   //  fprintf(stderr, "ide write %03x %02x size=%d\n", offset, data, size);
14071291   switch (BANK(bank, offset))
14081292   {
14091293      /* unknown config register */
14101294      case IDE_BANK2_CONFIG_UNK:
1411         ide->config_unknown = data;
1295         config_unknown = data;
14121296         break;
14131297
14141298      /* active config register */
14151299      case IDE_BANK2_CONFIG_REGISTER:
1416         ide->config_register_num = data;
1300         config_register_num = data;
14171301         break;
14181302
14191303      /* data from active config register */
14201304      case IDE_BANK2_CONFIG_DATA:
1421         if (ide->config_register_num < IDE_CONFIG_REGISTERS)
1422            ide->config_register[ide->config_register_num] = data;
1305         if (config_register_num < IDE_CONFIG_REGISTERS)
1306            config_register[config_register_num] = data;
14231307         break;
14241308
14251309      /* write data */
14261310      case IDE_BANK0_DATA:
1427         if (ide->status & IDE_STATUS_BUFFER_READY)
1311         if (status & IDE_STATUS_BUFFER_READY)
14281312         {
14291313            /* store the correct amount of data */
1430            ide->buffer[ide->buffer_offset++] = data;
1314            buffer[buffer_offset++] = data;
14311315            if (size > 1)
1432               ide->buffer[ide->buffer_offset++] = data >> 8;
1316               buffer[buffer_offset++] = data >> 8;
14331317            if (size > 2)
14341318            {
1435               ide->buffer[ide->buffer_offset++] = data >> 16;
1436               ide->buffer[ide->buffer_offset++] = data >> 24;
1319               buffer[buffer_offset++] = data >> 16;
1320               buffer[buffer_offset++] = data >> 24;
14371321            }
14381322
14391323            /* if we're at the end of the buffer, handle it */
1440            if (ide->buffer_offset >= IDE_DISK_SECTOR_SIZE)
1324            if (buffer_offset >= IDE_DISK_SECTOR_SIZE)
14411325            {
1442               LOG(("%s:IDE completed PIO write\n", device->machine().describe_context()));
1443               if (ide->command == IDE_COMMAND_SECURITY_UNLOCK)
1326               LOG(("%s:IDE completed PIO write\n", machine().describe_context()));
1327               if (command == IDE_COMMAND_SECURITY_UNLOCK)
14441328               {
1445                  if (ide->user_password_enable && memcmp(ide->buffer, ide->user_password, 2 + 32) == 0)
1329                  if (user_password_enable && memcmp(buffer, user_password, 2 + 32) == 0)
14461330                  {
14471331                     LOGPRINT(("IDE Unlocked user password\n"));
1448                     ide->user_password_enable = 0;
1332                     user_password_enable = 0;
14491333                  }
1450                  if (ide->master_password_enable && memcmp(ide->buffer, ide->master_password, 2 + 32) == 0)
1334                  if (master_password_enable && memcmp(buffer, master_password, 2 + 32) == 0)
14511335                  {
14521336                     LOGPRINT(("IDE Unlocked master password\n"));
1453                     ide->master_password_enable = 0;
1337                     master_password_enable = 0;
14541338                  }
14551339                  if (PRINTF_IDE_PASSWORD)
14561340                  {
r18713r18714
14611345                        if (i % 8 == 2)
14621346                           mame_printf_debug("\n");
14631347
1464                        mame_printf_debug("0x%02x, 0x%02x, ", ide->buffer[i], ide->buffer[i + 1]);
1465                        //mame_printf_debug("0x%02x%02x, ", ide->buffer[i], ide->buffer[i + 1]);
1348                        mame_printf_debug("0x%02x, 0x%02x, ", buffer[i], buffer[i + 1]);
1349                        //mame_printf_debug("0x%02x%02x, ", buffer[i], buffer[i + 1]);
14661350                     }
14671351                     mame_printf_debug("\n");
14681352                  }
14691353
14701354                  /* clear the busy and error flags */
1471                  ide->status &= ~IDE_STATUS_ERROR;
1472                  ide->status &= ~IDE_STATUS_BUSY;
1473                  ide->status &= ~IDE_STATUS_BUFFER_READY;
1355                  status &= ~IDE_STATUS_ERROR;
1356                  status &= ~IDE_STATUS_BUSY;
1357                  status &= ~IDE_STATUS_BUFFER_READY;
14741358
1475                  if (ide->master_password_enable || ide->user_password_enable)
1476                     security_error(ide);
1359                  if (master_password_enable || user_password_enable)
1360                     security_error();
14771361                  else
1478                     ide->status |= IDE_STATUS_DRIVE_READY;
1362                     status |= IDE_STATUS_DRIVE_READY;
14791363               }
1480               else if (ide->command == IDE_COMMAND_TAITO_GNET_UNLOCK_2)
1364               else if (command == IDE_COMMAND_TAITO_GNET_UNLOCK_2)
14811365               {
14821366                  UINT8 key[5] = { 0 };
14831367                  int i, bad = 0;
1484                  ide->drive[ide->cur_drive].slot->read_key(key);
1368                  drive[cur_drive].slot->read_key(key);
14851369
14861370                  for (i=0; !bad && i<512; i++)
1487                     bad = ((i < 2 || i >= 7) && ide->buffer[i]) || ((i >= 2 && i < 7) && ide->buffer[i] != key[i-2]);
1371                     bad = ((i < 2 || i >= 7) && buffer[i]) || ((i >= 2 && i < 7) && buffer[i] != key[i-2]);
14881372
1489                  ide->status &= ~IDE_STATUS_BUSY;
1490                  ide->status &= ~IDE_STATUS_BUFFER_READY;
1373                  status &= ~IDE_STATUS_BUSY;
1374                  status &= ~IDE_STATUS_BUFFER_READY;
14911375                  if (bad)
1492                     ide->status |= IDE_STATUS_ERROR;
1376                     status |= IDE_STATUS_ERROR;
14931377                  else {
1494                     ide->status &= ~IDE_STATUS_ERROR;
1495                     ide->gnetreadlock= 0;
1378                     status &= ~IDE_STATUS_ERROR;
1379                     gnetreadlock= 0;
14961380                  }
14971381               }
14981382               else
1499                  continue_write(ide);
1383                  continue_write();
15001384
15011385            }
15021386         }
r18713r18714
15041388
15051389      /* precompensation offset?? */
15061390      case IDE_BANK0_ERROR:
1507         ide->precomp_offset = data;
1391         precomp_offset = data;
15081392         break;
15091393
15101394      /* sector count */
15111395      case IDE_BANK0_SECTOR_COUNT:
1512         ide->sector_count = data ? data : 256;
1396         sector_count = data ? data : 256;
15131397         break;
15141398
15151399      /* current sector */
15161400      case IDE_BANK0_SECTOR_NUMBER:
1517         ide->drive[ide->cur_drive].cur_sector = data;
1401         drive[cur_drive].cur_sector = data;
15181402         break;
15191403
15201404      /* current cylinder LSB */
15211405      case IDE_BANK0_CYLINDER_LSB:
1522         ide->drive[ide->cur_drive].cur_cylinder = (ide->drive[ide->cur_drive].cur_cylinder & 0xff00) | (data & 0xff);
1406         drive[cur_drive].cur_cylinder = (drive[cur_drive].cur_cylinder & 0xff00) | (data & 0xff);
15231407         break;
15241408
15251409      /* current cylinder MSB */
15261410      case IDE_BANK0_CYLINDER_MSB:
1527         ide->drive[ide->cur_drive].cur_cylinder = (ide->drive[ide->cur_drive].cur_cylinder & 0x00ff) | ((data & 0xff) << 8);
1411         drive[cur_drive].cur_cylinder = (drive[cur_drive].cur_cylinder & 0x00ff) | ((data & 0xff) << 8);
15281412         break;
15291413
15301414      /* current head */
15311415      case IDE_BANK0_HEAD_NUMBER:
1532         ide->cur_drive = (data & 0x10) >> 4;
1533         ide->drive[ide->cur_drive].cur_head = data & 0x0f;
1534         ide->drive[ide->cur_drive].cur_head_reg = data;
1416         cur_drive = (data & 0x10) >> 4;
1417         drive[cur_drive].cur_head = data & 0x0f;
1418         drive[cur_drive].cur_head_reg = data;
15351419         // LBA mode = data & 0x40
15361420         break;
15371421
15381422      /* command */
15391423      case IDE_BANK0_STATUS_COMMAND:
1540         handle_command(ide, data);
1424         handle_command(data);
15411425         break;
15421426
15431427      /* adapter control */
15441428      case IDE_BANK1_STATUS_CONTROL:
1545         ide->adapter_control = data;
1429         adapter_control = data;
15461430
15471431         /* handle controller reset */
15481432         //if (data == 0x04)
15491433         if (data & 0x04)
15501434         {
1551            ide->status |= IDE_STATUS_BUSY;
1552            ide->status &= ~IDE_STATUS_DRIVE_READY;
1553            ide->reset_timer->adjust(attotime::from_msec(5));
1435            status |= IDE_STATUS_BUSY;
1436            status &= ~IDE_STATUS_DRIVE_READY;
1437            reset_timer->adjust(attotime::from_msec(5));
15541438         }
15551439         break;
15561440   }
r18713r18714
15641448 *
15651449 *************************************/
15661450
1567static UINT32 ide_bus_master_read(device_t *device, offs_t offset, int size)
1451UINT32 ide_controller_device::ide_bus_master_read(offs_t offset, int size)
15681452{
1569   ide_state *ide = get_safe_token(device);
1453   LOG(("%s:ide_bus_master_read(%d, %d)\n", machine().describe_context(), offset, size));
15701454
1571   LOG(("%s:ide_bus_master_read(%d, %d)\n", device->machine().describe_context(), offset, size));
1572
15731455   /* command register */
15741456   if (offset == 0)
1575      return ide->bus_master_command | (ide->bus_master_status << 16);
1457      return bus_master_command | (bus_master_status << 16);
15761458
15771459   /* status register */
15781460   if (offset == 2)
1579      return ide->bus_master_status;
1461      return bus_master_status;
15801462
15811463   /* descriptor table register */
15821464   if (offset == 4)
1583      return ide->bus_master_descriptor;
1465      return bus_master_descriptor;
15841466
15851467   return 0xffffffff;
15861468}
r18713r18714
15931475 *
15941476 *************************************/
15951477
1596static void ide_bus_master_write(device_t *device, offs_t offset, int size, UINT32 data)
1478void ide_controller_device::ide_bus_master_write(offs_t offset, int size, UINT32 data)
15971479{
1598   ide_state *ide = get_safe_token(device);
1480   LOG(("%s:ide_bus_master_write(%d, %d, %08X)\n", machine().describe_context(), offset, size, data));
15991481
1600   LOG(("%s:ide_bus_master_write(%d, %d, %08X)\n", device->machine().describe_context(), offset, size, data));
1601
16021482   /* command register */
16031483   if (offset == 0)
16041484   {
1605      UINT8 old = ide->bus_master_command;
1485      UINT8 old = bus_master_command;
16061486      UINT8 val = data & 0xff;
16071487
16081488      /* save the read/write bit and the start/stop bit */
1609      ide->bus_master_command = (old & 0xf6) | (val & 0x09);
1610      ide->bus_master_status = (ide->bus_master_status & ~IDE_BUSMASTER_STATUS_ACTIVE) | (val & 0x01);
1489      bus_master_command = (old & 0xf6) | (val & 0x09);
1490      bus_master_status = (bus_master_status & ~IDE_BUSMASTER_STATUS_ACTIVE) | (val & 0x01);
16111491
16121492      /* handle starting a transfer */
16131493      if (!(old & 1) && (val & 1))
16141494      {
16151495         /* reset all the DMA data */
1616         ide->dma_bytes_left = 0;
1617         ide->dma_last_buffer = 0;
1618         ide->dma_descriptor = ide->bus_master_descriptor;
1496         dma_bytes_left = 0;
1497         dma_last_buffer = 0;
1498         dma_descriptor = bus_master_descriptor;
16191499
16201500         /* if we're going live, start the pending read/write */
1621         if (ide->dma_active)
1501         if (dma_active)
16221502         {
1623            if (ide->bus_master_command & 8)
1624               read_next_sector(ide);
1503            if (bus_master_command & 8)
1504               read_next_sector();
16251505            else
16261506            {
1627               read_buffer_from_dma(ide);
1628               continue_write(ide);
1507               read_buffer_from_dma();
1508               continue_write();
16291509            }
16301510         }
16311511      }
r18713r18714
16341514   /* status register */
16351515   if (offset <= 2 && offset + size > 2)
16361516   {
1637      UINT8 old = ide->bus_master_status;
1517      UINT8 old = bus_master_status;
16381518      UINT8 val = data >> (8 * (2 - offset));
16391519
16401520      /* save the DMA capable bits */
1641      ide->bus_master_status = (old & 0x9f) | (val & 0x60);
1521      bus_master_status = (old & 0x9f) | (val & 0x60);
16421522
16431523      /* clear interrupt and error bits */
16441524      if (val & IDE_BUSMASTER_STATUS_IRQ)
1645         ide->bus_master_status &= ~IDE_BUSMASTER_STATUS_IRQ;
1525         bus_master_status &= ~IDE_BUSMASTER_STATUS_IRQ;
16461526      if (val & IDE_BUSMASTER_STATUS_ERROR)
1647         ide->bus_master_status &= ~IDE_BUSMASTER_STATUS_ERROR;
1527         bus_master_status &= ~IDE_BUSMASTER_STATUS_ERROR;
16481528   }
16491529
16501530   /* descriptor table register */
16511531   if (offset == 4)
1652      ide->bus_master_descriptor = data & 0xfffffffc;
1532      bus_master_descriptor = data & 0xfffffffc;
16531533}
16541534
16551535
r18713r18714
16701550*/
16711551int ide_bus_r(device_t *device, int select, int offset)
16721552{
1673   return ide_controller_read(device, select ? 1 : 0, offset, select == 0 && offset == 0 ? 2 : 1);
1553   ide_controller_device *ide = (ide_controller_device *) device;
1554   return ide->ide_controller_read(select ? 1 : 0, offset, select == 0 && offset == 0 ? 2 : 1);
16741555}
16751556
16761557/*
r18713r18714
16841565*/
16851566void ide_bus_w(device_t *device, int select, int offset, int data)
16861567{
1568   ide_controller_device *ide = (ide_controller_device *) device;
16871569   if (select == 0 && offset == 0)
1688      ide_controller_write(device, 0, 0, 2, data);
1570      ide->ide_controller_write(0, 0, 2, data);
16891571   else
1690      ide_controller_write(device, select ? 1 : 0, offset, 1, data & 0xff);
1572      ide->ide_controller_write(select ? 1 : 0, offset, 1, data & 0xff);
16911573}
16921574
16931575UINT32 ide_controller_r(device_t *device, int reg, int size)
16941576{
1577   ide_controller_device *ide = (ide_controller_device *) device;
16951578   if (reg >= 0x1f0 && reg < 0x1f8)
1696      return ide_controller_read(device, 0, reg & 7, size);
1579      return ide->ide_controller_read(0, reg & 7, size);
16971580   if (reg >= 0x3f0 && reg < 0x3f8)
1698      return ide_controller_read(device, 1, reg & 7, size);
1581      return ide->ide_controller_read(1, reg & 7, size);
16991582   if (reg >= 0x030 && reg < 0x040)
1700      return ide_controller_read(device, 2, reg & 0xf, size);
1583      return ide->ide_controller_read(2, reg & 0xf, size);
17011584   return 0xffffffff;
17021585}
17031586
17041587void ide_controller_w(device_t *device, int reg, int size, UINT32 data)
17051588{
1589   ide_controller_device *ide = (ide_controller_device *) device;
17061590   if (reg >= 0x1f0 && reg < 0x1f8)
1707      ide_controller_write(device, 0, reg & 7, size, data);
1591      ide->ide_controller_write(0, reg & 7, size, data);
17081592   if (reg >= 0x3f0 && reg < 0x3f8)
1709      ide_controller_write(device, 1, reg & 7, size, data);
1593      ide->ide_controller_write(1, reg & 7, size, data);
17101594   if (reg >= 0x030 && reg < 0x040)
1711      ide_controller_write(device, 2, reg & 0xf, size, data);
1595      ide->ide_controller_write(2, reg & 0xf, size, data);
17121596}
17131597
17141598
r18713r18714
17431627
17441628READ32_DEVICE_HANDLER( ide_controller32_pcmcia_r )
17451629{
1630   ide_controller_device *ide = (ide_controller_device *) device;
1631
17461632   int size;
17471633   UINT32 res = 0xffffffff;
17481634
r18713r18714
17501636   size = convert_to_offset_and_size32(&offset, mem_mask);
17511637
17521638   if (offset < 0x008)
1753      res = ide_controller_read(device, 0, offset & 7, size);
1639      res = ide->ide_controller_read(0, offset & 7, size);
17541640   if (offset >= 0x008 && offset < 0x010)
1755      res = ide_controller_read(device, 1, offset & 7, size);
1641      res = ide->ide_controller_read(1, offset & 7, size);
17561642
17571643   return res << ((offset & 3) * 8);
17581644}
r18713r18714
17621648{
17631649   int size;
17641650
1651   ide_controller_device *ide = (ide_controller_device *) device;
1652
17651653   offset *= 4;
17661654   size = convert_to_offset_and_size32(&offset, mem_mask);
17671655   data = data >> ((offset & 3) * 8);
17681656
17691657   if (offset < 0x008)
1770      ide_controller_write(device, 0, offset & 7, size, data);
1658      ide->ide_controller_write(0, offset & 7, size, data);
17711659   if (offset >= 0x008 && offset < 0x010)
1772      ide_controller_write(device, 1, offset & 7, size, data);
1660      ide->ide_controller_write(1, offset & 7, size, data);
17731661}
17741662
17751663READ32_DEVICE_HANDLER( ide_bus_master32_r )
17761664{
17771665   int size;
17781666
1667   ide_controller_device *ide = (ide_controller_device *) device;
1668
17791669   offset *= 4;
17801670   size = convert_to_offset_and_size32(&offset, mem_mask);
17811671
1782   return ide_bus_master_read(device, offset, size) << ((offset & 3) * 8);
1672   return ide->ide_bus_master_read(offset, size) << ((offset & 3) * 8);
17831673}
17841674
17851675
r18713r18714
17871677{
17881678   int size;
17891679
1680   ide_controller_device *ide = (ide_controller_device *) device;
1681
17901682   offset *= 4;
17911683   size = convert_to_offset_and_size32(&offset, mem_mask);
17921684
1793   ide_bus_master_write(device, offset, size, data >> ((offset & 3) * 8));
1685   ide->ide_bus_master_write(offset, size, data >> ((offset & 3) * 8));
17941686}
17951687
17961688
r18713r18714
18221714   ide_controller_w(device, offset, size, data >> ((offset & 1) * 8));
18231715}
18241716
1717SLOT_INTERFACE_START(ide_image_devices)
1718   SLOT_INTERFACE("hdd", IDE_HARDDISK_IMAGE)
1719SLOT_INTERFACE_END
18251720
1721SLOT_INTERFACE_START(ide_devices)
1722   SLOT_INTERFACE("hdd", IDE_HARDDISK)
1723SLOT_INTERFACE_END
18261724
1827/***************************************************************************
1828    DEVICE INTERFACE
1829***************************************************************************/
1725const device_type IDE_CONTROLLER = &device_creator<ide_controller_device>;
18301726
1831/*-------------------------------------------------
1832    device start callback
1833-------------------------------------------------*/
1834
1835static DEVICE_START( ide_controller )
1727ide_controller_device::ide_controller_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
1728   device_t(mconfig, IDE_CONTROLLER, "IDE Controller", tag, owner, clock),
1729   master_password(NULL),
1730   user_password(NULL),
1731   m_irq_handler(*this),
1732   bmcpu(NULL),
1733   bmspace(0)
18361734{
1837   ide_state *ide = get_safe_token(device);
1838   const ide_config *config;
1735}
18391736
1840   /* validate some basic stuff */
1841   assert(device != NULL);
1842   assert(device->static_config() != NULL);
1737//-------------------------------------------------
1738//  device_start - device-specific startup
1739//-------------------------------------------------
18431740
1844   /* store a pointer back to the device */
1845   ide->device = device;
1741void ide_controller_device::device_start()
1742{
1743   m_irq_handler.resolve_safe();
18461744
18471745   /* set MAME harddisk handle */
1848   config = (const ide_config *)device->static_config();
1746   drive[0].slot = owner()->subdevice<ide_slot_device>("drive_0");
1747   drive[1].slot = owner()->subdevice<ide_slot_device>("drive_1");
18491748
1850   ide->drive[0].slot = device->owner()->subdevice<ide_slot_device>("drive_0");
1851   ide->drive[1].slot = device->owner()->subdevice<ide_slot_device>("drive_1");
1852
18531749   /* find the bus master space */
1854   if (config->bmcpu != NULL)
1750   if (bmcpu != NULL)
18551751   {
1856      device_t *bmtarget = device->machine().device(config->bmcpu);
1752      device_t *bmtarget = machine().device(bmcpu);
18571753      if (bmtarget == NULL)
1858         throw emu_fatalerror("IDE controller '%s' bus master target '%s' doesn't exist!", device->tag(), config->bmcpu);
1754         throw emu_fatalerror("IDE controller '%s' bus master target '%s' doesn't exist!", tag(), bmcpu);
18591755      device_memory_interface *memory;
18601756      if (!bmtarget->interface(memory))
1861         throw emu_fatalerror("IDE controller '%s' bus master target '%s' has no memory!", device->tag(), config->bmcpu);
1862      ide->dma_space = &memory->space(config->bmspace);
1863      ide->dma_address_xor = (ide->dma_space->endianness() == ENDIANNESS_LITTLE) ? 0 : 3;
1757         throw emu_fatalerror("IDE controller '%s' bus master target '%s' has no memory!", tag(), bmcpu);
1758      dma_space = &memory->space(bmspace);
1759      dma_address_xor = (dma_space->endianness() == ENDIANNESS_LITTLE) ? 0 : 3;
18641760   }
18651761
18661762   /* create a timer for timing status */
1867   ide->last_status_timer = device->machine().scheduler().timer_alloc(FUNC_NULL);
1868   ide->reset_timer = device->machine().scheduler().timer_alloc(FUNC(reset_callback), (void *)device);
1763   last_status_timer = machine().scheduler().timer_alloc(FUNC_NULL);
1764   reset_timer = machine().scheduler().timer_alloc(FUNC(reset_callback), this);
18691765
18701766   /* register ide states */
1871   device->save_item(NAME(ide->adapter_control));
1872   device->save_item(NAME(ide->status));
1873   device->save_item(NAME(ide->error));
1874   device->save_item(NAME(ide->command));
1875   device->save_item(NAME(ide->interrupt_pending));
1876   device->save_item(NAME(ide->precomp_offset));
1767   save_item(NAME(adapter_control));
1768   save_item(NAME(status));
1769   save_item(NAME(error));
1770   save_item(NAME(command));
1771   save_item(NAME(interrupt_pending));
1772   save_item(NAME(precomp_offset));
18771773
1878   device->save_item(NAME(ide->buffer));
1879   //device->save_item(NAME(ide->features));
1880   device->save_item(NAME(ide->buffer_offset));
1881   device->save_item(NAME(ide->sector_count));
1774   save_item(NAME(buffer));
1775   //save_item(NAME(features));
1776   save_item(NAME(buffer_offset));
1777   save_item(NAME(sector_count));
18821778
1883   device->save_item(NAME(ide->block_count));
1884   device->save_item(NAME(ide->sectors_until_int));
1779   save_item(NAME(block_count));
1780   save_item(NAME(sectors_until_int));
18851781
1886   device->save_item(NAME(ide->dma_active));
1887   device->save_item(NAME(ide->dma_last_buffer));
1888   device->save_item(NAME(ide->dma_address));
1889   device->save_item(NAME(ide->dma_descriptor));
1890   device->save_item(NAME(ide->dma_bytes_left));
1782   save_item(NAME(dma_active));
1783   save_item(NAME(dma_last_buffer));
1784   save_item(NAME(dma_address));
1785   save_item(NAME(dma_descriptor));
1786   save_item(NAME(dma_bytes_left));
18911787
1892   device->save_item(NAME(ide->bus_master_command));
1893   device->save_item(NAME(ide->bus_master_status));
1894   device->save_item(NAME(ide->bus_master_descriptor));
1788   save_item(NAME(bus_master_command));
1789   save_item(NAME(bus_master_status));
1790   save_item(NAME(bus_master_descriptor));
18951791
1896   //device->save_item(NAME(ide->cur_cylinder));
1897   //device->save_item(NAME(ide->cur_sector));
1898   //device->save_item(NAME(ide->cur_head));
1899   //device->save_item(NAME(ide->cur_head_reg));
1792   //save_item(NAME(cur_cylinder));
1793   //save_item(NAME(cur_sector));
1794   //save_item(NAME(cur_head));
1795   //save_item(NAME(cur_head_reg));
19001796
1901   //device->save_item(NAME(ide->cur_lba));
1797   //save_item(NAME(cur_lba));
19021798
1903   //device->save_item(NAME(ide->num_cylinders));
1904   //device->save_item(NAME(ide->num_sectors));
1905   //device->save_item(NAME(ide->num_heads));
1799   //save_item(NAME(num_cylinders));
1800   //save_item(NAME(num_sectors));
1801   //save_item(NAME(num_heads));
19061802
1907   device->save_item(NAME(ide->config_unknown));
1908   device->save_item(NAME(ide->config_register));
1909   device->save_item(NAME(ide->config_register_num));
1803   save_item(NAME(config_unknown));
1804   save_item(NAME(config_register));
1805   save_item(NAME(config_register_num));
19101806
1911   device->save_item(NAME(ide->master_password_enable));
1912   device->save_item(NAME(ide->user_password_enable));
1807   save_item(NAME(master_password_enable));
1808   save_item(NAME(user_password_enable));
19131809
1914   device->save_item(NAME(ide->gnetreadlock));
1810   save_item(NAME(gnetreadlock));
19151811}
19161812
1917/*-------------------------------------------------
1918    device reset callback
1919-------------------------------------------------*/
1920
1921static DEVICE_RESET( ide_controller )
1922{
1923   ide_state *ide = get_safe_token(device);
1924   LOG(("IDE controller reset performed\n"));
1925   /* reset the drive state */
1926   ide->cur_drive = 0;
1927   ide->status = IDE_STATUS_DRIVE_READY | IDE_STATUS_SEEK_COMPLETE;
1928   ide->error = IDE_ERROR_DEFAULT;
1929   ide->buffer_offset = 0;
1930   ide->gnetreadlock = 0;
1931   ide->master_password_enable = (ide->master_password != NULL);
1932   ide->user_password_enable = (ide->user_password != NULL);
1933   clear_interrupt(ide);
1934}
1935
1936SLOT_INTERFACE_START(ide_image_devices)
1937   SLOT_INTERFACE("hdd", IDE_HARDDISK_IMAGE)
1938SLOT_INTERFACE_END
1939
1940SLOT_INTERFACE_START(ide_devices)
1941   SLOT_INTERFACE("hdd", IDE_HARDDISK)
1942SLOT_INTERFACE_END
1943
1944const device_type IDE_CONTROLLER = &device_creator<ide_controller_device>;
1945
1946ide_controller_device::ide_controller_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
1947   : device_t(mconfig, IDE_CONTROLLER, "IDE Controller", tag, owner, clock)
1948{
1949   m_token = global_alloc_clear(ide_state);
1950}
1951
19521813//-------------------------------------------------
1953//  device_config_complete - perform any
1954//  operations now that the configuration is
1955//  complete
1956//-------------------------------------------------
1957
1958void ide_controller_device::device_config_complete()
1959{
1960}
1961
1962//-------------------------------------------------
1963//  device_start - device-specific startup
1964//-------------------------------------------------
1965
1966void ide_controller_device::device_start()
1967{
1968   DEVICE_START_NAME( ide_controller )(this);
1969}
1970
1971//-------------------------------------------------
19721814//  device_reset - device-specific reset
19731815//-------------------------------------------------
19741816
19751817void ide_controller_device::device_reset()
19761818{
1977   DEVICE_RESET_NAME( ide_controller )(this);
1819   LOG(("IDE controller reset performed\n"));
1820   /* reset the drive state */
1821   cur_drive = 0;
1822   status = IDE_STATUS_DRIVE_READY | IDE_STATUS_SEEK_COMPLETE;
1823   error = IDE_ERROR_DEFAULT;
1824   buffer_offset = 0;
1825   gnetreadlock = 0;
1826   master_password_enable = (master_password != NULL);
1827   user_password_enable = (user_password != NULL);
1828   clear_interrupt();
19781829}
19791830
19801831
trunk/src/emu/machine/idectrl.h
r18713r18714
130130    TYPE DEFINITIONS
131131***************************************************************************/
132132
133struct ide_config
134{
135   void   (*interrupt)(device_t *device, int state);
136   const char *bmcpu;      /* name of bus master CPU */
137   UINT32 bmspace;         /* address space of bus master transfer */
138};
133#define MCFG_IDE_CONTROLLER_IRQ_HANDLER(_devcb) \
134   devcb = &ide_controller_device::set_irq_handler(*device, DEVCB2_##_devcb);
139135
136#define MCFG_IDE_CONTROLLER_BUS_MASTER(bmcpu, bmspace) \
137   ide_controller_device::set_bus_master(*device, bmcpu, bmspace);
140138
141139SLOT_INTERFACE_EXTERN(ide_devices);
142140SLOT_INTERFACE_EXTERN(ide_image_devices);
r18713r18714
145143    DEVICE CONFIGURATION MACROS
146144***************************************************************************/
147145
148#define MCFG_IDE_CONTROLLER_ADD(_tag, _config, _slotintf, _master, _slave, _fixed) \
146#define MCFG_IDE_CONTROLLER_ADD(_tag, _slotintf, _master, _slave, _fixed) \
149147   MCFG_DEVICE_ADD(_tag, IDE_CONTROLLER, 0) \
150   MCFG_DEVICE_CONFIG(_config) \
151148   MCFG_IDE_SLOT_ADD("drive_0", _slotintf, _master, NULL, _fixed) \
152149   MCFG_IDE_SLOT_ADD("drive_1", _slotintf, _slave, NULL, _fixed) \
150   MCFG_DEVICE_MODIFY(_tag)
153151
154152#define MCFG_IDE_SLOT_ADD(_tag, _slot_intf, _def_slot, _def_inp, _fixed) \
155153   MCFG_DEVICE_ADD(_tag, IDE_SLOT, 0) \
156   MCFG_DEVICE_SLOT_INTERFACE(_slot_intf, _def_slot, _def_inp, _fixed) \
154   MCFG_DEVICE_SLOT_INTERFACE(_slot_intf, _def_slot, _def_inp, _fixed)
157155
158156/***************************************************************************
159157    FUNCTION PROTOTYPES
160158***************************************************************************/
161159
162UINT8 *ide_get_features(device_t *device, int drive);
163
164void ide_set_master_password(device_t *device, const UINT8 *password);
165void ide_set_user_password(device_t *device, const UINT8 *password);
166
167void ide_set_gnet_readlock(device_t *device, const UINT8 onoff);
168
169160int ide_bus_r(device_t *config, int select, int offset);
170161void ide_bus_w(device_t *config, int select, int offset, int data);
171162
r18713r18714
182173DECLARE_READ16_DEVICE_HANDLER( ide_controller16_r );
183174DECLARE_WRITE16_DEVICE_HANDLER( ide_controller16_w );
184175
176/***************************************************************************
177    TYPE DEFINITIONS
178***************************************************************************/
179struct ide_device
180{
181   UINT16         cur_cylinder;
182   UINT8         cur_sector;
183   UINT8         cur_head;
184   UINT8         cur_head_reg;
185   UINT32         cur_lba;
186   ide_slot_device *slot;
187};
185188
189#define IDE_CONFIG_REGISTERS            0x10
190
186191/* ----- device interface ----- */
187192
188193class ide_controller_device : public device_t
189194{
190195public:
191196   ide_controller_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
192   ~ide_controller_device() { global_free(m_token); }
193197
194   // access to legacy token
195   void *token() const { assert(m_token != NULL); return m_token; }
198   // static configuration helpers
199   template<class _Object> static devcb2_base &set_irq_handler(device_t &device, _Object object) { return downcast<ide_controller_device &>(device).m_irq_handler.set_callback(object); }
200   static void set_bus_master(device_t &device, const char *bmcpu, UINT32 bmspace) {ide_controller_device &ide = downcast<ide_controller_device &>(device); ide.bmcpu = bmcpu; ide.bmspace = bmspace; }
201
202   UINT8 *ide_get_features(int drive);
203   void ide_set_gnet_readlock(const UINT8 onoff);
204   void ide_set_master_password(const UINT8 *password);
205   void ide_set_user_password(const UINT8 *password);
206
207   UINT32 ide_controller_read(int bank, offs_t offset, int size);
208   void ide_controller_write(int bank, offs_t offset, int size, UINT32 data);
209   UINT32 ide_bus_master_read(offs_t offset, int size);
210   void ide_bus_master_write(offs_t offset, int size, UINT32 data);
211   void signal_interrupt();
212   void clear_interrupt();
213   void read_sector_done();
214   void write_sector_done();
215
216   UINT8         status;
217
196218protected:
197219   // device-level overrides
198   virtual void device_config_complete();
199220   virtual void device_start();
200221   virtual void device_reset();
222
201223private:
202   // internal state
203   void *m_token;
224   void signal_delayed_interrupt(attotime time, int buffer_ready);
225   UINT32 lba_address();
226   void next_sector();
227   void security_error();
228   void continue_read();
229   void write_buffer_to_dma();
230   void read_first_sector();
231   void read_next_sector();
232   void read_buffer_from_dma();
233   void handle_command(UINT8 _command);
234   void continue_write();
235
236   UINT8         adapter_control;
237   UINT8         error;
238   UINT8         command;
239   UINT8         interrupt_pending;
240   UINT8         precomp_offset;
241
242   UINT8         buffer[IDE_DISK_SECTOR_SIZE];
243   UINT16         buffer_offset;
244   UINT16         sector_count;
245
246   UINT16         block_count;
247   UINT16         sectors_until_int;
248   UINT8         verify_only;
249
250   UINT8         dma_active;
251   address_space *dma_space;
252   UINT8         dma_address_xor;
253   UINT8         dma_last_buffer;
254   offs_t         dma_address;
255   offs_t         dma_descriptor;
256   UINT32         dma_bytes_left;
257
258   UINT8         bus_master_command;
259   UINT8         bus_master_status;
260   UINT32         bus_master_descriptor;
261
262   UINT8         config_unknown;
263   UINT8         config_register[IDE_CONFIG_REGISTERS];
264   UINT8         config_register_num;
265
266   emu_timer *      last_status_timer;
267   emu_timer *      reset_timer;
268
269   UINT8         master_password_enable;
270   UINT8         user_password_enable;
271   const UINT8 *   master_password;
272   const UINT8 *   user_password;
273
274   UINT8         gnetreadlock;
275
276   UINT8         cur_drive;
277   ide_device      drive[2];
278
279   devcb2_write_line m_irq_handler;
280   const char *bmcpu;
281   UINT32 bmspace;
204282};
205283
206284extern const device_type IDE_CONTROLLER;
trunk/src/mess/machine/isa_ide.c
r18713r18714
3030   ide_controller16_w(device, space, 0x3f6/2 + offset, data, 0x00ff);
3131}
3232
33static void ide_interrupt(device_t *device, int state)
33WRITE_LINE_MEMBER(isa16_ide_device::ide_interrupt)
3434{
35   isa16_ide_device *ide  = downcast<isa16_ide_device *>(device->owner());
36   if (ide->is_primary()) {
37      ide->m_isa->irq14_w(state);
38   } else {
39      ide->m_isa->irq15_w(state);
35   if (is_primary())
36   {
37      m_isa->irq14_w(state);
4038   }
39   else
40   {
41      m_isa->irq15_w(state);
42   }
4143}
4244
43static const ide_config ide_intf =
44{
45   ide_interrupt,
46   NULL,
47   0
48};
49
5045static MACHINE_CONFIG_FRAGMENT( ide )
51   MCFG_IDE_CONTROLLER_ADD("ide", ide_intf, ide_image_devices, "hdd", "hdd", false)
46   MCFG_IDE_CONTROLLER_ADD("ide", ide_image_devices, "hdd", "hdd", false)
47   MCFG_IDE_CONTROLLER_IRQ_HANDLER(DEVWRITELINE(DEVICE_SELF_OWNER, isa16_ide_device, ide_interrupt))
5248MACHINE_CONFIG_END
5349
5450static INPUT_PORTS_START( ide )
trunk/src/mess/machine/isa_ide.h
r18713r18714
1212
1313// ======================> isa16_ide_device
1414
15class isa16_ide_device :
16      public device_t,
17      public device_isa16_card_interface
15class isa16_ide_device : public device_t,
16   public device_isa16_card_interface
1817{
1918public:
20      // construction/destruction
21        isa16_ide_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
19   // construction/destruction
20   isa16_ide_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
2221
23      // optional information overrides
24      virtual machine_config_constructor device_mconfig_additions() const;
25      virtual ioport_constructor device_input_ports() const;
22   // optional information overrides
23   virtual machine_config_constructor device_mconfig_additions() const;
24   virtual ioport_constructor device_input_ports() const;
2625
27      bool is_primary() { return m_is_primary; }
26   bool is_primary() { return m_is_primary; }
27   DECLARE_WRITE_LINE_MEMBER(ide_interrupt);
28
2829protected:
29        // device-level overrides
30        virtual void device_start();
31        virtual void device_reset();
32      virtual void device_config_complete() { m_shortname = "isa_ide"; }
30   // device-level overrides
31   virtual void device_start();
32   virtual void device_reset();
33   virtual void device_config_complete() { m_shortname = "isa_ide"; }
34
3335private:
34        // internal state
35      bool m_is_primary;
36   // internal state
37   bool m_is_primary;
3638};
3739
3840
trunk/src/mess/machine/ti99/tn_ide.c
r18713r18714
278278    ti99_ide_interrupt()
279279    IDE interrupt callback
280280*/
281static void ide_interrupt_callback(device_t *device, int state)
281WRITE_LINE_MEMBER(nouspikel_ide_interface_device::ide_interrupt_callback)
282282{
283   nouspikel_ide_interface_device *card  = downcast<nouspikel_ide_interface_device *>(device->owner());
284   card->m_ide_irq = state;
285   if (card->m_cru_register & cru_reg_int_en)
286      card->do_inta(state);
283   m_ide_irq = state;
284   if (m_cru_register & cru_reg_int_en)
285      do_inta(state);
287286}
288287
289288/*
r18713r18714
334333   DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER, nouspikel_ide_interface_device, clock_interrupt_callback)
335334};
336335
337static const ide_config ide_intf =
338{
339   ide_interrupt_callback,
340   NULL,
341   0
342};
343
344336MACHINE_CONFIG_FRAGMENT( tn_ide )
345337   MCFG_RTC65271_ADD( "ide_rtc", ide_rtc_cfg )
346   MCFG_IDE_CONTROLLER_ADD( "ide", ide_intf, ide_image_devices, "hdd", NULL, false)  // see idectrl.c
338   MCFG_IDE_CONTROLLER_ADD( "ide", ide_image_devices, "hdd", NULL, false)  // see idectrl.c
339   MCFG_IDE_CONTROLLER_IRQ_HANDLER(DEVWRITELINE(DEVICE_SELF_OWNER, nouspikel_ide_interface_device, ide_interrupt_callback))
347340//  MCFG_IDE_CONTROLLER_REGIONS(":peribox:idehd0:drive", NULL)
348341MACHINE_CONFIG_END
349342
trunk/src/mess/machine/ti99/tn_ide.h
r18713r18714
3333   int    m_cru_register;
3434
3535   DECLARE_WRITE_LINE_MEMBER(clock_interrupt_callback);
36   DECLARE_WRITE_LINE_MEMBER(ide_interrupt_callback);
3637
3738protected:
3839   void device_start(void);
trunk/src/mess/machine/kc_d004.c
r18713r18714
8686   MCFG_FLOPPY_DRIVE_ADD(UPD765_TAG ":3", kc_d004_floppies, "525hd", 0, kc_d004_floppy_formats)
8787MACHINE_CONFIG_END
8888
89static const ide_config ide_intf =
90{
91   NULL,
92   NULL,
93   0
94};
95
9689static MACHINE_CONFIG_FRAGMENT(kc_d004_gide)
9790   MCFG_FRAGMENT_ADD(kc_d004)
9891
9992   MCFG_CPU_MODIFY(Z80_TAG)
10093   MCFG_CPU_IO_MAP(kc_d004_gide_io)
10194
102   MCFG_IDE_CONTROLLER_ADD(IDE_TAG, ide_intf, ide_image_devices, "hdd", "hdd", false)
95   MCFG_IDE_CONTROLLER_ADD(IDE_TAG, ide_image_devices, "hdd", "hdd", false)
10396MACHINE_CONFIG_END
10497
10598
trunk/src/mess/machine/c64_ide64.c
r18713r18714
4545//-------------------------------------------------
4646//  MACHINE_CONFIG_FRAGMENT( c64_ide64 )
4747//-------------------------------------------------
48static const ide_config ide_intf =
49{
50   NULL,
51   NULL,
52   0
53};
54
5548static MACHINE_CONFIG_FRAGMENT( c64_ide64 )
5649   MCFG_ATMEL_29C010_ADD(AT29C010A_TAG)
5750   MCFG_DS1302_ADD(DS1302_TAG, XTAL_32_768kHz)
5851
59   MCFG_IDE_CONTROLLER_ADD(IDE_TAG, ide_intf, ide_image_devices, "hdd", "hdd", false)
52   MCFG_IDE_CONTROLLER_ADD(IDE_TAG, ide_image_devices, "hdd", "hdd", false)
6053MACHINE_CONFIG_END
6154
6255
trunk/src/mess/machine/bebox.c
r18713r18714
555555}
556556
557557
558void bebox_ide_interrupt(device_t *device, int state)
558WRITE_LINE_MEMBER(bebox_state::bebox_ide_interrupt)
559559{
560   bebox_state *drvstate = device->machine().driver_data<bebox_state>();
561   bebox_set_irq_bit(device->machine(), 7, state);
562   if ( drvstate->m_devices.pic8259_master ) {
563      pic8259_ir6_w(drvstate->m_devices.pic8259_master, state);
560   bebox_set_irq_bit(machine(), 7, state);
561   if ( m_devices.pic8259_master ) {
562      pic8259_ir6_w(m_devices.pic8259_master, state);
564563   }
565564}
566565
trunk/src/mess/machine/a2cffa.c
r18713r18714
3131#define CFFA2_ROM_REGION  "cffa2_rom"
3232#define CFFA2_IDE_TAG     "cffa2_ide"
3333
34static const ide_config ide_intf =
35{
36   NULL,
37   NULL,
38   0
39};
40
4134MACHINE_CONFIG_FRAGMENT( cffa2 )
42    MCFG_IDE_CONTROLLER_ADD(CFFA2_IDE_TAG, ide_intf, ide_image_devices, "hdd", "hdd", false)
35    MCFG_IDE_CONTROLLER_ADD(CFFA2_IDE_TAG, ide_image_devices, "hdd", "hdd", false)
4336MACHINE_CONFIG_END
4437
4538ROM_START( cffa2 )
trunk/src/mess/includes/bebox.h
r18713r18714
8282   DECLARE_WRITE64_MEMBER(scsi53c810_w);
8383   DECLARE_READ64_MEMBER(bb_slave_64be_r);
8484
85   DECLARE_WRITE_LINE_MEMBER(bebox_ide_interrupt);
86
8587   void fdc_interrupt(bool state);
8688   void fdc_dma_drq(bool state);
8789};
r18713r18714
99101extern const ins8250_interface bebox_uart_inteface_2;
100102extern const ins8250_interface bebox_uart_inteface_3;
101103
102void bebox_ide_interrupt(device_t *device, int state);
103104void bebox_set_irq_bit(running_machine &machine, unsigned int interrupt_bit, int val);
104105
105106UINT32 scsi53c810_pci_read(device_t *busdevice, device_t *device, int function, int offset, UINT32 mem_mask);
trunk/src/mess/drivers/bebox.c
r18713r18714
152152   SLOT_INTERFACE("cirrus", CIRRUS)
153153SLOT_INTERFACE_END
154154
155static const ide_config ide_intf =
156{
157   bebox_ide_interrupt,
158   NULL,
159   0
160};
161
162155static MACHINE_CONFIG_START( bebox, bebox_state )
163156   /* basic machine hardware */
164157   MCFG_CPU_ADD("ppc1", PPC603, 66000000)   /* 66 MHz */
r18713r18714
199192   MCFG_SCSIDEV_ADD("scsi:cdrom", SCSICD, SCSI_ID_3)
200193   MCFG_LSI53C810_ADD( "scsi:lsi53c810", lsi53c810_intf)
201194
202   MCFG_IDE_CONTROLLER_ADD( "ide", ide_intf, ide_image_devices, "hdd", NULL, false )   /* FIXME */
195   MCFG_IDE_CONTROLLER_ADD( "ide", ide_image_devices, "hdd", NULL, false )   /* FIXME */
196   MCFG_IDE_CONTROLLER_IRQ_HANDLER(DEVWRITELINE(DEVICE_SELF_OWNER, bebox_state, bebox_ide_interrupt))
203197
204198   /* pci */
205199   MCFG_PCI_BUS_ADD("pcibus", 0)

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