Previous 199869 Revisions Next

r18694 Wednesday 24th October, 2012 at 19:52:23 UTC by hap
small update on interrupts
[src/mame/drivers]namcos23.c

trunk/src/mame/drivers/namcos23.c
r18693r18694
12381238#define S23_HSYNC      (16666150)
12391239#define S23_MODECLOCK   (130205)
12401240
1241#define MAIN_VBLANK_IRQ   1
1242#define MAIN_C361_IRQ   2
1243#define MAIN_SUBCPU_IRQ   4
1244#define MAIN_C435_IRQ   8
1245#define MAIN_C422_IRQ   16
1246
12411247enum { MODEL, FLUSH };
12421248
12431249struct namcos23_render_entry {
r18693r18694
13541360   tilemap_t *m_bgtilemap;
13551361   UINT8 m_jvssense;
13561362   INT32 m_has_jvsio;
1363   UINT32 m_main_irqcause;
13571364   bool m_ctl_vbl_active;
13581365   UINT8 m_ctl_led;
13591366   UINT16 m_ctl_inp_buffer[2];
r18693r18694
13971404   UINT8 m_im_wr;
13981405   UINT8 m_s23_tssio_port_4;
13991406
1407   void update_main_interrupts(UINT32 cause);
1408
14001409   DECLARE_WRITE32_MEMBER(namcos23_textram_w);
14011410   DECLARE_WRITE32_MEMBER(s23_txtchar_w);
14021411   DECLARE_WRITE32_MEMBER(namcos23_paletteram_w);
r18693r18694
14551464};
14561465
14571466
1467void namcos23_state::update_main_interrupts(UINT32 cause)
1468{
1469   UINT32 changed = cause ^ m_main_irqcause;
1470   m_main_irqcause = cause;
1471   
1472   // level 2: vblank
1473   if (changed & MAIN_VBLANK_IRQ)
1474      m_maincpu->set_input_line(MIPS3_IRQ0, (cause & MAIN_VBLANK_IRQ) ? ASSERT_LINE : CLEAR_LINE);
14581475
1476   // level 3: C361/subcpu
1477   if (changed & (MAIN_C361_IRQ | MAIN_SUBCPU_IRQ))
1478      m_maincpu->set_input_line(MIPS3_IRQ1, (cause & (MAIN_C361_IRQ | MAIN_SUBCPU_IRQ)) ? ASSERT_LINE : CLEAR_LINE);
1479
1480   // level 4: C435
1481   if (changed & MAIN_C435_IRQ)
1482      m_maincpu->set_input_line(MIPS3_IRQ2, (cause & MAIN_C435_IRQ) ? ASSERT_LINE : CLEAR_LINE);
1483
1484   // level 5: C422
1485   if (changed & MAIN_C422_IRQ)
1486      m_maincpu->set_input_line(MIPS3_IRQ3, (cause & MAIN_C422_IRQ) ? ASSERT_LINE : CLEAR_LINE);
1487}
1488
14591489static UINT16 nthword( const UINT32 *pSource, int offs )
14601490{
14611491   pSource += offs/2;
r18693r18694
15821612         break;
15831613      case 7:
15841614         logerror("c417_w: ack IRQ 2 (%x)\n", data);
1585         m_maincpu->set_input_line(MIPS3_IRQ2, CLEAR_LINE);
1615         update_main_interrupts(m_main_irqcause & ~MAIN_C435_IRQ);
15861616         break;
15871617      default:
15881618         logerror("c417_w %x, %04x @ %04x (%08x, %08x)\n", offset, data, mem_mask, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
r18693r18694
17541784         if(m_ctl_vbl_active)
17551785         {
17561786            m_ctl_vbl_active = false;
1757            space.device().execute().set_input_line(MIPS3_IRQ0, CLEAR_LINE);
1787            update_main_interrupts(m_main_irqcause & ~MAIN_VBLANK_IRQ);
17581788         }
17591789         break;
17601790
r18693r18694
17931823
17941824   if (c361.scanline != 0x1ff)
17951825   {
1796      m_maincpu->set_input_line(MIPS3_IRQ1, ASSERT_LINE);
1826      // need to do a partial update here, but doesn't work properly yet
1827      update_main_interrupts(m_main_irqcause | MAIN_C361_IRQ);
17971828
17981829      // TC2 indicates it's probably one-shot since it resets it each VBL...
17991830      //c361.timer->adjust(machine().primary_screen->time_until_pos(c361.scanline));
18001831   }
1832   else
1833      update_main_interrupts(m_main_irqcause & ~MAIN_C361_IRQ);
18011834}
18021835
18031836WRITE16_MEMBER(namcos23_state::s23_c361_w)
r18693r18694
18301863   switch (offset)
18311864   {
18321865      case 5:
1833         m_maincpu->set_input_line(MIPS3_IRQ1, CLEAR_LINE);
1866         update_main_interrupts(m_main_irqcause & ~MAIN_C361_IRQ);
18341867         return machine().primary_screen->vblank() ? 0x1ff : machine().primary_screen->vpos();
18351868      case 6:
1836         return machine().primary_screen->vblank();
1869         update_main_interrupts(m_main_irqcause & ~MAIN_C361_IRQ);
1870         return machine().primary_screen->vblank() ? ~0 : 0;
18371871   }
18381872
18391873   logerror("c361_r %x @ %04x (%08x, %08x)\n", offset, mem_mask, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31));
r18693r18694
18551889         if (data == 0xfffb)
18561890         {
18571891            logerror("c422_w: raise IRQ 3\n");
1858            m_maincpu->set_input_line(MIPS3_IRQ3, ASSERT_LINE);
1892            update_main_interrupts(m_main_irqcause | MAIN_C422_IRQ);
18591893         }
18601894         else if (data == 0x000f)
18611895         {
18621896            logerror("c422_w: ack IRQ 3\n");
1863            m_maincpu->set_input_line(MIPS3_IRQ3, CLEAR_LINE);
1897            update_main_interrupts(m_main_irqcause & ~MAIN_C422_IRQ);
18641898         }
18651899         break;
18661900
r18693r18694
18791913   {
18801914      case 2:
18811915         // subcpu irq ack
1882         m_maincpu->set_input_line(MIPS3_IRQ1, CLEAR_LINE);
1916         update_main_interrupts(m_main_irqcause & ~MAIN_SUBCPU_IRQ);
18831917         break;
18841918
18851919      case 5:
r18693r18694
24932527   if(!m_ctl_vbl_active)
24942528   {
24952529      m_ctl_vbl_active = true;
2496      device.execute().set_input_line(MIPS3_IRQ0, ASSERT_LINE);
2530      update_main_interrupts(m_main_irqcause | MAIN_VBLANK_IRQ);
24972531   }
24982532
24992533   render.cur = !render.cur;
r18693r18694
26292663{
26302664   if  ((mem_mask == 0xffff) && (data == 0x3170))
26312665   {
2632      m_maincpu->set_input_line(MIPS3_IRQ1, ASSERT_LINE);
2666      update_main_interrupts(m_main_irqcause | MAIN_SUBCPU_IRQ);
26332667   }
26342668   else
26352669   {
r18693r18694
31723206
31733207   m_mi_rd = m_mi_wr = m_im_rd = m_im_wr = 0;
31743208   m_jvssense = 1;
3209   m_main_irqcause = ~0;
31753210   m_ctl_vbl_active = false;
31763211   m_s23_lastpB = 0x50;
31773212   m_s23_setstate = 0;

Previous 199869 Revisions Next

© 1997-2024 The MAME Team