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r18266 Wednesday 3rd October, 2012 at 14:54:09 UTC by Miodrag Milanović
Some DC cleanup (no whatsnew)

[src/mame/includes]	dc.h
[src/mess]	mess.mak
[src/mess/drivers]	dc.c dccons.c*
[src/mess/includes]	dccons.h*

trunk/src/mame/includes/dc.h

r18265	r18266
89	89	DECLARE_DRIVER_INIT(vf4evoct);
90	90	DECLARE_DRIVER_INIT(naomi_mp);
91	91	DECLARE_DRIVER_INIT(mvsc2);
92		DECLARE_DRIVER_INIT(dc);
93		DECLARE_DRIVER_INIT(dcus);
94		DECLARE_DRIVER_INIT(dcjp);
95	92	virtual void machine_start();
96	93	virtual void machine_reset();
97	94	virtual void video_start();

trunk/src/mess/drivers/dc.c

r18265	r18266
1		/*
2
3		dc.c - Sega Dreamcast driver
4		by R. Belmont
5
6		SH-4 @ 200 MHz
7		ARM7DI @ 2.8223 MHz (no T or M extensions)
8		PowerVR 3D video
9		AICA audio
10		GD-ROM drive (modified ATAPI interface)
11
12		NTSC/N  NTSC/I   PAL/N   PAL/I   VGA
13		(x/240) (x/480) (x/240)  (x/480) (640x480)
14		VTOTAL   262     524      312     624    524
15		HTOTAL   857     857      863     863    857
16
17		PCLKs = 26917135 (NTSC 480 @ 59.94), 26944080 (VGA 480 @ 60.0), 13458568 (NTSC 240 @ 59.94),
18		25925600 (PAL 480 @ 50.00), 13462800 (PAL 240 @ 50.00)
19
20		*/
21
22		#include "emu.h"
23		#include "cpu/arm7/arm7.h"
24		#include "cpu/sh4/sh4.h"
25		#include "cpu/arm7/arm7core.h"
26		#include "sound/aica.h"
27		#include "includes/dc.h"
28		#include "imagedev/chd_cd.h"
29		#include "machine/maple-dc.h"
30		#include "machine/dc-ctrl.h"
31		#include "machine/gdrom.h"
32
33		#define CPU_CLOCK (200000000)
34
35		// things from mess/machine/dc.c
36		void dreamcast_atapi_init(running_machine &machine);
37		void dreamcast_atapi_reset(running_machine &machine);
38		extern DECLARE_READ64_HANDLER( dc_mess_gdrom_r );
39		extern DECLARE_WRITE64_HANDLER( dc_mess_gdrom_w );
40		extern DECLARE_READ64_HANDLER( dc_mess_g1_ctrl_r );
41		extern DECLARE_WRITE64_HANDLER( dc_mess_g1_ctrl_w );
42
43		static READ64_HANDLER( dcus_idle_skip_r )
44		{
45		if (space.device().safe_pc()==0xc0ba52a)
46		space.device().execute().spin_until_time(attotime::from_usec(2500));
47		//  device_spinuntil_int(&space.device());
48
49		return space.machine().driver_data<dc_state>()->dc_ram[0x2303b0/8];
50		}
51
52		static READ64_HANDLER( dcjp_idle_skip_r )
53		{
54		if (space.device().safe_pc()==0xc0bac62)
55		space.device().execute().spin_until_time(attotime::from_usec(2500));
56		//  device_spinuntil_int(&space.device());
57
58		return space.machine().driver_data<dc_state>()->dc_ram[0x2302f8/8];
59		}
60
61		DRIVER_INIT_MEMBER(dc_state,dc)
62		{
63		dreamcast_atapi_init(machine());
64		}
65
66		DRIVER_INIT_MEMBER(dc_state,dcus)
67		{
68		machine().device("maincpu")->memory().space(AS_PROGRAM).install_legacy_read_handler(0xc2303b0, 0xc2303b7, FUNC(dcus_idle_skip_r));
69
70		DRIVER_INIT_CALL(dc);
71		}
72
73		DRIVER_INIT_MEMBER(dc_state,dcjp)
74		{
75		machine().device("maincpu")->memory().space(AS_PROGRAM).install_legacy_read_handler(0xc2302f8, 0xc2302ff, FUNC(dcjp_idle_skip_r));
76
77		DRIVER_INIT_CALL(dc);
78		}
79
80		static UINT64 PDTRA, PCTRA;
81		static READ64_HANDLER( dc_pdtra_r )
82		{
83		UINT64 out = PCTRA<<32;
84
85		out |= PDTRA & ~3;
86
87		// if both bits are inputs
88		if (!(PCTRA & 0x5))
89		{
90		out |= 3;
91		}
92
93		// one's input one's output, always pull up both bits
94		if (((PCTRA & 5) == 1) || ((PCTRA & 5) == 4))
95		{
96		if (PDTRA & 3)
97		{
98		out |= 3;
99		}
100		}
101
102		return out;
103		}
104
105		static WRITE64_HANDLER( dc_pdtra_w )
106		{
107		PCTRA = (data>>16) & 0xffff;
108		PDTRA = (data & 0xffff);
109		}
110
111		static READ64_HANDLER( dc_arm_r )
112		{
113		dc_state *state = space.machine().driver_data<dc_state>();
114
115		return *((UINT64 *)state->dc_sound_ram.target()+offset);
116		}
117
118		static WRITE64_HANDLER( dc_arm_w )
119		{
120		dc_state *state = space.machine().driver_data<dc_state>();
121
122		COMBINE_DATA((UINT64 *)state->dc_sound_ram.target() + offset);
123		}
124
125
126		// SB_LMMODE0
127		static WRITE64_HANDLER( ta_texture_directpath0_w )
128		{
129		dc_state *state = space.machine().driver_data<dc_state>();
130
131		int mode = state->pvrctrl_regs[SB_LMMODE0]&1;
132		if (mode&1)
133		{
134		printf("ta_texture_directpath0_w 32-bit access!\n");
135		COMBINE_DATA(&state->dc_framebuffer_ram[offset]);
136		}
137		else
138		{
139		COMBINE_DATA(&state->dc_texture_ram[offset]);
140		}
141		}
142
143		// SB_LMMODE1
144		static WRITE64_HANDLER( ta_texture_directpath1_w )
145		{
146		dc_state *state = space.machine().driver_data<dc_state>();
147
148		int mode = state->pvrctrl_regs[SB_LMMODE1]&1;
149		if (mode&1)
150		{
151		printf("ta_texture_directpath1_w 32-bit access!\n");
152		COMBINE_DATA(&state->dc_framebuffer_ram[offset]);
153		}
154		else
155		{
156		COMBINE_DATA(&state->dc_texture_ram[offset]);
157		}
158		}
159
160		static ADDRESS_MAP_START( dc_map, AS_PROGRAM, 64, dc_state )
161		AM_RANGE(0x00000000, 0x001fffff) AM_ROM   AM_WRITENOP            // BIOS
162		AM_RANGE(0x00200000, 0x0021ffff) AM_ROM AM_REGION("maincpu", 0x200000)   // flash
163		AM_RANGE(0x005f6800, 0x005f69ff) AM_READWRITE_LEGACY(dc_sysctrl_r, dc_sysctrl_w )
164		AM_RANGE(0x005f6c00, 0x005f6cff) AM_DEVICE32( "maple_dc", maple_dc_device, amap, U64(0xffffffffffffffff) )
165		AM_RANGE(0x005f7000, 0x005f70ff) AM_READWRITE_LEGACY(dc_mess_gdrom_r, dc_mess_gdrom_w )
166		AM_RANGE(0x005f7400, 0x005f74ff) AM_READWRITE_LEGACY(dc_mess_g1_ctrl_r, dc_mess_g1_ctrl_w )
167		AM_RANGE(0x005f7800, 0x005f78ff) AM_READWRITE_LEGACY(dc_g2_ctrl_r, dc_g2_ctrl_w )
168		AM_RANGE(0x005f7c00, 0x005f7cff) AM_READWRITE_LEGACY(pvr_ctrl_r, pvr_ctrl_w )
169		AM_RANGE(0x005f8000, 0x005f9fff) AM_READWRITE_LEGACY(pvr_ta_r, pvr_ta_w )
170		AM_RANGE(0x00600000, 0x006007ff) AM_READWRITE_LEGACY(dc_modem_r, dc_modem_w )
171		AM_RANGE(0x00700000, 0x00707fff) AM_READWRITE(dc_aica_reg_r, dc_aica_reg_w )
172		AM_RANGE(0x00710000, 0x0071000f) AM_READWRITE_LEGACY(dc_rtc_r, dc_rtc_w )
173		AM_RANGE(0x00800000, 0x009fffff) AM_READWRITE_LEGACY(dc_arm_r, dc_arm_w )
174
175		/* Area 1 */
176		AM_RANGE(0x04000000, 0x04ffffff) AM_RAM   AM_SHARE("dc_texture_ram")      // texture memory 64 bit access
177		AM_RANGE(0x05000000, 0x05ffffff) AM_RAM AM_SHARE("frameram") // apparently this actually accesses the same memory as the 64-bit texture memory access, but in a different format, keep it apart for now
178
179		/* Area 3 */
180		AM_RANGE(0x0c000000, 0x0cffffff) AM_RAM AM_SHARE("dc_ram")
181		AM_RANGE(0x0d000000, 0x0dffffff) AM_RAM AM_SHARE("dc_ram")// extra ram on Naomi (mirror on DC)
182		AM_RANGE(0x0e000000, 0x0effffff) AM_RAM AM_SHARE("dc_ram")// mirror
183		AM_RANGE(0x0f000000, 0x0fffffff) AM_RAM AM_SHARE("dc_ram")// mirror
184
185		/* Area 4 */
186		AM_RANGE(0x10000000, 0x107fffff) AM_WRITE_LEGACY(ta_fifo_poly_w )
187		AM_RANGE(0x10800000, 0x10ffffff) AM_WRITE_LEGACY(ta_fifo_yuv_w )
188		AM_RANGE(0x11000000, 0x117fffff) AM_WRITE_LEGACY(ta_texture_directpath0_w ) AM_MIRROR(0x00800000)  // access to texture / fraembfufer memory (either 32-bit or 64-bit area depending on SB_LMMODE0 register - cannot be written directly, only through dma / store queue
189
190		AM_RANGE(0x12000000, 0x127fffff) AM_WRITE_LEGACY(ta_fifo_poly_w )
191		AM_RANGE(0x12800000, 0x12ffffff) AM_WRITE_LEGACY(ta_fifo_yuv_w )
192		AM_RANGE(0x13000000, 0x137fffff) AM_WRITE_LEGACY(ta_texture_directpath1_w ) AM_MIRROR(0x00800000) // access to texture / fraembfufer memory (either 32-bit or 64-bit area depending on SB_LMMODE1 register - cannot be written directly, only through dma / store queue
193
194		AM_RANGE(0x8c000000, 0x8cffffff) AM_RAM AM_SHARE("dc_ram")   // another RAM mirror
195
196		AM_RANGE(0xa0000000, 0xa01fffff) AM_ROM AM_REGION("maincpu", 0)
197		ADDRESS_MAP_END
198
199		static ADDRESS_MAP_START( dc_port, AS_IO, 64, dc_state )
200		AM_RANGE(0x00000000, 0x00000007) AM_READWRITE_LEGACY(dc_pdtra_r, dc_pdtra_w )
201		ADDRESS_MAP_END
202
203		static ADDRESS_MAP_START( dc_audio_map, AS_PROGRAM, 32, dc_state )
204		AM_RANGE(0x00000000, 0x001fffff) AM_RAM AM_SHARE("dc_sound_ram")      /* shared with SH-4 */
205		AM_RANGE(0x00800000, 0x00807fff) AM_READWRITE(dc_arm_aica_r, dc_arm_aica_w)
206		ADDRESS_MAP_END
207
208		static MACHINE_RESET( dc_console )
209		{
210		dc_state *state = machine.driver_data<dc_state>();
211
212		device_t *aica = machine.device("aica");
213		state->machine_reset();
214		aica_set_ram_base(aica, state->dc_sound_ram, 2*1024*1024);
215		dreamcast_atapi_reset(machine);
216		}
217
218		static void aica_irq(device_t *device, int irq)
219		{
220		device->machine().device("soundcpu")->execute().set_input_line(ARM7_FIRQ_LINE, irq ? ASSERT_LINE : CLEAR_LINE);
221		}
222
223		static const aica_interface dc_aica_interface =
224		{
225		0,
226		0,
227		aica_irq
228		};
229
230		static const struct sh4_config sh4cpu_config = {  1,  0,  1,  0,  0,  0,  1,  1,  0, CPU_CLOCK };
231
232		static MACHINE_CONFIG_START( dc, dc_state )
233		/* basic machine hardware */
234		MCFG_CPU_ADD("maincpu", SH4LE, CPU_CLOCK)
235		MCFG_CPU_CONFIG(sh4cpu_config)
236		MCFG_CPU_PROGRAM_MAP(dc_map)
237		MCFG_CPU_IO_MAP(dc_port)
238
239		MCFG_CPU_ADD("soundcpu", ARM7, ((XTAL_33_8688MHz*2)/3)/8)   // AICA bus clock is 2/3rds * 33.8688.  ARM7 gets 1 bus cycle out of each 8.
240		MCFG_CPU_PROGRAM_MAP(dc_audio_map)
241
242		MCFG_MACHINE_RESET( dc_console )
243
244		MCFG_MAPLE_DC_ADD( "maple_dc", "maincpu", dc_maple_irq )
245		MCFG_DC_CONTROLLER_ADD("dcctrl0", "maple_dc", 0, "P1:0", "P1:1", "P1:A0", "P1:A1", "P1:A2", "P1:A3", "P1:A4", "P1:A5")
246		MCFG_DC_CONTROLLER_ADD("dcctrl1", "maple_dc", 1, "P2:0", "P2:1", "P2:A0", "P2:A1", "P2:A2", "P2:A3", "P2:A4", "P2:A5")
247		MCFG_DC_CONTROLLER_ADD("dcctrl2", "maple_dc", 2, "P3:0", "P3:1", "P3:A0", "P3:A1", "P3:A2", "P3:A3", "P3:A4", "P3:A5")
248		MCFG_DC_CONTROLLER_ADD("dcctrl3", "maple_dc", 3, "P4:0", "P4:1", "P4:A0", "P4:A1", "P4:A2", "P4:A3", "P4:A4", "P4:A5")
249
250		/* video hardware */
251		MCFG_SCREEN_ADD("screen", RASTER)
252		MCFG_SCREEN_REFRESH_RATE(60)
253		MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500) /* not accurate */)
254		MCFG_SCREEN_SIZE(640, 480)
255		MCFG_SCREEN_VISIBLE_AREA(0, 640-1, 0, 480-1)
256		MCFG_SCREEN_UPDATE_DRIVER(dc_state, screen_update_dc)
257
258		MCFG_PALETTE_LENGTH(0x1000)
259
260
261		MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
262		MCFG_SOUND_ADD("aica", AICA, 0)
263		MCFG_SOUND_CONFIG(dc_aica_interface)
264		MCFG_SOUND_ROUTE(0, "lspeaker", 2.0)
265		MCFG_SOUND_ROUTE(0, "rspeaker", 2.0)
266
267		MCFG_DEVICE_ADD("cdrom", GDROM, 0)
268		MACHINE_CONFIG_END
269
270		ROM_START(dc)
271		ROM_REGION(0x220000, "maincpu", 0)
272		ROM_LOAD( "dc101d_us.bin", 0x000000, 0x200000, CRC(89f2b1a1) SHA1(8951d1bb219ab2ff8583033d2119c899cc81f18c) )   // BIOS
273		ROM_LOAD( "dcus_ntsc.bin", 0x200000, 0x020000, CRC(c611b498) SHA1(94d44d7f9529ec1642ba3771ed3c5f756d5bc872) )   // Flash
274		ROM_END
275
276		ROM_START( dceu )
277		ROM_REGION(0x220000, "maincpu", 0)
278		ROM_LOAD( "dc101d_eu.bin", 0x000000, 0x200000, CRC(a2564fad) SHA1(edc5d3d70a93c935703d26119b37731fd317d2bf) )   // BIOS
279		ROM_LOAD( "dceu_pal.bin", 0x200000, 0x020000, CRC(b7e5aeeb) SHA1(11e02433e13b793ec7ffe0ae2356750bb8a575b4) )   // Flash
280		ROM_END
281
282		ROM_START( dcjp )
283		ROM_REGION(0x220000, "maincpu", 0)
284		ROM_LOAD( "dc1004jp.bin", 0x000000, 0x200000, CRC(5454841f) SHA1(1ea132c0fbbf07ef76789eadc07908045c089bd6) )   // BIOS
285		/* ROM_LOAD( "dcjp_ntsc.bad", 0x200000, 0x020000, BAD_DUMP CRC(307a7035) SHA1(1411423a9d071340ea52c56e19c1aafc4e1309ee) )      // Hacked Flash */
286		ROM_LOAD( "dcjp_ntsc.bin", 0x200000, 0x020000, CRC(5F92BF76) SHA1(BE78B834F512AB2CF3D67B96E377C9F3093FF82A) )  // Flash
287		ROM_END
288
289		ROM_START( dcdev )
290		ROM_REGION(0x220000, "maincpu", 0)
291		ROM_LOAD( "hkt-0120.bin", 0x000000, 0x200000, CRC(2186E0E5) SHA1(6BD18FB83F8FDB56F1941E079580E5DD672A6DAD) )      // BIOS
292		ROM_LOAD( "hkt-0120-flash.bin", 0x200000, 0x020000, CRC(7784C304) SHA1(31EF57F550D8CD13E40263CBC657253089E53034) )   // Flash
293		ROM_END
294
295		ROM_START( dcprt )
296		ROM_REGION(0x220000, "maincpu", 0)
297		ROM_LOAD( "katana-set5-v0.41-98-08-27.bin", 0x000000, 0x200000, CRC(485877bd) SHA1(dc1af1f1248ffa87d57bc5ef2ea41aac95ecfc5e) ) // BIOS
298		ROM_LOAD( "dcjp_ntsc.bin", 0x200000, 0x020000, CRC(5F92BF76) SHA1(BE78B834F512AB2CF3D67B96E377C9F3093FF82A) )  // Flash
299		ROM_END
300
301		static INPUT_PORTS_START( dc )
302		PORT_START("P1:0")
303		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(1)
304		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(1)
305		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(1)
306		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(1)
307		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_START1 )
308		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1)
309		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(1)
310		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(1)
311		PORT_START("P1:1")
312		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_COIN1 )
313		PORT_SERVICE_NO_TOGGLE( 0x40, IP_ACTIVE_LOW )
314		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_SERVICE1 )
315		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
316		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
317		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON4 ) PORT_PLAYER(1)
318		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON5 ) PORT_PLAYER(1)
319		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON6 ) PORT_PLAYER(1)
320
321		PORT_START("P2:0")
322		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(2)
323		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(2)
324		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(2)
325		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(2)
326		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_START2 )
327		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
328		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2)
329		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2)
330		PORT_START("P2:1")
331		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_COIN2 )
332		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
333		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_SERVICE2 )
334		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
335		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
336		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON4 ) PORT_PLAYER(2)
337		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON5 ) PORT_PLAYER(2)
338		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON6 ) PORT_PLAYER(2)
339
340		PORT_START("P3:0")
341		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(3)
342		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(3)
343		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(3)
344		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(3)
345		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_START3 )
346		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(3)
347		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(3)
348		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(3)
349		PORT_START("P3:1")
350		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_COIN3 )
351		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
352		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_SERVICE3 )
353		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
354		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
355		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON4 ) PORT_PLAYER(3)
356		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON5 ) PORT_PLAYER(3)
357		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON6 ) PORT_PLAYER(3)
358
359		PORT_START("P4:0")
360		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(4)
361		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(4)
362		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(4)
363		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(4)
364		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_START4 )
365		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(4)
366		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(4)
367		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(4)
368		PORT_START("P4:1")
369		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_COIN4 )
370		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
371		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_SERVICE4 )
372		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
373		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
374		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON4 ) PORT_PLAYER(4)
375		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON5 ) PORT_PLAYER(4)
376		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON6 ) PORT_PLAYER(4)
377
378		PORT_START("MAMEDEBUG") \
379		PORT_DIPNAME( 0x01, 0x00, "Bilinear Filtering" )
380		PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
381		PORT_DIPSETTING(    0x01, DEF_STR( On ) )
382		INPUT_PORTS_END
383
384
385		/*    YEAR  NAME    PARENT  COMPAT  MACHINE INPUT   INIT      COMPANY FULLNAME */
386		CONS( 1999, dc,     dcjp,   0,      dc,     dc, dc_state,     dcus,   "Sega", "Dreamcast (USA, NTSC)", GAME_NOT_WORKING )
387		CONS( 1998, dcjp,   0,      0,      dc,     dc, dc_state,     dcjp,   "Sega", "Dreamcast (Japan, NTSC)", GAME_NOT_WORKING )
388		CONS( 1999, dceu,   dcjp,   0,      dc,     dc, dc_state,     dcus,   "Sega", "Dreamcast (Europe, PAL)", GAME_NOT_WORKING )
389		CONS( 1998, dcdev,  dcjp,   0,      dc,     dc, dc_state,     dc,     "Sega", "HKT-0120 Sega Dreamcast Development Box", GAME_NOT_WORKING )
390		CONS( 1998, dcprt,  dcjp,   0,      dc,     dc, dc_state,     dcjp,   "Sega", "Katana Set 5 Prototype", GAME_NOT_WORKING )
391

trunk/src/mess/drivers/dccons.c

r0	r18266
	1	/*
	2
	3	dc.c - Sega Dreamcast driver
	4	by R. Belmont
	5
	6	SH-4 @ 200 MHz
	7	ARM7DI @ 2.8223 MHz (no T or M extensions)
	8	PowerVR 3D video
	9	AICA audio
	10	GD-ROM drive (modified ATAPI interface)
	11
	12	NTSC/N  NTSC/I   PAL/N   PAL/I   VGA
	13	(x/240) (x/480) (x/240)  (x/480) (640x480)
	14	VTOTAL   262     524      312     624    524
	15	HTOTAL   857     857      863     863    857
	16
	17	PCLKs = 26917135 (NTSC 480 @ 59.94), 26944080 (VGA 480 @ 60.0), 13458568 (NTSC 240 @ 59.94),
	18	25925600 (PAL 480 @ 50.00), 13462800 (PAL 240 @ 50.00)
	19
	20	*/
	21
	22	#include "emu.h"
	23	#include "cpu/arm7/arm7.h"
	24	#include "cpu/sh4/sh4.h"
	25	#include "cpu/arm7/arm7core.h"
	26	#include "sound/aica.h"
	27	#include "includes/dc.h"
	28	#include "includes/dccons.h"
	29	#include "imagedev/chd_cd.h"
	30	#include "machine/maple-dc.h"
	31	#include "machine/dc-ctrl.h"
	32	#include "machine/gdrom.h"
	33
	34	#define CPU_CLOCK (200000000)
	35
	36	// things from mess/machine/dc.c
	37	void dreamcast_atapi_init(running_machine &machine);
	38	void dreamcast_atapi_reset(running_machine &machine);
	39	extern DECLARE_READ64_HANDLER( dc_mess_gdrom_r );
	40	extern DECLARE_WRITE64_HANDLER( dc_mess_gdrom_w );
	41	extern DECLARE_READ64_HANDLER( dc_mess_g1_ctrl_r );
	42	extern DECLARE_WRITE64_HANDLER( dc_mess_g1_ctrl_w );
	43
	44	READ64_MEMBER(dc_cons_state::dcus_idle_skip_r )
	45	{
	46	if (space.device().safe_pc()==0xc0ba52a)
	47	space.device().execute().spin_until_time(attotime::from_usec(2500));
	48	//  device_spinuntil_int(&space.device());
	49
	50	return dc_ram[0x2303b0/8];
	51	}
	52
	53	READ64_MEMBER(dc_cons_state::dcjp_idle_skip_r )
	54	{
	55	if (space.device().safe_pc()==0xc0bac62)
	56	space.device().execute().spin_until_time(attotime::from_usec(2500));
	57	//  device_spinuntil_int(&space.device());
	58
	59	return dc_ram[0x2302f8/8];
	60	}
	61
	62	DRIVER_INIT_MEMBER(dc_cons_state,dc)
	63	{
	64	dreamcast_atapi_init(machine());
	65	}
	66
	67	DRIVER_INIT_MEMBER(dc_cons_state,dcus)
	68	{
	69	machine().device("maincpu")->memory().space(AS_PROGRAM).install_read_handler(0xc2303b0, 0xc2303b7, read64_delegate(FUNC(dc_cons_state::dcus_idle_skip_r),this));
	70
	71	DRIVER_INIT_CALL(dc);
	72	}
	73
	74	DRIVER_INIT_MEMBER(dc_cons_state,dcjp)
	75	{
	76	machine().device("maincpu")->memory().space(AS_PROGRAM).install_read_handler(0xc2302f8, 0xc2302ff, read64_delegate(FUNC(dc_cons_state::dcjp_idle_skip_r),this));
	77
	78	DRIVER_INIT_CALL(dc);
	79	}
	80
	81	READ64_MEMBER(dc_cons_state::dc_pdtra_r )
	82	{
	83	UINT64 out = PCTRA<<32;
	84
	85	out |= PDTRA & ~3;
	86
	87	// if both bits are inputs
	88	if (!(PCTRA & 0x5))
	89	{
	90	out |= 3;
	91	}
	92
	93	// one's input one's output, always pull up both bits
	94	if (((PCTRA & 5) == 1) || ((PCTRA & 5) == 4))
	95	{
	96	if (PDTRA & 3)
	97	{
	98	out |= 3;
	99	}
	100	}
	101
	102	return out;
	103	}
	104
	105	WRITE64_MEMBER(dc_cons_state::dc_pdtra_w )
	106	{
	107	PCTRA = (data>>16) & 0xffff;
	108	PDTRA = (data & 0xffff);
	109	}
	110
	111	READ64_MEMBER(dc_cons_state::dc_arm_r )
	112	{
	113	return *((UINT64 *)dc_sound_ram.target()+offset);
	114	}
	115
	116	WRITE64_MEMBER(dc_cons_state::dc_arm_w )
	117	{
	118	COMBINE_DATA((UINT64 *)dc_sound_ram.target() + offset);
	119	}
	120
	121
	122	// SB_LMMODE0
	123	WRITE64_MEMBER(dc_cons_state::ta_texture_directpath0_w )
	124	{
	125	int mode = pvrctrl_regs[SB_LMMODE0]&1;
	126	if (mode&1)
	127	{
	128	printf("ta_texture_directpath0_w 32-bit access!\n");
	129	COMBINE_DATA(&dc_framebuffer_ram[offset]);
	130	}
	131	else
	132	{
	133	COMBINE_DATA(&dc_texture_ram[offset]);
	134	}
	135	}
	136
	137	// SB_LMMODE1
	138	WRITE64_MEMBER(dc_cons_state::ta_texture_directpath1_w )
	139	{
	140	int mode = pvrctrl_regs[SB_LMMODE1]&1;
	141	if (mode&1)
	142	{
	143	printf("ta_texture_directpath1_w 32-bit access!\n");
	144	COMBINE_DATA(&dc_framebuffer_ram[offset]);
	145	}
	146	else
	147	{
	148	COMBINE_DATA(&dc_texture_ram[offset]);
	149	}
	150	}
	151
	152	static ADDRESS_MAP_START( dc_map, AS_PROGRAM, 64, dc_cons_state )
	153	AM_RANGE(0x00000000, 0x001fffff) AM_ROM   AM_WRITENOP            // BIOS
	154	AM_RANGE(0x00200000, 0x0021ffff) AM_ROM AM_REGION("maincpu", 0x200000)   // flash
	155	AM_RANGE(0x005f6800, 0x005f69ff) AM_READWRITE_LEGACY(dc_sysctrl_r, dc_sysctrl_w )
	156	AM_RANGE(0x005f6c00, 0x005f6cff) AM_DEVICE32( "maple_dc", maple_dc_device, amap, U64(0xffffffffffffffff) )
	157	AM_RANGE(0x005f7000, 0x005f70ff) AM_READWRITE_LEGACY(dc_mess_gdrom_r, dc_mess_gdrom_w )
	158	AM_RANGE(0x005f7400, 0x005f74ff) AM_READWRITE_LEGACY(dc_mess_g1_ctrl_r, dc_mess_g1_ctrl_w )
	159	AM_RANGE(0x005f7800, 0x005f78ff) AM_READWRITE_LEGACY(dc_g2_ctrl_r, dc_g2_ctrl_w )
	160	AM_RANGE(0x005f7c00, 0x005f7cff) AM_READWRITE_LEGACY(pvr_ctrl_r, pvr_ctrl_w )
	161	AM_RANGE(0x005f8000, 0x005f9fff) AM_READWRITE_LEGACY(pvr_ta_r, pvr_ta_w )
	162	AM_RANGE(0x00600000, 0x006007ff) AM_READWRITE_LEGACY(dc_modem_r, dc_modem_w )
	163	AM_RANGE(0x00700000, 0x00707fff) AM_READWRITE(dc_aica_reg_r, dc_aica_reg_w )
	164	AM_RANGE(0x00710000, 0x0071000f) AM_READWRITE_LEGACY(dc_rtc_r, dc_rtc_w )
	165	AM_RANGE(0x00800000, 0x009fffff) AM_READWRITE(dc_arm_r, dc_arm_w )
	166
	167	/* Area 1 */
	168	AM_RANGE(0x04000000, 0x04ffffff) AM_RAM   AM_SHARE("dc_texture_ram")      // texture memory 64 bit access
	169	AM_RANGE(0x05000000, 0x05ffffff) AM_RAM AM_SHARE("frameram") // apparently this actually accesses the same memory as the 64-bit texture memory access, but in a different format, keep it apart for now
	170
	171	/* Area 3 */
	172	AM_RANGE(0x0c000000, 0x0cffffff) AM_RAM AM_SHARE("dc_ram")
	173	AM_RANGE(0x0d000000, 0x0dffffff) AM_RAM AM_SHARE("dc_ram")// extra ram on Naomi (mirror on DC)
	174	AM_RANGE(0x0e000000, 0x0effffff) AM_RAM AM_SHARE("dc_ram")// mirror
	175	AM_RANGE(0x0f000000, 0x0fffffff) AM_RAM AM_SHARE("dc_ram")// mirror
	176
	177	/* Area 4 */
	178	AM_RANGE(0x10000000, 0x107fffff) AM_WRITE_LEGACY(ta_fifo_poly_w )
	179	AM_RANGE(0x10800000, 0x10ffffff) AM_WRITE_LEGACY(ta_fifo_yuv_w )
	180	AM_RANGE(0x11000000, 0x117fffff) AM_WRITE(ta_texture_directpath0_w ) AM_MIRROR(0x00800000)  // access to texture / fraembfufer memory (either 32-bit or 64-bit area depending on SB_LMMODE0 register - cannot be written directly, only through dma / store queue
	181
	182	AM_RANGE(0x12000000, 0x127fffff) AM_WRITE_LEGACY(ta_fifo_poly_w )
	183	AM_RANGE(0x12800000, 0x12ffffff) AM_WRITE_LEGACY(ta_fifo_yuv_w )
	184	AM_RANGE(0x13000000, 0x137fffff) AM_WRITE(ta_texture_directpath1_w ) AM_MIRROR(0x00800000) // access to texture / fraembfufer memory (either 32-bit or 64-bit area depending on SB_LMMODE1 register - cannot be written directly, only through dma / store queue
	185
	186	AM_RANGE(0x8c000000, 0x8cffffff) AM_RAM AM_SHARE("dc_ram")   // another RAM mirror
	187
	188	AM_RANGE(0xa0000000, 0xa01fffff) AM_ROM AM_REGION("maincpu", 0)
	189	ADDRESS_MAP_END
	190
	191	static ADDRESS_MAP_START( dc_port, AS_IO, 64, dc_cons_state )
	192	AM_RANGE(0x00000000, 0x00000007) AM_READWRITE(dc_pdtra_r, dc_pdtra_w )
	193	ADDRESS_MAP_END
	194
	195	static ADDRESS_MAP_START( dc_audio_map, AS_PROGRAM, 32, dc_cons_state )
	196	AM_RANGE(0x00000000, 0x001fffff) AM_RAM AM_SHARE("dc_sound_ram")      /* shared with SH-4 */
	197	AM_RANGE(0x00800000, 0x00807fff) AM_READWRITE(dc_arm_aica_r, dc_arm_aica_w)
	198	ADDRESS_MAP_END
	199
	200	MACHINE_RESET_MEMBER(dc_cons_state,dc_console)
	201	{
	202	device_t *aica = machine().device("aica");
	203	dc_state::machine_reset();
	204	aica_set_ram_base(aica, dc_sound_ram, 2*1024*1024);
	205	dreamcast_atapi_reset(machine());
	206	}
	207
	208	static void aica_irq(device_t *device, int irq)
	209	{
	210	device->machine().device("soundcpu")->execute().set_input_line(ARM7_FIRQ_LINE, irq ? ASSERT_LINE : CLEAR_LINE);
	211	}
	212
	213	static const aica_interface dc_aica_interface =
	214	{
	215	0,
	216	0,
	217	aica_irq
	218	};
	219
	220	static const struct sh4_config sh4cpu_config = {  1,  0,  1,  0,  0,  0,  1,  1,  0, CPU_CLOCK };
	221
	222	static MACHINE_CONFIG_START( dc, dc_cons_state )
	223	/* basic machine hardware */
	224	MCFG_CPU_ADD("maincpu", SH4LE, CPU_CLOCK)
	225	MCFG_CPU_CONFIG(sh4cpu_config)
	226	MCFG_CPU_PROGRAM_MAP(dc_map)
	227	MCFG_CPU_IO_MAP(dc_port)
	228
	229	MCFG_CPU_ADD("soundcpu", ARM7, ((XTAL_33_8688MHz*2)/3)/8)   // AICA bus clock is 2/3rds * 33.8688.  ARM7 gets 1 bus cycle out of each 8.
	230	MCFG_CPU_PROGRAM_MAP(dc_audio_map)
	231
	232	MCFG_MACHINE_RESET_OVERRIDE(dc_cons_state,dc_console )
	233
	234	MCFG_MAPLE_DC_ADD( "maple_dc", "maincpu", dc_maple_irq )
	235	MCFG_DC_CONTROLLER_ADD("dcctrl0", "maple_dc", 0, "P1:0", "P1:1", "P1:A0", "P1:A1", "P1:A2", "P1:A3", "P1:A4", "P1:A5")
	236	MCFG_DC_CONTROLLER_ADD("dcctrl1", "maple_dc", 1, "P2:0", "P2:1", "P2:A0", "P2:A1", "P2:A2", "P2:A3", "P2:A4", "P2:A5")
	237	MCFG_DC_CONTROLLER_ADD("dcctrl2", "maple_dc", 2, "P3:0", "P3:1", "P3:A0", "P3:A1", "P3:A2", "P3:A3", "P3:A4", "P3:A5")
	238	MCFG_DC_CONTROLLER_ADD("dcctrl3", "maple_dc", 3, "P4:0", "P4:1", "P4:A0", "P4:A1", "P4:A2", "P4:A3", "P4:A4", "P4:A5")
	239
	240	/* video hardware */
	241	MCFG_SCREEN_ADD("screen", RASTER)
	242	MCFG_SCREEN_REFRESH_RATE(60)
	243	MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500) /* not accurate */)
	244	MCFG_SCREEN_SIZE(640, 480)
	245	MCFG_SCREEN_VISIBLE_AREA(0, 640-1, 0, 480-1)
	246	MCFG_SCREEN_UPDATE_DRIVER(dc_cons_state, screen_update_dc)
	247
	248	MCFG_PALETTE_LENGTH(0x1000)
	249
	250
	251	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
	252	MCFG_SOUND_ADD("aica", AICA, 0)
	253	MCFG_SOUND_CONFIG(dc_aica_interface)
	254	MCFG_SOUND_ROUTE(0, "lspeaker", 2.0)
	255	MCFG_SOUND_ROUTE(0, "rspeaker", 2.0)
	256
	257	MCFG_DEVICE_ADD("cdrom", GDROM, 0)
	258	MACHINE_CONFIG_END
	259
	260	ROM_START(dc)
	261	ROM_REGION(0x220000, "maincpu", 0)
	262	ROM_LOAD( "dc101d_us.bin", 0x000000, 0x200000, CRC(89f2b1a1) SHA1(8951d1bb219ab2ff8583033d2119c899cc81f18c) )   // BIOS
	263	ROM_LOAD( "dcus_ntsc.bin", 0x200000, 0x020000, CRC(c611b498) SHA1(94d44d7f9529ec1642ba3771ed3c5f756d5bc872) )   // Flash
	264	ROM_END
	265
	266	ROM_START( dceu )
	267	ROM_REGION(0x220000, "maincpu", 0)
	268	ROM_LOAD( "dc101d_eu.bin", 0x000000, 0x200000, CRC(a2564fad) SHA1(edc5d3d70a93c935703d26119b37731fd317d2bf) )   // BIOS
	269	ROM_LOAD( "dceu_pal.bin", 0x200000, 0x020000, CRC(b7e5aeeb) SHA1(11e02433e13b793ec7ffe0ae2356750bb8a575b4) )   // Flash
	270	ROM_END
	271
	272	ROM_START( dcjp )
	273	ROM_REGION(0x220000, "maincpu", 0)
	274	ROM_LOAD( "dc1004jp.bin", 0x000000, 0x200000, CRC(5454841f) SHA1(1ea132c0fbbf07ef76789eadc07908045c089bd6) )   // BIOS
	275	/* ROM_LOAD( "dcjp_ntsc.bad", 0x200000, 0x020000, BAD_DUMP CRC(307a7035) SHA1(1411423a9d071340ea52c56e19c1aafc4e1309ee) )      // Hacked Flash */
	276	ROM_LOAD( "dcjp_ntsc.bin", 0x200000, 0x020000, CRC(5F92BF76) SHA1(BE78B834F512AB2CF3D67B96E377C9F3093FF82A) )  // Flash
	277	ROM_END
	278
	279	ROM_START( dcdev )
	280	ROM_REGION(0x220000, "maincpu", 0)
	281	ROM_LOAD( "hkt-0120.bin", 0x000000, 0x200000, CRC(2186E0E5) SHA1(6BD18FB83F8FDB56F1941E079580E5DD672A6DAD) )      // BIOS
	282	ROM_LOAD( "hkt-0120-flash.bin", 0x200000, 0x020000, CRC(7784C304) SHA1(31EF57F550D8CD13E40263CBC657253089E53034) )   // Flash
	283	ROM_END
	284
	285	ROM_START( dcprt )
	286	ROM_REGION(0x220000, "maincpu", 0)
	287	ROM_LOAD( "katana-set5-v0.41-98-08-27.bin", 0x000000, 0x200000, CRC(485877bd) SHA1(dc1af1f1248ffa87d57bc5ef2ea41aac95ecfc5e) ) // BIOS
	288	ROM_LOAD( "dcjp_ntsc.bin", 0x200000, 0x020000, CRC(5F92BF76) SHA1(BE78B834F512AB2CF3D67B96E377C9F3093FF82A) )  // Flash
	289	ROM_END
	290
	291	static INPUT_PORTS_START( dc )
	292	PORT_START("P1:0")
	293	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(1)
	294	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(1)
	295	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(1)
	296	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(1)
	297	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_START1 )
	298	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1)
	299	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(1)
	300	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(1)
	301	PORT_START("P1:1")
	302	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_COIN1 )
	303	PORT_SERVICE_NO_TOGGLE( 0x40, IP_ACTIVE_LOW )
	304	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_SERVICE1 )
	305	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
	306	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
	307	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON4 ) PORT_PLAYER(1)
	308	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON5 ) PORT_PLAYER(1)
	309	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON6 ) PORT_PLAYER(1)
	310
	311	PORT_START("P2:0")
	312	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(2)
	313	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(2)
	314	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(2)
	315	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(2)
	316	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_START2 )
	317	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
	318	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2)
	319	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2)
	320	PORT_START("P2:1")
	321	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_COIN2 )
	322	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
	323	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_SERVICE2 )
	324	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
	325	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
	326	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON4 ) PORT_PLAYER(2)
	327	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON5 ) PORT_PLAYER(2)
	328	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON6 ) PORT_PLAYER(2)
	329
	330	PORT_START("P3:0")
	331	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(3)
	332	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(3)
	333	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(3)
	334	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(3)
	335	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_START3 )
	336	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(3)
	337	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(3)
	338	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(3)
	339	PORT_START("P3:1")
	340	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_COIN3 )
	341	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
	342	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_SERVICE3 )
	343	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
	344	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
	345	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON4 ) PORT_PLAYER(3)
	346	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON5 ) PORT_PLAYER(3)
	347	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON6 ) PORT_PLAYER(3)
	348
	349	PORT_START("P4:0")
	350	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(4)
	351	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(4)
	352	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(4)
	353	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(4)
	354	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_START4 )
	355	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(4)
	356	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(4)
	357	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(4)
	358	PORT_START("P4:1")
	359	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_COIN4 )
	360	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
	361	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_SERVICE4 )
	362	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
	363	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
	364	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON4 ) PORT_PLAYER(4)
	365	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON5 ) PORT_PLAYER(4)
	366	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON6 ) PORT_PLAYER(4)
	367
	368	PORT_START("MAMEDEBUG") \
	369	PORT_DIPNAME( 0x01, 0x00, "Bilinear Filtering" )
	370	PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
	371	PORT_DIPSETTING(    0x01, DEF_STR( On ) )
	372	INPUT_PORTS_END
	373
	374
	375	/*    YEAR  NAME    PARENT  COMPAT  MACHINE INPUT   INIT      COMPANY FULLNAME */
	376	CONS( 1999, dc,     dcjp,   0,      dc,     dc, dc_cons_state,     dcus,   "Sega", "Dreamcast (USA, NTSC)", GAME_NOT_WORKING )
	377	CONS( 1998, dcjp,   0,      0,      dc,     dc, dc_cons_state,     dcjp,   "Sega", "Dreamcast (Japan, NTSC)", GAME_NOT_WORKING )
	378	CONS( 1999, dceu,   dcjp,   0,      dc,     dc, dc_cons_state,     dcus,   "Sega", "Dreamcast (Europe, PAL)", GAME_NOT_WORKING )
	379	CONS( 1998, dcdev,  dcjp,   0,      dc,     dc, dc_cons_state,     dc,     "Sega", "HKT-0120 Sega Dreamcast Development Box", GAME_NOT_WORKING )
	380	CONS( 1998, dcprt,  dcjp,   0,      dc,     dc, dc_cons_state,     dcjp,   "Sega", "Katana Set 5 Prototype", GAME_NOT_WORKING )
	381

trunk/src/mess/mess.mak

r18265	r18266
1567	1567	$(MESS_DRIVERS)/sg1000.o   \
1568	1568	$(MAME_MACHINE)/md_cart.o   \
1569	1569	$(MESS_DRIVERS)/megadriv.o  \
1570		$(MESS_DRIVERS)/dc.o      \
	1570	$(MESS_DRIVERS)/dccons.o   \
1571	1571	$(MAME_MACHINE)/gdrom.o    \
1572	1572	$(MESS_MACHINE)/dccons.o   \
1573	1573	$(MESS_MACHINE)/sms.o   \

trunk/src/mess/includes/dccons.h

r0	r18266
	1	class dc_cons_state : public dc_state
	2	{
	3	public:
	4	dc_cons_state(const machine_config &mconfig, device_type type, const char *tag)
	5	: dc_state(mconfig, type, tag)
	6	{ }
	7
	8	DECLARE_DRIVER_INIT(dc);
	9	DECLARE_DRIVER_INIT(dcus);
	10	DECLARE_DRIVER_INIT(dcjp);
	11
	12	DECLARE_READ64_MEMBER(dcus_idle_skip_r);
	13	DECLARE_READ64_MEMBER(dcjp_idle_skip_r);
	14
	15	DECLARE_MACHINE_RESET(dc_console);
	16	DECLARE_READ64_MEMBER(dc_pdtra_r);
	17	DECLARE_WRITE64_MEMBER(dc_pdtra_w);
	18	DECLARE_READ64_MEMBER(dc_arm_r);
	19	DECLARE_WRITE64_MEMBER(dc_arm_w);
	20	DECLARE_WRITE64_MEMBER(ta_texture_directpath0_w);
	21	DECLARE_WRITE64_MEMBER(ta_texture_directpath1_w);
	22	private:
	23	UINT64 PDTRA, PCTRA;
	24
	25	};

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