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r18265 Wednesday 3rd October, 2012 at 14:36:54 UTC by Miodrag Milanović
some cleanup (nw)
[src/mess/drivers]bebox.c dgn_beta.c
[src/mess/includes]bebox.h dgn_beta.h fmtowns.h mbc55x.h
[src/mess/machine]bebox.c dgn_beta.c
[src/mess/video]dgn_beta.c

trunk/src/mess/machine/bebox.c
r18264r18265
194194}
195195
196196
197READ64_HANDLER( bebox_cpu0_imask_r )
197READ64_MEMBER(bebox_state::bebox_cpu0_imask_r )
198198{
199   bebox_state *state = space.machine().driver_data<bebox_state>();
200   return ((UINT64) state->m_cpu_imask[0]) << 32;
199   return ((UINT64) m_cpu_imask[0]) << 32;
201200}
202201
203READ64_HANDLER( bebox_cpu1_imask_r )
202READ64_MEMBER(bebox_state::bebox_cpu1_imask_r )
204203{
205   bebox_state *state = space.machine().driver_data<bebox_state>();
206   return ((UINT64) state->m_cpu_imask[1]) << 32;
204   return ((UINT64) m_cpu_imask[1]) << 32;
207205}
208206
209READ64_HANDLER( bebox_interrupt_sources_r )
207READ64_MEMBER(bebox_state::bebox_interrupt_sources_r )
210208{
211   bebox_state *state = space.machine().driver_data<bebox_state>();
212   return ((UINT64) state->m_interrupts) << 32;
209   return ((UINT64) m_interrupts) << 32;
213210}
214211
215WRITE64_HANDLER( bebox_cpu0_imask_w )
212WRITE64_MEMBER(bebox_state::bebox_cpu0_imask_w )
216213{
217   bebox_state *state = space.machine().driver_data<bebox_state>();
218   UINT32 old_imask = state->m_cpu_imask[0];
214   UINT32 old_imask = m_cpu_imask[0];
219215
220   bebox_mbreg32_w(&state->m_cpu_imask[0], data, mem_mask);
216   bebox_mbreg32_w(&m_cpu_imask[0], data, mem_mask);
221217
222   if (old_imask != state->m_cpu_imask[0])
218   if (old_imask != m_cpu_imask[0])
223219   {
224220      if (LOG_CPUIMASK)
225221      {
226222         logerror("BeBox CPU #0 pc=0x%08X imask=0x%08x\n",
227            (unsigned) space.device().safe_pc( ), state->m_cpu_imask[0]);
223            (unsigned) space.device().safe_pc( ), m_cpu_imask[0]);
228224      }
229225      bebox_update_interrupts(space.machine());
230226   }
231227}
232228
233WRITE64_HANDLER( bebox_cpu1_imask_w )
234{
235   bebox_state *state = space.machine().driver_data<bebox_state>();
236   UINT32 old_imask = state->m_cpu_imask[1];
229WRITE64_MEMBER(bebox_state::bebox_cpu1_imask_w )
230{   
231   UINT32 old_imask = m_cpu_imask[1];
237232
238   bebox_mbreg32_w(&state->m_cpu_imask[1], data, mem_mask);
233   bebox_mbreg32_w(&m_cpu_imask[1], data, mem_mask);
239234
240   if (old_imask != state->m_cpu_imask[1])
235   if (old_imask != m_cpu_imask[1])
241236   {
242237      if (LOG_CPUIMASK)
243238      {
244239         logerror("BeBox CPU #1 pc=0x%08X imask=0x%08x\n",
245            (unsigned) space.device() .safe_pc( ), state->m_cpu_imask[1]);
240            (unsigned) space.device() .safe_pc( ), m_cpu_imask[1]);
246241      }
247242      bebox_update_interrupts(space.machine());
248243   }
249244}
250245
251READ64_HANDLER( bebox_crossproc_interrupts_r )
246READ64_MEMBER(bebox_state::bebox_crossproc_interrupts_r )
252247{
253   bebox_state *state = space.machine().driver_data<bebox_state>();
254248   UINT32 result;
255   result = state->m_crossproc_interrupts;
249   result = m_crossproc_interrupts;
256250
257251   /* return a different result depending on which CPU is accessing this handler */
258252   if (&space != &space.machine().device("ppc1")->memory().space(AS_PROGRAM))
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263257   return ((UINT64) result) << 32;
264258}
265259
266WRITE64_HANDLER( bebox_crossproc_interrupts_w )
260WRITE64_MEMBER(bebox_state::bebox_crossproc_interrupts_w )
267261{
268   bebox_state *state = space.machine().driver_data<bebox_state>();
269262   static const struct
270263   {
271264      UINT32 mask;
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280273      { 0x04000000, 1, 0, 0/*PPC_INPUT_LINE_TLBISYNC*/ }
281274   };
282275   int i, line;
283   UINT32 old_crossproc_interrupts = state->m_crossproc_interrupts;
276   UINT32 old_crossproc_interrupts = m_crossproc_interrupts;
284277   static const char *const cputags[] = { "ppc1", "ppc2" };
285278
286   bebox_mbreg32_w(&state->m_crossproc_interrupts, data, mem_mask);
279   bebox_mbreg32_w(&m_crossproc_interrupts, data, mem_mask);
287280
288281   for (i = 0; i < ARRAY_LENGTH(crossproc_map); i++)
289282   {
290      if ((old_crossproc_interrupts ^ state->m_crossproc_interrupts) & crossproc_map[i].mask)
283      if ((old_crossproc_interrupts ^ m_crossproc_interrupts) & crossproc_map[i].mask)
291284      {
292         if (state->m_crossproc_interrupts & crossproc_map[i].mask)
285         if (m_crossproc_interrupts & crossproc_map[i].mask)
293286            line = crossproc_map[i].active_high ? ASSERT_LINE : CLEAR_LINE;
294287         else
295288            line = crossproc_map[i].active_high ? CLEAR_LINE : ASSERT_LINE;
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308301   }
309302}
310303
311WRITE64_HANDLER( bebox_processor_resets_w )
304WRITE64_MEMBER(bebox_state::bebox_processor_resets_w )
312305{
313306   UINT8 b = (UINT8) (data >> 56);
314307
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505498 *
506499 *************************************/
507500
508READ64_HANDLER( bebox_interrupt_ack_r )
501READ64_MEMBER(bebox_state::bebox_interrupt_ack_r )
509502{
510   bebox_state *state = space.machine().driver_data<bebox_state>();
511503   int result;
512   result = pic8259_acknowledge( state->m_devices.pic8259_master );
504   result = pic8259_acknowledge( m_devices.pic8259_master );
513505   bebox_set_irq_bit(space.machine(), 5, 0);   /* HACK */
514506   return ((UINT64) result) << 56;
515507}
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566558   return machine.device("ide");
567559}
568560
569READ8_HANDLER( bebox_800001F0_r ) { return ide_controller_r(ide_device(space.machine()), offset + 0x1F0, 1); }
570WRITE8_HANDLER( bebox_800001F0_w ) { ide_controller_w(ide_device(space.machine()), offset + 0x1F0, 1, data); }
561READ8_MEMBER(bebox_state::bebox_800001F0_r ) { return ide_controller_r(ide_device(space.machine()), offset + 0x1F0, 1); }
562WRITE8_MEMBER(bebox_state::bebox_800001F0_w ) { ide_controller_w(ide_device(space.machine()), offset + 0x1F0, 1, data); }
571563
572READ64_HANDLER( bebox_800003F0_r )
564READ64_MEMBER(bebox_state::bebox_800003F0_r )
573565{
574566   UINT64 result = read64be_with_read8_handler(pc_fdc_r, space, offset, mem_mask | 0xFFFF);
575567
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588580}
589581
590582
591WRITE64_HANDLER( bebox_800003F0_w )
583WRITE64_MEMBER(bebox_state::bebox_800003F0_w )
592584{
593585   write64be_with_write8_handler(pc_fdc_w, space, offset, data, mem_mask | 0xFFFF);
594586
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616608 *
617609 *************************************/
618610/*
619static READ64_HANDLER( bebox_video_r )
611static READ64_MEMBER(bebox_state::bebox_video_r )
620612{
621613   UINT64 result = 0;
622614   mem_mask = FLIPENDIAN_INT64(mem_mask);
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640632}
641633
642634
643static WRITE64_HANDLER( bebox_video_w )
635static WRITE64_MEMBER(bebox_state::bebox_video_w )
644636{
645637   data = FLIPENDIAN_INT64(data);
646638   mem_mask = FLIPENDIAN_INT64(mem_mask);
r18264r18265
669661 *************************************/
670662
671663
672READ8_HANDLER(bebox_page_r)
673{
674   bebox_state *state = space.machine().driver_data<bebox_state>();
675   UINT8 data = state->m_at_pages[offset % 0x10];
664READ8_MEMBER(bebox_state::bebox_page_r)
665{   
666   UINT8 data = m_at_pages[offset % 0x10];
676667
677668   switch(offset % 8)
678669   {
679670      case 1:
680         data = state->m_dma_offset[(offset / 8) & 1][2];
671         data = m_dma_offset[(offset / 8) & 1][2];
681672         break;
682673      case 2:
683         data = state->m_dma_offset[(offset / 8) & 1][3];
674         data = m_dma_offset[(offset / 8) & 1][3];
684675         break;
685676      case 3:
686         data = state->m_dma_offset[(offset / 8) & 1][1];
677         data = m_dma_offset[(offset / 8) & 1][1];
687678         break;
688679      case 7:
689         data = state->m_dma_offset[(offset / 8) & 1][0];
680         data = m_dma_offset[(offset / 8) & 1][0];
690681         break;
691682   }
692683   return data;
693684}
694685
695686
696WRITE8_HANDLER(bebox_page_w)
697{
698   bebox_state *state = space.machine().driver_data<bebox_state>();
699   state->m_at_pages[offset % 0x10] = data;
687WRITE8_MEMBER(bebox_state::bebox_page_w)
688{   
689   m_at_pages[offset % 0x10] = data;
700690
701691   switch(offset % 8)
702692   {
703693      case 1:
704         state->m_dma_offset[(offset / 8) & 1][2] &= 0xFF00;
705         state->m_dma_offset[(offset / 8) & 1][2] |= ((UINT16 ) data) << 0;
694         m_dma_offset[(offset / 8) & 1][2] &= 0xFF00;
695         m_dma_offset[(offset / 8) & 1][2] |= ((UINT16 ) data) << 0;
706696         break;
707697      case 2:
708         state->m_dma_offset[(offset / 8) & 1][3] &= 0xFF00;
709         state->m_dma_offset[(offset / 8) & 1][3] |= ((UINT16 ) data) << 0;
698         m_dma_offset[(offset / 8) & 1][3] &= 0xFF00;
699         m_dma_offset[(offset / 8) & 1][3] |= ((UINT16 ) data) << 0;
710700         break;
711701      case 3:
712         state->m_dma_offset[(offset / 8) & 1][1] &= 0xFF00;
713         state->m_dma_offset[(offset / 8) & 1][1] |= ((UINT16 ) data) << 0;
702         m_dma_offset[(offset / 8) & 1][1] &= 0xFF00;
703         m_dma_offset[(offset / 8) & 1][1] |= ((UINT16 ) data) << 0;
714704         break;
715705      case 7:
716         state->m_dma_offset[(offset / 8) & 1][0] &= 0xFF00;
717         state->m_dma_offset[(offset / 8) & 1][0] |= ((UINT16 ) data) << 0;
706         m_dma_offset[(offset / 8) & 1][0] &= 0xFF00;
707         m_dma_offset[(offset / 8) & 1][0] |= ((UINT16 ) data) << 0;
718708         break;
719709   }
720710}
721711
722712
723WRITE8_HANDLER(bebox_80000480_w)
724{
725   bebox_state *state = space.machine().driver_data<bebox_state>();
713WRITE8_MEMBER(bebox_state::bebox_80000480_w)
714{   
726715   switch(offset % 8)
727716   {
728717      case 1:
729         state->m_dma_offset[(offset / 8) & 1][2] &= 0x00FF;
730         state->m_dma_offset[(offset / 8) & 1][2] |= ((UINT16 ) data) << 8;
718         m_dma_offset[(offset / 8) & 1][2] &= 0x00FF;
719         m_dma_offset[(offset / 8) & 1][2] |= ((UINT16 ) data) << 8;
731720         break;
732721      case 2:
733         state->m_dma_offset[(offset / 8) & 1][3] &= 0x00FF;
734         state->m_dma_offset[(offset / 8) & 1][3] |= ((UINT16 ) data) << 8;
722         m_dma_offset[(offset / 8) & 1][3] &= 0x00FF;
723         m_dma_offset[(offset / 8) & 1][3] |= ((UINT16 ) data) << 8;
735724         break;
736725      case 3:
737         state->m_dma_offset[(offset / 8) & 1][1] &= 0x00FF;
738         state->m_dma_offset[(offset / 8) & 1][1] |= ((UINT16 ) data) << 8;
726         m_dma_offset[(offset / 8) & 1][1] &= 0x00FF;
727         m_dma_offset[(offset / 8) & 1][1] |= ((UINT16 ) data) << 8;
739728         break;
740729      case 7:
741         state->m_dma_offset[(offset / 8) & 1][0] &= 0x00FF;
742         state->m_dma_offset[(offset / 8) & 1][0] |= ((UINT16 ) data) << 8;
730         m_dma_offset[(offset / 8) & 1][0] &= 0x00FF;
731         m_dma_offset[(offset / 8) & 1][0] |= ((UINT16 ) data) << 8;
743732         break;
744733   }
745734}
746735
747736
748READ8_HANDLER(bebox_80000480_r)
737READ8_MEMBER(bebox_state::bebox_80000480_r)
749738{
750739   fatalerror("NYI\n");
751740}
r18264r18265
760749}
761750
762751
763static READ8_HANDLER( bebox_dma_read_byte )
752READ8_MEMBER(bebox_state::bebox_dma_read_byte )
764753{
765   bebox_state *state = space.machine().driver_data<bebox_state>();
766   offs_t page_offset = (((offs_t) state->m_dma_offset[0][state->m_dma_channel]) << 16)
754   address_space& prog_space = machine().device<cpu_device>("ppc1")->space(AS_PROGRAM); // get the right address space
755   offs_t page_offset = (((offs_t) m_dma_offset[0][m_dma_channel]) << 16)
767756      & 0x7FFF0000;
768   return space.read_byte(page_offset + offset);
757   return prog_space.read_byte(page_offset + offset);
769758}
770759
771760
772static WRITE8_HANDLER( bebox_dma_write_byte )
761WRITE8_MEMBER(bebox_state::bebox_dma_write_byte )
773762{
774   bebox_state *state = space.machine().driver_data<bebox_state>();
775   offs_t page_offset = (((offs_t) state->m_dma_offset[0][state->m_dma_channel]) << 16)
763   address_space& prog_space = machine().device<cpu_device>("ppc1")->space(AS_PROGRAM); // get the right address space
764   offs_t page_offset = (((offs_t) m_dma_offset[0][m_dma_channel]) << 16)
776765      & 0x7FFF0000;
777   space.write_byte(page_offset + offset, data);
766   prog_space.write_byte(page_offset + offset, data);
778767}
779768
780769
r18264r18265
808797{
809798   DEVCB_DRIVER_LINE_MEMBER(bebox_state,bebox_dma_hrq_changed),
810799   DEVCB_DRIVER_LINE_MEMBER(bebox_state,bebox_dma8237_out_eop),
811   DEVCB_MEMORY_HANDLER("ppc1", PROGRAM, bebox_dma_read_byte),
812   DEVCB_MEMORY_HANDLER("ppc1", PROGRAM, bebox_dma_write_byte),
800   DEVCB_DRIVER_MEMBER(bebox_state, bebox_dma_read_byte),
801   DEVCB_DRIVER_MEMBER(bebox_state, bebox_dma_write_byte),
813802   { DEVCB_NULL, DEVCB_NULL, DEVCB_DRIVER_MEMBER(bebox_state,bebox_dma8237_fdc_dack_r), DEVCB_NULL },
814803   { DEVCB_NULL, DEVCB_NULL, DEVCB_DRIVER_MEMBER(bebox_state,bebox_dma8237_fdc_dack_w), DEVCB_NULL },
815804   { DEVCB_DRIVER_LINE_MEMBER(bebox_state,pc_dack0_w), DEVCB_DRIVER_LINE_MEMBER(bebox_state,pc_dack1_w), DEVCB_DRIVER_LINE_MEMBER(bebox_state,pc_dack2_w), DEVCB_DRIVER_LINE_MEMBER(bebox_state,pc_dack3_w) }
r18264r18265
869858 *
870859 *************************************/
871860
872READ8_HANDLER( bebox_flash_r )
861READ8_MEMBER(bebox_state::bebox_flash_r )
873862{
874863   fujitsu_29f016a_device *flash = space.machine().device<fujitsu_29f016a_device>("flash");
875864   offset = (offset & ~7) | (7 - (offset & 7));
r18264r18265
877866}
878867
879868
880WRITE8_HANDLER( bebox_flash_w )
869WRITE8_MEMBER(bebox_state::bebox_flash_w )
881870{
882871   fujitsu_29f016a_device *flash = space.machine().device<fujitsu_29f016a_device>("flash");
883872   offset = (offset & ~7) | (7 - (offset & 7));
r18264r18265
920909 *************************************/
921910
922911
923static READ64_HANDLER( scsi53c810_r )
924{
925   bebox_state *state = space.machine().driver_data<bebox_state>();
912READ64_MEMBER(bebox_state::scsi53c810_r )
913{   
926914   int reg = offset*8;
927915   UINT64 r = 0;
928916   if (!(mem_mask & U64(0xff00000000000000))) {
929      r |= (UINT64)state->m_lsi53c810->lsi53c810_reg_r(reg+0) << 56;
917      r |= (UINT64)m_lsi53c810->lsi53c810_reg_r(reg+0) << 56;
930918   }
931919   if (!(mem_mask & U64(0x00ff000000000000))) {
932      r |= (UINT64)state->m_lsi53c810->lsi53c810_reg_r(reg+1) << 48;
920      r |= (UINT64)m_lsi53c810->lsi53c810_reg_r(reg+1) << 48;
933921   }
934922   if (!(mem_mask & U64(0x0000ff0000000000))) {
935      r |= (UINT64)state->m_lsi53c810->lsi53c810_reg_r(reg+2) << 40;
923      r |= (UINT64)m_lsi53c810->lsi53c810_reg_r(reg+2) << 40;
936924   }
937925   if (!(mem_mask & U64(0x000000ff00000000))) {
938      r |= (UINT64)state->m_lsi53c810->lsi53c810_reg_r(reg+3) << 32;
926      r |= (UINT64)m_lsi53c810->lsi53c810_reg_r(reg+3) << 32;
939927   }
940928   if (!(mem_mask & U64(0x00000000ff000000))) {
941      r |= (UINT64)state->m_lsi53c810->lsi53c810_reg_r(reg+4) << 24;
929      r |= (UINT64)m_lsi53c810->lsi53c810_reg_r(reg+4) << 24;
942930   }
943931   if (!(mem_mask & U64(0x0000000000ff0000))) {
944      r |= (UINT64)state->m_lsi53c810->lsi53c810_reg_r(reg+5) << 16;
932      r |= (UINT64)m_lsi53c810->lsi53c810_reg_r(reg+5) << 16;
945933   }
946934   if (!(mem_mask & U64(0x000000000000ff00))) {
947      r |= (UINT64)state->m_lsi53c810->lsi53c810_reg_r(reg+6) << 8;
935      r |= (UINT64)m_lsi53c810->lsi53c810_reg_r(reg+6) << 8;
948936   }
949937   if (!(mem_mask & U64(0x00000000000000ff))) {
950      r |= (UINT64)state->m_lsi53c810->lsi53c810_reg_r(reg+7) << 0;
938      r |= (UINT64)m_lsi53c810->lsi53c810_reg_r(reg+7) << 0;
951939   }
952940
953941   return r;
954942}
955943
956944
957static WRITE64_HANDLER( scsi53c810_w )
958{
959   bebox_state *state = space.machine().driver_data<bebox_state>();
945WRITE64_MEMBER(bebox_state::scsi53c810_w )
946{   
960947   int reg = offset*8;
961948   if (!(mem_mask & U64(0xff00000000000000))) {
962      state->m_lsi53c810->lsi53c810_reg_w(reg+0, data >> 56);
949      m_lsi53c810->lsi53c810_reg_w(reg+0, data >> 56);
963950   }
964951   if (!(mem_mask & U64(0x00ff000000000000))) {
965      state->m_lsi53c810->lsi53c810_reg_w(reg+1, data >> 48);
952      m_lsi53c810->lsi53c810_reg_w(reg+1, data >> 48);
966953   }
967954   if (!(mem_mask & U64(0x0000ff0000000000))) {
968      state->m_lsi53c810->lsi53c810_reg_w(reg+2, data >> 40);
955      m_lsi53c810->lsi53c810_reg_w(reg+2, data >> 40);
969956   }
970957   if (!(mem_mask & U64(0x000000ff00000000))) {
971      state->m_lsi53c810->lsi53c810_reg_w(reg+3, data >> 32);
958      m_lsi53c810->lsi53c810_reg_w(reg+3, data >> 32);
972959   }
973960   if (!(mem_mask & U64(0x00000000ff000000))) {
974      state->m_lsi53c810->lsi53c810_reg_w(reg+4, data >> 24);
961      m_lsi53c810->lsi53c810_reg_w(reg+4, data >> 24);
975962   }
976963   if (!(mem_mask & U64(0x0000000000ff0000))) {
977      state->m_lsi53c810->lsi53c810_reg_w(reg+5, data >> 16);
964      m_lsi53c810->lsi53c810_reg_w(reg+5, data >> 16);
978965   }
979966   if (!(mem_mask & U64(0x000000000000ff00))) {
980      state->m_lsi53c810->lsi53c810_reg_w(reg+6, data >> 8);
967      m_lsi53c810->lsi53c810_reg_w(reg+6, data >> 8);
981968   }
982969   if (!(mem_mask & U64(0x00000000000000ff))) {
983      state->m_lsi53c810->lsi53c810_reg_w(reg+7, data >> 0);
970      m_lsi53c810->lsi53c810_reg_w(reg+7, data >> 0);
984971   }
985972}
986973
r18264r18265
10401027                  address_space &space = device->machine().device("ppc1")->memory().space(AS_PROGRAM);
10411028
10421029                  addr = (state->m_scsi53c810_data[5] | 0xC0000000) & ~0xFF;
1043                  space.install_legacy_read_handler(addr, addr + 0xFF, FUNC(scsi53c810_r));
1044                  space.install_legacy_write_handler(addr, addr + 0xFF, FUNC(scsi53c810_w));
1030                  space.install_readwrite_handler(addr, addr + 0xFF, read64_delegate(FUNC(bebox_state::scsi53c810_r),state), write64_delegate(FUNC(bebox_state::scsi53c810_w),state));
10451031               }
10461032            }
10471033            break;
trunk/src/mess/machine/dgn_beta.c
r18264r18265
326326}
327327
328328// Return the value of a page register
329READ8_HANDLER( dgn_beta_page_r )
329READ8_MEMBER(dgn_beta_state::dgn_beta_page_r)
330330{
331   dgn_beta_state *state = space.machine().driver_data<dgn_beta_state>();
332   return state->m_PageRegs[state->m_PIATaskReg][offset].value;
331   return m_PageRegs[m_PIATaskReg][offset].value;
333332}
334333
335334// Write to a page register, writes to the register, and then checks to see
336335// if memory banking is active, if it is, it calls UpdateBanks, to actually
337336// setup the mappings.
338337
339WRITE8_HANDLER( dgn_beta_page_w )
338WRITE8_MEMBER(dgn_beta_state::dgn_beta_page_w )
340339{
341   dgn_beta_state *state = space.machine().driver_data<dgn_beta_state>();
342   state->m_PageRegs[state->m_PIATaskReg][offset].value=data;
340   m_PageRegs[m_PIATaskReg][offset].value=data;
343341
344   LOG_PAGE_WRITE(("PageRegWrite : task=$%X  offset=$%X value=$%X\n",state->m_PIATaskReg,offset,data));
342   LOG_PAGE_WRITE(("PageRegWrite : task=$%X  offset=$%X value=$%X\n",m_PIATaskReg,offset,data));
345343
346   if (state->m_EnableMapRegs)
344   if (m_EnableMapRegs)
347345   {
348      UpdateBanks(space.machine(), offset,offset);
346      UpdateBanks(machine(), offset,offset);
349347      if (offset==15)
350         UpdateBanks(space.machine(), offset+1,offset+1);
348         UpdateBanks(machine(), offset+1,offset+1);
351349   }
352350}
353351
r18264r18265
887885   {FLOPPY_0, FLOPPY_1, FLOPPY_2, FLOPPY_3}
888886};
889887
890READ8_HANDLER(dgnbeta_wd2797_r)
888READ8_MEMBER(dgn_beta_state::dgnbeta_wd2797_r)
891889{
892890   int result = 0;
893891   device_t *fdc = space.machine().device(FDC_TAG);
r18264r18265
914912   return result;
915913}
916914
917WRITE8_HANDLER(dgnbeta_wd2797_w)
915WRITE8_MEMBER(dgn_beta_state::dgnbeta_wd2797_w)
918916{
919   dgn_beta_state *state = space.machine().driver_data<dgn_beta_state>();
920917   device_t *fdc = space.machine().device(FDC_TAG);
921918
922    state->m_wd2797_written=1;
919    m_wd2797_written=1;
923920
924921    switch(offset & 0x3)
925922   {
trunk/src/mess/includes/bebox.h
r18264r18265
5454   DECLARE_WRITE_LINE_MEMBER(pc_dack2_w);
5555   DECLARE_WRITE_LINE_MEMBER(pc_dack3_w);
5656   DECLARE_WRITE_LINE_MEMBER(bebox_timer0_w);
57   DECLARE_READ64_MEMBER(bebox_cpu0_imask_r);
58   DECLARE_READ64_MEMBER(bebox_cpu1_imask_r);
59   DECLARE_READ64_MEMBER(bebox_interrupt_sources_r);
60   DECLARE_READ64_MEMBER(bebox_crossproc_interrupts_r);
61   DECLARE_READ8_MEMBER(bebox_800001F0_r);
62   DECLARE_READ64_MEMBER(bebox_800003F0_r);
63   DECLARE_READ64_MEMBER(bebox_interrupt_ack_r);
64   DECLARE_READ8_MEMBER(bebox_page_r);
65   DECLARE_READ8_MEMBER(bebox_80000480_r);
66   DECLARE_READ8_MEMBER(bebox_flash_r);
67
68   DECLARE_WRITE64_MEMBER(bebox_cpu0_imask_w);
69   DECLARE_WRITE64_MEMBER(bebox_cpu1_imask_w);
70   DECLARE_WRITE64_MEMBER(bebox_crossproc_interrupts_w);
71   DECLARE_WRITE64_MEMBER(bebox_processor_resets_w);
72   DECLARE_WRITE8_MEMBER(bebox_800001F0_w);
73   DECLARE_WRITE64_MEMBER(bebox_800003F0_w);
74   DECLARE_WRITE8_MEMBER(bebox_page_w);
75   DECLARE_WRITE8_MEMBER(bebox_80000480_w);
76   DECLARE_WRITE8_MEMBER(bebox_flash_w);
77   DECLARE_READ8_MEMBER(at_dma8237_1_r);
78   DECLARE_WRITE8_MEMBER(at_dma8237_1_w);
79   DECLARE_READ8_MEMBER(bebox_dma_read_byte);
80   DECLARE_WRITE8_MEMBER(bebox_dma_write_byte);
81   DECLARE_READ64_MEMBER(scsi53c810_r);
82   DECLARE_WRITE64_MEMBER(scsi53c810_w);
83   DECLARE_READ64_MEMBER(bb_slave_64be_r);
5784};
5885
5986
r18264r18265
6996extern const ins8250_interface bebox_uart_inteface_2;
7097extern const ins8250_interface bebox_uart_inteface_3;
7198
72
73
74
75DECLARE_READ64_HANDLER( bebox_cpu0_imask_r );
76DECLARE_READ64_HANDLER( bebox_cpu1_imask_r );
77DECLARE_READ64_HANDLER( bebox_interrupt_sources_r );
78DECLARE_READ64_HANDLER( bebox_crossproc_interrupts_r );
79DECLARE_READ8_HANDLER( bebox_800001F0_r );
80DECLARE_READ64_HANDLER( bebox_800003F0_r );
81DECLARE_READ64_HANDLER( bebox_interrupt_ack_r );
82DECLARE_READ8_HANDLER( bebox_page_r );
83DECLARE_READ8_HANDLER( bebox_80000480_r );
84DECLARE_READ8_HANDLER( bebox_flash_r );
85
86DECLARE_WRITE64_HANDLER( bebox_cpu0_imask_w );
87DECLARE_WRITE64_HANDLER( bebox_cpu1_imask_w );
88DECLARE_WRITE64_HANDLER( bebox_crossproc_interrupts_w );
89DECLARE_WRITE64_HANDLER( bebox_processor_resets_w );
90DECLARE_WRITE8_HANDLER( bebox_800001F0_w );
91DECLARE_WRITE64_HANDLER( bebox_800003F0_w );
92DECLARE_WRITE8_HANDLER( bebox_page_w );
93DECLARE_WRITE8_HANDLER( bebox_80000480_w );
94DECLARE_WRITE8_HANDLER( bebox_flash_w );
95
9699void bebox_ide_interrupt(device_t *device, int state);
97100void bebox_set_irq_bit(running_machine &machine, unsigned int interrupt_bit, int val);
98101
trunk/src/mess/includes/fmtowns.h
r18264r18265
2121
2222#define IRQ_LOG 0  // set to 1 to log IRQ line activity
2323
24DECLARE_READ8_HANDLER( towns_gfx_high_r );
25DECLARE_WRITE8_HANDLER( towns_gfx_high_w );
26DECLARE_READ8_HANDLER( towns_gfx_r );
27DECLARE_WRITE8_HANDLER( towns_gfx_w );
28DECLARE_READ8_HANDLER( towns_video_cff80_r );
29DECLARE_WRITE8_HANDLER( towns_video_cff80_w );
30DECLARE_READ8_HANDLER( towns_video_cff80_mem_r );
31DECLARE_WRITE8_HANDLER( towns_video_cff80_mem_w );
32DECLARE_READ8_HANDLER(towns_video_440_r);
33DECLARE_WRITE8_HANDLER(towns_video_440_w);
34DECLARE_READ8_HANDLER(towns_video_5c8_r);
35DECLARE_WRITE8_HANDLER(towns_video_5c8_w);
36DECLARE_READ8_HANDLER(towns_video_fd90_r);
37DECLARE_WRITE8_HANDLER(towns_video_fd90_w);
38DECLARE_READ8_HANDLER(towns_video_ff81_r);
39DECLARE_WRITE8_HANDLER(towns_video_ff81_w);
40DECLARE_READ32_HANDLER(towns_video_unknown_r);
41DECLARE_READ8_HANDLER(towns_spriteram_low_r);
42DECLARE_WRITE8_HANDLER(towns_spriteram_low_w);
43DECLARE_READ8_HANDLER(towns_spriteram_r);
44DECLARE_WRITE8_HANDLER(towns_spriteram_w);
45
4624struct towns_cdrom_controller
4725{
4826   UINT8 command;
trunk/src/mess/includes/dgn_beta.h
r18264r18265
183183   DECLARE_WRITE_LINE_MEMBER(dgnbeta_fdc_intrq_w);
184184   DECLARE_WRITE_LINE_MEMBER(dgnbeta_fdc_drq_w);
185185   DECLARE_WRITE_LINE_MEMBER(dgnbeta_vsync_changed);
186   /* 74HC670 4x4bit colour ram */
187   DECLARE_WRITE8_MEMBER(dgnbeta_colour_ram_w);
188   // Page IO at FE00
189   DECLARE_READ8_MEMBER(dgn_beta_page_r);
190   DECLARE_WRITE8_MEMBER(dgn_beta_page_w);
191
192   /*  WD2797 FDC */
193   DECLARE_READ8_HANDLER(dgnbeta_wd2797_r);
194   DECLARE_WRITE8_HANDLER(dgnbeta_wd2797_w);
186195};
187196
188197
r18264r18265
192201extern const pia6821_interface dgnbeta_pia_intf[];
193202
194203
195
196
197// Page IO at FE00
198DECLARE_READ8_HANDLER( dgn_beta_page_r );
199DECLARE_WRITE8_HANDLER( dgn_beta_page_w );
200
201/*  WD2797 FDC */
202DECLARE_READ8_HANDLER(dgnbeta_wd2797_r);
203DECLARE_WRITE8_HANDLER(dgnbeta_wd2797_w);
204
205204void dgn_beta_frame_interrupt (running_machine &machine, int data);
206205
207206
r18264r18265
210209/* mc6845 video display generator */
211210void dgnbeta_vid_set_gctrl(running_machine &machine, int data);
212211
213/* 74HC670 4x4bit colour ram */
214DECLARE_WRITE8_HANDLER(dgnbeta_colour_ram_w);
215
216212extern const mc6845_interface dgnbeta_crtc6845_interface;
217213
218214#endif /* DGN_BETA_H_ */
trunk/src/mess/includes/mbc55x.h
r18264r18265
160160   TIMER_CALLBACK_MEMBER(keyscan_callback);
161161};
162162
163/* IO chips */
164
165
166struct msm_rx_t
167{
168};
169
170163/*----------- defined in drivers/mbc55x.c -----------*/
171164
172165extern const unsigned char mbc55x_palette[SCREEN_NO_COLOURS][3];
r18264r18265
181174extern const i8251_interface mbc55x_i8251b_interface;
182175
183176
184
185
186
187177/* Memory controller */
188178#define RAM_BANK00_TAG  "bank0"
189179#define RAM_BANK01_TAG  "bank1"
r18264r18265
204194#define RAM_BANK_SIZE   (64*1024)
205195#define RAM_BANK_COUNT   15
206196
207
208DECLARE_READ8_HANDLER(ppi8255_r);
209DECLARE_WRITE8_HANDLER(ppi8255_w);
210
211197/* Floppy drive interface */
212198
213199#define FDC_PAUSE            10000
r18264r18265
219205
220206extern const mc6845_interface mb55x_mc6845_intf;
221207
222DECLARE_READ16_HANDLER (mbc55x_video_io_r);
223DECLARE_WRITE16_HANDLER (mbc55x_video_io_w);
224208
225
226209#define RED                     0
227210#define GREEN                   1
228211#define BLUE                    2
trunk/src/mess/video/dgn_beta.c
r18264r18265
294294
295295
296296/* Write handler for colour, pallate ram */
297WRITE8_HANDLER(dgnbeta_colour_ram_w)
297WRITE8_MEMBER(dgn_beta_state::dgnbeta_colour_ram_w)
298298{
299   dgn_beta_state *state = space.machine().driver_data<dgn_beta_state>();
300   state->m_ColourRAM[offset]=data&0x0f;         /* Colour ram 4 bit and write only to CPU */
299   m_ColourRAM[offset]=data&0x0f;         /* Colour ram 4 bit and write only to CPU */
301300}
trunk/src/mess/drivers/dgn_beta.c
r18264r18265
158158   AM_RANGE(0xfc80, 0xfc80)    AM_DEVWRITE("crtc", mc6845_device, address_w)
159159   AM_RANGE(0xfc81, 0xfc81)    AM_DEVREADWRITE("crtc", mc6845_device, register_r, register_w)
160160   AM_RANGE(0xfc82, 0xfC9F)   AM_NOP
161   AM_RANGE(0xFCA0, 0xFCA3)   AM_READNOP AM_WRITE_LEGACY(dgnbeta_colour_ram_w)          /* 4x4bit colour ram for graphics modes */
161   AM_RANGE(0xFCA0, 0xFCA3)   AM_READNOP AM_WRITE(dgnbeta_colour_ram_w)          /* 4x4bit colour ram for graphics modes */
162162   AM_RANGE(0xFCC0, 0xFCC3)   AM_DEVREADWRITE(PIA_2_TAG, pia6821_device, read, write)
163163   AM_RANGE(0xfcC4, 0xfcdf)   AM_NOP
164   AM_RANGE(0xfce0, 0xfce3)   AM_READWRITE_LEGACY(dgnbeta_wd2797_r   ,dgnbeta_wd2797_w)   /* Onboard disk interface */
164   AM_RANGE(0xfce0, 0xfce3)   AM_READWRITE(dgnbeta_wd2797_r   ,dgnbeta_wd2797_w)   /* Onboard disk interface */
165165   AM_RANGE(0xfce4, 0xfdff)   AM_NOP
166   AM_RANGE(0xFE00, 0xFE0F)   AM_READWRITE_LEGACY(dgn_beta_page_r   ,dgn_beta_page_w)
166   AM_RANGE(0xFE00, 0xFE0F)   AM_READWRITE(dgn_beta_page_r   ,dgn_beta_page_w)
167167   AM_RANGE(0xfe10, 0xfEff)   AM_NOP
168168   AM_RANGE(0xFF00, 0xFFFF)   AM_RAMBANK("bank17")
169169
trunk/src/mess/drivers/bebox.c
r18264r18265
3737#include "formats/pc_dsk.h"
3838#include "machine/ram.h"
3939
40static READ8_HANDLER(at_dma8237_1_r)  { return i8237_r(space.machine().device("dma8237_2"), space, offset / 2); }
41static WRITE8_HANDLER(at_dma8237_1_w) { i8237_w(space.machine().device("dma8237_2"), space, offset / 2, data); }
40READ8_MEMBER(bebox_state::at_dma8237_1_r)  { return i8237_r(machine().device("dma8237_2"), space, offset / 2); }
41WRITE8_MEMBER(bebox_state::at_dma8237_1_w) { i8237_w(machine().device("dma8237_2"), space, offset / 2, data); }
4242
4343static ADDRESS_MAP_START( bebox_mem, AS_PROGRAM, 64, bebox_state )
44   AM_RANGE(0x7FFFF0F0, 0x7FFFF0F7) AM_READWRITE_LEGACY(bebox_cpu0_imask_r, bebox_cpu0_imask_w )
45   AM_RANGE(0x7FFFF1F0, 0x7FFFF1F7) AM_READWRITE_LEGACY(bebox_cpu1_imask_r, bebox_cpu1_imask_w )
46   AM_RANGE(0x7FFFF2F0, 0x7FFFF2F7) AM_READ_LEGACY(bebox_interrupt_sources_r )
47   AM_RANGE(0x7FFFF3F0, 0x7FFFF3F7) AM_READWRITE_LEGACY(bebox_crossproc_interrupts_r, bebox_crossproc_interrupts_w )
48   AM_RANGE(0x7FFFF4F0, 0x7FFFF4F7) AM_WRITE_LEGACY(bebox_processor_resets_w )
44   AM_RANGE(0x7FFFF0F0, 0x7FFFF0F7) AM_READWRITE(bebox_cpu0_imask_r, bebox_cpu0_imask_w )
45   AM_RANGE(0x7FFFF1F0, 0x7FFFF1F7) AM_READWRITE(bebox_cpu1_imask_r, bebox_cpu1_imask_w )
46   AM_RANGE(0x7FFFF2F0, 0x7FFFF2F7) AM_READ(bebox_interrupt_sources_r )
47   AM_RANGE(0x7FFFF3F0, 0x7FFFF3F7) AM_READWRITE(bebox_crossproc_interrupts_r, bebox_crossproc_interrupts_w )
48   AM_RANGE(0x7FFFF4F0, 0x7FFFF4F7) AM_WRITE(bebox_processor_resets_w )
4949
5050   AM_RANGE(0x80000000, 0x8000001F) AM_DEVREADWRITE8_LEGACY("dma8237_1", i8237_r, i8237_w, U64(0xffffffffffffffff) )
5151   AM_RANGE(0x80000020, 0x8000003F) AM_DEVREADWRITE8_LEGACY("pic8259_master", pic8259_r, pic8259_w, U64(0xffffffffffffffff) )
5252   AM_RANGE(0x80000040, 0x8000005f) AM_DEVREADWRITE8_LEGACY("pit8254", pit8253_r, pit8253_w, U64(0xffffffffffffffff) )
5353   AM_RANGE(0x80000060, 0x8000006F) AM_READWRITE8_LEGACY(kbdc8042_8_r, kbdc8042_8_w, U64(0xffffffffffffffff) )
5454   AM_RANGE(0x80000070, 0x8000007F) AM_DEVREADWRITE8("rtc", mc146818_device, read, write , U64(0xffffffffffffffff) )
55   AM_RANGE(0x80000080, 0x8000009F) AM_READWRITE8_LEGACY(bebox_page_r, bebox_page_w, U64(0xffffffffffffffff) )
55   AM_RANGE(0x80000080, 0x8000009F) AM_READWRITE8(bebox_page_r, bebox_page_w, U64(0xffffffffffffffff) )
5656   AM_RANGE(0x800000A0, 0x800000BF) AM_DEVREADWRITE8_LEGACY("pic8259_slave", pic8259_r, pic8259_w, U64(0xffffffffffffffff) )
57   AM_RANGE(0x800000C0, 0x800000DF) AM_READWRITE8_LEGACY(at_dma8237_1_r, at_dma8237_1_w, U64(0xffffffffffffffff))
58   AM_RANGE(0x800001F0, 0x800001F7) AM_READWRITE8_LEGACY(bebox_800001F0_r, bebox_800001F0_w, U64(0xffffffffffffffff) )
57   AM_RANGE(0x800000C0, 0x800000DF) AM_READWRITE8(at_dma8237_1_r, at_dma8237_1_w, U64(0xffffffffffffffff))
58   AM_RANGE(0x800001F0, 0x800001F7) AM_READWRITE8(bebox_800001F0_r, bebox_800001F0_w, U64(0xffffffffffffffff) )
5959   AM_RANGE(0x800002F8, 0x800002FF) AM_DEVREADWRITE8( "ns16550_1", ns16550_device, ins8250_r, ins8250_w, U64(0xffffffffffffffff) )
6060   AM_RANGE(0x80000380, 0x80000387) AM_DEVREADWRITE8( "ns16550_2", ns16550_device, ins8250_r, ins8250_w, U64(0xffffffffffffffff) )
6161   AM_RANGE(0x80000388, 0x8000038F) AM_DEVREADWRITE8( "ns16550_3", ns16550_device, ins8250_r, ins8250_w, U64(0xffffffffffffffff) )
6262   AM_RANGE(0x800003b0, 0x800003bf) AM_DEVREADWRITE8("vga", cirrus_vga_device, port_03b0_r, port_03b0_w, U64(0xffffffffffffffff))
6363   AM_RANGE(0x800003c0, 0x800003cf) AM_DEVREADWRITE8("vga", cirrus_vga_device, port_03c0_r, port_03c0_w, U64(0xffffffffffffffff))
6464   AM_RANGE(0x800003d0, 0x800003df) AM_DEVREADWRITE8("vga", cirrus_vga_device, port_03d0_r, port_03d0_w, U64(0xffffffffffffffff))
65   AM_RANGE(0x800003F0, 0x800003F7) AM_READWRITE_LEGACY(bebox_800003F0_r, bebox_800003F0_w )
65   AM_RANGE(0x800003F0, 0x800003F7) AM_READWRITE(bebox_800003F0_r, bebox_800003F0_w )
6666   AM_RANGE(0x800003F8, 0x800003FF) AM_DEVREADWRITE8( "ns16550_0",ns16550_device,  ins8250_r, ins8250_w, U64(0xffffffffffffffff) )
67   AM_RANGE(0x80000480, 0x8000048F) AM_READWRITE8_LEGACY(bebox_80000480_r, bebox_80000480_w, U64(0xffffffffffffffff) )
67   AM_RANGE(0x80000480, 0x8000048F) AM_READWRITE8(bebox_80000480_r, bebox_80000480_w, U64(0xffffffffffffffff) )
6868   AM_RANGE(0x80000CF8, 0x80000CFF) AM_DEVREADWRITE("pcibus", pci_bus_device, read_64be, write_64be )
6969   //AM_RANGE(0x800042E8, 0x800042EF) AM_DEVWRITE8_LEGACY("cirrus", cirrus_42E8_w, U64(0xffffffffffffffff) )
7070
71   AM_RANGE(0xBFFFFFF0, 0xBFFFFFFF) AM_READ_LEGACY(bebox_interrupt_ack_r )
71   AM_RANGE(0xBFFFFFF0, 0xBFFFFFFF) AM_READ(bebox_interrupt_ack_r )
7272   AM_RANGE(0xC00A0000, 0XC00BFFFF) AM_DEVREADWRITE8("vga", cirrus_vga_device, mem_r, mem_w, U64(0xffffffffffffffff) )
7373   AM_RANGE(0xC1000000, 0XC11FFFFF) AM_DEVREADWRITE8("vga", cirrus_vga_device, mem_linear_r, mem_linear_w, U64(0xffffffffffffffff) )
7474   AM_RANGE(0xFFF00000, 0xFFF03FFF) AM_ROMBANK("bank2")
75   AM_RANGE(0xFFF04000, 0xFFFFFFFF) AM_READWRITE8_LEGACY(bebox_flash_r, bebox_flash_w, U64(0xffffffffffffffff) )
75   AM_RANGE(0xFFF04000, 0xFFFFFFFF) AM_READWRITE8(bebox_flash_r, bebox_flash_w, U64(0xffffffffffffffff) )
7676ADDRESS_MAP_END
7777
7878// The following is a gross hack to let the BeBox boot ROM identify the processors correctly.
7979// This needs to be done in a better way if someone comes up with one.
8080
81static READ64_HANDLER(bb_slave_64be_r)
81READ64_MEMBER(bebox_state::bb_slave_64be_r)
8282{
83   pci_bus_device *device = space.machine().device<pci_bus_device>("pcibus");
83   pci_bus_device *device = machine().device<pci_bus_device>("pcibus");
8484
8585   // 2e94 is the real address, 2e84 is where the PC appears to be under full DRC
8686   if ((space.device().safe_pc() == 0xfff02e94) || (space.device().safe_pc() == 0xfff02e84))
r18264r18265
9292}
9393
9494static ADDRESS_MAP_START( bebox_slave_mem, AS_PROGRAM, 64, bebox_state )
95   AM_RANGE(0x80000cf8, 0x80000cff) AM_READ_LEGACY(bb_slave_64be_r)
95   AM_RANGE(0x80000cf8, 0x80000cff) AM_READ(bb_slave_64be_r)
9696   AM_RANGE(0x80000cf8, 0x80000cff) AM_DEVWRITE("pcibus", pci_bus_device, write_64be )
9797   AM_IMPORT_FROM(bebox_mem)
9898ADDRESS_MAP_END

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