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r18064 Friday 21st September, 2012 at 15:23:07 UTC by Fabio Priuli
nes.c: modernized the driver by moving most code into the class, work by Micko. no whatsnew.

[src/mess/drivers]	nes.c
[src/mess/includes]	nes.h
[src/mess/machine]	nes.c nes_ines.c nes_mmc.c nes_mmc.h nes_pcb.c

trunk/src/mess/machine/nes.c

r18063	r18064
23	23	FUNCTION PROTOTYPES
24	24	***************************************************************************/
25	25
26		static void init_nes_core(running_machine &machine);
27	26	static void nes_machine_stop(running_machine &machine);
28	27
29	28
r18063	r18064
33	32	FUNCTIONS
34	33	***************************************************************************/
35	34
36		static void init_nes_core( running_machine &machine )
	35	void nes_state::init_nes_core()
37	36	{
38		nes_state *state = machine.driver_data<nes_state>();
39		address_space &space = machine.device("maincpu")->memory().space(AS_PROGRAM);
	37	address_space &space = machine().device("maincpu")->memory().space(AS_PROGRAM);
40	38	static const char *const bank_names[] = { "bank1", "bank2", "bank3", "bank4" };
41		int prg_banks = (state->m_prg_chunks == 1) ? (2 * 2) : (state->m_prg_chunks * 2);
	39	int prg_banks = (m_prg_chunks == 1) ? (2 * 2) : (m_prg_chunks * 2);
42	40	int i;
43	41
44		state->m_rom = machine.root_device().memregion("maincpu")->base();
45		state->m_ciram = machine.root_device().memregion("ciram")->base();
	42	m_rom = machine().root_device().memregion("maincpu")->base();
	43	m_ciram = machine().root_device().memregion("ciram")->base();
46	44	// other pointers got set in the loading routine
47	45
48	46	/* Brutal hack put in as a consequence of the new memory system; we really need to fix the NES code */
49	47	space.install_readwrite_bank(0x0000, 0x07ff, 0, 0x1800, "bank10");
50	48
51		machine.device("ppu")->memory().space(AS_PROGRAM).install_legacy_readwrite_handler(0, 0x1fff, FUNC(nes_chr_r), FUNC(nes_chr_w));
52		machine.device("ppu")->memory().space(AS_PROGRAM).install_legacy_readwrite_handler(0x2000, 0x3eff, FUNC(nes_nt_r), FUNC(nes_nt_w));
	49	machine().device("ppu")->memory().space(AS_PROGRAM).install_readwrite_handler(0, 0x1fff, read8_delegate(FUNC(nes_state::nes_chr_r),this), write8_delegate(FUNC(nes_state::nes_chr_w),this));
	50	machine().device("ppu")->memory().space(AS_PROGRAM).install_readwrite_handler(0x2000, 0x3eff, read8_delegate(FUNC(nes_state::nes_nt_r),this), write8_delegate(FUNC(nes_state::nes_nt_w),this));
53	51
54		state->membank("bank10")->set_base(state->m_rom);
	52	membank("bank10")->set_base(m_rom);
55	53
56	54	/* If there is Disk Expansion and no cart has been loaded, setup memory accordingly */
57		if (state->m_disk_expansion && state->m_pcb_id == NO_BOARD)
	55	if (m_disk_expansion && m_pcb_id == NO_BOARD)
58	56	{
59		/* If we are loading a disk we have already filled state->m_fds_data and we don't want to overwrite it,
	57	/* If we are loading a disk we have already filled m_fds_data and we don't want to overwrite it,
60	58	if we are loading a cart image identified as mapper 20 (probably wrong mapper...) we need to alloc
61	59	memory for use in nes_fds_r/nes_fds_w. Same goes for allocation of fds_ram (used for bank2)  */
62		if (state->m_fds_data == NULL)
	60	if (m_fds_data == NULL)
63	61	{
64		UINT32 size = (state->m_prg_chunks == 1) ? 2 * 0x4000 : state->m_prg_chunks * 0x4000;
65		state->m_fds_data = auto_alloc_array_clear(machine, UINT8, size);
66		memcpy(state->m_fds_data, state->m_prg, size);   // copy in fds_data the cart PRG
	62	UINT32 size = (m_prg_chunks == 1) ? 2 * 0x4000 : m_prg_chunks * 0x4000;
	63	m_fds_data = auto_alloc_array_clear(machine(), UINT8, size);
	64	memcpy(m_fds_data, m_prg, size);   // copy in fds_data the cart PRG
67	65	}
68		if (state->m_fds_ram == NULL)
69		state->m_fds_ram = auto_alloc_array(machine, UINT8, 0x8000);
	66	if (m_fds_ram == NULL)
	67	m_fds_ram = auto_alloc_array(machine(), UINT8, 0x8000);
70	68
71		space.install_read_handler(0x4030, 0x403f, read8_delegate(FUNC(nes_state::nes_fds_r),state));
	69	space.install_read_handler(0x4030, 0x403f, read8_delegate(FUNC(nes_state::nes_fds_r),this));
72	70	space.install_read_bank(0x6000, 0xdfff, "bank2");
73	71	space.install_read_bank(0xe000, 0xffff, "bank1");
74	72
75		space.install_write_handler(0x4020, 0x402f, write8_delegate(FUNC(nes_state::nes_fds_w),state));
	73	space.install_write_handler(0x4020, 0x402f, write8_delegate(FUNC(nes_state::nes_fds_w),this));
76	74	space.install_write_bank(0x6000, 0xdfff, "bank2");
77	75
78		state->membank("bank1")->set_base(&state->m_rom[0xe000]);
79		state->membank("bank2")->set_base(state->m_fds_ram);
	76	membank("bank1")->set_base(&m_rom[0xe000]);
	77	membank("bank2")->set_base(m_fds_ram);
80	78	return;
81	79	}
82	80
83	81	/* Set up the mapper callbacks */
84		pcb_handlers_setup(machine);
	82	pcb_handlers_setup(machine());
85	83
86	84	/* Set up the memory handlers for the mapper */
87	85	space.install_read_bank(0x8000, 0x9fff, "bank1");
r18063	r18064
93	91	/* configure banks 1-4 */
94	92	for (i = 0; i < 4; i++)
95	93	{
96		state->membank(bank_names[i])->configure_entries(0, prg_banks, state->m_prg, 0x2000);
	94	membank(bank_names[i])->configure_entries(0, prg_banks, m_prg, 0x2000);
97	95	// some mappers (e.g. MMC5) can map PRG RAM in  0x8000-0xffff as well
98		if (state->m_prg_ram)
99		state->membank(bank_names[i])->configure_entries(prg_banks, state->m_wram_size / 0x2000, state->m_wram, 0x2000);
	96	if (m_prg_ram)
	97	membank(bank_names[i])->configure_entries(prg_banks, m_wram_size / 0x2000, m_wram, 0x2000);
100	98	// however, at start we point to PRG ROM
101		state->membank(bank_names[i])->set_entry(i);
102		state->m_prg_bank[i] = i;
	99	membank(bank_names[i])->set_entry(i);
	100	m_prg_bank[i] = i;
103	101	}
104	102
105	103	/* bank 5 configuration is more delicate, since it can have PRG RAM, PRG ROM or SRAM mapped to it */
106		/* we first map PRG ROM banks, then the battery bank (if a battery is present), and finally PRG RAM (state->m_wram) */
107		state->membank("bank5")->configure_entries(0, prg_banks, state->m_prg, 0x2000);
108		state->m_battery_bank5_start = prg_banks;
109		state->m_prgram_bank5_start = prg_banks;
110		state->m_empty_bank5_start = prg_banks;
	104	/* we first map PRG ROM banks, then the battery bank (if a battery is present), and finally PRG RAM (m_wram) */
	105	membank("bank5")->configure_entries(0, prg_banks, m_prg, 0x2000);
	106	m_battery_bank5_start = prg_banks;
	107	m_prgram_bank5_start = prg_banks;
	108	m_empty_bank5_start = prg_banks;
111	109
112	110	/* add battery ram, but only if there's no trainer since they share overlapping memory. */
113		if (state->m_battery && !state->m_trainer)
	111	if (m_battery && !m_trainer)
114	112	{
115		UINT32 bank_size = (state->m_battery_size > 0x2000) ? 0x2000 : state->m_battery_size;
116		int bank_num = (state->m_battery_size > 0x2000) ? state->m_battery_size / 0x2000 : 1;
117		state->membank("bank5")->configure_entries(prg_banks, bank_num, state->m_battery_ram, bank_size);
118		state->m_prgram_bank5_start += bank_num;
119		state->m_empty_bank5_start += bank_num;
	113	UINT32 bank_size = (m_battery_size > 0x2000) ? 0x2000 : m_battery_size;
	114	int bank_num = (m_battery_size > 0x2000) ? m_battery_size / 0x2000 : 1;
	115	membank("bank5")->configure_entries(prg_banks, bank_num, m_battery_ram, bank_size);
	116	m_prgram_bank5_start += bank_num;
	117	m_empty_bank5_start += bank_num;
120	118	}
121	119	/* add prg ram. */
122		if (state->m_prg_ram)
	120	if (m_prg_ram)
123	121	{
124		state->membank("bank5")->configure_entries(state->m_prgram_bank5_start, state->m_wram_size / 0x2000, state->m_wram, 0x2000);
125		state->m_empty_bank5_start += state->m_wram_size / 0x2000;
	122	membank("bank5")->configure_entries(m_prgram_bank5_start, m_wram_size / 0x2000, m_wram, 0x2000);
	123	m_empty_bank5_start += m_wram_size / 0x2000;
126	124	}
127	125
128		state->membank("bank5")->configure_entry(state->m_empty_bank5_start, state->m_rom + 0x6000);
	126	membank("bank5")->configure_entry(m_empty_bank5_start, m_rom + 0x6000);
129	127
130	128	/* if we have any additional PRG RAM, point bank5 to its first bank */
131		if (state->m_battery || state->m_prg_ram)
132		state->m_prg_bank[4] = state->m_battery_bank5_start;
	129	if (m_battery || m_prg_ram)
	130	m_prg_bank[4] = m_battery_bank5_start;
133	131	else
134		state->m_prg_bank[4] = state->m_empty_bank5_start; // or shall we point to "maincpu" region at 0x6000? point is that we should never access this region if no sram or wram is present!
	132	m_prg_bank[4] = m_empty_bank5_start; // or shall we point to "maincpu" region at 0x6000? point is that we should never access this region if no sram or wram is present!
135	133
136		state->membank("bank5")->set_entry(state->m_prg_bank[4]);
	134	membank("bank5")->set_entry(m_prg_bank[4]);
137	135
138		if (state->m_four_screen_vram)
	136	if (m_four_screen_vram)
139	137	{
140		state->m_extended_ntram = auto_alloc_array_clear(machine, UINT8, 0x2000);
141		state->save_pointer(NAME(state->m_extended_ntram), 0x2000);
	138	m_extended_ntram = auto_alloc_array_clear(machine(), UINT8, 0x2000);
	139	save_pointer(NAME(m_extended_ntram), 0x2000);
142	140	}
143	141
144		if (state->m_four_screen_vram)
145		set_nt_mirroring(machine, PPU_MIRROR_4SCREEN);
	142	if (m_four_screen_vram)
	143	set_nt_mirroring(machine(), PPU_MIRROR_4SCREEN);
146	144	else
147	145	{
148		switch (state->m_hard_mirroring)
	146	switch (m_hard_mirroring)
149	147	{
150	148	case PPU_MIRROR_HORZ:
151	149	case PPU_MIRROR_VERT:
152	150	case PPU_MIRROR_HIGH:
153	151	case PPU_MIRROR_LOW:
154		set_nt_mirroring(machine, state->m_hard_mirroring);
	152	set_nt_mirroring(machine(), m_hard_mirroring);
155	153	break;
156	154	default:
157		set_nt_mirroring(machine, PPU_MIRROR_NONE);
	155	set_nt_mirroring(machine(), PPU_MIRROR_NONE);
158	156	break;
159	157	}
160	158	}
161	159
162	160	// there are still some quirk about writes to bank5... I hope to fix them soon. (mappers 34,45,52,246 have both mid_w and WRAM-->check)
163		if (state->m_mmc_write_mid)
164		space.install_legacy_write_handler(0x6000, 0x7fff, state->m_mmc_write_mid,state->m_mmc_write_mid_name);
165		if (state->m_mmc_write)
166		space.install_legacy_write_handler(0x8000, 0xffff, state->m_mmc_write, state->m_mmc_write_name);
	161	if (!m_mmc_write_mid.isnull())
	162	space.install_write_handler(0x6000, 0x7fff, m_mmc_write_mid);
	163	if (!m_mmc_write.isnull())
	164	space.install_write_handler(0x8000, 0xffff, m_mmc_write);
167	165
168	166	// In fact, we also allow single pcbs to overwrite the bank read handlers defined above,
169	167	// because some pcbs (mainly pirate ones) require protection values to be read instead of
170	168	// the expected ROM banks: these handlers, though, must take care of the ROM access as well
171		if (state->m_mmc_read_mid)
172		space.install_legacy_read_handler(0x6000, 0x7fff, state->m_mmc_read_mid,state->m_mmc_read_mid_name);
173		if (state->m_mmc_read)
174		space.install_legacy_read_handler(0x8000, 0xffff, state->m_mmc_read,state->m_mmc_read_name);
	169	if (!m_mmc_read_mid.isnull())
	170	space.install_read_handler(0x6000, 0x7fff, m_mmc_read_mid);
	171	if (!m_mmc_read.isnull())
	172	space.install_read_handler(0x8000, 0xffff, m_mmc_read);
175	173
176	174	// install additional handlers
177		if (state->m_pcb_id == BTL_SMB2B || state->m_mapper == 50)
	175	if (m_pcb_id == BTL_SMB2B || m_mapper == 50)
178	176	{
179		space.install_legacy_write_handler(0x4020, 0x403f, FUNC(smb2jb_extra_w));
180		space.install_legacy_write_handler(0x40a0, 0x40bf, FUNC(smb2jb_extra_w));
	177	space.install_write_handler(0x4020, 0x403f, write8_delegate(FUNC(nes_state::smb2jb_extra_w),this));
	178	space.install_write_handler(0x40a0, 0x40bf, write8_delegate(FUNC(nes_state::smb2jb_extra_w),this));
181	179	}
182	180
183		if (state->m_pcb_id == KAISER_KS7017)
	181	if (m_pcb_id == KAISER_KS7017)
184	182	{
185		space.install_legacy_read_handler(0x4030, 0x4030, FUNC(ks7017_extra_r));
186		space.install_legacy_write_handler(0x4020, 0x40ff, FUNC(ks7017_extra_w));
	183	space.install_read_handler(0x4030, 0x4030, read8_delegate(FUNC(nes_state::ks7017_extra_r),this));
	184	space.install_write_handler(0x4020, 0x40ff, write8_delegate(FUNC(nes_state::ks7017_extra_w),this));
187	185	}
188	186
189		if (state->m_pcb_id == UNL_603_5052)
	187	if (m_pcb_id == UNL_603_5052)
190	188	{
191		space.install_legacy_read_handler(0x4020, 0x40ff, FUNC(unl_6035052_extra_r));
192		space.install_legacy_write_handler(0x4020, 0x40ff, FUNC(unl_6035052_extra_w));
	189	space.install_read_handler(0x4020, 0x40ff, read8_delegate(FUNC(nes_state::unl_6035052_extra_r),this));
	190	space.install_write_handler(0x4020, 0x40ff, write8_delegate(FUNC(nes_state::unl_6035052_extra_w),this));
193	191	}
194	192
195		if (state->m_pcb_id == WAIXING_SH2)
196		machine.device("ppu")->memory().space(AS_PROGRAM).install_legacy_read_handler(0, 0x1fff, FUNC(waixing_sh2_chr_r));
	193	if (m_pcb_id == WAIXING_SH2)
	194	machine().device("ppu")->memory().space(AS_PROGRAM).install_read_handler(0, 0x1fff, read8_delegate(FUNC(nes_state::waixing_sh2_chr_r),this));
197	195	}
198	196
199	197	// to be probably removed (it does nothing since a long time)
r18063	r18064
291	289	{
292	290
293	291	m_ppu = machine().device<ppu2c0x_device>("ppu");
294		init_nes_core(machine());
	292	init_nes_core();
295	293	machine().add_notifier(MACHINE_NOTIFY_EXIT, machine_notify_delegate(FUNC(nes_machine_stop),&machine()));
296	294
297	295	m_maincpu = machine().device<cpu_device>("maincpu");

trunk/src/mess/machine/nes_mmc.c

r18063	r18064
137	137	#define LOG_FDS(x) do { if (VERBOSE) logerror x; } while (0)
138	138
139	139	static void ffe_irq( device_t *device, int scanline, int vblank, int blanked );
140		static DECLARE_WRITE8_HANDLER( mapper6_l_w );
141		static DECLARE_WRITE8_HANDLER( mapper6_w );
142		static DECLARE_WRITE8_HANDLER( mapper8_w );
143		static DECLARE_WRITE8_HANDLER( mapper17_l_w );
144	140
145	141	/*************************************************************
146	142
r18063	r18064
165	161
166	162	*************************************************************/
167	163
168		WRITE8_HANDLER( nes_chr_w )
	164	WRITE8_MEMBER(nes_state::nes_chr_w)
169	165	{
170		nes_state *state = space.machine().driver_data<nes_state>();
171	166	int bank = offset >> 10;
172	167
173		if (state->m_chr_map[bank].source == CHRRAM)
	168	if (m_chr_map[bank].source == CHRRAM)
174	169	{
175		state->m_chr_map[bank].access[offset & 0x3ff] = data;
	170	m_chr_map[bank].access[offset & 0x3ff] = data;
176	171	}
177	172	}
178	173
179		READ8_HANDLER( nes_chr_r )
	174	READ8_MEMBER(nes_state::nes_chr_r)
180	175	{
181		nes_state *state = space.machine().driver_data<nes_state>();
182	176	int bank = offset >> 10;
183	177
184	178	// a few CNROM boards contained copy protection schemes through
185	179	// suitably configured diodes, so that subsequent CHR reads can
186	180	// give actual VROM content or open bus values.
187	181	// For most boards, chr_open_bus remains always zero.
188		if (state->m_chr_open_bus)
	182	if (m_chr_open_bus)
189	183	return 0xff;
190	184
191		return state->m_chr_map[bank].access[offset & 0x3ff];
	185	return m_chr_map[bank].access[offset & 0x3ff];
192	186	}
193	187
194		WRITE8_HANDLER( nes_nt_w )
	188	WRITE8_MEMBER(nes_state::nes_nt_w)
195	189	{
196		nes_state *state = space.machine().driver_data<nes_state>();
197	190	int page = ((offset & 0xc00) >> 10);
198	191
199		if (state->m_nt_page[page].writable == 0)
	192	if (m_nt_page[page].writable == 0)
200	193	return;
201	194
202		state->m_nt_page[page].access[offset & 0x3ff] = data;
	195	m_nt_page[page].access[offset & 0x3ff] = data;
203	196	}
204	197
205		READ8_HANDLER( nes_nt_r )
	198	READ8_MEMBER(nes_state::nes_nt_r)
206	199	{
207		nes_state *state = space.machine().driver_data<nes_state>();
208	200	int page = ((offset & 0xc00) >> 10);
209	201
210		if (state->m_nt_page[page].source == MMC5FILL)
	202	if (m_nt_page[page].source == MMC5FILL)
211	203	{
212	204	if ((offset & 0x3ff) >= 0x3c0)
213		return state->m_MMC5_floodattr;
	205	return m_MMC5_floodattr;
214	206
215		return state->m_MMC5_floodtile;
	207	return m_MMC5_floodtile;
216	208	}
217		return state->m_nt_page[page].access[offset & 0x3ff];
	209	return m_nt_page[page].access[offset & 0x3ff];
218	210	}
219	211
220		WRITE8_HANDLER( nes_low_mapper_w )
	212	WRITE8_MEMBER(nes_state::nes_low_mapper_w)
221	213	{
222		nes_state *state = space.machine().driver_data<nes_state>();
223	214
224		if (state->m_mmc_write_low)
225		(*state->m_mmc_write_low)(space, offset, data, mem_mask);
	215	if (!m_mmc_write_low.isnull())
	216	(m_mmc_write_low)(space, offset, data, mem_mask);
226	217	else
227	218	logerror("Unimplemented LOW mapper write, offset: %04x, data: %02x\n", offset + 0x4100, data);
228	219	}
229	220
230		READ8_HANDLER( nes_low_mapper_r )
	221	READ8_MEMBER(nes_state::nes_low_mapper_r)
231	222	{
232		nes_state *state = space.machine().driver_data<nes_state>();
233	223
234		if (state->m_mmc_read_low)
235		return (*state->m_mmc_read_low)(space, offset, mem_mask);
	224	if (!m_mmc_read_low.isnull())
	225	return (m_mmc_read_low)(space, offset, mem_mask);
236	226	else
237	227	logerror("Unimplemented LOW mapper read, offset: %04x\n", offset + 0x4100);
238	228

trunk/src/mess/machine/nes_mmc.h

r18063	r18064
116	116	void pcb_handlers_setup(running_machine &machine);
117	117	int nes_pcb_reset(running_machine &machine);
118	118
119
120		DECLARE_WRITE8_HANDLER( nes_low_mapper_w );
121		DECLARE_READ8_HANDLER( nes_low_mapper_r );
122		DECLARE_WRITE8_HANDLER( nes_chr_w );
123		DECLARE_READ8_HANDLER( nes_chr_r );
124		DECLARE_WRITE8_HANDLER( nes_nt_w );
125		DECLARE_READ8_HANDLER( nes_nt_r );
126
127		DECLARE_WRITE8_HANDLER( smb2jb_extra_w );
128		DECLARE_WRITE8_HANDLER( ks7017_extra_w );
129		DECLARE_READ8_HANDLER( ks7017_extra_r );
130		DECLARE_WRITE8_HANDLER( unl_6035052_extra_w );
131		DECLARE_READ8_HANDLER( unl_6035052_extra_r );
132		DECLARE_READ8_HANDLER( waixing_sh2_chr_r );
133
134	119	//TEMPORARY PPU STUFF
135	120
136	121	/* mirroring types */

trunk/src/mess/machine/nes_ines.c

r18063	r18064
45	45	}
46	46	}
47	47
48		static WRITE8_HANDLER( mapper6_l_w )
	48	WRITE8_MEMBER(nes_state::mapper6_l_w)
49	49	{
50		nes_state *state = space.machine().driver_data<nes_state>();
51	50	LOG_MMC(("mapper6_l_w, offset: %04x, data: %02x\n", offset, data));
52	51
53	52	switch (offset)
54	53	{
55	54	case 0x1fe:
56		state->m_mmc_latch1 = data & 0x80;
57		set_nt_mirroring(space.machine(), BIT(data, 4) ? PPU_MIRROR_HIGH : PPU_MIRROR_LOW);
	55	m_mmc_latch1 = data & 0x80;
	56	set_nt_mirroring(machine(), BIT(data, 4) ? PPU_MIRROR_HIGH : PPU_MIRROR_LOW);
58	57	break;
59	58	case 0x1ff:
60		set_nt_mirroring(space.machine(), BIT(data, 4) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	59	set_nt_mirroring(machine(), BIT(data, 4) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
61	60	break;
62	61
63	62	case 0x401:
64		state->m_IRQ_enable = data & 0x01;
	63	m_IRQ_enable = data & 0x01;
65	64	break;
66	65	case 0x402:
67		state->m_IRQ_count = (state->m_IRQ_count & 0xff00) | data;
	66	m_IRQ_count = (m_IRQ_count & 0xff00) | data;
68	67	break;
69	68	case 0x403:
70		state->m_IRQ_enable = 1;
71		state->m_IRQ_count = (state->m_IRQ_count & 0x00ff) | (data << 8);
	69	m_IRQ_enable = 1;
	70	m_IRQ_count = (m_IRQ_count & 0x00ff) | (data << 8);
72	71	break;
73	72	}
74	73	}
75	74
76		static WRITE8_HANDLER( mapper6_w )
	75	WRITE8_MEMBER(nes_state::mapper6_w)
77	76	{
78		nes_state *state = space.machine().driver_data<nes_state>();
79	77	LOG_MMC(("mapper6_w, offset: %04x, data: %02x\n", offset, data));
80	78
81		if (!state->m_mmc_latch1)   // when in "FFE mode" we are forced to use CHRRAM/EXRAM bank?
	79	if (!m_mmc_latch1)   // when in "FFE mode" we are forced to use CHRRAM/EXRAM bank?
82	80	{
83		prg16_89ab(space.machine(), data >> 2);
84		// chr8(space.machine(), data & 0x03, ???);
	81	prg16_89ab(machine(), data >> 2);
	82	// chr8(machine(), data & 0x03, ???);
85	83	// due to lack of info on the exact behavior, we simply act as if mmc_latch1=1
86		if (state->m_mmc_chr_source == CHRROM)
87		chr8(space.machine(), data & 0x03, CHRROM);
	84	if (m_mmc_chr_source == CHRROM)
	85	chr8(machine(), data & 0x03, CHRROM);
88	86	}
89		else if (state->m_mmc_chr_source == CHRROM)         // otherwise, we can use CHRROM (when present)
90		chr8(space.machine(), data, CHRROM);
	87	else if (m_mmc_chr_source == CHRROM)         // otherwise, we can use CHRROM (when present)
	88	chr8(machine(), data, CHRROM);
91	89	}
92	90
93	91	/*************************************************************
r18063	r18064
101	99
102	100	*************************************************************/
103	101
104		static WRITE8_HANDLER( mapper8_w )
	102	WRITE8_MEMBER(nes_state::mapper8_w)
105	103	{
106	104	LOG_MMC(("mapper8_w, offset: %04x, data: %02x\n", offset, data));
107	105
108		chr8(space.machine(), data & 0x07, CHRROM);
109		prg16_89ab(space.machine(), data >> 3);
	106	chr8(machine(), data & 0x07, CHRROM);
	107	prg16_89ab(machine(), data >> 3);
110	108	}
111	109
112	110	/*************************************************************
r18063	r18064
121	119
122	120	*************************************************************/
123	121
124		static WRITE8_HANDLER( mapper17_l_w )
	122	WRITE8_MEMBER(nes_state::mapper17_l_w)
125	123	{
126		nes_state *state = space.machine().driver_data<nes_state>();
127	124	LOG_MMC(("mapper17_l_w, offset: %04x, data: %02x\n", offset, data));
128	125
129	126	switch (offset)
130	127	{
131	128	case 0x1fe:
132		set_nt_mirroring(space.machine(), BIT(data, 4) ? PPU_MIRROR_HIGH : PPU_MIRROR_LOW);
	129	set_nt_mirroring(machine(), BIT(data, 4) ? PPU_MIRROR_HIGH : PPU_MIRROR_LOW);
133	130	break;
134	131	case 0x1ff:
135		set_nt_mirroring(space.machine(), BIT(data, 4) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	132	set_nt_mirroring(machine(), BIT(data, 4) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
136	133	break;
137	134
138	135	case 0x401:
139		state->m_IRQ_enable = data & 0x01;
	136	m_IRQ_enable = data & 0x01;
140	137	break;
141	138	case 0x402:
142		state->m_IRQ_count = (state->m_IRQ_count & 0xff00) | data;
	139	m_IRQ_count = (m_IRQ_count & 0xff00) | data;
143	140	break;
144	141	case 0x403:
145		state->m_IRQ_enable = 1;
146		state->m_IRQ_count = (state->m_IRQ_count & 0x00ff) | (data << 8);
	142	m_IRQ_enable = 1;
	143	m_IRQ_count = (m_IRQ_count & 0x00ff) | (data << 8);
147	144	break;
148	145
149	146	case 0x404:
150		prg8_89(space.machine(), data);
	147	prg8_89(machine(), data);
151	148	break;
152	149	case 0x405:
153		prg8_ab(space.machine(), data);
	150	prg8_ab(machine(), data);
154	151	break;
155	152	case 0x406:
156		prg8_cd(space.machine(), data);
	153	prg8_cd(machine(), data);
157	154	break;
158	155	case 0x407:
159		prg8_ef(space.machine(), data);
	156	prg8_ef(machine(), data);
160	157	break;
161	158
162	159	case 0x410:
r18063	r18064
167	164	case 0x415:
168	165	case 0x416:
169	166	case 0x417:
170		chr1_x(space.machine(), offset & 7, data, CHRROM);
	167	chr1_x(machine(), offset & 7, data, CHRROM);
171	168	break;
172	169	}
173	170	}

trunk/src/mess/machine/nes_pcb.c

r18063	r18064
714	714
715	715	*************************************************************/
716	716
717		static WRITE8_HANDLER( uxrom_w )
	717	WRITE8_MEMBER(nes_state::uxrom_w)
718	718	{
719	719	LOG_MMC(("uxrom_w, offset: %04x, data: %02x\n", offset, data));
720	720
721		prg16_89ab(space.machine(), data);
	721	prg16_89ab(machine(), data);
722	722	}
723	723
724	724	/*************************************************************
r18063	r18064
737	737
738	738	*************************************************************/
739	739
740		static WRITE8_HANDLER( uxrom_cc_w )
	740	WRITE8_MEMBER(nes_state::uxrom_cc_w)
741	741	{
742	742	LOG_MMC(("uxrom_cc_w, offset: %04x, data: %02x\n", offset, data));
743	743
744		prg16_cdef(space.machine(), data);
	744	prg16_cdef(machine(), data);
745	745	}
746	746
747	747	/*************************************************************
r18063	r18064
760	760
761	761	*************************************************************/
762	762
763		static WRITE8_HANDLER( un1rom_w )
	763	WRITE8_MEMBER(nes_state::un1rom_w)
764	764	{
765	765	LOG_MMC(("un1rom_w, offset: %04x, data: %02x\n", offset, data));
766	766
767		prg16_89ab(space.machine(), data >> 2);
	767	prg16_89ab(machine(), data >> 2);
768	768	}
769	769
770	770	/*************************************************************
r18063	r18064
791	791
792	792	*************************************************************/
793	793
794		static WRITE8_HANDLER( cnrom_w )
	794	WRITE8_MEMBER(nes_state::cnrom_w)
795	795	{
796		nes_state *state = space.machine().driver_data<nes_state>();
797	796	LOG_MMC(("cnrom_w, offset: %04x, data: %02x\n", offset, data));
798	797
799		if (state->m_ce_mask)
	798	if (m_ce_mask)
800	799	{
801		chr8(space.machine(), data & ~state->m_ce_mask, CHRROM);
	800	chr8(machine(), data & ~m_ce_mask, CHRROM);
802	801
803		if ((data & state->m_ce_mask) == state->m_ce_state)
804		state->m_chr_open_bus = 0;
	802	if ((data & m_ce_mask) == m_ce_state)
	803	m_chr_open_bus = 0;
805	804	else
806		state->m_chr_open_bus = 1;
	805	m_chr_open_bus = 1;
807	806	}
808	807	else
809		chr8(space.machine(), data, CHRROM);
	808	chr8(machine(), data, CHRROM);
810	809	}
811	810
812	811	/*************************************************************
r18063	r18064
821	820
822	821	*************************************************************/
823	822
824		static WRITE8_HANDLER( bandai_pt554_m_w )
	823	WRITE8_MEMBER(nes_state::bandai_pt554_m_w)
825	824	{
826	825	LOG_MMC(("Bandai PT-554 Sound write, data: %02x\n", data));
827	826
r18063	r18064
846	845
847	846	*************************************************************/
848	847
849		static WRITE8_HANDLER( cprom_w )
	848	WRITE8_MEMBER(nes_state::cprom_w)
850	849	{
851	850	LOG_MMC(("cprom_w, offset: %04x, data: %02x\n", offset, data));
852		chr4_4(space.machine(), data, CHRRAM);
	851	chr4_4(machine(), data, CHRRAM);
853	852	}
854	853
855	854	/*************************************************************
r18063	r18064
868	867
869	868	*************************************************************/
870	869
871		static WRITE8_HANDLER( axrom_w )
	870	WRITE8_MEMBER(nes_state::axrom_w)
872	871	{
873	872	LOG_MMC(("axrom_w, offset: %04x, data: %02x\n", offset, data));
874	873
875		set_nt_mirroring(space.machine(), BIT(data, 4) ? PPU_MIRROR_HIGH : PPU_MIRROR_LOW);
876		prg32(space.machine(), data);
	874	set_nt_mirroring(machine(), BIT(data, 4) ? PPU_MIRROR_HIGH : PPU_MIRROR_LOW);
	875	prg32(machine(), data);
877	876	}
878	877
879	878	/*************************************************************
r18063	r18064
888	887
889	888	*************************************************************/
890	889
891		static WRITE8_HANDLER( bxrom_w )
	890	WRITE8_MEMBER(nes_state::bxrom_w)
892	891	{
893	892	/* This portion of the mapper is nearly identical to Mapper 7, except no one-screen mirroring */
894	893	/* Deadly Towers is really a BxROM game - the demo screens look wrong using mapper 7. */
895	894	LOG_MMC(("bxrom_w, offset: %04x, data: %02x\n", offset, data));
896	895
897		prg32(space.machine(), data);
	896	prg32(machine(), data);
898	897	}
899	898
900	899	/*************************************************************
r18063	r18064
909	908
910	909	*************************************************************/
911	910
912		static WRITE8_HANDLER( gxrom_w )
	911	WRITE8_MEMBER(nes_state::gxrom_w)
913	912	{
914	913	LOG_MMC(("gxrom_w, offset %04x, data: %02x\n", offset, data));
915	914
916		prg32(space.machine(), (data & 0xf0) >> 4);
917		chr8(space.machine(), data & 0x0f, CHRROM);
	915	prg32(machine(), (data & 0xf0) >> 4);
	916	chr8(machine(), data & 0x0f, CHRROM);
918	917	}
919	918
920	919	/*************************************************************
r18063	r18064
1101	1100	}
1102	1101	}
1103	1102
1104		static WRITE8_HANDLER( sxrom_w )
	1103	WRITE8_MEMBER(nes_state::sxrom_w)
1105	1104	{
1106		nes_state *state = space.machine().driver_data<nes_state>();
1107	1105
1108	1106	LOG_MMC(("sxrom_w, offset: %04x, data: %02x\n", offset, data));
1109		common_sxrom_write_handler(space, offset, data, state->m_pcb_id);
	1107	common_sxrom_write_handler(space, offset, data, m_pcb_id);
1110	1108	}
1111	1109
1112	1110	/*************************************************************
r18063	r18064
1150	1148	}
1151	1149	}
1152	1150
1153		static WRITE8_HANDLER( pxrom_w )
	1151	WRITE8_MEMBER(nes_state::pxrom_w)
1154	1152	{
1155		nes_state *state = space.machine().driver_data<nes_state>();
1156	1153	LOG_MMC(("pxrom_w, offset: %04x, data: %02x\n", offset, data));
1157	1154	switch (offset & 0x7000)
1158	1155	{
1159	1156	case 0x2000:
1160		prg8_89(space.machine(), data);
	1157	prg8_89(machine(), data);
1161	1158	break;
1162	1159	case 0x3000:
1163		state->m_mmc_reg[0] = data;
1164		if (state->m_mmc_latch1 == 0xfd)
1165		chr4_0(space.machine(), state->m_mmc_reg[0], CHRROM);
	1160	m_mmc_reg[0] = data;
	1161	if (m_mmc_latch1 == 0xfd)
	1162	chr4_0(machine(), m_mmc_reg[0], CHRROM);
1166	1163	break;
1167	1164	case 0x4000:
1168		state->m_mmc_reg[1] = data;
1169		if (state->m_mmc_latch1 == 0xfe)
1170		chr4_0(space.machine(), state->m_mmc_reg[1], CHRROM);
	1165	m_mmc_reg[1] = data;
	1166	if (m_mmc_latch1 == 0xfe)
	1167	chr4_0(machine(), m_mmc_reg[1], CHRROM);
1171	1168	break;
1172	1169	case 0x5000:
1173		state->m_mmc_reg[2] = data;
1174		if (state->m_mmc_latch2 == 0xfd)
1175		chr4_4(space.machine(), state->m_mmc_reg[2], CHRROM);
	1170	m_mmc_reg[2] = data;
	1171	if (m_mmc_latch2 == 0xfd)
	1172	chr4_4(machine(), m_mmc_reg[2], CHRROM);
1176	1173	break;
1177	1174	case 0x6000:
1178		state->m_mmc_reg[3] = data;
1179		if (state->m_mmc_latch2 == 0xfe)
1180		chr4_4(space.machine(), state->m_mmc_reg[3], CHRROM);
	1175	m_mmc_reg[3] = data;
	1176	if (m_mmc_latch2 == 0xfe)
	1177	chr4_4(machine(), m_mmc_reg[3], CHRROM);
1181	1178	break;
1182	1179	case 0x7000:
1183		set_nt_mirroring(space.machine(), BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	1180	set_nt_mirroring(machine(), BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
1184	1181	break;
1185	1182	default:
1186	1183	LOG_MMC(("MMC2 uncaught w: %04x:%02x\n", offset, data));
r18063	r18064
1200	1197
1201	1198	*************************************************************/
1202	1199
1203		static WRITE8_HANDLER( fxrom_w )
	1200	WRITE8_MEMBER(nes_state::fxrom_w)
1204	1201	{
1205	1202	LOG_MMC(("fxrom_w, offset: %04x, data: %02x\n", offset, data));
1206	1203	switch (offset & 0x7000)
1207	1204	{
1208	1205	case 0x2000:
1209		prg16_89ab(space.machine(), data);
	1206	prg16_89ab(machine(), data);
1210	1207	break;
1211	1208	default:
1212	1209	pxrom_w(space, offset, data, mem_mask);
r18063	r18064
1228	1225	nes_state *state = machine.driver_data<nes_state>();
1229	1226
1230	1227	// skip this function if we are emulating a MMC3 clone with mid writes
1231		if (state->m_mmc_write_mid != NULL)
	1228	if (!state->m_mmc_write_mid.isnull())
1232	1229	return;
1233	1230
1234	1231	if (BIT(state->m_mmc3_wram_protect, 7))
r18063	r18064
1297	1294	state->m_IRQ_clear = 0;
1298	1295	}
1299	1296
1300		static WRITE8_HANDLER( txrom_w )
	1297	WRITE8_MEMBER(nes_state::txrom_w)
1301	1298	{
1302		nes_state *state = space.machine().driver_data<nes_state>();
1303	1299	UINT8 mmc_helper, cmd;
1304	1300
1305	1301	LOG_MMC(("txrom_w, offset: %04x, data: %02x\n", offset, data));
r18063	r18064
1307	1303	switch (offset & 0x6001)
1308	1304	{
1309	1305	case 0x0000:
1310		mmc_helper = state->m_mmc3_latch ^ data;
1311		state->m_mmc3_latch = data;
	1306	mmc_helper = m_mmc3_latch ^ data;
	1307	m_mmc3_latch = data;
1312	1308
1313	1309	/* Has PRG Mode changed? */
1314	1310	if (mmc_helper & 0x40)
1315		mmc3_set_prg(space.machine(), state->m_mmc_prg_base, state->m_mmc_prg_mask);
	1311	mmc3_set_prg(machine(), m_mmc_prg_base, m_mmc_prg_mask);
1316	1312
1317	1313	/* Has CHR Mode changed? */
1318	1314	if (mmc_helper & 0x80)
1319		mmc3_set_chr(space.machine(), state->m_mmc_chr_source, state->m_mmc_chr_base, state->m_mmc_chr_mask);
	1315	mmc3_set_chr(machine(), m_mmc_chr_source, m_mmc_chr_base, m_mmc_chr_mask);
1320	1316	break;
1321	1317
1322	1318	case 0x0001:
1323		cmd = state->m_mmc3_latch & 0x07;
	1319	cmd = m_mmc3_latch & 0x07;
1324	1320	switch (cmd)
1325	1321	{
1326	1322	case 0: case 1:   // these do not need to be separated: we take care of them in set_chr!
1327	1323	case 2: case 3: case 4: case 5:
1328		state->m_mmc_vrom_bank[cmd] = data;
1329		mmc3_set_chr(space.machine(), state->m_mmc_chr_source, state->m_mmc_chr_base, state->m_mmc_chr_mask);
	1324	m_mmc_vrom_bank[cmd] = data;
	1325	mmc3_set_chr(machine(), m_mmc_chr_source, m_mmc_chr_base, m_mmc_chr_mask);
1330	1326	break;
1331	1327	case 6:
1332	1328	case 7:
1333		state->m_mmc_prg_bank[cmd - 6] = data;
1334		mmc3_set_prg(space.machine(), state->m_mmc_prg_base, state->m_mmc_prg_mask);
	1329	m_mmc_prg_bank[cmd - 6] = data;
	1330	mmc3_set_prg(machine(), m_mmc_prg_base, m_mmc_prg_mask);
1335	1331	break;
1336	1332	}
1337	1333	break;
1338	1334
1339	1335	case 0x2000:
1340		set_nt_mirroring(space.machine(), BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	1336	set_nt_mirroring(machine(), BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
1341	1337	break;
1342	1338
1343	1339	case 0x2001:
1344		state->m_mmc3_wram_protect = data;
	1340	m_mmc3_wram_protect = data;
1345	1341	mmc3_set_wram(space);
1346	1342	break;
1347	1343
1348	1344	case 0x4000:
1349		state->m_IRQ_count_latch = data;
	1345	m_IRQ_count_latch = data;
1350	1346	break;
1351	1347
1352	1348	case 0x4001:
1353		state->m_IRQ_count = 0;
	1349	m_IRQ_count = 0;
1354	1350	break;
1355	1351
1356	1352	case 0x6000:
1357		state->m_IRQ_enable = 0;
	1353	m_IRQ_enable = 0;
1358	1354	break;
1359	1355
1360	1356	case 0x6001:
1361		state->m_IRQ_enable = 1;
	1357	m_IRQ_enable = 1;
1362	1358	break;
1363	1359
1364	1360	default:
r18063	r18064
1375	1371
1376	1372	*************************************************************/
1377	1373
1378		static WRITE8_HANDLER( hkrom_m_w )
	1374	WRITE8_MEMBER(nes_state::hkrom_m_w)
1379	1375	{
1380		nes_state *state = space.machine().driver_data<nes_state>();
1381	1376	UINT8 write_hi, write_lo;
1382	1377	LOG_MMC(("hkrom_m_w, offset: %04x, data: %02x\n", offset, data));
1383	1378
r18063	r18064
1385	1380	return;
1386	1381
1387	1382	// banks can be written only if both read & write is enabled!
1388		write_hi = ((state->m_mmc6_reg & 0xc0) == 0xc0);
1389		write_lo = ((state->m_mmc6_reg & 0x30) == 0x30);
	1383	write_hi = ((m_mmc6_reg & 0xc0) == 0xc0);
	1384	write_lo = ((m_mmc6_reg & 0x30) == 0x30);
1390	1385
1391	1386	if (BIT(offset, 9) && write_hi)   // access to upper 1k
1392		state->m_mapper_bram[offset & (state->m_mapper_bram_size - 1)] = data;
	1387	m_mapper_bram[offset & (m_mapper_bram_size - 1)] = data;
1393	1388
1394	1389	if (!BIT(offset, 9) && write_lo)   // access to lower 1k
1395		state->m_mapper_bram[offset & (state->m_mapper_bram_size - 1)] = data;
	1390	m_mapper_bram[offset & (m_mapper_bram_size - 1)] = data;
1396	1391	}
1397	1392
1398		static READ8_HANDLER( hkrom_m_r )
	1393	READ8_MEMBER(nes_state::hkrom_m_r)
1399	1394	{
1400		nes_state *state = space.machine().driver_data<nes_state>();
1401	1395	LOG_MMC(("hkrom_m_r, offset: %04x\n", offset));
1402	1396
1403	1397	if (offset < 0x1000)
1404	1398	return 0xff;   // here it should be open bus
1405	1399
1406		if (!(state->m_mmc6_reg & 0xa0))
	1400	if (!(m_mmc6_reg & 0xa0))
1407	1401	return 0xff;   // here it should be open bus
1408	1402
1409		if (BIT(offset, 9) && BIT(state->m_mmc6_reg, 7))   // access to upper 1k when upper read is enabled
1410		return state->m_mapper_bram[offset & (state->m_mapper_bram_size - 1)];
	1403	if (BIT(offset, 9) && BIT(m_mmc6_reg, 7))   // access to upper 1k when upper read is enabled
	1404	return m_mapper_bram[offset & (m_mapper_bram_size - 1)];
1411	1405
1412		if (!BIT(offset, 9) && BIT(state->m_mmc6_reg, 5))   // access to lower 1k when lower read is enabled
1413		return state->m_mapper_bram[offset & (state->m_mapper_bram_size - 1)];
	1406	if (!BIT(offset, 9) && BIT(m_mmc6_reg, 5))   // access to lower 1k when lower read is enabled
	1407	return m_mapper_bram[offset & (m_mapper_bram_size - 1)];
1414	1408
1415	1409	// If only one bank is enabled for reading, the other reads back as zero
1416	1410	return 0x00;
1417	1411	}
1418	1412
1419		static WRITE8_HANDLER( hkrom_w )
	1413	WRITE8_MEMBER(nes_state::hkrom_w)
1420	1414	{
1421		nes_state *state = space.machine().driver_data<nes_state>();
1422	1415	UINT8 mmc6_helper;
1423	1416	LOG_MMC(("hkrom_w, offset: %04x, data: %02x\n", offset, data));
1424	1417
1425	1418	switch (offset & 0x6001)
1426	1419	{
1427	1420	case 0x0000:
1428		mmc6_helper = state->m_mmc3_latch ^ data;
1429		state->m_mmc3_latch = data;
	1421	mmc6_helper = m_mmc3_latch ^ data;
	1422	m_mmc3_latch = data;
1430	1423
1431		if (!state->m_mmc_latch2 && BIT(data, 5))   // if WRAM is disabled and has to be enabled, write
1432		state->m_mmc_latch2 = BIT(data, 5);   // (once WRAM has been enabled, it cannot be disabled without resetting the game)
	1424	if (!m_mmc_latch2 && BIT(data, 5))   // if WRAM is disabled and has to be enabled, write
	1425	m_mmc_latch2 = BIT(data, 5);   // (once WRAM has been enabled, it cannot be disabled without resetting the game)
1433	1426
1434	1427	/* Has PRG Mode changed? */
1435	1428	if (BIT(mmc6_helper, 6))
1436		mmc3_set_prg(space.machine(), state->m_mmc_prg_base, state->m_mmc_prg_mask);
	1429	mmc3_set_prg(machine(), m_mmc_prg_base, m_mmc_prg_mask);
1437	1430
1438	1431	/* Has CHR Mode changed? */
1439	1432	if (BIT(mmc6_helper, 7))
1440		mmc3_set_chr(space.machine(), state->m_mmc_chr_source, state->m_mmc_chr_base, state->m_mmc_chr_mask);
	1433	mmc3_set_chr(machine(), m_mmc_chr_source, m_mmc_chr_base, m_mmc_chr_mask);
1441	1434	break;
1442	1435
1443	1436	case 0x2001:
1444		if (state->m_mmc_latch2)
1445		state->m_mmc6_reg = data;
	1437	if (m_mmc_latch2)
	1438	m_mmc6_reg = data;
1446	1439	break;
1447	1440
1448	1441	case 0x4001:
1449		state->m_IRQ_count = 0;
1450		state->m_IRQ_clear = 1;
	1442	m_IRQ_count = 0;
	1443	m_IRQ_clear = 1;
1451	1444	break;
1452	1445
1453	1446	default:
r18063	r18064
1494	1487	chr1_x(machine, start, bank, source);
1495	1488	}
1496	1489
1497		static WRITE8_HANDLER( txsrom_w )
	1490	WRITE8_MEMBER(nes_state::txsrom_w)
1498	1491	{
1499	1492	LOG_MMC(("txsrom_w, offset: %04x, data: %02x\n", offset, data));
1500	1493
r18063	r18064
1544	1537	chr1_x(machine, chr_page ^ 7, (state->m_mmc_vrom_bank[5] & chr_mask[5]), chr_src[5]);
1545	1538	}
1546	1539
1547		static WRITE8_HANDLER( tqrom_w )
	1540	WRITE8_MEMBER(nes_state::tqrom_w)
1548	1541	{
1549		nes_state *state = space.machine().driver_data<nes_state>();
1550	1542	UINT8 mmc_helper, cmd;
1551	1543	LOG_MMC(("tqrom_w, offset: %04x, data: %02x\n", offset, data));
1552	1544
1553	1545	switch (offset & 0x6001)
1554	1546	{
1555	1547	case 0x0000:
1556		mmc_helper = state->m_mmc3_latch ^ data;
1557		state->m_mmc3_latch = data;
	1548	mmc_helper = m_mmc3_latch ^ data;
	1549	m_mmc3_latch = data;
1558	1550
1559	1551	/* Has PRG Mode changed? */
1560	1552	if (mmc_helper & 0x40)
1561		mmc3_set_prg(space.machine(), state->m_mmc_prg_base, state->m_mmc_prg_mask);
	1553	mmc3_set_prg(machine(), m_mmc_prg_base, m_mmc_prg_mask);
1562	1554
1563	1555	/* Has CHR Mode changed? */
1564	1556	if (mmc_helper & 0x80)
1565		tqrom_set_chr(space.machine());
	1557	tqrom_set_chr(machine());
1566	1558	break;
1567	1559	case 0x0001: /* $8001 */
1568		cmd = state->m_mmc3_latch & 0x07;
	1560	cmd = m_mmc3_latch & 0x07;
1569	1561	switch (cmd)
1570	1562	{
1571	1563	case 0: case 1:   // these do not need to be separated: we take care of them in set_chr!
1572	1564	case 2: case 3: case 4: case 5:
1573		state->m_mmc_vrom_bank[cmd] = data;
1574		tqrom_set_chr(space.machine());
	1565	m_mmc_vrom_bank[cmd] = data;
	1566	tqrom_set_chr(machine());
1575	1567	break;
1576	1568	case 6:
1577	1569	case 7:
1578		state->m_mmc_prg_bank[cmd - 6] = data;
1579		mmc3_set_prg(space.machine(), state->m_mmc_prg_base, state->m_mmc_prg_mask);
	1570	m_mmc_prg_bank[cmd - 6] = data;
	1571	mmc3_set_prg(machine(), m_mmc_prg_base, m_mmc_prg_mask);
1580	1572	break;
1581	1573	}
1582	1574	break;
r18063	r18064
1596	1588
1597	1589	*************************************************************/
1598	1590
1599		static WRITE8_HANDLER( zz_m_w )
	1591	WRITE8_MEMBER(nes_state::zz_m_w)
1600	1592	{
1601		nes_state *state = space.machine().driver_data<nes_state>();
1602	1593	UINT8 mmc_helper = data & 0x07;
1603	1594	LOG_MMC(("zz_m_w, offset: %04x, data: %02x\n", offset, data));
1604	1595
1605		state->m_mmc_prg_base = (BIT(mmc_helper, 2) << 4) | (((mmc_helper & 0x03) == 0x03) ? 0x08 : 0);
1606		state->m_mmc_prg_mask = (mmc_helper << 1) | 0x07;
1607		state->m_mmc_chr_base = BIT(mmc_helper, 2) << 7;
1608		state->m_mmc_chr_mask = 0x7f;
1609		mmc3_set_prg(space.machine(), state->m_mmc_prg_base, state->m_mmc_prg_mask);
1610		mmc3_set_chr(space.machine(), state->m_mmc_chr_source, state->m_mmc_chr_base, state->m_mmc_chr_mask);
	1596	m_mmc_prg_base = (BIT(mmc_helper, 2) << 4) | (((mmc_helper & 0x03) == 0x03) ? 0x08 : 0);
	1597	m_mmc_prg_mask = (mmc_helper << 1) | 0x07;
	1598	m_mmc_chr_base = BIT(mmc_helper, 2) << 7;
	1599	m_mmc_chr_mask = 0x7f;
	1600	mmc3_set_prg(machine(), m_mmc_prg_base, m_mmc_prg_mask);
	1601	mmc3_set_chr(machine(), m_mmc_chr_source, m_mmc_chr_base, m_mmc_chr_mask);
1611	1602	}
1612	1603
1613	1604	/*************************************************************
r18063	r18064
1619	1610
1620	1611	*************************************************************/
1621	1612
1622		static WRITE8_HANDLER( qj_m_w )
	1613	WRITE8_MEMBER(nes_state::qj_m_w)
1623	1614	{
1624		nes_state *state = space.machine().driver_data<nes_state>();
1625	1615	LOG_MMC(("qj_m_w, offset: %04x, data: %02x\n", offset, data));
1626	1616
1627		state->m_mmc_prg_base = BIT(data, 0) << 4;
1628		state->m_mmc_prg_mask = 0x0f;
1629		state->m_mmc_chr_base = BIT(data, 0) << 7;
1630		state->m_mmc_chr_mask = 0x7f;
1631		mmc3_set_prg(space.machine(), state->m_mmc_prg_base, state->m_mmc_prg_mask);
1632		mmc3_set_chr(space.machine(), state->m_mmc_chr_source, state->m_mmc_chr_base, state->m_mmc_chr_mask);
	1617	m_mmc_prg_base = BIT(data, 0) << 4;
	1618	m_mmc_prg_mask = 0x0f;
	1619	m_mmc_chr_base = BIT(data, 0) << 7;
	1620	m_mmc_chr_mask = 0x7f;
	1621	mmc3_set_prg(machine(), m_mmc_prg_base, m_mmc_prg_mask);
	1622	mmc3_set_chr(machine(), m_mmc_chr_source, m_mmc_chr_base, m_mmc_chr_mask);
1633	1623	}
1634	1624
1635	1625	/*************************************************************
r18063	r18064
1856	1846	}
1857	1847	}
1858	1848
1859		static READ8_HANDLER( exrom_l_r )
	1849	READ8_MEMBER(nes_state::exrom_l_r)
1860	1850	{
1861		nes_state *state = space.machine().driver_data<nes_state>();
1862	1851	int retVal;
1863	1852
1864	1853	/* $5c00 - $5fff: extended videoram attributes */
1865	1854	if ((offset >= 0x1b00) && (offset <= 0x1eff))
1866	1855	{
1867		return state->m_mapper_ram[offset - 0x1b00];
	1856	return m_mapper_ram[offset - 0x1b00];
1868	1857	}
1869	1858
1870	1859	switch (offset)
r18063	r18064
1876	1865	else
1877	1866	return 0x00;
1878	1867	#else
1879		retVal = state->m_IRQ_status;
1880		state->m_IRQ_status &= ~0x80;
	1868	retVal = m_IRQ_status;
	1869	m_IRQ_status &= ~0x80;
1881	1870	return retVal;
1882	1871	#endif
1883	1872
1884	1873	case 0x1105: /* $5205 */
1885		return (state->m_mult1 * state->m_mult2) & 0xff;
	1874	return (m_mult1 * m_mult2) & 0xff;
1886	1875	case 0x1106: /* $5206 */
1887		return ((state->m_mult1 * state->m_mult2) & 0xff00) >> 8;
	1876	return ((m_mult1 * m_mult2) & 0xff00) >> 8;
1888	1877
1889	1878	default:
1890	1879	logerror("** MMC5 uncaught read, offset: %04x\n", offset + 0x4100);
r18063	r18064
1893	1882	}
1894	1883
1895	1884
1896		static WRITE8_HANDLER( exrom_l_w )
	1885	WRITE8_MEMBER(nes_state::exrom_l_w)
1897	1886	{
1898		nes_state *state = space.machine().driver_data<nes_state>();
1899	1887
1900	1888	//  LOG_MMC(("Mapper 5 write, offset: %04x, data: %02x\n", offset + 0x4100, data));
1901	1889	/* Send $5000-$5015 to the sound chip */
1902	1890	if ((offset >= 0xf00) && (offset <= 0xf15))
1903	1891	{
1904		nes_psg_w(state->m_sound, space, offset & 0x1f, data);
	1892	nes_psg_w(m_sound, space, offset & 0x1f, data);
1905	1893	return;
1906	1894	}
1907	1895
1908	1896	/* $5c00 - $5fff: extended videoram attributes */
1909	1897	if ((offset >= 0x1b00) && (offset <= 0x1eff))
1910	1898	{
1911		if (state->m_MMC5_vram_protect == 0x03)
1912		state->m_mapper_ram[offset - 0x1b00] = data;
	1899	if (m_MMC5_vram_protect == 0x03)
	1900	m_mapper_ram[offset - 0x1b00] = data;
1913	1901	return;
1914	1902	}
1915	1903
1916	1904	switch (offset)
1917	1905	{
1918	1906	case 0x1000: /* $5100 */
1919		state->m_mmc5_prg_mode = data & 0x03;
1920		//          mmc5_update_prg(space.machine());
	1907	m_mmc5_prg_mode = data & 0x03;
	1908	//          mmc5_update_prg(machine());
1921	1909	LOG_MMC(("MMC5 rom bank mode: %02x\n", data));
1922	1910	break;
1923	1911
1924	1912	case 0x1001: /* $5101 */
1925		state->m_mmc5_chr_mode = data & 0x03;
	1913	m_mmc5_chr_mode = data & 0x03;
1926	1914	// update chr
1927	1915	LOG_MMC(("MMC5 vrom bank mode: %02x\n", data));
1928	1916	break;
1929	1917
1930	1918	case 0x1002: /* $5102 */
1931	1919	if (data == 0x02)
1932		state->m_MMC5_vram_protect |= 1;
	1920	m_MMC5_vram_protect |= 1;
1933	1921	else
1934		state->m_MMC5_vram_protect = 0;
	1922	m_MMC5_vram_protect = 0;
1935	1923	LOG_MMC(("MMC5 vram protect 1: %02x\n", data));
1936	1924	break;
1937	1925	case 0x1003: /* 5103 */
1938	1926	if (data == 0x01)
1939		state->m_MMC5_vram_protect |= 2;
	1927	m_MMC5_vram_protect |= 2;
1940	1928	else
1941		state->m_MMC5_vram_protect = 0;
	1929	m_MMC5_vram_protect = 0;
1942	1930	LOG_MMC(("MMC5 vram protect 2: %02x\n", data));
1943	1931	break;
1944	1932
1945	1933	case 0x1004: /* $5104 - Extra VRAM (EXRAM) control */
1946		state->m_mmc5_vram_control = data & 0x03;
	1934	m_mmc5_vram_control = data & 0x03;
1947	1935	// update render
1948		mmc5_update_render_mode(space.machine());
	1936	mmc5_update_render_mode(machine());
1949	1937	LOG_MMC(("MMC5 exram control: %02x\n", data));
1950	1938	break;
1951	1939
1952	1940	case 0x1005: /* $5105 */
1953		mmc5_ppu_mirror(space.machine(), 0, data & 0x03);
1954		mmc5_ppu_mirror(space.machine(), 1, (data & 0x0c) >> 2);
1955		mmc5_ppu_mirror(space.machine(), 2, (data & 0x30) >> 4);
1956		mmc5_ppu_mirror(space.machine(), 3, (data & 0xc0) >> 6);
	1941	mmc5_ppu_mirror(machine(), 0, data & 0x03);
	1942	mmc5_ppu_mirror(machine(), 1, (data & 0x0c) >> 2);
	1943	mmc5_ppu_mirror(machine(), 2, (data & 0x30) >> 4);
	1944	mmc5_ppu_mirror(machine(), 3, (data & 0xc0) >> 6);
1957	1945	// update render
1958		mmc5_update_render_mode(space.machine());
	1946	mmc5_update_render_mode(machine());
1959	1947	break;
1960	1948
1961	1949	/* tile data for MMC5 flood-fill NT mode */
1962	1950	case 0x1006:
1963		state->m_MMC5_floodtile = data;
	1951	m_MMC5_floodtile = data;
1964	1952	break;
1965	1953
1966	1954	/* attr data for MMC5 flood-fill NT mode */
r18063	r18064
1968	1956	switch (data & 3)
1969	1957	{
1970	1958	default:
1971		case 0: state->m_MMC5_floodattr = 0x00; break;
1972		case 1: state->m_MMC5_floodattr = 0x55; break;
1973		case 2: state->m_MMC5_floodattr = 0xaa; break;
1974		case 3: state->m_MMC5_floodattr = 0xff; break;
	1959	case 0: m_MMC5_floodattr = 0x00; break;
	1960	case 1: m_MMC5_floodattr = 0x55; break;
	1961	case 2: m_MMC5_floodattr = 0xaa; break;
	1962	case 3: m_MMC5_floodattr = 0xff; break;
1975	1963	}
1976	1964	break;
1977	1965
1978	1966	case 0x1013: /* $5113 */
1979	1967	LOG_MMC(("MMC5 mid RAM bank select: %02x\n", data & 0x07));
1980	1968	// FIXME: a few Koei games have both WRAM & BWRAM but here we don't support this (yet)
1981		if (state->m_battery)
1982		wram_bank(space.machine(), data, NES_BATTERY);
	1969	if (m_battery)
	1970	wram_bank(machine(), data, NES_BATTERY);
1983	1971	else
1984		wram_bank(space.machine(), data, NES_WRAM);
	1972	wram_bank(machine(), data, NES_WRAM);
1985	1973	break;
1986	1974
1987	1975
r18063	r18064
1989	1977	case 0x1015: /* $5115 */
1990	1978	case 0x1016: /* $5116 */
1991	1979	case 0x1017: /* $5117 */
1992		state->m_mmc5_prg_regs[offset & 3] = data;
1993		mmc5_update_prg(space.machine());
	1980	m_mmc5_prg_regs[offset & 3] = data;
	1981	mmc5_update_prg(machine());
1994	1982	break;
1995	1983
1996	1984	#if 0
r18063	r18064
2003	1991	case 0x1025: /* $5125 */
2004	1992	case 0x1026: /* $5126 */
2005	1993	case 0x1027: /* $5127 */
2006		data |= (state->m_mmc5_chr_high << 8);
2007		if (!state->m_mmc5_last_chr_a)
	1994	data |= (m_mmc5_chr_high << 8);
	1995	if (!m_mmc5_last_chr_a)
2008	1996	{
2009		state->m_mmc5_vrom_regA[offset & 0x07] = data;
2010		state->m_mmc5_last_chr_a = 1;
2011		if (state->m_ppu->get_current_scanline() == 240 || !state->m_ppu->is_sprite_8x16())
2012		mmc5_update_chr_a(space.machine());
	1997	m_mmc5_vrom_regA[offset & 0x07] = data;
	1998	m_mmc5_last_chr_a = 1;
	1999	if (m_ppu->get_current_scanline() == 240 || !m_ppu->is_sprite_8x16())
	2000	mmc5_update_chr_a(machine());
2013	2001	}
2014	2002	break;
2015	2003
r18063	r18064
2018	2006	case 0x1029: /* $5129 */
2019	2007	case 0x102a: /* $512a */
2020	2008	case 0x102b: /* $512b */
2021		data |= (state->m_mmc5_chr_high << 8);
2022		state->m_mmc5_vrom_regB[offset & 0x03] = data;
2023		state->m_mmc5_last_chr_a = 0;
2024		if (state->m_ppu->get_current_scanline() == 240 || !state->m_ppu->is_sprite_8x16())
2025		mmc5_update_chr_b(space.machine());
	2009	data |= (m_mmc5_chr_high << 8);
	2010	m_mmc5_vrom_regB[offset & 0x03] = data;
	2011	m_mmc5_last_chr_a = 0;
	2012	if (m_ppu->get_current_scanline() == 240 || !m_ppu->is_sprite_8x16())
	2013	mmc5_update_chr_b(machine());
2026	2014	break;
2027	2015
2028	2016	case 0x1030: /* $5130 */
2029		state->m_mmc5_chr_high = data & 0x03;
2030		if (state->m_mmc5_vram_control == 1)
	2017	m_mmc5_chr_high = data & 0x03;
	2018	if (m_mmc5_vram_control == 1)
2031	2019	{
2032		// in this case state->m_mmc5_chr_high selects which 256KB of CHR ROM
	2020	// in this case m_mmc5_chr_high selects which 256KB of CHR ROM
2033	2021	// is to be used for all background tiles on the screen.
2034	2022	}
2035	2023	break;
r18063	r18064
2037	2025	#endif
2038	2026
2039	2027	case 0x1020: /* $5120 */
2040		LOG_MMC(("MMC5 $5120 vrom select: %02x (mode: %d)\n", data, state->m_mmc5_chr_mode));
2041		switch (state->m_mmc5_chr_mode)
	2028	LOG_MMC(("MMC5 $5120 vrom select: %02x (mode: %d)\n", data, m_mmc5_chr_mode));
	2029	switch (m_mmc5_chr_mode)
2042	2030	{
2043	2031	case 0x03:
2044	2032	/* 1k switch */
2045		state->m_MMC5_vrom_bank[0] = data | (state->m_mmc5_high_chr << 8);
	2033	m_MMC5_vrom_bank[0] = data | (m_mmc5_high_chr << 8);
2046	2034	//                  mapper5_sync_vrom(0);
2047		chr1_0(space.machine(), state->m_MMC5_vrom_bank[0], CHRROM);
2048		//                  state->m_nes_vram_sprite[0] = state->m_MMC5_vrom_bank[0] * 64;
	2035	chr1_0(machine(), m_MMC5_vrom_bank[0], CHRROM);
	2036	//                  m_nes_vram_sprite[0] = m_MMC5_vrom_bank[0] * 64;
2049	2037	//                  vrom_next[0] = 4;
2050	2038	//                  vrom_page_a = 1;
2051	2039	//                  vrom_page_b = 0;
r18063	r18064
2053	2041	}
2054	2042	break;
2055	2043	case 0x1021: /* $5121 */
2056		LOG_MMC(("MMC5 $5121 vrom select: %02x (mode: %d)\n", data, state->m_mmc5_chr_mode));
2057		switch (state->m_mmc5_chr_mode)
	2044	LOG_MMC(("MMC5 $5121 vrom select: %02x (mode: %d)\n", data, m_mmc5_chr_mode));
	2045	switch (m_mmc5_chr_mode)
2058	2046	{
2059	2047	case 0x02:
2060	2048	/* 2k switch */
2061		chr2_0(space.machine(), data | (state->m_mmc5_high_chr << 8), CHRROM);
	2049	chr2_0(machine(), data | (m_mmc5_high_chr << 8), CHRROM);
2062	2050	break;
2063	2051	case 0x03:
2064	2052	/* 1k switch */
2065		state->m_MMC5_vrom_bank[1] = data | (state->m_mmc5_high_chr << 8);
	2053	m_MMC5_vrom_bank[1] = data | (m_mmc5_high_chr << 8);
2066	2054	//                  mapper5_sync_vrom(0);
2067		chr1_1(space.machine(), state->m_MMC5_vrom_bank[1], CHRROM);
2068		//                  state->m_nes_vram_sprite[1] = state->m_MMC5_vrom_bank[0] * 64;
	2055	chr1_1(machine(), m_MMC5_vrom_bank[1], CHRROM);
	2056	//                  m_nes_vram_sprite[1] = m_MMC5_vrom_bank[0] * 64;
2069	2057	//                  vrom_next[1] = 5;
2070	2058	//                  vrom_page_a = 1;
2071	2059	//                  vrom_page_b = 0;
r18063	r18064
2073	2061	}
2074	2062	break;
2075	2063	case 0x1022: /* $5122 */
2076		LOG_MMC(("MMC5 $5122 vrom select: %02x (mode: %d)\n", data, state->m_mmc5_chr_mode));
2077		switch (state->m_mmc5_chr_mode)
	2064	LOG_MMC(("MMC5 $5122 vrom select: %02x (mode: %d)\n", data, m_mmc5_chr_mode));
	2065	switch (m_mmc5_chr_mode)
2078	2066	{
2079	2067	case 0x03:
2080	2068	/* 1k switch */
2081		state->m_MMC5_vrom_bank[2] = data | (state->m_mmc5_high_chr << 8);
	2069	m_MMC5_vrom_bank[2] = data | (m_mmc5_high_chr << 8);
2082	2070	//                  mapper5_sync_vrom(0);
2083		chr1_2(space.machine(), state->m_MMC5_vrom_bank[2], CHRROM);
2084		//                  state->m_nes_vram_sprite[2] = state->m_MMC5_vrom_bank[0] * 64;
	2071	chr1_2(machine(), m_MMC5_vrom_bank[2], CHRROM);
	2072	//                  m_nes_vram_sprite[2] = m_MMC5_vrom_bank[0] * 64;
2085	2073	//                  vrom_next[2] = 6;
2086	2074	//                  vrom_page_a = 1;
2087	2075	//                  vrom_page_b = 0;
r18063	r18064
2089	2077	}
2090	2078	break;
2091	2079	case 0x1023: /* $5123 */
2092		LOG_MMC(("MMC5 $5123 vrom select: %02x (mode: %d)\n", data, state->m_mmc5_chr_mode));
2093		switch (state->m_mmc5_chr_mode)
	2080	LOG_MMC(("MMC5 $5123 vrom select: %02x (mode: %d)\n", data, m_mmc5_chr_mode));
	2081	switch (m_mmc5_chr_mode)
2094	2082	{
2095	2083	case 0x01:
2096		chr4_0(space.machine(), data, CHRROM);
	2084	chr4_0(machine(), data, CHRROM);
2097	2085	break;
2098	2086	case 0x02:
2099	2087	/* 2k switch */
2100		chr2_2(space.machine(), data | (state->m_mmc5_high_chr << 8), CHRROM);
	2088	chr2_2(machine(), data | (m_mmc5_high_chr << 8), CHRROM);
2101	2089	break;
2102	2090	case 0x03:
2103	2091	/* 1k switch */
2104		state->m_MMC5_vrom_bank[3] = data | (state->m_mmc5_high_chr << 8);
	2092	m_MMC5_vrom_bank[3] = data | (m_mmc5_high_chr << 8);
2105	2093	//                  mapper5_sync_vrom(0);
2106		chr1_3(space.machine(), state->m_MMC5_vrom_bank[3], CHRROM);
2107		//                  state->m_nes_vram_sprite[3] = state->m_MMC5_vrom_bank[0] * 64;
	2094	chr1_3(machine(), m_MMC5_vrom_bank[3], CHRROM);
	2095	//                  m_nes_vram_sprite[3] = m_MMC5_vrom_bank[0] * 64;
2108	2096	//                  vrom_next[3] = 7;
2109	2097	//                  vrom_page_a = 1;
2110	2098	//                  vrom_page_b = 0;
r18063	r18064
2112	2100	}
2113	2101	break;
2114	2102	case 0x1024: /* $5124 */
2115		LOG_MMC(("MMC5 $5124 vrom select: %02x (mode: %d)\n", data, state->m_mmc5_chr_mode));
2116		switch (state->m_mmc5_chr_mode)
	2103	LOG_MMC(("MMC5 $5124 vrom select: %02x (mode: %d)\n", data, m_mmc5_chr_mode));
	2104	switch (m_mmc5_chr_mode)
2117	2105	{
2118	2106	case 0x03:
2119	2107	/* 1k switch */
2120		state->m_MMC5_vrom_bank[4] = data | (state->m_mmc5_high_chr << 8);
	2108	m_MMC5_vrom_bank[4] = data | (m_mmc5_high_chr << 8);
2121	2109	//                  mapper5_sync_vrom(0);
2122		chr1_4(space.machine(), state->m_MMC5_vrom_bank[4], CHRROM);
2123		//                  state->m_nes_vram_sprite[4] = state->m_MMC5_vrom_bank[0] * 64;
	2110	chr1_4(machine(), m_MMC5_vrom_bank[4], CHRROM);
	2111	//                  m_nes_vram_sprite[4] = m_MMC5_vrom_bank[0] * 64;
2124	2112	//                  vrom_next[0] = 0;
2125	2113	//                  vrom_page_a = 0;
2126	2114	//                  vrom_page_b = 0;
r18063	r18064
2128	2116	}
2129	2117	break;
2130	2118	case 0x1025: /* $5125 */
2131		LOG_MMC(("MMC5 $5125 vrom select: %02x (mode: %d)\n", data, state->m_mmc5_chr_mode));
2132		switch (state->m_mmc5_chr_mode)
	2119	LOG_MMC(("MMC5 $5125 vrom select: %02x (mode: %d)\n", data, m_mmc5_chr_mode));
	2120	switch (m_mmc5_chr_mode)
2133	2121	{
2134	2122	case 0x02:
2135	2123	/* 2k switch */
2136		chr2_4(space.machine(), data | (state->m_mmc5_high_chr << 8), CHRROM);
	2124	chr2_4(machine(), data | (m_mmc5_high_chr << 8), CHRROM);
2137	2125	break;
2138	2126	case 0x03:
2139	2127	/* 1k switch */
2140		state->m_MMC5_vrom_bank[5] = data | (state->m_mmc5_high_chr << 8);
	2128	m_MMC5_vrom_bank[5] = data | (m_mmc5_high_chr << 8);
2141	2129	//                  mapper5_sync_vrom(0);
2142		chr1_5(space.machine(), state->m_MMC5_vrom_bank[5], CHRROM);
2143		//                  state->m_nes_vram_sprite[5] = state->m_MMC5_vrom_bank[0] * 64;
	2130	chr1_5(machine(), m_MMC5_vrom_bank[5], CHRROM);
	2131	//                  m_nes_vram_sprite[5] = m_MMC5_vrom_bank[0] * 64;
2144	2132	//                  vrom_next[1] = 1;
2145	2133	//                  vrom_page_a = 0;
2146	2134	//                  vrom_page_b = 0;
r18063	r18064
2148	2136	}
2149	2137	break;
2150	2138	case 0x1026: /* $5126 */
2151		LOG_MMC(("MMC5 $5126 vrom select: %02x (mode: %d)\n", data, state->m_mmc5_chr_mode));
2152		switch (state->m_mmc5_chr_mode)
	2139	LOG_MMC(("MMC5 $5126 vrom select: %02x (mode: %d)\n", data, m_mmc5_chr_mode));
	2140	switch (m_mmc5_chr_mode)
2153	2141	{
2154	2142	case 0x03:
2155	2143	/* 1k switch */
2156		state->m_MMC5_vrom_bank[6] = data | (state->m_mmc5_high_chr << 8);
	2144	m_MMC5_vrom_bank[6] = data | (m_mmc5_high_chr << 8);
2157	2145	//                  mapper5_sync_vrom(0);
2158		chr1_6(space.machine(), state->m_MMC5_vrom_bank[6], CHRROM);
2159		//                  state->m_nes_vram_sprite[6] = state->m_MMC5_vrom_bank[0] * 64;
	2146	chr1_6(machine(), m_MMC5_vrom_bank[6], CHRROM);
	2147	//                  m_nes_vram_sprite[6] = m_MMC5_vrom_bank[0] * 64;
2160	2148	//                  vrom_next[2] = 2;
2161	2149	//                  vrom_page_a = 0;
2162	2150	//                  vrom_page_b = 0;
r18063	r18064
2164	2152	}
2165	2153	break;
2166	2154	case 0x1027: /* $5127 */
2167		LOG_MMC(("MMC5 $5127 vrom select: %02x (mode: %d)\n", data, state->m_mmc5_chr_mode));
2168		switch (state->m_mmc5_chr_mode)
	2155	LOG_MMC(("MMC5 $5127 vrom select: %02x (mode: %d)\n", data, m_mmc5_chr_mode));
	2156	switch (m_mmc5_chr_mode)
2169	2157	{
2170	2158	case 0x00:
2171	2159	/* 8k switch */
2172		chr8(space.machine(), data, CHRROM);
	2160	chr8(machine(), data, CHRROM);
2173	2161	break;
2174	2162	case 0x01:
2175	2163	/* 4k switch */
2176		chr4_4(space.machine(), data, CHRROM);
	2164	chr4_4(machine(), data, CHRROM);
2177	2165	break;
2178	2166	case 0x02:
2179	2167	/* 2k switch */
2180		chr2_6(space.machine(), data | (state->m_mmc5_high_chr << 8), CHRROM);
	2168	chr2_6(machine(), data | (m_mmc5_high_chr << 8), CHRROM);
2181	2169	break;
2182	2170	case 0x03:
2183	2171	/* 1k switch */
2184		state->m_MMC5_vrom_bank[7] = data | (state->m_mmc5_high_chr << 8);
	2172	m_MMC5_vrom_bank[7] = data | (m_mmc5_high_chr << 8);
2185	2173	//                  mapper5_sync_vrom(0);
2186		chr1_7(space.machine(), state->m_MMC5_vrom_bank[7], CHRROM);
2187		//                  state->m_nes_vram_sprite[7] = state->m_MMC5_vrom_bank[0] * 64;
	2174	chr1_7(machine(), m_MMC5_vrom_bank[7], CHRROM);
	2175	//                  m_nes_vram_sprite[7] = m_MMC5_vrom_bank[0] * 64;
2188	2176	//                  vrom_next[3] = 3;
2189	2177	//                  vrom_page_a = 0;
2190	2178	//                  vrom_page_b = 0;
r18063	r18064
2192	2180	}
2193	2181	break;
2194	2182	case 0x1028: /* $5128 */
2195		LOG_MMC(("MMC5 $5128 vrom select: %02x (mode: %d)\n", data, state->m_mmc5_chr_mode));
2196		switch (state->m_mmc5_chr_mode)
	2183	LOG_MMC(("MMC5 $5128 vrom select: %02x (mode: %d)\n", data, m_mmc5_chr_mode));
	2184	switch (m_mmc5_chr_mode)
2197	2185	{
2198	2186	case 0x03:
2199	2187	/* 1k switch */
2200		state->m_MMC5_vrom_bank[8] = data | (state->m_mmc5_high_chr << 8);
	2188	m_MMC5_vrom_bank[8] = data | (m_mmc5_high_chr << 8);
2201	2189	//                  nes_vram[vrom_next[0]] = data * 64;
2202	2190	//                  nes_vram[0 + (vrom_page_a*4)] = data * 64;
2203	2191	//                  nes_vram[0] = data * 64;
2204		chr1_4(space.machine(), state->m_MMC5_vrom_bank[8], CHRROM);
	2192	chr1_4(machine(), m_MMC5_vrom_bank[8], CHRROM);
2205	2193	//                  mapper5_sync_vrom(1);
2206		if (!state->m_vrom_page_b)
	2194	if (!m_vrom_page_b)
2207	2195	{
2208		state->m_vrom_page_a ^= 0x01;
2209		state->m_vrom_page_b = 1;
	2196	m_vrom_page_a ^= 0x01;
	2197	m_vrom_page_b = 1;
2210	2198	}
2211	2199	break;
2212	2200	}
2213	2201	break;
2214	2202	case 0x1029: /* $5129 */
2215		LOG_MMC(("MMC5 $5129 vrom select: %02x (mode: %d)\n", data, state->m_mmc5_chr_mode));
2216		switch (state->m_mmc5_chr_mode)
	2203	LOG_MMC(("MMC5 $5129 vrom select: %02x (mode: %d)\n", data, m_mmc5_chr_mode));
	2204	switch (m_mmc5_chr_mode)
2217	2205	{
2218	2206	case 0x02:
2219	2207	/* 2k switch */
2220		chr2_0(space.machine(), data | (state->m_mmc5_high_chr << 8), CHRROM);
2221		chr2_4(space.machine(), data | (state->m_mmc5_high_chr << 8), CHRROM);
	2208	chr2_0(machine(), data | (m_mmc5_high_chr << 8), CHRROM);
	2209	chr2_4(machine(), data | (m_mmc5_high_chr << 8), CHRROM);
2222	2210	break;
2223	2211	case 0x03:
2224	2212	/* 1k switch */
2225		state->m_MMC5_vrom_bank[9] = data | (state->m_mmc5_high_chr << 8);
	2213	m_MMC5_vrom_bank[9] = data | (m_mmc5_high_chr << 8);
2226	2214	//                  nes_vram[vrom_next[1]] = data * 64;
2227	2215	//                  nes_vram[1 + (vrom_page_a*4)] = data * 64;
2228	2216	//                  nes_vram[1] = data * 64;
2229		chr1_5(space.machine(), state->m_MMC5_vrom_bank[9], CHRROM);
	2217	chr1_5(machine(), m_MMC5_vrom_bank[9], CHRROM);
2230	2218	//                  mapper5_sync_vrom(1);
2231		if (!state->m_vrom_page_b)
	2219	if (!m_vrom_page_b)
2232	2220	{
2233		state->m_vrom_page_a ^= 0x01;
2234		state->m_vrom_page_b = 1;
	2221	m_vrom_page_a ^= 0x01;
	2222	m_vrom_page_b = 1;
2235	2223	}
2236	2224	break;
2237	2225	}
2238	2226	break;
2239	2227	case 0x102a: /* $512a */
2240		LOG_MMC(("MMC5 $512a vrom select: %02x (mode: %d)\n", data, state->m_mmc5_chr_mode));
2241		switch (state->m_mmc5_chr_mode)
	2228	LOG_MMC(("MMC5 $512a vrom select: %02x (mode: %d)\n", data, m_mmc5_chr_mode));
	2229	switch (m_mmc5_chr_mode)
2242	2230	{
2243	2231	case 0x03:
2244	2232	/* 1k switch */
2245		state->m_MMC5_vrom_bank[10] = data | (state->m_mmc5_high_chr << 8);
	2233	m_MMC5_vrom_bank[10] = data | (m_mmc5_high_chr << 8);
2246	2234	//                  nes_vram[vrom_next[2]] = data * 64;
2247	2235	//                  nes_vram[2 + (vrom_page_a*4)] = data * 64;
2248	2236	//                  nes_vram[2] = data * 64;
2249		chr1_6(space.machine(), state->m_MMC5_vrom_bank[10], CHRROM);
	2237	chr1_6(machine(), m_MMC5_vrom_bank[10], CHRROM);
2250	2238	//                  mapper5_sync_vrom(1);
2251		if (!state->m_vrom_page_b)
	2239	if (!m_vrom_page_b)
2252	2240	{
2253		state->m_vrom_page_a ^= 0x01;
2254		state->m_vrom_page_b = 1;
	2241	m_vrom_page_a ^= 0x01;
	2242	m_vrom_page_b = 1;
2255	2243	}
2256	2244	break;
2257	2245	}
2258	2246	break;
2259	2247	case 0x102b: /* $512b */
2260		LOG_MMC(("MMC5 $512b vrom select: %02x (mode: %d)\n", data, state->m_mmc5_chr_mode));
2261		switch (state->m_mmc5_chr_mode)
	2248	LOG_MMC(("MMC5 $512b vrom select: %02x (mode: %d)\n", data, m_mmc5_chr_mode));
	2249	switch (m_mmc5_chr_mode)
2262	2250	{
2263	2251	case 0x00:
2264	2252	/* 8k switch */
2265	2253	/* switches in first half of an 8K bank!) */
2266		chr4_0(space.machine(), data << 1, CHRROM);
2267		chr4_4(space.machine(), data << 1, CHRROM);
	2254	chr4_0(machine(), data << 1, CHRROM);
	2255	chr4_4(machine(), data << 1, CHRROM);
2268	2256	break;
2269	2257	case 0x01:
2270	2258	/* 4k switch */
2271		chr4_0(space.machine(), data, CHRROM);
2272		chr4_4(space.machine(), data, CHRROM);
	2259	chr4_0(machine(), data, CHRROM);
	2260	chr4_4(machine(), data, CHRROM);
2273	2261	break;
2274	2262	case 0x02:
2275	2263	/* 2k switch */
2276		chr2_2(space.machine(), data | (state->m_mmc5_high_chr << 8), CHRROM);
2277		chr2_6(space.machine(), data | (state->m_mmc5_high_chr << 8), CHRROM);
	2264	chr2_2(machine(), data | (m_mmc5_high_chr << 8), CHRROM);
	2265	chr2_6(machine(), data | (m_mmc5_high_chr << 8), CHRROM);
2278	2266	break;
2279	2267	case 0x03:
2280	2268	/* 1k switch */
2281		state->m_MMC5_vrom_bank[11] = data | (state->m_mmc5_high_chr << 8);
	2269	m_MMC5_vrom_bank[11] = data | (m_mmc5_high_chr << 8);
2282	2270	//                  nes_vram[vrom_next[3]] = data * 64;
2283	2271	//                  nes_vram[3 + (vrom_page_a*4)] = data * 64;
2284	2272	//                  nes_vram[3] = data * 64;
2285		chr1_7(space.machine(), state->m_MMC5_vrom_bank[11], CHRROM);
	2273	chr1_7(machine(), m_MMC5_vrom_bank[11], CHRROM);
2286	2274	//                  mapper5_sync_vrom(1);
2287		if (!state->m_vrom_page_b)
	2275	if (!m_vrom_page_b)
2288	2276	{
2289		state->m_vrom_page_a ^= 0x01;
2290		state->m_vrom_page_b = 1;
	2277	m_vrom_page_a ^= 0x01;
	2278	m_vrom_page_b = 1;
2291	2279	}
2292	2280	break;
2293	2281	}
2294	2282	break;
2295	2283
2296	2284	case 0x1030: /* $5130 */
2297		state->m_mmc5_high_chr = data & 0x03;
2298		if (state->m_mmc5_vram_control == 1)
	2285	m_mmc5_high_chr = data & 0x03;
	2286	if (m_mmc5_vram_control == 1)
2299	2287	{
2300		// in this case state->m_mmc5_high_chr selects which 256KB of CHR ROM
	2288	// in this case m_mmc5_high_chr selects which 256KB of CHR ROM
2301	2289	// is to be used for all background tiles on the screen.
2302	2290	}
2303	2291	break;
2304	2292
2305	2293
2306	2294	case 0x1100: /* $5200 */
2307		state->m_mmc5_split_scr = data;
	2295	m_mmc5_split_scr = data;
2308	2296	// in EX2 and EX3 modes, no split screen
2309		if (state->m_mmc5_vram_control & 0x02)
2310		state->m_mmc5_split_scr &= 0x7f;
2311		state->m_mmc5_split_ctrl = data;
	2297	if (m_mmc5_vram_control & 0x02)
	2298	m_mmc5_split_scr &= 0x7f;
	2299	m_mmc5_split_ctrl = data;
2312	2300	break;
2313	2301
2314	2302	case 0x1101: /* $5201 */
2315		state->m_mmc5_split_yst = (data >= 240) ? data - 16 : data;
	2303	m_mmc5_split_yst = (data >= 240) ? data - 16 : data;
2316	2304	break;
2317	2305
2318	2306	case 0x1102: /* $5202 */
2319		state->m_mmc5_split_bank = data;
	2307	m_mmc5_split_bank = data;
2320	2308	break;
2321	2309
2322	2310	case 0x1103: /* $5203 */
2323		state->m_IRQ_count = data;
2324		state->m_MMC5_scanline = data;
2325		LOG_MMC(("MMC5 irq scanline: %d\n", state->m_IRQ_count));
	2311	m_IRQ_count = data;
	2312	m_MMC5_scanline = data;
	2313	LOG_MMC(("MMC5 irq scanline: %d\n", m_IRQ_count));
2326	2314	break;
2327	2315	case 0x1104: /* $5204 */
2328		state->m_IRQ_enable = data & 0x80;
	2316	m_IRQ_enable = data & 0x80;
2329	2317	LOG_MMC(("MMC5 irq enable: %02x\n", data));
2330	2318	break;
2331	2319	case 0x1105: /* $5205 */
2332		state->m_mult1 = data;
	2320	m_mult1 = data;
2333	2321	break;
2334	2322	case 0x1106: /* $5206 */
2335		state->m_mult2 = data;
	2323	m_mult2 = data;
2336	2324	break;
2337	2325
2338	2326	default:
r18063	r18064
2395	2383	}
2396	2384	}
2397	2385
2398		static WRITE8_HANDLER( ntbrom_w )
	2386	WRITE8_MEMBER(nes_state::ntbrom_w)
2399	2387	{
2400		nes_state *state = space.machine().driver_data<nes_state>();
2401	2388
2402	2389	LOG_MMC(("ntbrom_w, offset %04x, data: %02x\n", offset, data));
2403	2390
2404	2391	switch (offset & 0x7000)
2405	2392	{
2406	2393	case 0x0000:
2407		chr2_0(space.machine(), data, CHRROM);
	2394	chr2_0(machine(), data, CHRROM);
2408	2395	break;
2409	2396	case 0x1000:
2410		chr2_2(space.machine(), data, CHRROM);
	2397	chr2_2(machine(), data, CHRROM);
2411	2398	break;
2412	2399	case 0x2000:
2413		chr2_4(space.machine(), data, CHRROM);
	2400	chr2_4(machine(), data, CHRROM);
2414	2401	break;
2415	2402	case 0x3000:
2416		chr2_6(space.machine(), data, CHRROM);
	2403	chr2_6(machine(), data, CHRROM);
2417	2404	break;
2418	2405	case 0x4000:
2419		state->m_mmc_latch1 = data & 0x7f;
2420		ntbrom_mirror(space.machine(), state->m_mmc_reg[0], state->m_mmc_latch1, state->m_mmc_latch2);
	2406	m_mmc_latch1 = data & 0x7f;
	2407	ntbrom_mirror(machine(), m_mmc_reg[0], m_mmc_latch1, m_mmc_latch2);
2421	2408	break;
2422	2409	case 0x5000:
2423		state->m_mmc_latch2 = data & 0x7f;
2424		ntbrom_mirror(space.machine(), state->m_mmc_reg[0], state->m_mmc_latch1, state->m_mmc_latch2);
	2410	m_mmc_latch2 = data & 0x7f;
	2411	ntbrom_mirror(machine(), m_mmc_reg[0], m_mmc_latch1, m_mmc_latch2);
2425	2412	break;
2426	2413	case 0x6000:
2427		state->m_mmc_reg[0] = data & 0x13;
2428		ntbrom_mirror(space.machine(), state->m_mmc_reg[0], state->m_mmc_latch1, state->m_mmc_latch2);
	2414	m_mmc_reg[0] = data & 0x13;
	2415	ntbrom_mirror(machine(), m_mmc_reg[0], m_mmc_latch1, m_mmc_latch2);
2429	2416	break;
2430	2417	case 0x7000:
2431		prg16_89ab(space.machine(), data);
	2418	prg16_89ab(machine(), data);
2432	2419	break;
2433	2420	default:
2434	2421	LOG_MMC(("ntbrom_w uncaught write, offset: %04x, data: %02x\n", offset, data));
r18063	r18064
2474	2461	}
2475	2462	}
2476	2463
2477		static WRITE8_HANDLER( jxrom_w )
	2464	WRITE8_MEMBER(nes_state::jxrom_w)
2478	2465	{
2479		nes_state *state = space.machine().driver_data<nes_state>();
2480	2466	LOG_MMC(("jxrom_w, offset %04x, data: %02x\n", offset, data));
2481	2467
2482	2468	switch (offset & 0x6000)
2483	2469	{
2484	2470	case 0x0000:
2485		state->m_mmc_latch1 = data & 0x0f;
	2471	m_mmc_latch1 = data & 0x0f;
2486	2472	break;
2487	2473
2488	2474	case 0x2000:
2489		switch (state->m_mmc_latch1)
	2475	switch (m_mmc_latch1)
2490	2476	{
2491	2477	case 0: case 1: case 2: case 3: case 4: case 5: case 6: case 7:
2492		chr1_x(space.machine(), state->m_mmc_latch1, data, CHRROM);
	2478	chr1_x(machine(), m_mmc_latch1, data, CHRROM);
2493	2479	break;
2494	2480
2495	2481	case 8:
r18063	r18064
2497	2483	{
2498	2484	// is PRG ROM
2499	2485	space.unmap_write(0x6000, 0x7fff);
2500		prg8_67(space.machine(), data & 0x3f);
	2486	prg8_67(machine(), data & 0x3f);
2501	2487	}
2502	2488	else if (data & 0x80)
2503	2489	{
2504	2490	// is PRG RAM
2505	2491	space.install_write_bank(0x6000, 0x7fff, "bank5");
2506		state->m_prg_bank[4] = state->m_battery_bank5_start + (data & 0x3f);
2507		state->membank("bank5")->set_entry(state->m_prg_bank[4]);
	2492	m_prg_bank[4] = m_battery_bank5_start + (data & 0x3f);
	2493	membank("bank5")->set_entry(m_prg_bank[4]);
2508	2494	}
2509	2495	break;
2510	2496
2511	2497	case 9:
2512		prg8_89(space.machine(), data);
	2498	prg8_89(machine(), data);
2513	2499	break;
2514	2500	case 0x0a:
2515		prg8_ab(space.machine(), data);
	2501	prg8_ab(machine(), data);
2516	2502	break;
2517	2503	case 0x0b:
2518		prg8_cd(space.machine(), data);
	2504	prg8_cd(machine(), data);
2519	2505	break;
2520	2506	case 0x0c:
2521	2507	switch (data & 0x03)
2522	2508	{
2523		case 0x00: set_nt_mirroring(space.machine(), PPU_MIRROR_VERT); break;
2524		case 0x01: set_nt_mirroring(space.machine(), PPU_MIRROR_HORZ); break;
2525		case 0x02: set_nt_mirroring(space.machine(), PPU_MIRROR_LOW); break;
2526		case 0x03: set_nt_mirroring(space.machine(), PPU_MIRROR_HIGH); break;
	2509	case 0x00: set_nt_mirroring(machine(), PPU_MIRROR_VERT); break;
	2510	case 0x01: set_nt_mirroring(machine(), PPU_MIRROR_HORZ); break;
	2511	case 0x02: set_nt_mirroring(machine(), PPU_MIRROR_LOW); break;
	2512	case 0x03: set_nt_mirroring(machine(), PPU_MIRROR_HIGH); break;
2527	2513	}
2528	2514	break;
2529	2515	case 0x0d:
2530		state->m_IRQ_enable = data;
	2516	m_IRQ_enable = data;
2531	2517	break;
2532	2518	case 0x0e:
2533		state->m_IRQ_count = (state->m_IRQ_count & 0xff00) | data;
	2519	m_IRQ_count = (m_IRQ_count & 0xff00) | data;
2534	2520	break;
2535	2521	case 0x0f:
2536		state->m_IRQ_count = (state->m_IRQ_count & 0x00ff) | (data << 8);
	2522	m_IRQ_count = (m_IRQ_count & 0x00ff) | (data << 8);
2537	2523	break;
2538	2524	}
2539	2525	break;
r18063	r18064
2567	2553
2568	2554	*************************************************************/
2569	2555
2570		static WRITE8_HANDLER( dxrom_w )
	2556	WRITE8_MEMBER(nes_state::dxrom_w)
2571	2557	{
2572		nes_state *state = space.machine().driver_data<nes_state>();
2573	2558	LOG_MMC(("dxrom_w, offset: %04x, data: %02x\n", offset, data));
2574	2559
2575	2560	if (offset >= 0x2000)
r18063	r18064
2578	2563	switch (offset & 1)
2579	2564	{
2580	2565	case 1:
2581		switch (state->m_mmc_latch1 & 0x07)
	2566	switch (m_mmc_latch1 & 0x07)
2582	2567	{
2583		case 0: chr2_0(space.machine(), data >> 1, CHRROM); break;
2584		case 1: chr2_2(space.machine(), data >> 1, CHRROM); break;
2585		case 2: chr1_4(space.machine(), data | 0x40, CHRROM); break;
2586		case 3: chr1_5(space.machine(), data | 0x40, CHRROM); break;
2587		case 4: chr1_6(space.machine(), data | 0x40, CHRROM); break;
2588		case 5: chr1_7(space.machine(), data | 0x40, CHRROM); break;
2589		case 6: prg8_89(space.machine(), data); break;
2590		case 7: prg8_ab(space.machine(), data); break;
	2568	case 0: chr2_0(machine(), data >> 1, CHRROM); break;
	2569	case 1: chr2_2(machine(), data >> 1, CHRROM); break;
	2570	case 2: chr1_4(machine(), data | 0x40, CHRROM); break;
	2571	case 3: chr1_5(machine(), data | 0x40, CHRROM); break;
	2572	case 4: chr1_6(machine(), data | 0x40, CHRROM); break;
	2573	case 5: chr1_7(machine(), data | 0x40, CHRROM); break;
	2574	case 6: prg8_89(machine(), data); break;
	2575	case 7: prg8_ab(machine(), data); break;
2591	2576	}
2592	2577	break;
2593	2578	case 0:
2594		state->m_mmc_latch1 = data;
	2579	m_mmc_latch1 = data;
2595	2580	break;
2596	2581	}
2597	2582	}
r18063	r18064
2610	2595
2611	2596	*************************************************************/
2612	2597
2613		static WRITE8_HANDLER( namcot3453_w )
	2598	WRITE8_MEMBER(nes_state::namcot3453_w)
2614	2599	{
2615	2600	LOG_MMC(("namcot3453_w, offset: %04x, data: %02x\n", offset, data));
2616	2601
2617	2602	// additional mirroring control when writing to even addresses
2618	2603	if (!(offset & 1))
2619		set_nt_mirroring(space.machine(), BIT(data, 6) ? PPU_MIRROR_HIGH : PPU_MIRROR_LOW);
	2604	set_nt_mirroring(machine(), BIT(data, 6) ? PPU_MIRROR_HIGH : PPU_MIRROR_LOW);
2620	2605
2621	2606	dxrom_w(space, offset, data, mem_mask);
2622	2607	}
r18063	r18064
2633	2618
2634	2619	*************************************************************/
2635	2620
2636		static WRITE8_HANDLER( namcot3446_w )
	2621	WRITE8_MEMBER(nes_state::namcot3446_w)
2637	2622	{
2638		nes_state *state = space.machine().driver_data<nes_state>();
2639	2623	LOG_MMC(("namcot3446_w, offset: %04x, data: %02x\n", offset, data));
2640	2624
2641	2625	// NEStopia does not have this!
2642	2626	if (offset >= 0x2000)
2643	2627	{
2644	2628	if (!(offset & 1))
2645		set_nt_mirroring(space.machine(), BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	2629	set_nt_mirroring(machine(), BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
2646	2630	return;
2647	2631	}
2648	2632
2649	2633	switch (offset & 1)
2650	2634	{
2651	2635	case 1:
2652		switch (state->m_mmc_latch1 & 0x07)
	2636	switch (m_mmc_latch1 & 0x07)
2653	2637	{
2654		case 2: chr2_0(space.machine(), data, CHRROM); break;
2655		case 3: chr2_2(space.machine(), data, CHRROM); break;
2656		case 4: chr2_4(space.machine(), data, CHRROM); break;
2657		case 5: chr2_6(space.machine(), data, CHRROM); break;
2658		case 6: BIT(state->m_mmc_latch1, 6) ? prg8_cd(space.machine(), data) : prg8_89(space.machine(), data); break;
2659		case 7: prg8_ab(space.machine(), data); break;
	2638	case 2: chr2_0(machine(), data, CHRROM); break;
	2639	case 3: chr2_2(machine(), data, CHRROM); break;
	2640	case 4: chr2_4(machine(), data, CHRROM); break;
	2641	case 5: chr2_6(machine(), data, CHRROM); break;
	2642	case 6: BIT(m_mmc_latch1, 6) ? prg8_cd(machine(), data) : prg8_89(machine(), data); break;
	2643	case 7: prg8_ab(machine(), data); break;
2660	2644	}
2661	2645	break;
2662	2646	case 0:
2663		state->m_mmc_latch1 = data;
	2647	m_mmc_latch1 = data;
2664	2648	break;
2665	2649	}
2666	2650	}
r18063	r18064
2678	2662
2679	2663	*************************************************************/
2680	2664
2681		static WRITE8_HANDLER( namcot3425_w )
	2665	WRITE8_MEMBER(nes_state::namcot3425_w)
2682	2666	{
2683		nes_state *state = space.machine().driver_data<nes_state>();
2684	2667	UINT8 mode;
2685	2668	LOG_MMC(("namcot3425_w, offset: %04x, data: %02x\n", offset, data));
2686	2669	if (offset >= 0x2000)
r18063	r18064
2689	2672	switch (offset & 1)
2690	2673	{
2691	2674	case 1:
2692		mode = state->m_mmc_latch1 & 0x07;
	2675	mode = m_mmc_latch1 & 0x07;
2693	2676	switch (mode)
2694	2677	{
2695		case 0: chr2_0(space.machine(), data >> 1, CHRROM); break;
2696		case 1: chr2_2(space.machine(), data >> 1, CHRROM); break;
	2678	case 0: chr2_0(machine(), data >> 1, CHRROM); break;
	2679	case 1: chr2_2(machine(), data >> 1, CHRROM); break;
2697	2680	case 2:
2698	2681	case 3:
2699	2682	case 4:
2700	2683	case 5:
2701		chr1_x(space.machine(), 2 + mode, data, CHRROM);
2702		state->m_mmc_reg[mode - 2] = BIT(data, 5);
2703		if (!BIT(state->m_mmc_latch1, 7))
	2684	chr1_x(machine(), 2 + mode, data, CHRROM);
	2685	m_mmc_reg[mode - 2] = BIT(data, 5);
	2686	if (!BIT(m_mmc_latch1, 7))
2704	2687	{
2705		set_nt_page(space.machine(), 0, CIRAM, state->m_mmc_reg[0], 1);
2706		set_nt_page(space.machine(), 1, CIRAM, state->m_mmc_reg[1], 1);
2707		set_nt_page(space.machine(), 2, CIRAM, state->m_mmc_reg[2], 1);
2708		set_nt_page(space.machine(), 3, CIRAM, state->m_mmc_reg[3], 1);
	2688	set_nt_page(machine(), 0, CIRAM, m_mmc_reg[0], 1);
	2689	set_nt_page(machine(), 1, CIRAM, m_mmc_reg[1], 1);
	2690	set_nt_page(machine(), 2, CIRAM, m_mmc_reg[2], 1);
	2691	set_nt_page(machine(), 3, CIRAM, m_mmc_reg[3], 1);
2709	2692	}
2710	2693	else
2711		set_nt_mirroring(space.machine(), PPU_MIRROR_HORZ);
	2694	set_nt_mirroring(machine(), PPU_MIRROR_HORZ);
2712	2695	break;
2713		case 6: prg8_89(space.machine(), data); break;
2714		case 7: prg8_ab(space.machine(), data); break;
	2696	case 6: prg8_89(machine(), data); break;
	2697	case 7: prg8_ab(machine(), data); break;
2715	2698	}
2716	2699	break;
2717	2700	case 0:
2718		state->m_mmc_latch1 = data;
	2701	m_mmc_latch1 = data;
2719	2702	break;
2720	2703	}
2721	2704	}
r18063	r18064
2732	2715
2733	2716	*************************************************************/
2734	2717
2735		static WRITE8_HANDLER( dis_74x377_w )
	2718	WRITE8_MEMBER(nes_state::dis_74x377_w)
2736	2719	{
2737		nes_state *state = space.machine().driver_data<nes_state>();
2738	2720	LOG_MMC(("dis_74x377_w, offset: %04x, data: %02x\n", offset, data));
2739	2721
2740		chr8(space.machine(), data >> 4, state->m_mmc_chr_source);
2741		prg32(space.machine(), data & 0x0f);
	2722	chr8(machine(), data >> 4, m_mmc_chr_source);
	2723	prg32(machine(), data & 0x0f);
2742	2724	}
2743	2725
2744	2726	/*************************************************************
r18063	r18064
2749	2731
2750	2732	*************************************************************/
2751	2733
2752		static WRITE8_HANDLER( dis_74x139x74_m_w )
	2734	WRITE8_MEMBER(nes_state::dis_74x139x74_m_w)
2753	2735	{
2754	2736	LOG_MMC(("dis_74x139x74_m_w, offset: %04x, data: %02x\n", offset, data));
2755	2737
2756		chr8(space.machine(), ((data & 0x02) >> 1) | ((data & 0x01) << 1), CHRROM);
	2738	chr8(machine(), ((data & 0x02) >> 1) | ((data & 0x01) << 1), CHRROM);
2757	2739	}
2758	2740
2759	2741	/*************************************************************
r18063	r18064
2766	2748
2767	2749	*************************************************************/
2768	2750
2769		static WRITE8_HANDLER( dis_74x161x138_m_w )
	2751	WRITE8_MEMBER(nes_state::dis_74x161x138_m_w)
2770	2752	{
2771	2753	LOG_MMC(("dis_74x161x138_m_w, offset: %04x, data: %02x\n", offset, data));
2772	2754
2773		chr8(space.machine(), data >> 2, CHRROM);
2774		prg32(space.machine(), data);
	2755	chr8(machine(), data >> 2, CHRROM);
	2756	prg32(machine(), data);
2775	2757	}
2776	2758
2777	2759	/*************************************************************
r18063	r18064
2786	2768
2787	2769	*************************************************************/
2788	2770
2789		static WRITE8_HANDLER( dis_74x161x161x32_w )
	2771	WRITE8_MEMBER(nes_state::dis_74x161x161x32_w)
2790	2772	{
2791		nes_state *state = space.machine().driver_data<nes_state>();
2792	2773	LOG_MMC(("dis_74x161x161x32_w, offset: %04x, data: %02x\n", offset, data));
2793	2774
2794		if (!state->m_hard_mirroring)   // there are two 'variants' depending on hardwired or mapper ctrl mirroring
2795		set_nt_mirroring(space.machine(), BIT(data, 7) ? PPU_MIRROR_HIGH : PPU_MIRROR_LOW);
2796		chr8(space.machine(), data, CHRROM);
2797		prg16_89ab(space.machine(), data >> 4);
	2775	if (!m_hard_mirroring)   // there are two 'variants' depending on hardwired or mapper ctrl mirroring
	2776	set_nt_mirroring(machine(), BIT(data, 7) ? PPU_MIRROR_HIGH : PPU_MIRROR_LOW);
	2777	chr8(machine(), data, CHRROM);
	2778	prg16_89ab(machine(), data >> 4);
2798	2779	}
2799	2780
2800	2781	/*************************************************************
r18063	r18064
2840	2821	}
2841	2822	}
2842	2823
2843		static WRITE8_HANDLER( lz93d50_w )
	2824	WRITE8_MEMBER(nes_state::lz93d50_w)
2844	2825	{
2845		nes_state *state = space.machine().driver_data<nes_state>();
2846	2826	LOG_MMC(("lz93d50_w, offset: %04x, data: %02x\n", offset, data));
2847	2827
2848	2828	switch (offset & 0x000f)
2849	2829	{
2850	2830	case 0: case 1: case 2: case 3:
2851	2831	case 4: case 5: case 6: case 7:
2852		chr1_x(space.machine(), offset & 0x07, data, state->m_mmc_chr_source);
	2832	chr1_x(machine(), offset & 0x07, data, m_mmc_chr_source);
2853	2833	break;
2854	2834	case 8:
2855		prg16_89ab(space.machine(), data);
	2835	prg16_89ab(machine(), data);
2856	2836	break;
2857	2837	case 9:
2858	2838	switch (data & 0x03)
2859	2839	{
2860		case 0: set_nt_mirroring(space.machine(), PPU_MIRROR_VERT); break;
2861		case 1: set_nt_mirroring(space.machine(), PPU_MIRROR_HORZ); break;
2862		case 2: set_nt_mirroring(space.machine(), PPU_MIRROR_LOW); break;
2863		case 3: set_nt_mirroring(space.machine(), PPU_MIRROR_HIGH); break;
	2840	case 0: set_nt_mirroring(machine(), PPU_MIRROR_VERT); break;
	2841	case 1: set_nt_mirroring(machine(), PPU_MIRROR_HORZ); break;
	2842	case 2: set_nt_mirroring(machine(), PPU_MIRROR_LOW); break;
	2843	case 3: set_nt_mirroring(machine(), PPU_MIRROR_HIGH); break;
2864	2844	}
2865	2845	break;
2866	2846	case 0x0a:
2867		state->m_IRQ_enable = data & 0x01;
	2847	m_IRQ_enable = data & 0x01;
2868	2848	break;
2869	2849	case 0x0b:
2870		state->m_IRQ_count = (state->m_IRQ_count & 0xff00) | data;
	2850	m_IRQ_count = (m_IRQ_count & 0xff00) | data;
2871	2851	break;
2872	2852	case 0x0c:
2873		state->m_IRQ_count = (state->m_IRQ_count & 0x00ff) | (data << 8);
	2853	m_IRQ_count = (m_IRQ_count & 0x00ff) | (data << 8);
2874	2854	break;
2875	2855	default:
2876	2856	logerror("lz93d50_w uncaught write, offset: %04x, data: %02x\n", offset, data);
r18063	r18064
2878	2858	}
2879	2859	}
2880	2860
2881		static WRITE8_HANDLER( lz93d50_m_w )
	2861	WRITE8_MEMBER(nes_state::lz93d50_m_w)
2882	2862	{
2883		nes_state *state = space.machine().driver_data<nes_state>();
2884	2863	LOG_MMC(("lz93d50_m_w, offset: %04x, data: %02x\n", offset, data));
2885	2864
2886		if (!state->m_battery && !state->m_wram)
	2865	if (!m_battery && !m_wram)
2887	2866	lz93d50_w(space, offset & 0x0f, data, mem_mask);
2888		else if (state->m_battery)
2889		state->m_battery_ram[offset] = data;
	2867	else if (m_battery)
	2868	m_battery_ram[offset] = data;
2890	2869	else
2891		state->m_wram[offset] = data;
	2870	m_wram[offset] = data;
2892	2871	}
2893	2872
2894	2873	static void fjump2_set_prg( running_machine &machine )
r18063	r18064
2904	2883	prg16_cdef(machine, mmc_helper | 0x0f);
2905	2884	}
2906	2885
2907		static WRITE8_HANDLER( fjump2_w )
	2886	WRITE8_MEMBER(nes_state::fjump2_w)
2908	2887	{
2909		nes_state *state = space.machine().driver_data<nes_state>();
2910	2888	LOG_MMC(("fjump2_w, offset: %04x, data: %02x\n", offset, data));
2911	2889
2912	2890	switch (offset & 0x000f)
2913	2891	{
2914	2892	case 0: case 1: case 2: case 3:
2915	2893	case 4: case 5: case 6: case 7:
2916		state->m_mmc_reg[offset & 0x000f] = data;
2917		fjump2_set_prg(space.machine());
	2894	m_mmc_reg[offset & 0x000f] = data;
	2895	fjump2_set_prg(machine());
2918	2896	break;
2919	2897	case 8:
2920		state->m_mmc_latch1 = (data & 0x0f);
2921		fjump2_set_prg(space.machine());
	2898	m_mmc_latch1 = (data & 0x0f);
	2899	fjump2_set_prg(machine());
2922	2900	break;
2923	2901	default:
2924	2902	lz93d50_m_w(space, offset & 0x0f, data, mem_mask);
r18063	r18064
2938	2916
2939	2917	*************************************************************/
2940	2918
2941		static WRITE8_HANDLER( bandai_ks_w )
	2919	WRITE8_MEMBER(nes_state::bandai_ks_w)
2942	2920	{
2943	2921	LOG_MMC(("bandai_ks_w, offset: %04x, data: %02x\n", offset, data));
2944	2922
2945		prg16_89ab(space.machine(), data ^ 0x08);
	2923	prg16_89ab(machine(), data ^ 0x08);
2946	2924	}
2947	2925
2948	2926	/*************************************************************
r18063	r18064
2958	2936
2959	2937	*************************************************************/
2960	2938
2961		static WRITE8_HANDLER( bandai_ok_w )
	2939	WRITE8_MEMBER(nes_state::bandai_ok_w)
2962	2940	{
2963		nes_state *state = space.machine().driver_data<nes_state>();
2964	2941	UINT8 mmc_helper;
2965	2942	LOG_MMC(("mapper96_w, offset: %04x, data: %02x\n", offset, data));
2966	2943
2967		prg32(space.machine(), data);
	2944	prg32(machine(), data);
2968	2945
2969		state->m_mmc_latch1 = data;
2970		mmc_helper = (state->m_mmc_latch1 & 0x03) | (data & 0x04);
2971		chr4_0(space.machine(), mmc_helper, CHRRAM);
2972		chr4_4(space.machine(), 0x03 | (data & 0x04), CHRRAM);
	2946	m_mmc_latch1 = data;
	2947	mmc_helper = (m_mmc_latch1 & 0x03) | (data & 0x04);
	2948	chr4_0(machine(), mmc_helper, CHRRAM);
	2949	chr4_4(machine(), 0x03 | (data & 0x04), CHRRAM);
2973	2950	}
2974	2951
2975	2952	/*************************************************************
r18063	r18064
2982	2959
2983	2960	*************************************************************/
2984	2961
2985		static WRITE8_HANDLER( lrog017_w )
	2962	WRITE8_MEMBER(nes_state::lrog017_w)
2986	2963	{
2987	2964	LOG_MMC(("lrog017_w, offset: %04x, data: %02x\n", offset, data));
2988	2965
2989		prg32(space.machine(), data);
2990		chr2_0(space.machine(), (data >> 4), CHRROM);
	2966	prg32(machine(), data);
	2967	chr2_0(machine(), (data >> 4), CHRROM);
2991	2968	}
2992	2969
2993	2970	/*************************************************************
r18063	r18064
2998	2975
2999	2976	*************************************************************/
3000	2977
3001		static WRITE8_HANDLER( irem_hd_w )
	2978	WRITE8_MEMBER(nes_state::irem_hd_w)
3002	2979	{
3003	2980	LOG_MMC(("irem_hd_w, offset: %04x, data: %02x\n", offset, data));
3004	2981
3005		set_nt_mirroring(space.machine(), BIT(data, 3) ? PPU_MIRROR_VERT : PPU_MIRROR_HORZ);
3006		chr8(space.machine(), data >> 4, CHRROM);
3007		prg16_89ab(space.machine(), data);
	2982	set_nt_mirroring(machine(), BIT(data, 3) ? PPU_MIRROR_VERT : PPU_MIRROR_HORZ);
	2983	chr8(machine(), data >> 4, CHRROM);
	2984	prg16_89ab(machine(), data);
3008	2985	}
3009	2986
3010	2987	/*************************************************************
r18063	r18064
3019	2996
3020	2997	*************************************************************/
3021	2998
3022		static WRITE8_HANDLER( tam_s1_w )
	2999	WRITE8_MEMBER(nes_state::tam_s1_w)
3023	3000	{
3024	3001	LOG_MMC(("tam_s1_w, offset: %04x, data: %02x\n", offset, data));
3025	3002
3026	3003	if (offset < 0x4000)
3027	3004	{
3028		set_nt_mirroring(space.machine(), BIT(data, 7) ? PPU_MIRROR_VERT : PPU_MIRROR_HORZ);
3029		prg16_cdef(space.machine(), data);
	3005	set_nt_mirroring(machine(), BIT(data, 7) ? PPU_MIRROR_VERT : PPU_MIRROR_HORZ);
	3006	prg16_cdef(machine(), data);
3030	3007	}
3031	3008	}
3032	3009
r18063	r18064
3040	3017
3041	3018	*************************************************************/
3042	3019
3043		static WRITE8_HANDLER( g101_w )
	3020	WRITE8_MEMBER(nes_state::g101_w)
3044	3021	{
3045		nes_state *state = space.machine().driver_data<nes_state>();
3046	3022	LOG_MMC(("g101_w, offset: %04x, data: %02x\n", offset, data));
3047	3023
3048	3024	switch (offset & 0x7000)
3049	3025	{
3050	3026	case 0x0000:
3051	3027	// NEStopia here differs a little bit
3052		state->m_mmc_latch1 ? prg8_cd(space.machine(), data) : prg8_89(space.machine(), data);
	3028	m_mmc_latch1 ? prg8_cd(machine(), data) : prg8_89(machine(), data);
3053	3029	break;
3054	3030	case 0x1000:
3055		state->m_mmc_latch1 = BIT(data, 1);
3056		if (!state->m_hard_mirroring)   // there are two 'variants' depending on hardwired or mapper ctrl mirroring
3057		set_nt_mirroring(space.machine(), BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	3031	m_mmc_latch1 = BIT(data, 1);
	3032	if (!m_hard_mirroring)   // there are two 'variants' depending on hardwired or mapper ctrl mirroring
	3033	set_nt_mirroring(machine(), BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
3058	3034	break;
3059	3035	case 0x2000:
3060		prg8_ab(space.machine(), data);
	3036	prg8_ab(machine(), data);
3061	3037	break;
3062	3038	case 0x3000:
3063		chr1_x(space.machine(), offset & 0x07, data, CHRROM);
	3039	chr1_x(machine(), offset & 0x07, data, CHRROM);
3064	3040	break;
3065	3041	}
3066	3042	}
r18063	r18064
3096	3072	}
3097	3073	}
3098	3074
3099		static WRITE8_HANDLER( h3001_w )
	3075	WRITE8_MEMBER(nes_state::h3001_w)
3100	3076	{
3101		nes_state *state = space.machine().driver_data<nes_state>();
3102	3077	LOG_MMC(("h3001_w, offset %04x, data: %02x\n", offset, data));
3103	3078
3104	3079	switch (offset & 0x7fff)
3105	3080	{
3106	3081	case 0x0000:
3107		prg8_89(space.machine(), data);
	3082	prg8_89(machine(), data);
3108	3083	break;
3109	3084
3110	3085	case 0x1001:
3111		set_nt_mirroring(space.machine(), BIT(data, 7) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	3086	set_nt_mirroring(machine(), BIT(data, 7) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
3112	3087	break;
3113	3088
3114	3089	case 0x1003:
3115		state->m_IRQ_enable = data & 0x80;
	3090	m_IRQ_enable = data & 0x80;
3116	3091	break;
3117	3092
3118	3093	case 0x1004:
3119		state->m_IRQ_count = state->m_IRQ_count_latch;
	3094	m_IRQ_count = m_IRQ_count_latch;
3120	3095	break;
3121	3096
3122	3097	case 0x1005:
3123		state->m_IRQ_count_latch = (state->m_IRQ_count_latch & 0x00ff) | (data << 8);
	3098	m_IRQ_count_latch = (m_IRQ_count_latch & 0x00ff) | (data << 8);
3124	3099	break;
3125	3100
3126	3101	case 0x1006:
3127		state->m_IRQ_count_latch = (state->m_IRQ_count_latch & 0xff00) | data;
	3102	m_IRQ_count_latch = (m_IRQ_count_latch & 0xff00) | data;
3128	3103	break;
3129	3104
3130	3105	case 0x2000:
3131		prg8_ab(space.machine(), data);
	3106	prg8_ab(machine(), data);
3132	3107	break;
3133	3108
3134	3109	case 0x3000: case 0x3001: case 0x3002: case 0x3003:
3135	3110	case 0x3004: case 0x3005: case 0x3006: case 0x3007:
3136		chr1_x(space.machine(), offset & 0x07, data, CHRROM);
	3111	chr1_x(machine(), offset & 0x07, data, CHRROM);
3137	3112	break;
3138	3113
3139	3114	case 0x4000:
3140		prg8_cd(space.machine(), data);
	3115	prg8_cd(machine(), data);
3141	3116	break;
3142	3117
3143	3118	default:
r18063	r18064
3209	3184	}
3210	3185	}
3211	3186
3212		static WRITE8_HANDLER( ss88006_w )
	3187	WRITE8_MEMBER(nes_state::ss88006_w)
3213	3188	{
3214		nes_state *state = space.machine().driver_data<nes_state>();
3215	3189	UINT8 bank;
3216	3190	LOG_MMC(("mapper18_w, offset: %04x, data: %02x\n", offset, data));
3217	3191
3218	3192	switch (offset & 0x7003)
3219	3193	{
3220	3194	case 0x0000:
3221		state->m_mmc_prg_bank[0] = (state->m_mmc_prg_bank[0] & 0xf0) | (data & 0x0f);
3222		prg8_89(space.machine(), state->m_mmc_prg_bank[0]);
	3195	m_mmc_prg_bank[0] = (m_mmc_prg_bank[0] & 0xf0) | (data & 0x0f);
	3196	prg8_89(machine(), m_mmc_prg_bank[0]);
3223	3197	break;
3224	3198	case 0x0001:
3225		state->m_mmc_prg_bank[0] = (state->m_mmc_prg_bank[0] & 0x0f) | (data << 4);
3226		prg8_89(space.machine(), state->m_mmc_prg_bank[0]);
	3199	m_mmc_prg_bank[0] = (m_mmc_prg_bank[0] & 0x0f) | (data << 4);
	3200	prg8_89(machine(), m_mmc_prg_bank[0]);
3227	3201	break;
3228	3202	case 0x0002:
3229		state->m_mmc_prg_bank[1] = (state->m_mmc_prg_bank[1] & 0xf0) | (data & 0x0f);
3230		prg8_ab(space.machine(), state->m_mmc_prg_bank[1]);
	3203	m_mmc_prg_bank[1] = (m_mmc_prg_bank[1] & 0xf0) | (data & 0x0f);
	3204	prg8_ab(machine(), m_mmc_prg_bank[1]);
3231	3205	break;
3232	3206	case 0x0003:
3233		state->m_mmc_prg_bank[1] = (state->m_mmc_prg_bank[1] & 0x0f) | (data << 4);
3234		prg8_ab(space.machine(), state->m_mmc_prg_bank[1]);
	3207	m_mmc_prg_bank[1] = (m_mmc_prg_bank[1] & 0x0f) | (data << 4);
	3208	prg8_ab(machine(), m_mmc_prg_bank[1]);
3235	3209	break;
3236	3210	case 0x1000:
3237		state->m_mmc_prg_bank[2] = (state->m_mmc_prg_bank[2] & 0xf0) | (data & 0x0f);
3238		prg8_cd(space.machine(), state->m_mmc_prg_bank[2]);
	3211	m_mmc_prg_bank[2] = (m_mmc_prg_bank[2] & 0xf0) | (data & 0x0f);
	3212	prg8_cd(machine(), m_mmc_prg_bank[2]);
3239	3213	break;
3240	3214	case 0x1001:
3241		state->m_mmc_prg_bank[2] = (state->m_mmc_prg_bank[2] & 0x0f) | (data << 4);
3242		prg8_cd(space.machine(), state->m_mmc_prg_bank[2]);
	3215	m_mmc_prg_bank[2] = (m_mmc_prg_bank[2] & 0x0f) | (data << 4);
	3216	prg8_cd(machine(), m_mmc_prg_bank[2]);
3243	3217	break;
3244	3218
3245	3219	/* $9002, 3 (1002, 3) uncaught = Jaleco Baseball writes 0 */
r18063	r18064
3251	3225	case 0x5000: case 0x5001: case 0x5002: case 0x5003:
3252	3226	bank = ((offset & 0x7000) - 0x2000) / 0x0800 + ((offset & 0x0002) >> 1);
3253	3227	if (offset & 0x0001)
3254		state->m_mmc_vrom_bank[bank] = (state->m_mmc_vrom_bank[bank] & 0x0f) | ((data & 0x0f)<< 4);
	3228	m_mmc_vrom_bank[bank] = (m_mmc_vrom_bank[bank] & 0x0f) | ((data & 0x0f)<< 4);
3255	3229	else
3256		state->m_mmc_vrom_bank[bank] = (state->m_mmc_vrom_bank[bank] & 0xf0) | (data & 0x0f);
	3230	m_mmc_vrom_bank[bank] = (m_mmc_vrom_bank[bank] & 0xf0) | (data & 0x0f);
3257	3231
3258		chr1_x(space.machine(), bank, state->m_mmc_vrom_bank[bank], CHRROM);
	3232	chr1_x(machine(), bank, m_mmc_vrom_bank[bank], CHRROM);
3259	3233	break;
3260	3234
3261	3235	case 0x6000:
3262		state->m_IRQ_count_latch = (state->m_IRQ_count_latch & 0xfff0) | (data & 0x0f);
	3236	m_IRQ_count_latch = (m_IRQ_count_latch & 0xfff0) | (data & 0x0f);
3263	3237	break;
3264	3238	case 0x6001:
3265		state->m_IRQ_count_latch = (state->m_IRQ_count_latch & 0xff0f) | ((data & 0x0f) << 4);
	3239	m_IRQ_count_latch = (m_IRQ_count_latch & 0xff0f) | ((data & 0x0f) << 4);
3266	3240	break;
3267	3241	case 0x6002:
3268		state->m_IRQ_count_latch = (state->m_IRQ_count_latch & 0xf0ff) | ((data & 0x0f) << 8);
	3242	m_IRQ_count_latch = (m_IRQ_count_latch & 0xf0ff) | ((data & 0x0f) << 8);
3269	3243	break;
3270	3244	case 0x6003:
3271		state->m_IRQ_count_latch = (state->m_IRQ_count_latch & 0x0fff) | ((data & 0x0f) << 12);
	3245	m_IRQ_count_latch = (m_IRQ_count_latch & 0x0fff) | ((data & 0x0f) << 12);
3272	3246	break;
3273	3247
3274	3248	case 0x7000:
3275		state->m_IRQ_count = state->m_IRQ_count_latch;
	3249	m_IRQ_count = m_IRQ_count_latch;
3276	3250	break;
3277	3251	case 0x7001:
3278		state->m_IRQ_enable = data & 0x01;
3279		state->m_IRQ_mode = data & 0x0e;
	3252	m_IRQ_enable = data & 0x01;
	3253	m_IRQ_mode = data & 0x0e;
3280	3254	break;
3281	3255
3282	3256	case 0x7002:
3283	3257	switch (data & 0x03)
3284	3258	{
3285		case 0: set_nt_mirroring(space.machine(), PPU_MIRROR_HORZ); break;
3286		case 1: set_nt_mirroring(space.machine(), PPU_MIRROR_VERT); break;
3287		case 2: set_nt_mirroring(space.machine(), PPU_MIRROR_LOW); break;
3288		case 3: set_nt_mirroring(space.machine(), PPU_MIRROR_HIGH); break;
	3259	case 0: set_nt_mirroring(machine(), PPU_MIRROR_HORZ); break;
	3260	case 1: set_nt_mirroring(machine(), PPU_MIRROR_VERT); break;
	3261	case 2: set_nt_mirroring(machine(), PPU_MIRROR_LOW); break;
	3262	case 3: set_nt_mirroring(machine(), PPU_MIRROR_HIGH); break;
3289	3263	}
3290	3264	break;
3291	3265
r18063	r18064
3307	3281
3308	3282	*************************************************************/
3309	3283
3310		static WRITE8_HANDLER( jf11_m_w )
	3284	WRITE8_MEMBER(nes_state::jf11_m_w)
3311	3285	{
3312	3286	LOG_MMC(("jf11_m_w, offset: %04x, data: %02x\n", offset, data));
3313		chr8(space.machine(), data, CHRROM);
3314		prg32(space.machine(), data >> 4);
	3287	chr8(machine(), data, CHRROM);
	3288	prg32(machine(), data >> 4);
3315	3289	}
3316	3290
3317	3291	/*************************************************************
r18063	r18064
3328	3302
3329	3303	*************************************************************/
3330	3304
3331		static WRITE8_HANDLER( jf13_m_w )
	3305	WRITE8_MEMBER(nes_state::jf13_m_w)
3332	3306	{
3333	3307	LOG_MMC(("jf13_m_w, offset: %04x, data: %02x\n", offset, data));
3334	3308
3335	3309	if (offset == 0)
3336	3310	{
3337		prg32(space.machine(), (data >> 4) & 0x03);
3338		chr8(space.machine(), ((data >> 4) & 0x04) | (data & 0x03), CHRROM);
	3311	prg32(machine(), (data >> 4) & 0x03);
	3312	chr8(machine(), ((data >> 4) & 0x04) | (data & 0x03), CHRROM);
3339	3313	}
3340	3314
3341	3315	if (offset == 0x1000)
r18063	r18064
3357	3331
3358	3332	*************************************************************/
3359	3333
3360		static WRITE8_HANDLER( jf16_w )
	3334	WRITE8_MEMBER(nes_state::jf16_w)
3361	3335	{
3362	3336	LOG_MMC(("jf16_w, offset: %04x, data: %02x\n", offset, data));
3363	3337
3364		set_nt_mirroring(space.machine(), BIT(data, 3) ? PPU_MIRROR_HIGH : PPU_MIRROR_LOW);
3365		chr8(space.machine(), data >> 4, CHRROM);
3366		prg16_89ab(space.machine(), data);
	3338	set_nt_mirroring(machine(), BIT(data, 3) ? PPU_MIRROR_HIGH : PPU_MIRROR_LOW);
	3339	chr8(machine(), data >> 4, CHRROM);
	3340	prg16_89ab(machine(), data);
3367	3341	}
3368	3342
3369	3343	/*************************************************************
r18063	r18064
3381	3355
3382	3356	*************************************************************/
3383	3357
3384		static WRITE8_HANDLER( jf17_w )
	3358	WRITE8_MEMBER(nes_state::jf17_w)
3385	3359	{
3386	3360	LOG_MMC(("jf17_w, offset: %04x, data: %02x\n", offset, data));
3387	3361
3388	3362	if (BIT(data, 7))
3389		prg16_89ab(space.machine(), data & 0x0f);
	3363	prg16_89ab(machine(), data & 0x0f);
3390	3364	if (BIT(data, 6))
3391		chr8(space.machine(), data & 0x0f, CHRROM);
	3365	chr8(machine(), data & 0x0f, CHRROM);
3392	3366	if (BIT(data, 5) && !BIT(data,4))
3393	3367	LOG_MMC(("Jaleco JF-17 sound write, data: %02x\n", data & 0x1f));
3394	3368	}
r18063	r18064
3407	3381
3408	3382	*************************************************************/
3409	3383
3410		static WRITE8_HANDLER( jf19_w )
	3384	WRITE8_MEMBER(nes_state::jf19_w)
3411	3385	{
3412	3386	LOG_MMC(("jf19_w, offset: %04x, data: %02x\n", offset, data));
3413	3387
3414	3388	if (BIT(data, 7))
3415		prg16_cdef(space.machine(), data & 0x0f);
	3389	prg16_cdef(machine(), data & 0x0f);
3416	3390	if (BIT(data, 6))
3417		chr8(space.machine(), data & 0x0f, CHRROM);
	3391	chr8(machine(), data & 0x0f, CHRROM);
3418	3392	if (BIT(data, 5) && !BIT(data,4))
3419	3393	LOG_MMC(("Jaleco JF-19 sound write, data: %02x\n", data & 0x1f));
3420	3394	}
r18063	r18064
3431	3405
3432	3406	*************************************************************/
3433	3407
3434		static WRITE8_HANDLER( konami_vrc1_w )
	3408	WRITE8_MEMBER(nes_state::konami_vrc1_w)
3435	3409	{
3436		nes_state *state = space.machine().driver_data<nes_state>();
3437	3410	LOG_MMC(("konami_vrc1_w, offset: %04x, data: %02x\n", offset, data));
3438	3411
3439	3412	switch (offset & 0x7000)
3440	3413	{
3441	3414	case 0x0000:
3442		prg8_89(space.machine(), data);
	3415	prg8_89(machine(), data);
3443	3416	break;
3444	3417	case 0x1000:
3445		set_nt_mirroring(space.machine(), (data & 0x01) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
3446		state->m_mmc_vrom_bank[0] = (state->m_mmc_vrom_bank[0] & 0x0f) | ((data & 0x02) << 3);
3447		state->m_mmc_vrom_bank[1] = (state->m_mmc_vrom_bank[1] & 0x0f) | ((data & 0x04) << 2);
3448		chr4_0(space.machine(), state->m_mmc_vrom_bank[0], CHRROM);
3449		chr4_4(space.machine(), state->m_mmc_vrom_bank[1], CHRROM);
	3418	set_nt_mirroring(machine(), (data & 0x01) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	3419	m_mmc_vrom_bank[0] = (m_mmc_vrom_bank[0] & 0x0f) | ((data & 0x02) << 3);
	3420	m_mmc_vrom_bank[1] = (m_mmc_vrom_bank[1] & 0x0f) | ((data & 0x04) << 2);
	3421	chr4_0(machine(), m_mmc_vrom_bank[0], CHRROM);
	3422	chr4_4(machine(), m_mmc_vrom_bank[1], CHRROM);
3450	3423	break;
3451	3424	case 0x2000:
3452		prg8_ab(space.machine(), data);
	3425	prg8_ab(machine(), data);
3453	3426	break;
3454	3427	case 0x4000:
3455		prg8_cd(space.machine(), data);
	3428	prg8_cd(machine(), data);
3456	3429	break;
3457	3430	case 0x6000:
3458		state->m_mmc_vrom_bank[0] = (state->m_mmc_vrom_bank[0] & 0x10) | (data & 0x0f);
3459		chr4_0(space.machine(), state->m_mmc_vrom_bank[0], CHRROM);
	3431	m_mmc_vrom_bank[0] = (m_mmc_vrom_bank[0] & 0x10) | (data & 0x0f);
	3432	chr4_0(machine(), m_mmc_vrom_bank[0], CHRROM);
3460	3433	break;
3461	3434	case 0x7000:
3462		state->m_mmc_vrom_bank[1] = (state->m_mmc_vrom_bank[1] & 0x10) | (data & 0x0f);
3463		chr4_4(space.machine(), state->m_mmc_vrom_bank[1], CHRROM);
	3435	m_mmc_vrom_bank[1] = (m_mmc_vrom_bank[1] & 0x10) | (data & 0x0f);
	3436	chr4_4(machine(), m_mmc_vrom_bank[1], CHRROM);
3464	3437	break;
3465	3438	}
3466	3439	}
r18063	r18064
3473	3446
3474	3447	*************************************************************/
3475	3448
3476		static WRITE8_HANDLER( konami_vrc2_w )
	3449	WRITE8_MEMBER(nes_state::konami_vrc2_w)
3477	3450	{
3478		nes_state *state = space.machine().driver_data<nes_state>();
3479	3451	UINT8 bank, shift, mask;
3480	3452	UINT32 shifted_offs = (offset & 0x7000)
3481		| ((offset << (9 - state->m_vrc_ls_prg_a)) & 0x200)
3482		| ((offset << (8 - state->m_vrc_ls_prg_b)) & 0x100);
	3453	| ((offset << (9 - m_vrc_ls_prg_a)) & 0x200)
	3454	| ((offset << (8 - m_vrc_ls_prg_b)) & 0x100);
3483	3455	LOG_MMC(("konami_vrc2_w, offset: %04x, data: %02x\n", offset, data));
3484	3456
3485	3457	if (offset < 0x1000)
3486		prg8_89(space.machine(), data);
	3458	prg8_89(machine(), data);
3487	3459	else if (offset < 0x2000)
3488	3460	{
3489	3461	switch (data & 0x03)
3490	3462	{
3491		case 0x00: set_nt_mirroring(space.machine(), PPU_MIRROR_VERT); break;
3492		case 0x01: set_nt_mirroring(space.machine(), PPU_MIRROR_HORZ); break;
3493		case 0x02: set_nt_mirroring(space.machine(), PPU_MIRROR_LOW); break;
3494		case 0x03: set_nt_mirroring(space.machine(), PPU_MIRROR_HIGH); break;
	3463	case 0x00: set_nt_mirroring(machine(), PPU_MIRROR_VERT); break;
	3464	case 0x01: set_nt_mirroring(machine(), PPU_MIRROR_HORZ); break;
	3465	case 0x02: set_nt_mirroring(machine(), PPU_MIRROR_LOW); break;
	3466	case 0x03: set_nt_mirroring(machine(), PPU_MIRROR_HIGH); break;
3495	3467	}
3496	3468	}
3497	3469	else if (offset < 0x3000)
3498		prg8_ab(space.machine(), data);
	3470	prg8_ab(machine(), data);
3499	3471	else if (offset < 0x7000)
3500	3472	{
3501	3473	bank = ((shifted_offs & 0x7000) - 0x3000) / 0x0800 + BIT(shifted_offs, 9);
3502	3474	shift = BIT(shifted_offs, 8) * 4;
3503	3475	mask = (0xf0 >> shift);
3504		state->m_mmc_vrom_bank[bank] = (state->m_mmc_vrom_bank[bank] & mask)
3505		| (((data >> state->m_vrc_ls_chr) & 0x0f) << shift);
3506		chr1_x(space.machine(), bank, state->m_mmc_vrom_bank[bank], CHRROM);
	3476	m_mmc_vrom_bank[bank] = (m_mmc_vrom_bank[bank] & mask)
	3477	| (((data >> m_vrc_ls_chr) & 0x0f) << shift);
	3478	chr1_x(machine(), bank, m_mmc_vrom_bank[bank], CHRROM);
3507	3479	}
3508	3480	else
3509	3481	logerror("konami_vrc2_w uncaught write, addr: %04x value: %02x\n", offset + 0x8000, data);
r18063	r18064
3521	3493
3522	3494	*************************************************************/
3523	3495
3524		static WRITE8_HANDLER( konami_vrc3_w )
	3496	WRITE8_MEMBER(nes_state::konami_vrc3_w)
3525	3497	{
3526	3498	LOG_MMC(("konami_vrc3_w, offset: %04x, data: %02x\n", offset, data));
3527		nes_state *state = space.machine().driver_data<nes_state>();
3528	3499
3529	3500	switch (offset & 0x7000)
3530	3501	{
3531	3502	case 0x0000:
3532	3503	case 0x1000:
3533	3504	/* dunno which address controls these */
3534		state->m_IRQ_count_latch = data;
3535		state->m_IRQ_enable_latch = data;
	3505	m_IRQ_count_latch = data;
	3506	m_IRQ_enable_latch = data;
3536	3507	break;
3537	3508	case 0x2000:
3538		state->m_IRQ_enable = data;
	3509	m_IRQ_enable = data;
3539	3510	break;
3540	3511	case 0x3000:
3541		state->m_IRQ_count &= ~0x0f;
3542		state->m_IRQ_count |= data & 0x0f;
	3512	m_IRQ_count &= ~0x0f;
	3513	m_IRQ_count |= data & 0x0f;
3543	3514	break;
3544	3515	case 0x4000:
3545		state->m_IRQ_count &= ~0xf0;
3546		state->m_IRQ_count |= (data & 0x0f) << 4;
	3516	m_IRQ_count &= ~0xf0;
	3517	m_IRQ_count |= (data & 0x0f) << 4;
3547	3518	break;
3548	3519	case 0x7000:
3549		prg16_89ab(space.machine(), data);
	3520	prg16_89ab(machine(), data);
3550	3521	break;
3551	3522	default:
3552	3523	logerror("konami_vrc3_w uncaught write, offset %04x, data: %02x\n", offset, data);
r18063	r18064
3589	3560	}
3590	3561	}
3591	3562
3592		static WRITE8_HANDLER( konami_vrc4_w )
	3563	WRITE8_MEMBER(nes_state::konami_vrc4_w)
3593	3564	{
3594		nes_state *state = space.machine().driver_data<nes_state>();
3595	3565	UINT8 bank, shift, mask;
3596	3566	UINT32 shifted_offs = (offset & 0x7000)
3597		| ((offset << (9 - state->m_vrc_ls_prg_a)) & 0x200)
3598		| ((offset << (8 - state->m_vrc_ls_prg_b)) & 0x100);
	3567	| ((offset << (9 - m_vrc_ls_prg_a)) & 0x200)
	3568	| ((offset << (8 - m_vrc_ls_prg_b)) & 0x100);
3599	3569	LOG_MMC(("konami_vrc4_w, offset: %04x, data: %02x\n", offset, data));
3600	3570
3601	3571	if (offset < 0x1000)
3602	3572	{
3603		state->m_mmc_prg_bank[0] = data;
3604		vrc4_set_prg(space.machine());
	3573	m_mmc_prg_bank[0] = data;
	3574	vrc4_set_prg(machine());
3605	3575	}
3606	3576	else if (offset >= 0x2000 && offset < 0x3000)
3607		prg8_ab(space.machine(), data);
	3577	prg8_ab(machine(), data);
3608	3578	else
3609	3579	{
3610	3580	switch (shifted_offs & 0x7300)
r18063	r18064
3613	3583	case 0x1100:
3614	3584	switch (data & 0x03)
3615	3585	{
3616		case 0x00: set_nt_mirroring(space.machine(), PPU_MIRROR_VERT); break;
3617		case 0x01: set_nt_mirroring(space.machine(), PPU_MIRROR_HORZ); break;
3618		case 0x02: set_nt_mirroring(space.machine(), PPU_MIRROR_LOW); break;
3619		case 0x03: set_nt_mirroring(space.machine(), PPU_MIRROR_HIGH); break;
	3586	case 0x00: set_nt_mirroring(machine(), PPU_MIRROR_VERT); break;
	3587	case 0x01: set_nt_mirroring(machine(), PPU_MIRROR_HORZ); break;
	3588	case 0x02: set_nt_mirroring(machine(), PPU_MIRROR_LOW); break;
	3589	case 0x03: set_nt_mirroring(machine(), PPU_MIRROR_HIGH); break;
3620	3590	}
3621	3591	break;
3622	3592	case 0x1200:
3623	3593	case 0x1300:
3624		state->m_mmc_latch1 = data & 0x02;
3625		vrc4_set_prg(space.machine());
	3594	m_mmc_latch1 = data & 0x02;
	3595	vrc4_set_prg(machine());
3626	3596	break;
3627	3597	case 0x3000:
3628	3598	case 0x3100:
r18063	r18064
3643	3613	bank = ((shifted_offs & 0x7000) - 0x3000) / 0x0800 + BIT(shifted_offs, 9);
3644	3614	shift = BIT(shifted_offs, 8) * 4;
3645	3615	mask = (0xf0 >> shift);
3646		state->m_mmc_vrom_bank[bank] = (state->m_mmc_vrom_bank[bank] & mask) | ((data & 0x0f) << shift);
3647		chr1_x(space.machine(), bank, state->m_mmc_vrom_bank[bank], CHRROM);
	3616	m_mmc_vrom_bank[bank] = (m_mmc_vrom_bank[bank] & mask) | ((data & 0x0f) << shift);
	3617	chr1_x(machine(), bank, m_mmc_vrom_bank[bank], CHRROM);
3648	3618	break;
3649	3619	case 0x7000:
3650		state->m_IRQ_count_latch = (state->m_IRQ_count_latch & 0xf0) | (data & 0x0f);
	3620	m_IRQ_count_latch = (m_IRQ_count_latch & 0xf0) | (data & 0x0f);
3651	3621	break;
3652	3622	case 0x7100:
3653		state->m_IRQ_count_latch = (state->m_IRQ_count_latch & 0x0f) | ((data & 0x0f) << 4);
	3623	m_IRQ_count_latch = (m_IRQ_count_latch & 0x0f) | ((data & 0x0f) << 4);
3654	3624	break;
3655	3625	case 0x7200:
3656		state->m_IRQ_mode = data & 0x04;   // currently not implemented: 0 = prescaler mode / 1 = CPU mode
3657		state->m_IRQ_enable = data & 0x02;
3658		state->m_IRQ_enable_latch = data & 0x01;
	3626	m_IRQ_mode = data & 0x04;   // currently not implemented: 0 = prescaler mode / 1 = CPU mode
	3627	m_IRQ_enable = data & 0x02;
	3628	m_IRQ_enable_latch = data & 0x01;
3659	3629	if (data & 0x02)
3660		state->m_IRQ_count = state->m_IRQ_count_latch;
	3630	m_IRQ_count = m_IRQ_count_latch;
3661	3631	break;
3662	3632	case 0x7300:
3663		state->m_IRQ_enable = state->m_IRQ_enable_latch;
	3633	m_IRQ_enable = m_IRQ_enable_latch;
3664	3634	break;
3665	3635	default:
3666	3636	logerror("konami_vrc4_w uncaught write, addr: %04x value: %02x\n", shifted_offs + 0x8000, data);
r18063	r18064
3678	3648
3679	3649	*************************************************************/
3680	3650
3681		static WRITE8_HANDLER( konami_vrc6_w )
	3651	WRITE8_MEMBER(nes_state::konami_vrc6_w)
3682	3652	{
3683		nes_state *state = space.machine().driver_data<nes_state>();
3684	3653	UINT8 bank;
3685	3654	UINT32 shifted_offs = (offset & 0x7000)
3686		| ((offset << (9 - state->m_vrc_ls_prg_a)) & 0x200)
3687		| ((offset << (8 - state->m_vrc_ls_prg_b)) & 0x100);
	3655	| ((offset << (9 - m_vrc_ls_prg_a)) & 0x200)
	3656	| ((offset << (8 - m_vrc_ls_prg_b)) & 0x100);
3688	3657	LOG_MMC(("konami_vrc6_w, offset: %04x, data: %02x\n", offset, data));
3689	3658
3690	3659	if (offset < 0x1000)
3691		prg16_89ab(space.machine(), data);
	3660	prg16_89ab(machine(), data);
3692	3661	else if (offset >= 0x4000 && offset < 0x5000)
3693		prg8_cd(space.machine(), data);
	3662	prg8_cd(machine(), data);
3694	3663	else
3695	3664	{
3696	3665	switch (shifted_offs & 0x7300)
r18063	r18064
3709	3678	case 0x3300:
3710	3679	switch (data & 0x0c)
3711	3680	{
3712		case 0x00: set_nt_mirroring(space.machine(), PPU_MIRROR_VERT); break;
3713		case 0x04: set_nt_mirroring(space.machine(), PPU_MIRROR_HORZ); break;
3714		case 0x08: set_nt_mirroring(space.machine(), PPU_MIRROR_LOW); break;
3715		case 0x0c: set_nt_mirroring(space.machine(), PPU_MIRROR_HIGH); break;
	3681	case 0x00: set_nt_mirroring(machine(), PPU_MIRROR_VERT); break;
	3682	case 0x04: set_nt_mirroring(machine(), PPU_MIRROR_HORZ); break;
	3683	case 0x08: set_nt_mirroring(machine(), PPU_MIRROR_LOW); break;
	3684	case 0x0c: set_nt_mirroring(machine(), PPU_MIRROR_HIGH); break;
3716	3685	}
3717	3686	break;
3718	3687	case 0x5000:
r18063	r18064
3724	3693	case 0x6200:
3725	3694	case 0x6300:
3726	3695	bank = ((shifted_offs & 0x7000) - 0x5000) / 0x0400 + ((shifted_offs & 0x0300) >> 8);
3727		chr1_x(space.machine(), bank, data, CHRROM);
	3696	chr1_x(machine(), bank, data, CHRROM);
3728	3697	break;
3729	3698	case 0x7000:
3730		state->m_IRQ_count_latch = data;
	3699	m_IRQ_count_latch = data;
3731	3700	break;
3732	3701	case 0x7100:
3733		state->m_IRQ_mode = data & 0x04;   // currently not implemented: 0 = prescaler mode / 1 = CPU mode
3734		state->m_IRQ_enable = data & 0x02;
3735		state->m_IRQ_enable_latch = data & 0x01;
	3702	m_IRQ_mode = data & 0x04;   // currently not implemented: 0 = prescaler mode / 1 = CPU mode
	3703	m_IRQ_enable = data & 0x02;
	3704	m_IRQ_enable_latch = data & 0x01;
3736	3705	if (data & 0x02)
3737		state->m_IRQ_count = state->m_IRQ_count_latch;
	3706	m_IRQ_count = m_IRQ_count_latch;
3738	3707	break;
3739	3708	case 0x7200:
3740		state->m_IRQ_enable = state->m_IRQ_enable_latch;
	3709	m_IRQ_enable = m_IRQ_enable_latch;
3741	3710	break;
3742	3711	default:
3743	3712	logerror("konami_vrc6_w uncaught write, addr: %04x value: %02x\n", shifted_offs + 0x8000, data);
r18063	r18064
3758	3727
3759	3728	*************************************************************/
3760	3729
3761		static WRITE8_HANDLER( konami_vrc7_w )
	3730	WRITE8_MEMBER(nes_state::konami_vrc7_w)
3762	3731	{
3763		nes_state *state = space.machine().driver_data<nes_state>();
3764	3732	UINT8 bank;
3765	3733	LOG_MMC(("konami_vrc7_w, offset: %04x, data: %02x\n", offset, data));
3766	3734
3767	3735	switch (offset & 0x7018)
3768	3736	{
3769	3737	case 0x0000:
3770		prg8_89(space.machine(), data);
	3738	prg8_89(machine(), data);
3771	3739	break;
3772	3740	case 0x0008:
3773	3741	case 0x0010:
3774	3742	case 0x0018:
3775		prg8_ab(space.machine(), data);
	3743	prg8_ab(machine(), data);
3776	3744	break;
3777	3745
3778	3746	case 0x1000:
3779		prg8_cd(space.machine(), data);
	3747	prg8_cd(machine(), data);
3780	3748	break;
3781	3749
3782	3750	/* TODO: there are sound regs in here */
r18063	r18064
3798	3766	case 0x5010:
3799	3767	case 0x5018:
3800	3768	bank = ((offset & 0x7000) - 0x2000) / 0x0800 + ((offset & 0x0018) ? 1 : 0);
3801		chr1_x(space.machine(), bank, data, state->m_mmc_chr_source);
	3769	chr1_x(machine(), bank, data, m_mmc_chr_source);
3802	3770	break;
3803	3771
3804	3772	case 0x6000:
3805	3773	switch (data & 0x03)
3806	3774	{
3807		case 0x00: set_nt_mirroring(space.machine(), PPU_MIRROR_VERT); break;
3808		case 0x01: set_nt_mirroring(space.machine(), PPU_MIRROR_HORZ); break;
3809		case 0x02: set_nt_mirroring(space.machine(), PPU_MIRROR_LOW); break;
3810		case 0x03: set_nt_mirroring(space.machine(), PPU_MIRROR_HIGH); break;
	3775	case 0x00: set_nt_mirroring(machine(), PPU_MIRROR_VERT); break;
	3776	case 0x01: set_nt_mirroring(machine(), PPU_MIRROR_HORZ); break;
	3777	case 0x02: set_nt_mirroring(machine(), PPU_MIRROR_LOW); break;
	3778	case 0x03: set_nt_mirroring(machine(), PPU_MIRROR_HIGH); break;
3811	3779	}
3812	3780	break;
3813	3781	case 0x6008: case 0x6010: case 0x6018:
3814		state->m_IRQ_count_latch = data;
	3782	m_IRQ_count_latch = data;
3815	3783	break;
3816	3784	case 0x7000:
3817		state->m_IRQ_mode = data & 0x04;   // currently not implemented: 0 = prescaler mode / 1 = CPU mode
3818		state->m_IRQ_enable = data & 0x02;
3819		state->m_IRQ_enable_latch = data & 0x01;
	3785	m_IRQ_mode = data & 0x04;   // currently not implemented: 0 = prescaler mode / 1 = CPU mode
	3786	m_IRQ_enable = data & 0x02;
	3787	m_IRQ_enable_latch = data & 0x01;
3820	3788	if (data & 0x02)
3821		state->m_IRQ_count = state->m_IRQ_count_latch;
	3789	m_IRQ_count = m_IRQ_count_latch;
3822	3790	break;
3823	3791	case 0x7008: case 0x7010: case 0x7018:
3824		state->m_IRQ_enable = state->m_IRQ_enable_latch;
	3792	m_IRQ_enable = m_IRQ_enable_latch;
3825	3793	break;
3826	3794
3827	3795	default:
r18063	r18064
3862	3830	}
3863	3831	}
3864	3832
3865		static WRITE8_HANDLER( namcot163_l_w )
	3833	WRITE8_MEMBER(nes_state::namcot163_l_w)
3866	3834	{
3867		nes_state *state = space.machine().driver_data<nes_state>();
3868	3835	LOG_MMC(("namcot163_l_w, offset: %04x, data: %02x\n", offset, data));
3869	3836	offset += 0x100;
3870	3837
r18063	r18064
3874	3841	LOG_MMC(("Namcot-163 sound reg write, data: %02x\n", data));
3875	3842	break;
3876	3843	case 0x1000: /* low byte of IRQ */
3877		state->m_IRQ_count = (state->m_IRQ_count & 0x7f00) | data;
	3844	m_IRQ_count = (m_IRQ_count & 0x7f00) | data;
3878	3845	break;
3879	3846	case 0x1800: /* high byte of IRQ, IRQ enable in high bit */
3880		state->m_IRQ_count = (state->m_IRQ_count & 0xff) | ((data & 0x7f) << 8);
3881		state->m_IRQ_enable = data & 0x80;
	3847	m_IRQ_count = (m_IRQ_count & 0xff) | ((data & 0x7f) << 8);
	3848	m_IRQ_enable = data & 0x80;
3882	3849	break;
3883	3850	}
3884	3851	}
3885	3852
3886		static READ8_HANDLER( namcot163_l_r )
	3853	READ8_MEMBER(nes_state::namcot163_l_r)
3887	3854	{
3888		nes_state *state = space.machine().driver_data<nes_state>();
3889	3855	LOG_MMC(("namcot163_l_r, offset: %04x\n", offset));
3890	3856	offset += 0x100;
3891	3857
3892	3858	switch (offset & 0x1800)
3893	3859	{
3894	3860	case 0x1000:
3895		return state->m_IRQ_count & 0xff;
	3861	return m_IRQ_count & 0xff;
3896	3862	case 0x1800:
3897		return (state->m_IRQ_count >> 8) & 0xff;
	3863	return (m_IRQ_count >> 8) & 0xff;
3898	3864	case 0x0800:
3899	3865	LOG_MMC(("Namcot-163 sound reg read\n"));
3900	3866	default:
r18063	r18064
3910	3876	set_nt_page(machine, page, ROM, data, 0);
3911	3877	}
3912	3878
3913		static WRITE8_HANDLER( namcot163_w )
	3879	WRITE8_MEMBER(nes_state::namcot163_w)
3914	3880	{
3915		nes_state *state = space.machine().driver_data<nes_state>();
3916	3881	LOG_MMC(("namcot163_w, offset: %04x, data: %02x\n", offset, data));
3917	3882	switch (offset & 0x7800)
3918	3883	{
r18063	r18064
3920	3885	case 0x1000: case 0x1800:
3921	3886	case 0x2000: case 0x2800:
3922	3887	case 0x3000: case 0x3800:
3923		chr1_x(space.machine(), offset / 0x800, data, CHRROM);
	3888	chr1_x(machine(), offset / 0x800, data, CHRROM);
3924	3889	break;
3925	3890	case 0x4000:
3926		namcot163_set_mirror(space.machine(), 0, data);
	3891	namcot163_set_mirror(machine(), 0, data);
3927	3892	break;
3928	3893	case 0x4800:
3929		namcot163_set_mirror(space.machine(), 1, data);
	3894	namcot163_set_mirror(machine(), 1, data);
3930	3895	break;
3931	3896	case 0x5000:
3932		namcot163_set_mirror(space.machine(), 2, data);
	3897	namcot163_set_mirror(machine(), 2, data);
3933	3898	break;
3934	3899	case 0x5800:
3935		namcot163_set_mirror(space.machine(), 3, data);
	3900	namcot163_set_mirror(machine(), 3, data);
3936	3901	break;
3937	3902	case 0x6000:
3938		prg8_89(space.machine(), data & 0x3f);
	3903	prg8_89(machine(), data & 0x3f);
3939	3904	break;
3940	3905	case 0x6800:
3941		state->m_mmc_latch1 = data & 0xc0;      // this should enable High CHRRAM, but we still have to properly implement it!
3942		prg8_ab(space.machine(), data & 0x3f);
	3906	m_mmc_latch1 = data & 0xc0;      // this should enable High CHRRAM, but we still have to properly implement it!
	3907	prg8_ab(machine(), data & 0x3f);
3943	3908	break;
3944	3909	case 0x7000:
3945		prg8_cd(space.machine(), data & 0x3f);
	3910	prg8_cd(machine(), data & 0x3f);
3946	3911	break;
3947	3912	case 0x7800:
3948	3913	LOG_MMC(("Namcot-163 sound address write, data: %02x\n", data));
r18063	r18064
3962	3927
3963	3928	*************************************************************/
3964	3929
3965		static WRITE8_HANDLER( sunsoft1_m_w )
	3930	WRITE8_MEMBER(nes_state::sunsoft1_m_w)
3966	3931	{
3967		nes_state *state = space.machine().driver_data<nes_state>();
3968	3932	LOG_MMC(("sunsoft1_m_w, offset: %04x, data: %02x\n", offset, data));
3969	3933
3970		if (state->m_chr_chunks)
	3934	if (m_chr_chunks)
3971	3935	{
3972		chr4_0(space.machine(), data & 0x0f, CHRROM);
3973		chr4_4(space.machine(), data >> 4, CHRROM);
	3936	chr4_0(machine(), data & 0x0f, CHRROM);
	3937	chr4_4(machine(), data >> 4, CHRROM);
3974	3938	}
3975	3939	else
3976		prg16_89ab(space.machine(), data & 0x0f);
	3940	prg16_89ab(machine(), data & 0x0f);
3977	3941	}
3978	3942
3979	3943	/*************************************************************
r18063	r18064
3987	3951
3988	3952	*************************************************************/
3989	3953
3990		static WRITE8_HANDLER( sunsoft2_w )
	3954	WRITE8_MEMBER(nes_state::sunsoft2_w)
3991	3955	{
3992		nes_state *state = space.machine().driver_data<nes_state>();
3993	3956	UINT8 sunsoft_helper = (data & 0x07) | ((data & 0x80) ? 0x08 : 0x00);
3994	3957	LOG_MMC(("sunsoft2_w, offset: %04x, data: %02x\n", offset, data));
3995	3958
3996		if (!state->m_hard_mirroring)   // there are two 'variants' depending on hardwired or mapper ctrl mirroring
3997		set_nt_mirroring(space.machine(), BIT(data, 3) ? PPU_MIRROR_HIGH : PPU_MIRROR_LOW);
3998		if (state->m_chr_chunks)
3999		chr8(space.machine(), sunsoft_helper, CHRROM);
	3959	if (!m_hard_mirroring)   // there are two 'variants' depending on hardwired or mapper ctrl mirroring
	3960	set_nt_mirroring(machine(), BIT(data, 3) ? PPU_MIRROR_HIGH : PPU_MIRROR_LOW);
	3961	if (m_chr_chunks)
	3962	chr8(machine(), sunsoft_helper, CHRROM);
4000	3963
4001		prg16_89ab(space.machine(), data >> 4);
	3964	prg16_89ab(machine(), data >> 4);
4002	3965	}
4003	3966
4004	3967	/*************************************************************
r18063	r18064
4034	3997	}
4035	3998	}
4036	3999
4037		static WRITE8_HANDLER( sunsoft3_w )
	4000	WRITE8_MEMBER(nes_state::sunsoft3_w)
4038	4001	{
4039		nes_state *state = space.machine().driver_data<nes_state>();
4040	4002	LOG_MMC(("sunsoft3_w, offset %04x, data: %02x\n", offset, data));
4041	4003
4042	4004	switch (offset & 0x7800)
4043	4005	{
4044	4006	case 0x0800:
4045		chr2_0(space.machine(), data, CHRROM);
	4007	chr2_0(machine(), data, CHRROM);
4046	4008	break;
4047	4009	case 0x1800:
4048		chr2_2(space.machine(), data, CHRROM);
	4010	chr2_2(machine(), data, CHRROM);
4049	4011	break;
4050	4012	case 0x2800:
4051		chr2_4(space.machine(), data, CHRROM);
	4013	chr2_4(machine(), data, CHRROM);
4052	4014	break;
4053	4015	case 0x3800:
4054		chr2_6(space.machine(), data, CHRROM);
	4016	chr2_6(machine(), data, CHRROM);
4055	4017	break;
4056	4018	case 0x4000:
4057	4019	case 0x4800:
4058		state->m_IRQ_toggle ^= 1;
4059		if (state->m_IRQ_toggle)
4060		state->m_IRQ_count = (state->m_IRQ_count & 0x00ff) | (data << 8);
	4020	m_IRQ_toggle ^= 1;
	4021	if (m_IRQ_toggle)
	4022	m_IRQ_count = (m_IRQ_count & 0x00ff) | (data << 8);
4061	4023	else
4062		state->m_IRQ_count = (state->m_IRQ_count & 0xff00) | data;
	4024	m_IRQ_count = (m_IRQ_count & 0xff00) | data;
4063	4025	break;
4064	4026	case 0x5800:
4065		state->m_IRQ_enable = BIT(data, 4);
4066		state->m_IRQ_toggle = 0;
	4027	m_IRQ_enable = BIT(data, 4);
	4028	m_IRQ_toggle = 0;
4067	4029	break;
4068	4030	case 0x6800:
4069	4031	switch (data & 3)
4070	4032	{
4071		case 0x00: set_nt_mirroring(space.machine(), PPU_MIRROR_VERT); break;
4072		case 0x01: set_nt_mirroring(space.machine(), PPU_MIRROR_HORZ); break;
4073		case 0x02: set_nt_mirroring(space.machine(), PPU_MIRROR_LOW); break;
4074		case 0x03: set_nt_mirroring(space.machine(), PPU_MIRROR_HIGH); break;
	4033	case 0x00: set_nt_mirroring(machine(), PPU_MIRROR_VERT); break;
	4034	case 0x01: set_nt_mirroring(machine(), PPU_MIRROR_HORZ); break;
	4035	case 0x02: set_nt_mirroring(machine(), PPU_MIRROR_LOW); break;
	4036	case 0x03: set_nt_mirroring(machine(), PPU_MIRROR_HIGH); break;
4075	4037	}
4076	4038	break;
4077	4039	case 0x7800:
4078		prg16_89ab(space.machine(), data);
	4040	prg16_89ab(machine(), data);
4079	4041	break;
4080	4042	default:
4081	4043	LOG_MMC(("sunsoft3_w uncaught write, offset: %04x, data: %02x\n", offset, data));
r18063	r18064
4097	4059
4098	4060	*************************************************************/
4099	4061
4100		static WRITE8_HANDLER( tc0190fmc_w )
	4062	WRITE8_MEMBER(nes_state::tc0190fmc_w)
4101	4063	{
4102	4064	LOG_MMC(("tc0190fmc_w, offset: %04x, data: %02x\n", offset, data));
4103	4065
4104	4066	switch (offset & 0x7003)
4105	4067	{
4106	4068	case 0x0000:
4107		set_nt_mirroring(space.machine(), BIT(data, 6) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
4108		prg8_89(space.machine(), data);
	4069	set_nt_mirroring(machine(), BIT(data, 6) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	4070	prg8_89(machine(), data);
4109	4071	break;
4110	4072	case 0x0001:
4111		prg8_ab(space.machine(), data);
	4073	prg8_ab(machine(), data);
4112	4074	break;
4113	4075	case 0x0002:
4114		chr2_0(space.machine(), data, CHRROM);
	4076	chr2_0(machine(), data, CHRROM);
4115	4077	break;
4116	4078	case 0x0003:
4117		chr2_2(space.machine(), data, CHRROM);
	4079	chr2_2(machine(), data, CHRROM);
4118	4080	break;
4119	4081	case 0x2000:
4120		chr1_4(space.machine(), data, CHRROM);
	4082	chr1_4(machine(), data, CHRROM);
4121	4083	break;
4122	4084	case 0x2001:
4123		chr1_5(space.machine(), data, CHRROM);
	4085	chr1_5(machine(), data, CHRROM);
4124	4086	break;
4125	4087	case 0x2002:
4126		chr1_6(space.machine(), data, CHRROM);
	4088	chr1_6(machine(), data, CHRROM);
4127	4089	break;
4128	4090	case 0x2003:
4129		chr1_7(space.machine(), data, CHRROM);
	4091	chr1_7(machine(), data, CHRROM);
4130	4092	break;
4131	4093	}
4132	4094	}
r18063	r18064
4150	4112
4151	4113	*************************************************************/
4152	4114
4153		static WRITE8_HANDLER( tc0190fmc_p16_w )
	4115	WRITE8_MEMBER(nes_state::tc0190fmc_p16_w)
4154	4116	{
4155		nes_state *state = space.machine().driver_data<nes_state>();
4156	4117	LOG_MMC(("tc0190fmc_p16_w, offset: %04x, data: %02x\n", offset, data));
4157	4118
4158	4119	switch (offset & 0x7003)
4159	4120	{
4160	4121	case 0x0000:
4161		prg8_89(space.machine(), data);
	4122	prg8_89(machine(), data);
4162	4123	break;
4163	4124	case 0x0001:
4164	4125	case 0x0002:
r18063	r18064
4170	4131	tc0190fmc_w(space, offset, data, mem_mask);
4171	4132	break;
4172	4133	case 0x4000:
4173		state->m_IRQ_count_latch = (0x100 - data) & 0xff;
	4134	m_IRQ_count_latch = (0x100 - data) & 0xff;
4174	4135	break;
4175	4136	case 0x4001:
4176		state->m_IRQ_count = state->m_IRQ_count_latch;
	4137	m_IRQ_count = m_IRQ_count_latch;
4177	4138	break;
4178	4139	case 0x4002:
4179		state->m_IRQ_enable = 1;
	4140	m_IRQ_enable = 1;
4180	4141	break;
4181	4142	case 0x4003:
4182		state->m_IRQ_enable = 0;
	4143	m_IRQ_enable = 0;
4183	4144	break;
4184	4145	case 0x6000:
4185		set_nt_mirroring(space.machine(), BIT(data, 6) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	4146	set_nt_mirroring(machine(), BIT(data, 6) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
4186	4147	break;
4187	4148	}
4188	4149	}
r18063	r18064
4201	4162
4202	4163	*************************************************************/
4203	4164
4204		static WRITE8_HANDLER( x1005_m_w )
	4165	WRITE8_MEMBER(nes_state::x1005_m_w)
4205	4166	{
4206		nes_state *state = space.machine().driver_data<nes_state>();
4207	4167	LOG_MMC(("x1005_m_w, offset: %04x, data: %02x\n", offset, data));
4208	4168
4209	4169	switch (offset)
4210	4170	{
4211	4171	case 0x1ef0:
4212		chr2_0(space.machine(), (data & 0x7f) >> 1, CHRROM);
	4172	chr2_0(machine(), (data & 0x7f) >> 1, CHRROM);
4213	4173	break;
4214	4174	case 0x1ef1:
4215		chr2_2(space.machine(), (data & 0x7f) >> 1, CHRROM);
	4175	chr2_2(machine(), (data & 0x7f) >> 1, CHRROM);
4216	4176	break;
4217	4177	case 0x1ef2:
4218		chr1_4(space.machine(), data, CHRROM);
	4178	chr1_4(machine(), data, CHRROM);
4219	4179	break;
4220	4180	case 0x1ef3:
4221		chr1_5(space.machine(), data, CHRROM);
	4181	chr1_5(machine(), data, CHRROM);
4222	4182	break;
4223	4183	case 0x1ef4:
4224		chr1_6(space.machine(), data, CHRROM);
	4184	chr1_6(machine(), data, CHRROM);
4225	4185	break;
4226	4186	case 0x1ef5:
4227		chr1_7(space.machine(), data, CHRROM);
	4187	chr1_7(machine(), data, CHRROM);
4228	4188	break;
4229	4189	case 0x1ef6:
4230	4190	case 0x1ef7:
4231		set_nt_mirroring(space.machine(), BIT(data, 0) ? PPU_MIRROR_VERT : PPU_MIRROR_HORZ);
	4191	set_nt_mirroring(machine(), BIT(data, 0) ? PPU_MIRROR_VERT : PPU_MIRROR_HORZ);
4232	4192	break;
4233	4193	case 0x1ef8:
4234	4194	case 0x1ef9:
4235		state->m_mmc_latch1 = data;
	4195	m_mmc_latch1 = data;
4236	4196	break;
4237	4197	case 0x1efa:
4238	4198	case 0x1efb:
4239		prg8_89(space.machine(), data);
	4199	prg8_89(machine(), data);
4240	4200	break;
4241	4201	case 0x1efc:
4242	4202	case 0x1efd:
4243		prg8_ab(space.machine(), data);
	4203	prg8_ab(machine(), data);
4244	4204	break;
4245	4205	case 0x1efe:
4246	4206	case 0x1eff:
4247		prg8_cd(space.machine(), data);
	4207	prg8_cd(machine(), data);
4248	4208	break;
4249	4209	default:
4250	4210	logerror("mapper80_m_w uncaught addr: %04x, value: %02x\n", offset + 0x6000, data);
4251	4211	break;
4252	4212	}
4253	4213
4254		if (offset >= 0x1f00 && state->m_mapper_ram != NULL && state->m_mmc_latch1 == 0xa3)
4255		state->m_mapper_ram[offset & (state->m_mapper_ram_size - 1)] = data;
4256		else if (offset >= 0x1f00 && state->m_mapper_bram != NULL && state->m_mmc_latch1 == 0xa3)
4257		state->m_mapper_bram[offset & (state->m_mapper_bram_size - 1)] = data;
	4214	if (offset >= 0x1f00 && m_mapper_ram != NULL && m_mmc_latch1 == 0xa3)
	4215	m_mapper_ram[offset & (m_mapper_ram_size - 1)] = data;
	4216	else if (offset >= 0x1f00 && m_mapper_bram != NULL && m_mmc_latch1 == 0xa3)
	4217	m_mapper_bram[offset & (m_mapper_bram_size - 1)] = data;
4258	4218	}
4259	4219
4260		static READ8_HANDLER( x1005_m_r )
	4220	READ8_MEMBER(nes_state::x1005_m_r)
4261	4221	{
4262		nes_state *state = space.machine().driver_data<nes_state>();
4263	4222	LOG_MMC(("x1005a_m_r, offset: %04x\n", offset));
4264	4223
4265		if (offset >= 0x1f00 && state->m_mapper_ram != NULL && state->m_mmc_latch1 == 0xa3)
4266		return state->m_mapper_ram[offset & (state->m_mapper_ram_size - 1)];
4267		else if (offset >= 0x1f00 && state->m_mapper_bram != NULL && state->m_mmc_latch1 == 0xa3)
4268		return state->m_mapper_bram[offset & (state->m_mapper_bram_size - 1)];
	4224	if (offset >= 0x1f00 && m_mapper_ram != NULL && m_mmc_latch1 == 0xa3)
	4225	return m_mapper_ram[offset & (m_mapper_ram_size - 1)];
	4226	else if (offset >= 0x1f00 && m_mapper_bram != NULL && m_mmc_latch1 == 0xa3)
	4227	return m_mapper_bram[offset & (m_mapper_bram_size - 1)];
4269	4228
4270	4229	return 0xff;
4271	4230	}
4272	4231
4273		static WRITE8_HANDLER( x1005a_m_w )
	4232	WRITE8_MEMBER(nes_state::x1005a_m_w)
4274	4233	{
4275	4234	LOG_MMC(("x1005a_m_w, offset: %04x, data: %02x\n", offset, data));
4276	4235
r18063	r18064
4281	4240	switch (offset)
4282	4241	{
4283	4242	case 0x1ef0:
4284		set_nt_page(space.machine(), 0, CIRAM, (data & 0x80) ? 1 : 0, 1);
4285		set_nt_page(space.machine(), 1, CIRAM, (data & 0x80) ? 1 : 0, 1);
	4243	set_nt_page(machine(), 0, CIRAM, (data & 0x80) ? 1 : 0, 1);
	4244	set_nt_page(machine(), 1, CIRAM, (data & 0x80) ? 1 : 0, 1);
4286	4245	break;
4287	4246	case 0x1ef1:
4288		set_nt_page(space.machine(), 2, CIRAM, (data & 0x80) ? 1 : 0, 1);
4289		set_nt_page(space.machine(), 3, CIRAM, (data & 0x80) ? 1 : 0, 1);
	4247	set_nt_page(machine(), 2, CIRAM, (data & 0x80) ? 1 : 0, 1);
	4248	set_nt_page(machine(), 3, CIRAM, (data & 0x80) ? 1 : 0, 1);
4290	4249	break;
4291	4250	}
4292	4251
r18063	r18064
4328	4287	chr1_x(machine, 7 ^ state->m_mmc_latch1, state->m_mmc_vrom_bank[5], CHRROM);
4329	4288	}
4330	4289
4331		static WRITE8_HANDLER( x1017_m_w )
	4290	WRITE8_MEMBER(nes_state::x1017_m_w)
4332	4291	{
4333		nes_state *state = space.machine().driver_data<nes_state>();
4334	4292	UINT8 reg = offset & 0x07;
4335	4293	LOG_MMC(("x1017_m_w, offset: %04x, data: %02x\n", offset, data));
4336	4294
r18063	r18064
4338	4296	{
4339	4297	case 0x1ef0:
4340	4298	case 0x1ef1:
4341		if (state->m_mmc_vrom_bank[reg] != data)
	4299	if (m_mmc_vrom_bank[reg] != data)
4342	4300	{
4343		state->m_mmc_vrom_bank[reg] = data;
4344		x1017_set_chr(space.machine());
	4301	m_mmc_vrom_bank[reg] = data;
	4302	x1017_set_chr(machine());
4345	4303	}
4346	4304	break;
4347	4305	case 0x1ef2:
4348	4306	case 0x1ef3:
4349	4307	case 0x1ef4:
4350	4308	case 0x1ef5:
4351		if (state->m_mmc_vrom_bank[reg] != data)
	4309	if (m_mmc_vrom_bank[reg] != data)
4352	4310	{
4353		state->m_mmc_vrom_bank[reg] = data;
4354		x1017_set_chr(space.machine());
	4311	m_mmc_vrom_bank[reg] = data;
	4312	x1017_set_chr(machine());
4355	4313	}
4356	4314	break;
4357	4315	case 0x1ef6:
4358		set_nt_mirroring(space.machine(), BIT(data, 0) ? PPU_MIRROR_VERT : PPU_MIRROR_HORZ);
4359		state->m_mmc_latch1 = ((data & 0x02) << 1);
4360		x1017_set_chr(space.machine());
	4316	set_nt_mirroring(machine(), BIT(data, 0) ? PPU_MIRROR_VERT : PPU_MIRROR_HORZ);
	4317	m_mmc_latch1 = ((data & 0x02) << 1);
	4318	x1017_set_chr(machine());
4361	4319	break;
4362	4320	case 0x1ef7:
4363	4321	case 0x1ef8:
4364	4322	case 0x1ef9:
4365		state->m_mmc_reg[(offset & 0x0f) - 7] = data;
	4323	m_mmc_reg[(offset & 0x0f) - 7] = data;
4366	4324	break;
4367	4325	case 0x1efa:
4368		prg8_89(space.machine(), data >> 2);
	4326	prg8_89(machine(), data >> 2);
4369	4327	break;
4370	4328	case 0x1efb:
4371		prg8_ab(space.machine(), data >> 2);
	4329	prg8_ab(machine(), data >> 2);
4372	4330	break;
4373	4331	case 0x1efc:
4374		prg8_cd(space.machine(), data >> 2);
	4332	prg8_cd(machine(), data >> 2);
4375	4333	break;
4376	4334	default:
4377	4335	logerror("x1017_m_w uncaught write, addr: %04x, value: %02x\n", offset + 0x6000, data);
r18063	r18064
4379	4337	}
4380	4338	}
4381	4339
4382		static READ8_HANDLER( x1017_m_r )
	4340	READ8_MEMBER(nes_state::x1017_m_r)
4383	4341	{
4384		nes_state *state = space.machine().driver_data<nes_state>();
4385	4342	LOG_MMC(("x1017_m_r, offset: %04x\n", offset));
4386	4343
4387	4344	// 2+2+1 KB of Internal RAM can be independently enabled/disabled!
4388		if (offset < 0x0800 && state->m_mapper_bram != NULL && state->m_mmc_reg[0] == 0xca)
4389		return state->m_mapper_bram[offset & (state->m_mapper_bram_size - 1)];
4390		if (offset < 0x1000 && state->m_mapper_bram != NULL && state->m_mmc_reg[1] == 0x69)
4391		return state->m_mapper_bram[offset & (state->m_mapper_bram_size - 1)];
4392		if (offset < 0x1800 && state->m_mapper_bram != NULL && state->m_mmc_reg[2] == 0x84)
4393		return state->m_mapper_bram[offset & (state->m_mapper_bram_size - 1)];
	4345	if (offset < 0x0800 && m_mapper_bram != NULL && m_mmc_reg[0] == 0xca)
	4346	return m_mapper_bram[offset & (m_mapper_bram_size - 1)];
	4347	if (offset < 0x1000 && m_mapper_bram != NULL && m_mmc_reg[1] == 0x69)
	4348	return m_mapper_bram[offset & (m_mapper_bram_size - 1)];
	4349	if (offset < 0x1800 && m_mapper_bram != NULL && m_mmc_reg[2] == 0x84)
	4350	return m_mapper_bram[offset & (m_mapper_bram_size - 1)];
4394	4351
4395	4352	return 0xff;
4396	4353	}
r18063	r18064
4413	4370
4414	4371	*************************************************************/
4415	4372
4416		static WRITE8_HANDLER( agci_50282_w )
	4373	WRITE8_MEMBER(nes_state::agci_50282_w)
4417	4374	{
4418	4375	LOG_MMC(("agci_50282_w, offset: %04x, data: %02x\n", offset, data));
4419	4376
4420	4377	offset += 0x8000;
4421	4378	data |= (space.read_byte(offset) & 1);
4422	4379
4423		chr8(space.machine(), data >> 4, CHRROM);
4424		prg32(space.machine(), data);
	4380	chr8(machine(), data >> 4, CHRROM);
	4381	prg32(machine(), data);
4425	4382	}
4426	4383
4427	4384	/*************************************************************
r18063	r18064
4432	4389
4433	4390	*************************************************************/
4434	4391
4435		static WRITE8_HANDLER( nina01_m_w )
	4392	WRITE8_MEMBER(nes_state::nina01_m_w)
4436	4393	{
4437	4394	LOG_MMC(("nina01_m_w, offset: %04x, data: %02x\n", offset, data));
4438	4395
4439	4396	switch (offset)
4440	4397	{
4441	4398	case 0x1ffd:
4442		prg32(space.machine(), data);
	4399	prg32(machine(), data);
4443	4400	break;
4444	4401	case 0x1ffe:
4445		chr4_0(space.machine(), data, CHRROM);
	4402	chr4_0(machine(), data, CHRROM);
4446	4403	break;
4447	4404	case 0x1fff:
4448		chr4_4(space.machine(), data, CHRROM);
	4405	chr4_4(machine(), data, CHRROM);
4449	4406	break;
4450	4407	}
4451	4408	}
r18063	r18064
4463	4420
4464	4421	*************************************************************/
4465	4422
4466		static WRITE8_HANDLER( nina06_l_w )
	4423	WRITE8_MEMBER(nes_state::nina06_l_w)
4467	4424	{
4468	4425	LOG_MMC(("nina06_l_w, offset: %04x, data: %02x\n", offset, data));
4469	4426
4470	4427	if (!(offset & 0x0100))
4471	4428	{
4472		prg32(space.machine(), data >> 3);
4473		chr8(space.machine(), data, CHRROM);
	4429	prg32(machine(), data >> 3);
	4430	chr8(machine(), data, CHRROM);
4474	4431	}
4475	4432	}
4476	4433
r18063	r18064
4482	4439
4483	4440	*************************************************************/
4484	4441
4485		static WRITE8_HANDLER( ae_act52_w )
	4442	WRITE8_MEMBER(nes_state::ae_act52_w)
4486	4443	{
4487	4444	int pbank, cbank;
4488	4445	UINT8 pmode;
4489	4446	LOG_MMC(("ae_act52_w, offset: %04x, data: %02x\n", offset, data));
4490	4447
4491		set_nt_mirroring(space.machine(), BIT(offset, 13) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	4448	set_nt_mirroring(machine(), BIT(offset, 13) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
4492	4449
4493	4450	cbank = (data & 0x03) | ((offset & 0x0f) << 2);
4494		chr8(space.machine(), cbank, CHRROM);
	4451	chr8(machine(), cbank, CHRROM);
4495	4452
4496	4453	pmode = offset & 0x20;
4497	4454	pbank = (offset & 0x1fc0) >> 6;
4498	4455	if (pmode)
4499	4456	{
4500		prg16_89ab(space.machine(), pbank);
4501		prg16_cdef(space.machine(), pbank);
	4457	prg16_89ab(machine(), pbank);
	4458	prg16_cdef(machine(), pbank);
4502	4459	}
4503	4460	else
4504		prg32(space.machine(), pbank >> 1);
	4461	prg32(machine(), pbank >> 1);
4505	4462	}
4506	4463
4507	4464
r18063	r18064
4520	4477
4521	4478	*************************************************************/
4522	4479
4523		static WRITE8_HANDLER( cne_decathl_w )
	4480	WRITE8_MEMBER(nes_state::cne_decathl_w)
4524	4481	{
4525	4482	LOG_MMC(("cne_decathl_w, offset: %04x, data: %02x\n", offset, data));
4526	4483
r18063	r18064
4528	4485	return;
4529	4486	if (offset < 0x00a5)
4530	4487	{
4531		prg32(space.machine(), (offset - 0x0065) & 0x03);
	4488	prg32(machine(), (offset - 0x0065) & 0x03);
4532	4489	return;
4533	4490	}
4534	4491	if (offset < 0x00e5)
4535	4492	{
4536		chr8(space.machine(), (offset - 0x00a5) & 0x07, CHRROM);
	4493	chr8(machine(), (offset - 0x00a5) & 0x07, CHRROM);
4537	4494	}
4538	4495	}
4539	4496
r18063	r18064
4554	4511
4555	4512	*************************************************************/
4556	4513
4557		static WRITE8_HANDLER( cne_fsb_m_w )
	4514	WRITE8_MEMBER(nes_state::cne_fsb_m_w)
4558	4515	{
4559		nes_state *state = space.machine().driver_data<nes_state>();
4560	4516	LOG_MMC(("cne_fsb_m_w, offset: %04x, data: %02x\n", offset, data));
4561	4517
4562	4518	if (offset < 0x0800)
r18063	r18064
4564	4520	switch (offset & 0x0007)
4565	4521	{
4566	4522	case 0x0000:
4567		prg8_89(space.machine(), data);
	4523	prg8_89(machine(), data);
4568	4524	break;
4569	4525	case 0x0001:
4570		prg8_ab(space.machine(), data);
	4526	prg8_ab(machine(), data);
4571	4527	break;
4572	4528	case 0x0002:
4573		prg8_cd(space.machine(), data);
	4529	prg8_cd(machine(), data);
4574	4530	break;
4575	4531	case 0x0003:
4576		prg8_ef(space.machine(), data);
	4532	prg8_ef(machine(), data);
4577	4533	break;
4578	4534	case 0x0004:
4579		chr2_0(space.machine(), data, CHRROM);
	4535	chr2_0(machine(), data, CHRROM);
4580	4536	break;
4581	4537	case 0x0005:
4582		chr2_2(space.machine(), data, CHRROM);
	4538	chr2_2(machine(), data, CHRROM);
4583	4539	break;
4584	4540	case 0x0006:
4585		chr2_4(space.machine(), data, CHRROM);
	4541	chr2_4(machine(), data, CHRROM);
4586	4542	break;
4587	4543	case 0x0007:
4588		chr2_6(space.machine(), data, CHRROM);
	4544	chr2_6(machine(), data, CHRROM);
4589	4545	break;
4590	4546	}
4591	4547	}
4592	4548	else
4593		state->m_battery_ram[offset] = data;
	4549	m_battery_ram[offset] = data;
4594	4550	}
4595	4551
4596	4552	/*************************************************************
r18063	r18064
4610	4566
4611	4567	*************************************************************/
4612	4568
4613		static WRITE8_HANDLER( cne_shlz_l_w )
	4569	WRITE8_MEMBER(nes_state::cne_shlz_l_w)
4614	4570	{
4615	4571	LOG_MMC(("cne_shlz_l_w, offset: %04x, data: %02x\n", offset, data));
4616	4572
4617		prg32(space.machine(), data >> 4);
4618		chr8(space.machine(), data & 0x0f, CHRROM);
	4573	prg32(machine(), data >> 4);
	4574	chr8(machine(), data & 0x0f, CHRROM);
4619	4575	}
4620	4576
4621	4577	/*************************************************************
r18063	r18064
4630	4586
4631	4587	*************************************************************/
4632	4588
4633		static WRITE8_HANDLER( caltron6in1_m_w )
	4589	WRITE8_MEMBER(nes_state::caltron6in1_m_w)
4634	4590	{
4635		nes_state *state = space.machine().driver_data<nes_state>();
4636	4591	LOG_MMC(("caltron6in1_m_w, offset: %04x, data: %02x\n", offset, data));
4637	4592
4638		state->m_mmc_latch1 = offset & 0xff;
4639		set_nt_mirroring(space.machine(), BIT(data, 5) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
4640		prg32(space.machine(), offset & 0x07);
	4593	m_mmc_latch1 = offset & 0xff;
	4594	set_nt_mirroring(machine(), BIT(data, 5) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	4595	prg32(machine(), offset & 0x07);
4641	4596	}
4642	4597
4643		static WRITE8_HANDLER( caltron6in1_w )
	4598	WRITE8_MEMBER(nes_state::caltron6in1_w)
4644	4599	{
4645		nes_state *state = space.machine().driver_data<nes_state>();
4646	4600	LOG_MMC(("caltron6in1_w, offset: %04x, data: %02x\n", offset, data));
4647	4601
4648		if (state->m_mmc_latch1 & 0x04)
4649		chr8(space.machine(), ((state->m_mmc_latch1 & 0x18) >> 1) | (data & 0x03), CHRROM);
	4602	if (m_mmc_latch1 & 0x04)
	4603	chr8(machine(), ((m_mmc_latch1 & 0x18) >> 1) | (data & 0x03), CHRROM);
4650	4604	}
4651	4605
4652	4606	/*************************************************************
r18063	r18064
4666	4620
4667	4621	*************************************************************/
4668	4622
4669		static WRITE8_HANDLER( bf9093_w )
	4623	WRITE8_MEMBER(nes_state::bf9093_w)
4670	4624	{
4671		nes_state *state = space.machine().driver_data<nes_state>();
4672	4625	LOG_MMC(("bf9093_w, offset: %04x, data: %02x\n", offset, data));
4673	4626
4674	4627	switch (offset & 0x7000)
4675	4628	{
4676	4629	case 0x0000:
4677	4630	case 0x1000:
4678		if (!state->m_hard_mirroring)
4679		set_nt_mirroring(space.machine(), BIT(data, 4) ? PPU_MIRROR_HIGH : PPU_MIRROR_LOW);
	4631	if (!m_hard_mirroring)
	4632	set_nt_mirroring(machine(), BIT(data, 4) ? PPU_MIRROR_HIGH : PPU_MIRROR_LOW);
4680	4633	break;
4681	4634	case 0x4000:
4682	4635	case 0x5000:
4683	4636	case 0x6000:
4684	4637	case 0x7000:
4685		prg16_89ab(space.machine(), data);
	4638	prg16_89ab(machine(), data);
4686	4639	break;
4687	4640	}
4688	4641	}
r18063	r18064
4712	4665	prg16_cdef(machine, 0x03 | ((state->m_mmc_latch1 & 0x18) >> 1));
4713	4666	}
4714	4667
4715		static WRITE8_HANDLER( bf9096_w )
	4668	WRITE8_MEMBER(nes_state::bf9096_w)
4716	4669	{
4717		nes_state *state = space.machine().driver_data<nes_state>();
4718	4670	LOG_MMC(("bf9096_w, offset: %04x, data: %02x\n", offset, data));
4719	4671
4720	4672	if (offset < 0x2000)
4721		state->m_mmc_latch1 = data;
	4673	m_mmc_latch1 = data;
4722	4674	else
4723		state->m_mmc_latch2 = data;
	4675	m_mmc_latch2 = data;
4724	4676
4725		bf9096_set_prg(space.machine());
	4677	bf9096_set_prg(machine());
4726	4678	}
4727	4679
4728	4680	/*************************************************************
r18063	r18064
4737	4689
4738	4690	*************************************************************/
4739	4691
4740		static WRITE8_HANDLER( golden5_w )
	4692	WRITE8_MEMBER(nes_state::golden5_w)
4741	4693	{
4742		nes_state *state = space.machine().driver_data<nes_state>();
4743	4694	LOG_MMC(("golden5_w, offset: %04x, data: %02x\n", offset, data));
4744	4695
4745	4696	if (offset < 0x4000)
4746	4697	{
4747	4698	if (data & 0x08)
4748	4699	{
4749		state->m_mmc_prg_bank[0] = ((data & 0x07) << 4) | (state->m_mmc_prg_bank[0] & 0x0f);
4750		prg16_89ab(space.machine(), state->m_mmc_prg_bank[0]);
4751		prg16_cdef(space.machine(), ((data & 0x07) << 4) | 0x0f);
	4700	m_mmc_prg_bank[0] = ((data & 0x07) << 4) | (m_mmc_prg_bank[0] & 0x0f);
	4701	prg16_89ab(machine(), m_mmc_prg_bank[0]);
	4702	prg16_cdef(machine(), ((data & 0x07) << 4) | 0x0f);
4752	4703	}
4753	4704
4754	4705	}
4755	4706	else
4756	4707	{
4757		state->m_mmc_prg_bank[0] = (state->m_mmc_prg_bank[0] & 0x70) | (data & 0x0f);
4758		prg16_89ab(space.machine(), state->m_mmc_prg_bank[0]);
	4708	m_mmc_prg_bank[0] = (m_mmc_prg_bank[0] & 0x70) | (data & 0x0f);
	4709	prg16_89ab(machine(), m_mmc_prg_bank[0]);
4759	4710	}
4760	4711	}
4761	4712
r18063	r18064
4772	4723
4773	4724	*************************************************************/
4774	4725
4775		static WRITE8_HANDLER( cony_l_w )
	4726	WRITE8_MEMBER(nes_state::cony_l_w)
4776	4727	{
4777		nes_state *state = space.machine().driver_data<nes_state>();
4778	4728	LOG_MMC(("cony_l_w, offset: %04x, data: %02x\n", offset, data));
4779	4729
4780	4730	if (offset >= 0x1000 && offset < 0x1103) // from 0x5100-0x51ff
4781		state->m_mapper83_low_reg[offset & 0x03] = data;
	4731	m_mapper83_low_reg[offset & 0x03] = data;
4782	4732	}
4783	4733
4784		static READ8_HANDLER( cony_l_r )
	4734	READ8_MEMBER(nes_state::cony_l_r)
4785	4735	{
4786		nes_state *state = space.machine().driver_data<nes_state>();
4787	4736	LOG_MMC(("cony_l_r, offset: %04x\n", offset));
4788	4737
4789	4738	if (offset == 0x0f00)   // 0x5000
r18063	r18064
4791	4740	// read dipswitch bit! - currently unimplemented
4792	4741	}
4793	4742	if (offset >= 0x1000 && offset < 0x1103) // from 0x5100-0x51ff
4794		return state->m_mapper83_low_reg[offset & 0x03];
	4743	return m_mapper83_low_reg[offset & 0x03];
4795	4744	else
4796	4745	return 0x00;
4797	4746	}
r18063	r18064
4831	4780	}
4832	4781	}
4833	4782
4834		static WRITE8_HANDLER( cony_w )
	4783	WRITE8_MEMBER(nes_state::cony_w)
4835	4784	{
4836		nes_state *state = space.machine().driver_data<nes_state>();
4837	4785	LOG_MMC(("cony_w, offset: %04x, data: %02x\n", offset, data));
4838	4786
4839	4787	switch (offset)
4840	4788	{
4841	4789	case 0x0000:
4842		state->m_mmc_latch1 = 1;
	4790	m_mmc_latch1 = 1;
4843	4791	case 0x3000:
4844	4792	case 0x30ff:
4845	4793	case 0x31ff:
4846		state->m_mapper83_reg[8] = data;
4847		cony_set_prg(space.machine());
4848		cony_set_chr(space.machine());
	4794	m_mapper83_reg[8] = data;
	4795	cony_set_prg(machine());
	4796	cony_set_chr(machine());
4849	4797	break;
4850	4798	case 0x0100:
4851		state->m_mmc_reg[0] = data & 0x80;
	4799	m_mmc_reg[0] = data & 0x80;
4852	4800	switch (data & 0x03)
4853	4801	{
4854	4802	case 0:
4855		set_nt_mirroring(space.machine(), PPU_MIRROR_VERT);
	4803	set_nt_mirroring(machine(), PPU_MIRROR_VERT);
4856	4804	break;
4857	4805	case 1:
4858		set_nt_mirroring(space.machine(), PPU_MIRROR_HORZ);
	4806	set_nt_mirroring(machine(), PPU_MIRROR_HORZ);
4859	4807	break;
4860	4808	case 2:
4861		set_nt_mirroring(space.machine(), PPU_MIRROR_LOW);
	4809	set_nt_mirroring(machine(), PPU_MIRROR_LOW);
4862	4810	break;
4863	4811	case 3:
4864		set_nt_mirroring(space.machine(), PPU_MIRROR_HIGH);
	4812	set_nt_mirroring(machine(), PPU_MIRROR_HIGH);
4865	4813	break;
4866	4814	}
4867	4815	break;
4868	4816	case 0x0200:
4869		state->m_IRQ_count = (state->m_IRQ_count & 0xff00) | data;
	4817	m_IRQ_count = (m_IRQ_count & 0xff00) | data;
4870	4818	break;
4871	4819	case 0x0201:
4872		state->m_IRQ_enable = state->m_mmc_reg[0];
4873		state->m_IRQ_count = (data << 8) | (state->m_IRQ_count & 0xff);
	4820	m_IRQ_enable = m_mmc_reg[0];
	4821	m_IRQ_count = (data << 8) | (m_IRQ_count & 0xff);
4874	4822	break;
4875	4823	case 0x0300:
4876		prg8_89(space.machine(), data);
	4824	prg8_89(machine(), data);
4877	4825	break;
4878	4826	case 0x0301:
4879		prg8_ab(space.machine(), data);
	4827	prg8_ab(machine(), data);
4880	4828	break;
4881	4829	case 0x0302:
4882		prg8_cd(space.machine(), data);
	4830	prg8_cd(machine(), data);
4883	4831	break;
4884	4832	case 0x0312:
4885	4833	case 0x0313:
4886	4834	case 0x0314:
4887	4835	case 0x0315:
4888		state->m_mmc_latch2 = 1;
	4836	m_mmc_latch2 = 1;
4889	4837	case 0x0310:
4890	4838	case 0x0311:
4891	4839	case 0x0316:
4892	4840	case 0x0317:
4893		state->m_mapper83_reg[offset - 0x0310] = data;
4894		cony_set_chr(space.machine());
	4841	m_mapper83_reg[offset - 0x0310] = data;
	4842	cony_set_chr(machine());
4895	4843	break;
4896	4844	case 0x0318:
4897		state->m_mapper83_reg[9] = data;
4898		cony_set_prg(space.machine());
	4845	m_mapper83_reg[9] = data;
	4846	cony_set_prg(machine());
4899	4847	break;
4900	4848	}
4901	4849	}
r18063	r18064
4913	4861
4914	4862	*************************************************************/
4915	4863
4916		static WRITE8_HANDLER( yoko_l_w )
	4864	WRITE8_MEMBER(nes_state::yoko_l_w)
4917	4865	{
4918		nes_state *state = space.machine().driver_data<nes_state>();
4919	4866	LOG_MMC(("cony_l_w, offset: %04x, data: %02x\n", offset, data));
4920	4867
4921	4868	if (offset >= 0x1300) // from 0x5400
4922		state->m_mapper83_low_reg[offset & 0x03] = data;
	4869	m_mapper83_low_reg[offset & 0x03] = data;
4923	4870	}
4924	4871
4925		static READ8_HANDLER( yoko_l_r )
	4872	READ8_MEMBER(nes_state::yoko_l_r)
4926	4873	{
4927		nes_state *state = space.machine().driver_data<nes_state>();
4928	4874	LOG_MMC(("cony_l_r, offset: %04x\n", offset));
4929	4875
4930	4876	if (offset >= 0x0f00 && offset < 0x1300)   // 0x5000
r18063	r18064
4932	4878	// read dipswitch bit! - currently unimplemented
4933	4879	}
4934	4880	if (offset >= 0x1300) // from 0x5400
4935		return state->m_mapper83_low_reg[offset & 0x03];
	4881	return m_mapper83_low_reg[offset & 0x03];
4936	4882	else
4937	4883	return 0x00;
4938	4884	}
r18063	r18064
4966	4912	chr2_6(machine, state->m_mapper83_reg[7], CHRROM);
4967	4913	}
4968	4914
4969		static WRITE8_HANDLER( yoko_w )
	4915	WRITE8_MEMBER(nes_state::yoko_w)
4970	4916	{
4971		nes_state *state = space.machine().driver_data<nes_state>();
4972	4917	LOG_MMC(("yoko_w, offset: %04x, data: %02x\n", offset, data));
4973	4918
4974	4919	switch (offset & 0x0c17)
4975	4920	{
4976	4921	case 0x0000:
4977		state->m_mmc_reg[1] = data;
4978		yoko_set_prg(space.machine());
	4922	m_mmc_reg[1] = data;
	4923	yoko_set_prg(machine());
4979	4924	break;
4980	4925	case 0x400:
4981		state->m_mmc_reg[0] = data;
	4926	m_mmc_reg[0] = data;
4982	4927	if (data & 1)
4983		set_nt_mirroring(space.machine(), PPU_MIRROR_HORZ);
	4928	set_nt_mirroring(machine(), PPU_MIRROR_HORZ);
4984	4929	else
4985		set_nt_mirroring(space.machine(), PPU_MIRROR_VERT);
4986		yoko_set_prg(space.machine());
	4930	set_nt_mirroring(machine(), PPU_MIRROR_VERT);
	4931	yoko_set_prg(machine());
4987	4932	break;
4988	4933	case 0x0800:
4989		state->m_IRQ_count = (state->m_IRQ_count & 0xff00) | data;
	4934	m_IRQ_count = (m_IRQ_count & 0xff00) | data;
4990	4935	break;
4991	4936	case 0x0801:
4992		state->m_IRQ_enable = state->m_mmc_reg[0] & 0x80;
4993		state->m_IRQ_count = (data << 8) | (state->m_IRQ_count & 0xff);
	4937	m_IRQ_enable = m_mmc_reg[0] & 0x80;
	4938	m_IRQ_count = (data << 8) | (m_IRQ_count & 0xff);
4994	4939	break;
4995	4940	case 0x0c00:
4996	4941	case 0x0c01:
4997	4942	case 0x0c02:
4998		state->m_mapper83_reg[offset & 3] = data;
4999		yoko_set_prg(space.machine());
	4943	m_mapper83_reg[offset & 3] = data;
	4944	yoko_set_prg(machine());
5000	4945	break;
5001	4946	case 0x0c10:
5002	4947	case 0x0c11:
5003	4948	case 0x0c16:
5004	4949	case 0x0c17:
5005		state->m_mapper83_reg[4 + (offset & 3)] = data;
5006		yoko_set_chr(space.machine());
	4950	m_mapper83_reg[4 + (offset & 3)] = data;
	4951	yoko_set_chr(machine());
5007	4952	break;
5008	4953	}
5009	4954	}
r18063	r18064
5018	4963
5019	4964	*************************************************************/
5020	4965
5021		static WRITE8_HANDLER( dreamtech_l_w )
	4966	WRITE8_MEMBER(nes_state::dreamtech_l_w)
5022	4967	{
5023	4968	LOG_MMC(("dreamtech_l_w offset: %04x, data: %02x\n", offset, data));
5024	4969	offset += 0x100;
5025	4970
5026	4971	if (offset == 0x1020)   /* 0x5020 */
5027		prg16_89ab(space.machine(), data);
	4972	prg16_89ab(machine(), data);
5028	4973	}
5029	4974
5030	4975	/*************************************************************
r18063	r18064
5040	4985
5041	4986	*************************************************************/
5042	4987
5043		static WRITE8_HANDLER( fukutake_l_w )
	4988	WRITE8_MEMBER(nes_state::fukutake_l_w)
5044	4989	{
5045		nes_state *state = space.machine().driver_data<nes_state>();
5046	4990	LOG_MMC(("fukutake_l_w offset: %04x, data: %02x\n", offset, data));
5047	4991	offset += 0x100;
5048	4992
5049	4993	if (offset >= 0x200 && offset < 0x400)
5050	4994	{
5051	4995	if (offset & 1)
5052		prg16_89ab(space.machine(), data);
	4996	prg16_89ab(machine(), data);
5053	4997	else
5054		wram_bank(space.machine(), data >> 6, NES_WRAM);
	4998	wram_bank(machine(), data >> 6, NES_WRAM);
5055	4999	}
5056	5000	else if (offset >= 0x400 && offset < 0xf00)
5057		state->m_mapper_ram[offset - 0x400] = data;
	5001	m_mapper_ram[offset - 0x400] = data;
5058	5002	}
5059	5003
5060		static READ8_HANDLER( fukutake_l_r )
	5004	READ8_MEMBER(nes_state::fukutake_l_r)
5061	5005	{
5062		nes_state *state = space.machine().driver_data<nes_state>();
5063	5006	LOG_MMC(("fukutake_l_r offset: %04x\n", offset));
5064	5007	offset += 0x100;
5065	5008
r18063	r18064
5073	5016	return 0xff;
5074	5017	}
5075	5018	else if (offset >= 0x400 && offset < 0xf00)
5076		return state->m_mapper_ram[offset - 0x400];
	5019	return m_mapper_ram[offset - 0x400];
5077	5020
5078	5021	return 0;
5079	5022	}
r18063	r18064
5104	5047	}
5105	5048	}
5106	5049
5107		static WRITE8_HANDLER( futuremedia_w )
	5050	WRITE8_MEMBER(nes_state::futuremedia_w)
5108	5051	{
5109		nes_state *state = space.machine().driver_data<nes_state>();
5110	5052	LOG_MMC(("futuremedia_w, offset: %04x, data: %02x\n", offset, data));
5111	5053
5112	5054	switch (offset)
5113	5055	{
5114	5056	case 0x0000:
5115		prg8_89(space.machine(), data);
	5057	prg8_89(machine(), data);
5116	5058	break;
5117	5059	case 0x0001:
5118		prg8_ab(space.machine(), data);
	5060	prg8_ab(machine(), data);
5119	5061	break;
5120	5062	case 0x0002:
5121		prg8_cd(space.machine(), data);
	5063	prg8_cd(machine(), data);
5122	5064	break;
5123	5065	case 0x0003:
5124		prg8_ef(space.machine(), data);
	5066	prg8_ef(machine(), data);
5125	5067	break;
5126	5068	case 0x2000:
5127	5069	case 0x2001:
r18063	r18064
5131	5073	case 0x2005:
5132	5074	case 0x2006:
5133	5075	case 0x2007:
5134		chr1_x(space.machine(), offset & 0x07, data, CHRROM);
	5076	chr1_x(machine(), offset & 0x07, data, CHRROM);
5135	5077	break;
5136	5078
5137	5079	case 0x5000:
5138		set_nt_mirroring(space.machine(), BIT(data, 0) ?  PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	5080	set_nt_mirroring(machine(), BIT(data, 0) ?  PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
5139	5081	break;
5140	5082
5141	5083	case 0x4001:
5142		state->m_IRQ_count_latch = data;
	5084	m_IRQ_count_latch = data;
5143	5085	break;
5144	5086	case 0x4002:
5145	5087	// IRQ cleared
5146	5088	break;
5147	5089	case 0x4003:
5148		state->m_IRQ_count = state->m_IRQ_count_latch;
	5090	m_IRQ_count = m_IRQ_count_latch;
5149	5091	break;
5150	5092	case 0x6000:
5151		state->m_IRQ_enable = data & 0x01;
	5093	m_IRQ_enable = data & 0x01;
5152	5094	break;
5153	5095	}
5154	5096	}
r18063	r18064
5167	5109
5168	5110	*************************************************************/
5169	5111
5170		static WRITE8_HANDLER( gouder_sf4_l_w )
	5112	WRITE8_MEMBER(nes_state::gouder_sf4_l_w)
5171	5113	{
5172		nes_state *state = space.machine().driver_data<nes_state>();
5173	5114	static const UINT8 conv_table[256] =
5174	5115	{
5175	5116	0x59,0x59,0x59,0x59,0x59,0x59,0x59,0x59,0x59,0x49,0x19,0x09,0x59,0x49,0x19,0x09,
r18063	r18064
5193	5134	LOG_MMC(("gouder_sf4_l_w, offset: %04x, data: %02x\n", offset, data));
5194	5135
5195	5136	if (!(offset < 0x1700))
5196		state->m_mmc_reg[offset & 0x03] = data ^ conv_table[state->m_mmc_reg[4]];
	5137	m_mmc_reg[offset & 0x03] = data ^ conv_table[m_mmc_reg[4]];
5197	5138	else if (!(offset < 0xf00))
5198		state->m_mmc_reg[4] = data;
	5139	m_mmc_reg[4] = data;
5199	5140	else if (!(offset < 0x700))
5200		prg32(space.machine(), ((data >> 3) & 0x02) | (data & 0x01));
	5141	prg32(machine(), ((data >> 3) & 0x02) | (data & 0x01));
5201	5142	}
5202	5143
5203		static READ8_HANDLER( gouder_sf4_l_r )
	5144	READ8_MEMBER(nes_state::gouder_sf4_l_r)
5204	5145	{
5205		nes_state *state = space.machine().driver_data<nes_state>();
5206	5146	LOG_MMC(("gouder_sf4_l_r, offset: %04x\n", offset));
5207	5147
5208	5148	if (!(offset < 0x1700))
5209		return state->m_mmc_reg[offset & 0x03];
	5149	return m_mmc_reg[offset & 0x03];
5210	5150
5211	5151	return 0x00;
5212	5152	}
r18063	r18064
5234	5174
5235	5175	*************************************************************/
5236	5176
5237		static WRITE8_HANDLER( henggedianzi_w )
	5177	WRITE8_MEMBER(nes_state::henggedianzi_w)
5238	5178	{
5239	5179	LOG_MMC(("henggedianzi_w, offset: %04x, data: %02x\n", offset, data));
5240	5180
5241		prg32(space.machine(), data);
5242		set_nt_mirroring(space.machine(), BIT(data, 5) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	5181	prg32(machine(), data);
	5182	set_nt_mirroring(machine(), BIT(data, 5) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
5243	5183	}
5244	5184
5245	5185	/*************************************************************
r18063	r18064
5257	5197
5258	5198	*************************************************************/
5259	5199
5260		static WRITE8_HANDLER( heng_xjzb_l_w )
	5200	WRITE8_MEMBER(nes_state::heng_xjzb_l_w)
5261	5201	{
5262	5202	LOG_MMC(("heng_xjzb_l_w, offset: %04x, data: %02x\n", offset, data));
5263	5203	offset += 0x4100;
5264	5204
5265	5205	if (offset & 0x5000)
5266		prg32(space.machine(), data >> 1);
	5206	prg32(machine(), data >> 1);
5267	5207	}
5268	5208
5269		static WRITE8_HANDLER( heng_xjzb_w )
	5209	WRITE8_MEMBER(nes_state::heng_xjzb_w)
5270	5210	{
5271	5211	LOG_MMC(("heng_xjzb_w, offset: %04x, data: %02x\n", offset, data));
5272	5212
5273		set_nt_mirroring(space.machine(), BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	5213	set_nt_mirroring(machine(), BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
5274	5214	}
5275	5215
5276	5216	/*************************************************************
r18063	r18064
5289	5229
5290	5230	*************************************************************/
5291	5231
5292		static WRITE8_HANDLER( hes6in1_l_w )
	5232	WRITE8_MEMBER(nes_state::hes6in1_l_w)
5293	5233	{
5294	5234	LOG_MMC(("hes6in1_l_w, offset: %04x, data: %02x\n", offset, data));
5295	5235
5296	5236	if (!(offset & 0x100))
5297	5237	{
5298		prg32(space.machine(), (data & 0x38) >> 3);
5299		chr8(space.machine(), (data & 0x07) | ((data & 0x40) >> 3), CHRROM);
5300		set_nt_mirroring(space.machine(), BIT(data, 7) ? PPU_MIRROR_VERT : PPU_MIRROR_HORZ);
	5238	prg32(machine(), (data & 0x38) >> 3);
	5239	chr8(machine(), (data & 0x07) | ((data & 0x40) >> 3), CHRROM);
	5240	set_nt_mirroring(machine(), BIT(data, 7) ? PPU_MIRROR_VERT : PPU_MIRROR_HORZ);
5301	5241	}
5302	5242	}
5303	5243
5304		static WRITE8_HANDLER( hes_l_w )
	5244	WRITE8_MEMBER(nes_state::hes_l_w)
5305	5245	{
5306	5246	LOG_MMC(("hes_l_w, offset: %04x, data: %02x\n", offset, data));
5307	5247
5308	5248	if (!(offset & 0x100))
5309	5249	{
5310		prg32(space.machine(), (data & 0x38) >> 3);
5311		chr8(space.machine(), (data & 0x07) | ((data & 0x40) >> 3), CHRROM);
	5250	prg32(machine(), (data & 0x38) >> 3);
	5251	chr8(machine(), (data & 0x07) | ((data & 0x40) >> 3), CHRROM);
5312	5252	}
5313	5253	}
5314	5254
r18063	r18064
5324	5264
5325	5265	*************************************************************/
5326	5266
5327		static WRITE8_HANDLER( hosenkan_w )
	5267	WRITE8_MEMBER(nes_state::hosenkan_w)
5328	5268	{
5329		nes_state *state = space.machine().driver_data<nes_state>();
5330	5269	LOG_MMC(("hosenkan_w, offset: %04x, data: %02x\n", offset, data));
5331	5270
5332	5271	switch (offset & 0x7003)
5333	5272	{
5334	5273	case 0x0001:
5335		set_nt_mirroring(space.machine(), BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	5274	set_nt_mirroring(machine(), BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
5336	5275	break;
5337	5276	case 0x2000:
5338		state->m_mmc_latch1 = data;
	5277	m_mmc_latch1 = data;
5339	5278	break;
5340	5279	case 0x4000:
5341		switch (state->m_mmc_latch1)
	5280	switch (m_mmc_latch1)
5342	5281	{
5343	5282	case 0:
5344		chr2_0(space.machine(), data >> 1, CHRROM);
	5283	chr2_0(machine(), data >> 1, CHRROM);
5345	5284	break;
5346	5285	case 1:
5347		chr1_5(space.machine(), data, CHRROM);
	5286	chr1_5(machine(), data, CHRROM);
5348	5287	break;
5349	5288	case 2:
5350		chr2_2(space.machine(), data >> 1, CHRROM);
	5289	chr2_2(machine(), data >> 1, CHRROM);
5351	5290	break;
5352	5291	case 3:
5353		chr1_7(space.machine(), data, CHRROM);
	5292	chr1_7(machine(), data, CHRROM);
5354	5293	break;
5355	5294	case 4:
5356		prg8_89(space.machine(), data);
	5295	prg8_89(machine(), data);
5357	5296	break;
5358	5297	case 5:
5359		prg8_ab(space.machine(), data);
	5298	prg8_ab(machine(), data);
5360	5299	break;
5361	5300	case 6:
5362		chr1_4(space.machine(), data, CHRROM);
	5301	chr1_4(machine(), data, CHRROM);
5363	5302	break;
5364	5303	case 7:
5365		chr1_6(space.machine(), data, CHRROM);
	5304	chr1_6(machine(), data, CHRROM);
5366	5305	break;
5367	5306	}
5368	5307	break;
5369	5308	case 0x6003:
5370	5309	if (data)
5371	5310	{
5372		state->m_IRQ_count = data;
5373		state->m_IRQ_enable = 1;
	5311	m_IRQ_count = data;
	5312	m_IRQ_enable = 1;
5374	5313	}
5375	5314	else
5376		state->m_IRQ_enable = 0;
	5315	m_IRQ_enable = 0;
5377	5316	break;
5378	5317	}
5379	5318	}
r18063	r18064
5394	5333
5395	5334	*************************************************************/
5396	5335
5397		static WRITE8_HANDLER( ks7058_w )
	5336	WRITE8_MEMBER(nes_state::ks7058_w)
5398	5337	{
5399	5338	LOG_MMC(("ks7058_w, offset: %04x, data: %02x\n", offset, data));
5400	5339
5401	5340	switch (offset & 0x7080)
5402	5341	{
5403	5342	case 0x7000:
5404		chr4_0(space.machine(), data, CHRROM);
	5343	chr4_0(machine(), data, CHRROM);
5405	5344	break;
5406	5345	case 0x7080:
5407		chr4_4(space.machine(), data, CHRROM);
	5346	chr4_4(machine(), data, CHRROM);
5408	5347	break;
5409	5348	}
5410	5349	}
r18063	r18064
5421	5360
5422	5361	*************************************************************/
5423	5362
5424		static WRITE8_HANDLER( ks7022_w )
	5363	WRITE8_MEMBER(nes_state::ks7022_w)
5425	5364	{
5426		nes_state *state = space.machine().driver_data<nes_state>();
5427	5365	LOG_MMC(("ks7022_w, offset: %04x, data: %02x\n", offset, data));
5428	5366
5429	5367	if (offset == 0)
5430		set_nt_mirroring(space.machine(), BIT(data, 2) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	5368	set_nt_mirroring(machine(), BIT(data, 2) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
5431	5369
5432	5370	if (offset == 0x2000)
5433		state->m_mmc_latch1 = data & 0x0f;
	5371	m_mmc_latch1 = data & 0x0f;
5434	5372	}
5435	5373
5436		static READ8_HANDLER( ks7022_r )
	5374	READ8_MEMBER(nes_state::ks7022_r)
5437	5375	{
5438		nes_state *state = space.machine().driver_data<nes_state>();
5439	5376	LOG_MMC(("ks7022_r, offset: %04x\n", offset));
5440	5377
5441	5378	if (offset == 0x7ffc)
5442	5379	{
5443		chr8(space.machine(), state->m_mmc_latch1, CHRROM);
5444		prg16_89ab(space.machine(), state->m_mmc_latch1);
5445		prg16_cdef(space.machine(), state->m_mmc_latch1);
	5380	chr8(machine(), m_mmc_latch1, CHRROM);
	5381	prg16_89ab(machine(), m_mmc_latch1);
	5382	prg16_cdef(machine(), m_mmc_latch1);
5446	5383	}
5447	5384
5448		return mmc_hi_access_rom(space.machine(), offset);
	5385	return mmc_hi_access_rom(machine(), offset);
5449	5386	}
5450	5387
5451	5388	/*************************************************************
r18063	r18064
5487	5424	}
5488	5425	}
5489	5426
5490		static WRITE8_HANDLER( ks7032_w )
	5427	WRITE8_MEMBER(nes_state::ks7032_w)
5491	5428	{
5492		nes_state *state = space.machine().driver_data<nes_state>();
5493	5429	LOG_MMC(("ks7032_w, offset: %04x, data: %02x\n", offset, data));
5494	5430
5495	5431	switch (offset & 0x7000)
5496	5432	{
5497	5433	case 0x0000:
5498		state->m_IRQ_count = (state->m_IRQ_count & 0xfff0) | (data & 0x0f);
	5434	m_IRQ_count = (m_IRQ_count & 0xfff0) | (data & 0x0f);
5499	5435	break;
5500	5436	case 0x1000:
5501		state->m_IRQ_count = (state->m_IRQ_count & 0xff0f) | ((data & 0x0f) << 4);
	5437	m_IRQ_count = (m_IRQ_count & 0xff0f) | ((data & 0x0f) << 4);
5502	5438	break;
5503	5439	case 0x2000:
5504		state->m_IRQ_count = (state->m_IRQ_count & 0xf0ff) | ((data & 0x0f) << 8);
	5440	m_IRQ_count = (m_IRQ_count & 0xf0ff) | ((data & 0x0f) << 8);
5505	5441	break;
5506	5442	case 0x3000:
5507		state->m_IRQ_count = (state->m_IRQ_count & 0x0fff) | ((data & 0x0f) << 12);
	5443	m_IRQ_count = (m_IRQ_count & 0x0fff) | ((data & 0x0f) << 12);
5508	5444	break;
5509	5445	case 0x4000:
5510		state->m_IRQ_enable = 1;
	5446	m_IRQ_enable = 1;
5511	5447	break;
5512	5448	case 0x6000:
5513		state->m_mmc_latch1 = data & 0x07;
	5449	m_mmc_latch1 = data & 0x07;
5514	5450	break;
5515	5451	case 0x7000:
5516		state->m_mmc_reg[state->m_mmc_latch1] = data;
5517		ks7032_prg_update(space.machine());
	5452	m_mmc_reg[m_mmc_latch1] = data;
	5453	ks7032_prg_update(machine());
5518	5454	break;
5519	5455	}
5520	5456	}
r18063	r18064
5532	5468	*************************************************************/
5533	5469
5534	5470
5535		static WRITE8_HANDLER( ks202_w )
	5471	WRITE8_MEMBER(nes_state::ks202_w)
5536	5472	{
5537		nes_state *state = space.machine().driver_data<nes_state>();
5538	5473	LOG_MMC(("ks202_w, offset: %04x, data: %02x\n", offset, data));
5539	5474
5540	5475	switch (offset & 0x7000)
5541	5476	{
5542	5477	case 0x0000:
5543		state->m_IRQ_count = (state->m_IRQ_count & 0xfff0) | (data & 0x0f);
	5478	m_IRQ_count = (m_IRQ_count & 0xfff0) | (data & 0x0f);
5544	5479	break;
5545	5480	case 0x1000:
5546		state->m_IRQ_count = (state->m_IRQ_count & 0xff0f) | ((data & 0x0f) << 4);
	5481	m_IRQ_count = (m_IRQ_count & 0xff0f) | ((data & 0x0f) << 4);
5547	5482	break;
5548	5483	case 0x2000:
5549		state->m_IRQ_count = (state->m_IRQ_count & 0xf0ff) | ((data & 0x0f) << 8);
	5484	m_IRQ_count = (m_IRQ_count & 0xf0ff) | ((data & 0x0f) << 8);
5550	5485	break;
5551	5486	case 0x3000:
5552		state->m_IRQ_count = (state->m_IRQ_count & 0x0fff) | ((data & 0x0f) << 12);
	5487	m_IRQ_count = (m_IRQ_count & 0x0fff) | ((data & 0x0f) << 12);
5553	5488	break;
5554	5489	case 0x4000:
5555		state->m_IRQ_enable = 1;
	5490	m_IRQ_enable = 1;
5556	5491	break;
5557	5492	case 0x6000:
5558		state->m_mmc_latch1 = data & 0x07;
	5493	m_mmc_latch1 = data & 0x07;
5559	5494	break;
5560	5495	case 0x7000:
5561		state->m_mmc_reg[state->m_mmc_latch1] = data;
5562		ks7032_prg_update(space.machine());
	5496	m_mmc_reg[m_mmc_latch1] = data;
	5497	ks7032_prg_update(machine());
5563	5498	switch (offset & 0xc00)
5564	5499	{
5565	5500	case 0x800:
5566		set_nt_mirroring(space.machine(), BIT(data, 0) ? PPU_MIRROR_VERT : PPU_MIRROR_HORZ);
	5501	set_nt_mirroring(machine(), BIT(data, 0) ? PPU_MIRROR_VERT : PPU_MIRROR_HORZ);
5567	5502	break;
5568	5503	case 0xc00:
5569		chr1_x(space.machine(), offset & 0x07, data, CHRROM);
	5504	chr1_x(machine(), offset & 0x07, data, CHRROM);
5570	5505	break;
5571	5506	}
5572	5507	break;
r18063	r18064
5602	5537	}
5603	5538	}
5604	5539
5605		static WRITE8_HANDLER( ks7017_l_w )
	5540	WRITE8_MEMBER(nes_state::ks7017_l_w)
5606	5541	{
5607		nes_state *state = space.machine().driver_data<nes_state>();
5608	5542	LOG_MMC(("ks7022_w, offset: %04x, data: %02x\n", offset, data));
5609	5543
5610	5544	offset += 0x100;
5611	5545
5612	5546	if (offset >= 0xa00 && offset < 0xb00)
5613		state->m_mmc_latch1 = ((offset >> 2) & 0x03) | ((offset >> 4) & 0x04);
	5547	m_mmc_latch1 = ((offset >> 2) & 0x03) | ((offset >> 4) & 0x04);
5614	5548
5615	5549	if (offset >= 0x1000 && offset < 0x1100)
5616		prg16_89ab(space.machine(), state->m_mmc_latch1);
	5550	prg16_89ab(machine(), m_mmc_latch1);
5617	5551	}
5618	5552
5619		WRITE8_HANDLER( ks7017_extra_w )
	5553	WRITE8_MEMBER(nes_state::ks7017_extra_w)
5620	5554	{
5621		nes_state *state = space.machine().driver_data<nes_state>();
5622	5555	LOG_MMC(("ks7017_extra_w, offset: %04x, data: %02x\n", offset, data));
5623	5556
5624	5557	offset += 0x20;
5625	5558
5626	5559	if (offset == 0x0020) /* 0x4020 */
5627		state->m_IRQ_count = (state->m_IRQ_count & 0xff00) | data;
	5560	m_IRQ_count = (m_IRQ_count & 0xff00) | data;
5628	5561
5629	5562	if (offset == 0x0021) /* 0x4021 */
5630		state->m_IRQ_count = (state->m_IRQ_count & 0x00ff) | (data << 8);
	5563	m_IRQ_count = (m_IRQ_count & 0x00ff) | (data << 8);
5631	5564
5632	5565	if (offset == 0x0025) /* 0x4025 */
5633		set_nt_mirroring(space.machine(), BIT(data, 3) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	5566	set_nt_mirroring(machine(), BIT(data, 3) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
5634	5567	}
5635	5568
5636		READ8_HANDLER( ks7017_extra_r )
	5569	READ8_MEMBER(nes_state::ks7017_extra_r)
5637	5570	{
5638		nes_state *state = space.machine().driver_data<nes_state>();
5639	5571	LOG_MMC(("ks7017_extra_r, offset: %04x\n", offset));
5640	5572
5641		state->m_IRQ_status &= ~0x01;
5642		return state->m_IRQ_status;
	5573	m_IRQ_status &= ~0x01;
	5574	return m_IRQ_status;
5643	5575	}
5644	5576
5645	5577	/*************************************************************
r18063	r18064
5657	5589
5658	5590	*************************************************************/
5659	5591
5660		static WRITE8_HANDLER( kay_pp_l_w )
	5592	WRITE8_MEMBER(nes_state::kay_pp_l_w)
5661	5593	{
5662		nes_state *state = space.machine().driver_data<nes_state>();
5663	5594	LOG_MMC(("kay_pp_l_w, offset: %04x, data: %02x\n", offset, data));
5664	5595	offset += 0x100;
5665	5596
r18063	r18064
5669	5600	{
5670	5601	case 0x00:
5671	5602	case 0x01:
5672		state->m_mmc_reg[0] = 0x83;
	5603	m_mmc_reg[0] = 0x83;
5673	5604	break;
5674	5605	case 0x02:
5675		state->m_mmc_reg[0] = 0x42;
	5606	m_mmc_reg[0] = 0x42;
5676	5607	break;
5677	5608	case 0x03:
5678		state->m_mmc_reg[0] = 0x00;
	5609	m_mmc_reg[0] = 0x00;
5679	5610	break;
5680	5611	}
5681	5612	}
5682	5613	}
5683	5614
5684		static READ8_HANDLER( kay_pp_l_r )
	5615	READ8_MEMBER(nes_state::kay_pp_l_r)
5685	5616	{
5686		nes_state *state = space.machine().driver_data<nes_state>();
5687	5617	LOG_MMC(("kay_pp_l_r, offset: %04x\n", offset));
5688	5618	offset += 0x100;
5689	5619
5690	5620	if (offset >= 0x1000)
5691		return state->m_mmc_reg[0];
	5621	return m_mmc_reg[0];
5692	5622	else
5693	5623	return 0xff;
5694	5624	}
r18063	r18064
5761	5691	chr1_x(machine, start, bank, source);
5762	5692	}
5763	5693
5764		static WRITE8_HANDLER( kay_pp_w )
	5694	WRITE8_MEMBER(nes_state::kay_pp_w)
5765	5695	{
5766		nes_state *state = space.machine().driver_data<nes_state>();
5767	5696	LOG_MMC(("kay_pp_w, offset: %04x, data: %02x\n", offset, data));
5768	5697
5769	5698	switch (offset & 0x6003)
5770	5699	{
5771	5700	case 0x0000:
5772	5701	txrom_w(space, offset, data, mem_mask);
5773		mmc3_set_prg(space.machine(), state->m_mmc_prg_base, state->m_mmc_prg_mask);
	5702	mmc3_set_prg(machine(), m_mmc_prg_base, m_mmc_prg_mask);
5774	5703	break;
5775	5704
5776	5705	case 0x0001:
5777		state->m_mmc_reg[6] = (BIT(data, 0) << 5) | (BIT(data, 1) << 4) | (BIT(data, 2) << 3)
	5706	m_mmc_reg[6] = (BIT(data, 0) << 5) | (BIT(data, 1) << 4) | (BIT(data, 2) << 3)
5778	5707	| (BIT(data, 3) << 2) | (BIT(data, 4) << 1) | BIT(data, 5);
5779		if (!state->m_mmc_reg[7])
5780		kay_pp_update_regs(space.machine());
	5708	if (!m_mmc_reg[7])
	5709	kay_pp_update_regs(machine());
5781	5710	txrom_w(space, offset, data, mem_mask);
5782		mmc3_set_prg(space.machine(), state->m_mmc_prg_base, state->m_mmc_prg_mask);
	5711	mmc3_set_prg(machine(), m_mmc_prg_base, m_mmc_prg_mask);
5783	5712	break;
5784	5713
5785	5714	case 0x0003:
5786		state->m_mmc_reg[5] = data;
5787		kay_pp_update_regs(space.machine());
	5715	m_mmc_reg[5] = data;
	5716	kay_pp_update_regs(machine());
5788	5717	txrom_w(space, 0x0000, data, mem_mask);
5789		mmc3_set_prg(space.machine(), state->m_mmc_prg_base, state->m_mmc_prg_mask);
	5718	mmc3_set_prg(machine(), m_mmc_prg_base, m_mmc_prg_mask);
5790	5719	break;
5791	5720
5792	5721	default:
r18063	r18064
5819	5748	prg8_x(machine, start, bank);
5820	5749	}
5821	5750
5822		static WRITE8_HANDLER( kasing_m_w )
	5751	WRITE8_MEMBER(nes_state::kasing_m_w)
5823	5752	{
5824		nes_state *state = space.machine().driver_data<nes_state>();
5825	5753	LOG_MMC(("kasing_m_w, offset: %04x, data: %02x\n", offset, data));
5826	5754
5827	5755	switch (offset & 0x01)
5828	5756	{
5829	5757	case 0x00:
5830		state->m_mmc_reg[0] = data;
5831		mmc3_set_prg(space.machine(), state->m_mmc_prg_base, state->m_mmc_prg_mask);
	5758	m_mmc_reg[0] = data;
	5759	mmc3_set_prg(machine(), m_mmc_prg_base, m_mmc_prg_mask);
5832	5760	break;
5833	5761	case 0x01:
5834		state->m_mmc_chr_base = (data & 0x01) ? 0x100 : 0x000;
5835		mmc3_set_chr(space.machine(), state->m_mmc_chr_source, state->m_mmc_chr_base, state->m_mmc_chr_mask);
	5762	m_mmc_chr_base = (data & 0x01) ? 0x100 : 0x000;
	5763	mmc3_set_chr(machine(), m_mmc_chr_source, m_mmc_chr_base, m_mmc_chr_mask);
5836	5764	break;
5837	5765	}
5838	5766	}
r18063	r18064
5852	5780
5853	5781	*************************************************************/
5854	5782
5855		static WRITE8_HANDLER( magics_md_w )
	5783	WRITE8_MEMBER(nes_state::magics_md_w)
5856	5784	{
5857	5785	LOG_MMC(("magics_md_w, offset: %04x, data: %02x\n", offset, data));
5858	5786
5859		prg32(space.machine(), data >> 1);
5860		chr8(space.machine(), data, CHRROM);
	5787	prg32(machine(), data >> 1);
	5788	chr8(machine(), data, CHRROM);
5861	5789	}
5862	5790
5863	5791	/*************************************************************
r18063	r18064
5893	5821
5894	5822	}
5895	5823
5896		static WRITE8_HANDLER( nanjing_l_w )
	5824	WRITE8_MEMBER(nes_state::nanjing_l_w)
5897	5825	{
5898		nes_state *state = space.machine().driver_data<nes_state>();
5899	5826	LOG_MMC(("nanjing_l_w, offset: %04x, data: %02x\n", offset, data));
5900	5827
5901	5828	offset += 0x100;
r18063	r18064
5906	5833	if (offset == 0x1100)   // 0x5100
5907	5834	{
5908	5835	if (data == 6)
5909		prg32(space.machine(), 3);
	5836	prg32(machine(), 3);
5910	5837	return;
5911	5838	}
5912	5839
5913	5840	if (offset == 0x1101)   // 0x5101
5914	5841	{
5915		UINT8 temp = state->m_mmc_count;
5916		state->m_mmc_count = data;
	5842	UINT8 temp = m_mmc_count;
	5843	m_mmc_count = data;
5917	5844
5918	5845	if (temp & !data)
5919		state->m_mmc_latch2 ^= 0xff;
	5846	m_mmc_latch2 ^= 0xff;
5920	5847	}
5921	5848
5922	5849	switch (offset & 0x300)
5923	5850	{
5924	5851	case 0x000:
5925	5852	case 0x200:
5926		state->m_mmc_reg[BIT(offset, 9)] = data;
5927		if (!BIT(state->m_mmc_reg[0], 7) && state->m_ppu->get_current_scanline() <= 127)
5928		chr8(space.machine(), 0, CHRRAM);
	5853	m_mmc_reg[BIT(offset, 9)] = data;
	5854	if (!BIT(m_mmc_reg[0], 7) && m_ppu->get_current_scanline() <= 127)
	5855	chr8(machine(), 0, CHRRAM);
5929	5856	break;
5930	5857	case 0x300:
5931		state->m_mmc_latch1 = data;
	5858	m_mmc_latch1 = data;
5932	5859	break;
5933	5860	}
5934	5861
5935		prg32(space.machine(), (state->m_mmc_reg[0] & 0x0f) | ((state->m_mmc_reg[1] & 0x0f) << 4));
	5862	prg32(machine(), (m_mmc_reg[0] & 0x0f) | ((m_mmc_reg[1] & 0x0f) << 4));
5936	5863	}
5937	5864
5938		static READ8_HANDLER( nanjing_l_r )
	5865	READ8_MEMBER(nes_state::nanjing_l_r)
5939	5866	{
5940		nes_state *state = space.machine().driver_data<nes_state>();
5941	5867	UINT8 value = 0;
5942	5868	LOG_MMC(("nanjing_l_r, offset: %04x\n", offset));
5943	5869
r18063	r18064
5949	5875	switch (offset & 0x700)
5950	5876	{
5951	5877	case 0x100:
5952		value = state->m_mmc_latch1;
	5878	value = m_mmc_latch1;
5953	5879	break;
5954	5880	case 0x500:
5955		value = state->m_mmc_latch2 & state->m_mmc_latch1;
	5881	value = m_mmc_latch2 & m_mmc_latch1;
5956	5882	break;
5957	5883	case 0x000:
5958	5884	case 0x200:
r18063	r18064
5981	5907
5982	5908	*************************************************************/
5983	5909
5984		static WRITE8_HANDLER( nitra_w )
	5910	WRITE8_MEMBER(nes_state::nitra_w)
5985	5911	{
5986	5912	LOG_MMC(("nitra_w, offset: %04x, data: %02x\n", offset, data));
5987	5913
r18063	r18064
6001	5927
6002	5928	*************************************************************/
6003	5929
6004		static WRITE8_HANDLER( ntdec_asder_w )
	5930	WRITE8_MEMBER(nes_state::ntdec_asder_w)
6005	5931	{
6006		nes_state *state = space.machine().driver_data<nes_state>();
6007	5932	LOG_MMC(("ntdec_asder_w, offset: %04x, data: %02x\n", offset, data));
6008	5933
6009	5934	switch (offset)
6010	5935	{
6011	5936	case 0x0000:
6012		state->m_mmc_latch1 = data & 0x07;
	5937	m_mmc_latch1 = data & 0x07;
6013	5938	break;
6014	5939	case 0x2000:
6015		switch (state->m_mmc_latch1)
	5940	switch (m_mmc_latch1)
6016	5941	{
6017	5942	case 0:
6018		prg8_89(space.machine(), data);
	5943	prg8_89(machine(), data);
6019	5944	break;
6020	5945	case 1:
6021		prg8_ab(space.machine(), data);
	5946	prg8_ab(machine(), data);
6022	5947	break;
6023	5948	case 2:
6024	5949	data &= 0xfe;
6025		chr1_0(space.machine(), data, CHRROM);
6026		chr1_1(space.machine(), data + 1, CHRROM);
	5950	chr1_0(machine(), data, CHRROM);
	5951	chr1_1(machine(), data + 1, CHRROM);
6027	5952	break;
6028	5953	case 3:
6029	5954	data &= 0xfe;
6030		chr1_2(space.machine(), data, CHRROM);
6031		chr1_3(space.machine(), data + 1, CHRROM);
	5955	chr1_2(machine(), data, CHRROM);
	5956	chr1_3(machine(), data + 1, CHRROM);
6032	5957	break;
6033	5958	case 4:
6034		chr1_4(space.machine(), data, CHRROM);
	5959	chr1_4(machine(), data, CHRROM);
6035	5960	break;
6036	5961	case 5:
6037		chr1_5(space.machine(), data, CHRROM);
	5962	chr1_5(machine(), data, CHRROM);
6038	5963	break;
6039	5964	case 6:
6040		chr1_6(space.machine(), data, CHRROM);
	5965	chr1_6(machine(), data, CHRROM);
6041	5966	break;
6042	5967	case 7:
6043		chr1_7(space.machine(), data, CHRROM);
	5968	chr1_7(machine(), data, CHRROM);
6044	5969	break;
6045	5970	}
6046	5971	break;
6047	5972	case 0x6000:
6048		set_nt_mirroring(space.machine(), BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	5973	set_nt_mirroring(machine(), BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
6049	5974	break;
6050	5975	}
6051	5976	}
r18063	r18064
6065	5990
6066	5991	*************************************************************/
6067	5992
6068		static WRITE8_HANDLER( ntdec_fh_m_w )
	5993	WRITE8_MEMBER(nes_state::ntdec_fh_m_w)
6069	5994	{
6070	5995	LOG_MMC(("ntdec_fh_m_w, offset: %04x, data: %02x\n", offset, data));
6071	5996
6072	5997	switch (offset & 0x03)
6073	5998	{
6074	5999	case 0:
6075		chr4_0(space.machine(), data >> 2, CHRROM);
	6000	chr4_0(machine(), data >> 2, CHRROM);
6076	6001	break;
6077	6002	case 1:
6078		chr2_4(space.machine(), data >> 1, CHRROM);
	6003	chr2_4(machine(), data >> 1, CHRROM);
6079	6004	break;
6080	6005	case 2:
6081		chr2_6(space.machine(), data >> 1 , CHRROM);
	6006	chr2_6(machine(), data >> 1 , CHRROM);
6082	6007	break;
6083	6008	case 3:
6084		prg8_89(space.machine(), data);
	6009	prg8_89(machine(), data);
6085	6010	break;
6086	6011	}
6087	6012	}
r18063	r18064
6101	6026
6102	6027	*************************************************************/
6103	6028
6104		static WRITE8_HANDLER( daou306_w )
	6029	WRITE8_MEMBER(nes_state::daou306_w)
6105	6030	{
6106		nes_state *state = space.machine().driver_data<nes_state>();
6107	6031	LOG_MMC(("daou306_w, offset: %04x, data: %02x\n", offset, data));
6108	6032	int reg = BIT(offset, 2) ? 8 : 0;
6109	6033
r18063	r18064
6111	6035	{
6112	6036	case 0x4000:
6113	6037	case 0x4004:
6114		state->m_mmc_reg[reg + 0] = data;
6115		chr1_0(space.machine(), state->m_mmc_reg[0] | (state->m_mmc_reg[8] << 8), CHRROM);
	6038	m_mmc_reg[reg + 0] = data;
	6039	chr1_0(machine(), m_mmc_reg[0] | (m_mmc_reg[8] << 8), CHRROM);
6116	6040	break;
6117	6041	case 0x4001:
6118	6042	case 0x4005:
6119		state->m_mmc_reg[reg + 1] = data;
6120		chr1_1(space.machine(), state->m_mmc_reg[1] | (state->m_mmc_reg[9] << 8), CHRROM);
	6043	m_mmc_reg[reg + 1] = data;
	6044	chr1_1(machine(), m_mmc_reg[1] | (m_mmc_reg[9] << 8), CHRROM);
6121	6045	break;
6122	6046	case 0x4002:
6123	6047	case 0x4006:
6124		state->m_mmc_reg[reg + 2] = data;
6125		chr1_2(space.machine(), state->m_mmc_reg[2] | (state->m_mmc_reg[10] << 8), CHRROM);
	6048	m_mmc_reg[reg + 2] = data;
	6049	chr1_2(machine(), m_mmc_reg[2] | (m_mmc_reg[10] << 8), CHRROM);
6126	6050	break;
6127	6051	case 0x4003:
6128	6052	case 0x4007:
6129		state->m_mmc_reg[reg + 3] = data;
6130		chr1_3(space.machine(), state->m_mmc_reg[3] | (state->m_mmc_reg[11] << 8), CHRROM);
	6053	m_mmc_reg[reg + 3] = data;
	6054	chr1_3(machine(), m_mmc_reg[3] | (m_mmc_reg[11] << 8), CHRROM);
6131	6055	break;
6132	6056	case 0x4008:
6133	6057	case 0x400c:
6134		state->m_mmc_reg[reg + 4] = data;
6135		chr1_4(space.machine(), state->m_mmc_reg[4] | (state->m_mmc_reg[12] << 8), CHRROM);
	6058	m_mmc_reg[reg + 4] = data;
	6059	chr1_4(machine(), m_mmc_reg[4] | (m_mmc_reg[12] << 8), CHRROM);
6136	6060	break;
6137	6061	case 0x4009:
6138	6062	case 0x400d:
6139		state->m_mmc_reg[reg + 5] = data;
6140		chr1_5(space.machine(), state->m_mmc_reg[5] | (state->m_mmc_reg[13] << 8), CHRROM);
	6063	m_mmc_reg[reg + 5] = data;
	6064	chr1_5(machine(), m_mmc_reg[5] | (m_mmc_reg[13] << 8), CHRROM);
6141	6065	break;
6142	6066	case 0x400a:
6143	6067	case 0x400e:
6144		state->m_mmc_reg[reg + 6] = data;
6145		chr1_6(space.machine(), state->m_mmc_reg[6] | (state->m_mmc_reg[14] << 8), CHRROM);
	6068	m_mmc_reg[reg + 6] = data;
	6069	chr1_6(machine(), m_mmc_reg[6] | (m_mmc_reg[14] << 8), CHRROM);
6146	6070	break;
6147	6071	case 0x400b:
6148	6072	case 0x400f:
6149		state->m_mmc_reg[reg + 7] = data;
6150		chr1_7(space.machine(), state->m_mmc_reg[7] | (state->m_mmc_reg[15] << 8), CHRROM);
	6073	m_mmc_reg[reg + 7] = data;
	6074	chr1_7(machine(), m_mmc_reg[7] | (m_mmc_reg[15] << 8), CHRROM);
6151	6075	break;
6152	6076	case 0x4010:
6153		prg16_89ab(space.machine(), data);
	6077	prg16_89ab(machine(), data);
6154	6078	break;
6155	6079	case 0x4014:
6156	6080	if (data & 1)
6157		set_nt_mirroring(space.machine(), PPU_MIRROR_HORZ);
	6081	set_nt_mirroring(machine(), PPU_MIRROR_HORZ);
6158	6082	else
6159		set_nt_mirroring(space.machine(), PPU_MIRROR_VERT);
	6083	set_nt_mirroring(machine(), PPU_MIRROR_VERT);
6160	6084	break;
6161	6085	}
6162	6086	}
r18063	r18064
6176	6100
6177	6101	*************************************************************/
6178	6102
6179		static WRITE8_HANDLER( gs2015_w )
	6103	WRITE8_MEMBER(nes_state::gs2015_w)
6180	6104	{
6181		nes_state *state = space.machine().driver_data<nes_state>();
6182	6105	LOG_MMC(("gs2015_w, offset: %04x, data: %02x\n", offset, data));
6183	6106
6184		prg32(space.machine(), offset);
6185		chr8(space.machine(), offset >> 1, state->m_mmc_chr_source);
	6107	prg32(machine(), offset);
	6108	chr8(machine(), offset >> 1, m_mmc_chr_source);
6186	6109	}
6187	6110
6188	6111	/*************************************************************
r18063	r18064
6203	6126
6204	6127	*************************************************************/
6205	6128
6206		static WRITE8_HANDLER( rcm_tf_w )
	6129	WRITE8_MEMBER(nes_state::rcm_tf_w)
6207	6130	{
6208	6131	LOG_MMC(("rcm_tf_w, offset: %04x, data: %02x\n", offset, data));
6209	6132
r18063	r18064
6211	6134	{
6212	6135	case 0x00:
6213	6136	case 0x30:
6214		prg32(space.machine(), offset & 0x0f);
	6137	prg32(machine(), offset & 0x0f);
6215	6138	break;
6216	6139	case 0x10:
6217	6140	case 0x20:
6218		prg16_89ab(space.machine(), ((offset & 0x0f) << 1) | ((offset & 0x20) >> 4));
6219		prg16_cdef(space.machine(), ((offset & 0x0f) << 1) | ((offset & 0x20) >> 4));
	6141	prg16_89ab(machine(), ((offset & 0x0f) << 1) | ((offset & 0x20) >> 4));
	6142	prg16_cdef(machine(), ((offset & 0x0f) << 1) | ((offset & 0x20) >> 4));
6220	6143	break;
6221	6144	}
6222		set_nt_mirroring(space.machine(), BIT(data, 7) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	6145	set_nt_mirroring(machine(), BIT(data, 7) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
6223	6146	}
6224	6147
6225	6148	/*************************************************************
r18063	r18064
6236	6159
6237	6160	*************************************************************/
6238	6161
6239		static WRITE8_HANDLER( rex_dbz_l_w )
	6162	WRITE8_MEMBER(nes_state::rex_dbz_l_w)
6240	6163	{
6241		nes_state *state = space.machine().driver_data<nes_state>();
6242	6164	LOG_MMC(("rex_dbz_l_w, offset: %04x, data: %02x\n", offset, data));
6243	6165
6244		state->m_mmc_reg[0] = data;
6245		mmc3_set_chr(space.machine(), state->m_mmc_chr_source, state->m_mmc_chr_base, state->m_mmc_chr_mask);
	6166	m_mmc_reg[0] = data;
	6167	mmc3_set_chr(machine(), m_mmc_chr_source, m_mmc_chr_base, m_mmc_chr_mask);
6246	6168	}
6247	6169
6248	6170	/* we would need to use this read handler in 0x6000-0x7fff as well */
6249		static READ8_HANDLER( rex_dbz_l_r )
	6171	READ8_MEMBER(nes_state::rex_dbz_l_r)
6250	6172	{
6251	6173	LOG_MMC(("rex_dbz_l_r, offset: %04x\n", offset));
6252	6174	return 0x01;
r18063	r18064
6328	6250	chr1_x(machine, chr_page ^ 7, chr_base2[7] | (bank[7] & chr_mask), chr);
6329	6251	}
6330	6252
6331		static WRITE8_HANDLER( rex_sl1632_w )
	6253	WRITE8_MEMBER(nes_state::rex_sl1632_w)
6332	6254	{
6333		nes_state *state = space.machine().driver_data<nes_state>();
6334	6255	UINT8 map14_helper1, map14_helper2, mmc_helper, cmd;
6335	6256	LOG_MMC(("rex_sl1632_w, offset: %04x, data: %02x\n", offset, data));
6336	6257
6337	6258	if (offset == 0x2131)
6338	6259	{
6339		state->m_mmc_reg[0] = data;
6340		rex_sl1632_set_prg(space.machine(), state->m_mmc_prg_base, state->m_mmc_prg_mask);
6341		rex_sl1632_set_chr(space.machine(), state->m_mmc_chr_source, state->m_mmc_chr_base, state->m_mmc_chr_mask);
	6260	m_mmc_reg[0] = data;
	6261	rex_sl1632_set_prg(machine(), m_mmc_prg_base, m_mmc_prg_mask);
	6262	rex_sl1632_set_chr(machine(), m_mmc_chr_source, m_mmc_chr_base, m_mmc_chr_mask);
6342	6263
6343		if (!(state->m_mmc_reg[0] & 0x02))
6344		set_nt_mirroring(space.machine(), BIT(state->m_mmc_reg[1], 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	6264	if (!(m_mmc_reg[0] & 0x02))
	6265	set_nt_mirroring(machine(), BIT(m_mmc_reg[1], 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
6345	6266	}
6346	6267
6347		if (state->m_mmc_reg[0] & 0x02)
	6268	if (m_mmc_reg[0] & 0x02)
6348	6269	{
6349	6270	switch (offset & 0x6001)
6350	6271	{
6351	6272	case 0x0000:
6352		mmc_helper = state->m_mmc3_latch ^ data;
6353		state->m_mmc3_latch = data;
	6273	mmc_helper = m_mmc3_latch ^ data;
	6274	m_mmc3_latch = data;
6354	6275
6355	6276	/* Has PRG Mode changed? */
6356	6277	if (mmc_helper & 0x40)
6357		rex_sl1632_set_prg(space.machine(), state->m_mmc_prg_base, state->m_mmc_prg_mask);
	6278	rex_sl1632_set_prg(machine(), m_mmc_prg_base, m_mmc_prg_mask);
6358	6279
6359	6280	/* Has CHR Mode changed? */
6360	6281	if (mmc_helper & 0x80)
6361		rex_sl1632_set_chr(space.machine(), state->m_mmc_chr_source, state->m_mmc_chr_base, state->m_mmc_chr_mask);
	6282	rex_sl1632_set_chr(machine(), m_mmc_chr_source, m_mmc_chr_base, m_mmc_chr_mask);
6362	6283	break;
6363	6284
6364	6285	case 0x0001:
6365		cmd = state->m_mmc3_latch & 0x07;
	6286	cmd = m_mmc3_latch & 0x07;
6366	6287	switch (cmd)
6367	6288	{
6368	6289	case 0: case 1:   // these have to be changed due to the different way rex_sl1632_set_chr works (it handles 1k banks)!
6369		state->m_mmc_vrom_bank[2 * cmd] = data;
6370		state->m_mmc_vrom_bank[2 * cmd + 1] = data;
6371		rex_sl1632_set_chr(space.machine(), state->m_mmc_chr_source, state->m_mmc_chr_base, state->m_mmc_chr_mask);
	6290	m_mmc_vrom_bank[2 * cmd] = data;
	6291	m_mmc_vrom_bank[2 * cmd + 1] = data;
	6292	rex_sl1632_set_chr(machine(), m_mmc_chr_source, m_mmc_chr_base, m_mmc_chr_mask);
6372	6293	break;
6373	6294	case 2: case 3: case 4: case 5:
6374		state->m_mmc_vrom_bank[cmd + 2] = data;
6375		rex_sl1632_set_chr(space.machine(), state->m_mmc_chr_source, state->m_mmc_chr_base, state->m_mmc_chr_mask);
	6295	m_mmc_vrom_bank[cmd + 2] = data;
	6296	rex_sl1632_set_chr(machine(), m_mmc_chr_source, m_mmc_chr_base, m_mmc_chr_mask);
6376	6297	break;
6377	6298	case 6:
6378	6299	case 7:
6379		state->m_mmc_prg_bank[cmd - 6] = data;
6380		rex_sl1632_set_prg(space.machine(), state->m_mmc_prg_base, state->m_mmc_prg_mask);
	6300	m_mmc_prg_bank[cmd - 6] = data;
	6301	rex_sl1632_set_prg(machine(), m_mmc_prg_base, m_mmc_prg_mask);
6381	6302	break;
6382	6303	}
6383	6304	break;
6384	6305
6385	6306	case 0x2000:
6386		set_nt_mirroring(space.machine(), BIT(state->m_mmc_reg[1], 0) ? PPU_MIRROR_VERT : PPU_MIRROR_HORZ);
	6307	set_nt_mirroring(machine(), BIT(m_mmc_reg[1], 0) ? PPU_MIRROR_VERT : PPU_MIRROR_HORZ);
6387	6308	break;
6388	6309
6389	6310	default:
r18063	r18064
6395	6316	{
6396	6317	map14_helper1 = (offset & 0x01) << 2;
6397	6318	offset = ((offset & 0x02) | (offset >> 10)) >> 1;
6398		map14_helper2 = ((offset + 2) & 0x07) + 4; // '+4' because first 4 state->m_mmc_extra_banks are for PRG!
6399		state->m_mmc_extra_bank[map14_helper2] = (state->m_mmc_extra_bank[map14_helper2] & (0xf0 >> map14_helper1)) | ((data & 0x0f) << map14_helper1);
6400		rex_sl1632_set_chr(space.machine(), state->m_mmc_chr_source, state->m_mmc_chr_base, state->m_mmc_chr_mask);
	6319	map14_helper2 = ((offset + 2) & 0x07) + 4; // '+4' because first 4 m_mmc_extra_banks are for PRG!
	6320	m_mmc_extra_bank[map14_helper2] = (m_mmc_extra_bank[map14_helper2] & (0xf0 >> map14_helper1)) | ((data & 0x0f) << map14_helper1);
	6321	rex_sl1632_set_chr(machine(), m_mmc_chr_source, m_mmc_chr_base, m_mmc_chr_mask);
6401	6322	}
6402	6323	else
6403	6324	{
r18063	r18064
6405	6326	{
6406	6327	case 0x0000:
6407	6328	case 0x2000:
6408		state->m_mmc_extra_bank[offset >> 13] = data;
6409		rex_sl1632_set_prg(space.machine(), state->m_mmc_prg_base, state->m_mmc_prg_mask);
	6329	m_mmc_extra_bank[offset >> 13] = data;
	6330	rex_sl1632_set_prg(machine(), m_mmc_prg_base, m_mmc_prg_mask);
6410	6331	break;
6411	6332
6412	6333	case 0x1000:
6413		state->m_mmc_reg[1] = data;
6414		set_nt_mirroring(space.machine(), BIT(state->m_mmc_reg[1], 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	6334	m_mmc_reg[1] = data;
	6335	set_nt_mirroring(machine(), BIT(m_mmc_reg[1], 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
6415	6336	break;
6416	6337	}
6417	6338	}
r18063	r18064
6429	6350
6430	6351	*************************************************************/
6431	6352
6432		static WRITE8_HANDLER( rumblestation_m_w )
	6353	WRITE8_MEMBER(nes_state::rumblestation_m_w)
6433	6354	{
6434		nes_state *state = space.machine().driver_data<nes_state>();
6435	6355	LOG_MMC(("rumblestation_m_w, offset: %04x, data: %02x\n", offset, data));
6436	6356
6437		state->m_mmc_prg_bank[0] = (state->m_mmc_prg_bank[0] & 0x01) | ((data & 0x0f) << 1);
6438		state->m_mmc_vrom_bank[0] = (state->m_mmc_vrom_bank[0] & 0x07) | ((data & 0xf0) >> 1);
6439		prg32(space.machine(), state->m_mmc_prg_bank[0]);
6440		chr8(space.machine(), state->m_mmc_vrom_bank[0], CHRROM);
	6357	m_mmc_prg_bank[0] = (m_mmc_prg_bank[0] & 0x01) | ((data & 0x0f) << 1);
	6358	m_mmc_vrom_bank[0] = (m_mmc_vrom_bank[0] & 0x07) | ((data & 0xf0) >> 1);
	6359	prg32(machine(), m_mmc_prg_bank[0]);
	6360	chr8(machine(), m_mmc_vrom_bank[0], CHRROM);
6441	6361	}
6442	6362
6443		static WRITE8_HANDLER( rumblestation_w )
	6363	WRITE8_MEMBER(nes_state::rumblestation_w)
6444	6364	{
6445		nes_state *state = space.machine().driver_data<nes_state>();
6446	6365	LOG_MMC(("rumblestation_w, offset: %04x, data: %02x\n", offset, data));
6447	6366
6448		state->m_mmc_prg_bank[0] = (state->m_mmc_prg_bank[0] & ~0x01) | (data & 0x01);
6449		state->m_mmc_vrom_bank[0] = (state->m_mmc_vrom_bank[0] & ~0x07) | ((data & 0x70) >> 4);
6450		prg32(space.machine(), state->m_mmc_prg_bank[0]);
6451		chr8(space.machine(), state->m_mmc_vrom_bank[0], CHRROM);
	6367	m_mmc_prg_bank[0] = (m_mmc_prg_bank[0] & ~0x01) | (data & 0x01);
	6368	m_mmc_vrom_bank[0] = (m_mmc_vrom_bank[0] & ~0x07) | ((data & 0x70) >> 4);
	6369	prg32(machine(), m_mmc_prg_bank[0]);
	6370	chr8(machine(), m_mmc_vrom_bank[0], CHRROM);
6452	6371	}
6453	6372
6454	6373	/*************************************************************
r18063	r18064
6485	6404	}
6486	6405	}
6487	6406
6488		static WRITE8_HANDLER( sachen_74x374_l_w )
	6407	WRITE8_MEMBER(nes_state::sachen_74x374_l_w)
6489	6408	{
6490		nes_state *state = space.machine().driver_data<nes_state>();
6491	6409	LOG_MMC(("sachen_74x374_l_w, offset: %04x, data: %02x\n", offset, data));
6492	6410
6493	6411	/* write happens only if we are at 0x4100 + k * 0x200, but 0x4100 is offset = 0 */
6494	6412	if (!(offset & 0x100))
6495	6413	{
6496	6414	if (!(offset & 0x01))
6497		state->m_mmc_latch1 = data & 0x07;
	6415	m_mmc_latch1 = data & 0x07;
6498	6416	else
6499	6417	{
6500		switch (state->m_mmc_latch1)
	6418	switch (m_mmc_latch1)
6501	6419	{
6502	6420	case 0x02:
6503		state->m_mmc_vrom_bank[0] = (state->m_mmc_vrom_bank[0] & ~0x08) | ((data << 3) & 0x08);
6504		chr8(space.machine(), state->m_mmc_vrom_bank[0], CHRROM);
6505		prg32(space.machine(), data & 0x01);
	6421	m_mmc_vrom_bank[0] = (m_mmc_vrom_bank[0] & ~0x08) | ((data << 3) & 0x08);
	6422	chr8(machine(), m_mmc_vrom_bank[0], CHRROM);
	6423	prg32(machine(), data & 0x01);
6506	6424	break;
6507	6425	case 0x04:
6508		state->m_mmc_vrom_bank[0] = (state->m_mmc_vrom_bank[0] & ~0x04) | ((data << 2) & 0x04);
6509		chr8(space.machine(), state->m_mmc_vrom_bank[0], CHRROM);
	6426	m_mmc_vrom_bank[0] = (m_mmc_vrom_bank[0] & ~0x04) | ((data << 2) & 0x04);
	6427	chr8(machine(), m_mmc_vrom_bank[0], CHRROM);
6510	6428	break;
6511	6429	case 0x05:
6512		prg32(space.machine(), data & 0x07);
	6430	prg32(machine(), data & 0x07);
6513	6431	break;
6514	6432	case 0x06:
6515		state->m_mmc_vrom_bank[0] = (state->m_mmc_vrom_bank[0] & ~0x03) | ((data << 0) & 0x03);
6516		chr8(space.machine(), state->m_mmc_vrom_bank[0], CHRROM);
	6433	m_mmc_vrom_bank[0] = (m_mmc_vrom_bank[0] & ~0x03) | ((data << 0) & 0x03);
	6434	chr8(machine(), m_mmc_vrom_bank[0], CHRROM);
6517	6435	break;
6518	6436	case 0x07:
6519		sachen_set_mirror(space.machine(), (data >> 1) & 0x03);
	6437	sachen_set_mirror(machine(), (data >> 1) & 0x03);
6520	6438	break;
6521	6439	default:
6522	6440	break;
r18063	r18064
6525	6443	}
6526	6444	}
6527	6445
6528		static READ8_HANDLER( sachen_74x374_l_r )
	6446	READ8_MEMBER(nes_state::sachen_74x374_l_r)
6529	6447	{
6530		nes_state *state = space.machine().driver_data<nes_state>();
6531	6448	LOG_MMC(("sachen_74x374_l_r, offset: %04x", offset));
6532	6449
6533	6450	/* read  happens only if we are at 0x4100 + k * 0x200, but 0x4100 is offset = 0 */
6534	6451	if (!(offset & 0x100))
6535		return (~state->m_mmc_latch1 & 0x3f) /* ^ dips*/;   // we would need to check the Dips here
	6452	return (~m_mmc_latch1 & 0x3f) /* ^ dips*/;   // we would need to check the Dips here
6536	6453	else
6537	6454	return 0;
6538	6455	}
6539	6456
6540		static WRITE8_HANDLER( sachen_74x374a_l_w )
	6457	WRITE8_MEMBER(nes_state::sachen_74x374a_l_w)
6541	6458	{
6542		nes_state *state = space.machine().driver_data<nes_state>();
6543	6459	LOG_MMC(("sachen_74x374a_l_w, offset: %04x, data: %02x\n", offset, data));
6544	6460
6545	6461	/* write happens only if we are at 0x4100 + k * 0x200, but 0x4100 is offset = 0 */
6546	6462	if (!(offset & 0x100))
6547	6463	{
6548	6464	if (!(offset & 0x01))
6549		state->m_mmc_latch1 = data;
	6465	m_mmc_latch1 = data;
6550	6466	else
6551	6467	{
6552		switch (state->m_mmc_latch1 & 0x07)
	6468	switch (m_mmc_latch1 & 0x07)
6553	6469	{
6554	6470	case 0x00:
6555		prg32(space.machine(), 0);
6556		chr8(space.machine(), 3, CHRROM);
	6471	prg32(machine(), 0);
	6472	chr8(machine(), 3, CHRROM);
6557	6473	break;
6558	6474	case 0x02:
6559		state->m_mmc_vrom_bank[0] = (state->m_mmc_vrom_bank[0] & ~0x08) | ((data << 3) & 0x08);
6560		chr8(space.machine(), state->m_mmc_vrom_bank[0], CHRROM);
	6475	m_mmc_vrom_bank[0] = (m_mmc_vrom_bank[0] & ~0x08) | ((data << 3) & 0x08);
	6476	chr8(machine(), m_mmc_vrom_bank[0], CHRROM);
6561	6477	break;
6562	6478	case 0x04:
6563		state->m_mmc_vrom_bank[0] = (state->m_mmc_vrom_bank[0] & ~0x01) | ((data << 0) & 0x01);
6564		chr8(space.machine(), state->m_mmc_vrom_bank[0], CHRROM);
	6479	m_mmc_vrom_bank[0] = (m_mmc_vrom_bank[0] & ~0x01) | ((data << 0) & 0x01);
	6480	chr8(machine(), m_mmc_vrom_bank[0], CHRROM);
6565	6481	break;
6566	6482	case 0x05:
6567		prg32(space.machine(), data & 0x01);
	6483	prg32(machine(), data & 0x01);
6568	6484	break;
6569	6485	case 0x06:
6570		state->m_mmc_vrom_bank[0] = (state->m_mmc_vrom_bank[0] & ~0x06) | ((data << 1) & 0x06);
6571		chr8(space.machine(), state->m_mmc_vrom_bank[0], CHRROM);
	6486	m_mmc_vrom_bank[0] = (m_mmc_vrom_bank[0] & ~0x06) | ((data << 1) & 0x06);
	6487	chr8(machine(), m_mmc_vrom_bank[0], CHRROM);
6572	6488	break;
6573	6489	case 0x07:
6574		sachen_set_mirror(space.machine(), BIT(data, 0));
	6490	sachen_set_mirror(machine(), BIT(data, 0));
6575	6491	break;
6576	6492	default:
6577	6493	break;
r18063	r18064
6644	6560	}
6645	6561	}
6646	6562
6647		static WRITE8_HANDLER( s8259_l_w )
	6563	WRITE8_MEMBER(nes_state::s8259_l_w)
6648	6564	{
6649		nes_state *state = space.machine().driver_data<nes_state>();
6650		LOG_MMC(("s8259_w, type: %d, offset: %04x, data: %02x\n", state->m_pcb_id, offset, data));
	6565	LOG_MMC(("s8259_w, type: %d, offset: %04x, data: %02x\n", m_pcb_id, offset, data));
6651	6566
6652		common_s8259_write_handler(space, offset, data, state->m_pcb_id);
	6567	common_s8259_write_handler(space, offset, data, m_pcb_id);
6653	6568	}
6654	6569
6655		static WRITE8_HANDLER( s8259_m_w )
	6570	WRITE8_MEMBER(nes_state::s8259_m_w)
6656	6571	{
6657		nes_state *state = space.machine().driver_data<nes_state>();
6658		LOG_MMC(("s8259_w, type: %d, offset: %04x, data: %02x\n", state->m_pcb_id, offset, data));
	6572	LOG_MMC(("s8259_w, type: %d, offset: %04x, data: %02x\n", m_pcb_id, offset, data));
6659	6573
6660		common_s8259_write_handler(space, (offset + 0x100) & 0xfff, data, state->m_pcb_id);
	6574	common_s8259_write_handler(space, (offset + 0x100) & 0xfff, data, m_pcb_id);
6661	6575	}
6662	6576
6663	6577
r18063	r18064
6673	6587
6674	6588	*************************************************************/
6675	6589
6676		static WRITE8_HANDLER( sa009_l_w )
	6590	WRITE8_MEMBER(nes_state::sa009_l_w)
6677	6591	{
6678		nes_state *state = space.machine().driver_data<nes_state>();
6679	6592	LOG_MMC(("sa009_l_w, offset: %04x, data: %02x\n", offset, data));
6680	6593
6681		chr8(space.machine(), data, state->m_mmc_chr_source);
	6594	chr8(machine(), data, m_mmc_chr_source);
6682	6595	}
6683	6596
6684	6597	/*************************************************************
r18063	r18064
6693	6606
6694	6607	*************************************************************/
6695	6608
6696		static WRITE8_HANDLER( sa0036_w )
	6609	WRITE8_MEMBER(nes_state::sa0036_w)
6697	6610	{
6698	6611	LOG_MMC(("sa0036_w, offset: %04x, data: %02x\n", offset, data));
6699	6612
6700		chr8(space.machine(), data >> 7, CHRROM);
	6613	chr8(machine(), data >> 7, CHRROM);
6701	6614	}
6702	6615
6703	6616	/*************************************************************
r18063	r18064
6712	6625
6713	6626	*************************************************************/
6714	6627
6715		static WRITE8_HANDLER( sa0037_w )
	6628	WRITE8_MEMBER(nes_state::sa0037_w)
6716	6629	{
6717	6630	LOG_MMC(("sa0037_w, offset: %04x, data: %02x\n", offset, data));
6718	6631
6719		prg32(space.machine(), data >> 3);
6720		chr8(space.machine(), data, CHRROM);
	6632	prg32(machine(), data >> 3);
	6633	chr8(machine(), data, CHRROM);
6721	6634	}
6722	6635
6723	6636	/*************************************************************
r18063	r18064
6732	6645
6733	6646	*************************************************************/
6734	6647
6735		static WRITE8_HANDLER( sa72007_l_w )
	6648	WRITE8_MEMBER(nes_state::sa72007_l_w)
6736	6649	{
6737	6650	LOG_MMC(("sa72007_l_w, offset: %04x, data: %02x\n", offset, data));
6738	6651
6739	6652	/* only if we are at 0x4100 + k * 0x200, but 0x4100 is offset = 0 */
6740	6653	if (!(offset & 0x100))
6741		chr8(space.machine(), data >> 7, CHRROM);
	6654	chr8(machine(), data >> 7, CHRROM);
6742	6655	}
6743	6656
6744	6657	/*************************************************************
r18063	r18064
6753	6666
6754	6667	*************************************************************/
6755	6668
6756		static WRITE8_HANDLER( sa72008_l_w )
	6669	WRITE8_MEMBER(nes_state::sa72008_l_w)
6757	6670	{
6758	6671	LOG_MMC(("sa72008_l_w, offset: %04x, data: %02x\n", offset, data));
6759	6672
6760		prg32(space.machine(), data >> 2);
6761		chr8(space.machine(), data, CHRROM);
	6673	prg32(machine(), data >> 2);
	6674	chr8(machine(), data, CHRROM);
6762	6675	}
6763	6676
6764	6677	/*************************************************************
r18063	r18064
6773	6686
6774	6687	*************************************************************/
6775	6688
6776		static READ8_HANDLER( tca01_l_r )
	6689	READ8_MEMBER(nes_state::tca01_l_r)
6777	6690	{
6778	6691	LOG_MMC(("tca01_l_r, offset: %04x\n", offset));
6779	6692
r18063	r18064
6796	6709
6797	6710	*************************************************************/
6798	6711
6799		static WRITE8_HANDLER( tcu01_l_w )
	6712	WRITE8_MEMBER(nes_state::tcu01_l_w)
6800	6713	{
6801	6714	LOG_MMC(("tcu01_l_w, offset: %04x, data: %02x\n", offset, data));
6802	6715
6803	6716	if ((offset & 0x103) == 0x002)
6804	6717	{
6805		prg32(space.machine(), ((data >> 6) & 0x02) | ((data >> 2) & 0x01));
6806		chr8(space.machine(), data >> 3, CHRROM);
	6718	prg32(machine(), ((data >> 6) & 0x02) | ((data >> 2) & 0x01));
	6719	chr8(machine(), data >> 3, CHRROM);
6807	6720	}
6808	6721	}
6809	6722
6810		static WRITE8_HANDLER( tcu01_m_w )
	6723	WRITE8_MEMBER(nes_state::tcu01_m_w)
6811	6724	{
6812	6725	LOG_MMC(("tcu01_m_w, offset: %04x, data: %02x\n", offset, data));
6813	6726
6814	6727	tcu01_l_w(space, (offset + 0x100) & 0xfff, data, mem_mask);
6815	6728	}
6816	6729
6817		static WRITE8_HANDLER( tcu01_w )
	6730	WRITE8_MEMBER(nes_state::tcu01_w)
6818	6731	{
6819	6732	LOG_MMC(("tcu01_w, offset: %04x, data: %02x\n", offset, data));
6820	6733
r18063	r18064
6833	6746
6834	6747	*************************************************************/
6835	6748
6836		static WRITE8_HANDLER( tcu02_l_w )
	6749	WRITE8_MEMBER(nes_state::tcu02_l_w)
6837	6750	{
6838		nes_state *state = space.machine().driver_data<nes_state>();
6839	6751	LOG_MMC(("tcu02_l_w, offset: %04x, data: %02x\n", offset, data));
6840	6752
6841	6753	if ((offset & 0x103) == 0x002)
6842	6754	{
6843		state->m_mmc_latch1 = (data & 0x30) | ((data + 3) & 0x0f);
6844		chr8(space.machine(), state->m_mmc_latch1, CHRROM);
	6755	m_mmc_latch1 = (data & 0x30) | ((data + 3) & 0x0f);
	6756	chr8(machine(), m_mmc_latch1, CHRROM);
6845	6757	}
6846	6758	}
6847	6759
6848		static READ8_HANDLER( tcu02_l_r )
	6760	READ8_MEMBER(nes_state::tcu02_l_r)
6849	6761	{
6850		nes_state *state = space.machine().driver_data<nes_state>();
6851	6762	LOG_MMC(("tcu02_l_r, offset: %04x\n", offset));
6852	6763
6853	6764	if ((offset & 0x103) == 0x000)
6854		return state->m_mmc_latch1 | 0x40;
	6765	return m_mmc_latch1 | 0x40;
6855	6766	else
6856	6767	return 0x00;
6857	6768	}
r18063	r18064
6865	6776
6866	6777	*************************************************************/
6867	6778
6868		static WRITE8_HANDLER( subor0_w )
	6779	WRITE8_MEMBER(nes_state::subor0_w)
6869	6780	{
6870		nes_state *state = space.machine().driver_data<nes_state>();
6871	6781	UINT8 subor_helper1, subor_helper2;
6872	6782	LOG_MMC(("subor0_w, offset: %04x, data: %02x\n", offset, data));
6873	6783
6874		state->m_subor_reg[(offset >> 13) & 0x03] = data;
6875		subor_helper1 = ((state->m_subor_reg[0] ^ state->m_subor_reg[1]) << 1) & 0x20;
6876		subor_helper2 = ((state->m_subor_reg[2] ^ state->m_subor_reg[3]) << 0) & 0x1f;
	6784	m_subor_reg[(offset >> 13) & 0x03] = data;
	6785	subor_helper1 = ((m_subor_reg[0] ^ m_subor_reg[1]) << 1) & 0x20;
	6786	subor_helper2 = ((m_subor_reg[2] ^ m_subor_reg[3]) << 0) & 0x1f;
6877	6787
6878		if (state->m_subor_reg[1] & 0x08)
	6788	if (m_subor_reg[1] & 0x08)
6879	6789	{
6880	6790	subor_helper1 += subor_helper2 & 0xfe;
6881	6791	subor_helper2 = subor_helper1;
6882	6792	subor_helper1 += 1;
6883	6793	}
6884		else if (state->m_subor_reg[1] & 0x04)
	6794	else if (m_subor_reg[1] & 0x04)
6885	6795	{
6886	6796	subor_helper2 += subor_helper1;
6887	6797	subor_helper1 = 0x1f;
r18063	r18064
6892	6802	subor_helper2 = 0x20;
6893	6803	}
6894	6804
6895		prg16_89ab(space.machine(), subor_helper1);
6896		prg16_cdef(space.machine(), subor_helper2);
	6805	prg16_89ab(machine(), subor_helper1);
	6806	prg16_cdef(machine(), subor_helper2);
6897	6807	}
6898	6808
6899	6809	/*************************************************************
r18063	r18064
6904	6814
6905	6815	*************************************************************/
6906	6816
6907		static WRITE8_HANDLER( subor1_w )
	6817	WRITE8_MEMBER(nes_state::subor1_w)
6908	6818	{
6909		nes_state *state = space.machine().driver_data<nes_state>();
6910	6819	UINT8 subor_helper1, subor_helper2;
6911	6820	LOG_MMC(("subor1_w, offset: %04x, data: %02x\n", offset, data));
6912	6821
6913		state->m_subor_reg[(offset >> 13) & 0x03] = data;
6914		subor_helper1 = ((state->m_subor_reg[0] ^ state->m_subor_reg[1]) << 1) & 0x20;
6915		subor_helper2 = ((state->m_subor_reg[2] ^ state->m_subor_reg[3]) << 0) & 0x1f;
	6822	m_subor_reg[(offset >> 13) & 0x03] = data;
	6823	subor_helper1 = ((m_subor_reg[0] ^ m_subor_reg[1]) << 1) & 0x20;
	6824	subor_helper2 = ((m_subor_reg[2] ^ m_subor_reg[3]) << 0) & 0x1f;
6916	6825
6917		if (state->m_subor_reg[1] & 0x08)
	6826	if (m_subor_reg[1] & 0x08)
6918	6827	{
6919	6828	subor_helper1 += subor_helper2 & 0xfe;
6920	6829	subor_helper2 = subor_helper1;
6921	6830	subor_helper2 += 1;
6922	6831	}
6923		else if (state->m_subor_reg[1] & 0x04)
	6832	else if (m_subor_reg[1] & 0x04)
6924	6833	{
6925	6834	subor_helper2 += subor_helper1;
6926	6835	subor_helper1 = 0x1f;
r18063	r18064
6931	6840	subor_helper2 = 0x07;
6932	6841	}
6933	6842
6934		prg16_89ab(space.machine(), subor_helper1);
6935		prg16_cdef(space.machine(), subor_helper2);
	6843	prg16_89ab(machine(), subor_helper1);
	6844	prg16_cdef(machine(), subor_helper2);
6936	6845	}
6937	6846
6938	6847	/*************************************************************
r18063	r18064
6988	6897	mmc3_set_prg(machine, state->m_mmc_prg_base, state->m_mmc_prg_mask);
6989	6898	}
6990	6899
6991		static WRITE8_HANDLER( sgame_boog_l_w )
	6900	WRITE8_MEMBER(nes_state::sgame_boog_l_w)
6992	6901	{
6993		nes_state *state = space.machine().driver_data<nes_state>();
6994	6902	LOG_MMC(("sgame_boog_l_w, offset: %04x, data: %02x\n", offset, data));
6995	6903	offset += 0x100;
6996	6904
6997	6905	if (offset == 0x1000)
6998	6906	{
6999		state->m_mmc_reg[0] = data;
7000		sgame_boog_set_prg(space.machine());
	6907	m_mmc_reg[0] = data;
	6908	sgame_boog_set_prg(machine());
7001	6909	}
7002	6910	else if (offset == 0x1001)
7003	6911	{
7004		state->m_mmc_reg[1] = data;
7005		mmc3_set_chr(space.machine(), state->m_mmc_chr_source, state->m_mmc_chr_base, state->m_mmc_chr_mask);
	6912	m_mmc_reg[1] = data;
	6913	mmc3_set_chr(machine(), m_mmc_chr_source, m_mmc_chr_base, m_mmc_chr_mask);
7006	6914	}
7007	6915	else if (offset == 0x1007)
7008	6916	{
7009		state->m_mmc3_latch = 0;
7010		state->m_mmc_reg[2] = data;
7011		sgame_boog_set_prg(space.machine());
7012		mmc3_set_chr(space.machine(), state->m_mmc_chr_source, state->m_mmc_chr_base, state->m_mmc_chr_mask);
	6917	m_mmc3_latch = 0;
	6918	m_mmc_reg[2] = data;
	6919	sgame_boog_set_prg(machine());
	6920	mmc3_set_chr(machine(), m_mmc_chr_source, m_mmc_chr_base, m_mmc_chr_mask);
7013	6921	}
7014	6922	}
7015	6923
7016		static WRITE8_HANDLER( sgame_boog_m_w )
	6924	WRITE8_MEMBER(nes_state::sgame_boog_m_w)
7017	6925	{
7018		nes_state *state = space.machine().driver_data<nes_state>();
7019	6926	LOG_MMC(("sgame_boog_m_w, offset: %04x, data: %02x\n", offset, data));
7020	6927
7021	6928	if (offset == 0x0000)
7022	6929	{
7023		state->m_mmc_reg[0] = data;
7024		sgame_boog_set_prg(space.machine());
	6930	m_mmc_reg[0] = data;
	6931	sgame_boog_set_prg(machine());
7025	6932	}
7026	6933	else if (offset == 0x0001)
7027	6934	{
7028		state->m_mmc_reg[1] = data;
7029		mmc3_set_chr(space.machine(), state->m_mmc_chr_source, state->m_mmc_chr_base, state->m_mmc_chr_mask);
	6935	m_mmc_reg[1] = data;
	6936	mmc3_set_chr(machine(), m_mmc_chr_source, m_mmc_chr_base, m_mmc_chr_mask);
7030	6937	}
7031	6938	else if (offset == 0x0007)
7032	6939	{
7033		state->m_mmc3_latch = 0;
7034		state->m_mmc_reg[2] = data;
7035		sgame_boog_set_prg(space.machine());
7036		mmc3_set_chr(space.machine(), state->m_mmc_chr_source, state->m_mmc_chr_base, state->m_mmc_chr_mask);
	6940	m_mmc3_latch = 0;
	6941	m_mmc_reg[2] = data;
	6942	sgame_boog_set_prg(machine());
	6943	mmc3_set_chr(machine(), m_mmc_chr_source, m_mmc_chr_base, m_mmc_chr_mask);
7037	6944	}
7038	6945	}
7039	6946
7040		static WRITE8_HANDLER( sgame_boog_w )
	6947	WRITE8_MEMBER(nes_state::sgame_boog_w)
7041	6948	{
7042		nes_state *state = space.machine().driver_data<nes_state>();
7043	6949	static const UINT8 conv_table[8] = {0,2,5,3,6,1,7,4};
7044	6950	LOG_MMC(("sgame_boog_w, offset: %04x, data: %02x\n", offset, data));
7045	6951
7046	6952	switch (offset & 0x6001)
7047	6953	{
7048	6954	case 0x0000:
7049		if (!state->m_mmc_reg[2])
	6955	if (!m_mmc_reg[2])
7050	6956	txrom_w(space, 0x0000, data, mem_mask);
7051	6957	break;
7052	6958
7053	6959	case 0x0001:
7054		if (!state->m_mmc_reg[2])
	6960	if (!m_mmc_reg[2])
7055	6961	txrom_w(space, 0x0001, data, mem_mask);
7056		else if (state->m_mmc_reg[3] && ((state->m_mmc_reg[0] & 0x80) == 0 || (state->m_mmc_latch1 & 0x07) < 6))   // if we use the prg16 banks and cmd=6,7 DON'T enter!
	6962	else if (m_mmc_reg[3] && ((m_mmc_reg[0] & 0x80) == 0 || (m_mmc_latch1 & 0x07) < 6))   // if we use the prg16 banks and cmd=6,7 DON'T enter!
7057	6963	{
7058		state->m_mmc_reg[3] = 0;
	6964	m_mmc_reg[3] = 0;
7059	6965	txrom_w(space, 0x0001, data, mem_mask);
7060	6966	}
7061	6967	break;
7062	6968
7063	6969	case 0x2000:
7064		if (!state->m_mmc_reg[2])
	6970	if (!m_mmc_reg[2])
7065	6971	txrom_w(space, 0x2000, data, mem_mask);
7066	6972	else
7067	6973	{
7068	6974	data = (data & 0xc0) | conv_table[data & 0x07];
7069		state->m_mmc_reg[3] = 1;
	6975	m_mmc_reg[3] = 1;
7070	6976	txrom_w(space, 0x0000, data, mem_mask);
7071	6977	break;
7072	6978	}
7073	6979	break;
7074	6980
7075	6981	case 0x4000:
7076		if (!state->m_mmc_reg[2])
	6982	if (!m_mmc_reg[2])
7077	6983	txrom_w(space, 0x4000, data, mem_mask);
7078	6984	else
7079		set_nt_mirroring(space.machine(), ((data >> 7) | data) & 0x01 ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	6985	set_nt_mirroring(machine(), ((data >> 7) | data) & 0x01 ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
7080	6986	break;
7081	6987
7082	6988	case 0x4001:
7083		if (!state->m_mmc_reg[2])
	6989	if (!m_mmc_reg[2])
7084	6990	txrom_w(space, 0x4001, data, mem_mask);
7085	6991	else
7086	6992	txrom_w(space, 0x6001, data, mem_mask);
7087	6993	break;
7088	6994
7089	6995	case 0x6001:
7090		if (!state->m_mmc_reg[2])
	6996	if (!m_mmc_reg[2])
7091	6997	txrom_w(space, 0x6001, data, mem_mask);
7092	6998	else
7093	6999	{
r18063	r18064
7116	7022
7117	7023	*************************************************************/
7118	7024
7119		static WRITE8_HANDLER( sgame_lion_m_w )
	7025	WRITE8_MEMBER(nes_state::sgame_lion_m_w)
7120	7026	{
7121		nes_state *state = space.machine().driver_data<nes_state>();
7122	7027	LOG_MMC(("sgame_lion_m_w, offset: %04x, data: %02x\n", offset, data));
7123	7028
7124		state->m_map114_reg = data;
	7029	m_map114_reg = data;
7125	7030
7126		if (state->m_map114_reg & 0x80)
	7031	if (m_map114_reg & 0x80)
7127	7032	{
7128		prg16_89ab(space.machine(), data & 0x1f);
7129		prg16_cdef(space.machine(), data & 0x1f);
	7033	prg16_89ab(machine(), data & 0x1f);
	7034	prg16_cdef(machine(), data & 0x1f);
7130	7035	}
7131	7036	else
7132		mmc3_set_prg(space.machine(), state->m_mmc_prg_base, state->m_mmc_prg_mask);
	7037	mmc3_set_prg(machine(), m_mmc_prg_base, m_mmc_prg_mask);
7133	7038
7134	7039	}
7135	7040
7136		static WRITE8_HANDLER( sgame_lion_w )
	7041	WRITE8_MEMBER(nes_state::sgame_lion_w)
7137	7042	{
7138		nes_state *state = space.machine().driver_data<nes_state>();
7139	7043	static const UINT8 conv_table[8] = {0, 3, 1, 5, 6, 7, 2, 4};
7140	7044	LOG_MMC(("sgame_lion_w, offset: %04x, data: %02x\n", offset, data));
7141	7045
r18063	r18064
7144	7048	switch (offset & 0x6000)
7145	7049	{
7146	7050	case 0x0000:
7147		set_nt_mirroring(space.machine(), BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	7051	set_nt_mirroring(machine(), BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
7148	7052	break;
7149	7053	case 0x2000:
7150		state->m_map114_reg_enabled = 1;
	7054	m_map114_reg_enabled = 1;
7151	7055	data = (data & 0xc0) | conv_table[data & 0x07];
7152	7056	txrom_w(space, 0x0000, data, mem_mask);
7153	7057	break;
7154	7058	case 0x4000:
7155		if (state->m_map114_reg_enabled && (state->m_map114_reg & 0x80) == 0)
	7059	if (m_map114_reg_enabled && (m_map114_reg & 0x80) == 0)
7156	7060	{
7157		state->m_map114_reg_enabled = 0;
	7061	m_map114_reg_enabled = 0;
7158	7062	txrom_w(space, 0x0001, data, mem_mask);
7159	7063	}
7160	7064	break;
r18063	r18064
7186	7090
7187	7091	*************************************************************/
7188	7092
7189		static WRITE8_HANDLER( tengen_800008_w )
	7093	WRITE8_MEMBER(nes_state::tengen_800008_w)
7190	7094	{
7191	7095	LOG_MMC(("tengen_800008_w, offset: %04x, data: %02x\n", offset, data));
7192	7096
7193		prg32(space.machine(), data >> 3);
7194		chr8(space.machine(), data, CHRROM);
	7097	prg32(machine(), data >> 3);
	7098	chr8(machine(), data, CHRROM);
7195	7099	}
7196	7100
7197	7101	/*************************************************************
r18063	r18064
7300	7204	chr1_x(machine, 7 ^ chr_page, state->m_mmc_vrom_bank[5], CHRROM);
7301	7205	}
7302	7206
7303		static WRITE8_HANDLER( tengen_800032_w )
	7207	WRITE8_MEMBER(nes_state::tengen_800032_w)
7304	7208	{
7305		nes_state *state = space.machine().driver_data<nes_state>();
7306	7209	UINT8 map64_helper, cmd;
7307	7210	LOG_MMC(("tengen_800032_w, offset: %04x, data: %02x\n", offset, data));
7308	7211
7309	7212	switch (offset & 0x6001)
7310	7213	{
7311	7214	case 0x0000:
7312		map64_helper = state->m_mmc_latch1 ^ data;
7313		state->m_mmc_latch1 = data;
	7215	map64_helper = m_mmc_latch1 ^ data;
	7216	m_mmc_latch1 = data;
7314	7217
7315	7218	/* Has PRG Mode changed? */
7316	7219	if (map64_helper & 0x40)
7317		tengen_800032_set_prg(space.machine());
	7220	tengen_800032_set_prg(machine());
7318	7221
7319	7222	/* Has CHR Mode changed? */
7320	7223	if (map64_helper & 0xa0)
7321		tengen_800032_set_chr(space.machine());
	7224	tengen_800032_set_chr(machine());
7322	7225	break;
7323	7226
7324	7227	case 0x0001:
7325		cmd = state->m_mmc_latch1 & 0x0f;
	7228	cmd = m_mmc_latch1 & 0x0f;
7326	7229	switch (cmd)
7327	7230	{
7328	7231	case 0: case 1:
7329	7232	case 2: case 3:
7330	7233	case 4: case 5:
7331		state->m_mmc_vrom_bank[cmd] = data;
7332		tengen_800032_set_chr(space.machine());
	7234	m_mmc_vrom_bank[cmd] = data;
	7235	tengen_800032_set_chr(machine());
7333	7236	break;
7334	7237	case 6: case 7:
7335		state->m_mmc_prg_bank[cmd - 6] = data;
7336		tengen_800032_set_prg(space.machine());
	7238	m_mmc_prg_bank[cmd - 6] = data;
	7239	tengen_800032_set_prg(machine());
7337	7240	break;
7338	7241	case 8: case 9:
7339		state->m_mmc_vrom_bank[cmd - 2] = data;
7340		tengen_800032_set_chr(space.machine());
	7242	m_mmc_vrom_bank[cmd - 2] = data;
	7243	tengen_800032_set_chr(machine());
7341	7244	break;
7342	7245	case 0x0f:
7343		state->m_mmc_prg_bank[2] = data;
7344		tengen_800032_set_prg(space.machine());
	7246	m_mmc_prg_bank[2] = data;
	7247	tengen_800032_set_prg(machine());
7345	7248	break;
7346	7249	}
7347	7250	break;
7348	7251
7349	7252	case 0x2000:
7350		set_nt_mirroring(space.machine(), BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	7253	set_nt_mirroring(machine(), BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
7351	7254	break;
7352	7255
7353	7256	case 0x4000:
7354		state->m_IRQ_count_latch = data;
	7257	m_IRQ_count_latch = data;
7355	7258	break;
7356	7259
7357	7260	case 0x4001: /* $c001 - IRQ scanline latch */
7358		state->m_IRQ_mode = data & 0x01;
7359		state->m_IRQ_reset = 1;
	7261	m_IRQ_mode = data & 0x01;
	7262	m_IRQ_reset = 1;
7360	7263	break;
7361	7264
7362	7265	case 0x6000:
7363		state->m_IRQ_enable = 0;
	7266	m_IRQ_enable = 0;
7364	7267	break;
7365	7268
7366	7269	case 0x6001:
7367		state->m_IRQ_enable = 1;
	7270	m_IRQ_enable = 1;
7368	7271	break;
7369	7272
7370	7273	default:
r18063	r18064
7397	7300	set_nt_page(machine, 3, ROM, state->m_mmc_vrom_bank[nt_mode ? 5 : 1], 0);
7398	7301	}
7399	7302
7400		static WRITE8_HANDLER( tengen_800037_w )
	7303	WRITE8_MEMBER(nes_state::tengen_800037_w)
7401	7304	{
7402		nes_state *state = space.machine().driver_data<nes_state>();
7403	7305	UINT8 map158_helper, cmd;
7404	7306	LOG_MMC(("tengen_800037_w, offset: %04x, data: %02x\n", offset, data));
7405	7307
7406	7308	switch (offset & 0x6001)
7407	7309	{
7408	7310	case 0x0000:
7409		map158_helper = state->m_mmc_latch1 ^ data;
7410		state->m_mmc_latch1 = data;
	7311	map158_helper = m_mmc_latch1 ^ data;
	7312	m_mmc_latch1 = data;
7411	7313
7412	7314	/* Has PRG Mode changed? */
7413	7315	if (map158_helper & 0x40)
7414		tengen_800032_set_prg(space.machine());
	7316	tengen_800032_set_prg(machine());
7415	7317
7416	7318	/* Has CHR Mode changed? */
7417	7319	if (map158_helper & 0xa0)
7418	7320	{
7419		tengen_800032_set_chr(space.machine());
7420		tengen_800037_set_mirror(space.machine());
	7321	tengen_800032_set_chr(machine());
	7322	tengen_800037_set_mirror(machine());
7421	7323	}
7422	7324	break;
7423	7325
7424	7326	case 0x0001:
7425		cmd = state->m_mmc_latch1 & 0x0f;
	7327	cmd = m_mmc_latch1 & 0x0f;
7426	7328	switch (cmd)
7427	7329	{
7428	7330	case 0: case 1:
7429	7331	case 2: case 3:
7430	7332	case 4: case 5:
7431		state->m_mmc_vrom_bank[cmd] = data;
7432		tengen_800032_set_chr(space.machine());
7433		tengen_800037_set_mirror(space.machine());
	7333	m_mmc_vrom_bank[cmd] = data;
	7334	tengen_800032_set_chr(machine());
	7335	tengen_800037_set_mirror(machine());
7434	7336	break;
7435	7337	case 6: case 7:
7436		state->m_mmc_prg_bank[cmd - 6] = data;
7437		tengen_800032_set_prg(space.machine());
	7338	m_mmc_prg_bank[cmd - 6] = data;
	7339	tengen_800032_set_prg(machine());
7438	7340	break;
7439	7341	case 8: case 9:
7440		state->m_mmc_vrom_bank[cmd - 2] = data;
7441		tengen_800032_set_chr(space.machine());
7442		tengen_800037_set_mirror(space.machine());
	7342	m_mmc_vrom_bank[cmd - 2] = data;
	7343	tengen_800032_set_chr(machine());
	7344	tengen_800037_set_mirror(machine());
7443	7345	break;
7444	7346	case 0x0f:
7445		state->m_mmc_prg_bank[2] = data;
7446		tengen_800032_set_prg(space.machine());
	7347	m_mmc_prg_bank[2] = data;
	7348	tengen_800032_set_prg(machine());
7447	7349	break;
7448	7350	}
7449	7351	break;
r18063	r18064
7473	7375
7474	7376	*************************************************************/
7475	7377
7476		static WRITE8_HANDLER( txc_22211_l_w )
	7378	WRITE8_MEMBER(nes_state::txc_22211_l_w)
7477	7379	{
7478		nes_state *state = space.machine().driver_data<nes_state>();
7479	7380	LOG_MMC(("txc_22211_l_w, offset: %04x, data: %02x\n", offset, data));
7480	7381
7481	7382	if (offset < 4)
7482		state->m_txc_reg[offset & 0x03] = data;
	7383	m_txc_reg[offset & 0x03] = data;
7483	7384	}
7484	7385
7485		static READ8_HANDLER( txc_22211_l_r )
	7386	READ8_MEMBER(nes_state::txc_22211_l_r)
7486	7387	{
7487		nes_state *state = space.machine().driver_data<nes_state>();
7488	7388	LOG_MMC(("txc_22211_l_r, offset: %04x\n", offset));
7489	7389
7490	7390	if (offset == 0x0000)
7491		return (state->m_txc_reg[1] ^ state->m_txc_reg[2]) | 0x40;
	7391	return (m_txc_reg[1] ^ m_txc_reg[2]) | 0x40;
7492	7392	else
7493	7393	return 0x00;
7494	7394	}
7495	7395
7496		static WRITE8_HANDLER( txc_22211_w )
	7396	WRITE8_MEMBER(nes_state::txc_22211_w)
7497	7397	{
7498		nes_state *state = space.machine().driver_data<nes_state>();
7499	7398	LOG_MMC(("txc_22211_w, offset: %04x, data: %02x\n", offset, data));
7500	7399
7501		prg32(space.machine(), state->m_txc_reg[2] >> 2);
7502		chr8(space.machine(), state->m_txc_reg[2], CHRROM);
	7400	prg32(machine(), m_txc_reg[2] >> 2);
	7401	chr8(machine(), m_txc_reg[2], CHRROM);
7503	7402	}
7504	7403
7505	7404	/*************************************************************
r18063	r18064
7517	7416
7518	7417	*************************************************************/
7519	7418
7520		static WRITE8_HANDLER( txc_22211b_w )
	7419	WRITE8_MEMBER(nes_state::txc_22211b_w)
7521	7420	{
7522		nes_state *state = space.machine().driver_data<nes_state>();
7523	7421	LOG_MMC(("txc_22211b_w, offset: %04x, data: %02x\n", offset, data));
7524	7422
7525		prg32(space.machine(), state->m_txc_reg[2] >> 2);
7526		chr8(space.machine(), (((data ^ state->m_txc_reg[2]) >> 3) & 0x02) | (((data ^ state->m_txc_reg[2]) >> 5) & 0x01), CHRROM);
	7423	prg32(machine(), m_txc_reg[2] >> 2);
	7424	chr8(machine(), (((data ^ m_txc_reg[2]) >> 3) & 0x02) | (((data ^ m_txc_reg[2]) >> 5) & 0x01), CHRROM);
7527	7425	}
7528	7426
7529	7427	/*************************************************************
r18063	r18064
7541	7439
7542	7440	*************************************************************/
7543	7441
7544		static READ8_HANDLER( txc_22211c_l_r )
	7442	READ8_MEMBER(nes_state::txc_22211c_l_r)
7545	7443	{
7546		nes_state *state = space.machine().driver_data<nes_state>();
7547	7444	LOG_MMC(("txc_22211c_l_r, offset: %04x\n", offset));
7548	7445
7549	7446	if (offset == 0x0000)
7550		return (state->m_txc_reg[1] ^ state->m_txc_reg[2]) | 0x41;
	7447	return (m_txc_reg[1] ^ m_txc_reg[2]) | 0x41;
7551	7448	else
7552	7449	return 0x00;
7553	7450	}
r18063	r18064
7566	7463
7567	7464	*************************************************************/
7568	7465
7569		static WRITE8_HANDLER( txc_tw_l_w )
	7466	WRITE8_MEMBER(nes_state::txc_tw_l_w)
7570	7467	{
7571	7468	LOG_MMC(("txctw_l_w, offset: %04x, data: %02x\n", offset, data));
7572	7469
7573		prg32(space.machine(), (data >> 4) | data);
	7470	prg32(machine(), (data >> 4) | data);
7574	7471	}
7575	7472
7576		static WRITE8_HANDLER( txc_tw_m_w )
	7473	WRITE8_MEMBER(nes_state::txc_tw_m_w)
7577	7474	{
7578	7475	LOG_MMC(("txctw_m_w, offset: %04x, data: %04x\n", offset, data));
7579	7476
r18063	r18064
7600	7497
7601	7498	*************************************************************/
7602	7499
7603		static WRITE8_HANDLER( txc_strikewolf_w )
	7500	WRITE8_MEMBER(nes_state::txc_strikewolf_w)
7604	7501	{
7605	7502	LOG_MMC(("txc_strikewolf_w, offset: %04x, data: %02x\n", offset, data));
7606	7503
7607	7504	if ((offset >= 0x400) && (offset < 0x7fff))
7608	7505	{
7609		prg32(space.machine(), data >> 4);
7610		chr8(space.machine(), data & 0x0f, CHRROM);
	7506	prg32(machine(), data >> 4);
	7507	chr8(machine(), data & 0x0f, CHRROM);
7611	7508	}
7612	7509	}
7613	7510
r18063	r18064
7627	7524
7628	7525	*************************************************************/
7629	7526
7630		static READ8_HANDLER( txc_mxmdhtwo_l_r )
	7527	READ8_MEMBER(nes_state::txc_mxmdhtwo_l_r)
7631	7528	{
7632	7529	return 0x50;
7633	7530	}
7634	7531
7635		static WRITE8_HANDLER( txc_mxmdhtwo_w )
	7532	WRITE8_MEMBER(nes_state::txc_mxmdhtwo_w)
7636	7533	{
7637	7534	LOG_MMC(("txc_mxmdhtwo_w, offset: %04x, data: %02x\n", offset, data));
7638	7535
7639		prg32(space.machine(), data);
	7536	prg32(machine(), data);
7640	7537	}
7641	7538
7642	7539	/*************************************************************
r18063	r18064
7691	7588	chr1_x(machine, start, bank, chr_src);
7692	7589	}
7693	7590
7694		static WRITE8_HANDLER( waixing_a_w )
	7591	WRITE8_MEMBER(nes_state::waixing_a_w)
7695	7592	{
7696	7593	LOG_MMC(("waixing_a_w, offset: %04x, data: %02x\n", offset, data));
7697	7594
7698	7595	switch (offset & 0x6001)
7699	7596	{
7700	7597	case 0x2000:
7701		waixing_set_mirror(space.machine(), data);   //maybe data & 0x03?
	7598	waixing_set_mirror(machine(), data);   //maybe data & 0x03?
7702	7599	break;
7703	7600
7704	7601	case 0x2001:
r18063	r18064
7813	7710
7814	7711	*************************************************************/
7815	7712
7816		static WRITE8_HANDLER( waixing_f_w )
	7713	WRITE8_MEMBER(nes_state::waixing_f_w)
7817	7714	{
7818		nes_state *state = space.machine().driver_data<nes_state>();
7819	7715	UINT8 cmd;
7820	7716	LOG_MMC(("waixing_f_w, offset: %04x, data: %02x\n", offset, data));
7821	7717
7822	7718	switch (offset & 0x6001)
7823	7719	{
7824	7720	case 0x0001:
7825		cmd = state->m_mmc_latch1 & 0x07;
	7721	cmd = m_mmc_latch1 & 0x07;
7826	7722	if (cmd >= 6)
7827	7723	{
7828		state->m_mmc_prg_bank[cmd - 6] = data & ((data > 0x3f) ? 0x4f : 0x3f);
7829		mmc3_set_prg(space.machine(), state->m_mmc_prg_base, state->m_mmc_prg_mask);
	7724	m_mmc_prg_bank[cmd - 6] = data & ((data > 0x3f) ? 0x4f : 0x3f);
	7725	mmc3_set_prg(machine(), m_mmc_prg_base, m_mmc_prg_mask);
7830	7726	}
7831	7727	else
7832	7728	waixing_a_w(space, offset, data, mem_mask);
r18063	r18064
7874	7770	state->m_mmc3_chr_cb(machine, chr_page ^ 7, chr_base | (state->m_mmc_vrom_bank[5] & chr_mask), state->m_mmc_chr_source);
7875	7771	}
7876	7772
7877		static WRITE8_HANDLER( waixing_g_w )
	7773	WRITE8_MEMBER(nes_state::waixing_g_w)
7878	7774	{
7879		nes_state *state = space.machine().driver_data<nes_state>();
7880	7775	UINT8 MMC3_helper, cmd;
7881	7776	LOG_MMC(("waixing_g_w, offset: %04x, data: %02x\n", offset, data));
7882	7777
7883	7778	switch (offset & 0x6001)
7884	7779	{
7885	7780	case 0x0000:
7886		MMC3_helper = state->m_mmc_latch1 ^ data;
7887		state->m_mmc_latch1 = data;
	7781	MMC3_helper = m_mmc_latch1 ^ data;
	7782	m_mmc_latch1 = data;
7888	7783
7889	7784	/* Has PRG Mode changed? */
7890	7785	if (MMC3_helper & 0x40)
7891		mmc3_set_prg(space.machine(), state->m_mmc_prg_base, state->m_mmc_prg_mask);
	7786	mmc3_set_prg(machine(), m_mmc_prg_base, m_mmc_prg_mask);
7892	7787
7893	7788	/* Has CHR Mode changed? */
7894	7789	if (MMC3_helper & 0x80)
7895		waixing_g_set_chr(space.machine(), state->m_mmc_chr_base, state->m_mmc_chr_mask);
	7790	waixing_g_set_chr(machine(), m_mmc_chr_base, m_mmc_chr_mask);
7896	7791	break;
7897	7792
7898	7793	case 0x0001:
7899		cmd = state->m_mmc_latch1 & 0x0f;
	7794	cmd = m_mmc_latch1 & 0x0f;
7900	7795	switch (cmd)
7901	7796	{
7902	7797	case 0: case 1:   // these do not need to be separated: we take care of them in set_chr!
7903	7798	case 2: case 3: case 4: case 5:
7904		state->m_mmc_vrom_bank[cmd] = data;
7905		waixing_g_set_chr(space.machine(), state->m_mmc_chr_base, state->m_mmc_chr_mask);
	7799	m_mmc_vrom_bank[cmd] = data;
	7800	waixing_g_set_chr(machine(), m_mmc_chr_base, m_mmc_chr_mask);
7906	7801	break;
7907	7802	case 6:
7908	7803	case 7:
7909	7804	case 8:
7910	7805	case 9:
7911		state->m_mmc_prg_bank[cmd - 6] = data;
7912		mmc3_set_prg(space.machine(), state->m_mmc_prg_base, state->m_mmc_prg_mask);
	7806	m_mmc_prg_bank[cmd - 6] = data;
	7807	mmc3_set_prg(machine(), m_mmc_prg_base, m_mmc_prg_mask);
7913	7808	break;
7914	7809	case 0x0a: case 0x0b:
7915		state->m_mmc_vrom_bank[cmd - 4] = data;
7916		waixing_g_set_chr(space.machine(), state->m_mmc_chr_base, state->m_mmc_chr_mask);
	7810	m_mmc_vrom_bank[cmd - 4] = data;
	7811	waixing_g_set_chr(machine(), m_mmc_chr_base, m_mmc_chr_mask);
7917	7812	break;
7918	7813	}
7919	7814	break;
r18063	r18064
7945	7840	chr1_x(machine, start, bank, source);
7946	7841	}
7947	7842
7948		static WRITE8_HANDLER( waixing_h_w )
	7843	WRITE8_MEMBER(nes_state::waixing_h_w)
7949	7844	{
7950		nes_state *state = space.machine().driver_data<nes_state>();
7951	7845	UINT8 cmd;
7952	7846	LOG_MMC(("waixing_h_w, offset: %04x, data: %02x\n", offset, data));
7953	7847
7954	7848	switch (offset & 0x6001)
7955	7849	{
7956	7850	case 0x0001:
7957		cmd = state->m_mmc3_latch & 0x07;
	7851	cmd = m_mmc3_latch & 0x07;
7958	7852	switch (cmd)
7959	7853	{
7960		case 0:    // in this case we set prg_base in addition to state->m_mmc_vrom_bank!
7961		state->m_mmc_prg_base = (data << 5) & 0x40;
7962		state->m_mmc_prg_mask = 0x3f;
7963		mmc3_set_prg(space.machine(), state->m_mmc_prg_base, state->m_mmc_prg_mask);
	7854	case 0:    // in this case we set prg_base in addition to m_mmc_vrom_bank!
	7855	m_mmc_prg_base = (data << 5) & 0x40;
	7856	m_mmc_prg_mask = 0x3f;
	7857	mmc3_set_prg(machine(), m_mmc_prg_base, m_mmc_prg_mask);
7964	7858	txrom_w(space, offset, data, mem_mask);
7965	7859	default:
7966	7860	txrom_w(space, offset, data, mem_mask);
r18063	r18064
7991	7885
7992	7886	*************************************************************/
7993	7887
7994		static WRITE8_HANDLER( waixing_sgz_w )
	7888	WRITE8_MEMBER(nes_state::waixing_sgz_w)
7995	7889	{
7996		nes_state *state = space.machine().driver_data<nes_state>();
7997	7890	UINT8 mmc_helper, bank;
7998	7891	LOG_MMC(("waixing_sgz_w, offset: %04x, data: %02x\n", offset, data));
7999	7892
8000	7893	switch (offset & 0x7000)
8001	7894	{
8002	7895	case 0x0000:
8003		prg8_89(space.machine(), data);
	7896	prg8_89(machine(), data);
8004	7897	break;
8005	7898	case 0x2000:
8006		prg8_ab(space.machine(), data);
	7899	prg8_ab(machine(), data);
8007	7900	break;
8008	7901	case 0x3000:
8009	7902	case 0x4000:
r18063	r18064
8012	7905	bank = ((offset & 0x7000) - 0x3000) / 0x0800 + ((offset & 0x0008) >> 3);
8013	7906	mmc_helper = offset & 0x04;
8014	7907	if (mmc_helper)
8015		state->m_mmc_vrom_bank[bank] = (state->m_mmc_vrom_bank[bank] & 0x0f) | ((data & 0x0f) << 4);
	7908	m_mmc_vrom_bank[bank] = (m_mmc_vrom_bank[bank] & 0x0f) | ((data & 0x0f) << 4);
8016	7909	else
8017		state->m_mmc_vrom_bank[bank] = (state->m_mmc_vrom_bank[bank] & 0xf0) | (data & 0x0f);
8018		chr1_x(space.machine(), bank, state->m_mmc_vrom_bank[bank], CHRROM);
	7910	m_mmc_vrom_bank[bank] = (m_mmc_vrom_bank[bank] & 0xf0) | (data & 0x0f);
	7911	chr1_x(machine(), bank, m_mmc_vrom_bank[bank], CHRROM);
8019	7912	break;
8020	7913	case 0x7000:
8021	7914	switch (offset & 0x0c)
8022	7915	{
8023	7916	case 0x00:
8024		state->m_IRQ_count_latch = (state->m_IRQ_count_latch & 0xf0) | (data & 0x0f);
	7917	m_IRQ_count_latch = (m_IRQ_count_latch & 0xf0) | (data & 0x0f);
8025	7918	break;
8026	7919	case 0x04:
8027		state->m_IRQ_count_latch = (state->m_IRQ_count_latch & 0x0f) | ((data & 0x0f) << 4);
	7920	m_IRQ_count_latch = (m_IRQ_count_latch & 0x0f) | ((data & 0x0f) << 4);
8028	7921	break;
8029	7922	case 0x08:
8030		state->m_IRQ_enable = data & 0x02;
8031		state->m_IRQ_enable_latch = data & 0x01;
	7923	m_IRQ_enable = data & 0x02;
	7924	m_IRQ_enable_latch = data & 0x01;
8032	7925	if (data & 0x02)
8033		state->m_IRQ_count = state->m_IRQ_count_latch;
	7926	m_IRQ_count = m_IRQ_count_latch;
8034	7927	break;
8035	7928	case 0x0c:
8036		state->m_IRQ_enable = state->m_IRQ_enable_latch;
	7929	m_IRQ_enable = m_IRQ_enable_latch;
8037	7930	break;
8038	7931	}
8039	7932	break;
r18063	r18064
8054	7947
8055	7948	*************************************************************/
8056	7949
8057		static WRITE8_HANDLER( waixing_sgzlz_l_w )
	7950	WRITE8_MEMBER(nes_state::waixing_sgzlz_l_w)
8058	7951	{
8059		nes_state *state = space.machine().driver_data<nes_state>();
8060	7952	LOG_MMC(("waixing_sgzlz_l_w, offset: %04x, data: %02x\n", offset, data));
8061	7953
8062	7954	switch (offset)
8063	7955	{
8064	7956	case 0x700:
8065		set_nt_mirroring(space.machine(), data ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	7957	set_nt_mirroring(machine(), data ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
8066	7958	break;
8067	7959	case 0x701:
8068		state->m_mmc_latch1 = (state->m_mmc_latch1 & 0x0c) | ((data >> 1) & 0x03);
8069		prg32(space.machine(), state->m_mmc_latch1);
	7960	m_mmc_latch1 = (m_mmc_latch1 & 0x0c) | ((data >> 1) & 0x03);
	7961	prg32(machine(), m_mmc_latch1);
8070	7962	break;
8071	7963	case 0x702:
8072		state->m_mmc_latch1 = (state->m_mmc_latch1 & 0x03) | ((data << 2) & 0x0c);
	7964	m_mmc_latch1 = (m_mmc_latch1 & 0x03) | ((data << 2) & 0x0c);
8073	7965	break;
8074	7966	}
8075	7967	}
r18063	r18064
8087	7979
8088	7980	*************************************************************/
8089	7981
8090		static WRITE8_HANDLER( waixing_ffv_l_w )
	7982	WRITE8_MEMBER(nes_state::waixing_ffv_l_w)
8091	7983	{
8092		nes_state *state = space.machine().driver_data<nes_state>();
8093	7984	UINT8 mmc_helper;
8094	7985	LOG_MMC(("waixing_ffv_l_w, offset: %04x, data: %02x\n", offset, data));
8095	7986	offset += 0x100; /* the checks work better on addresses */
8096	7987
8097	7988	if (0x1000 == (offset & 0x1200))
8098	7989	{
8099		state->m_mmc_reg[BIT(offset, 8)] = data;
8100		mmc_helper = BIT(state->m_mmc_reg[1], 0) << 5;
8101		switch (state->m_mmc_reg[0] & 0x70)
	7990	m_mmc_reg[BIT(offset, 8)] = data;
	7991	mmc_helper = BIT(m_mmc_reg[1], 0) << 5;
	7992	switch (m_mmc_reg[0] & 0x70)
8102	7993	{
8103	7994	case 0x00:
8104	7995	case 0x20:
8105	7996	case 0x40:
8106	7997	case 0x60:
8107		prg16_89ab(space.machine(), mmc_helper | ((state->m_mmc_reg[0] >> 1) & 0x10) | (state->m_mmc_reg[0] & 0x0f));
8108		prg16_cdef(space.machine(), mmc_helper & 0x1f);
	7998	prg16_89ab(machine(), mmc_helper | ((m_mmc_reg[0] >> 1) & 0x10) | (m_mmc_reg[0] & 0x0f));
	7999	prg16_cdef(machine(), mmc_helper & 0x1f);
8109	8000	break;
8110	8001	case 0x50:
8111		prg32(space.machine(), (mmc_helper >> 1) | (state->m_mmc_reg[0] & 0x0f));
	8002	prg32(machine(), (mmc_helper >> 1) | (m_mmc_reg[0] & 0x0f));
8112	8003	break;
8113	8004	case 0x70:
8114		prg16_89ab(space.machine(), mmc_helper | ((state->m_mmc_reg[0] << 1) & 0x10) | (state->m_mmc_reg[0] & 0x0f));
8115		prg16_cdef(space.machine(), mmc_helper & 0x1f);
	8005	prg16_89ab(machine(), mmc_helper | ((m_mmc_reg[0] << 1) & 0x10) | (m_mmc_reg[0] & 0x0f));
	8006	prg16_cdef(machine(), mmc_helper & 0x1f);
8116	8007	break;
8117	8008	}
8118	8009	}
r18063	r18064
8137	8028
8138	8029	*************************************************************/
8139	8030
8140		static WRITE8_HANDLER( waixing_zs_w )
	8031	WRITE8_MEMBER(nes_state::waixing_zs_w)
8141	8032	{
8142	8033	LOG_MMC(("waixing_zs_w, offset: %04x, data: %02x\n", offset, data));
8143	8034
8144		prg32(space.machine(), offset >> 3);
	8035	prg32(machine(), offset >> 3);
8145	8036
8146	8037	switch (data & 0x03)
8147	8038	{
8148		case 0: set_nt_mirroring(space.machine(), PPU_MIRROR_VERT); break;
8149		case 1: set_nt_mirroring(space.machine(), PPU_MIRROR_HORZ); break;
8150		case 2: set_nt_mirroring(space.machine(), PPU_MIRROR_LOW); break;
8151		case 3: set_nt_mirroring(space.machine(), PPU_MIRROR_HIGH); break;
	8039	case 0: set_nt_mirroring(machine(), PPU_MIRROR_VERT); break;
	8040	case 1: set_nt_mirroring(machine(), PPU_MIRROR_HORZ); break;
	8041	case 2: set_nt_mirroring(machine(), PPU_MIRROR_LOW); break;
	8042	case 3: set_nt_mirroring(machine(), PPU_MIRROR_HIGH); break;
8152	8043	}
8153	8044	}
8154	8045
r18063	r18064
8167	8058
8168	8059	*************************************************************/
8169	8060
8170		static WRITE8_HANDLER( waixing_dq8_w )
	8061	WRITE8_MEMBER(nes_state::waixing_dq8_w)
8171	8062	{
8172	8063	LOG_MMC(("waixing_dq8_w, offset: %04x, data: %02x\n", offset, data));
8173	8064
8174		prg32(space.machine(), offset >> 3);
	8065	prg32(machine(), offset >> 3);
8175	8066	}
8176	8067
8177	8068
r18063	r18064
8187	8078
8188	8079	*************************************************************/
8189	8080
8190		static WRITE8_HANDLER( waixing_ps2_w )
	8081	WRITE8_MEMBER(nes_state::waixing_ps2_w)
8191	8082	{
8192	8083	UINT8 map15_flip = (data & 0x80) >> 7;
8193	8084	UINT8 map15_helper = (data & 0x7f) << 1;
8194	8085
8195	8086	LOG_MMC(("waixing_ps2_w, offset: %04x, data: %02x\n", offset, data));
8196	8087
8197		set_nt_mirroring(space.machine(), BIT(data, 6) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	8088	set_nt_mirroring(machine(), BIT(data, 6) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
8198	8089
8199	8090	switch (offset & 0x0fff)
8200	8091	{
8201	8092	case 0x000:
8202		prg8_89(space.machine(), (map15_helper + 0) ^ map15_flip);
8203		prg8_ab(space.machine(), (map15_helper + 1) ^ map15_flip);
8204		prg8_cd(space.machine(), (map15_helper + 2) ^ map15_flip);
8205		prg8_ef(space.machine(), (map15_helper + 3) ^ map15_flip);
	8093	prg8_89(machine(), (map15_helper + 0) ^ map15_flip);
	8094	prg8_ab(machine(), (map15_helper + 1) ^ map15_flip);
	8095	prg8_cd(machine(), (map15_helper + 2) ^ map15_flip);
	8096	prg8_ef(machine(), (map15_helper + 3) ^ map15_flip);
8206	8097	break;
8207	8098	case 0x001:
8208	8099	map15_helper |= map15_flip;
8209		prg8_89(space.machine(), map15_helper);
8210		prg8_ab(space.machine(), map15_helper + 1);
8211		prg8_cd(space.machine(), map15_helper + 1);
8212		prg8_ef(space.machine(), map15_helper + 1);
	8100	prg8_89(machine(), map15_helper);
	8101	prg8_ab(machine(), map15_helper + 1);
	8102	prg8_cd(machine(), map15_helper + 1);
	8103	prg8_ef(machine(), map15_helper + 1);
8213	8104	break;
8214	8105	case 0x002:
8215	8106	map15_helper |= map15_flip;
8216		prg8_89(space.machine(), map15_helper);
8217		prg8_ab(space.machine(), map15_helper);
8218		prg8_cd(space.machine(), map15_helper);
8219		prg8_ef(space.machine(), map15_helper);
	8107	prg8_89(machine(), map15_helper);
	8108	prg8_ab(machine(), map15_helper);
	8109	prg8_cd(machine(), map15_helper);
	8110	prg8_ef(machine(), map15_helper);
8220	8111	break;
8221	8112	case 0x003:
8222	8113	map15_helper |= map15_flip;
8223		prg8_89(space.machine(), map15_helper);
8224		prg8_ab(space.machine(), map15_helper + 1);
8225		prg8_cd(space.machine(), map15_helper);
8226		prg8_ef(space.machine(), map15_helper + 1);
	8114	prg8_89(machine(), map15_helper);
	8115	prg8_ab(machine(), map15_helper + 1);
	8116	prg8_cd(machine(), map15_helper);
	8117	prg8_ef(machine(), map15_helper + 1);
8227	8118	break;
8228	8119	}
8229	8120	}
r18063	r18064
8264	8155	chr1_x(machine, start, bank, source);
8265	8156	}
8266	8157
8267		static WRITE8_HANDLER( waixing_sec_l_w )
	8158	WRITE8_MEMBER(nes_state::waixing_sec_l_w)
8268	8159	{
8269		nes_state *state = space.machine().driver_data<nes_state>();
8270	8160	LOG_MMC(("waixing_sec_l_w, offset: %04x, data: %02x\n", offset, data));
8271	8161
8272	8162	offset += 0x100;
8273	8163
8274	8164	if (offset == 0x1000)
8275	8165	{
8276		state->m_mmc_reg[0] = data & 0x02;
8277		mmc3_set_prg(space.machine(), state->m_mmc_prg_base, state->m_mmc_prg_mask);
8278		mmc3_set_chr(space.machine(), state->m_mmc_chr_source, state->m_mmc_chr_base, state->m_mmc_chr_mask);
	8166	m_mmc_reg[0] = data & 0x02;
	8167	mmc3_set_prg(machine(), m_mmc_prg_base, m_mmc_prg_mask);
	8168	mmc3_set_chr(machine(), m_mmc_chr_source, m_mmc_chr_base, m_mmc_chr_mask);
8279	8169	}
8280	8170	}
8281	8171
r18063	r18064
8301	8191	chr4_4(machine, state->m_mmc_reg[1], state->m_mmc_reg[1] ? CHRRAM : CHRROM);
8302	8192	}
8303	8193
8304		READ8_HANDLER( waixing_sh2_chr_r )
	8194	READ8_MEMBER(nes_state::waixing_sh2_chr_r)
8305	8195	{
8306		nes_state *state = space.machine().driver_data<nes_state>();
8307	8196	int bank = offset >> 10;
8308		UINT8 val = state->m_chr_map[bank].access[offset & 0x3ff];   // this would be usual return value
	8197	UINT8 val = m_chr_map[bank].access[offset & 0x3ff];   // this would be usual return value
8309	8198	int chr_helper;
8310	8199
8311	8200	switch (offset & 0xff8)
r18063	r18064
8315	8204	default: return val;
8316	8205	}
8317	8206
8318		state->m_mmc_reg[offset >> 12] = chr_helper;
	8207	m_mmc_reg[offset >> 12] = chr_helper;
8319	8208	if (offset & 0x1000)
8320		chr4_4(space.machine(), state->m_mmc_reg[1], state->m_mmc_reg[1] ? CHRRAM : CHRROM);
	8209	chr4_4(machine(), m_mmc_reg[1], m_mmc_reg[1] ? CHRRAM : CHRROM);
8321	8210	else
8322		chr4_0(space.machine(), state->m_mmc_reg[0], state->m_mmc_reg[0] ? CHRRAM : CHRROM);
	8211	chr4_0(machine(), m_mmc_reg[0], m_mmc_reg[0] ? CHRRAM : CHRROM);
8323	8212
8324	8213	return val;
8325	8214	}
r18063	r18064
8352	8241	chr1_x(machine, start, bank, source);
8353	8242	}
8354	8243
8355		static WRITE8_HANDLER( unl_8237_l_w )
	8244	WRITE8_MEMBER(nes_state::unl_8237_l_w)
8356	8245	{
8357		nes_state *state = space.machine().driver_data<nes_state>();
8358	8246	LOG_MMC(("unl_8237_l_w offset: %04x, data: %02x\n", offset, data));
8359	8247	offset += 0x100;
8360	8248
8361	8249	if (offset == 0x1000)
8362	8250	{
8363		state->m_mmc_reg[0] = data;
8364		if (state->m_mmc_reg[0] & 0x80)
	8251	m_mmc_reg[0] = data;
	8252	if (m_mmc_reg[0] & 0x80)
8365	8253	{
8366		if (state->m_mmc_reg[0] & 0x20)
8367		prg32(space.machine(), (state->m_mmc_reg[0] & 0x0f) >> 1);
	8254	if (m_mmc_reg[0] & 0x20)
	8255	prg32(machine(), (m_mmc_reg[0] & 0x0f) >> 1);
8368	8256	else
8369	8257	{
8370		prg16_89ab(space.machine(), state->m_mmc_reg[0] & 0x1f);
8371		prg16_cdef(space.machine(), state->m_mmc_reg[0] & 0x1f);
	8258	prg16_89ab(machine(), m_mmc_reg[0] & 0x1f);
	8259	prg16_cdef(machine(), m_mmc_reg[0] & 0x1f);
8372	8260	}
8373	8261	}
8374	8262	else
8375		mmc3_set_prg(space.machine(), state->m_mmc_prg_base, state->m_mmc_prg_mask);
	8263	mmc3_set_prg(machine(), m_mmc_prg_base, m_mmc_prg_mask);
8376	8264	}
8377	8265
8378	8266	if (offset == 0x1001)
8379	8267	{
8380		state->m_mmc_reg[1] = data;
8381		mmc3_set_chr(space.machine(), state->m_mmc_chr_source, state->m_mmc_chr_base, state->m_mmc_chr_mask);
	8268	m_mmc_reg[1] = data;
	8269	mmc3_set_chr(machine(), m_mmc_chr_source, m_mmc_chr_base, m_mmc_chr_mask);
8382	8270	}
8383	8271	}
8384	8272
8385		static WRITE8_HANDLER( unl_8237_w )
	8273	WRITE8_MEMBER(nes_state::unl_8237_w)
8386	8274	{
8387		nes_state *state = space.machine().driver_data<nes_state>();
8388	8275	static const UINT8 conv_table[8] = {0, 2, 6, 1, 7, 3, 4, 5};
8389	8276	LOG_MMC(("unl_8237_w offset: %04x, data: %02x\n", offset, data));
8390	8277
r18063	r18064
8392	8279	{
8393	8280	case 0x0000:
8394	8281	case 0x1000:
8395		set_nt_mirroring(space.machine(), (data | (data >> 7)) & 0x01 ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	8282	set_nt_mirroring(machine(), (data | (data >> 7)) & 0x01 ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
8396	8283	break;
8397	8284
8398	8285	case 0x2000:
8399	8286	case 0x3000:
8400		state->m_mmc_reg[2] = 1;
	8287	m_mmc_reg[2] = 1;
8401	8288	data = (data & 0xc0) | conv_table[data & 0x07];
8402	8289	txrom_w(space, 0x0000, data, mem_mask);
8403	8290	break;
8404	8291
8405	8292	case 0x4000:
8406	8293	case 0x5000:
8407		if (state->m_mmc_reg[2])
	8294	if (m_mmc_reg[2])
8408	8295	{
8409		state->m_mmc_reg[2] = 0;
	8296	m_mmc_reg[2] = 0;
8410	8297	txrom_w(space, 0x0001, data, mem_mask);
8411	8298	}
8412	8299	break;
r18063	r18064
8439	8326	prg8_ab(machine, state->m_mmc_prg_bank[1]);
8440	8327	}
8441	8328
8442		static WRITE8_HANDLER( unl_ax5705_w )
	8329	WRITE8_MEMBER(nes_state::unl_ax5705_w)
8443	8330	{
8444		nes_state *state = space.machine().driver_data<nes_state>();
8445	8331	UINT8 bank;
8446	8332	LOG_MMC(("unl_ax5705_w offset: %04x, data: %02x\n", offset, data));
8447	8333
8448	8334	switch (offset & 0x700f)
8449	8335	{
8450	8336	case 0x0000:
8451		state->m_mmc_prg_bank[0] = (data & 0x05) | ((data & 0x08) >> 2) | ((data & 0x02) << 2);
8452		unl_ax5705_set_prg(space.machine());
	8337	m_mmc_prg_bank[0] = (data & 0x05) | ((data & 0x08) >> 2) | ((data & 0x02) << 2);
	8338	unl_ax5705_set_prg(machine());
8453	8339	break;
8454	8340	case 0x0008:
8455		set_nt_mirroring(space.machine(), BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	8341	set_nt_mirroring(machine(), BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
8456	8342	break;
8457	8343	case 0x2000:
8458		state->m_mmc_prg_bank[1] = (data & 0x05) | ((data & 0x08) >> 2) | ((data & 0x02) << 2);
8459		unl_ax5705_set_prg(space.machine());
	8344	m_mmc_prg_bank[1] = (data & 0x05) | ((data & 0x08) >> 2) | ((data & 0x02) << 2);
	8345	unl_ax5705_set_prg(machine());
8460	8346	break;
8461	8347	/* CHR banks 0, 1, 4, 5 */
8462	8348	case 0x2008:
r18063	r18064
8464	8350	case 0x4008:
8465	8351	case 0x400a:
8466	8352	bank = ((offset & 0x4000) ? 4 : 0) + ((offset & 0x0002) ? 1 : 0);
8467		state->m_mmc_vrom_bank[bank] = (state->m_mmc_vrom_bank[bank] & 0xf0) | (data & 0x0f);
8468		chr1_x(space.machine(), bank, state->m_mmc_vrom_bank[bank], CHRROM);
	8353	m_mmc_vrom_bank[bank] = (m_mmc_vrom_bank[bank] & 0xf0) | (data & 0x0f);
	8354	chr1_x(machine(), bank, m_mmc_vrom_bank[bank], CHRROM);
8469	8355	break;
8470	8356	case 0x2009:
8471	8357	case 0x200b:
8472	8358	case 0x4009:
8473	8359	case 0x400b:
8474	8360	bank = ((offset & 0x4000) ? 4 : 0) + ((offset & 0x0002) ? 1 : 0);
8475		state->m_mmc_vrom_bank[bank] = (state->m_mmc_vrom_bank[bank] & 0x0f) | ((data & 0x04) << 3) | ((data & 0x02) << 5) | ((data & 0x09) << 4);
8476		chr1_x(space.machine(), bank, state->m_mmc_vrom_bank[bank], CHRROM);
	8361	m_mmc_vrom_bank[bank] = (m_mmc_vrom_bank[bank] & 0x0f) | ((data & 0x04) << 3) | ((data & 0x02) << 5) | ((data & 0x09) << 4);
	8362	chr1_x(machine(), bank, m_mmc_vrom_bank[bank], CHRROM);
8477	8363	break;
8478	8364	/* CHR banks 2, 3, 6, 7 */
8479	8365	case 0x4000:
r18063	r18064
8481	8367	case 0x6000:
8482	8368	case 0x6002:
8483	8369	bank = 2 + ((offset & 0x2000) ? 4 : 0) + ((offset & 0x0002) ? 1 : 0);
8484		state->m_mmc_vrom_bank[bank] = (state->m_mmc_vrom_bank[bank] & 0xf0) | (data & 0x0f);
8485		chr1_x(space.machine(), bank, state->m_mmc_vrom_bank[bank], CHRROM);
	8370	m_mmc_vrom_bank[bank] = (m_mmc_vrom_bank[bank] & 0xf0) | (data & 0x0f);
	8371	chr1_x(machine(), bank, m_mmc_vrom_bank[bank], CHRROM);
8486	8372	break;
8487	8373	case 0x4001:
8488	8374	case 0x4003:
8489	8375	case 0x6001:
8490	8376	case 0x6003:
8491	8377	bank = 2 + ((offset & 0x2000) ? 4 : 0) + ((offset & 0x0002) ? 1 : 0);
8492		state->m_mmc_vrom_bank[bank] = (state->m_mmc_vrom_bank[bank] & 0x0f) | ((data & 0x04) << 3) | ((data & 0x02) << 5) | ((data & 0x09) << 4);
8493		chr1_x(space.machine(), bank, state->m_mmc_vrom_bank[bank], CHRROM);
	8378	m_mmc_vrom_bank[bank] = (m_mmc_vrom_bank[bank] & 0x0f) | ((data & 0x04) << 3) | ((data & 0x02) << 5) | ((data & 0x09) << 4);
	8379	chr1_x(machine(), bank, m_mmc_vrom_bank[bank], CHRROM);
8494	8380	break;
8495	8381	}
8496	8382	}
r18063	r18064
8505	8391
8506	8392	*************************************************************/
8507	8393
8508		static WRITE8_HANDLER( unl_cc21_w )
	8394	WRITE8_MEMBER(nes_state::unl_cc21_w)
8509	8395	{
8510	8396	LOG_MMC(("unl_cc21_w offset: %04x, data: %02x\n", offset, data));
8511	8397
8512		set_nt_mirroring(space.machine(), BIT(data, 1) ? PPU_MIRROR_HIGH : PPU_MIRROR_LOW);
8513		chr8(space.machine(), (offset & 0x01), CHRROM);
	8398	set_nt_mirroring(machine(), BIT(data, 1) ? PPU_MIRROR_HIGH : PPU_MIRROR_LOW);
	8399	chr8(machine(), (offset & 0x01), CHRROM);
8514	8400	}
8515	8401
8516	8402	/*************************************************************
r18063	r18064
8530	8416	return ((data >> 1) & 0x01) | ((data >> 4) & 0x02) | ((data << 2) & 0x04) | ((data >> 0) & 0xd8) | ((data << 3) & 0x20);
8531	8417	}
8532	8418
8533		static WRITE8_HANDLER( unl_kof97_w )
	8419	WRITE8_MEMBER(nes_state::unl_kof97_w)
8534	8420	{
8535	8421	LOG_MMC(("unl_kof97_w offset: %04x, data: %02x\n", offset, data));
8536	8422
r18063	r18064
8586	8472
8587	8473	*************************************************************/
8588	8474
8589		static WRITE8_HANDLER( ks7057_w )
	8475	WRITE8_MEMBER(nes_state::ks7057_w)
8590	8476	{
8591	8477	LOG_MMC(("ks7057_w, offset: %04x, data: %02x\n", offset, data));
8592	8478	offset = (BIT(offset, 0) << 1) | BIT(offset, 1) | (offset & ~0x03);
r18063	r18064
8603	8489
8604	8490	*************************************************************/
8605	8491
8606		static WRITE8_HANDLER( unl_t230_w )
	8492	WRITE8_MEMBER(nes_state::unl_t230_w)
8607	8493	{
8608		nes_state *state = space.machine().driver_data<nes_state>();
8609	8494	UINT8 bank;
8610	8495	LOG_MMC(("unl_t230_w offset: %04x, data: %02x\n", offset, data));
8611	8496
r18063	r18064
8614	8499	case 0x0000:
8615	8500	break;
8616	8501	case 0x2000:
8617		prg16_89ab(space.machine(), data);
	8502	prg16_89ab(machine(), data);
8618	8503	break;
8619	8504
8620	8505	// the part below works like VRC-2. how was the original board wired up?
r18063	r18064
8625	8510	case 0x100c:
8626	8511	switch (data & 0x03)
8627	8512	{
8628		case 0x00: set_nt_mirroring(space.machine(), PPU_MIRROR_VERT); break;
8629		case 0x01: set_nt_mirroring(space.machine(), PPU_MIRROR_HORZ); break;
8630		case 0x02: set_nt_mirroring(space.machine(), PPU_MIRROR_LOW); break;
8631		case 0x03: set_nt_mirroring(space.machine(), PPU_MIRROR_HIGH); break;
	8513	case 0x00: set_nt_mirroring(machine(), PPU_MIRROR_VERT); break;
	8514	case 0x01: set_nt_mirroring(machine(), PPU_MIRROR_HORZ); break;
	8515	case 0x02: set_nt_mirroring(machine(), PPU_MIRROR_LOW); break;
	8516	case 0x03: set_nt_mirroring(machine(), PPU_MIRROR_HIGH); break;
8632	8517	}
8633	8518	break;
8634	8519
r18063	r18064
8650	8535	case 0x600c:
8651	8536	bank = ((offset & 0x7000) - 0x3000) / 0x0800 + ((offset & 0x0008) >> 2);
8652	8537	if (offset & 0x0004)
8653		state->m_mmc_vrom_bank[bank] = (state->m_mmc_vrom_bank[bank] & 0x0f) | (data << 4);
	8538	m_mmc_vrom_bank[bank] = (m_mmc_vrom_bank[bank] & 0x0f) | (data << 4);
8654	8539	else
8655		state->m_mmc_vrom_bank[bank] = (state->m_mmc_vrom_bank[bank] & 0xf0) | (data & 0x0f);
	8540	m_mmc_vrom_bank[bank] = (m_mmc_vrom_bank[bank] & 0xf0) | (data & 0x0f);
8656	8541
8657		chr1_x(space.machine(), bank, state->m_mmc_vrom_bank[bank], state->m_mmc_chr_source);
	8542	chr1_x(machine(), bank, m_mmc_vrom_bank[bank], m_mmc_chr_source);
8658	8543	break;
8659	8544	case 0x7000:
8660		state->m_IRQ_count_latch &= ~0x0f;
8661		state->m_IRQ_count_latch |= data & 0x0f;
	8545	m_IRQ_count_latch &= ~0x0f;
	8546	m_IRQ_count_latch |= data & 0x0f;
8662	8547	break;
8663	8548	case 0x7004:
8664		state->m_IRQ_count_latch &= ~0xf0;
8665		state->m_IRQ_count_latch |= (data << 4) & 0xf0;
	8549	m_IRQ_count_latch &= ~0xf0;
	8550	m_IRQ_count_latch |= (data << 4) & 0xf0;
8666	8551	break;
8667	8552	case 0x7008:
8668		state->m_IRQ_mode = data & 0x04;   // currently not implemented: 0 = prescaler mode / 1 = CPU mode
8669		state->m_IRQ_enable = data & 0x02;
8670		state->m_IRQ_enable_latch = data & 0x01;
	8553	m_IRQ_mode = data & 0x04;   // currently not implemented: 0 = prescaler mode / 1 = CPU mode
	8554	m_IRQ_enable = data & 0x02;
	8555	m_IRQ_enable_latch = data & 0x01;
8671	8556	if (data & 0x02)
8672		state->m_IRQ_count = state->m_IRQ_count_latch;
	8557	m_IRQ_count = m_IRQ_count_latch;
8673	8558	break;
8674	8559
8675	8560	default:
r18063	r18064
8712	8597	chr1_x(machine, start, bank, source);
8713	8598	}
8714	8599
8715		static WRITE8_HANDLER( kof96_l_w )
	8600	WRITE8_MEMBER(nes_state::kof96_l_w)
8716	8601	{
8717		nes_state *state = space.machine().driver_data<nes_state>();
8718	8602	UINT8 new_bank;
8719	8603	LOG_MMC(("kof96_l_w, offset: %04x, data: %02x\n", offset, data));
8720	8604	offset += 0x100;
8721	8605
8722	8606	if (offset == 0x1000)
8723	8607	{
8724		state->m_mmc_reg[0] = data;
	8608	m_mmc_reg[0] = data;
8725	8609
8726		if (state->m_mmc_reg[0] & 0x80)
	8610	if (m_mmc_reg[0] & 0x80)
8727	8611	{
8728		new_bank = (state->m_mmc_reg[0] & 0x1f);
	8612	new_bank = (m_mmc_reg[0] & 0x1f);
8729	8613
8730		if (state->m_mmc_reg[0] & 0x20)
8731		prg32(space.machine(), new_bank >> 2);
	8614	if (m_mmc_reg[0] & 0x20)
	8615	prg32(machine(), new_bank >> 2);
8732	8616	else
8733	8617	{
8734		prg16_89ab(space.machine(), new_bank);
8735		prg16_cdef(space.machine(), new_bank);
	8618	prg16_89ab(machine(), new_bank);
	8619	prg16_cdef(machine(), new_bank);
8736	8620	}
8737	8621	}
8738	8622	else
8739		mmc3_set_prg(space.machine(), state->m_mmc_prg_base, state->m_mmc_prg_mask);
	8623	mmc3_set_prg(machine(), m_mmc_prg_base, m_mmc_prg_mask);
8740	8624	}
8741	8625
8742	8626	if (offset >= 0x1000)
r18063	r18064
8745	8629	{
8746	8630	case 0x00:
8747	8631	case 0x01:
8748		state->m_mmc_reg[1] = 0x83;
	8632	m_mmc_reg[1] = 0x83;
8749	8633	break;
8750	8634	case 0x02:
8751		state->m_mmc_reg[1] = 0x42;
	8635	m_mmc_reg[1] = 0x42;
8752	8636	break;
8753	8637	case 0x03:
8754		state->m_mmc_reg[1] = 0x00;
	8638	m_mmc_reg[1] = 0x00;
8755	8639	break;
8756	8640	}
8757	8641
8758	8642	}
8759	8643
8760		if (!state->m_mmc_reg[3] && offset > 0x1000)
	8644	if (!m_mmc_reg[3] && offset > 0x1000)
8761	8645	{
8762		state->m_mmc_reg[3] = 1;
	8646	m_mmc_reg[3] = 1;
8763	8647	space.write_byte(0x4017, 0x40);
8764	8648	}
8765	8649	}
8766	8650
8767		static READ8_HANDLER( kof96_l_r )
	8651	READ8_MEMBER(nes_state::kof96_l_r)
8768	8652	{
8769		nes_state *state = space.machine().driver_data<nes_state>();
8770	8653	LOG_MMC(("kof96_l_r, offset: %04x\n", offset));
8771	8654	offset += 0x100;
8772	8655
8773	8656	if (!(offset < 0x1000))
8774		return state->m_mmc_reg[1];
	8657	return m_mmc_reg[1];
8775	8658	else
8776	8659	return 0;
8777	8660	}
8778	8661
8779		static WRITE8_HANDLER( kof96_w )
	8662	WRITE8_MEMBER(nes_state::kof96_w)
8780	8663	{
8781		nes_state *state = space.machine().driver_data<nes_state>();
8782	8664	LOG_MMC(("kof96_w, offset: %04x, data: %02x\n", offset, data));
8783	8665
8784	8666	switch (offset & 0x6003)
8785	8667	{
8786	8668	case 0x0000:
8787		state->m_mmc_reg[2] = 1;
	8669	m_mmc_reg[2] = 1;
8788	8670	txrom_w(space, 0x0000, data, mem_mask);
8789	8671	break;
8790	8672
8791	8673	case 0x0001:
8792		if (state->m_mmc_reg[2])
	8674	if (m_mmc_reg[2])
8793	8675	txrom_w(space, 0x0001, data, mem_mask);
8794	8676	break;
8795	8677
r18063	r18064
8797	8679	break;
8798	8680
8799	8681	case 0x0003:
8800		state->m_mmc_reg[2] = 0;
	8682	m_mmc_reg[2] = 0;
8801	8683
8802	8684	if (data == 0x28)
8803		prg8_cd(space.machine(), 0x17);
	8685	prg8_cd(machine(), 0x17);
8804	8686	else if (data == 0x2a)
8805		prg8_ab(space.machine(), 0x0f);
	8687	prg8_ab(machine(), 0x0f);
8806	8688	break;
8807	8689
8808	8690	default:
r18063	r18064
8827	8709
8828	8710	*************************************************************/
8829	8711
8830		static WRITE8_HANDLER( mk2_m_w )
	8712	WRITE8_MEMBER(nes_state::mk2_m_w)
8831	8713	{
8832		nes_state *state = space.machine().driver_data<nes_state>();
8833	8714	LOG_MMC(("mk2_m_w, offset: %04x, data: %02x\n", offset, data));
8834	8715
8835	8716	switch (offset & 0x1000)
r18063	r18064
8837	8718	case 0x0000:
8838	8719	switch (offset & 0x03)
8839	8720	{
8840		case 0x00: chr2_0(space.machine(), data, CHRROM); break;
8841		case 0x01: chr2_2(space.machine(), data, CHRROM); break;
8842		case 0x02: chr2_4(space.machine(), data, CHRROM); break;
8843		case 0x03: chr2_6(space.machine(), data, CHRROM); break;
	8721	case 0x00: chr2_0(machine(), data, CHRROM); break;
	8722	case 0x01: chr2_2(machine(), data, CHRROM); break;
	8723	case 0x02: chr2_4(machine(), data, CHRROM); break;
	8724	case 0x03: chr2_6(machine(), data, CHRROM); break;
8844	8725	}
8845	8726	break;
8846	8727	case 0x1000:
8847	8728	switch (offset & 0x03)
8848	8729	{
8849		case 0x00: prg8_89(space.machine(), data); break;
8850		case 0x01: prg8_ab(space.machine(), data); break;
8851		case 0x02: state->m_IRQ_enable = 0; state->m_IRQ_count = 0; break;
8852		case 0x03: state->m_IRQ_enable = 1; state->m_IRQ_count = 7; break;
	8730	case 0x00: prg8_89(machine(), data); break;
	8731	case 0x01: prg8_ab(machine(), data); break;
	8732	case 0x02: m_IRQ_enable = 0; m_IRQ_count = 0; break;
	8733	case 0x03: m_IRQ_enable = 1; m_IRQ_count = 7; break;
8853	8734	}
8854	8735	break;
8855	8736	default:
r18063	r18064
8883	8764	prg16_cdef(machine, map221_helper2 | ((reg1 & 0x70) >> 1));
8884	8765	}
8885	8766
8886		static WRITE8_HANDLER( n625092_w )
	8767	WRITE8_MEMBER(nes_state::n625092_w)
8887	8768	{
8888		nes_state *state = space.machine().driver_data<nes_state>();
8889	8769	LOG_MMC(("n625092_w, offset: %04x, data: %02x\n", offset, data));
8890	8770
8891	8771	if (offset < 0x4000)
8892	8772	{
8893		set_nt_mirroring(space.machine(), BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	8773	set_nt_mirroring(machine(), BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
8894	8774	offset = (offset >> 1) & 0xff;
8895	8775
8896		if (state->m_mmc_latch1 != offset)
	8776	if (m_mmc_latch1 != offset)
8897	8777	{
8898		state->m_mmc_latch1 = offset;
8899		n625092_set_prg(space.machine(), state->m_mmc_latch1, state->m_mmc_latch2);
	8778	m_mmc_latch1 = offset;
	8779	n625092_set_prg(machine(), m_mmc_latch1, m_mmc_latch2);
8900	8780	}
8901	8781	}
8902	8782	else
8903	8783	{
8904	8784	offset &= 0x07;
8905	8785
8906		if (state->m_mmc_latch2 != offset)
	8786	if (m_mmc_latch2 != offset)
8907	8787	{
8908		state->m_mmc_latch2 = offset;
8909		n625092_set_prg(space.machine(), state->m_mmc_latch1, state->m_mmc_latch2);
	8788	m_mmc_latch2 = offset;
	8789	n625092_set_prg(machine(), m_mmc_latch1, m_mmc_latch2);
8910	8790	}
8911	8791	}
8912	8792	}
r18063	r18064
8941	8821	}
8942	8822	}
8943	8823
8944		static WRITE8_HANDLER( sc127_w )
	8824	WRITE8_MEMBER(nes_state::sc127_w)
8945	8825	{
8946		nes_state *state = space.machine().driver_data<nes_state>();
8947	8826	LOG_MMC(("sc127_w, offset: %04x, data: %02x\n", offset, data));
8948	8827
8949	8828	switch (offset)
8950	8829	{
8951	8830	case 0x0000:
8952		prg8_89(space.machine(), data);
	8831	prg8_89(machine(), data);
8953	8832	break;
8954	8833	case 0x0001:
8955		prg8_ab(space.machine(), data);
	8834	prg8_ab(machine(), data);
8956	8835	break;
8957	8836	case 0x0002:
8958		//      state->m_mmc_prg_bank[offset & 0x02] = data;
8959		prg8_cd(space.machine(), data);
	8837	//      m_mmc_prg_bank[offset & 0x02] = data;
	8838	prg8_cd(machine(), data);
8960	8839	break;
8961	8840	case 0x1000:
8962	8841	case 0x1001:
r18063	r18064
8966	8845	case 0x1005:
8967	8846	case 0x1006:
8968	8847	case 0x1007:
8969		//      state->m_mmc_vrom_bank[offset & 0x07] = data;
8970		chr1_x(space.machine(), offset & 0x07, data, CHRROM);
	8848	//      m_mmc_vrom_bank[offset & 0x07] = data;
	8849	chr1_x(machine(), offset & 0x07, data, CHRROM);
8971	8850	break;
8972	8851	case 0x4002:
8973		state->m_IRQ_enable = 0;
	8852	m_IRQ_enable = 0;
8974	8853	break;
8975	8854	case 0x4003:
8976		state->m_IRQ_enable = 1;
	8855	m_IRQ_enable = 1;
8977	8856	break;
8978	8857	case 0x4005:
8979		state->m_IRQ_count = data;
	8858	m_IRQ_count = data;
8980	8859	break;
8981	8860	case 0x5001:
8982		set_nt_mirroring(space.machine(), BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	8861	set_nt_mirroring(machine(), BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
8983	8862	break;
8984	8863	}
8985	8864	}
r18063	r18064
8997	8876
8998	8877	*************************************************************/
8999	8878
9000		static WRITE8_HANDLER( smb2j_w )
	8879	WRITE8_MEMBER(nes_state::smb2j_w)
9001	8880	{
9002		nes_state *state = space.machine().driver_data<nes_state>();
9003	8881	int bank = (((offset >> 8) & 0x03) * 0x20) + (offset & 0x1f);
9004	8882
9005	8883	LOG_MMC(("smb2j_w, offset: %04x, data: %02x\n", offset, data));
9006	8884
9007		set_nt_mirroring(space.machine(), (offset & 0x2000) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	8885	set_nt_mirroring(machine(), (offset & 0x2000) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
9008	8886
9009	8887	if (offset & 0x0800)
9010	8888	{
9011	8889	if (offset & 0x1000)
9012	8890	{
9013		if (bank * 2 >= state->m_prg_chunks)
	8891	if (bank * 2 >= m_prg_chunks)
9014	8892	{
9015		state->membank("bank3")->set_base(state->m_wram);
9016		state->membank("bank4")->set_base(state->m_wram);
	8893	membank("bank3")->set_base(m_wram);
	8894	membank("bank4")->set_base(m_wram);
9017	8895	}
9018	8896	else
9019	8897	{
9020	8898	LOG_MMC(("smb2j_w, selecting upper 16KB bank of #%02x\n", bank));
9021		prg16_cdef(space.machine(), 2 * bank + 1);
	8899	prg16_cdef(machine(), 2 * bank + 1);
9022	8900	}
9023	8901	}
9024	8902	else
9025	8903	{
9026		if (bank * 2 >= state->m_prg_chunks)
	8904	if (bank * 2 >= m_prg_chunks)
9027	8905	{
9028		state->membank("bank1")->set_base(state->m_wram);
9029		state->membank("bank2")->set_base(state->m_wram);
	8906	membank("bank1")->set_base(m_wram);
	8907	membank("bank2")->set_base(m_wram);
9030	8908	}
9031	8909	else
9032	8910	{
9033	8911	LOG_MMC(("smb2j_w, selecting lower 16KB bank of #%02x\n", bank));
9034		prg16_89ab(space.machine(), 2 * bank);
	8912	prg16_89ab(machine(), 2 * bank);
9035	8913	}
9036	8914	}
9037	8915	}
9038	8916	else
9039	8917	{
9040		if (bank * 2 >= state->m_prg_chunks)
	8918	if (bank * 2 >= m_prg_chunks)
9041	8919	{
9042		state->membank("bank1")->set_base(state->m_wram);
9043		state->membank("bank2")->set_base(state->m_wram);
9044		state->membank("bank3")->set_base(state->m_wram);
9045		state->membank("bank4")->set_base(state->m_wram);
	8920	membank("bank1")->set_base(m_wram);
	8921	membank("bank2")->set_base(m_wram);
	8922	membank("bank3")->set_base(m_wram);
	8923	membank("bank4")->set_base(m_wram);
9046	8924	}
9047	8925	else
9048	8926	{
9049	8927	LOG_MMC(("smb2j_w, selecting 32KB bank #%02x\n", bank));
9050		prg32(space.machine(), bank);
	8928	prg32(machine(), bank);
9051	8929	}
9052	8930	}
9053	8931	}
r18063	r18064
9085	8963	}
9086	8964	}
9087	8965
9088		static WRITE8_HANDLER( smb2jb_l_w )
	8966	WRITE8_MEMBER(nes_state::smb2jb_l_w)
9089	8967	{
9090		nes_state *state = space.machine().driver_data<nes_state>();
9091	8968	UINT8 prg;
9092	8969	LOG_MMC(("smb2jb_l_w, offset: %04x, data: %02x\n", offset, data));
9093	8970	offset += 0x100;
r18063	r18064
9096	8973	{
9097	8974	case 0x020:
9098	8975	prg = (data & 0x08) | ((data & 0x06) >> 1) | ((data & 0x01) << 2);
9099		prg8_cd(space.machine(), prg);
	8976	prg8_cd(machine(), prg);
9100	8977	break;
9101	8978	case 0x120:
9102		state->m_IRQ_enable = data & 0x01;
	8979	m_IRQ_enable = data & 0x01;
9103	8980	break;
9104	8981	}
9105	8982	}
9106	8983
9107	8984	/* This goes to 0x4020-0x403f */
9108		WRITE8_HANDLER( smb2jb_extra_w )
	8985	WRITE8_MEMBER(nes_state::smb2jb_extra_w)
9109	8986	{
9110	8987	UINT8 prg;
9111	8988	LOG_MMC(("smb2jb_extra_w, offset: %04x, data: %02x\n", offset, data));
9112	8989
9113	8990	prg = (data & 0x08) | ((data & 0x06) >> 1) | ((data & 0x01) << 2);
9114		prg8_cd(space.machine(), prg);
	8991	prg8_cd(machine(), prg);
9115	8992	}
9116	8993
9117	8994	/*************************************************************
r18063	r18064
9134	9011	chr2_6(machine, chr_base | (state->m_mmc_vrom_bank[2] & chr_mask), chr_source);
9135	9012	}
9136	9013
9137		static WRITE8_HANDLER( unl_sf3_w )
	9014	WRITE8_MEMBER(nes_state::unl_sf3_w)
9138	9015	{
9139		nes_state *state = space.machine().driver_data<nes_state>();
9140	9016	UINT8 mmc_helper, cmd;
9141	9017	LOG_MMC(("unl_sf3_w, offset: %04x, data: %02x\n", offset, data));
9142	9018
9143	9019	switch (offset & 0x6001)
9144	9020	{
9145	9021	case 0x0000:
9146		mmc_helper = state->m_mmc3_latch ^ data;
9147		state->m_mmc3_latch = data;
	9022	mmc_helper = m_mmc3_latch ^ data;
	9023	m_mmc3_latch = data;
9148	9024
9149	9025	/* Has PRG Mode changed? */
9150	9026	if (mmc_helper & 0x40)
9151		mmc3_set_prg(space.machine(), state->m_mmc_prg_base, state->m_mmc_prg_mask);
	9027	mmc3_set_prg(machine(), m_mmc_prg_base, m_mmc_prg_mask);
9152	9028
9153	9029	/* Has CHR Mode changed? */
9154	9030	if (mmc_helper & 0x80)
9155		unl_sf3_set_chr(space.machine(), state->m_mmc_chr_source, state->m_mmc_chr_base, state->m_mmc_chr_mask);
	9031	unl_sf3_set_chr(machine(), m_mmc_chr_source, m_mmc_chr_base, m_mmc_chr_mask);
9156	9032	break;
9157	9033
9158	9034	case 0x0001:
9159		cmd = state->m_mmc3_latch & 0x0f;
	9035	cmd = m_mmc3_latch & 0x0f;
9160	9036	switch (cmd)
9161	9037	{
9162	9038	case 0: case 2: case 4:
9163		state->m_mmc_vrom_bank[cmd >> 1] = data;
9164		unl_sf3_set_chr(space.machine(), state->m_mmc_chr_source, state->m_mmc_chr_base, state->m_mmc_chr_mask);
	9039	m_mmc_vrom_bank[cmd >> 1] = data;
	9040	unl_sf3_set_chr(machine(), m_mmc_chr_source, m_mmc_chr_base, m_mmc_chr_mask);
9165	9041	break;
9166	9042	case 6:
9167	9043	case 7:
9168		state->m_mmc_prg_bank[cmd - 6] = data;
9169		mmc3_set_prg(space.machine(), state->m_mmc_prg_base, state->m_mmc_prg_mask);
	9044	m_mmc_prg_bank[cmd - 6] = data;
	9045	mmc3_set_prg(machine(), m_mmc_prg_base, m_mmc_prg_mask);
9170	9046	break;
9171	9047	}
9172	9048	break;
r18063	r18064
9192	9068
9193	9069	*************************************************************/
9194	9070
9195		static WRITE8_HANDLER( unl_xzy_l_w )
	9071	WRITE8_MEMBER(nes_state::unl_xzy_l_w)
9196	9072	{
9197	9073	LOG_MMC(("unl_xzy_l_w, offset: %04x, data: %02x\n", offset, data));
9198	9074
9199	9075	switch (offset)
9200	9076	{
9201	9077	case 0x1ef1:   /* 0x5ff1 */
9202		prg32(space.machine(), data >> 1);
	9078	prg32(machine(), data >> 1);
9203	9079	break;
9204	9080	case 0x1ef2:   /* 0x5ff2 */
9205		chr8(space.machine(), data, CHRROM);
	9081	chr8(machine(), data, CHRROM);
9206	9082	break;
9207	9083	}
9208	9084	}
r18063	r18064
9223	9099	prg16_89ab(machine, state->m_mmc_latch1 >> 1);
9224	9100	}
9225	9101
9226		static WRITE8_HANDLER( unl_racmate_w )
	9102	WRITE8_MEMBER(nes_state::unl_racmate_w)
9227	9103	{
9228		nes_state *state = space.machine().driver_data<nes_state>();
9229	9104	LOG_MMC(("unl_racmate_w offset: %04x, data: %02x\n", offset, data));
9230	9105
9231	9106	if (offset == 0x3000)
9232	9107	{
9233		state->m_mmc_latch1 = data;
9234		racmate_update_banks(space.machine());
	9108	m_mmc_latch1 = data;
	9109	racmate_update_banks(machine());
9235	9110	}
9236	9111	}
9237	9112
r18063	r18064
9248	9123
9249	9124	*************************************************************/
9250	9125
9251		static WRITE8_HANDLER( unl_fs304_l_w )
	9126	WRITE8_MEMBER(nes_state::unl_fs304_l_w)
9252	9127	{
9253		nes_state *state = space.machine().driver_data<nes_state>();
9254	9128	LOG_MMC(("unl_fs304_l_w, offset: %04x, data: %02x\n", offset, data));
9255	9129	int bank;
9256	9130	offset += 0x100;
9257	9131
9258	9132	if (offset >= 0x1000)
9259	9133	{
9260		state->m_mmc_reg[(offset >> 8) & 3] = data;
9261		bank = ((state->m_mmc_reg[2] & 0x0f) << 4) | BIT(state->m_mmc_reg[1], 1) | (state->m_mmc_reg[0] & 0x0e);
9262		prg32(space.machine(), bank);
9263		chr8(space.machine(), 0, CHRRAM);
	9134	m_mmc_reg[(offset >> 8) & 3] = data;
	9135	bank = ((m_mmc_reg[2] & 0x0f) << 4) | BIT(m_mmc_reg[1], 1) | (m_mmc_reg[0] & 0x0e);
	9136	prg32(machine(), bank);
	9137	chr8(machine(), 0, CHRRAM);
9264	9138	}
9265	9139	}
9266	9140
r18063	r18064
9286	9160
9287	9161	*************************************************************/
9288	9162
9289		static WRITE8_HANDLER( btl_smb11_w )
	9163	WRITE8_MEMBER(nes_state::btl_smb11_w)
9290	9164	{
9291	9165	LOG_MMC(("btl_smb11_w, offset: %04x, data: %02x\n", offset, data));
9292	9166
r18063	r18064
9306	9180	*************************************************************/
9307	9181
9308	9182	// is the code fine for ai senshi nicol?!?
9309		static WRITE8_HANDLER( btl_mariobaby_w )
	9183	WRITE8_MEMBER(nes_state::btl_mariobaby_w)
9310	9184	{
9311		nes_state *state = space.machine().driver_data<nes_state>();
9312	9185	LOG_MMC(("btl_mariobaby_w, offset: %04x, data: %02x\n", offset, data));
9313	9186
9314	9187	if (offset >= 0x7000)
r18063	r18064
9316	9189	switch (offset & 0x03)
9317	9190	{
9318	9191	case 0x00:
9319		prg8_67(space.machine(), data);
	9192	prg8_67(machine(), data);
9320	9193	break;
9321	9194	case 0x01:
9322		set_nt_mirroring(space.machine(), BIT(data, 3) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	9195	set_nt_mirroring(machine(), BIT(data, 3) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
9323	9196	break;
9324	9197	case 0x02:
9325	9198	/* Check if IRQ is being enabled */
9326		if (!state->m_IRQ_enable && (data & 0x02))
	9199	if (!m_IRQ_enable && (data & 0x02))
9327	9200	{
9328		state->m_IRQ_enable = 1;
9329		state->m_irq_timer->adjust(downcast<cpu_device *>(state->m_maincpu)->cycles_to_attotime(24576));
	9201	m_IRQ_enable = 1;
	9202	m_irq_timer->adjust(downcast<cpu_device *>(m_maincpu)->cycles_to_attotime(24576));
9330	9203	}
9331	9204	if (!(data & 0x02))
9332	9205	{
9333		state->m_IRQ_enable = 0;
9334		state->m_irq_timer->adjust(attotime::never);
	9206	m_IRQ_enable = 0;
	9207	m_irq_timer->adjust(attotime::never);
9335	9208	}
9336	9209	break;
9337	9210	}
r18063	r18064
9367	9240	}
9368	9241	}
9369	9242
9370		static WRITE8_HANDLER( btl_smb2a_w )
	9243	WRITE8_MEMBER(nes_state::btl_smb2a_w)
9371	9244	{
9372		nes_state *state = space.machine().driver_data<nes_state>();
9373	9245	LOG_MMC(("btl_smb2a_w, offset: %04x, data: %02x\n", offset, data));
9374	9246
9375	9247	switch (offset & 0x6000)
9376	9248	{
9377	9249	case 0x0000:
9378		state->m_IRQ_enable = 0;
9379		state->m_IRQ_count = 0;
	9250	m_IRQ_enable = 0;
	9251	m_IRQ_count = 0;
9380	9252	break;
9381	9253	case 0x2000:
9382		state->m_IRQ_enable = 1;
	9254	m_IRQ_enable = 1;
9383	9255	break;
9384	9256	case 0x6000:
9385		prg8_cd(space.machine(), data);
	9257	prg8_cd(machine(), data);
9386	9258	break;
9387	9259	}
9388	9260	}
r18063	r18064
9399	9271
9400	9272	*************************************************************/
9401	9273
9402		static WRITE8_HANDLER( whirl2706_w )
	9274	WRITE8_MEMBER(nes_state::whirl2706_w)
9403	9275	{
9404	9276	LOG_MMC(("whirl2706_w, offset: %04x, data: %02x\n", offset, data));
9405		prg8_67(space.machine(), data);
	9277	prg8_67(machine(), data);
9406	9278	}
9407	9279
9408	9280	/*************************************************************
r18063	r18064
9417	9289
9418	9290	*************************************************************/
9419	9291
9420		static WRITE8_HANDLER( btl_tobi_l_w )
	9292	WRITE8_MEMBER(nes_state::btl_tobi_l_w)
9421	9293	{
9422	9294	LOG_MMC(("btl_tobi_l_w, offset: %04x, data: %02x\n", offset, data));
9423	9295	offset += 0x100;
9424	9296
9425	9297	if ((offset & 0x43c0) == 0x41c0)
9426		prg8_67(space.machine(), data & 0x07);
	9298	prg8_67(machine(), data & 0x07);
9427	9299	}
9428	9300
9429	9301	/*************************************************************
r18063	r18064
9454	9326	}
9455	9327	}
9456	9328
9457		static WRITE8_HANDLER( btl_smb3_w )
	9329	WRITE8_MEMBER(nes_state::btl_smb3_w)
9458	9330	{
9459		nes_state *state = space.machine().driver_data<nes_state>();
9460	9331	LOG_MMC(("btl_smb3_w, offset: %04x, data: %02x\n", offset, data));
9461	9332	switch (offset & 0x0f)
9462	9333	{
9463	9334	case 0x00:
9464	9335	case 0x02:
9465		chr1_x(space.machine(), offset & 0x07, data & 0xfe, CHRROM);
	9336	chr1_x(machine(), offset & 0x07, data & 0xfe, CHRROM);
9466	9337	break;
9467	9338	case 0x01:
9468	9339	case 0x03:
9469		chr1_x(space.machine(), offset & 0x07, data | 0x01, CHRROM);
	9340	chr1_x(machine(), offset & 0x07, data | 0x01, CHRROM);
9470	9341	break;
9471	9342	case 0x04: case 0x05:
9472	9343	case 0x06: case 0x07:
9473		chr1_x(space.machine(), offset & 0x07, data, CHRROM);
	9344	chr1_x(machine(), offset & 0x07, data, CHRROM);
9474	9345	break;
9475	9346	case 0x08:
9476		prg8_89(space.machine(), data | 0x10);
	9347	prg8_89(machine(), data | 0x10);
9477	9348	break;
9478	9349	case 0x09:
9479		prg8_ab(space.machine(), data);
	9350	prg8_ab(machine(), data);
9480	9351	break;
9481	9352	case 0x0a:
9482		prg8_cd(space.machine(), data);
	9353	prg8_cd(machine(), data);
9483	9354	break;
9484	9355	case 0x0b:
9485		prg8_ef(space.machine(), data | 0x10);
	9356	prg8_ef(machine(), data | 0x10);
9486	9357	break;
9487	9358	case 0x0c:
9488		set_nt_mirroring(space.machine(), BIT(data, 0) ?  PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	9359	set_nt_mirroring(machine(), BIT(data, 0) ?  PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
9489	9360	break;
9490	9361	case 0x0d:
9491		state->m_IRQ_count = 0;
9492		state->m_IRQ_enable = 0;
	9362	m_IRQ_count = 0;
	9363	m_IRQ_enable = 0;
9493	9364	break;
9494	9365	case 0x0e:
9495		state->m_IRQ_count = (state->m_IRQ_count & 0xff00) | data;
	9366	m_IRQ_count = (m_IRQ_count & 0xff00) | data;
9496	9367	break;
9497	9368	case 0x0f:
9498		state->m_IRQ_count = (state->m_IRQ_count & 0x00ff) | (data << 8);
9499		state->m_IRQ_enable = 1;
	9369	m_IRQ_count = (m_IRQ_count & 0x00ff) | (data << 8);
	9370	m_IRQ_enable = 1;
9500	9371	break;
9501	9372	}
9502	9373	}
r18063	r18064
9529	9400	}
9530	9401	}
9531	9402
9532		static WRITE8_HANDLER( btl_dn_w )
	9403	WRITE8_MEMBER(nes_state::btl_dn_w)
9533	9404	{
9534		nes_state *state = space.machine().driver_data<nes_state>();
9535	9405	UINT8 bank;
9536	9406	LOG_MMC(("btl_dn_w, offset: %04x, data: %02x\n", offset, data));
9537	9407
9538	9408	switch (offset & 0x7003)
9539	9409	{
9540	9410	case 0x0000:
9541		prg8_89(space.machine(), data);
	9411	prg8_89(machine(), data);
9542	9412	break;
9543	9413	case 0x1000:
9544		set_nt_mirroring(space.machine(), BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	9414	set_nt_mirroring(machine(), BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
9545	9415	break;
9546	9416	case 0x2000:
9547		prg8_ab(space.machine(), data);
	9417	prg8_ab(machine(), data);
9548	9418	break;
9549	9419	case 0x3000:
9550	9420	case 0x3002:
r18063	r18064
9555	9425	case 0x6000:
9556	9426	case 0x6002:
9557	9427	bank = ((offset & 0x7000) - 0x3000) / 0x0800 + ((offset & 0x0002) >> 3);
9558		chr1_x(space.machine(), bank, data, CHRROM);
	9428	chr1_x(machine(), bank, data, CHRROM);
9559	9429	break;
9560	9430	case 0x7000:
9561		state->m_IRQ_count = data;
	9431	m_IRQ_count = data;
9562	9432	break;
9563	9433	}
9564	9434	}
r18063	r18064
9575	9445
9576	9446	*************************************************************/
9577	9447
9578		static WRITE8_HANDLER( btl_pika_y2k_w )
	9448	WRITE8_MEMBER(nes_state::btl_pika_y2k_w)
9579	9449	{
9580		nes_state *state = space.machine().driver_data<nes_state>();
9581	9450	LOG_MMC(("btl_pika_y2k_w, offset: %04x, data: %02x\n", offset, data));
9582	9451
9583	9452	switch (offset & 0x6001)
9584	9453	{
9585	9454	case 0x2001:
9586		state->m_mmc_latch2 = data;
	9455	m_mmc_latch2 = data;
9587	9456	break;
9588	9457
9589	9458	case 0x2000:
9590		state->m_mmc_reg[0] = 0;
	9459	m_mmc_reg[0] = 0;
9591	9460	default:
9592	9461	txrom_w(space, offset, data, mem_mask);
9593	9462	break;
r18063	r18064
9595	9464	}
9596	9465
9597	9466	// strange WRAM usage: it is protected at start, and gets unprotected after the first write to 0xa000
9598		static WRITE8_HANDLER( btl_pika_y2k_m_w )
	9467	WRITE8_MEMBER(nes_state::btl_pika_y2k_m_w)
9599	9468	{
9600		nes_state *state = space.machine().driver_data<nes_state>();
9601	9469	LOG_MMC(("btl_pika_y2k_m_w, offset: %04x, data: %02x\n", offset, data));
9602	9470
9603		state->m_wram[offset] = data;
	9471	m_wram[offset] = data;
9604	9472	}
9605	9473
9606		static READ8_HANDLER( btl_pika_y2k_m_r )
	9474	READ8_MEMBER(nes_state::btl_pika_y2k_m_r)
9607	9475	{
9608		nes_state *state = space.machine().driver_data<nes_state>();
9609	9476	LOG_MMC(("btl_pika_y2k_m_r, offset: %04x\n", offset));
9610	9477
9611		return   state->m_wram[offset] ^ (state->m_mmc_latch2 & state->m_mmc_reg[0]);
	9478	return   m_wram[offset] ^ (m_mmc_latch2 & m_mmc_reg[0]);
9612	9479	}
9613	9480
9614	9481	/*************************************************************
r18063	r18064
9714	9581	}
9715	9582	}
9716	9583
9717		static WRITE8_HANDLER( fk23c_l_w )
	9584	WRITE8_MEMBER(nes_state::fk23c_l_w)
9718	9585	{
9719		nes_state *state = space.machine().driver_data<nes_state>();
9720	9586	LOG_MMC(("fk23c_l_w, offset: %04x, data: %02x\n", offset, data));
9721	9587	offset += 0x100;
9722	9588
9723	9589	if (offset >= 0x1000)
9724	9590	{
9725		if (offset & (1 << 4))   // here it should be (4 + state->m_mmc_dipsetting)
	9591	if (offset & (1 << 4))   // here it should be (4 + m_mmc_dipsetting)
9726	9592	{
9727		state->m_mmc_reg[offset & 0x03] = data;
	9593	m_mmc_reg[offset & 0x03] = data;
9728	9594
9729		fk23c_set_prg(space.machine());
9730		fk23c_set_chr(space.machine());
	9595	fk23c_set_prg(machine());
	9596	fk23c_set_chr(machine());
9731	9597	}
9732	9598	}
9733	9599	}
9734	9600
9735		static WRITE8_HANDLER( fk23c_w )
	9601	WRITE8_MEMBER(nes_state::fk23c_w)
9736	9602	{
9737		nes_state *state = space.machine().driver_data<nes_state>();
9738	9603	LOG_MMC(("fk23c_w, offset: %04x, data: %02x\n", offset, data));
9739	9604
9740		if (state->m_mmc_reg[0] & 0x40)
	9605	if (m_mmc_reg[0] & 0x40)
9741	9606	{
9742		if (state->m_mmc_reg[0] & 0x30)
9743		state->m_mmc_cmd1 = 0;
	9607	if (m_mmc_reg[0] & 0x30)
	9608	m_mmc_cmd1 = 0;
9744	9609	else
9745	9610	{
9746		state->m_mmc_cmd1 = data & 0x03;
9747		fk23c_set_chr(space.machine());
	9611	m_mmc_cmd1 = data & 0x03;
	9612	fk23c_set_chr(machine());
9748	9613	}
9749	9614	}
9750	9615	else
r18063	r18064
9752	9617	switch (offset & 0x6001)
9753	9618	{
9754	9619	case 0x0001:
9755		if ((state->m_mmc_reg[3] & 0x02) && (state->m_mmc3_latch & 0x08))
	9620	if ((m_mmc_reg[3] & 0x02) && (m_mmc3_latch & 0x08))
9756	9621	{
9757		state->m_mmc_reg[4 | (state->m_mmc3_latch & 0x03)] = data;
9758		fk23c_set_prg(space.machine());
9759		fk23c_set_chr(space.machine());
	9622	m_mmc_reg[4 | (m_mmc3_latch & 0x03)] = data;
	9623	fk23c_set_prg(machine());
	9624	fk23c_set_chr(machine());
9760	9625	}
9761	9626	else
9762	9627	txrom_w(space, offset, data, mem_mask);
9763	9628	break;
9764	9629
9765	9630	case 0x2000:
9766		set_nt_mirroring(space.machine(), data ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	9631	set_nt_mirroring(machine(), data ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
9767	9632	break;
9768	9633
9769	9634	default:
r18063	r18064
9804	9669	prg16_cdef(machine, helper2);
9805	9670	}
9806	9671
9807		static WRITE8_HANDLER( bmc_64in1nr_l_w )
	9672	WRITE8_MEMBER(nes_state::bmc_64in1nr_l_w)
9808	9673	{
9809		nes_state *state = space.machine().driver_data<nes_state>();
9810	9674	LOG_MMC(("bmc_64in1nr_l_w offset: %04x, data: %02x\n", offset, data));
9811	9675	offset += 0x100;
9812	9676
r18063	r18064
9816	9680	case 0x1001:
9817	9681	case 0x1002:
9818	9682	case 0x1003:
9819		state->m_mmc_reg[offset & 0x03] = data;
9820		bmc_64in1nr_set_prg(space.machine());
9821		chr8(space.machine(), ((state->m_mmc_reg[0] >> 1) & 0x03) | (state->m_mmc_reg[2] << 2), CHRROM);
	9683	m_mmc_reg[offset & 0x03] = data;
	9684	bmc_64in1nr_set_prg(machine());
	9685	chr8(machine(), ((m_mmc_reg[0] >> 1) & 0x03) | (m_mmc_reg[2] << 2), CHRROM);
9822	9686	break;
9823	9687	}
9824	9688	if (offset == 0x1000)   /* reg[0] also sets mirroring */
9825		set_nt_mirroring(space.machine(), BIT(data, 5) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	9689	set_nt_mirroring(machine(), BIT(data, 5) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
9826	9690	}
9827	9691
9828		static WRITE8_HANDLER( bmc_64in1nr_w )
	9692	WRITE8_MEMBER(nes_state::bmc_64in1nr_w)
9829	9693	{
9830		nes_state *state = space.machine().driver_data<nes_state>();
9831	9694	LOG_MMC(("bmc_64in1nr_w offset: %04x, data: %02x\n", offset, data));
9832	9695
9833		state->m_mmc_reg[3] = data;   // reg[3] is currently unused?!?
	9696	m_mmc_reg[3] = data;   // reg[3] is currently unused?!?
9834	9697	}
9835	9698
9836	9699	/*************************************************************
r18063	r18064
9843	9706
9844	9707	*************************************************************/
9845	9708
9846		static WRITE8_HANDLER( bmc_190in1_w )
	9709	WRITE8_MEMBER(nes_state::bmc_190in1_w)
9847	9710	{
9848	9711	LOG_MMC(("bmc_190in1_w offset: %04x, data: %02x\n", offset, data));
9849	9712
9850		set_nt_mirroring(space.machine(), BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	9713	set_nt_mirroring(machine(), BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
9851	9714	offset >>= 2;
9852		prg16_89ab(space.machine(), offset);
9853		prg16_cdef(space.machine(), offset);
9854		chr8(space.machine(), offset, CHRROM);
	9715	prg16_89ab(machine(), offset);
	9716	prg16_cdef(machine(), offset);
	9717	chr8(machine(), offset, CHRROM);
9855	9718	}
9856	9719
9857	9720	/*************************************************************
r18063	r18064
9864	9727
9865	9728	*************************************************************/
9866	9729
9867		static WRITE8_HANDLER( bmc_a65as_w )
	9730	WRITE8_MEMBER(nes_state::bmc_a65as_w)
9868	9731	{
9869	9732	UINT8 helper = (data & 0x30) >> 1;
9870	9733	LOG_MMC(("bmc_a65as_w offset: %04x, data: %02x\n", offset, data));
9871	9734
9872	9735	if (data & 0x80)
9873		set_nt_mirroring(space.machine(), BIT(data, 5) ? PPU_MIRROR_HIGH : PPU_MIRROR_LOW);
	9736	set_nt_mirroring(machine(), BIT(data, 5) ? PPU_MIRROR_HIGH : PPU_MIRROR_LOW);
9874	9737	else
9875		set_nt_mirroring(space.machine(), BIT(data, 3) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	9738	set_nt_mirroring(machine(), BIT(data, 3) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
9876	9739
9877	9740	if (data & 0x40)
9878		prg32(space.machine(), data >> 1);
	9741	prg32(machine(), data >> 1);
9879	9742	else
9880	9743	{
9881		prg16_89ab(space.machine(), helper | (data & 0x07));
9882		prg16_cdef(space.machine(), helper | 0x07);
	9744	prg16_89ab(machine(), helper | (data & 0x07));
	9745	prg16_cdef(machine(), helper | 0x07);
9883	9746	}
9884	9747	}
9885	9748
r18063	r18064
9894	9757
9895	9758	*************************************************************/
9896	9759
9897		static WRITE8_HANDLER( bmc_gs2004_w )
	9760	WRITE8_MEMBER(nes_state::bmc_gs2004_w)
9898	9761	{
9899	9762	LOG_MMC(("bmc_gs2004_w offset: %04x, data: %02x\n", offset, data));
9900	9763
9901		prg32(space.machine(), data);
	9764	prg32(machine(), data);
9902	9765	}
9903	9766
9904	9767	/*************************************************************
r18063	r18064
9912	9775
9913	9776	*************************************************************/
9914	9777
9915		static WRITE8_HANDLER( bmc_gs2013_w )
	9778	WRITE8_MEMBER(nes_state::bmc_gs2013_w)
9916	9779	{
9917	9780	LOG_MMC(("bmc_gs2013_w offset: %04x, data: %02x\n", offset, data));
9918	9781
9919	9782	if (data & 0x08)
9920		prg32(space.machine(), data & 0x09);
	9783	prg32(machine(), data & 0x09);
9921	9784	else
9922		prg32(space.machine(), data & 0x07);
	9785	prg32(machine(), data & 0x07);
9923	9786	}
9924	9787
9925	9788	/*************************************************************
r18063	r18064
9952	9815	chr1_x(machine, start, chr_base | bank, chr);
9953	9816	}
9954	9817
9955		static WRITE8_HANDLER( bmc_s24in1sc03_l_w )
	9818	WRITE8_MEMBER(nes_state::bmc_s24in1sc03_l_w)
9956	9819	{
9957		nes_state *state = space.machine().driver_data<nes_state>();
9958	9820	LOG_MMC(("bmc_s24in1sc03_l_w offset: %04x, data: %02x\n", offset, data));
9959	9821	offset += 0x100;
9960	9822
9961	9823	if (offset == 0x1ff0)
9962	9824	{
9963		state->m_mmc_reg[0] = data;
9964		mmc3_set_chr(space.machine(), state->m_mmc_chr_source, state->m_mmc_chr_base, state->m_mmc_chr_mask);
9965		mmc3_set_prg(space.machine(), state->m_mmc_prg_base, state->m_mmc_prg_mask);
	9825	m_mmc_reg[0] = data;
	9826	mmc3_set_chr(machine(), m_mmc_chr_source, m_mmc_chr_base, m_mmc_chr_mask);
	9827	mmc3_set_prg(machine(), m_mmc_prg_base, m_mmc_prg_mask);
9966	9828	}
9967	9829
9968	9830	if (offset == 0x1ff1)
9969	9831	{
9970		state->m_mmc_reg[1] = data;
9971		mmc3_set_prg(space.machine(), state->m_mmc_prg_base, state->m_mmc_prg_mask);
	9832	m_mmc_reg[1] = data;
	9833	mmc3_set_prg(machine(), m_mmc_prg_base, m_mmc_prg_mask);
9972	9834	}
9973	9835
9974	9836	if (offset == 0x1ff2)
9975	9837	{
9976		state->m_mmc_reg[2] = data;
9977		mmc3_set_chr(space.machine(), state->m_mmc_chr_source, state->m_mmc_chr_base, state->m_mmc_chr_mask);
	9838	m_mmc_reg[2] = data;
	9839	mmc3_set_chr(machine(), m_mmc_chr_source, m_mmc_chr_base, m_mmc_chr_mask);
9978	9840	}
9979	9841	}
9980	9842
r18063	r18064
9988	9850
9989	9851	*************************************************************/
9990	9852
9991		static WRITE8_HANDLER( bmc_t262_w )
	9853	WRITE8_MEMBER(nes_state::bmc_t262_w)
9992	9854	{
9993		nes_state *state = space.machine().driver_data<nes_state>();
9994	9855	UINT8 mmc_helper;
9995	9856	LOG_MMC(("bmc_t262_w offset: %04x, data: %02x\n", offset, data));
9996	9857
9997		if (state->m_mmc_latch2 || offset == 0)
	9858	if (m_mmc_latch2 || offset == 0)
9998	9859	{
9999		state->m_mmc_latch1 = (state->m_mmc_latch1 & 0x38) | (data & 0x07);
10000		prg16_89ab(space.machine(), state->m_mmc_latch1);
	9860	m_mmc_latch1 = (m_mmc_latch1 & 0x38) | (data & 0x07);
	9861	prg16_89ab(machine(), m_mmc_latch1);
10001	9862	}
10002	9863	else
10003	9864	{
10004		state->m_mmc_latch2 = 1;
10005		set_nt_mirroring(space.machine(), BIT(data, 1) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	9865	m_mmc_latch2 = 1;
	9866	set_nt_mirroring(machine(), BIT(data, 1) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
10006	9867	mmc_helper = ((offset >> 3) & 0x20) | ((offset >> 2) & 0x18);
10007		state->m_mmc_latch1 = mmc_helper | (state->m_mmc_latch1 & 0x07);
10008		prg16_89ab(space.machine(), state->m_mmc_latch1);
10009		prg16_cdef(space.machine(), mmc_helper | 0x07);
	9868	m_mmc_latch1 = mmc_helper | (m_mmc_latch1 & 0x07);
	9869	prg16_89ab(machine(), m_mmc_latch1);
	9870	prg16_cdef(machine(), mmc_helper | 0x07);
10010	9871	}
10011	9872	}
10012	9873
r18063	r18064
10021	9882
10022	9883	*************************************************************/
10023	9884
10024		static WRITE8_HANDLER( bmc_ws_m_w )
	9885	WRITE8_MEMBER(nes_state::bmc_ws_m_w)
10025	9886	{
10026		nes_state *state = space.machine().driver_data<nes_state>();
10027	9887	UINT8 mmc_helper;
10028	9888	LOG_MMC(("bmc_ws_m_w offset: %04x, data: %02x\n", offset, data));
10029	9889
r18063	r18064
10032	9892	switch (offset & 0x01)
10033	9893	{
10034	9894	case 0:
10035		if (!state->m_mmc_latch1)
	9895	if (!m_mmc_latch1)
10036	9896	{
10037		state->m_mmc_latch1 = data & 0x20;
10038		set_nt_mirroring(space.machine(), BIT(data, 4) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	9897	m_mmc_latch1 = data & 0x20;
	9898	set_nt_mirroring(machine(), BIT(data, 4) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
10039	9899	mmc_helper = (~data & 0x08) >> 3;
10040		prg16_89ab(space.machine(), data & ~mmc_helper);
10041		prg16_cdef(space.machine(), data |  mmc_helper);
	9900	prg16_89ab(machine(), data & ~mmc_helper);
	9901	prg16_cdef(machine(), data |  mmc_helper);
10042	9902	}
10043	9903	break;
10044	9904	case 1:
10045		if (!state->m_mmc_latch1)
	9905	if (!m_mmc_latch1)
10046	9906	{
10047		chr8(space.machine(), data, CHRROM);
	9907	chr8(machine(), data, CHRROM);
10048	9908	}
10049	9909	break;
10050	9910	}
r18063	r18064
10068	9928	*************************************************************/
10069	9929
10070	9930	// Are this correct or should they work the same?
10071		static WRITE8_HANDLER( novel1_w )
	9931	WRITE8_MEMBER(nes_state::novel1_w)
10072	9932	{
10073	9933	LOG_MMC(("novel1_w, offset: %04x, data: %02x\n", offset, data));
10074	9934
10075		prg32(space.machine(), offset & 0x03);
10076		chr8(space.machine(), offset & 0x07, CHRROM);
	9935	prg32(machine(), offset & 0x03);
	9936	chr8(machine(), offset & 0x07, CHRROM);
10077	9937	}
10078	9938
10079		static WRITE8_HANDLER( novel2_w )
	9939	WRITE8_MEMBER(nes_state::novel2_w)
10080	9940	{
10081	9941	LOG_MMC(("novel2_w, offset: %04x, data: %02x\n", offset, data));
10082	9942
10083		prg32(space.machine(), offset >> 1);
10084		chr8(space.machine(), offset >> 3, CHRROM);
	9943	prg32(machine(), offset >> 1);
	9944	chr8(machine(), offset >> 3, CHRROM);
10085	9945	}
10086	9946
10087	9947	/*************************************************************
r18063	r18064
10097	9957
10098	9958	*************************************************************/
10099	9959
10100		static WRITE8_HANDLER( bmc_gka_w )
	9960	WRITE8_MEMBER(nes_state::bmc_gka_w)
10101	9961	{
10102		nes_state *state = space.machine().driver_data<nes_state>();
10103	9962	LOG_MMC(("bmc_gka_w, offset: %04x, data: %02x\n", offset, data));
10104	9963
10105	9964	if (offset & 0x0800)
10106		state->m_mmc_latch2 = data;
	9965	m_mmc_latch2 = data;
10107	9966	else
10108		state->m_mmc_latch1 = data;
	9967	m_mmc_latch1 = data;
10109	9968
10110		if (state->m_mmc_latch2 & 0x80)
10111		prg32(space.machine(), 2 | (state->m_mmc_latch2 >> 6));
	9969	if (m_mmc_latch2 & 0x80)
	9970	prg32(machine(), 2 | (m_mmc_latch2 >> 6));
10112	9971	else
10113	9972	{
10114		prg16_89ab(space.machine(), (state->m_mmc_latch2 >> 5) & 0x03);
10115		prg16_cdef(space.machine(), (state->m_mmc_latch2 >> 5) & 0x03);
	9973	prg16_89ab(machine(), (m_mmc_latch2 >> 5) & 0x03);
	9974	prg16_cdef(machine(), (m_mmc_latch2 >> 5) & 0x03);
10116	9975	}
10117	9976
10118		set_nt_mirroring(space.machine(), (state->m_mmc_latch2 & 0x08) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	9977	set_nt_mirroring(machine(), (m_mmc_latch2 & 0x08) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
10119	9978
10120		chr8(space.machine(), (state->m_mmc_latch1 & 0x03) | (state->m_mmc_latch2 & 0x07) | ((state->m_mmc_latch2 & 0x10) >> 1), CHRROM);
	9979	chr8(machine(), (m_mmc_latch1 & 0x03) | (m_mmc_latch2 & 0x07) | ((m_mmc_latch2 & 0x10) >> 1), CHRROM);
10121	9980	}
10122	9981
10123	9982
r18063	r18064
10134	9993
10135	9994	*************************************************************/
10136	9995
10137		static WRITE8_HANDLER( sng32_w )
	9996	WRITE8_MEMBER(nes_state::sng32_w)
10138	9997	{
10139	9998	LOG_MMC(("sng32_w, offset: %04x, data: %02x\n", offset, data));
10140		prg32(space.machine(), data);
	9999	prg32(machine(), data);
10141	10000	}
10142	10001
10143	10002	/*************************************************************
r18063	r18064
10153	10012
10154	10013	*************************************************************/
10155	10014
10156		static WRITE8_HANDLER( bmc_gkb_w )
	10015	WRITE8_MEMBER(nes_state::bmc_gkb_w)
10157	10016	{
10158		nes_state *state = space.machine().driver_data<nes_state>();
10159	10017	UINT8 bank = (offset & 0x40) ? 0 : 1;
10160	10018	LOG_MMC(("bmc_gkb_w, offset: %04x, data: %02x\n", offset, data));
10161	10019
10162		prg16_89ab(space.machine(), offset & ~bank);
10163		prg16_cdef(space.machine(), offset | bank);
10164		chr8(space.machine(), offset >> 3, state->m_mmc_chr_source);
10165		set_nt_mirroring(space.machine(), BIT(data, 7) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	10020	prg16_89ab(machine(), offset & ~bank);
	10021	prg16_cdef(machine(), offset | bank);
	10022	chr8(machine(), offset >> 3, m_mmc_chr_source);
	10023	set_nt_mirroring(machine(), BIT(data, 7) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
10166	10024	}
10167	10025
10168	10026	/*************************************************************
r18063	r18064
10178	10036
10179	10037	*************************************************************/
10180	10038
10181		static WRITE8_HANDLER( bmc_super700in1_w )
	10039	WRITE8_MEMBER(nes_state::bmc_super700in1_w)
10182	10040	{
10183	10041	LOG_MMC(("bmc_super700in1_w, offset :%04x, data: %02x\n", offset, data));
10184	10042
10185		chr8(space.machine(), ((offset & 0x1f) << 2) | (data & 0x03), CHRROM);
	10043	chr8(machine(), ((offset & 0x1f) << 2) | (data & 0x03), CHRROM);
10186	10044
10187	10045	if (offset & 0x20)
10188	10046	{
10189		prg16_89ab(space.machine(), (offset & 0x40) | ((offset >> 8) & 0x3f));
10190		prg16_cdef(space.machine(), (offset & 0x40) | ((offset >> 8) & 0x3f));
	10047	prg16_89ab(machine(), (offset & 0x40) | ((offset >> 8) & 0x3f));
	10048	prg16_cdef(machine(), (offset & 0x40) | ((offset >> 8) & 0x3f));
10191	10049	}
10192	10050	else
10193	10051	{
10194		prg32(space.machine(), ((offset & 0x40) | ((offset >> 8) & 0x3f)) >> 1);
	10052	prg32(machine(), ((offset & 0x40) | ((offset >> 8) & 0x3f)) >> 1);
10195	10053	}
10196	10054
10197		set_nt_mirroring(space.machine(), BIT(data, 7) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	10055	set_nt_mirroring(machine(), BIT(data, 7) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
10198	10056	}
10199	10057
10200	10058	/*************************************************************
r18063	r18064
10210	10068
10211	10069	*************************************************************/
10212	10070
10213		static WRITE8_HANDLER( bmc_36in1_w )
	10071	WRITE8_MEMBER(nes_state::bmc_36in1_w)
10214	10072	{
10215	10073	LOG_MMC(("bmc_36in1_w, offset: %04x, data: %02x\n", offset, data));
10216	10074
10217		prg16_89ab(space.machine(), offset & 0x07);
10218		prg16_cdef(space.machine(), offset & 0x07);
10219		chr8(space.machine(), offset & 0x07, CHRROM);
	10075	prg16_89ab(machine(), offset & 0x07);
	10076	prg16_cdef(machine(), offset & 0x07);
	10077	chr8(machine(), offset & 0x07, CHRROM);
10220	10078
10221		set_nt_mirroring(space.machine(), BIT(data, 3) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	10079	set_nt_mirroring(machine(), BIT(data, 3) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
10222	10080	}
10223	10081
10224	10082	/*************************************************************
r18063	r18064
10234	10092
10235	10093	*************************************************************/
10236	10094
10237		static WRITE8_HANDLER( bmc_21in1_w )
	10095	WRITE8_MEMBER(nes_state::bmc_21in1_w)
10238	10096	{
10239	10097	LOG_MMC(("bmc_21in1_w, offset: %04x, data: %02x\n", offset, data));
10240	10098
10241		prg32(space.machine(), offset & 0x03);
10242		chr8(space.machine(), offset & 0x03, CHRROM);
	10099	prg32(machine(), offset & 0x03);
	10100	chr8(machine(), offset & 0x03, CHRROM);
10243	10101	}
10244	10102
10245	10103	/*************************************************************
r18063	r18064
10255	10113
10256	10114	*************************************************************/
10257	10115
10258		static WRITE8_HANDLER( bmc_150in1_w )
	10116	WRITE8_MEMBER(nes_state::bmc_150in1_w)
10259	10117	{
10260	10118	int bank = (offset >> 1) & 0x07;
10261	10119
10262	10120	LOG_MMC(("bmc_150in1_w, offset: %04x, data: %02x\n", offset, data));
10263	10121
10264		prg16_89ab(space.machine(), bank);
10265		prg16_cdef(space.machine(), bank + (((bank & 0x06) == 0x06) ? 1 : 0));
10266		chr8(space.machine(), bank, CHRROM);
	10122	prg16_89ab(machine(), bank);
	10123	prg16_cdef(machine(), bank + (((bank & 0x06) == 0x06) ? 1 : 0));
	10124	chr8(machine(), bank, CHRROM);
10267	10125
10268		set_nt_mirroring(space.machine(), BIT(data, 0) ? PPU_MIRROR_HORZ: PPU_MIRROR_VERT);
	10126	set_nt_mirroring(machine(), BIT(data, 0) ? PPU_MIRROR_HORZ: PPU_MIRROR_VERT);
10269	10127	}
10270	10128
10271	10129	/*************************************************************
r18063	r18064
10281	10139
10282	10140	*************************************************************/
10283	10141
10284		static WRITE8_HANDLER( bmc_35in1_w )
	10142	WRITE8_MEMBER(nes_state::bmc_35in1_w)
10285	10143	{
10286	10144	LOG_MMC(("bmc_35in1_w, offset: %04x, data: %02x\n", offset, data));
10287	10145
10288		prg16_89ab(space.machine(), (data >> 2) & 0x03);
10289		prg16_cdef(space.machine(), (data >> 2) & 0x03);
10290		chr8(space.machine(), data & 0x03, CHRROM);
	10146	prg16_89ab(machine(), (data >> 2) & 0x03);
	10147	prg16_cdef(machine(), (data >> 2) & 0x03);
	10148	chr8(machine(), data & 0x03, CHRROM);
10291	10149	}
10292	10150
10293	10151	/*************************************************************
r18063	r18064
10303	10161
10304	10162	*************************************************************/
10305	10163
10306		static WRITE8_HANDLER( bmc_64in1_w )
	10164	WRITE8_MEMBER(nes_state::bmc_64in1_w)
10307	10165	{
10308	10166	int bank = (offset >> 1) & (offset >> 2) & 0x01;
10309	10167
10310	10168	LOG_MMC(("bmc_64in1_w, offset: %04x, data: %02x\n", offset, data));
10311	10169
10312		prg16_89ab(space.machine(), offset & ~bank);
10313		prg16_cdef(space.machine(), offset | bank);
10314		chr8(space.machine(), offset & ~bank, CHRROM);
	10170	prg16_89ab(machine(), offset & ~bank);
	10171	prg16_cdef(machine(), offset | bank);
	10172	chr8(machine(), offset & ~bank, CHRROM);
10315	10173
10316		set_nt_mirroring(space.machine(), BIT(data, 4) ? PPU_MIRROR_HORZ: PPU_MIRROR_VERT);
	10174	set_nt_mirroring(machine(), BIT(data, 4) ? PPU_MIRROR_HORZ: PPU_MIRROR_VERT);
10317	10175	}
10318	10176
10319	10177	/*************************************************************
r18063	r18064
10329	10187
10330	10188	*************************************************************/
10331	10189
10332		static WRITE8_HANDLER( bmc_15in1_m_w )
	10190	WRITE8_MEMBER(nes_state::bmc_15in1_m_w)
10333	10191	{
10334		nes_state *state = space.machine().driver_data<nes_state>();
10335	10192	LOG_MMC(("bmc_15in1_m_w, offset: %04x, data: %02x\n", offset, data));
10336	10193
10337	10194	if (offset & 0x0800)
10338	10195	{
10339		state->m_mmc_prg_base = (data & 0x03) << 4;
10340		state->m_mmc_prg_mask = (data & 0x02) ? 0x0f : 0x1f;
10341		state->m_mmc_chr_base = (data & 0x03) << 7;
10342		state->m_mmc_chr_mask = (data & 0x02) ? 0x7f : 0xff;
10343		mmc3_set_prg(space.machine(), state->m_mmc_prg_base, state->m_mmc_prg_mask);
10344		mmc3_set_chr(space.machine(), state->m_mmc_chr_source, state->m_mmc_chr_base, state->m_mmc_chr_mask);
	10196	m_mmc_prg_base = (data & 0x03) << 4;
	10197	m_mmc_prg_mask = (data & 0x02) ? 0x0f : 0x1f;
	10198	m_mmc_chr_base = (data & 0x03) << 7;
	10199	m_mmc_chr_mask = (data & 0x02) ? 0x7f : 0xff;
	10200	mmc3_set_prg(machine(), m_mmc_prg_base, m_mmc_prg_mask);
	10201	mmc3_set_chr(machine(), m_mmc_chr_source, m_mmc_chr_base, m_mmc_chr_mask);
10345	10202	}
10346	10203	}
10347	10204
r18063	r18064
10358	10215
10359	10216	*************************************************************/
10360	10217
10361		static WRITE8_HANDLER( bmc_hik300_w )
	10218	WRITE8_MEMBER(nes_state::bmc_hik300_w)
10362	10219	{
10363	10220	LOG_MMC(("bmc_hik300_w, offset: %04x, data: %02x\n", offset, data));
10364	10221
10365		set_nt_mirroring(space.machine(), BIT(data, 3) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
10366		chr8(space.machine(), offset, CHRROM);
	10222	set_nt_mirroring(machine(), BIT(data, 3) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	10223	chr8(machine(), offset, CHRROM);
10367	10224
10368	10225	if (offset < 0x4000)
10369	10226	{
10370		prg16_89ab(space.machine(), offset);
10371		prg16_cdef(space.machine(), offset);
	10227	prg16_89ab(machine(), offset);
	10228	prg16_cdef(machine(), offset);
10372	10229	}
10373	10230	else
10374		prg32(space.machine(), offset >> 1);
	10231	prg32(machine(), offset >> 1);
10375	10232	}
10376	10233
10377	10234	/*************************************************************
r18063	r18064
10387	10244
10388	10245	*************************************************************/
10389	10246
10390		static WRITE8_HANDLER( supergun20in1_w )
	10247	WRITE8_MEMBER(nes_state::supergun20in1_w)
10391	10248	{
10392	10249	LOG_MMC(("supergun20in1_w, offset: %04x, data: %02x\n", offset, data));
10393	10250
10394		prg16_89ab(space.machine(), offset >> 2);
10395		prg16_cdef(space.machine(), offset >> 2);
10396		chr8(space.machine(), offset, CHRROM);
	10251	prg16_89ab(machine(), offset >> 2);
	10252	prg16_cdef(machine(), offset >> 2);
	10253	chr8(machine(), offset, CHRROM);
10397	10254	}
10398	10255
10399	10256	/*************************************************************
r18063	r18064
10409	10266
10410	10267	*************************************************************/
10411	10268
10412		static WRITE8_HANDLER( bmc_72in1_w )
	10269	WRITE8_MEMBER(nes_state::bmc_72in1_w)
10413	10270	{
10414	10271	int hi_bank;
10415	10272	int size_16;
r18063	r18064
10417	10274
10418	10275	LOG_MMC(("bmc_72in1_w, offset: %04x, data: %02x\n", offset, data));
10419	10276
10420		chr8(space.machine(), offset, CHRROM);
10421		set_nt_mirroring(space.machine(), (offset & 0x2000) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	10277	chr8(machine(), offset, CHRROM);
	10278	set_nt_mirroring(machine(), (offset & 0x2000) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
10422	10279
10423	10280	hi_bank = offset & 0x40;
10424	10281	size_16 = offset & 0x1000;
r18063	r18064
10429	10286	if (hi_bank)
10430	10287	bank ++;
10431	10288
10432		prg16_89ab(space.machine(), bank);
10433		prg16_cdef(space.machine(), bank);
	10289	prg16_89ab(machine(), bank);
	10290	prg16_cdef(machine(), bank);
10434	10291	}
10435	10292	else
10436		prg32(space.machine(), bank);
	10293	prg32(machine(), bank);
10437	10294	}
10438	10295
10439	10296	/*************************************************************
r18063	r18064
10450	10307	*************************************************************/
10451	10308
10452	10309	// does this work for super42in1 as well?!?
10453		static WRITE8_HANDLER( bmc_76in1_w )
	10310	WRITE8_MEMBER(nes_state::bmc_76in1_w)
10454	10311	{
10455		nes_state *state = space.machine().driver_data<nes_state>();
10456	10312	int hi_bank;
10457	10313	int size_16;
10458	10314	int bank;
r18063	r18064
10460	10316	LOG_MMC(("bmc_76in1_w, offset: %04x, data: %02x\n", offset, data));
10461	10317
10462	10318	if (offset & 0x01)
10463		state->m_mmc_latch2 = data;
	10319	m_mmc_latch2 = data;
10464	10320	else
10465		state->m_mmc_latch1 = data;
	10321	m_mmc_latch1 = data;
10466	10322
10467		set_nt_mirroring(space.machine(), BIT(state->m_mmc_latch1, 6) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	10323	set_nt_mirroring(machine(), BIT(m_mmc_latch1, 6) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
10468	10324
10469		hi_bank = state->m_mmc_latch1 & 0x01;
10470		size_16 = state->m_mmc_latch1 & 0x20;
10471		bank = ((state->m_mmc_latch1 & 0x1e) >> 1) | ((state->m_mmc_latch1 & 0x80) >> 3) | ((state->m_mmc_latch2 & 0x01) << 5);
	10325	hi_bank = m_mmc_latch1 & 0x01;
	10326	size_16 = m_mmc_latch1 & 0x20;
	10327	bank = ((m_mmc_latch1 & 0x1e) >> 1) | ((m_mmc_latch1 & 0x80) >> 3) | ((m_mmc_latch2 & 0x01) << 5);
10472	10328
10473	10329	if (size_16)
10474	10330	{
r18063	r18064
10476	10332	if (hi_bank)
10477	10333	bank ++;
10478	10334
10479		prg16_89ab(space.machine(), bank);
10480		prg16_cdef(space.machine(), bank);
	10335	prg16_89ab(machine(), bank);
	10336	prg16_cdef(machine(), bank);
10481	10337	}
10482	10338	else
10483		prg32(space.machine(), bank);
	10339	prg32(machine(), bank);
10484	10340	}
10485	10341
10486	10342	/*************************************************************
r18063	r18064
10496	10352
10497	10353	*************************************************************/
10498	10354
10499		static WRITE8_HANDLER( bmc_1200in1_w )
	10355	WRITE8_MEMBER(nes_state::bmc_1200in1_w)
10500	10356	{
10501	10357	int hi_bank;
10502	10358	int size_32;
r18063	r18064
10513	10369	if (hi_bank)
10514	10370	bank ++;
10515	10371
10516		prg16_89ab(space.machine(), bank);
10517		prg16_cdef(space.machine(), bank);
	10372	prg16_89ab(machine(), bank);
	10373	prg16_cdef(machine(), bank);
10518	10374	}
10519	10375	else
10520		prg32(space.machine(), bank);
	10376	prg32(machine(), bank);
10521	10377
10522	10378	if (!(offset & 0x80))
10523	10379	{
10524	10380	if (offset & 0x200)
10525		prg16_cdef(space.machine(), ((bank << 1) & 0x38) + 7);
	10381	prg16_cdef(machine(), ((bank << 1) & 0x38) + 7);
10526	10382	else
10527		prg16_cdef(space.machine(), ((bank << 1) & 0x38));
	10383	prg16_cdef(machine(), ((bank << 1) & 0x38));
10528	10384	}
10529	10385
10530		set_nt_mirroring(space.machine(), BIT(data, 1) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	10386	set_nt_mirroring(machine(), BIT(data, 1) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
10531	10387	}
10532	10388
10533	10389	/*************************************************************
r18063	r18064
10543	10399
10544	10400	*************************************************************/
10545	10401
10546		static WRITE8_HANDLER( bmc_31in1_w )
	10402	WRITE8_MEMBER(nes_state::bmc_31in1_w)
10547	10403	{
10548	10404	LOG_MMC(("bmc_31in1_w, offset: %04x, data: %02x\n", offset, data));
10549	10405
10550		set_nt_mirroring(space.machine(), BIT(data, 5) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
10551		chr8(space.machine(), offset, CHRROM);
	10406	set_nt_mirroring(machine(), BIT(data, 5) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	10407	chr8(machine(), offset, CHRROM);
10552	10408
10553	10409	if ((offset & 0x1e) == 0)
10554	10410	{
10555		prg16_89ab(space.machine(), 0);
10556		prg16_89ab(space.machine(), 1);
	10411	prg16_89ab(machine(), 0);
	10412	prg16_89ab(machine(), 1);
10557	10413	}
10558	10414	else
10559	10415	{
10560		prg16_89ab(space.machine(), offset & 0x1f);
10561		prg16_89ab(space.machine(), offset & 0x1f);
	10416	prg16_89ab(machine(), offset & 0x1f);
	10417	prg16_89ab(machine(), offset & 0x1f);
10562	10418	}
10563	10419	}
10564	10420
r18063	r18064
10576	10432
10577	10433	*************************************************************/
10578	10434
10579		static WRITE8_HANDLER( bmc_22g_w )
	10435	WRITE8_MEMBER(nes_state::bmc_22g_w)
10580	10436	{
10581	10437	LOG_MMC(("bmc_22g_w, offset: %04x, data: %02x\n", offset, data));
10582	10438
10583	10439	if (1)   // this should flip at reset
10584	10440	{
10585		prg16_89ab(space.machine(), data & 0x07);
	10441	prg16_89ab(machine(), data & 0x07);
10586	10442	}
10587	10443	else
10588	10444	{
10589	10445	if (data & 0x20)
10590	10446	{
10591		prg16_89ab(space.machine(), (data & 0x1f) + 8);
10592		prg16_cdef(space.machine(), (data & 0x1f) + 8);
	10447	prg16_89ab(machine(), (data & 0x1f) + 8);
	10448	prg16_cdef(machine(), (data & 0x1f) + 8);
10593	10449	}
10594	10450	else
10595	10451	{
10596		prg16_89ab(space.machine(), (data & 0x1f) + 8);
10597		prg16_cdef(space.machine(), (data & 0x1f) + 9);
	10452	prg16_89ab(machine(), (data & 0x1f) + 8);
	10453	prg16_cdef(machine(), (data & 0x1f) + 9);
10598	10454	}
10599		set_nt_mirroring(space.machine(), BIT(data, 6) ? PPU_MIRROR_VERT : PPU_MIRROR_HORZ);
	10455	set_nt_mirroring(machine(), BIT(data, 6) ? PPU_MIRROR_VERT : PPU_MIRROR_HORZ);
10600	10456	}
10601	10457	}
10602	10458
r18063	r18064
10613	10469
10614	10470	*************************************************************/
10615	10471
10616		static WRITE8_HANDLER( bmc_20in1_w )
	10472	WRITE8_MEMBER(nes_state::bmc_20in1_w)
10617	10473	{
10618	10474	LOG_MMC(("bmc_20in1_w, offset: %04x, data: %02x\n", offset, data));
10619	10475
10620		set_nt_mirroring(space.machine(), BIT(data, 7) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	10476	set_nt_mirroring(machine(), BIT(data, 7) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
10621	10477
10622		prg16_89ab(space.machine(), (offset & 0x1e));
10623		prg16_cdef(space.machine(), (offset & 0x1e) | ((offset & 0x20) ? 1 : 0));
	10478	prg16_89ab(machine(), (offset & 0x1e));
	10479	prg16_cdef(machine(), (offset & 0x1e) | ((offset & 0x20) ? 1 : 0));
10624	10480	}
10625	10481
10626	10482	/*************************************************************
r18063	r18064
10636	10492
10637	10493	*************************************************************/
10638	10494
10639		static WRITE8_HANDLER( bmc_110in1_w )
	10495	WRITE8_MEMBER(nes_state::bmc_110in1_w)
10640	10496	{
10641	10497	UINT8 map255_helper1 = (offset >> 12) ? 0 : 1;
10642	10498	UINT8 map255_helper2 = ((offset >> 8) & 0x40) | ((offset >> 6) & 0x3f);
10643	10499
10644	10500	LOG_MMC(("bmc_110in1_w, offset: %04x, data: %02x\n", offset, data));
10645	10501
10646		set_nt_mirroring(space.machine(), (offset & 0x2000) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
10647		prg16_89ab(space.machine(), map255_helper1 & ~map255_helper2);
10648		prg16_cdef(space.machine(), map255_helper1 | map255_helper2);
10649		chr8(space.machine(), ((offset >> 8) & 0x40) | (offset & 0x3f), CHRROM);
	10502	set_nt_mirroring(machine(), (offset & 0x2000) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	10503	prg16_89ab(machine(), map255_helper1 & ~map255_helper2);
	10504	prg16_cdef(machine(), map255_helper1 | map255_helper2);
	10505	chr8(machine(), ((offset >> 8) & 0x40) | (offset & 0x3f), CHRROM);
10650	10506	}
10651	10507
10652	10508	/*************************************************************
r18063	r18064
10662	10518
10663	10519	*************************************************************/
10664	10520
10665		static WRITE8_HANDLER( bmc_sbig7_w )
	10521	WRITE8_MEMBER(nes_state::bmc_sbig7_w)
10666	10522	{
10667		nes_state *state = space.machine().driver_data<nes_state>();
10668	10523	UINT8 page;
10669	10524	LOG_MMC(("bmc_sbig7_w, offset: %04x, data: %02x\n", offset, data));
10670	10525
r18063	r18064
10675	10530	if (page > 6)
10676	10531	page = 6;
10677	10532
10678		state->m_mmc_prg_base = page << 4;
10679		state->m_mmc_prg_mask = (page > 5) ? 0x1f : 0x0f;
10680		state->m_mmc_chr_base = page << 7;
10681		state->m_mmc_chr_mask = (page > 5) ? 0xff : 0x7f;
10682		mmc3_set_prg(space.machine(), state->m_mmc_prg_base, state->m_mmc_prg_mask);
10683		mmc3_set_chr(space.machine(), state->m_mmc_chr_source, state->m_mmc_chr_base, state->m_mmc_chr_mask);
	10533	m_mmc_prg_base = page << 4;
	10534	m_mmc_prg_mask = (page > 5) ? 0x1f : 0x0f;
	10535	m_mmc_chr_base = page << 7;
	10536	m_mmc_chr_mask = (page > 5) ? 0xff : 0x7f;
	10537	mmc3_set_prg(machine(), m_mmc_prg_base, m_mmc_prg_mask);
	10538	mmc3_set_chr(machine(), m_mmc_chr_source, m_mmc_chr_base, m_mmc_chr_mask);
10684	10539	break;
10685	10540
10686	10541	default:
r18063	r18064
10702	10557
10703	10558	*************************************************************/
10704	10559
10705		static WRITE8_HANDLER( bmc_hik8_m_w )
	10560	WRITE8_MEMBER(nes_state::bmc_hik8_m_w)
10706	10561	{
10707		nes_state *state = space.machine().driver_data<nes_state>();
10708	10562	LOG_MMC(("bmc_hik8_m_w, offset: %04x, data: %02x\n", offset, data));
10709	10563
10710	10564	/* This bit is the "register lock". Once register are locked, writes go to WRAM
10711	10565	and there is no way to unlock them (except by resetting the machine) */
10712		if ((state->m_mmc_reg[3] & 0x40) && state->m_wram != NULL)
10713		state->m_wram[offset] = data;
	10566	if ((m_mmc_reg[3] & 0x40) && m_wram != NULL)
	10567	m_wram[offset] = data;
10714	10568	else
10715	10569	{
10716		state->m_mmc_reg[state->m_mmc_count] = data;
10717		state->m_mmc_count = (state->m_mmc_count + 1) & 0x03;
	10570	m_mmc_reg[m_mmc_count] = data;
	10571	m_mmc_count = (m_mmc_count + 1) & 0x03;
10718	10572
10719		if (!state->m_mmc_count)
	10573	if (!m_mmc_count)
10720	10574	{
10721		LOG_MMC(("bmc_hik8_m_w, command completed %02x %02x %02x %02x\n", state->m_mmc_reg[3],
10722		state->m_mmc_reg[2], state->m_mmc_reg[1], state->m_mmc_reg[0]));
	10575	LOG_MMC(("bmc_hik8_m_w, command completed %02x %02x %02x %02x\n", m_mmc_reg[3],
	10576	m_mmc_reg[2], m_mmc_reg[1], m_mmc_reg[0]));
10723	10577
10724		state->m_mmc_prg_base = state->m_mmc_reg[1];
10725		state->m_mmc_prg_mask = 0x3f ^ (state->m_mmc_reg[3] & 0x3f);
10726		state->m_mmc_chr_base = ((state->m_mmc_reg[2] & 0xf0) << 4) | state->m_mmc_reg[0];
10727		if (BIT(state->m_mmc_reg[2], 3))
10728		state->m_mmc_chr_mask = (1 << ((state->m_mmc_reg[2] & 7) + 1)) - 1;
10729		else if (state->m_mmc_reg[2])
10730		state->m_mmc_chr_mask = 0;
	10578	m_mmc_prg_base = m_mmc_reg[1];
	10579	m_mmc_prg_mask = 0x3f ^ (m_mmc_reg[3] & 0x3f);
	10580	m_mmc_chr_base = ((m_mmc_reg[2] & 0xf0) << 4) | m_mmc_reg[0];
	10581	if (BIT(m_mmc_reg[2], 3))
	10582	m_mmc_chr_mask = (1 << ((m_mmc_reg[2] & 7) + 1)) - 1;
	10583	else if (m_mmc_reg[2])
	10584	m_mmc_chr_mask = 0;
10731	10585	else
10732		state->m_mmc_chr_mask = 0xff;   // i.e. we use the vrom_bank with no masking
	10586	m_mmc_chr_mask = 0xff;   // i.e. we use the vrom_bank with no masking
10733	10587
10734		mmc3_set_prg(space.machine(), state->m_mmc_prg_base, state->m_mmc_prg_mask);
10735		mmc3_set_chr(space.machine(), state->m_mmc_chr_source, state->m_mmc_chr_base, state->m_mmc_chr_mask);
	10588	mmc3_set_prg(machine(), m_mmc_prg_base, m_mmc_prg_mask);
	10589	mmc3_set_chr(machine(), m_mmc_chr_source, m_mmc_chr_base, m_mmc_chr_mask);
10736	10590	}
10737	10591	}
10738	10592	}
r18063	r18064
10750	10604
10751	10605	*************************************************************/
10752	10606
10753		static WRITE8_HANDLER( bmc_hik4in1_m_w )
	10607	WRITE8_MEMBER(nes_state::bmc_hik4in1_m_w)
10754	10608	{
10755		nes_state *state = space.machine().driver_data<nes_state>();
10756	10609	LOG_MMC(("bmc_hik4in1_m_w, offset: %04x, data: %02x\n", offset, data));
10757	10610
10758	10611	/* mid writes only work when WRAM is enabled. not sure if I should
10759		change the condition to state->m_mmc_latch2==0x80 (i.e. what is the effect of
	10612	change the condition to m_mmc_latch2==0x80 (i.e. what is the effect of
10760	10613	the read-only bit?) */
10761		if (state->m_mmc3_wram_protect & 0x80)
	10614	if (m_mmc3_wram_protect & 0x80)
10762	10615	{
10763	10616	if (data & 0x01)   /* if this is 0, then we have 32k PRG blocks */
10764	10617	{
10765		state->m_mmc_prg_base = (data & 0xc0) >> 2;
10766		state->m_mmc_prg_mask = 0x0f;
10767		mmc3_set_prg(space.machine(), state->m_mmc_prg_base, state->m_mmc_prg_mask);
	10618	m_mmc_prg_base = (data & 0xc0) >> 2;
	10619	m_mmc_prg_mask = 0x0f;
	10620	mmc3_set_prg(machine(), m_mmc_prg_base, m_mmc_prg_mask);
10768	10621	}
10769	10622	else
10770		prg32(space.machine(), (data & 0x30) >> 4);
	10623	prg32(machine(), (data & 0x30) >> 4);
10771	10624
10772		state->m_mmc_chr_base = (data & 0xc0) << 1;
10773		state->m_mmc_chr_mask = 0x7f;
10774		mmc3_set_chr(space.machine(), state->m_mmc_chr_source, state->m_mmc_chr_base, state->m_mmc_chr_mask);
	10625	m_mmc_chr_base = (data & 0xc0) << 1;
	10626	m_mmc_chr_mask = 0x7f;
	10627	mmc3_set_chr(machine(), m_mmc_chr_source, m_mmc_chr_base, m_mmc_chr_mask);
10775	10628	}
10776	10629	}
10777	10630
r18063	r18064
10804	10657	}
10805	10658	}
10806	10659
10807		static WRITE8_HANDLER( bmc_ball11_m_w )
	10660	WRITE8_MEMBER(nes_state::bmc_ball11_m_w)
10808	10661	{
10809		nes_state *state = space.machine().driver_data<nes_state>();
10810	10662
10811	10663	LOG_MMC(("bmc_ball11_m_w, offset: %04x, data: %02x\n", offset, data));
10812	10664
10813		state->m_mmc_reg[0] = ((data >> 1) & 0x01) | ((data >> 3) & 0x02);
10814		bmc_ball11_set_banks(space.machine());
	10665	m_mmc_reg[0] = ((data >> 1) & 0x01) | ((data >> 3) & 0x02);
	10666	bmc_ball11_set_banks(machine());
10815	10667	}
10816	10668
10817		static WRITE8_HANDLER( bmc_ball11_w )
	10669	WRITE8_MEMBER(nes_state::bmc_ball11_w)
10818	10670	{
10819		nes_state *state = space.machine().driver_data<nes_state>();
10820	10671
10821	10672	LOG_MMC(("bmc_ball11_w, offset: %04x, data: %02x\n", offset, data));
10822	10673
10823	10674	switch (offset & 0x6000)
10824	10675	{
10825	10676	case 0x4000:   // here we also update reg[0] upper bit
10826		state->m_mmc_reg[0] = (state->m_mmc_reg[0] & 0x01) | ((data >> 3) & 0x02);
	10677	m_mmc_reg[0] = (m_mmc_reg[0] & 0x01) | ((data >> 3) & 0x02);
10827	10678	case 0x0000:
10828	10679	case 0x2000:
10829	10680	case 0x6000:
10830		state->m_mmc_reg[1] = data & 0x0f;
10831		bmc_ball11_set_banks(space.machine());
	10681	m_mmc_reg[1] = data & 0x0f;
	10682	bmc_ball11_set_banks(machine());
10832	10683	break;
10833	10684	}
10834	10685	}
r18063	r18064
10848	10699
10849	10700	*************************************************************/
10850	10701
10851		static WRITE8_HANDLER( bmc_mario7in1_m_w )
	10702	WRITE8_MEMBER(nes_state::bmc_mario7in1_m_w)
10852	10703	{
10853		nes_state *state = space.machine().driver_data<nes_state>();
10854	10704	UINT8 map52_helper1, map52_helper2;
10855	10705	LOG_MMC(("bmc_mario7in1_m_w, offset: %04x, data: %02x\n", offset, data));
10856	10706
10857	10707	/* mid writes only work when WRAM is enabled. not sure if I should
10858		change the condition to state->m_map52_reg_written == 0x80 (i.e. what is the effect of
	10708	change the condition to m_map52_reg_written == 0x80 (i.e. what is the effect of
10859	10709	the read-only bit?) and it only can happen once! */
10860		if ((state->m_mmc3_wram_protect & 0x80) && !state->m_map52_reg_written)
	10710	if ((m_mmc3_wram_protect & 0x80) && !m_map52_reg_written)
10861	10711	{
10862	10712	map52_helper1 = (data & 0x08);
10863	10713	map52_helper2 = (data & 0x40);
10864	10714
10865		state->m_mmc_prg_base = map52_helper1 ? ((data & 0x07) << 4) : ((data & 0x06) << 4);
10866		state->m_mmc_prg_mask = map52_helper1 ? 0x0f : 0x1f;
10867		state->m_mmc_chr_base = ((data & 0x20) << 4) | ((data & 0x04) << 6) | (map52_helper2 ? ((data & 0x10) << 3) : 0);
10868		state->m_mmc_chr_mask = map52_helper2 ? 0x7f : 0xff;
10869		mmc3_set_prg(space.machine(), state->m_mmc_prg_base, state->m_mmc_prg_mask);
10870		mmc3_set_chr(space.machine(), state->m_mmc_chr_source, state->m_mmc_chr_base, state->m_mmc_chr_mask);
	10715	m_mmc_prg_base = map52_helper1 ? ((data & 0x07) << 4) : ((data & 0x06) << 4);
	10716	m_mmc_prg_mask = map52_helper1 ? 0x0f : 0x1f;
	10717	m_mmc_chr_base = ((data & 0x20) << 4) | ((data & 0x04) << 6) | (map52_helper2 ? ((data & 0x10) << 3) : 0);
	10718	m_mmc_chr_mask = map52_helper2 ? 0x7f : 0xff;
	10719	mmc3_set_prg(machine(), m_mmc_prg_base, m_mmc_prg_mask);
	10720	mmc3_set_chr(machine(), m_mmc_chr_source, m_mmc_chr_base, m_mmc_chr_mask);
10871	10721
10872		state->m_map52_reg_written = 1;
	10722	m_map52_reg_written = 1;
10873	10723	}
10874	10724	else
10875		state->m_wram[offset] = data;
	10725	m_wram[offset] = data;
10876	10726	}
10877	10727
10878	10728	/*************************************************************
r18063	r18064
10891	10741
10892	10742	*************************************************************/
10893	10743
10894		static WRITE8_HANDLER( bmc_gold7in1_m_w )
	10744	WRITE8_MEMBER(nes_state::bmc_gold7in1_m_w)
10895	10745	{
10896		nes_state *state = space.machine().driver_data<nes_state>();
10897	10746	UINT8 map52_helper1, map52_helper2;
10898	10747	LOG_MMC(("bmc_gold7in1_m_w, offset: %04x, data: %02x\n", offset, data));
10899	10748
10900		if ((state->m_mmc3_wram_protect & 0x80) && !state->m_map52_reg_written)
	10749	if ((m_mmc3_wram_protect & 0x80) && !m_map52_reg_written)
10901	10750	{
10902	10751	map52_helper1 = (data & 0x08);
10903	10752	map52_helper2 = (data & 0x40);
10904	10753
10905		state->m_mmc_prg_base = map52_helper1 ? ((data & 0x07) << 4) : ((data & 0x06) << 4);
10906		state->m_mmc_prg_mask = map52_helper1 ? 0x0f : 0x1f;
10907		state->m_mmc_chr_base = ((data & 0x20) << 3) | ((data & 0x04) << 7) | (map52_helper2 ? ((data & 0x10) << 3) : 0);
10908		state->m_mmc_chr_mask = map52_helper2 ? 0x7f : 0xff;
10909		mmc3_set_prg(space.machine(), state->m_mmc_prg_base, state->m_mmc_prg_mask);
10910		mmc3_set_chr(space.machine(), state->m_mmc_chr_source, state->m_mmc_chr_base, state->m_mmc_chr_mask);
	10754	m_mmc_prg_base = map52_helper1 ? ((data & 0x07) << 4) : ((data & 0x06) << 4);
	10755	m_mmc_prg_mask = map52_helper1 ? 0x0f : 0x1f;
	10756	m_mmc_chr_base = ((data & 0x20) << 3) | ((data & 0x04) << 7) | (map52_helper2 ? ((data & 0x10) << 3) : 0);
	10757	m_mmc_chr_mask = map52_helper2 ? 0x7f : 0xff;
	10758	mmc3_set_prg(machine(), m_mmc_prg_base, m_mmc_prg_mask);
	10759	mmc3_set_chr(machine(), m_mmc_chr_source, m_mmc_chr_base, m_mmc_chr_mask);
10911	10760
10912		state->m_map52_reg_written = BIT(data, 7);   // mc_2hikg & mc_s3nt3 write here multiple time
	10761	m_map52_reg_written = BIT(data, 7);   // mc_2hikg & mc_s3nt3 write here multiple time
10913	10762	}
10914	10763	else
10915		state->m_wram[offset] = data;
	10764	m_wram[offset] = data;
10916	10765	}
10917	10766
10918	10767	/*************************************************************
r18063	r18064
10961	10810	chr1_x(machine, chr_page ^ 7, chr_base | (state->m_mmc_vrom_bank[5] & chr_mask), chr);
10962	10811	}
10963	10812
10964		static WRITE8_HANDLER( bmc_gc6in1_l_w )
	10813	WRITE8_MEMBER(nes_state::bmc_gc6in1_l_w)
10965	10814	{
10966		nes_state *state = space.machine().driver_data<nes_state>();
10967	10815	UINT8 bank;
10968	10816	LOG_MMC(("bmc_gc6in1_l_w, offset: %04x, data: %02x\n", offset, data));
10969	10817	offset += 0x100;
10970	10818
10971	10819	if (offset == 0x1000)
10972	10820	{
10973		state->m_mmc_reg[0] = data;
	10821	m_mmc_reg[0] = data;
10974	10822	if (data & 0x80)
10975	10823	{
10976		bank = (data & 0x0f) | ((state->m_mmc_reg[1] & 0x03) << 4);
10977		prg16_89ab(space.machine(), bank);
10978		prg16_cdef(space.machine(), bank);
	10824	bank = (data & 0x0f) | ((m_mmc_reg[1] & 0x03) << 4);
	10825	prg16_89ab(machine(), bank);
	10826	prg16_cdef(machine(), bank);
10979	10827	}
10980	10828	else
10981		bmc_gc6in1_set_prg(space.machine(), state->m_mmc_prg_base, state->m_mmc_prg_mask);
	10829	bmc_gc6in1_set_prg(machine(), m_mmc_prg_base, m_mmc_prg_mask);
10982	10830	}
10983	10831	else if (offset == 0x1001)
10984	10832	{
10985		state->m_mmc_reg[1] = data;
10986		bmc_gc6in1_set_prg(space.machine(), state->m_mmc_prg_base, state->m_mmc_prg_mask);
	10833	m_mmc_reg[1] = data;
	10834	bmc_gc6in1_set_prg(machine(), m_mmc_prg_base, m_mmc_prg_mask);
10987	10835	}
10988	10836	else if (offset == 0x1007)
10989	10837	{
10990		state->m_mmc_reg[2] = data;
	10838	m_mmc_reg[2] = data;
10991	10839	}
10992	10840	}
10993	10841
10994		static WRITE8_HANDLER( bmc_gc6in1_w )
	10842	WRITE8_MEMBER(nes_state::bmc_gc6in1_w)
10995	10843	{
10996		nes_state *state = space.machine().driver_data<nes_state>();
10997	10844	UINT8 mmc_helper, cmd;
10998	10845	static const UINT8 conv_table[8] = {0, 6, 3, 7, 5, 2, 4, 1};
10999	10846	LOG_MMC(("bmc_gc6in1_w, offset: %04x, data: %02x\n", offset, data));
11000	10847
11001		if (!state->m_mmc_reg[2]) // in this case we act like MMC3, only with alt prg/chr handlers
	10848	if (!m_mmc_reg[2]) // in this case we act like MMC3, only with alt prg/chr handlers
11002	10849	{
11003	10850	switch (offset & 0x6001)
11004	10851	{
11005	10852	case 0x0000:
11006		mmc_helper = state->m_mmc3_latch ^ data;
11007		state->m_mmc3_latch = data;
	10853	mmc_helper = m_mmc3_latch ^ data;
	10854	m_mmc3_latch = data;
11008	10855
11009	10856	/* Has PRG Mode changed? */
11010	10857	if (mmc_helper & 0x40)
11011		bmc_gc6in1_set_prg(space.machine(), state->m_mmc_prg_base, state->m_mmc_prg_mask);
	10858	bmc_gc6in1_set_prg(machine(), m_mmc_prg_base, m_mmc_prg_mask);
11012	10859
11013	10860	/* Has CHR Mode changed? */
11014	10861	if (mmc_helper & 0x80)
11015		bmc_gc6in1_set_chr(space.machine(), state->m_mmc_chr_source);
	10862	bmc_gc6in1_set_chr(machine(), m_mmc_chr_source);
11016	10863	break;
11017	10864
11018	10865	case 0x0001:
11019		cmd = state->m_mmc3_latch & 0x07;
	10866	cmd = m_mmc3_latch & 0x07;
11020	10867	switch (cmd)
11021	10868	{
11022	10869	case 0: case 1:   // these do not need to be separated: we take care of them in set_chr!
11023	10870	case 2: case 3: case 4: case 5:
11024		state->m_mmc_vrom_bank[cmd] = data;
11025		bmc_gc6in1_set_chr(space.machine(), state->m_mmc_chr_source);
	10871	m_mmc_vrom_bank[cmd] = data;
	10872	bmc_gc6in1_set_chr(machine(), m_mmc_chr_source);
11026	10873	break;
11027	10874	case 6:
11028	10875	case 7:
11029		state->m_mmc_prg_bank[cmd - 6] = data;
11030		bmc_gc6in1_set_prg(space.machine(), state->m_mmc_prg_base, state->m_mmc_prg_mask);
	10876	m_mmc_prg_bank[cmd - 6] = data;
	10877	bmc_gc6in1_set_prg(machine(), m_mmc_prg_base, m_mmc_prg_mask);
11031	10878	break;
11032	10879	}
11033	10880	break;
r18063	r18064
11047	10894
11048	10895	case 0x0001:
11049	10896	data = (data & 0xc0) | conv_table[data & 0x07];
11050		mmc_helper = state->m_mmc3_latch ^ data;
11051		state->m_mmc3_latch = data;
	10897	mmc_helper = m_mmc3_latch ^ data;
	10898	m_mmc3_latch = data;
11052	10899
11053	10900	/* Has PRG Mode changed? */
11054	10901	if (mmc_helper & 0x40)
11055		bmc_gc6in1_set_prg(space.machine(), state->m_mmc_prg_base, state->m_mmc_prg_mask);
	10902	bmc_gc6in1_set_prg(machine(), m_mmc_prg_base, m_mmc_prg_mask);
11056	10903
11057	10904	/* Has CHR Mode changed? */
11058	10905	if (mmc_helper & 0x80)
11059		bmc_gc6in1_set_chr(space.machine(), state->m_mmc_chr_source);
	10906	bmc_gc6in1_set_chr(machine(), m_mmc_chr_source);
11060	10907
11061		state->m_mmc_reg[3] = 1;
	10908	m_mmc_reg[3] = 1;
11062	10909	break;
11063	10910
11064	10911	case 0x2000:
11065		cmd = state->m_mmc3_latch & 0x07;
11066		if (state->m_mmc_reg[3])
	10912	cmd = m_mmc3_latch & 0x07;
	10913	if (m_mmc_reg[3])
11067	10914	{
11068		state->m_mmc_reg[3] = 0;
	10915	m_mmc_reg[3] = 0;
11069	10916	switch (cmd)
11070	10917	{
11071	10918	case 0: case 1:   // these do not need to be separated: we take care of them in set_chr!
11072	10919	case 2: case 3: case 4: case 5:
11073		state->m_mmc_vrom_bank[cmd] = data;
11074		bmc_gc6in1_set_chr(space.machine(), state->m_mmc_chr_source);
	10920	m_mmc_vrom_bank[cmd] = data;
	10921	bmc_gc6in1_set_chr(machine(), m_mmc_chr_source);
11075	10922	break;
11076	10923	case 6:
11077	10924	case 7:
11078		state->m_mmc_prg_bank[cmd - 6] = data;
11079		bmc_gc6in1_set_prg(space.machine(), state->m_mmc_prg_base, state->m_mmc_prg_mask);
	10925	m_mmc_prg_bank[cmd - 6] = data;
	10926	bmc_gc6in1_set_prg(machine(), m_mmc_prg_base, m_mmc_prg_mask);
11080	10927	break;
11081	10928	}
11082	10929	}
r18063	r18064
11084	10931
11085	10932
11086	10933	case 0x2001:
11087		set_nt_mirroring(space.machine(), BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	10934	set_nt_mirroring(machine(), BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
11088	10935	break;
11089	10936
11090	10937	default:
r18063	r18064
11109	10956
11110	10957	*************************************************************/
11111	10958
11112		static WRITE8_HANDLER( bmc_family4646_m_w )
	10959	WRITE8_MEMBER(nes_state::bmc_family4646_m_w)
11113	10960	{
11114		nes_state *state = space.machine().driver_data<nes_state>();
11115	10961	LOG_MMC(("bmc_family4646_m_w, offset: %04x, data: %02x\n", offset, data));
11116	10962
11117	10963	if (offset == 0x01)
11118	10964	{
11119		state->m_mmc_prg_base = (data & 0x02) << 4;
11120		state->m_mmc_prg_mask = 0x1f;
11121		state->m_mmc_chr_base = (data & 0x20) << 3;
11122		state->m_mmc_chr_mask = 0xff;
11123		mmc3_set_prg(space.machine(), state->m_mmc_prg_base, state->m_mmc_prg_mask);
11124		mmc3_set_chr(space.machine(), state->m_mmc_chr_source, state->m_mmc_chr_base, state->m_mmc_chr_mask);
	10965	m_mmc_prg_base = (data & 0x02) << 4;
	10966	m_mmc_prg_mask = 0x1f;
	10967	m_mmc_chr_base = (data & 0x20) << 3;
	10968	m_mmc_chr_mask = 0xff;
	10969	mmc3_set_prg(machine(), m_mmc_prg_base, m_mmc_prg_mask);
	10970	mmc3_set_chr(machine(), m_mmc_chr_source, m_mmc_chr_base, m_mmc_chr_mask);
11125	10971	}
11126	10972	}
11127	10973
r18063	r18064
11131	10977
11132	10978	*************************************************************/
11133	10979
11134		static WRITE8_HANDLER( bmc_vt5201_w )
	10980	WRITE8_MEMBER(nes_state::bmc_vt5201_w)
11135	10981	{
11136		nes_state *state = space.machine().driver_data<nes_state>();
11137	10982	LOG_MMC(("bmc_vt5201_w, offset: %04x, data: %02x\n", offset, data));
11138	10983
11139		state->m_mmc_latch1 = BIT(offset, 8);
	10984	m_mmc_latch1 = BIT(offset, 8);
11140	10985
11141	10986	// not sure about this mirroring bit!!
11142	10987	// without it TN 95 in 1 has glitches in Lunar Ball; with it TN 95 in 1 has glitches in Galaxian!
11143		set_nt_mirroring(space.machine(), BIT(data, 3) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	10988	set_nt_mirroring(machine(), BIT(data, 3) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
11144	10989	if (BIT(offset, 7))
11145	10990	{
11146		prg16_89ab(space.machine(), (offset >> 4) & 0x07);
11147		prg16_cdef(space.machine(), (offset >> 4) & 0x07);
	10991	prg16_89ab(machine(), (offset >> 4) & 0x07);
	10992	prg16_cdef(machine(), (offset >> 4) & 0x07);
11148	10993	}
11149	10994	else
11150		prg32(space.machine(), (offset >> 5) & 0x03);
11151		chr8(space.machine(), offset, CHRROM);
	10995	prg32(machine(), (offset >> 5) & 0x03);
	10996	chr8(machine(), offset, CHRROM);
11152	10997	}
11153	10998
11154		static READ8_HANDLER( bmc_vt5201_r )
	10999	READ8_MEMBER(nes_state::bmc_vt5201_r)
11155	11000	{
11156		nes_state *state = space.machine().driver_data<nes_state>();
11157	11001	LOG_MMC(("bmc_vt5201_r, offset: %04x\n", offset));
11158		//  state->m_mmc_dipsetting = state->ioport("CARTDIPS")->read();
	11002	//  m_mmc_dipsetting = ioport("CARTDIPS")->read();
11159	11003
11160		if (state->m_mmc_latch1)
11161		return state->m_mmc_dipsetting; // cart mode, depending on the Dip Switches (always zero atm, given we have no way to add cart-based DIPs)
	11004	if (m_mmc_latch1)
	11005	return m_mmc_dipsetting; // cart mode, depending on the Dip Switches (always zero atm, given we have no way to add cart-based DIPs)
11162	11006	else
11163		return mmc_hi_access_rom(space.machine(), offset);
	11007	return mmc_hi_access_rom(machine(), offset);
11164	11008	}
11165	11009
11166	11010	/*************************************************************
r18063	r18064
11185	11029	chr2_6(machine, state->m_mmc_vrom_bank[3], CHRROM);
11186	11030	}
11187	11031
11188		static WRITE8_HANDLER( bmc_bs5_w )
	11032	WRITE8_MEMBER(nes_state::bmc_bs5_w)
11189	11033	{
11190		nes_state *state = space.machine().driver_data<nes_state>();
11191	11034	UINT8 bs5_helper = (offset & 0xc00) >> 10;
11192	11035	LOG_MMC(("bmc_bs5_w, offset: %04x, data: %02x\n", offset, data));
11193		//  state->m_mmc_dipsetting = state->ioport("CARTDIPS")->read();
	11036	//  m_mmc_dipsetting = ioport("CARTDIPS")->read();
11194	11037
11195	11038	switch (offset & 0x7000)
11196	11039	{
11197	11040	case 0x0000:
11198		state->m_mmc_vrom_bank[bs5_helper] = offset & 0x1f;
	11041	m_mmc_vrom_bank[bs5_helper] = offset & 0x1f;
11199	11042	break;
11200	11043	case 0x2000:
11201		if (BIT(offset, state->m_mmc_dipsetting + 4))   // mmc_dipsetting is always zero atm, given we have no way to add cart-based DIPs
11202		state->m_mmc_prg_bank[bs5_helper] = offset & 0x0f;
	11044	if (BIT(offset, m_mmc_dipsetting + 4))   // mmc_dipsetting is always zero atm, given we have no way to add cart-based DIPs
	11045	m_mmc_prg_bank[bs5_helper] = offset & 0x0f;
11203	11046	break;
11204	11047	}
11205		bmc_bs5_update_banks(space.machine());
	11048	bmc_bs5_update_banks(machine());
11206	11049	}
11207	11050
11208	11051	/*************************************************************
r18063	r18064
11213	11056
11214	11057	*************************************************************/
11215	11058
11216		static WRITE8_HANDLER( bmc_810544_w )
	11059	WRITE8_MEMBER(nes_state::bmc_810544_w)
11217	11060	{
11218	11061	UINT8 bank = (offset >> 7);
11219	11062	LOG_MMC(("bmc_810544_w, offset: %04x, data: %02x\n", offset, data));
11220	11063
11221	11064	if (!BIT(offset, 6))
11222	11065	{
11223		prg16_89ab(space.machine(), (bank << 1) | BIT(offset, 5));
11224		prg16_cdef(space.machine(), (bank << 1) | BIT(offset, 5));
	11066	prg16_89ab(machine(), (bank << 1) | BIT(offset, 5));
	11067	prg16_cdef(machine(), (bank << 1) | BIT(offset, 5));
11225	11068	}
11226	11069	else
11227		prg32(space.machine(), bank);
	11070	prg32(machine(), bank);
11228	11071
11229		set_nt_mirroring(space.machine(), BIT(offset, 4) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	11072	set_nt_mirroring(machine(), BIT(offset, 4) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
11230	11073
11231		chr8(space.machine(), offset & 0x0f, CHRROM);
	11074	chr8(machine(), offset & 0x0f, CHRROM);
11232	11075	}
11233	11076
11234	11077	/*************************************************************
r18063	r18064
11237	11080
11238	11081	*************************************************************/
11239	11082
11240		static WRITE8_HANDLER( bmc_ntd03_w )
	11083	WRITE8_MEMBER(nes_state::bmc_ntd03_w)
11241	11084	{
11242	11085	UINT8 pbank, cbank;
11243	11086	LOG_MMC(("bmc_ntd03_w, offset: %04x, data: %02x\n", offset, data));
r18063	r18064
11247	11090
11248	11091	if (BIT(offset, 7))
11249	11092	{
11250		prg16_89ab(space.machine(), pbank | BIT(offset, 6));
11251		prg16_cdef(space.machine(), pbank | BIT(offset, 6));
	11093	prg16_89ab(machine(), pbank | BIT(offset, 6));
	11094	prg16_cdef(machine(), pbank | BIT(offset, 6));
11252	11095	}
11253	11096	else
11254		prg32(space.machine(), pbank >> 1);
	11097	prg32(machine(), pbank >> 1);
11255	11098
11256		set_nt_mirroring(space.machine(), BIT(offset, 10) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	11099	set_nt_mirroring(machine(), BIT(offset, 10) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
11257	11100
11258		chr8(space.machine(), cbank, CHRROM);
	11101	chr8(machine(), cbank, CHRROM);
11259	11102	}
11260	11103
11261	11104	/*************************************************************
r18063	r18064
11286	11129	//      chr8(machine, 0, CHRROM);
11287	11130	}
11288	11131
11289		static WRITE8_HANDLER( bmc_gb63_w )
	11132	WRITE8_MEMBER(nes_state::bmc_gb63_w)
11290	11133	{
11291		nes_state *state = space.machine().driver_data<nes_state>();
11292	11134	LOG_MMC(("bmc_gb63_w, offset: %04x, data: %02x\n", offset, data));
11293	11135
11294		state->m_mmc_reg[offset & 1] = data;
11295		state->m_mmc_latch1 = BIT(state->m_mmc_reg[0], 7) | (BIT(state->m_mmc_reg[1], 0) << 1);
	11136	m_mmc_reg[offset & 1] = data;
	11137	m_mmc_latch1 = BIT(m_mmc_reg[0], 7) | (BIT(m_mmc_reg[1], 0) << 1);
11296	11138
11297	11139	}
11298	11140
11299		static READ8_HANDLER( bmc_gb63_r )
	11141	READ8_MEMBER(nes_state::bmc_gb63_r)
11300	11142	{
11301		nes_state *state = space.machine().driver_data<nes_state>();
11302	11143	LOG_MMC(("bmc_gb63_r, offset: %04x\n", offset));
11303		//  state->m_mmc_dipsetting = state->ioport("CARTDIPS")->read();
	11144	//  m_mmc_dipsetting = ioport("CARTDIPS")->read();
11304	11145
11305		if (state->m_mmc_latch1 == 1)
	11146	if (m_mmc_latch1 == 1)
11306	11147	return 0xff;   // open bus
11307	11148	else
11308		return mmc_hi_access_rom(space.machine(), offset);
	11149	return mmc_hi_access_rom(machine(), offset);
11309	11150	}
11310	11151
11311	11152	/*************************************************************
r18063	r18064
11314	11155
11315	11156	*************************************************************/
11316	11157
11317		static WRITE8_HANDLER( edu2k_w )
	11158	WRITE8_MEMBER(nes_state::edu2k_w)
11318	11159	{
11319	11160	LOG_MMC(("edu2k_w, offset: %04x, data: %02x\n", offset, data));
11320	11161
11321		prg32(space.machine(), data & 0x1f);
11322		wram_bank(space.machine(), (data & 0xc0) >> 6, NES_WRAM);
	11162	prg32(machine(), data & 0x1f);
	11163	wram_bank(machine(), (data & 0xc0) >> 6, NES_WRAM);
11323	11164	}
11324	11165
11325	11166	/*************************************************************
r18063	r18064
11336	11177	prg8_x(machine, start, bank);
11337	11178	}
11338	11179
11339		static WRITE8_HANDLER( h2288_l_w )
	11180	WRITE8_MEMBER(nes_state::h2288_l_w)
11340	11181	{
11341		nes_state *state = space.machine().driver_data<nes_state>();
11342	11182	LOG_MMC(("h2288_l_w offset: %04x, data: %02x\n", offset, data));
11343	11183	offset += 0x100;
11344	11184
11345	11185	if (offset >= 0x1800)
11346	11186	{
11347		state->m_mmc_reg[offset & 1] = data;
11348		if (state->m_mmc_reg[0] & 0x40)
	11187	m_mmc_reg[offset & 1] = data;
	11188	if (m_mmc_reg[0] & 0x40)
11349	11189	{
11350		UINT8 helper1 = (state->m_mmc_reg[0] & 0x05) | ((state->m_mmc_reg[0] >> 2) & 0x0a);
11351		UINT8 helper2 = BIT(state->m_mmc_reg[0], 1);
11352		prg16_89ab(space.machine(), helper1 & ~helper2);
11353		prg16_cdef(space.machine(), helper1 |  helper2);
	11190	UINT8 helper1 = (m_mmc_reg[0] & 0x05) | ((m_mmc_reg[0] >> 2) & 0x0a);
	11191	UINT8 helper2 = BIT(m_mmc_reg[0], 1);
	11192	prg16_89ab(machine(), helper1 & ~helper2);
	11193	prg16_cdef(machine(), helper1 |  helper2);
11354	11194	}
11355	11195	else
11356		mmc3_set_prg(space.machine(), state->m_mmc_prg_base, state->m_mmc_prg_mask);
	11196	mmc3_set_prg(machine(), m_mmc_prg_base, m_mmc_prg_mask);
11357	11197	}
11358	11198	}
11359	11199
11360		static READ8_HANDLER( h2288_l_r )
	11200	READ8_MEMBER(nes_state::h2288_l_r)
11361	11201	{
11362	11202	LOG_MMC(("h2288_l_r offset: %04x\n", offset));
11363	11203	offset += 0x100;
r18063	r18064
11374	11214	return 0;
11375	11215	}
11376	11216
11377		static WRITE8_HANDLER( h2288_w )
	11217	WRITE8_MEMBER(nes_state::h2288_w)
11378	11218	{
11379	11219	static const UINT8 conv_table[8] = {0, 3, 1, 5, 6, 7, 2, 4};
11380	11220	LOG_MMC(("h2288_w, offset: %04x, data: %02x\n", offset, data));
r18063	r18064
11442	11282	}
11443	11283	}
11444	11284
11445		static WRITE8_HANDLER( shjy3_w )
	11285	WRITE8_MEMBER(nes_state::shjy3_w)
11446	11286	{
11447		nes_state *state = space.machine().driver_data<nes_state>();
11448	11287	UINT8 mmc_helper, shift;
11449	11288	LOG_MMC(("shjy3_w, offset: %04x, data: %02x\n", offset, data));
11450	11289
r18063	r18064
11455	11294	mmc_helper &= 7;
11456	11295	shift = offset & 4;
11457	11296
11458		state->m_mmc_vrom_bank[mmc_helper] = (state->m_mmc_vrom_bank[mmc_helper] & (0xf0 >> shift)) | ((data & 0x0f) << shift);
	11297	m_mmc_vrom_bank[mmc_helper] = (m_mmc_vrom_bank[mmc_helper] & (0xf0 >> shift)) | ((data & 0x0f) << shift);
11459	11298	if (shift)
11460		state->m_mmc_extra_bank[mmc_helper] = data >> 4;
	11299	m_mmc_extra_bank[mmc_helper] = data >> 4;
11461	11300	}
11462	11301	else
11463	11302	{
11464	11303	switch (offset)
11465	11304	{
11466	11305	case 0x0010:
11467		state->m_mmc_prg_bank[0] = data;
	11306	m_mmc_prg_bank[0] = data;
11468	11307	break;
11469	11308	case 0x2010:
11470		state->m_mmc_prg_bank[1] = data;
	11309	m_mmc_prg_bank[1] = data;
11471	11310	break;
11472	11311	case 0x1400:
11473	11312	switch (data & 0x03)
11474	11313	{
11475		case 0: set_nt_mirroring(space.machine(), PPU_MIRROR_VERT); break;
11476		case 1: set_nt_mirroring(space.machine(), PPU_MIRROR_HORZ); break;
11477		case 2: set_nt_mirroring(space.machine(), PPU_MIRROR_LOW); break;
11478		case 3: set_nt_mirroring(space.machine(), PPU_MIRROR_HIGH); break;
	11314	case 0: set_nt_mirroring(machine(), PPU_MIRROR_VERT); break;
	11315	case 1: set_nt_mirroring(machine(), PPU_MIRROR_HORZ); break;
	11316	case 2: set_nt_mirroring(machine(), PPU_MIRROR_LOW); break;
	11317	case 3: set_nt_mirroring(machine(), PPU_MIRROR_HIGH); break;
11479	11318	}
11480	11319	break;
11481	11320	case 0x7000:
11482		state->m_IRQ_count_latch = (state->m_IRQ_count_latch & 0xf0) | (data & 0x0f);
	11321	m_IRQ_count_latch = (m_IRQ_count_latch & 0xf0) | (data & 0x0f);
11483	11322	break;
11484	11323	case 0x7004:
11485		state->m_IRQ_count_latch = (state->m_IRQ_count_latch & 0x0f) | ((data & 0x0f) << 4);
	11324	m_IRQ_count_latch = (m_IRQ_count_latch & 0x0f) | ((data & 0x0f) << 4);
11486	11325	break;
11487	11326	case 0x7008:
11488		state->m_IRQ_enable = data & 0x03;
11489		if (state->m_IRQ_enable & 0x02)
11490		state->m_IRQ_count = state->m_IRQ_count_latch;
	11327	m_IRQ_enable = data & 0x03;
	11328	if (m_IRQ_enable & 0x02)
	11329	m_IRQ_count = m_IRQ_count_latch;
11491	11330	break;
11492	11331	}
11493	11332	}
11494		shjy3_update(space.machine());
	11333	shjy3_update(machine());
11495	11334	}
11496	11335
11497	11336	/*************************************************************
r18063	r18064
11504	11343
11505	11344	*************************************************************/
11506	11345
11507		WRITE8_HANDLER( unl_6035052_extra_w )
	11346	WRITE8_MEMBER(nes_state::unl_6035052_extra_w)
11508	11347	{
11509		nes_state *state = space.machine().driver_data<nes_state>();
11510	11348	LOG_MMC(("unl_6035052_extra_w, offset: %04x, data: %02x\n", offset, data));
11511		state->m_mmc_latch1 = data & 0x03;
11512		if (state->m_mmc_latch1 == 1)
11513		state->m_mmc_latch1 = 2;
	11349	m_mmc_latch1 = data & 0x03;
	11350	if (m_mmc_latch1 == 1)
	11351	m_mmc_latch1 = 2;
11514	11352	}
11515	11353
11516		READ8_HANDLER( unl_6035052_extra_r )
	11354	READ8_MEMBER(nes_state::unl_6035052_extra_r)
11517	11355	{
11518		nes_state *state = space.machine().driver_data<nes_state>();
11519	11356	LOG_MMC(("unl_6035052_extra_r, offset: %04x\n", offset));
11520		return state->m_mmc_latch1;
	11357	return m_mmc_latch1;
11521	11358	}
11522	11359
11523	11360
r18063	r18064
11570	11407	state->m_mmc_chr_mask = BIT(state->m_mmc_reg[0], 7) ? 0x7f : 0xff;
11571	11408	}
11572	11409
11573		static WRITE8_HANDLER( pjoy84_m_w )
	11410	WRITE8_MEMBER(nes_state::pjoy84_m_w)
11574	11411	{
11575		nes_state *state = space.machine().driver_data<nes_state>();
11576	11412	LOG_MMC(("pjoy84_m_w offset: %04x, data: %02x\n", offset, data));
11577	11413
11578	11414	switch (offset & 0x03)
11579	11415	{
11580	11416	case 0x00:
11581	11417	case 0x03:
11582		if (state->m_mmc_reg[3] & 0x80)
	11418	if (m_mmc_reg[3] & 0x80)
11583	11419	return;   // else we act as if offset & 3 = 1,2
11584	11420	case 0x01:
11585	11421	case 0x02:
11586		state->m_mmc_reg[offset & 0x03] = data;
11587		pjoy84_set_base_mask(space.machine());
11588		if (state->m_mmc_reg[3] & 0x10)
11589		chr8(space.machine(), (state->m_mmc_chr_base >> 3) | (state->m_mmc_reg[2] & 0x0f), state->m_mmc_chr_source);
	11422	m_mmc_reg[offset & 0x03] = data;
	11423	pjoy84_set_base_mask(machine());
	11424	if (m_mmc_reg[3] & 0x10)
	11425	chr8(machine(), (m_mmc_chr_base >> 3) | (m_mmc_reg[2] & 0x0f), m_mmc_chr_source);
11590	11426	else
11591		mmc3_set_chr(space.machine(), state->m_mmc_chr_source, state->m_mmc_chr_base, state->m_mmc_chr_mask);
11592		mmc3_set_prg(space.machine(), state->m_mmc_prg_base, state->m_mmc_prg_mask);
	11427	mmc3_set_chr(machine(), m_mmc_chr_source, m_mmc_chr_base, m_mmc_chr_mask);
	11428	mmc3_set_prg(machine(), m_mmc_prg_base, m_mmc_prg_mask);
11593	11429	break;
11594	11430	}
11595	11431	}
r18063	r18064
11650	11486	chr8(machine, (state->m_mmc_reg[1] & 0x1f) >> 1, state->m_mmc_chr_source);
11651	11487	}
11652	11488
11653		static WRITE8_HANDLER( someri_mmc1_w )
	11489	WRITE8_MEMBER(nes_state::someri_mmc1_w)
11654	11490	{
11655		nes_state *state = space.machine().driver_data<nes_state>();
11656	11491
11657		assert(state->m_mmc_cmd1 == 2);
	11492	assert(m_mmc_cmd1 == 2);
11658	11493
11659	11494	if (data & 0x80)
11660	11495	{
11661		state->m_mmc1_count = 0;
11662		state->m_mmc1_latch = 0;
	11496	m_mmc1_count = 0;
	11497	m_mmc1_latch = 0;
11663	11498
11664		state->m_mmc_reg[0] |= 0x0c;
11665		someri_mmc1_set_prg(space.machine());
	11499	m_mmc_reg[0] |= 0x0c;
	11500	someri_mmc1_set_prg(machine());
11666	11501	return;
11667	11502	}
11668	11503
11669		if (state->m_mmc1_count < 5)
	11504	if (m_mmc1_count < 5)
11670	11505	{
11671		if (state->m_mmc1_count == 0) state->m_mmc1_latch = 0;
11672		state->m_mmc1_latch >>= 1;
11673		state->m_mmc1_latch |= (data & 0x01) ? 0x10 : 0x00;
11674		state->m_mmc1_count++;
	11506	if (m_mmc1_count == 0) m_mmc1_latch = 0;
	11507	m_mmc1_latch >>= 1;
	11508	m_mmc1_latch |= (data & 0x01) ? 0x10 : 0x00;
	11509	m_mmc1_count++;
11675	11510	}
11676	11511
11677		if (state->m_mmc1_count == 5)
	11512	if (m_mmc1_count == 5)
11678	11513	{
11679	11514	switch (offset & 0x6000)
11680	11515	{
11681	11516	case 0x0000:
11682		state->m_mmc_reg[0] = state->m_mmc1_latch;
11683		switch (state->m_mmc_reg[0] & 0x03)
	11517	m_mmc_reg[0] = m_mmc1_latch;
	11518	switch (m_mmc_reg[0] & 0x03)
11684	11519	{
11685		case 0: set_nt_mirroring(space.machine(), PPU_MIRROR_LOW); break;
11686		case 1: set_nt_mirroring(space.machine(), PPU_MIRROR_HIGH); break;
11687		case 2: set_nt_mirroring(space.machine(), PPU_MIRROR_VERT); break;
11688		case 3: set_nt_mirroring(space.machine(), PPU_MIRROR_HORZ); break;
	11520	case 0: set_nt_mirroring(machine(), PPU_MIRROR_LOW); break;
	11521	case 1: set_nt_mirroring(machine(), PPU_MIRROR_HIGH); break;
	11522	case 2: set_nt_mirroring(machine(), PPU_MIRROR_VERT); break;
	11523	case 3: set_nt_mirroring(machine(), PPU_MIRROR_HORZ); break;
11689	11524	}
11690		someri_mmc1_set_chr(space.machine());
11691		someri_mmc1_set_prg(space.machine());
	11525	someri_mmc1_set_chr(machine());
	11526	someri_mmc1_set_prg(machine());
11692	11527	break;
11693	11528	case 0x2000:
11694		state->m_mmc_reg[1] = state->m_mmc1_latch;
11695		someri_mmc1_set_chr(space.machine());
11696		someri_mmc1_set_prg(space.machine());
	11529	m_mmc_reg[1] = m_mmc1_latch;
	11530	someri_mmc1_set_chr(machine());
	11531	someri_mmc1_set_prg(machine());
11697	11532	break;
11698	11533	case 0x4000:
11699		state->m_mmc_reg[2] = state->m_mmc1_latch;
11700		someri_mmc1_set_chr(space.machine());
	11534	m_mmc_reg[2] = m_mmc1_latch;
	11535	someri_mmc1_set_chr(machine());
11701	11536	break;
11702	11537	case 0x6000:
11703		state->m_mmc_reg[3] = state->m_mmc1_latch;
11704		someri_mmc1_set_prg(space.machine());
	11538	m_mmc_reg[3] = m_mmc1_latch;
	11539	someri_mmc1_set_prg(machine());
11705	11540	break;
11706	11541	}
11707	11542
11708		state->m_mmc1_count = 0;
	11543	m_mmc1_count = 0;
11709	11544	}
11710	11545	}
11711	11546
11712	11547	// MMC3 Mode emulation
11713		static WRITE8_HANDLER( someri_mmc3_w )
	11548	WRITE8_MEMBER(nes_state::someri_mmc3_w)
11714	11549	{
11715		nes_state *state = space.machine().driver_data<nes_state>();
11716	11550	UINT8 mmc_helper, cmd;
11717	11551
11718		assert(state->m_mmc_cmd1 == 1);
	11552	assert(m_mmc_cmd1 == 1);
11719	11553	switch (offset & 0x6001)
11720	11554	{
11721	11555	case 0x0000:
11722		mmc_helper = state->m_mmc3_latch ^ data;
11723		state->m_mmc3_latch = data;
	11556	mmc_helper = m_mmc3_latch ^ data;
	11557	m_mmc3_latch = data;
11724	11558
11725	11559	if (mmc_helper & 0x40)
11726		mmc3_set_prg(space.machine(), state->m_mmc_prg_base, state->m_mmc_prg_mask);
	11560	mmc3_set_prg(machine(), m_mmc_prg_base, m_mmc_prg_mask);
11727	11561
11728	11562	if (mmc_helper & 0x80)
11729		mmc3_set_chr(space.machine(), state->m_mmc_chr_source, state->m_mmc_chr_base, state->m_mmc_chr_mask);
	11563	mmc3_set_chr(machine(), m_mmc_chr_source, m_mmc_chr_base, m_mmc_chr_mask);
11730	11564	break;
11731	11565
11732	11566	case 0x0001:
11733		cmd = state->m_mmc3_latch & 0x07;
	11567	cmd = m_mmc3_latch & 0x07;
11734	11568	switch (cmd)
11735	11569	{
11736	11570	case 0: case 1:
11737	11571	case 2: case 3: case 4: case 5:
11738		state->m_mmc_vrom_bank[cmd] = data;
11739		mmc3_set_chr(space.machine(), state->m_mmc_chr_source, state->m_mmc_chr_base, state->m_mmc_chr_mask);
	11572	m_mmc_vrom_bank[cmd] = data;
	11573	mmc3_set_chr(machine(), m_mmc_chr_source, m_mmc_chr_base, m_mmc_chr_mask);
11740	11574	break;
11741	11575	case 6:
11742	11576	case 7:
11743		state->m_mmc_prg_bank[cmd - 6] = data;
11744		mmc3_set_prg(space.machine(), state->m_mmc_prg_base, state->m_mmc_prg_mask);
	11577	m_mmc_prg_bank[cmd - 6] = data;
	11578	mmc3_set_prg(machine(), m_mmc_prg_base, m_mmc_prg_mask);
11745	11579	break;
11746	11580	}
11747	11581	break;
11748	11582
11749	11583	case 0x2000:
11750		set_nt_mirroring(space.machine(), BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	11584	set_nt_mirroring(machine(), BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
11751	11585	break;
11752	11586	case 0x2001: break;
11753		case 0x4000: state->m_IRQ_count_latch = data; break;
11754		case 0x4001: state->m_IRQ_count = 0; break;
11755		case 0x6000: state->m_IRQ_enable = 0; break;
11756		case 0x6001: state->m_IRQ_enable = 1; break;
	11587	case 0x4000: m_IRQ_count_latch = data; break;
	11588	case 0x4001: m_IRQ_count = 0; break;
	11589	case 0x6000: m_IRQ_enable = 0; break;
	11590	case 0x6001: m_IRQ_enable = 1; break;
11757	11591	}
11758	11592	}
11759	11593
11760	11594	// VRC2 Mode emulation
11761		static WRITE8_HANDLER( someri_vrc2_w )
	11595	WRITE8_MEMBER(nes_state::someri_vrc2_w)
11762	11596	{
11763		nes_state *state = space.machine().driver_data<nes_state>();
11764	11597	UINT8 bank, shift;
11765	11598
11766		assert(state->m_mmc_cmd1 == 0);
	11599	assert(m_mmc_cmd1 == 0);
11767	11600
11768	11601	if (offset < 0x1000)
11769	11602	{
11770		state->m_mmc_prg_bank[4] = data;
11771		prg8_89(space.machine(), state->m_mmc_prg_bank[4]);
	11603	m_mmc_prg_bank[4] = data;
	11604	prg8_89(machine(), m_mmc_prg_bank[4]);
11772	11605	}
11773	11606	else if (offset < 0x2000)
11774	11607	{
11775	11608	switch (data & 0x03)
11776	11609	{
11777		case 0x00: set_nt_mirroring(space.machine(), PPU_MIRROR_VERT); break;
11778		case 0x01: set_nt_mirroring(space.machine(), PPU_MIRROR_HORZ); break;
11779		case 0x02: set_nt_mirroring(space.machine(), PPU_MIRROR_LOW); break;
11780		case 0x03: set_nt_mirroring(space.machine(), PPU_MIRROR_HIGH); break;
	11610	case 0x00: set_nt_mirroring(machine(), PPU_MIRROR_VERT); break;
	11611	case 0x01: set_nt_mirroring(machine(), PPU_MIRROR_HORZ); break;
	11612	case 0x02: set_nt_mirroring(machine(), PPU_MIRROR_LOW); break;
	11613	case 0x03: set_nt_mirroring(machine(), PPU_MIRROR_HIGH); break;
11781	11614	}
11782	11615	}
11783	11616	else if (offset < 0x3000)
11784	11617	{
11785		state->m_mmc_prg_bank[5] = data;
11786		prg8_ab(space.machine(), state->m_mmc_prg_bank[5]);
	11618	m_mmc_prg_bank[5] = data;
	11619	prg8_ab(machine(), m_mmc_prg_bank[5]);
11787	11620	}
11788	11621	else if (offset < 0x7000)
11789	11622	{
11790	11623	bank = ((offset & 0x7000) - 0x3000) / 0x0800 + BIT(offset, 1);
11791	11624	shift = BIT(offset, 2) * 4;
11792	11625	data = (data & 0x0f) << shift;
11793		state->m_mmc_vrom_bank[6 + bank] = data | state->m_mmc_chr_base;
11794		chr1_x(space.machine(), bank, state->m_mmc_vrom_bank[6 + bank], CHRROM);
	11626	m_mmc_vrom_bank[6 + bank] = data | m_mmc_chr_base;
	11627	chr1_x(machine(), bank, m_mmc_vrom_bank[6 + bank], CHRROM);
11795	11628	}
11796	11629	}
11797	11630
11798		static WRITE8_HANDLER( someri_w )
	11631	WRITE8_MEMBER(nes_state::someri_w)
11799	11632	{
11800		nes_state *state = space.machine().driver_data<nes_state>();
11801		LOG_MMC(("someri_w mode %d, offset: %04x, data: %02x\n", state->m_mmc_cmd1, offset, data));
	11633	LOG_MMC(("someri_w mode %d, offset: %04x, data: %02x\n", m_mmc_cmd1, offset, data));
11802	11634
11803		switch (state->m_mmc_cmd1)
	11635	switch (m_mmc_cmd1)
11804	11636	{
11805	11637	case 0x00: someri_vrc2_w(space, offset, data, mem_mask); break;
11806	11638	case 0x01: someri_mmc3_w(space, offset, data, mem_mask); break;
r18063	r18064
11832	11664	}
11833	11665	}
11834	11666
11835		static WRITE8_HANDLER( someri_l_w )
	11667	WRITE8_MEMBER(nes_state::someri_l_w)
11836	11668	{
11837		nes_state *state = space.machine().driver_data<nes_state>();
11838	11669	LOG_MMC(("someri_l_w, offset: %04x, data: %02x\n", offset, data));
11839	11670	offset += 0x100;
11840	11671
11841	11672	if (offset & 0x100)
11842	11673	{
11843		state->m_mmc_cmd1 = data & 0x03;
11844		state->m_mmc_chr_base = ((state->m_mmc_cmd1 & 0x04) << 6);
11845		if (state->m_mmc_cmd1 != 1)
11846		state->m_IRQ_enable = 0;
11847		someri_mode_update(space.machine());
	11674	m_mmc_cmd1 = data & 0x03;
	11675	m_mmc_chr_base = ((m_mmc_cmd1 & 0x04) << 6);
	11676	if (m_mmc_cmd1 != 1)
	11677	m_IRQ_enable = 0;
	11678	someri_mode_update(machine());
11848	11679	}
11849	11680	}
11850	11681
r18063	r18064
11857	11688
11858	11689	*************************************************************/
11859	11690
11860		static WRITE8_HANDLER( fujiya_m_w )
	11691	WRITE8_MEMBER(nes_state::fujiya_m_w)
11861	11692	{
11862		nes_state *state = space.machine().driver_data<nes_state>();
11863	11693	LOG_MMC(("fujiya_m_w, offset: %04x, data: %02x\n", offset, data));
11864	11694	offset += 0x6000;
11865	11695
11866	11696	if (offset == 0x6502 || offset == 0x7000)
11867		state->m_mmc_latch1 = (data & 0x40) << 1;
	11697	m_mmc_latch1 = (data & 0x40) << 1;
11868	11698	}
11869	11699
11870		static READ8_HANDLER( fujiya_m_r )
	11700	READ8_MEMBER(nes_state::fujiya_m_r)
11871	11701	{
11872		nes_state *state = space.machine().driver_data<nes_state>();
11873	11702	LOG_MMC(("fujiya_m_r, offset: %04x\n", offset));
11874	11703	offset += 0x6000;
11875	11704
11876	11705	if (offset == 0x7001 || offset == 0x7777)
11877		return state->m_mmc_latch1 | ((offset >> 8) & 0x7f);
	11706	return m_mmc_latch1 | ((offset >> 8) & 0x7f);
11878	11707
11879	11708	return 0;
11880	11709	}
r18063	r18064
11887	11716
11888	11717	struct nes_memory_accessor
11889	11718	{
11890		write8_space_func write;
11891		const char        *write_name;
11892		read8_space_func  read;
11893		const char        *read_name;
	11719	write8_delegate    write;
	11720	read8_delegate  read;
11894	11721	};
11895	11722
11896	11723	struct nes_pcb_intf
r18063	r18064
11904	11731	ppu2c0x_hblank_cb      mmc_hblank;
11905	11732	};
11906	11733
	11734
11907	11735	#define NES_NOACCESS \
11908		{FUNC_NULL, FUNC_NULL}
	11736	{write8_delegate(), read8_delegate()}
11909	11737
11910	11738	#define NES_READONLY(a) \
11911		{FUNC_NULL, FUNC(a)}
	11739	{write8_delegate(), read8_delegate(FUNC(a),(nes_state *)0)}
11912	11740
11913	11741	#define NES_WRITEONLY(a) \
11914		{FUNC(a), FUNC_NULL}
	11742	{write8_delegate(FUNC(a),(nes_state *)0), read8_delegate()}
11915	11743
11916		static WRITE8_HANDLER( dummy_l_w )
	11744	WRITE8_MEMBER(nes_state::dummy_l_w)
11917	11745	{
11918	11746	logerror("write access, offset: %04x, data: %02x\n", offset + 0x4100, data);
11919	11747	}
11920	11748
11921		static WRITE8_HANDLER( dummy_m_w )
	11749	WRITE8_MEMBER(nes_state::dummy_m_w)
11922	11750	{
11923	11751	logerror("write access, offset: %04x, data: %02x\n", offset + 0x6000, data);
11924	11752	}
11925	11753
11926		static WRITE8_HANDLER( dummy_w )
	11754	WRITE8_MEMBER(nes_state::dummy_w)
11927	11755	{
11928	11756	logerror("write access, offset: %04x, data: %02x\n", offset + 0x8000, data);
11929	11757	}
11930	11758
11931		static READ8_HANDLER( dummy_l_r )
	11759	READ8_MEMBER(nes_state::dummy_l_r)
11932	11760	{
11933	11761	logerror("read access, offset: %04x\n", offset + 0x4100);
11934	11762	return 0x00;
11935	11763	}
11936	11764
11937		static READ8_HANDLER( dummy_m_r )
	11765	READ8_MEMBER(nes_state::dummy_m_r)
11938	11766	{
11939	11767	logerror("read access, offset: %04x\n", offset + 0x6000);
11940	11768	return 0x00;
11941	11769	}
11942	11770
11943		static READ8_HANDLER( dummy_r )
	11771	READ8_MEMBER(nes_state::dummy_r)
11944	11772	{
11945	11773	logerror("read access, offset: %04x\n", offset + 0x8000);
11946	11774	return 0x00;
r18063	r18064
11951	11779	{ STD_NROM,             NES_NOACCESS, NES_NOACCESS, NES_NOACCESS,                         NULL, NULL, NULL },
11952	11780	{ HVC_FAMBASIC,         NES_NOACCESS, NES_NOACCESS, NES_NOACCESS,                         NULL, NULL, NULL },
11953	11781	{ GG_NROM,              NES_NOACCESS, NES_NOACCESS, NES_NOACCESS,                         NULL, NULL, NULL },
11954		{ STD_UXROM,            NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(uxrom_w),               NULL, NULL, NULL },
11955		{ STD_UN1ROM,           NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(un1rom_w),              NULL, NULL, NULL },
11956		{ STD_CPROM,            NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(cprom_w),               NULL, NULL, NULL },
11957		{ STD_CNROM,            NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(cnrom_w),               NULL, NULL, NULL },
11958		{ BANDAI_PT554,         NES_NOACCESS, NES_WRITEONLY(bandai_pt554_m_w), NES_WRITEONLY(cnrom_w), NULL, NULL, NULL },
11959		{ STD_AXROM,            NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(axrom_w),               NULL, NULL, NULL },
11960		{ STD_PXROM,            NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(pxrom_w),               mmc2_latch, NULL, NULL },
11961		{ STD_FXROM,            NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(fxrom_w),               mmc2_latch, NULL, NULL },
11962		{ STD_BXROM,            NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(bxrom_w),               NULL, NULL, NULL },
11963		{ STD_GXROM,            NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(gxrom_w),               NULL, NULL, NULL },
11964		{ STD_MXROM,            NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(gxrom_w),               NULL, NULL, NULL },
11965		{ STD_NXROM,            NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(ntbrom_w),              NULL, NULL, NULL },
11966		{ SUNSOFT_DCS,          NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(ntbrom_w),              NULL, NULL, NULL },
11967		{ STD_JXROM,            NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(jxrom_w),               NULL, NULL, jxrom_irq },
11968		{ STD_SXROM,            NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(sxrom_w),               NULL, NULL, NULL },
11969		{ STD_SOROM,            NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(sxrom_w),               NULL, NULL, NULL },
11970		{ STD_SXROM_A,          NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(sxrom_w),               NULL, NULL, NULL },
11971		{ STD_SOROM_A,          NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(sxrom_w),               NULL, NULL, NULL },
11972		{ STD_TXROM,            NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(txrom_w),               NULL, NULL, mmc3_irq },
11973		{ STD_TVROM,            NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(txrom_w),               NULL, NULL, mmc3_irq },
11974		{ STD_TKROM,            NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(txrom_w),               NULL, NULL, mmc3_irq },
11975		{ STD_HKROM,            NES_NOACCESS, {FUNC(hkrom_m_w), FUNC(hkrom_m_r)}, NES_WRITEONLY(hkrom_w),     NULL, NULL, mmc3_irq },
11976		{ STD_TQROM,            NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(tqrom_w),               NULL, NULL, mmc3_irq },
11977		{ STD_TXSROM,           NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(txsrom_w),              NULL, NULL, mmc3_irq },
11978		{ STD_DXROM,            NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(dxrom_w),               NULL, NULL, NULL },
11979		{ STD_DRROM,            NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(dxrom_w),               NULL, NULL, NULL },
11980		{ NAMCOT_34X3,          NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(dxrom_w),               NULL, NULL, NULL },
11981		{ NAMCOT_3425,          NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(namcot3425_w),          NULL, NULL, NULL },
11982		{ NAMCOT_3446,          NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(namcot3446_w),          NULL, NULL, NULL },
11983		{ NAMCOT_3453,          NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(namcot3453_w),          NULL, NULL, NULL },
11984		{ STD_EXROM,            {FUNC(exrom_l_w), FUNC(exrom_l_r)}, NES_NOACCESS, NES_NOACCESS,               NULL, NULL, mmc5_irq },
11985		{ NES_QJ,               NES_NOACCESS, NES_WRITEONLY(qj_m_w), NES_WRITEONLY(txrom_w),      NULL, NULL, mmc3_irq },
11986		{ PAL_ZZ,               NES_NOACCESS, NES_WRITEONLY(zz_m_w), NES_WRITEONLY(txrom_w),      NULL, NULL, mmc3_irq },
11987		{ UXROM_CC,             NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(uxrom_cc_w),            NULL, NULL, NULL },
	11782	{ STD_UXROM,            NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::uxrom_w),               NULL, NULL, NULL },
	11783	{ STD_UN1ROM,           NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::un1rom_w),              NULL, NULL, NULL },
	11784	{ STD_CPROM,            NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::cprom_w),               NULL, NULL, NULL },
	11785	{ STD_CNROM,            NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::cnrom_w),               NULL, NULL, NULL },
	11786	{ BANDAI_PT554,         NES_NOACCESS, NES_WRITEONLY(nes_state::bandai_pt554_m_w), NES_WRITEONLY(nes_state::cnrom_w), NULL, NULL, NULL },
	11787	{ STD_AXROM,            NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::axrom_w),               NULL, NULL, NULL },
	11788	{ STD_PXROM,            NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::pxrom_w),               mmc2_latch, NULL, NULL },
	11789	{ STD_FXROM,            NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::fxrom_w),               mmc2_latch, NULL, NULL },
	11790	{ STD_BXROM,            NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::bxrom_w),               NULL, NULL, NULL },
	11791	{ STD_GXROM,            NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::gxrom_w),               NULL, NULL, NULL },
	11792	{ STD_MXROM,            NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::gxrom_w),               NULL, NULL, NULL },
	11793	{ STD_NXROM,            NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::ntbrom_w),              NULL, NULL, NULL },
	11794	{ SUNSOFT_DCS,          NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::ntbrom_w),              NULL, NULL, NULL },
	11795	{ STD_JXROM,            NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::jxrom_w),               NULL, NULL, jxrom_irq },
	11796	{ STD_SXROM,            NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::sxrom_w),               NULL, NULL, NULL },
	11797	{ STD_SOROM,            NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::sxrom_w),               NULL, NULL, NULL },
	11798	{ STD_SXROM_A,          NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::sxrom_w),               NULL, NULL, NULL },
	11799	{ STD_SOROM_A,          NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::sxrom_w),               NULL, NULL, NULL },
	11800	{ STD_TXROM,            NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::txrom_w),               NULL, NULL, mmc3_irq },
	11801	{ STD_TVROM,            NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::txrom_w),               NULL, NULL, mmc3_irq },
	11802	{ STD_TKROM,            NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::txrom_w),               NULL, NULL, mmc3_irq },
	11803	{ STD_HKROM,            NES_NOACCESS, {write8_delegate(FUNC(nes_state::hkrom_m_w),(nes_state *)0), read8_delegate(FUNC(nes_state::hkrom_m_r),(nes_state *)0)}, NES_WRITEONLY(nes_state::hkrom_w),     NULL, NULL, mmc3_irq },
	11804	{ STD_TQROM,            NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::tqrom_w),               NULL, NULL, mmc3_irq },
	11805	{ STD_TXSROM,           NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::txsrom_w),              NULL, NULL, mmc3_irq },
	11806	{ STD_DXROM,            NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::dxrom_w),               NULL, NULL, NULL },
	11807	{ STD_DRROM,            NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::dxrom_w),               NULL, NULL, NULL },
	11808	{ NAMCOT_34X3,          NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::dxrom_w),               NULL, NULL, NULL },
	11809	{ NAMCOT_3425,          NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::namcot3425_w),          NULL, NULL, NULL },
	11810	{ NAMCOT_3446,          NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::namcot3446_w),          NULL, NULL, NULL },
	11811	{ NAMCOT_3453,          NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::namcot3453_w),          NULL, NULL, NULL },
	11812	{ STD_EXROM,            {write8_delegate(FUNC(nes_state::exrom_l_w),(nes_state *)0), read8_delegate(FUNC(nes_state::exrom_l_r),(nes_state *)0)}, NES_NOACCESS, NES_NOACCESS,               NULL, NULL, mmc5_irq },
	11813	{ NES_QJ,               NES_NOACCESS, NES_WRITEONLY(nes_state::qj_m_w), NES_WRITEONLY(nes_state::txrom_w),      NULL, NULL, mmc3_irq },
	11814	{ PAL_ZZ,               NES_NOACCESS, NES_WRITEONLY(nes_state::zz_m_w), NES_WRITEONLY(nes_state::txrom_w),      NULL, NULL, mmc3_irq },
	11815	{ UXROM_CC,             NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::uxrom_cc_w),            NULL, NULL, NULL },
11988	11816	//
11989		{ DIS_74X139X74,        NES_NOACCESS, NES_WRITEONLY(dis_74x139x74_m_w), NES_NOACCESS,     NULL, NULL, NULL },
11990		{ DIS_74X377,           NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(dis_74x377_w),          NULL, NULL, NULL },
11991		{ DIS_74X161X161X32,    NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(dis_74x161x161x32_w),   NULL, NULL, NULL },
11992		{ DIS_74X161X138,       NES_NOACCESS, NES_WRITEONLY(dis_74x161x138_m_w), NES_NOACCESS,    NULL, NULL, NULL },
11993		{ BANDAI_LZ93,          NES_NOACCESS, NES_WRITEONLY(lz93d50_m_w), NES_WRITEONLY(lz93d50_w), NULL, NULL, bandai_lz_irq },
11994		{ BANDAI_LZ93EX,        NES_NOACCESS, NES_WRITEONLY(lz93d50_m_w), NES_WRITEONLY(lz93d50_w), NULL, NULL, bandai_lz_irq },
11995		{ BANDAI_FCG,           NES_NOACCESS, NES_WRITEONLY(lz93d50_m_w), NES_WRITEONLY(lz93d50_w), NULL, NULL, bandai_lz_irq },
11996		{ BANDAI_DATACH,        NES_NOACCESS, NES_WRITEONLY(lz93d50_m_w), NES_WRITEONLY(lz93d50_w), NULL, NULL, bandai_lz_irq },
11997		{ BANDAI_JUMP2,         NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(fjump2_w),              NULL, NULL, bandai_lz_irq },
11998		{ BANDAI_KARAOKE,       NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(bandai_ks_w),           NULL, NULL, NULL },
11999		{ BANDAI_OEKAKIDS,      NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(bandai_ok_w),           NULL, NULL, NULL },
12000		{ IREM_G101,            NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(g101_w),                NULL, NULL, NULL },
12001		{ IREM_LROG017,         NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(lrog017_w),             NULL, NULL, NULL },
12002		{ IREM_H3001,           NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(h3001_w),               NULL, NULL, h3001_irq },
12003		{ IREM_TAM_S1,          NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(tam_s1_w),              NULL, NULL, NULL },
12004		{ IREM_HOLYDIV,         NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(irem_hd_w),             NULL, NULL, NULL },
12005		{ JALECO_SS88006,       NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(ss88006_w),             NULL, NULL, ss88006_irq },
12006		{ JALECO_JF11,          NES_NOACCESS, NES_WRITEONLY(jf11_m_w), NES_NOACCESS,              NULL, NULL, NULL },
12007		{ JALECO_JF13,          NES_NOACCESS, NES_WRITEONLY(jf13_m_w), NES_NOACCESS,              NULL, NULL, NULL },
12008		{ JALECO_JF16,          NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(jf16_w),                NULL, NULL, NULL },
12009		{ JALECO_JF17,          NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(jf17_w),                NULL, NULL, NULL },
12010		{ JALECO_JF19,          NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(jf19_w),                NULL, NULL, NULL },
12011		{ KONAMI_VRC1,          NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(konami_vrc1_w),         NULL, NULL, NULL },
12012		{ KONAMI_VRC2,          NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(konami_vrc2_w),         NULL, NULL, NULL },
12013		{ KONAMI_VRC3,          NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(konami_vrc3_w),         NULL, NULL, konami_irq },
12014		{ KONAMI_VRC4,          NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(konami_vrc4_w),         NULL, NULL, konami_irq },
12015		{ KONAMI_VRC6,          NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(konami_vrc6_w),         NULL, NULL, konami_irq },
12016		{ KONAMI_VRC7,          NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(konami_vrc7_w),         NULL, NULL, konami_irq },
12017		{ NAMCOT_163,           {FUNC(namcot163_l_w), FUNC(namcot163_l_r) }, NES_NOACCESS, NES_WRITEONLY(namcot163_w), NULL, NULL, namcot_irq },
12018		{ SUNSOFT_1,            NES_NOACCESS, NES_WRITEONLY(sunsoft1_m_w), NES_NOACCESS,          NULL, NULL, NULL },
12019		{ SUNSOFT_2,            NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(sunsoft2_w),            NULL, NULL, NULL },
12020		{ SUNSOFT_3,            NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(sunsoft3_w),            NULL, NULL, sunsoft3_irq },
12021		{ TAITO_TC0190FMC,      NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(tc0190fmc_w),           NULL, NULL, NULL },
12022		{ TAITO_TC0190FMCP,     NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(tc0190fmc_p16_w),       NULL, NULL, mmc3_irq },
12023		{ TAITO_X1_005,         NES_NOACCESS, {FUNC(x1005_m_w), FUNC(x1005_m_r)}, NES_NOACCESS,               NULL, NULL, NULL },
12024		{ TAITO_X1_005_A,       NES_NOACCESS, {FUNC(x1005a_m_w), FUNC(x1005_m_r)}, NES_NOACCESS,              NULL, NULL, NULL },
12025		{ TAITO_X1_017,         NES_NOACCESS, {FUNC(x1017_m_w), FUNC(x1017_m_r)}, NES_NOACCESS,               NULL, NULL, NULL },
	11817	{ DIS_74X139X74,        NES_NOACCESS, NES_WRITEONLY(nes_state::dis_74x139x74_m_w), NES_NOACCESS,     NULL, NULL, NULL },
	11818	{ DIS_74X377,           NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::dis_74x377_w),          NULL, NULL, NULL },
	11819	{ DIS_74X161X161X32,    NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::dis_74x161x161x32_w),   NULL, NULL, NULL },
	11820	{ DIS_74X161X138,       NES_NOACCESS, NES_WRITEONLY(nes_state::dis_74x161x138_m_w), NES_NOACCESS,    NULL, NULL, NULL },
	11821	{ BANDAI_LZ93,          NES_NOACCESS, NES_WRITEONLY(nes_state::lz93d50_m_w), NES_WRITEONLY(nes_state::lz93d50_w), NULL, NULL, bandai_lz_irq },
	11822	{ BANDAI_LZ93EX,        NES_NOACCESS, NES_WRITEONLY(nes_state::lz93d50_m_w), NES_WRITEONLY(nes_state::lz93d50_w), NULL, NULL, bandai_lz_irq },
	11823	{ BANDAI_FCG,           NES_NOACCESS, NES_WRITEONLY(nes_state::lz93d50_m_w), NES_WRITEONLY(nes_state::lz93d50_w), NULL, NULL, bandai_lz_irq },
	11824	{ BANDAI_DATACH,        NES_NOACCESS, NES_WRITEONLY(nes_state::lz93d50_m_w), NES_WRITEONLY(nes_state::lz93d50_w), NULL, NULL, bandai_lz_irq },
	11825	{ BANDAI_JUMP2,         NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::fjump2_w),              NULL, NULL, bandai_lz_irq },
	11826	{ BANDAI_KARAOKE,       NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::bandai_ks_w),           NULL, NULL, NULL },
	11827	{ BANDAI_OEKAKIDS,      NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::bandai_ok_w),           NULL, NULL, NULL },
	11828	{ IREM_G101,            NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::g101_w),                NULL, NULL, NULL },
	11829	{ IREM_LROG017,         NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::lrog017_w),             NULL, NULL, NULL },
	11830	{ IREM_H3001,           NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::h3001_w),               NULL, NULL, h3001_irq },
	11831	{ IREM_TAM_S1,          NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::tam_s1_w),              NULL, NULL, NULL },
	11832	{ IREM_HOLYDIV,         NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::irem_hd_w),             NULL, NULL, NULL },
	11833	{ JALECO_SS88006,       NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::ss88006_w),             NULL, NULL, ss88006_irq },
	11834	{ JALECO_JF11,          NES_NOACCESS, NES_WRITEONLY(nes_state::jf11_m_w), NES_NOACCESS,              NULL, NULL, NULL },
	11835	{ JALECO_JF13,          NES_NOACCESS, NES_WRITEONLY(nes_state::jf13_m_w), NES_NOACCESS,              NULL, NULL, NULL },
	11836	{ JALECO_JF16,          NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::jf16_w),                NULL, NULL, NULL },
	11837	{ JALECO_JF17,          NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::jf17_w),                NULL, NULL, NULL },
	11838	{ JALECO_JF19,          NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::jf19_w),                NULL, NULL, NULL },
	11839	{ KONAMI_VRC1,          NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::konami_vrc1_w),         NULL, NULL, NULL },
	11840	{ KONAMI_VRC2,          NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::konami_vrc2_w),         NULL, NULL, NULL },
	11841	{ KONAMI_VRC3,          NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::konami_vrc3_w),         NULL, NULL, konami_irq },
	11842	{ KONAMI_VRC4,          NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::konami_vrc4_w),         NULL, NULL, konami_irq },
	11843	{ KONAMI_VRC6,          NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::konami_vrc6_w),         NULL, NULL, konami_irq },
	11844	{ KONAMI_VRC7,          NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::konami_vrc7_w),         NULL, NULL, konami_irq },
	11845	{ NAMCOT_163,           {write8_delegate(FUNC(nes_state::namcot163_l_w),(nes_state *)0), read8_delegate(FUNC(nes_state::namcot163_l_r),(nes_state *)0)}, NES_NOACCESS, NES_WRITEONLY(nes_state::namcot163_w), NULL, NULL, namcot_irq },
	11846	{ SUNSOFT_1,            NES_NOACCESS, NES_WRITEONLY(nes_state::sunsoft1_m_w), NES_NOACCESS,          NULL, NULL, NULL },
	11847	{ SUNSOFT_2,            NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::sunsoft2_w),            NULL, NULL, NULL },
	11848	{ SUNSOFT_3,            NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::sunsoft3_w),            NULL, NULL, sunsoft3_irq },
	11849	{ TAITO_TC0190FMC,      NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::tc0190fmc_w),           NULL, NULL, NULL },
	11850	{ TAITO_TC0190FMCP,     NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::tc0190fmc_p16_w),       NULL, NULL, mmc3_irq },
	11851	{ TAITO_X1_005,         NES_NOACCESS, {write8_delegate(FUNC(nes_state::x1005_m_w),(nes_state *)0), read8_delegate(FUNC(nes_state::x1005_m_r),(nes_state *)0)}, NES_NOACCESS,               NULL, NULL, NULL },
	11852	{ TAITO_X1_005_A,       NES_NOACCESS, {write8_delegate(FUNC(nes_state::x1005a_m_w),(nes_state *)0), read8_delegate(FUNC(nes_state::x1005_m_r),(nes_state *)0)}, NES_NOACCESS,              NULL, NULL, NULL },
	11853	{ TAITO_X1_017,         NES_NOACCESS, {write8_delegate(FUNC(nes_state::x1017_m_w),(nes_state *)0), read8_delegate(FUNC(nes_state::x1017_m_r),(nes_state *)0)}, NES_NOACCESS,               NULL, NULL, NULL },
12026	11854	//
12027		{ AGCI_50282,           NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(agci_50282_w),          NULL, NULL, NULL },
12028		{ ACTENT_ACT52,         NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(ae_act52_w),            NULL, NULL, NULL },
12029		{ AVE_NINA01,           NES_NOACCESS, NES_WRITEONLY(nina01_m_w), NES_NOACCESS,            NULL, NULL, NULL },
12030		{ AVE_NINA06,           NES_WRITEONLY(nina06_l_w), NES_NOACCESS, NES_NOACCESS,            NULL, NULL, NULL },
12031		{ CNE_DECATHLON,        NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(cne_decathl_w),         NULL, NULL, NULL },
12032		{ CNE_FSB,              NES_NOACCESS, NES_WRITEONLY(cne_fsb_m_w), NES_NOACCESS,           NULL, NULL, NULL },
12033		{ CNE_SHLZ,             NES_WRITEONLY(cne_shlz_l_w), NES_NOACCESS, NES_NOACCESS,          NULL, NULL, NULL },
12034		{ CALTRON_6IN1,         NES_NOACCESS, NES_WRITEONLY(caltron6in1_m_w), NES_WRITEONLY(caltron6in1_w),      NULL, NULL, NULL },
12035		{ CAMERICA_BF9093,      NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(bf9093_w),              NULL, NULL, NULL },
12036		{ CAMERICA_BF9097,      NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(bf9093_w),              NULL, NULL, NULL },
12037		{ CAMERICA_BF9096,      NES_NOACCESS, NES_WRITEONLY(bf9096_w), NES_WRITEONLY(bf9096_w),   NULL, NULL, NULL },
12038		{ CAMERICA_GOLDENFIVE,  NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(golden5_w),             NULL, NULL, NULL },
12039		{ CONY_BOARD,           {FUNC(cony_l_w), FUNC(cony_l_r)}, NES_NOACCESS, NES_WRITEONLY(cony_w),        NULL, NULL, sunsoft3_irq },
12040		{ YOKO_BOARD,           {FUNC(yoko_l_w), FUNC(yoko_l_r)}, NES_NOACCESS, NES_WRITEONLY(yoko_w),        NULL, NULL, sunsoft3_irq },
12041		{ DREAMTECH_BOARD,      NES_WRITEONLY(dreamtech_l_w), NES_NOACCESS, NES_NOACCESS,         NULL, NULL, NULL },
12042		{ FUTUREMEDIA_BOARD,    NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(futuremedia_w),         NULL, NULL, futuremedia_irq },
12043		{ FUKUTAKE_BOARD,       {FUNC(fukutake_l_w), FUNC(fukutake_l_r)}, NES_NOACCESS, NES_NOACCESS,         NULL, NULL, NULL },
12044		{ GOUDER_37017,         {FUNC(gouder_sf4_l_w), FUNC(gouder_sf4_l_r)}, NES_NOACCESS, NES_WRITEONLY(txrom_w), NULL, NULL, mmc3_irq },
12045		{ HENGEDIANZI_BOARD,    NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(henggedianzi_w),        NULL, NULL, NULL },
12046		{ HENGEDIANZI_XJZB,     NES_WRITEONLY(heng_xjzb_l_w), NES_NOACCESS, NES_WRITEONLY(heng_xjzb_w), NULL, NULL, NULL },
12047		{ HES6IN1_BOARD,        NES_WRITEONLY(hes6in1_l_w), NES_NOACCESS, NES_NOACCESS,           NULL, NULL, NULL },
12048		{ HES_BOARD,            NES_WRITEONLY(hes_l_w), NES_NOACCESS, NES_NOACCESS,               NULL, NULL, NULL },
12049		{ HOSENKAN_BOARD,       NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(hosenkan_w),            NULL, NULL, mmc3_irq },
12050		{ KAISER_KS7058,        NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(ks7058_w),              NULL, NULL, NULL },
12051		{ KAISER_KS7022,        NES_NOACCESS, NES_NOACCESS, {FUNC(ks7022_w), FUNC(ks7022_r)},                 NULL, NULL, NULL },
12052		{ KAISER_KS7032,        NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(ks7032_w),              NULL, NULL, ks7032_irq },
12053		{ KAISER_KS202,         NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(ks202_w),               NULL, NULL, ks7032_irq },
12054		{ KAISER_KS7017,      NES_WRITEONLY(ks7017_l_w), NES_NOACCESS, NES_NOACCESS,            NULL, NULL, mmc_fds_irq },
12055		{ KAY_PANDAPRINCE,      {FUNC(kay_pp_l_w), FUNC(kay_pp_l_r)}, NES_NOACCESS, NES_WRITEONLY(kay_pp_w),  NULL, NULL, mmc3_irq },
12056		{ KASING_BOARD,         NES_NOACCESS, NES_WRITEONLY(kasing_m_w), NES_WRITEONLY(txrom_w),  NULL, NULL, mmc3_irq },
12057		{ SACHEN_74LS374,       {FUNC(sachen_74x374_l_w), FUNC(sachen_74x374_l_r)}, NES_NOACCESS, NES_NOACCESS, NULL, NULL, NULL },
12058		{ SACHEN_74LS374_A,     NES_WRITEONLY(sachen_74x374a_l_w), NES_NOACCESS, NES_NOACCESS,    NULL, NULL, NULL },
12059		{ SACHEN_8259A,         NES_WRITEONLY(s8259_l_w), NES_WRITEONLY(s8259_m_w), NES_NOACCESS, NULL, NULL, NULL },
12060		{ SACHEN_8259B,         NES_WRITEONLY(s8259_l_w), NES_WRITEONLY(s8259_m_w), NES_NOACCESS, NULL, NULL, NULL },
12061		{ SACHEN_8259C,         NES_WRITEONLY(s8259_l_w), NES_WRITEONLY(s8259_m_w), NES_NOACCESS, NULL, NULL, NULL },
12062		{ SACHEN_8259D,         NES_WRITEONLY(s8259_l_w), NES_WRITEONLY(s8259_m_w), NES_NOACCESS, NULL, NULL, NULL },
12063		{ SACHEN_SA009,         NES_WRITEONLY(sa009_l_w), NES_NOACCESS, NES_NOACCESS,             NULL, NULL, NULL },
12064		{ SACHEN_SA0036,        NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(sa0036_w),              NULL, NULL, NULL },
12065		{ SACHEN_SA0037,        NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(sa0037_w),              NULL, NULL, NULL },
12066		{ SACHEN_SA72007,       NES_WRITEONLY(sa72007_l_w), NES_NOACCESS, NES_NOACCESS,           NULL, NULL, NULL },
12067		{ SACHEN_SA72008,       NES_WRITEONLY(sa72008_l_w), NES_NOACCESS, NES_NOACCESS,           NULL, NULL, NULL },
12068		{ SACHEN_TCA01,         NES_READONLY(tca01_l_r), NES_NOACCESS, NES_NOACCESS,              NULL, NULL, NULL },
12069		{ SACHEN_TCU01,         NES_WRITEONLY(tcu01_l_w), NES_WRITEONLY(tcu01_m_w), NES_WRITEONLY(tcu01_w), NULL, NULL, NULL },
12070		{ SACHEN_TCU02,         {FUNC(tcu02_l_w), FUNC(tcu02_l_r)}, NES_NOACCESS, NES_NOACCESS,               NULL, NULL, NULL },
12071		{ SUBOR_TYPE0,          NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(subor0_w),              NULL, NULL, NULL },
12072		{ SUBOR_TYPE1,          NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(subor1_w),              NULL, NULL, NULL },
12073		{ MAGICSERIES_MD,       NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(magics_md_w),           NULL, NULL, NULL },
12074		{ NANJING_BOARD,        {FUNC(nanjing_l_w), FUNC(nanjing_l_r)}, NES_NOACCESS, NES_NOACCESS,           NULL, NULL, nanjing_irq },
12075		{ NITRA_TDA,            NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nitra_w),               NULL, NULL, mmc3_irq },
12076		{ NTDEC_ASDER,          NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(ntdec_asder_w),         NULL, NULL, NULL },
12077		{ NTDEC_FIGHTINGHERO,   NES_NOACCESS, NES_WRITEONLY(ntdec_fh_m_w), NES_NOACCESS,          NULL, NULL, NULL },
12078		{ OPENCORP_DAOU306,     NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(daou306_w),             NULL, NULL, NULL },
12079		{ RCM_GS2015,           NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(gs2015_w),              NULL, NULL, NULL },
12080		{ RCM_TETRISFAMILY,     NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(rcm_tf_w),              NULL, NULL, NULL },
12081		{ REXSOFT_DBZ5,         {FUNC(rex_dbz_l_w), FUNC(rex_dbz_l_r)}, NES_READONLY(rex_dbz_l_r), NES_WRITEONLY(txrom_w), NULL, NULL, mmc3_irq },
12082		{ REXSOFT_SL1632,       NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(rex_sl1632_w),          NULL, NULL, mmc3_irq },
12083		{ RUMBLESTATION_BOARD,  NES_NOACCESS, NES_WRITEONLY(rumblestation_m_w), NES_WRITEONLY(rumblestation_w),      NULL, NULL, NULL },
12084		{ SOMERI_SL12,          NES_WRITEONLY(someri_l_w), NES_NOACCESS, NES_WRITEONLY(someri_w), NULL, NULL, mmc3_irq },
12085		{ SUPERGAME_BOOGERMAN,  NES_WRITEONLY(sgame_boog_l_w), NES_WRITEONLY(sgame_boog_m_w), NES_WRITEONLY(sgame_boog_w), NULL, NULL, mmc3_irq },
12086		{ SUPERGAME_LIONKING,   NES_NOACCESS, NES_WRITEONLY(sgame_lion_m_w), NES_WRITEONLY(sgame_lion_w), NULL, NULL, mmc3_irq },
12087		{ TENGEN_800008,        NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(tengen_800008_w),       NULL, NULL, NULL },
12088		{ TENGEN_800032,        NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(tengen_800032_w),       NULL, NULL, tengen_800032_irq },
12089		{ TENGEN_800037,        NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(tengen_800037_w),       NULL, NULL, tengen_800032_irq },
12090		{ TXC_22211A,           {FUNC(txc_22211_l_w), FUNC(txc_22211_l_r)}, NES_NOACCESS, NES_WRITEONLY(txc_22211_w), NULL, NULL, NULL },
12091		{ TXC_22211B,           {FUNC(txc_22211_l_w), FUNC(txc_22211_l_r)}, NES_NOACCESS, NES_WRITEONLY(txc_22211b_w), NULL, NULL, NULL },
12092		{ TXC_22211C,           {FUNC(txc_22211_l_w), FUNC(txc_22211c_l_r)}, NES_NOACCESS, NES_WRITEONLY(txc_22211_w), NULL, NULL, NULL },
12093		{ TXC_TW,               NES_WRITEONLY(txc_tw_l_w), NES_WRITEONLY(txc_tw_m_w), NES_WRITEONLY(txrom_w), NULL, NULL, mmc3_irq },
12094		{ TXC_STRIKEWOLF,       NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(txc_strikewolf_w),      NULL, NULL, NULL },
12095		{ TXC_MXMDHTWO,         NES_READONLY(txc_mxmdhtwo_l_r), NES_NOACCESS, NES_WRITEONLY(txc_mxmdhtwo_w), NULL, NULL, NULL },
12096		{ WAIXING_TYPE_A,       NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(waixing_a_w),           NULL, NULL, mmc3_irq },
12097		{ WAIXING_TYPE_A_1,     NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(waixing_a_w),           NULL, NULL, mmc3_irq },
12098		{ WAIXING_TYPE_B,       NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(waixing_a_w),           NULL, NULL, mmc3_irq },
12099		{ WAIXING_TYPE_C,       NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(waixing_a_w),           NULL, NULL, mmc3_irq },
12100		{ WAIXING_TYPE_D,       NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(waixing_a_w),           NULL, NULL, mmc3_irq },
12101		{ WAIXING_TYPE_E,       NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(waixing_a_w),           NULL, NULL, mmc3_irq },
12102		{ WAIXING_TYPE_F,       NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(waixing_f_w),           NULL, NULL, mmc3_irq },
12103		{ WAIXING_TYPE_G,       NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(waixing_g_w),           NULL, NULL, mmc3_irq },
12104		{ WAIXING_TYPE_H,       NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(waixing_h_w),           NULL, NULL, mmc3_irq },
12105		{ WAIXING_TYPE_I,       NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(txrom_w),               NULL, NULL, mmc3_irq },   // this is MMC3 + possibly additional WRAM added in 0x5000-0x5fff
12106		{ WAIXING_TYPE_J,       NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(txrom_w),               NULL, NULL, mmc3_irq },   // this is MMC3 + possibly additional WRAM added in 0x5000-0x5fff
12107		{ WAIXING_SGZ,          NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(waixing_sgz_w),         NULL, NULL, konami_irq },
12108		{ WAIXING_SGZLZ,        NES_WRITEONLY(waixing_sgzlz_l_w), NES_NOACCESS, NES_NOACCESS,     NULL, NULL, NULL },
12109		{ WAIXING_FFV,          NES_WRITEONLY(waixing_ffv_l_w), NES_NOACCESS, NES_NOACCESS,       NULL, NULL, NULL },
12110		{ WAIXING_ZS,           NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(waixing_zs_w),          NULL, NULL, NULL },
12111		{ WAIXING_DQ8,          NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(waixing_dq8_w),         NULL, NULL, NULL },
12112		{ WAIXING_SECURITY,     NES_WRITEONLY(waixing_sec_l_w), NES_NOACCESS, NES_WRITEONLY(txrom_w), NULL, NULL, mmc3_irq },
12113		{ WAIXING_SH2,          NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(txrom_w),               NULL, NULL, mmc3_irq },   // this is MMC3 + possibly additional WRAM added in 0x5000-0x5fff
12114		{ WAIXING_PS2,          NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(waixing_ps2_w),         NULL, NULL, NULL },
12115		{ UNL_8237,             NES_WRITEONLY(unl_8237_l_w), NES_NOACCESS, NES_WRITEONLY(unl_8237_w),      NULL, NULL, mmc3_irq },
12116		{ UNL_AX5705,           NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(unl_ax5705_w),          NULL, NULL, NULL },
12117		{ UNL_CC21,             NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(unl_cc21_w),            NULL, NULL, NULL },
12118		{ UNL_KOF97,            NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(unl_kof97_w),           NULL, NULL, mmc3_irq },
12119		{ UNL_KS7057,           NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(ks7057_w),              NULL, NULL, mmc3_irq },
12120		{ UNL_T230,             NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(unl_t230_w),            NULL, NULL, konami_irq },
12121		{ UNL_KOF96,            {FUNC(kof96_l_w), FUNC(kof96_l_r)}, NES_NOACCESS, NES_WRITEONLY(kof96_w),     NULL, NULL, mmc3_irq },
12122		{ UNL_MK2,              NES_NOACCESS, NES_WRITEONLY(mk2_m_w), NES_NOACCESS,               NULL, NULL, mmc3_irq },
12123		{ UNL_N625092,          NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(n625092_w),             NULL, NULL, NULL },
12124		{ UNL_SC127,            NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(sc127_w),               NULL, NULL, sc127_irq },
12125		{ UNL_SMB2J,            NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(smb2j_w),               NULL, NULL, NULL },
12126		{ UNL_SUPERFIGHTER3,    NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(unl_sf3_w),             NULL, NULL, mmc3_irq },
12127		{ UNL_XZY,              NES_WRITEONLY(unl_xzy_l_w), NES_NOACCESS, NES_NOACCESS,           NULL, NULL, NULL },
12128		{ UNL_RACERMATE,        NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(unl_racmate_w),         NULL, NULL, NULL },
12129		{ UNL_STUDYNGAME,       NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(sng32_w),               NULL, NULL, NULL },
12130		{ UNL_603_5052,         {FUNC(unl_6035052_extra_w), FUNC(unl_6035052_extra_r)}, {FUNC(unl_6035052_extra_w), FUNC(unl_6035052_extra_r)}, NES_WRITEONLY(txrom_w), NULL, NULL, mmc3_irq },
12131		{ UNL_EDU2K,            NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(edu2k_w),               NULL, NULL, NULL },
12132		{ UNL_SHJY3,            NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(shjy3_w),               NULL, NULL, shjy3_irq },
12133		{ UNL_H2288,            {FUNC(h2288_l_w), FUNC(h2288_l_r)}, NES_NOACCESS, NES_WRITEONLY(h2288_w),     NULL, NULL, mmc3_irq },
12134		{ UNL_FS304,            NES_WRITEONLY(unl_fs304_l_w), NES_NOACCESS, NES_NOACCESS,         NULL, NULL, NULL },
	11855	{ AGCI_50282,           NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::agci_50282_w),          NULL, NULL, NULL },
	11856	{ ACTENT_ACT52,         NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::ae_act52_w),            NULL, NULL, NULL },
	11857	{ AVE_NINA01,           NES_NOACCESS, NES_WRITEONLY(nes_state::nina01_m_w), NES_NOACCESS,            NULL, NULL, NULL },
	11858	{ AVE_NINA06,           NES_WRITEONLY(nes_state::nina06_l_w), NES_NOACCESS, NES_NOACCESS,            NULL, NULL, NULL },
	11859	{ CNE_DECATHLON,        NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::cne_decathl_w),         NULL, NULL, NULL },
	11860	{ CNE_FSB,              NES_NOACCESS, NES_WRITEONLY(nes_state::cne_fsb_m_w), NES_NOACCESS,           NULL, NULL, NULL },
	11861	{ CNE_SHLZ,             NES_WRITEONLY(nes_state::cne_shlz_l_w), NES_NOACCESS, NES_NOACCESS,          NULL, NULL, NULL },
	11862	{ CALTRON_6IN1,         NES_NOACCESS, NES_WRITEONLY(nes_state::caltron6in1_m_w), NES_WRITEONLY(nes_state::caltron6in1_w),      NULL, NULL, NULL },
	11863	{ CAMERICA_BF9093,      NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::bf9093_w),              NULL, NULL, NULL },
	11864	{ CAMERICA_BF9097,      NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::bf9093_w),              NULL, NULL, NULL },
	11865	{ CAMERICA_BF9096,      NES_NOACCESS, NES_WRITEONLY(nes_state::bf9096_w), NES_WRITEONLY(nes_state::bf9096_w),   NULL, NULL, NULL },
	11866	{ CAMERICA_GOLDENFIVE,  NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::golden5_w),             NULL, NULL, NULL },
	11867	{ CONY_BOARD,           {write8_delegate(FUNC(nes_state::cony_l_w),(nes_state *)0), read8_delegate(FUNC(nes_state::cony_l_r),(nes_state *)0)}, NES_NOACCESS, NES_WRITEONLY(nes_state::cony_w),        NULL, NULL, sunsoft3_irq },
	11868	{ YOKO_BOARD,           {write8_delegate(FUNC(nes_state::yoko_l_w),(nes_state *)0), read8_delegate(FUNC(nes_state::yoko_l_r),(nes_state *)0)}, NES_NOACCESS, NES_WRITEONLY(nes_state::yoko_w),        NULL, NULL, sunsoft3_irq },
	11869	{ DREAMTECH_BOARD,      NES_WRITEONLY(nes_state::dreamtech_l_w), NES_NOACCESS, NES_NOACCESS,         NULL, NULL, NULL },
	11870	{ FUTUREMEDIA_BOARD,    NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::futuremedia_w),         NULL, NULL, futuremedia_irq },
	11871	{ FUKUTAKE_BOARD,       {write8_delegate(FUNC(nes_state::fukutake_l_w),(nes_state *)0), read8_delegate(FUNC(nes_state::fukutake_l_r),(nes_state *)0)}, NES_NOACCESS, NES_NOACCESS,         NULL, NULL, NULL },
	11872	{ GOUDER_37017,         {write8_delegate(FUNC(nes_state::gouder_sf4_l_w),(nes_state *)0), read8_delegate(FUNC(nes_state::gouder_sf4_l_r),(nes_state *)0)}, NES_NOACCESS, NES_WRITEONLY(nes_state::txrom_w), NULL, NULL, mmc3_irq },
	11873	{ HENGEDIANZI_BOARD,    NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::henggedianzi_w),        NULL, NULL, NULL },
	11874	{ HENGEDIANZI_XJZB,     NES_WRITEONLY(nes_state::heng_xjzb_l_w), NES_NOACCESS, NES_WRITEONLY(nes_state::heng_xjzb_w), NULL, NULL, NULL },
	11875	{ HES6IN1_BOARD,        NES_WRITEONLY(nes_state::hes6in1_l_w), NES_NOACCESS, NES_NOACCESS,           NULL, NULL, NULL },
	11876	{ HES_BOARD,            NES_WRITEONLY(nes_state::hes_l_w), NES_NOACCESS, NES_NOACCESS,               NULL, NULL, NULL },
	11877	{ HOSENKAN_BOARD,       NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::hosenkan_w),            NULL, NULL, mmc3_irq },
	11878	{ KAISER_KS7058,        NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::ks7058_w),              NULL, NULL, NULL },
	11879	{ KAISER_KS7022,        NES_NOACCESS, NES_NOACCESS, {write8_delegate(FUNC(nes_state::ks7022_w),(nes_state *)0), read8_delegate(FUNC(nes_state::ks7022_r),(nes_state *)0)},                 NULL, NULL, NULL },
	11880	{ KAISER_KS7032,        NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::ks7032_w),              NULL, NULL, ks7032_irq },
	11881	{ KAISER_KS202,         NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::ks202_w),               NULL, NULL, ks7032_irq },
	11882	{ KAISER_KS7017,      NES_WRITEONLY(nes_state::ks7017_l_w), NES_NOACCESS, NES_NOACCESS,            NULL, NULL, mmc_fds_irq },
	11883	{ KAY_PANDAPRINCE,      {write8_delegate(FUNC(nes_state::kay_pp_l_w),(nes_state *)0), read8_delegate(FUNC(nes_state::kay_pp_l_r),(nes_state *)0)}, NES_NOACCESS, NES_WRITEONLY(nes_state::kay_pp_w),  NULL, NULL, mmc3_irq },
	11884	{ KASING_BOARD,         NES_NOACCESS, NES_WRITEONLY(nes_state::kasing_m_w), NES_WRITEONLY(nes_state::txrom_w),  NULL, NULL, mmc3_irq },
	11885	{ SACHEN_74LS374,       {write8_delegate(FUNC(nes_state::sachen_74x374_l_w),(nes_state *)0), read8_delegate(FUNC(nes_state::sachen_74x374_l_r),(nes_state *)0)}, NES_NOACCESS, NES_NOACCESS, NULL, NULL, NULL },
	11886	{ SACHEN_74LS374_A,     NES_WRITEONLY(nes_state::sachen_74x374a_l_w), NES_NOACCESS, NES_NOACCESS,    NULL, NULL, NULL },
	11887	{ SACHEN_8259A,         NES_WRITEONLY(nes_state::s8259_l_w), NES_WRITEONLY(nes_state::s8259_m_w), NES_NOACCESS, NULL, NULL, NULL },
	11888	{ SACHEN_8259B,         NES_WRITEONLY(nes_state::s8259_l_w), NES_WRITEONLY(nes_state::s8259_m_w), NES_NOACCESS, NULL, NULL, NULL },
	11889	{ SACHEN_8259C,         NES_WRITEONLY(nes_state::s8259_l_w), NES_WRITEONLY(nes_state::s8259_m_w), NES_NOACCESS, NULL, NULL, NULL },
	11890	{ SACHEN_8259D,         NES_WRITEONLY(nes_state::s8259_l_w), NES_WRITEONLY(nes_state::s8259_m_w), NES_NOACCESS, NULL, NULL, NULL },
	11891	{ SACHEN_SA009,         NES_WRITEONLY(nes_state::sa009_l_w), NES_NOACCESS, NES_NOACCESS,             NULL, NULL, NULL },
	11892	{ SACHEN_SA0036,        NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::sa0036_w),              NULL, NULL, NULL },
	11893	{ SACHEN_SA0037,        NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::sa0037_w),              NULL, NULL, NULL },
	11894	{ SACHEN_SA72007,       NES_WRITEONLY(nes_state::sa72007_l_w), NES_NOACCESS, NES_NOACCESS,           NULL, NULL, NULL },
	11895	{ SACHEN_SA72008,       NES_WRITEONLY(nes_state::sa72008_l_w), NES_NOACCESS, NES_NOACCESS,           NULL, NULL, NULL },
	11896	{ SACHEN_TCA01,         NES_READONLY(nes_state::tca01_l_r), NES_NOACCESS, NES_NOACCESS,              NULL, NULL, NULL },
	11897	{ SACHEN_TCU01,         NES_WRITEONLY(nes_state::tcu01_l_w), NES_WRITEONLY(nes_state::tcu01_m_w), NES_WRITEONLY(nes_state::tcu01_w), NULL, NULL, NULL },
	11898	{ SACHEN_TCU02,         {write8_delegate(FUNC(nes_state::tcu02_l_w),(nes_state *)0), read8_delegate(FUNC(nes_state::tcu02_l_r),(nes_state *)0)}, NES_NOACCESS, NES_NOACCESS,               NULL, NULL, NULL },
	11899	{ SUBOR_TYPE0,          NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::subor0_w),              NULL, NULL, NULL },
	11900	{ SUBOR_TYPE1,          NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::subor1_w),              NULL, NULL, NULL },
	11901	{ MAGICSERIES_MD,       NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::magics_md_w),           NULL, NULL, NULL },
	11902	{ NANJING_BOARD,        {write8_delegate(FUNC(nes_state::nanjing_l_w),(nes_state *)0), read8_delegate(FUNC(nes_state::nanjing_l_r),(nes_state *)0)}, NES_NOACCESS, NES_NOACCESS,           NULL, NULL, nanjing_irq },
	11903	{ NITRA_TDA,            NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::nitra_w),               NULL, NULL, mmc3_irq },
	11904	{ NTDEC_ASDER,          NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::ntdec_asder_w),         NULL, NULL, NULL },
	11905	{ NTDEC_FIGHTINGHERO,   NES_NOACCESS, NES_WRITEONLY(nes_state::ntdec_fh_m_w), NES_NOACCESS,          NULL, NULL, NULL },
	11906	{ OPENCORP_DAOU306,     NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::daou306_w),             NULL, NULL, NULL },
	11907	{ RCM_GS2015,           NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::gs2015_w),              NULL, NULL, NULL },
	11908	{ RCM_TETRISFAMILY,     NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::rcm_tf_w),              NULL, NULL, NULL },
	11909	{ REXSOFT_DBZ5,         {write8_delegate(FUNC(nes_state::rex_dbz_l_w),(nes_state *)0), read8_delegate(FUNC(nes_state::rex_dbz_l_r),(nes_state *)0)}, NES_READONLY(nes_state::rex_dbz_l_r), NES_WRITEONLY(nes_state::txrom_w), NULL, NULL, mmc3_irq },
	11910	{ REXSOFT_SL1632,       NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::rex_sl1632_w),          NULL, NULL, mmc3_irq },
	11911	{ RUMBLESTATION_BOARD,  NES_NOACCESS, NES_WRITEONLY(nes_state::rumblestation_m_w), NES_WRITEONLY(nes_state::rumblestation_w),      NULL, NULL, NULL },
	11912	{ SOMERI_SL12,          NES_WRITEONLY(nes_state::someri_l_w), NES_NOACCESS, NES_WRITEONLY(nes_state::someri_w), NULL, NULL, mmc3_irq },
	11913	{ SUPERGAME_BOOGERMAN,  NES_WRITEONLY(nes_state::sgame_boog_l_w), NES_WRITEONLY(nes_state::sgame_boog_m_w), NES_WRITEONLY(nes_state::sgame_boog_w), NULL, NULL, mmc3_irq },
	11914	{ SUPERGAME_LIONKING,   NES_NOACCESS, NES_WRITEONLY(nes_state::sgame_lion_m_w), NES_WRITEONLY(nes_state::sgame_lion_w), NULL, NULL, mmc3_irq },
	11915	{ TENGEN_800008,        NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::tengen_800008_w),       NULL, NULL, NULL },
	11916	{ TENGEN_800032,        NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::tengen_800032_w),       NULL, NULL, tengen_800032_irq },
	11917	{ TENGEN_800037,        NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::tengen_800037_w),       NULL, NULL, tengen_800032_irq },
	11918	{ TXC_22211A,           {write8_delegate(FUNC(nes_state::txc_22211_l_w),(nes_state *)0), read8_delegate(FUNC(nes_state::txc_22211_l_r),(nes_state *)0)}, NES_NOACCESS, NES_WRITEONLY(nes_state::txc_22211_w), NULL, NULL, NULL },
	11919	{ TXC_22211B,           {write8_delegate(FUNC(nes_state::txc_22211_l_w),(nes_state *)0), read8_delegate(FUNC(nes_state::txc_22211_l_r),(nes_state *)0)}, NES_NOACCESS, NES_WRITEONLY(nes_state::txc_22211b_w), NULL, NULL, NULL },
	11920	{ TXC_22211C,           {write8_delegate(FUNC(nes_state::txc_22211_l_w),(nes_state *)0), read8_delegate(FUNC(nes_state::txc_22211c_l_r),(nes_state *)0)}, NES_NOACCESS, NES_WRITEONLY(nes_state::txc_22211_w), NULL, NULL, NULL },
	11921	{ TXC_TW,               NES_WRITEONLY(nes_state::txc_tw_l_w), NES_WRITEONLY(nes_state::txc_tw_m_w), NES_WRITEONLY(nes_state::txrom_w), NULL, NULL, mmc3_irq },
	11922	{ TXC_STRIKEWOLF,       NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::txc_strikewolf_w),      NULL, NULL, NULL },
	11923	{ TXC_MXMDHTWO,         NES_READONLY(nes_state::txc_mxmdhtwo_l_r), NES_NOACCESS, NES_WRITEONLY(nes_state::txc_mxmdhtwo_w), NULL, NULL, NULL },
	11924	{ WAIXING_TYPE_A,       NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::waixing_a_w),           NULL, NULL, mmc3_irq },
	11925	{ WAIXING_TYPE_A_1,     NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::waixing_a_w),           NULL, NULL, mmc3_irq },
	11926	{ WAIXING_TYPE_B,       NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::waixing_a_w),           NULL, NULL, mmc3_irq },
	11927	{ WAIXING_TYPE_C,       NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::waixing_a_w),           NULL, NULL, mmc3_irq },
	11928	{ WAIXING_TYPE_D,       NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::waixing_a_w),           NULL, NULL, mmc3_irq },
	11929	{ WAIXING_TYPE_E,       NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::waixing_a_w),           NULL, NULL, mmc3_irq },
	11930	{ WAIXING_TYPE_F,       NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::waixing_f_w),           NULL, NULL, mmc3_irq },
	11931	{ WAIXING_TYPE_G,       NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::waixing_g_w),           NULL, NULL, mmc3_irq },
	11932	{ WAIXING_TYPE_H,       NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::waixing_h_w),           NULL, NULL, mmc3_irq },
	11933	{ WAIXING_TYPE_I,       NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::txrom_w),               NULL, NULL, mmc3_irq },   // this is MMC3 + possibly additional WRAM added in 0x5000-0x5fff
	11934	{ WAIXING_TYPE_J,       NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::txrom_w),               NULL, NULL, mmc3_irq },   // this is MMC3 + possibly additional WRAM added in 0x5000-0x5fff
	11935	{ WAIXING_SGZ,          NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::waixing_sgz_w),         NULL, NULL, konami_irq },
	11936	{ WAIXING_SGZLZ,        NES_WRITEONLY(nes_state::waixing_sgzlz_l_w), NES_NOACCESS, NES_NOACCESS,     NULL, NULL, NULL },
	11937	{ WAIXING_FFV,          NES_WRITEONLY(nes_state::waixing_ffv_l_w), NES_NOACCESS, NES_NOACCESS,       NULL, NULL, NULL },
	11938	{ WAIXING_ZS,           NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::waixing_zs_w),          NULL, NULL, NULL },
	11939	{ WAIXING_DQ8,          NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::waixing_dq8_w),         NULL, NULL, NULL },
	11940	{ WAIXING_SECURITY,     NES_WRITEONLY(nes_state::waixing_sec_l_w), NES_NOACCESS, NES_WRITEONLY(nes_state::txrom_w), NULL, NULL, mmc3_irq },
	11941	{ WAIXING_SH2,          NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::txrom_w),               NULL, NULL, mmc3_irq },   // this is MMC3 + possibly additional WRAM added in 0x5000-0x5fff
	11942	{ WAIXING_PS2,          NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::waixing_ps2_w),         NULL, NULL, NULL },
	11943	{ UNL_8237,             NES_WRITEONLY(nes_state::unl_8237_l_w), NES_NOACCESS, NES_WRITEONLY(nes_state::unl_8237_w),      NULL, NULL, mmc3_irq },
	11944	{ UNL_AX5705,           NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::unl_ax5705_w),          NULL, NULL, NULL },
	11945	{ UNL_CC21,             NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::unl_cc21_w),            NULL, NULL, NULL },
	11946	{ UNL_KOF97,            NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::unl_kof97_w),           NULL, NULL, mmc3_irq },
	11947	{ UNL_KS7057,           NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::ks7057_w),              NULL, NULL, mmc3_irq },
	11948	{ UNL_T230,             NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::unl_t230_w),            NULL, NULL, konami_irq },
	11949	{ UNL_KOF96,            {write8_delegate(FUNC(nes_state::kof96_l_w),(nes_state *)0), read8_delegate(FUNC(nes_state::kof96_l_r),(nes_state *)0)}, NES_NOACCESS, NES_WRITEONLY(nes_state::kof96_w),     NULL, NULL, mmc3_irq },
	11950	{ UNL_MK2,              NES_NOACCESS, NES_WRITEONLY(nes_state::mk2_m_w), NES_NOACCESS,               NULL, NULL, mmc3_irq },
	11951	{ UNL_N625092,          NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::n625092_w),             NULL, NULL, NULL },
	11952	{ UNL_SC127,            NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::sc127_w),               NULL, NULL, sc127_irq },
	11953	{ UNL_SMB2J,            NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::smb2j_w),               NULL, NULL, NULL },
	11954	{ UNL_SUPERFIGHTER3,    NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::unl_sf3_w),             NULL, NULL, mmc3_irq },
	11955	{ UNL_XZY,              NES_WRITEONLY(nes_state::unl_xzy_l_w), NES_NOACCESS, NES_NOACCESS,           NULL, NULL, NULL },
	11956	{ UNL_RACERMATE,        NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::unl_racmate_w),         NULL, NULL, NULL },
	11957	{ UNL_STUDYNGAME,       NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::sng32_w),               NULL, NULL, NULL },
	11958	{ UNL_603_5052,         {write8_delegate(FUNC(nes_state::unl_6035052_extra_w),(nes_state *)0), read8_delegate(FUNC(nes_state::unl_6035052_extra_r),(nes_state *)0)}, {write8_delegate(FUNC(nes_state::unl_6035052_extra_w),(nes_state *)0), read8_delegate(FUNC(nes_state::unl_6035052_extra_r),(nes_state *)0)}, NES_WRITEONLY(nes_state::txrom_w), NULL, NULL, mmc3_irq },
	11959	{ UNL_EDU2K,            NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::edu2k_w),               NULL, NULL, NULL },
	11960	{ UNL_SHJY3,            NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::shjy3_w),               NULL, NULL, shjy3_irq },
	11961	{ UNL_H2288,            {write8_delegate(FUNC(nes_state::h2288_l_w),(nes_state *)0), read8_delegate(FUNC(nes_state::h2288_l_r),(nes_state *)0)}, NES_NOACCESS, NES_WRITEONLY(nes_state::h2288_w),     NULL, NULL, mmc3_irq },
	11962	{ UNL_FS304,            NES_WRITEONLY(nes_state::unl_fs304_l_w), NES_NOACCESS, NES_NOACCESS,         NULL, NULL, NULL },
12135	11963	//
12136		{ BTL_AISENSHINICOL,    NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(btl_mariobaby_w),       NULL, NULL, NULL },
12137		{ BTL_DRAGONNINJA,      NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(btl_dn_w),              NULL, NULL, btl_dn_irq },
12138		{ BTL_MARIOBABY,        NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(btl_mariobaby_w),       NULL, NULL, NULL },
12139		{ BTL_SMB2A,            NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(btl_smb2a_w),           NULL, NULL, btl_smb2a_irq },
12140		{ BTL_SMB2B,            NES_WRITEONLY(smb2jb_l_w), NES_NOACCESS, NES_NOACCESS,            NULL, NULL, smb2jb_irq },
12141		{ BTL_SMB3,             NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(btl_smb3_w),            NULL, NULL, btl_smb3_irq },
12142		{ BTL_SUPERBROS11,      NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(btl_smb11_w),           NULL, NULL, mmc3_irq },
12143		{ BTL_TOBIDASE,         NES_WRITEONLY(btl_tobi_l_w), NES_NOACCESS, NES_NOACCESS,          NULL, NULL, NULL },
12144		{ BTL_PIKACHUY2K,       NES_NOACCESS, {FUNC(btl_pika_y2k_m_w), FUNC(btl_pika_y2k_m_r)}, NES_WRITEONLY(btl_pika_y2k_w),  NULL, NULL, mmc3_irq },
12145		{ WHIRLWIND_2706,       NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(whirl2706_w),           NULL, NULL, NULL },
	11964	{ BTL_AISENSHINICOL,    NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::btl_mariobaby_w),       NULL, NULL, NULL },
	11965	{ BTL_DRAGONNINJA,      NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::btl_dn_w),              NULL, NULL, btl_dn_irq },
	11966	{ BTL_MARIOBABY,        NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::btl_mariobaby_w),       NULL, NULL, NULL },
	11967	{ BTL_SMB2A,            NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::btl_smb2a_w),           NULL, NULL, btl_smb2a_irq },
	11968	{ BTL_SMB2B,            NES_WRITEONLY(nes_state::smb2jb_l_w), NES_NOACCESS, NES_NOACCESS,            NULL, NULL, smb2jb_irq },
	11969	{ BTL_SMB3,             NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::btl_smb3_w),            NULL, NULL, btl_smb3_irq },
	11970	{ BTL_SUPERBROS11,      NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::btl_smb11_w),           NULL, NULL, mmc3_irq },
	11971	{ BTL_TOBIDASE,         NES_WRITEONLY(nes_state::btl_tobi_l_w), NES_NOACCESS, NES_NOACCESS,          NULL, NULL, NULL },
	11972	{ BTL_PIKACHUY2K,       NES_NOACCESS, {write8_delegate(FUNC(nes_state::btl_pika_y2k_m_w),(nes_state *)0), read8_delegate(FUNC(nes_state::btl_pika_y2k_m_r),(nes_state *)0)}, NES_WRITEONLY(nes_state::btl_pika_y2k_w),  NULL, NULL, mmc3_irq },
	11973	{ WHIRLWIND_2706,       NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::whirl2706_w),           NULL, NULL, NULL },
12146	11974	//
12147		{ BMC_190IN1,           NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(bmc_190in1_w),          NULL, NULL, NULL },
12148		{ BMC_A65AS,            NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(bmc_a65as_w),           NULL, NULL, NULL },
12149		{ BMC_GS2004,           NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(bmc_gs2004_w),          NULL, NULL, NULL },
12150		{ BMC_GS2013,           NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(bmc_gs2013_w),          NULL, NULL, NULL },
12151		{ BMC_NOVELDIAMOND,     NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(novel1_w),              NULL, NULL, NULL },
12152		{ BMC_9999999IN1,       NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(novel2_w),              NULL, NULL, NULL },
12153		{ BMC_T262,             NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(bmc_t262_w),            NULL, NULL, NULL },
12154		{ BMC_WS,               NES_NOACCESS, NES_WRITEONLY(bmc_ws_m_w), NES_NOACCESS,            NULL, NULL, NULL },
12155		{ BMC_GKA,              NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(bmc_gka_w),             NULL, NULL, NULL },
12156		{ BMC_GKB,              NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(bmc_gkb_w),             NULL, NULL, NULL },
12157		{ BMC_SUPER_700IN1,     NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(bmc_super700in1_w),     NULL, NULL, NULL },
12158		{ BMC_36IN1,            NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(bmc_36in1_w),           NULL, NULL, NULL },
12159		{ BMC_21IN1,            NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(bmc_21in1_w),           NULL, NULL, NULL },
12160		{ BMC_150IN1,           NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(bmc_150in1_w),          NULL, NULL, NULL },
12161		{ BMC_35IN1,            NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(bmc_35in1_w),           NULL, NULL, NULL },
12162		{ BMC_64IN1,            NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(bmc_64in1_w),           NULL, NULL, NULL },
12163		{ BMC_SUPERHIK_300IN1,  NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(bmc_hik300_w),          NULL, NULL, NULL },
12164		{ BMC_SUPERGUN_20IN1,   NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(supergun20in1_w),       NULL, NULL, NULL },
12165		{ BMC_72IN1,            NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(bmc_72in1_w),           NULL, NULL, NULL },
12166		{ BMC_76IN1,            NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(bmc_76in1_w),           NULL, NULL, NULL },
12167		{ BMC_SUPER_42IN1,      NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(bmc_76in1_w),           NULL, NULL, NULL },
12168		{ BMC_1200IN1,          NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(bmc_1200in1_w),         NULL, NULL, NULL },
12169		{ BMC_31IN1,            NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(bmc_31in1_w),           NULL, NULL, NULL },
12170		{ BMC_22GAMES,          NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(bmc_22g_w),             NULL, NULL, NULL },
12171		{ BMC_20IN1,            NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(bmc_20in1_w),           NULL, NULL, NULL },
12172		{ BMC_110IN1,           NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(bmc_110in1_w),          NULL, NULL, NULL },
12173		{ BMC_64IN1NR,          NES_WRITEONLY(bmc_64in1nr_l_w), NES_NOACCESS, NES_WRITEONLY(bmc_64in1nr_w), NULL, NULL, NULL },
12174		{ BMC_S24IN1SC03,       NES_WRITEONLY(bmc_s24in1sc03_l_w), NES_NOACCESS, NES_WRITEONLY(txrom_w), NULL, NULL, mmc3_irq },
12175		{ BMC_HIK8IN1,          NES_NOACCESS, NES_WRITEONLY(bmc_hik8_m_w), NES_WRITEONLY(txrom_w), NULL, NULL, mmc3_irq },
12176		{ BMC_SUPERHIK_4IN1,    NES_NOACCESS, NES_WRITEONLY(bmc_hik4in1_m_w), NES_WRITEONLY(txrom_w), NULL, NULL, mmc3_irq },
12177		{ BMC_SUPERBIG_7IN1,    NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(bmc_sbig7_w),           NULL, NULL, mmc3_irq },
12178		{ BMC_MARIOPARTY_7IN1,  NES_NOACCESS, NES_WRITEONLY(bmc_mario7in1_m_w), NES_WRITEONLY(txrom_w), NULL, NULL, mmc3_irq },
12179		{ BMC_GOLD_7IN1,        NES_NOACCESS, NES_WRITEONLY(bmc_gold7in1_m_w), NES_WRITEONLY(txrom_w), NULL, NULL, mmc3_irq },
12180		{ BMC_FAMILY_4646B,     NES_NOACCESS, NES_WRITEONLY(bmc_family4646_m_w), NES_WRITEONLY(txrom_w), NULL, NULL, mmc3_irq },
12181		{ BMC_15IN1,            NES_NOACCESS, NES_WRITEONLY(bmc_15in1_m_w), NES_WRITEONLY(txrom_w), NULL, NULL, mmc3_irq },
12182		{ BMC_BALLGAMES_11IN1,  NES_NOACCESS, NES_WRITEONLY(bmc_ball11_m_w), NES_WRITEONLY(bmc_ball11_w), NULL, NULL, NULL },
12183		{ BMC_GOLDENCARD_6IN1,  NES_WRITEONLY(bmc_gc6in1_l_w), NES_NOACCESS, NES_WRITEONLY(bmc_gc6in1_w), NULL, NULL, mmc3_irq },
12184		{ BMC_VT5201,           NES_NOACCESS, NES_NOACCESS, {FUNC(bmc_vt5201_w), FUNC(bmc_vt5201_r)},         NULL, NULL, NULL },
12185		{ BMC_BENSHENG_BS5,     NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(bmc_bs5_w),             NULL, NULL, NULL },
12186		{ BMC_810544,           NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(bmc_810544_w),          NULL, NULL, NULL },
12187		{ BMC_NTD_03,           NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(bmc_ntd03_w),           NULL, NULL, NULL },
12188		{ BMC_G63IN1,           NES_NOACCESS, NES_NOACCESS, {FUNC(bmc_gb63_w), FUNC(bmc_gb63_r)},             NULL, NULL, NULL },
12189		{ BMC_FK23C,            NES_WRITEONLY(fk23c_l_w), NES_NOACCESS, NES_WRITEONLY(fk23c_w),   NULL, NULL, mmc3_irq },
12190		{ BMC_FK23CA,           NES_WRITEONLY(fk23c_l_w), NES_NOACCESS, NES_WRITEONLY(fk23c_w),   NULL, NULL, mmc3_irq },
12191		{ BMC_PJOY84,           NES_NOACCESS, NES_WRITEONLY(pjoy84_m_w), NES_WRITEONLY(txrom_w),  NULL, NULL, mmc3_irq },
	11975	{ BMC_190IN1,           NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::bmc_190in1_w),          NULL, NULL, NULL },
	11976	{ BMC_A65AS,            NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::bmc_a65as_w),           NULL, NULL, NULL },
	11977	{ BMC_GS2004,           NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::bmc_gs2004_w),          NULL, NULL, NULL },
	11978	{ BMC_GS2013,           NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::bmc_gs2013_w),          NULL, NULL, NULL },
	11979	{ BMC_NOVELDIAMOND,     NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::novel1_w),              NULL, NULL, NULL },
	11980	{ BMC_9999999IN1,       NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::novel2_w),              NULL, NULL, NULL },
	11981	{ BMC_T262,             NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::bmc_t262_w),            NULL, NULL, NULL },
	11982	{ BMC_WS,               NES_NOACCESS, NES_WRITEONLY(nes_state::bmc_ws_m_w), NES_NOACCESS,            NULL, NULL, NULL },
	11983	{ BMC_GKA,              NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::bmc_gka_w),             NULL, NULL, NULL },
	11984	{ BMC_GKB,              NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::bmc_gkb_w),             NULL, NULL, NULL },
	11985	{ BMC_SUPER_700IN1,     NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::bmc_super700in1_w),     NULL, NULL, NULL },
	11986	{ BMC_36IN1,            NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::bmc_36in1_w),           NULL, NULL, NULL },
	11987	{ BMC_21IN1,            NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::bmc_21in1_w),           NULL, NULL, NULL },
	11988	{ BMC_150IN1,           NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::bmc_150in1_w),          NULL, NULL, NULL },
	11989	{ BMC_35IN1,            NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::bmc_35in1_w),           NULL, NULL, NULL },
	11990	{ BMC_64IN1,            NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::bmc_64in1_w),           NULL, NULL, NULL },
	11991	{ BMC_SUPERHIK_300IN1,  NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::bmc_hik300_w),          NULL, NULL, NULL },
	11992	{ BMC_SUPERGUN_20IN1,   NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::supergun20in1_w),       NULL, NULL, NULL },
	11993	{ BMC_72IN1,            NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::bmc_72in1_w),           NULL, NULL, NULL },
	11994	{ BMC_76IN1,            NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::bmc_76in1_w),           NULL, NULL, NULL },
	11995	{ BMC_SUPER_42IN1,      NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::bmc_76in1_w),           NULL, NULL, NULL },
	11996	{ BMC_1200IN1,          NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::bmc_1200in1_w),         NULL, NULL, NULL },
	11997	{ BMC_31IN1,            NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::bmc_31in1_w),           NULL, NULL, NULL },
	11998	{ BMC_22GAMES,          NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::bmc_22g_w),             NULL, NULL, NULL },
	11999	{ BMC_20IN1,            NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::bmc_20in1_w),           NULL, NULL, NULL },
	12000	{ BMC_110IN1,           NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::bmc_110in1_w),          NULL, NULL, NULL },
	12001	{ BMC_64IN1NR,          NES_WRITEONLY(nes_state::bmc_64in1nr_l_w), NES_NOACCESS, NES_WRITEONLY(nes_state::bmc_64in1nr_w), NULL, NULL, NULL },
	12002	{ BMC_S24IN1SC03,       NES_WRITEONLY(nes_state::bmc_s24in1sc03_l_w), NES_NOACCESS, NES_WRITEONLY(nes_state::txrom_w), NULL, NULL, mmc3_irq },
	12003	{ BMC_HIK8IN1,          NES_NOACCESS, NES_WRITEONLY(nes_state::bmc_hik8_m_w), NES_WRITEONLY(nes_state::txrom_w), NULL, NULL, mmc3_irq },
	12004	{ BMC_SUPERHIK_4IN1,    NES_NOACCESS, NES_WRITEONLY(nes_state::bmc_hik4in1_m_w), NES_WRITEONLY(nes_state::txrom_w), NULL, NULL, mmc3_irq },
	12005	{ BMC_SUPERBIG_7IN1,    NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::bmc_sbig7_w),           NULL, NULL, mmc3_irq },
	12006	{ BMC_MARIOPARTY_7IN1,  NES_NOACCESS, NES_WRITEONLY(nes_state::bmc_mario7in1_m_w), NES_WRITEONLY(nes_state::txrom_w), NULL, NULL, mmc3_irq },
	12007	{ BMC_GOLD_7IN1,        NES_NOACCESS, NES_WRITEONLY(nes_state::bmc_gold7in1_m_w), NES_WRITEONLY(nes_state::txrom_w), NULL, NULL, mmc3_irq },
	12008	{ BMC_FAMILY_4646B,     NES_NOACCESS, NES_WRITEONLY(nes_state::bmc_family4646_m_w), NES_WRITEONLY(nes_state::txrom_w), NULL, NULL, mmc3_irq },
	12009	{ BMC_15IN1,            NES_NOACCESS, NES_WRITEONLY(nes_state::bmc_15in1_m_w), NES_WRITEONLY(nes_state::txrom_w), NULL, NULL, mmc3_irq },
	12010	{ BMC_BALLGAMES_11IN1,  NES_NOACCESS, NES_WRITEONLY(nes_state::bmc_ball11_m_w), NES_WRITEONLY(nes_state::bmc_ball11_w), NULL, NULL, NULL },
	12011	{ BMC_GOLDENCARD_6IN1,  NES_WRITEONLY(nes_state::bmc_gc6in1_l_w), NES_NOACCESS, NES_WRITEONLY(nes_state::bmc_gc6in1_w), NULL, NULL, mmc3_irq },
	12012	{ BMC_VT5201,           NES_NOACCESS, NES_NOACCESS, {write8_delegate(FUNC(nes_state::bmc_vt5201_w),(nes_state *)0), read8_delegate(FUNC(nes_state::bmc_vt5201_r),(nes_state *)0)},         NULL, NULL, NULL },
	12013	{ BMC_BENSHENG_BS5,     NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::bmc_bs5_w),             NULL, NULL, NULL },
	12014	{ BMC_810544,           NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::bmc_810544_w),          NULL, NULL, NULL },
	12015	{ BMC_NTD_03,           NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::bmc_ntd03_w),           NULL, NULL, NULL },
	12016	{ BMC_G63IN1,           NES_NOACCESS, NES_NOACCESS, {write8_delegate(FUNC(nes_state::bmc_gb63_w),(nes_state *)0), read8_delegate(FUNC(nes_state::bmc_gb63_r),(nes_state *)0)},             NULL, NULL, NULL },
	12017	{ BMC_FK23C,            NES_WRITEONLY(nes_state::fk23c_l_w), NES_NOACCESS, NES_WRITEONLY(nes_state::fk23c_w),   NULL, NULL, mmc3_irq },
	12018	{ BMC_FK23CA,           NES_WRITEONLY(nes_state::fk23c_l_w), NES_NOACCESS, NES_WRITEONLY(nes_state::fk23c_w),   NULL, NULL, mmc3_irq },
	12019	{ BMC_PJOY84,           NES_NOACCESS, NES_WRITEONLY(nes_state::pjoy84_m_w), NES_WRITEONLY(nes_state::txrom_w),  NULL, NULL, mmc3_irq },
12192	12020	//
12193		{ FFE_MAPPER6,          NES_WRITEONLY(mapper6_l_w), NES_NOACCESS, NES_WRITEONLY(mapper6_w), NULL, NULL, ffe_irq },
12194		{ FFE_MAPPER8,          NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(mapper8_w),             NULL, NULL, NULL },
12195		{ FFE_MAPPER17,         NES_WRITEONLY(mapper17_l_w), NES_NOACCESS, NES_NOACCESS,          NULL, NULL, ffe_irq },
	12021	{ FFE_MAPPER6,          NES_WRITEONLY(nes_state::mapper6_l_w), NES_NOACCESS, NES_WRITEONLY(nes_state::mapper6_w), NULL, NULL, ffe_irq },
	12022	{ FFE_MAPPER8,          NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(nes_state::mapper8_w),             NULL, NULL, NULL },
	12023	{ FFE_MAPPER17,         NES_WRITEONLY(nes_state::mapper17_l_w), NES_NOACCESS, NES_NOACCESS,          NULL, NULL, ffe_irq },
12196	12024	// for debug and development
12197		{ UNKNOWN_BOARD,        {FUNC(dummy_l_w), FUNC(dummy_l_r)}, {FUNC(dummy_m_w), FUNC(dummy_m_r)}, {FUNC(dummy_w), FUNC(dummy_r)}, NULL, NULL, NULL },
	12025	{ UNKNOWN_BOARD,        {write8_delegate(FUNC(nes_state::dummy_l_w),(nes_state *)0), read8_delegate(FUNC(nes_state::dummy_l_r),(nes_state *)0)}, {write8_delegate(FUNC(nes_state::dummy_m_w),(nes_state *)0), read8_delegate(FUNC(nes_state::dummy_m_r),(nes_state *)0)}, {write8_delegate(FUNC(nes_state::dummy_w),(nes_state *)0), read8_delegate(FUNC(nes_state::dummy_r),(nes_state *)0)}, NULL, NULL, NULL },
12198	12026	//
12199	12027	{ UNSUPPORTED_BOARD,    NES_NOACCESS, NES_NOACCESS, NES_NOACCESS,                         NULL, NULL, NULL },
12200	12028	//
r18063	r18064
12220	12048	fatalerror("Missing PCB interface\n");
12221	12049
12222	12050	if (intf)
12223		{
	12051	{
12224	12052	state->m_mmc_write_low = intf->mmc_l.write;
12225		state->m_mmc_write_low_name = intf->mmc_l.write_name;
	12053	if (!state->m_mmc_write_low.isnull()) state->m_mmc_write_low.late_bind(*state);
12226	12054	state->m_mmc_write_mid = intf->mmc_m.write;
12227		state->m_mmc_write_mid_name = intf->mmc_m.write_name;
	12055	if (!state->m_mmc_write_mid.isnull()) state->m_mmc_write_mid.late_bind(*state);
12228	12056	state->m_mmc_write = intf->mmc_h.write;
12229		state->m_mmc_write_name = intf->mmc_h.write_name;
	12057	if (!state->m_mmc_write.isnull()) state->m_mmc_write.late_bind(*state);
12230	12058	state->m_mmc_read_low = intf->mmc_l.read;
12231		state->m_mmc_read_low_name = intf->mmc_l.read_name;
	12059	if (!state->m_mmc_read_low.isnull()) state->m_mmc_read_low.late_bind(*state);
12232	12060	state->m_mmc_read_mid = intf->mmc_m.read;   // in progress
12233		state->m_mmc_read_mid_name = intf->mmc_m.read_name;
	12061	if (!state->m_mmc_read_mid.isnull()) state->m_mmc_read_mid.late_bind(*state);
12234	12062	state->m_mmc_read = intf->mmc_h.read;   // in progress
12235		state->m_mmc_read_name = intf->mmc_h.read_name;
	12063	if (!state->m_mmc_read.isnull()) state->m_mmc_read.late_bind(*state);
12236	12064	state->m_ppu->set_latch(intf->mmc_ppu_latch);
12237	12065	}
12238	12066	else
12239	12067	{
12240	12068	logerror("PCB %d is not yet supported, defaulting to no mapper.\n", state->m_pcb_id);
12241		state->m_mmc_write_low = NULL;
12242		state->m_mmc_write_mid = NULL;
12243		state->m_mmc_write = NULL;
12244		state->m_mmc_read_low = NULL;
12245		state->m_mmc_read_mid = NULL;   // in progress
12246		state->m_mmc_read = NULL;   // in progress
	12069	state->m_mmc_write_low = write8_delegate();
	12070	state->m_mmc_write_mid = write8_delegate();
	12071	state->m_mmc_write = write8_delegate();
	12072	state->m_mmc_read_low = read8_delegate();
	12073	state->m_mmc_read_mid = read8_delegate();   // in progress
	12074	state->m_mmc_read = read8_delegate();   // in progress
12247	12075	state->m_ppu->set_latch(NULL);
12248	12076	}
12249	12077

trunk/src/mess/includes/nes.h

r18063	r18064
108	108	int m_last_frame_flip;
109	109
110	110	/* misc */
111		write8_space_func   m_mmc_write_low;
112		const char        *m_mmc_write_low_name;
113		write8_space_func   m_mmc_write_mid;
114		const char        *m_mmc_write_mid_name;
115		write8_space_func   m_mmc_write;
116		const char        *m_mmc_write_name;
117		read8_space_func    m_mmc_read_low;
118		const char        *m_mmc_read_low_name;
119		read8_space_func    m_mmc_read_mid;
120		const char        *m_mmc_read_mid_name;
121		read8_space_func    m_mmc_read;
122		const char        *m_mmc_read_name;
	111	write8_delegate   m_mmc_write_low;
	112	write8_delegate   m_mmc_write_mid;
	113	write8_delegate   m_mmc_write;
	114	read8_delegate    m_mmc_read_low;
	115	read8_delegate    m_mmc_read_mid;
	116	read8_delegate    m_mmc_read;
123	117	emu_timer           *m_irq_timer;
124	118
125	119	nes_prg_callback    m_mmc3_prg_cb;   // these are used to simplify a lot emulation of some MMC3 pirate clones
r18063	r18064
260	254	virtual void video_start();
261	255	virtual void palette_init();
262	256	UINT32 screen_update_nes(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
	257	DECLARE_WRITE8_MEMBER(mapper6_l_w);
	258	DECLARE_WRITE8_MEMBER(mapper6_w);
	259	DECLARE_WRITE8_MEMBER(mapper8_w);
	260	DECLARE_WRITE8_MEMBER(mapper17_l_w);
	261	DECLARE_WRITE8_MEMBER(nes_chr_w);
	262	DECLARE_READ8_MEMBER(nes_chr_r);
	263	DECLARE_WRITE8_MEMBER(nes_nt_w);
	264	DECLARE_READ8_MEMBER(nes_nt_r);
	265	DECLARE_WRITE8_MEMBER(nes_low_mapper_w);
	266	DECLARE_READ8_MEMBER(nes_low_mapper_r);
	267	DECLARE_WRITE8_MEMBER(uxrom_w);
	268	DECLARE_WRITE8_MEMBER(uxrom_cc_w);
	269	DECLARE_WRITE8_MEMBER(un1rom_w);
	270	DECLARE_WRITE8_MEMBER(cnrom_w);
	271	DECLARE_WRITE8_MEMBER(bandai_pt554_m_w);
	272	DECLARE_WRITE8_MEMBER(cprom_w);
	273	DECLARE_WRITE8_MEMBER(axrom_w);
	274	DECLARE_WRITE8_MEMBER(bxrom_w);
	275	DECLARE_WRITE8_MEMBER(gxrom_w);
	276	DECLARE_WRITE8_MEMBER(sxrom_w);
	277	DECLARE_WRITE8_MEMBER(pxrom_w);
	278	DECLARE_WRITE8_MEMBER(fxrom_w);
	279	DECLARE_WRITE8_MEMBER(txrom_w);
	280	DECLARE_WRITE8_MEMBER(hkrom_m_w);
	281	DECLARE_READ8_MEMBER(hkrom_m_r);
	282	DECLARE_WRITE8_MEMBER(hkrom_w);
	283	DECLARE_WRITE8_MEMBER(txsrom_w);
	284	DECLARE_WRITE8_MEMBER(tqrom_w);
	285	DECLARE_WRITE8_MEMBER(zz_m_w);
	286	DECLARE_WRITE8_MEMBER(qj_m_w);
	287	DECLARE_READ8_MEMBER(exrom_l_r);
	288	DECLARE_WRITE8_MEMBER(exrom_l_w);
	289	DECLARE_WRITE8_MEMBER(ntbrom_w);
	290	DECLARE_WRITE8_MEMBER(jxrom_w);
	291	DECLARE_WRITE8_MEMBER(dxrom_w);
	292	DECLARE_WRITE8_MEMBER(namcot3453_w);
	293	DECLARE_WRITE8_MEMBER(namcot3446_w);
	294	DECLARE_WRITE8_MEMBER(namcot3425_w);
	295	DECLARE_WRITE8_MEMBER(dis_74x377_w);
	296	DECLARE_WRITE8_MEMBER(dis_74x139x74_m_w);
	297	DECLARE_WRITE8_MEMBER(dis_74x161x138_m_w);
	298	DECLARE_WRITE8_MEMBER(dis_74x161x161x32_w);
	299	DECLARE_WRITE8_MEMBER(lz93d50_w);
	300	DECLARE_WRITE8_MEMBER(lz93d50_m_w);
	301	DECLARE_WRITE8_MEMBER(fjump2_w);
	302	DECLARE_WRITE8_MEMBER(bandai_ks_w);
	303	DECLARE_WRITE8_MEMBER(bandai_ok_w);
	304	DECLARE_WRITE8_MEMBER(lrog017_w);
	305	DECLARE_WRITE8_MEMBER(irem_hd_w);
	306	DECLARE_WRITE8_MEMBER(tam_s1_w);
	307	DECLARE_WRITE8_MEMBER(g101_w);
	308	DECLARE_WRITE8_MEMBER(h3001_w);
	309	DECLARE_WRITE8_MEMBER(ss88006_w);
	310	DECLARE_WRITE8_MEMBER(jf11_m_w);
	311	DECLARE_WRITE8_MEMBER(jf13_m_w);
	312	DECLARE_WRITE8_MEMBER(jf16_w);
	313	DECLARE_WRITE8_MEMBER(jf17_w);
	314	DECLARE_WRITE8_MEMBER(jf19_w);
	315	DECLARE_WRITE8_MEMBER(konami_vrc1_w);
	316	DECLARE_WRITE8_MEMBER(konami_vrc2_w);
	317	DECLARE_WRITE8_MEMBER(konami_vrc3_w);
	318	DECLARE_WRITE8_MEMBER(konami_vrc4_w);
	319	DECLARE_WRITE8_MEMBER(konami_vrc6_w);
	320	DECLARE_WRITE8_MEMBER(konami_vrc7_w);
	321	DECLARE_WRITE8_MEMBER(namcot163_l_w);
	322	DECLARE_READ8_MEMBER(namcot163_l_r);
	323	DECLARE_WRITE8_MEMBER(namcot163_w);
	324	DECLARE_WRITE8_MEMBER(sunsoft1_m_w);
	325	DECLARE_WRITE8_MEMBER(sunsoft2_w);
	326	DECLARE_WRITE8_MEMBER(sunsoft3_w);
	327	DECLARE_WRITE8_MEMBER(tc0190fmc_w);
	328	DECLARE_WRITE8_MEMBER(tc0190fmc_p16_w);
	329	DECLARE_WRITE8_MEMBER(x1005_m_w);
	330	DECLARE_READ8_MEMBER(x1005_m_r);
	331	DECLARE_WRITE8_MEMBER(x1005a_m_w);
	332	DECLARE_WRITE8_MEMBER(x1017_m_w);
	333	DECLARE_READ8_MEMBER(x1017_m_r);
	334	DECLARE_WRITE8_MEMBER(agci_50282_w);
	335	DECLARE_WRITE8_MEMBER(nina01_m_w);
	336	DECLARE_WRITE8_MEMBER(nina06_l_w);
	337	DECLARE_WRITE8_MEMBER(ae_act52_w);
	338	DECLARE_WRITE8_MEMBER(cne_decathl_w);
	339	DECLARE_WRITE8_MEMBER(cne_fsb_m_w);
	340	DECLARE_WRITE8_MEMBER(cne_shlz_l_w);
	341	DECLARE_WRITE8_MEMBER(caltron6in1_m_w);
	342	DECLARE_WRITE8_MEMBER(caltron6in1_w);
	343	DECLARE_WRITE8_MEMBER(bf9093_w);
	344	DECLARE_WRITE8_MEMBER(bf9096_w);
	345	DECLARE_WRITE8_MEMBER(golden5_w);
	346	DECLARE_WRITE8_MEMBER(cony_l_w);
	347	DECLARE_READ8_MEMBER(cony_l_r);
	348	DECLARE_WRITE8_MEMBER(cony_w);
	349	DECLARE_WRITE8_MEMBER(yoko_l_w);
	350	DECLARE_READ8_MEMBER(yoko_l_r);
	351	DECLARE_WRITE8_MEMBER(yoko_w);
	352	DECLARE_WRITE8_MEMBER(dreamtech_l_w);
	353	DECLARE_WRITE8_MEMBER(fukutake_l_w);
	354	DECLARE_READ8_MEMBER(fukutake_l_r);
	355	DECLARE_WRITE8_MEMBER(futuremedia_w);
	356	DECLARE_WRITE8_MEMBER(gouder_sf4_l_w);
	357	DECLARE_READ8_MEMBER(gouder_sf4_l_r);
	358	DECLARE_WRITE8_MEMBER(henggedianzi_w);
	359	DECLARE_WRITE8_MEMBER(heng_xjzb_l_w);
	360	DECLARE_WRITE8_MEMBER(heng_xjzb_w);
	361	DECLARE_WRITE8_MEMBER(hes6in1_l_w);
	362	DECLARE_WRITE8_MEMBER(hes_l_w);
	363	DECLARE_WRITE8_MEMBER(hosenkan_w);
	364	DECLARE_WRITE8_MEMBER(ks7058_w);
	365	DECLARE_WRITE8_MEMBER(ks7022_w);
	366	DECLARE_READ8_MEMBER(ks7022_r);
	367	DECLARE_WRITE8_MEMBER(ks7032_w);
	368	DECLARE_WRITE8_MEMBER(ks202_w);
	369	DECLARE_WRITE8_MEMBER(ks7017_l_w);
	370	DECLARE_WRITE8_MEMBER(ks7017_extra_w);
	371	DECLARE_READ8_MEMBER(ks7017_extra_r);
	372	DECLARE_WRITE8_MEMBER(kay_pp_l_w);
	373	DECLARE_READ8_MEMBER(kay_pp_l_r);
	374	DECLARE_WRITE8_MEMBER(kay_pp_w);
	375	DECLARE_WRITE8_MEMBER(kasing_m_w);
	376	DECLARE_WRITE8_MEMBER(magics_md_w);
	377	DECLARE_WRITE8_MEMBER(nanjing_l_w);
	378	DECLARE_READ8_MEMBER(nanjing_l_r);
	379	DECLARE_WRITE8_MEMBER(nitra_w);
	380	DECLARE_WRITE8_MEMBER(ntdec_asder_w);
	381	DECLARE_WRITE8_MEMBER(ntdec_fh_m_w);
	382	DECLARE_WRITE8_MEMBER(daou306_w);
	383	DECLARE_WRITE8_MEMBER(gs2015_w);
	384	DECLARE_WRITE8_MEMBER(rcm_tf_w);
	385	DECLARE_WRITE8_MEMBER(rex_dbz_l_w);
	386	DECLARE_READ8_MEMBER(rex_dbz_l_r);
	387	DECLARE_WRITE8_MEMBER(rex_sl1632_w);
	388	DECLARE_WRITE8_MEMBER(rumblestation_m_w);
	389	DECLARE_WRITE8_MEMBER(rumblestation_w);
	390	DECLARE_WRITE8_MEMBER(sachen_74x374_l_w);
	391	DECLARE_READ8_MEMBER(sachen_74x374_l_r);
	392	DECLARE_WRITE8_MEMBER(sachen_74x374a_l_w);
	393	DECLARE_WRITE8_MEMBER(s8259_l_w);
	394	DECLARE_WRITE8_MEMBER(s8259_m_w);
	395	DECLARE_WRITE8_MEMBER(sa009_l_w);
	396	DECLARE_WRITE8_MEMBER(sa0036_w);
	397	DECLARE_WRITE8_MEMBER(sa0037_w);
	398	DECLARE_WRITE8_MEMBER(sa72007_l_w);
	399	DECLARE_WRITE8_MEMBER(sa72008_l_w);
	400	DECLARE_READ8_MEMBER(tca01_l_r);
	401	DECLARE_WRITE8_MEMBER(tcu01_l_w);
	402	DECLARE_WRITE8_MEMBER(tcu01_m_w);
	403	DECLARE_WRITE8_MEMBER(tcu01_w);
	404	DECLARE_WRITE8_MEMBER(tcu02_l_w);
	405	DECLARE_READ8_MEMBER(tcu02_l_r);
	406	DECLARE_WRITE8_MEMBER(subor0_w);
	407	DECLARE_WRITE8_MEMBER(subor1_w);
	408	DECLARE_WRITE8_MEMBER(sgame_boog_l_w);
	409	DECLARE_WRITE8_MEMBER(sgame_boog_m_w);
	410	DECLARE_WRITE8_MEMBER(sgame_boog_w);
	411	DECLARE_WRITE8_MEMBER(sgame_lion_m_w);
	412	DECLARE_WRITE8_MEMBER(sgame_lion_w);
	413	DECLARE_WRITE8_MEMBER(tengen_800008_w);
	414	DECLARE_WRITE8_MEMBER(tengen_800032_w);
	415	DECLARE_WRITE8_MEMBER(tengen_800037_w);
	416	DECLARE_WRITE8_MEMBER(txc_22211_l_w);
	417	DECLARE_READ8_MEMBER(txc_22211_l_r);
	418	DECLARE_WRITE8_MEMBER(txc_22211_w);
	419	DECLARE_WRITE8_MEMBER(txc_22211b_w);
	420	DECLARE_READ8_MEMBER(txc_22211c_l_r);
	421	DECLARE_WRITE8_MEMBER(txc_tw_l_w);
	422	DECLARE_WRITE8_MEMBER(txc_tw_m_w);
	423	DECLARE_WRITE8_MEMBER(txc_strikewolf_w);
	424	DECLARE_READ8_MEMBER(txc_mxmdhtwo_l_r);
	425	DECLARE_WRITE8_MEMBER(txc_mxmdhtwo_w);
	426	DECLARE_WRITE8_MEMBER(waixing_a_w);
	427	DECLARE_WRITE8_MEMBER(waixing_f_w);
	428	DECLARE_WRITE8_MEMBER(waixing_g_w);
	429	DECLARE_WRITE8_MEMBER(waixing_h_w);
	430	DECLARE_WRITE8_MEMBER(waixing_sgz_w);
	431	DECLARE_WRITE8_MEMBER(waixing_sgzlz_l_w);
	432	DECLARE_WRITE8_MEMBER(waixing_ffv_l_w);
	433	DECLARE_WRITE8_MEMBER(waixing_zs_w);
	434	DECLARE_WRITE8_MEMBER(waixing_dq8_w);
	435	DECLARE_WRITE8_MEMBER(waixing_ps2_w);
	436	DECLARE_WRITE8_MEMBER(waixing_sec_l_w);
	437	DECLARE_READ8_MEMBER(waixing_sh2_chr_r);
	438	DECLARE_WRITE8_MEMBER(unl_8237_l_w);
	439	DECLARE_WRITE8_MEMBER(unl_8237_w);
	440	DECLARE_WRITE8_MEMBER(unl_ax5705_w);
	441	DECLARE_WRITE8_MEMBER(unl_cc21_w);
	442	DECLARE_WRITE8_MEMBER(unl_kof97_w);
	443	DECLARE_WRITE8_MEMBER(ks7057_w);
	444	DECLARE_WRITE8_MEMBER(unl_t230_w);
	445	DECLARE_WRITE8_MEMBER(kof96_l_w);
	446	DECLARE_READ8_MEMBER(kof96_l_r);
	447	DECLARE_WRITE8_MEMBER(kof96_w);
	448	DECLARE_WRITE8_MEMBER(mk2_m_w);
	449	DECLARE_WRITE8_MEMBER(n625092_w);
	450	DECLARE_WRITE8_MEMBER(sc127_w);
	451	DECLARE_WRITE8_MEMBER(smb2j_w);
	452	DECLARE_WRITE8_MEMBER(smb2jb_l_w);
	453	DECLARE_WRITE8_MEMBER(smb2jb_extra_w);
	454	DECLARE_WRITE8_MEMBER(unl_sf3_w);
	455	DECLARE_WRITE8_MEMBER(unl_xzy_l_w);
	456	DECLARE_WRITE8_MEMBER(unl_racmate_w);
	457	DECLARE_WRITE8_MEMBER(unl_fs304_l_w);
	458	DECLARE_WRITE8_MEMBER(btl_smb11_w);
	459	DECLARE_WRITE8_MEMBER(btl_mariobaby_w);
	460	DECLARE_WRITE8_MEMBER(btl_smb2a_w);
	461	DECLARE_WRITE8_MEMBER(whirl2706_w);
	462	DECLARE_WRITE8_MEMBER(btl_tobi_l_w);
	463	DECLARE_WRITE8_MEMBER(btl_smb3_w);
	464	DECLARE_WRITE8_MEMBER(btl_dn_w);
	465	DECLARE_WRITE8_MEMBER(btl_pika_y2k_w);
	466	DECLARE_WRITE8_MEMBER(btl_pika_y2k_m_w);
	467	DECLARE_READ8_MEMBER(btl_pika_y2k_m_r);
	468	DECLARE_WRITE8_MEMBER(fk23c_l_w);
	469	DECLARE_WRITE8_MEMBER(fk23c_w);
	470	DECLARE_WRITE8_MEMBER(bmc_64in1nr_l_w);
	471	DECLARE_WRITE8_MEMBER(bmc_64in1nr_w);
	472	DECLARE_WRITE8_MEMBER(bmc_190in1_w);
	473	DECLARE_WRITE8_MEMBER(bmc_a65as_w);
	474	DECLARE_WRITE8_MEMBER(bmc_gs2004_w);
	475	DECLARE_WRITE8_MEMBER(bmc_gs2013_w);
	476	DECLARE_WRITE8_MEMBER(bmc_s24in1sc03_l_w);
	477	DECLARE_WRITE8_MEMBER(bmc_t262_w);
	478	DECLARE_WRITE8_MEMBER(bmc_ws_m_w);
	479	DECLARE_WRITE8_MEMBER(novel1_w);
	480	DECLARE_WRITE8_MEMBER(novel2_w);
	481	DECLARE_WRITE8_MEMBER(bmc_gka_w);
	482	DECLARE_WRITE8_MEMBER(sng32_w);
	483	DECLARE_WRITE8_MEMBER(bmc_gkb_w);
	484	DECLARE_WRITE8_MEMBER(bmc_super700in1_w);
	485	DECLARE_WRITE8_MEMBER(bmc_36in1_w);
	486	DECLARE_WRITE8_MEMBER(bmc_21in1_w);
	487	DECLARE_WRITE8_MEMBER(bmc_150in1_w);
	488	DECLARE_WRITE8_MEMBER(bmc_35in1_w);
	489	DECLARE_WRITE8_MEMBER(bmc_64in1_w);
	490	DECLARE_WRITE8_MEMBER(bmc_15in1_m_w);
	491	DECLARE_WRITE8_MEMBER(bmc_hik300_w);
	492	DECLARE_WRITE8_MEMBER(supergun20in1_w);
	493	DECLARE_WRITE8_MEMBER(bmc_72in1_w);
	494	DECLARE_WRITE8_MEMBER(bmc_76in1_w);
	495	DECLARE_WRITE8_MEMBER(bmc_1200in1_w);
	496	DECLARE_WRITE8_MEMBER(bmc_31in1_w);
	497	DECLARE_WRITE8_MEMBER(bmc_22g_w);
	498	DECLARE_WRITE8_MEMBER(bmc_20in1_w);
	499	DECLARE_WRITE8_MEMBER(bmc_110in1_w);
	500	DECLARE_WRITE8_MEMBER(bmc_sbig7_w);
	501	DECLARE_WRITE8_MEMBER(bmc_hik8_m_w);
	502	DECLARE_WRITE8_MEMBER(bmc_hik4in1_m_w);
	503	DECLARE_WRITE8_MEMBER(bmc_ball11_m_w);
	504	DECLARE_WRITE8_MEMBER(bmc_ball11_w);
	505	DECLARE_WRITE8_MEMBER(bmc_mario7in1_m_w);
	506	DECLARE_WRITE8_MEMBER(bmc_gold7in1_m_w);
	507	DECLARE_WRITE8_MEMBER(bmc_gc6in1_l_w);
	508	DECLARE_WRITE8_MEMBER(bmc_gc6in1_w);
	509	DECLARE_WRITE8_MEMBER(bmc_family4646_m_w);
	510	DECLARE_WRITE8_MEMBER(bmc_vt5201_w);
	511	DECLARE_READ8_MEMBER(bmc_vt5201_r);
	512	DECLARE_WRITE8_MEMBER(bmc_bs5_w);
	513	DECLARE_WRITE8_MEMBER(bmc_810544_w);
	514	DECLARE_WRITE8_MEMBER(bmc_ntd03_w);
	515	DECLARE_WRITE8_MEMBER(bmc_gb63_w);
	516	DECLARE_READ8_MEMBER(bmc_gb63_r);
	517	DECLARE_WRITE8_MEMBER(edu2k_w);
	518	DECLARE_WRITE8_MEMBER(h2288_l_w);
	519	DECLARE_READ8_MEMBER(h2288_l_r);
	520	DECLARE_WRITE8_MEMBER(h2288_w);
	521	DECLARE_WRITE8_MEMBER(shjy3_w);
	522	DECLARE_WRITE8_MEMBER(unl_6035052_extra_w);
	523	DECLARE_READ8_MEMBER(unl_6035052_extra_r);
	524	DECLARE_WRITE8_MEMBER(pjoy84_m_w);
	525	DECLARE_WRITE8_MEMBER(someri_mmc1_w);
	526	DECLARE_WRITE8_MEMBER(someri_mmc3_w);
	527	DECLARE_WRITE8_MEMBER(someri_vrc2_w);
	528	DECLARE_WRITE8_MEMBER(someri_w);
	529	DECLARE_WRITE8_MEMBER(someri_l_w);
	530	DECLARE_WRITE8_MEMBER(fujiya_m_w);
	531	DECLARE_READ8_MEMBER(fujiya_m_r);
	532	DECLARE_WRITE8_MEMBER(dummy_l_w);
	533	DECLARE_WRITE8_MEMBER(dummy_m_w);
	534	DECLARE_WRITE8_MEMBER(dummy_w);
	535	DECLARE_READ8_MEMBER(dummy_l_r);
	536	DECLARE_READ8_MEMBER(dummy_m_r);
	537	DECLARE_READ8_MEMBER(dummy_r);
	538	void init_nes_core();
263	539	};
264	540
265	541	/*----------- defined in machine/nes.c -----------*/

trunk/src/mess/drivers/nes.c

r18063	r18064
50	50	AM_RANGE(0x4016, 0x4016) AM_READWRITE(nes_IN0_r, nes_IN0_w)         /* IN0 - input port 1 */
51	51	AM_RANGE(0x4017, 0x4017) AM_READ(nes_IN1_r)                     /* IN1 - input port 2 */
52	52	AM_RANGE(0x4017, 0x4017) AM_DEVWRITE_LEGACY("nessound", psg_4017_w)      /* PSG second control register */
53		AM_RANGE(0x4100, 0x5fff) AM_READWRITE_LEGACY(nes_low_mapper_r, nes_low_mapper_w)   /* Perform unholy acts on the machine */
	53	AM_RANGE(0x4100, 0x5fff) AM_READWRITE(nes_low_mapper_r, nes_low_mapper_w)   /* Perform unholy acts on the machine */
54	54	ADDRESS_MAP_END
55	55
56	56
r18063	r18064
544	544	MCFG_SOFTWARE_LIST_ADD("flop_list","famicom_flop")
545	545	MACHINE_CONFIG_END
546	546
	547	//static MACHINE_CONFIG_DERIVED( nes_test, nes )
	548	//MACHINE_CONFIG_END
547	549
	550
548	551	/* rom regions are just place-holders: they get removed and re-allocated when a cart is loaded */
549	552	ROM_START( nes )
550	553	ROM_REGION( 0x10000, "maincpu", ROMREGION_ERASE00 )  /* Main RAM */
r18063	r18064
596	599	ROM_REGION( 0x800,   "ciram", ROMREGION_ERASE00 )  /* CI RAM */
597	600	ROM_END
598	601
	602	//#define rom_nes_test rom_nes
	603
599	604	/***************************************************************************
600	605
601	606	Game driver(s)
r18063	r18064
610	615	CONS( 198?, m82,       nes,    0,     nes,      nes, driver_device,     0,       "Nintendo",  "M82 Display Unit", GAME_IMPERFECT_GRAPHICS | GAME_NOT_WORKING )
611	616	CONS( 1996, drpcjr,    nes,    0,     famicom,  famicom, nes_state, famicom, "Bung",      "Doctor PC Jr", GAME_IMPERFECT_GRAPHICS )
612	617	CONS( 1992, dendy,     nes,    0,     dendy,    nes, driver_device,     0,       "Steepler",  "Dendy Classic", GAME_IMPERFECT_GRAPHICS )
	618
	619	//CONS( 1985, nes_test,  0,      0,     nes_test, nes, driver_device,     0,       "Nintendo",  "Nintendo Entertainment System (Testdriver)", GAME_IMPERFECT_GRAPHICS )

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