trunk/src/mess/drivers/pcw16.c
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| 165 | 165 | m_colour_palette[offset & 0x0f] = data & 31; |
| 166 | 166 | } |
| 167 | 167 | |
| 168 | | |
| 168 | /* |
| 169 | 169 | static const char *const pcw16_write_handler_dram[4] = |
| 170 | 170 | { |
| 171 | 171 | "bank5", |
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| 181 | 181 | "bank3", |
| 182 | 182 | "bank4" |
| 183 | 183 | }; |
| 184 | | /*******************************************/ |
| 185 | 184 | |
| 186 | 185 | |
| 187 | | /* PCW16 Flash interface */ |
| 188 | | /* PCW16 can have two 1mb flash chips */ |
| 189 | 186 | |
| 190 | | /* read flash0 */ |
| 187 | // PCW16 Flash interface |
| 188 | // PCW16 can have two 1mb flash chips |
| 189 | |
| 190 | // read flash0 |
| 191 | 191 | static int pcw16_flash0_bank_handler_r(running_machine &machine, int bank, int offset) |
| 192 | 192 | { |
| 193 | 193 | pcw16_state *state = machine.driver_data<pcw16_state>(); |
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| 196 | 196 | return flash->read(flash_offset); |
| 197 | 197 | } |
| 198 | 198 | |
| 199 | | /* read flash1 */ |
| 199 | // read flash1 |
| 200 | 200 | static int pcw16_flash1_bank_handler_r(running_machine &machine, int bank, int offset) |
| 201 | 201 | { |
| 202 | 202 | pcw16_state *state = machine.driver_data<pcw16_state>(); |
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| 206 | 206 | return flash->read(flash_offset); |
| 207 | 207 | } |
| 208 | 208 | |
| 209 | | /* flash 0 */ |
| 209 | // flash 0 |
| 210 | 210 | static READ8_HANDLER(pcw16_flash0_bank_handler0_r) |
| 211 | 211 | { |
| 212 | 212 | return pcw16_flash0_bank_handler_r(space.machine(),0, offset); |
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| 227 | 227 | return pcw16_flash0_bank_handler_r(space.machine(),3, offset); |
| 228 | 228 | } |
| 229 | 229 | |
| 230 | | /* flash 1 */ |
| 230 | // flash 1 |
| 231 | 231 | static READ8_HANDLER(pcw16_flash1_bank_handler0_r) |
| 232 | 232 | { |
| 233 | 233 | return pcw16_flash1_bank_handler_r(space.machine(),0, offset); |
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| 264 | 264 | { FUNC(pcw16_flash1_bank_handler3_r) } |
| 265 | 265 | }; |
| 266 | 266 | |
| 267 | | /* write flash0 */ |
| 267 | // write flash0 |
| 268 | 268 | static void pcw16_flash0_bank_handler_w(running_machine &machine, int bank, int offset, int data) |
| 269 | 269 | { |
| 270 | 270 | pcw16_state *state = machine.driver_data<pcw16_state>(); |
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| 275 | 275 | flash->write(flash_offset, data); |
| 276 | 276 | } |
| 277 | 277 | |
| 278 | | /* read flash1 */ |
| 278 | // read flash1 |
| 279 | 279 | static void pcw16_flash1_bank_handler_w(running_machine &machine, int bank, int offset, int data) |
| 280 | 280 | { |
| 281 | 281 | pcw16_state *state = machine.driver_data<pcw16_state>(); |
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| 286 | 286 | flash->write(flash_offset,data); |
| 287 | 287 | } |
| 288 | 288 | |
| 289 | | /* flash 0 */ |
| 289 | // flash 0 |
| 290 | 290 | static WRITE8_HANDLER(pcw16_flash0_bank_handler0_w) |
| 291 | 291 | { |
| 292 | 292 | pcw16_flash0_bank_handler_w(space.machine(),0, offset, data); |
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| 309 | 309 | } |
| 310 | 310 | |
| 311 | 311 | |
| 312 | | /* flash 1 */ |
| 312 | // flash 1 |
| 313 | 313 | static WRITE8_HANDLER(pcw16_flash1_bank_handler0_w) |
| 314 | 314 | { |
| 315 | 315 | pcw16_flash1_bank_handler_w(space.machine(),0, offset, data); |
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| 349 | 349 | |
| 350 | 350 | enum PCW16_RAM_TYPE |
| 351 | 351 | { |
| 352 | | /* rom which is really first block of flash0 */ |
| 352 | // rom which is really first block of flash0 |
| 353 | 353 | PCW16_MEM_ROM, |
| 354 | | /* flash 0 */ |
| 354 | // flash 0 |
| 355 | 355 | PCW16_MEM_FLASH_1, |
| 356 | | /* flash 1 i.e. unexpanded pcw16 */ |
| 356 | // flash 1 i.e. unexpanded pcw16 |
| 357 | 357 | PCW16_MEM_FLASH_2, |
| 358 | | /* dram */ |
| 358 | // dram |
| 359 | 359 | PCW16_MEM_DRAM, |
| 360 | | /* no mem. i.e. unexpanded pcw16 */ |
| 360 | // no mem. i.e. unexpanded pcw16 |
| 361 | 361 | PCW16_MEM_NONE |
| 362 | 362 | }; |
| 363 | 363 | |
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| 366 | 366 | return 0x0ff; |
| 367 | 367 | } |
| 368 | 368 | |
| 369 | | /* |
| 369 | |
| 370 | 370 | static void pcw16_set_bank_handlers(running_machine &machine, int bank, PCW16_RAM_TYPE type) |
| 371 | 371 | { |
| 372 | 372 | address_space &space = machine.device("maincpu")->memory().space(AS_PROGRAM); |
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| 486 | 486 | pcw16_set_bank_handlers(machine, bank, PCW16_MEM_DRAM); |
| 487 | 487 | } |
| 488 | 488 | } |
| 489 | | */ |
| 490 | 489 | |
| 491 | | /* update memory h/w */ |
| 490 | |
| 491 | // update memory h/w |
| 492 | 492 | static void pcw16_update_memory(running_machine &machine) |
| 493 | 493 | { |
| 494 | | // pcw16_update_bank(machine, 0); |
| 495 | | // pcw16_update_bank(machine, 1); |
| 496 | | // pcw16_update_bank(machine, 2); |
| 497 | | // pcw16_update_bank(machine, 3); |
| 494 | pcw16_update_bank(machine, 0); |
| 495 | pcw16_update_bank(machine, 1); |
| 496 | pcw16_update_bank(machine, 2); |
| 497 | pcw16_update_bank(machine, 3); |
| 498 | 498 | |
| 499 | 499 | } |
| 500 | | |
| 500 | */ |
| 501 | 501 | UINT8 pcw16_state::read_bank_data(UINT8 type, UINT16 offset) |
| 502 | 502 | { |
| 503 | 503 | if(type & 0x80) // DRAM |
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| 623 | 623 | |
| 624 | 624 | m_banks[offset] = data; |
| 625 | 625 | |
| 626 | | pcw16_update_memory(machine()); |
| 626 | //pcw16_update_memory(machine()); |
| 627 | 627 | } |
| 628 | 628 | |
| 629 | 629 | WRITE8_MEMBER(pcw16_state::pcw16_video_control_w) |