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| r17799 Tuesday 11th September, 2012 at 16:29:26 UTC by Aaron Giles |
|---|
| Add ambiguous execute() and memory() methods to the device_execute/memory_interfaces respectively in order to catch unnecessary usage of the corresponding device_t methods. Removed all existing redundant usage. [Aaron Giles] |
| [src/emu] | diexec.h dimemory.h distate.h |
| [src/emu/machine] | latch8.c |
| [src/emu/sound] | scsp.c |
| [src/emu/video] | pc_cga.c pc_vga.c |
| [src/mame/audio] | 8080bw.c atarijsa.c cage.c dcs.c harddriv.c |
| [src/mame/drivers] | 8080bw.c deshoros.c gunbustr.c harddriv.c igs017.c magictg.c metro.c midqslvr.c multigam.c namcos22.c pacman.c pntnpuzl.c segae.c |
| [src/mame/machine] | snes.c |
| [src/mame/video] | namcos22.c |
| [src/mess/drivers] | a5105.c a7000.c abc1600.c abc80x.c ace.c adam.c apricot.c apricotf.c atarist.c atom.c avigo.c bigbord2.c bml3.c bw12.c bw2.c c64.c camplynx.c cosmicos.c cxhumax.c elf.c exp85.c fk1.c fp1100.c kyocera.c lc80.c m5.c mc1000.c micronic.c mikromik.c mpf1.c msbc1.c mstation.c newbrain.c next.c ob68k1a.c osi.c pasopia7.c pc1512.c pc8001.c pc8401a.c pce220.c pcfx.c plus4.c poly.c portfoli.c prestige.c prof80.c px8.c ql.c rex6000.c sg1000.c super6.c supracan.c tandy2k.c tek405x.c tiki100.c tmc1800.c tmc600.c tvc.c unixpc.c v1050.c vic10.c victor9k.c vii.c vixen.c wangpc.c x07.c xerox820.c xor100.c z88.c z9001.c |
| [src/mess/formats] | ace_ace.c atom_atm.c cbm_snqk.c comx35_comx.c trs_cmd.c |
| [src/mess/machine] | advision.c amstrad.c c128.c c64.c compis.c comx_clm.c genpc.c hd63450.c kaypro.c kc.c kc_d004.c mac.c mbee.c pc.c sorcerer.c special.c ti85.c trs80.c wswan.c |
| [src/mess/video] | atarist.c isa_cga.c newbrain.c pc_aga.c pc_t1t.c ti85.c |
| r17798 | r17799 | |
|---|---|---|
| 147 | 147 | |
| 148 | 148 | /* install POKEY memory handlers */ |
| 149 | 149 | if (pokey != NULL) |
| 150 | jsacpu-> | |
| 150 | jsacpu-> | |
| 151 | 151 | |
| 152 | 152 | init_save_state(machine); |
| 153 | 153 | atarijsa_reset(); |
| r17798 | r17799 | |
|---|---|---|
| 177 | 177 | state->timer[1] = machine.device<timer_device>("cage_timer1"); |
| 178 | 178 | |
| 179 | 179 | if (speedup) |
| 180 | state->speedup_ram = state->cpu-> | |
| 180 | state->speedup_ram = state->cpu-> | |
| 181 | 181 | |
| 182 | 182 | for (chan = 0; chan < DAC_BUFFER_CHANNELS; chan++) |
| 183 | 183 | { |
| r17798 | r17799 | |
|---|---|---|
| 2141 | 2141 | machine.scheduler().timer_set(attotime::from_usec(1), FUNC(s1_ack_callback2), param); |
| 2142 | 2142 | return; |
| 2143 | 2143 | } |
| 2144 | output_latch_w(dcs.cpu-> | |
| 2144 | output_latch_w(dcs.cpu-> | |
| 2145 | 2145 | } |
| 2146 | 2146 | |
| 2147 | 2147 | |
| r17798 | r17799 | |
| 2153 | 2153 | machine.scheduler().timer_set(attotime::from_usec(1), FUNC(s1_ack_callback1), param); |
| 2154 | 2154 | return; |
| 2155 | 2155 | } |
| 2156 | output_latch_w(dcs.cpu-> | |
| 2156 | output_latch_w(dcs.cpu-> | |
| 2157 | 2157 | |
| 2158 | 2158 | /* chain to the next word we need to write back */ |
| 2159 | 2159 | machine.scheduler().timer_set(attotime::from_usec(1), FUNC(s1_ack_callback2)); |
| r17798 | r17799 | |
| 2285 | 2285 | |
| 2286 | 2286 | static TIMER_CALLBACK( s2_ack_callback ) |
| 2287 | 2287 | { |
| 2288 | address_space *space = dcs.cpu-> | |
| 2288 | address_space *space = dcs.cpu-> | |
| 2289 | 2289 | |
| 2290 | 2290 | /* if the output is full, stall for a usec */ |
| 2291 | 2291 | if (IS_OUTPUT_FULL()) |
| r17798 | r17799 | |
|---|---|---|
| 898 | 898 | |
| 899 | 899 | static void schaser_reinit_555_time_remain(_8080bw_state *state) |
| 900 | 900 | { |
| 901 | address_space *space = state->m_maincpu-> | |
| 901 | address_space *space = state->m_maincpu-> | |
| 902 | 902 | state->m_schaser_effect_555_time_remain = attotime::from_double(state->m_schaser_effect_555_time_remain_savable); |
| 903 | 903 | state->schaser_sh_port_2_w(*space, 0, state->m_port_2_last_extra); |
| 904 | 904 | } |
| r17798 | r17799 | |
|---|---|---|
| 231 | 231 | |
| 232 | 232 | READ16_MEMBER(harddriv_state::hdsnd68k_320ports_r) |
| 233 | 233 | { |
| 234 | address_space *iospace = m_sounddsp->memory().space(AS_IO); | |
| 235 | return iospace->read_word((offset & 7) << 1); | |
| 234 | return m_sounddsp->space(AS_IO)->read_word((offset & 7) << 1); | |
| 236 | 235 | } |
| 237 | 236 | |
| 238 | 237 | |
| 239 | 238 | WRITE16_MEMBER(harddriv_state::hdsnd68k_320ports_w) |
| 240 | 239 | { |
| 241 | address_space *iospace = m_sounddsp->memory().space(AS_IO); | |
| 242 | iospace->write_word((offset & 7) << 1, data); | |
| 240 | m_sounddsp->space(AS_IO)->write_word((offset & 7) << 1, data); | |
| 243 | 241 | } |
| 244 | 242 | |
| 245 | 243 |
| r17798 | r17799 | |
|---|---|---|
| 135 | 135 | { |
| 136 | 136 | snes_state *state = machine.driver_data<snes_state>(); |
| 137 | 137 | // make sure we're in the 65816's context since we're messing with the OAM and stuff |
| 138 | address_space *space = state->m_maincpu-> | |
| 138 | address_space *space = state->m_maincpu-> | |
| 139 | 139 | |
| 140 | 140 | if (!(snes_ppu.screen_disabled)) //Reset OAM address, byuu says it happens at H=10 |
| 141 | 141 | { |
| r17798 | r17799 | |
| 148 | 148 | static TIMER_CALLBACK( snes_reset_hdma ) |
| 149 | 149 | { |
| 150 | 150 | snes_state *state = machine.driver_data<snes_state>(); |
| 151 | address_space *cpu0space = state->m_maincpu-> | |
| 151 | address_space *cpu0space = state->m_maincpu-> | |
| 152 | 152 | snes_hdma_init(cpu0space); |
| 153 | 153 | } |
| 154 | 154 | |
| 155 | 155 | static TIMER_CALLBACK( snes_update_io ) |
| 156 | 156 | { |
| 157 | 157 | snes_state *state = machine.driver_data<snes_state>(); |
| 158 | address_space *cpu0space = state->m_maincpu-> | |
| 158 | address_space *cpu0space = state->m_maincpu-> | |
| 159 | 159 | state->m_io_read(cpu0space->machine()); |
| 160 | 160 | snes_ram[HVBJOY] &= 0xfe; /* Clear busy bit */ |
| 161 | 161 | |
| r17798 | r17799 | |
| 233 | 233 | // hdma reset happens at scanline 0, H=~6 |
| 234 | 234 | if (snes_ppu.beam.current_vert == 0) |
| 235 | 235 | { |
| 236 | address_space *cpu0space = state->m_maincpu-> | |
| 236 | address_space *cpu0space = state->m_maincpu-> | |
| 237 | 237 | snes_hdma_init(cpu0space); |
| 238 | 238 | } |
| 239 | 239 | |
| r17798 | r17799 | |
| 257 | 257 | static TIMER_CALLBACK( snes_hblank_tick ) |
| 258 | 258 | { |
| 259 | 259 | snes_state *state = machine.driver_data<snes_state>(); |
| 260 | address_space *cpu0space = state->m_maincpu-> | |
| 260 | address_space *cpu0space = state->m_maincpu-> | |
| 261 | 261 | int nextscan; |
| 262 | 262 | |
| 263 | 263 | snes_ppu.beam.current_vert = machine.primary_screen->vpos(); |
| r17798 | r17799 | |
|---|---|---|
| 2818 | 2818 | FILE *f = fopen( "dump.txt", "wb" ); |
| 2819 | 2819 | if( f ) |
| 2820 | 2820 | { |
| 2821 | address_space *space = state->m_maincpu-> | |
| 2821 | address_space *space = state->m_maincpu-> | |
| 2822 | 2822 | |
| 2823 | 2823 | if (1) // czram |
| 2824 | 2824 | { |
| r17798 | r17799 | |
| 2883 | 2883 | FILE *f = fopen( "dump.txt", "wb" ); |
| 2884 | 2884 | if( f ) |
| 2885 | 2885 | { |
| 2886 | address_space *space = state->m_maincpu-> | |
| 2886 | address_space *space = state->m_maincpu-> | |
| 2887 | 2887 | |
| 2888 | 2888 | //Dump(space, f,0x90000000, 0x90000003, "led?" ); |
| 2889 | 2889 | Dump(space, f,0x90010000, 0x90017fff, "cz_ram"); |
| r17798 | r17799 | |
|---|---|---|
| 3399 | 3399 | { |
| 3400 | 3400 | igs017_state *state = machine.driver_data<igs017_state>(); |
| 3401 | 3401 | MACHINE_RESET_CALL( mgcs ); |
| 3402 | state->lhzb2a_input_addr_w(*state->m_maincpu-> | |
| 3402 | state->lhzb2a_input_addr_w(*state->m_maincpu-> | |
| 3403 | 3403 | } |
| 3404 | 3404 | |
| 3405 | 3405 | static MACHINE_CONFIG_START( lhzb2a, igs017_state ) |
| r17798 | r17799 | |
|---|---|---|
| 133 | 133 | static void update_irq_state( running_machine &machine ) |
| 134 | 134 | { |
| 135 | 135 | metro_state *state = machine.driver_data<metro_state>(); |
| 136 | address_space *space = state->m_maincpu-> | |
| 136 | address_space *space = state->m_maincpu-> | |
| 137 | 137 | |
| 138 | 138 | /* Get the pending IRQs (only the enabled ones, e.g. where irq_enable is *0*) */ |
| 139 | 139 | UINT16 irq = state->metro_irq_cause_r(*space, 0, 0xffff) & ~*state->m_irq_enable; |
| r17798 | r17799 | |
| 266 | 266 | static int metro_io_callback( device_t *device, int ioline, int state ) |
| 267 | 267 | { |
| 268 | 268 | metro_state *driver_state = device->machine().driver_data<metro_state>(); |
| 269 | address_space *space = driver_state->m_maincpu-> | |
| 269 | address_space *space = driver_state->m_maincpu-> | |
| 270 | 270 | UINT8 data = 0; |
| 271 | 271 | |
| 272 | 272 | switch (ioline) |
| r17798 | r17799 | |
|---|---|---|
| 252 | 252 | |
| 253 | 253 | void destiny_state::machine_reset() |
| 254 | 254 | { |
| 255 | bank_select_w(*m_maincpu-> | |
| 255 | bank_select_w(*m_maincpu-> | |
| 256 | 256 | } |
| 257 | 257 | |
| 258 | 258 | static MACHINE_CONFIG_START( destiny, destiny_state ) |
| r17798 | r17799 | |
|---|---|---|
| 511 | 511 | { |
| 512 | 512 | systeme_state::driver_start(); |
| 513 | 513 | |
| 514 | m_maincpu->memory().space(AS_IO)->install_read_handler(0xf8, 0xf8, read8_delegate(FUNC(systeme_state::ridleofp_port_f8_read), this)); | |
| 515 | m_maincpu->memory().space(AS_IO)->install_write_handler(0xfa, 0xfa, write8_delegate(FUNC(systeme_state::ridleofp_port_fa_write), this)); | |
| 514 | m_maincpu->space(AS_IO)->install_read_handler(0xf8, 0xf8, read8_delegate(FUNC(systeme_state::ridleofp_port_f8_read), this)); | |
| 515 | m_maincpu->space(AS_IO)->install_write_handler(0xfa, 0xfa, write8_delegate(FUNC(systeme_state::ridleofp_port_fa_write), this)); | |
| 516 | 516 | } |
| 517 | 517 | |
| 518 | 518 | |
| r17798 | r17799 | |
| 520 | 520 | { |
| 521 | 521 | systeme_state::driver_start(); |
| 522 | 522 | |
| 523 | m_maincpu->memory().space(AS_IO)->install_read_handler(0xf8, 0xf8, read8_delegate(FUNC(systeme_state::hangonjr_port_f8_read), this)); | |
| 524 | m_maincpu->memory().space(AS_IO)->install_write_handler(0xfa, 0xfa, write8_delegate(FUNC(systeme_state::hangonjr_port_fa_write), this)); | |
| 523 | m_maincpu->space(AS_IO)->install_read_handler(0xf8, 0xf8, read8_delegate(FUNC(systeme_state::hangonjr_port_f8_read), this)); | |
| 524 | m_maincpu->space(AS_IO)->install_write_handler(0xfa, 0xfa, write8_delegate(FUNC(systeme_state::hangonjr_port_fa_write), this)); | |
| 525 | 525 | } |
| 526 | 526 | |
| 527 | 527 |
| r17798 | r17799 | |
|---|---|---|
| 872 | 872 | state->m_supergm3_chr_bank == 0x40 ) |
| 873 | 873 | { |
| 874 | 874 | // VRAM |
| 875 | ppu->memory().space(AS_PROGRAM)->install_read_bank(0x0000, 0x1fff, "bank1"); | |
| 876 | ppu->memory().space(AS_PROGRAM)->install_write_bank(0x0000, 0x1fff, "bank1"); | |
| 875 | ppu->space(AS_PROGRAM)->install_read_bank(0x0000, 0x1fff, "bank1"); | |
| 876 | ppu->space(AS_PROGRAM)->install_write_bank(0x0000, 0x1fff, "bank1"); | |
| 877 | 877 | state->membank("bank1")->set_base(state->m_vram); |
| 878 | 878 | |
| 879 | 879 | if (state->m_supergm3_chr_bank == 0x40) |
| r17798 | r17799 | |
| 881 | 881 | } |
| 882 | 882 | else |
| 883 | 883 | { |
| 884 | ppu->memory().space(AS_PROGRAM)->install_read_bank(0x0000, 0x03ff, "bank2"); | |
| 885 | ppu->memory().space(AS_PROGRAM)->install_read_bank(0x0400, 0x07ff, "bank3"); | |
| 886 | ppu->memory().space(AS_PROGRAM)->install_read_bank(0x0800, 0x0bff, "bank4"); | |
| 887 | ppu->memory().space(AS_PROGRAM)->install_read_bank(0x0c00, 0x0fff, "bank5"); | |
| 888 | ppu->memory().space(AS_PROGRAM)->install_read_bank(0x1000, 0x13ff, "bank6"); | |
| 889 | ppu->memory().space(AS_PROGRAM)->install_read_bank(0x1400, 0x17ff, "bank7"); | |
| 890 | ppu->memory().space(AS_PROGRAM)->install_read_bank(0x1800, 0x1bff, "bank8"); | |
| 891 | ppu->memory().space(AS_PROGRAM)->install_read_bank(0x1c00, 0x1fff, "bank9"); | |
| 892 | ppu->memory().space(AS_PROGRAM)->unmap_write(0x0000, 0x1fff); | |
| 884 | ppu->space(AS_PROGRAM)->install_read_bank(0x0000, 0x03ff, "bank2"); | |
| 885 | ppu->space(AS_PROGRAM)->install_read_bank(0x0400, 0x07ff, "bank3"); | |
| 886 | ppu->space(AS_PROGRAM)->install_read_bank(0x0800, 0x0bff, "bank4"); | |
| 887 | ppu->space(AS_PROGRAM)->install_read_bank(0x0c00, 0x0fff, "bank5"); | |
| 888 | ppu->space(AS_PROGRAM)->install_read_bank(0x1000, 0x13ff, "bank6"); | |
| 889 | ppu->space(AS_PROGRAM)->install_read_bank(0x1400, 0x17ff, "bank7"); | |
| 890 | ppu->space(AS_PROGRAM)->install_read_bank(0x1800, 0x1bff, "bank8"); | |
| 891 | ppu->space(AS_PROGRAM)->install_read_bank(0x1c00, 0x1fff, "bank9"); | |
| 892 | ppu->space(AS_PROGRAM)->unmap_write(0x0000, 0x1fff); | |
| 893 | 893 | |
| 894 | 894 | set_videorom_bank(machine, 0, 8, 0, 8); |
| 895 | 895 | } |
| r17798 | r17799 | |
|---|---|---|
| 251 | 251 | |
| 252 | 252 | static UINT8 piix4_config_r(device_t *busdevice, device_t *device, int function, int reg) |
| 253 | 253 | { |
| 254 | address_space *space = busdevice->machine().firstcpu-> | |
| 254 | address_space *space = busdevice->machine().firstcpu-> | |
| 255 | 255 | midqslvr_state *state = busdevice->machine().driver_data<midqslvr_state>(); |
| 256 | 256 | |
| 257 | 257 | function &= 3; |
| r17798 | r17799 | |
|---|---|---|
| 761 | 761 | UINT32 src_addr = (page << 14) | m_adsp_regs.bdma_external_addr; |
| 762 | 762 | |
| 763 | 763 | if (type == 0) |
| 764 | addr_space = m_adsp-> | |
| 764 | addr_space = m_adsp-> | |
| 765 | 765 | else |
| 766 | addr_space = m_adsp-> | |
| 766 | addr_space = m_adsp-> | |
| 767 | 767 | |
| 768 | 768 | if (dir == 0) |
| 769 | 769 | { |
| r17798 | r17799 | |
|---|---|---|
| 2691 | 2691 | int i; |
| 2692 | 2692 | for (i = 0; i < 16; i++) |
| 2693 | 2693 | { |
| 2694 | generic_pulse_irq_line(m_mcu | |
| 2694 | generic_pulse_irq_line(*m_mcu | |
| 2695 | 2695 | } |
| 2696 | 2696 | } |
| 2697 | 2697 | |
| r17798 | r17799 | |
| 5448 | 5448 | { |
| 5449 | 5449 | namcos22_state *state = machine.driver_data<namcos22_state>(); |
| 5450 | 5450 | if (MCU_SPEEDUP) |
| 5451 | state->m_mcu-> | |
| 5451 | state->m_mcu-> | |
| 5452 | 5452 | } |
| 5453 | 5453 | |
| 5454 | 5454 | static void install_130_speedup(running_machine &machine) |
| r17798 | r17799 | |
| 5456 | 5456 | namcos22_state *state = machine.driver_data<namcos22_state>(); |
| 5457 | 5457 | // install speedup cheat for 1.30 MCU BIOS |
| 5458 | 5458 | if (MCU_SPEEDUP) |
| 5459 | state->m_mcu-> | |
| 5459 | state->m_mcu-> | |
| 5460 | 5460 | } |
| 5461 | 5461 | |
| 5462 | 5462 | static void install_141_speedup(running_machine &machine) |
| r17798 | r17799 | |
| 5464 | 5464 | namcos22_state *state = machine.driver_data<namcos22_state>(); |
| 5465 | 5465 | // install speedup cheat for 1.41 MCU BIOS |
| 5466 | 5466 | if (MCU_SPEEDUP) |
| 5467 | state->m_mcu-> | |
| 5467 | state->m_mcu-> | |
| 5468 | 5468 | } |
| 5469 | 5469 | |
| 5470 | 5470 | static void namcos22_init( running_machine &machine, int game_type ) |
| r17798 | r17799 | |
| 5487 | 5487 | namcos22_state *state = machine.driver_data<namcos22_state>(); |
| 5488 | 5488 | namcos22_init(machine, game_type); |
| 5489 | 5489 | |
| 5490 | state->m_mcu->memory().space(AS_IO)->install_read_handler(M37710_ADC0_L, M37710_ADC7_H, read8_delegate(FUNC(namcos22_state::alpineracer_mcu_adc_r),state)); | |
| 5491 | state->m_mcu->memory().space(AS_IO)->install_write_handler(M37710_PORT5, M37710_PORT5, write8_delegate(FUNC(namcos22_state::alpine_mcu_port5_w),state)); | |
| 5490 | state->m_mcu->space(AS_IO)->install_read_handler(M37710_ADC0_L, M37710_ADC7_H, read8_delegate(FUNC(namcos22_state::alpineracer_mcu_adc_r),state)); | |
| 5491 | state->m_mcu->space(AS_IO)->install_write_handler(M37710_PORT5, M37710_PORT5, write8_delegate(FUNC(namcos22_state::alpine_mcu_port5_w),state)); | |
| 5492 | 5492 | |
| 5493 | 5493 | state->m_motor_timer = machine.scheduler().timer_alloc(FUNC(alpine_steplock_callback)); |
| 5494 | 5494 | state->m_motor_timer->reset(); |
| r17798 | r17799 | |
| 5517 | 5517 | { |
| 5518 | 5518 | alpine_init_common(machine(), NAMCOS22_ALPINE_SURFER); |
| 5519 | 5519 | |
| 5520 | m_maincpu->memory().space(AS_PROGRAM)->install_read_handler (0x200000, 0x200003, read32_delegate(FUNC(namcos22_state::alpinesa_prot_r),this)); | |
| 5521 | m_maincpu->memory().space(AS_PROGRAM)->install_write_handler(0x300000, 0x300003, write32_delegate(FUNC(namcos22_state::alpinesa_prot_w),this)); | |
| 5520 | m_maincpu->space(AS_PROGRAM)->install_read_handler (0x200000, 0x200003, read32_delegate(FUNC(namcos22_state::alpinesa_prot_r),this)); | |
| 5521 | m_maincpu->space(AS_PROGRAM)->install_write_handler(0x300000, 0x300003, write32_delegate(FUNC(namcos22_state::alpinesa_prot_w),this)); | |
| 5522 | 5522 | install_141_speedup(machine()); |
| 5523 | 5523 | |
| 5524 | 5524 | m_keycus_id = 0x01a9; |
| r17798 | r17799 | |
| 5529 | 5529 | namcos22_init(machine(), NAMCOS22_AIR_COMBAT22); |
| 5530 | 5530 | |
| 5531 | 5531 | // S22-BIOS ver1.20 namco all rights reserved 94/12/21 |
| 5532 | m_mcu-> | |
| 5532 | m_mcu-> | |
| 5533 | 5533 | } |
| 5534 | 5534 | |
| 5535 | 5535 | DRIVER_INIT_MEMBER(namcos22_state,propcycl) |
| r17798 | r17799 | |
| 5552 | 5552 | // pROM[0x22296/4] |= 0x00004e75; |
| 5553 | 5553 | |
| 5554 | 5554 | namcos22_init(machine(), NAMCOS22_PROP_CYCLE); |
| 5555 | m_mcu->memory().space(AS_IO)->install_read_handler(M37710_ADC0_L, M37710_ADC7_H, read8_delegate(FUNC(namcos22_state::propcycle_mcu_adc_r),this)); | |
| 5556 | m_mcu->memory().space(AS_IO)->install_write_handler(M37710_PORT5, M37710_PORT5, write8_delegate(FUNC(namcos22_state::propcycle_mcu_port5_w),this)); | |
| 5555 | m_mcu->space(AS_IO)->install_read_handler(M37710_ADC0_L, M37710_ADC7_H, read8_delegate(FUNC(namcos22_state::propcycle_mcu_adc_r),this)); | |
| 5556 | m_mcu->space(AS_IO)->install_write_handler(M37710_PORT5, M37710_PORT5, write8_delegate(FUNC(namcos22_state::propcycle_mcu_port5_w),this)); | |
| 5557 | 5557 | install_141_speedup(machine()); |
| 5558 | 5558 | } |
| 5559 | 5559 | |
| r17798 | r17799 | |
| 5613 | 5613 | { |
| 5614 | 5614 | namcos22_init(machine(), NAMCOS22_CYBER_CYCLES); |
| 5615 | 5615 | |
| 5616 | m_mcu-> | |
| 5616 | m_mcu-> | |
| 5617 | 5617 | install_130_speedup(machine()); |
| 5618 | 5618 | |
| 5619 | 5619 | m_keycus_id = 0x0387; |
| r17798 | r17799 | |
| 5630 | 5630 | { |
| 5631 | 5631 | namcos22_init(machine(), NAMCOS22_TOKYO_WARS); |
| 5632 | 5632 | |
| 5633 | m_mcu-> | |
| 5633 | m_mcu-> | |
| 5634 | 5634 | install_141_speedup(machine()); |
| 5635 | 5635 | |
| 5636 | 5636 | m_keycus_id = 0x01a8; |
| r17798 | r17799 | |
| 5639 | 5639 | DRIVER_INIT_MEMBER(namcos22_state,aquajet) |
| 5640 | 5640 | { |
| 5641 | 5641 | namcos22_init(machine(), NAMCOS22_AQUA_JET); |
| 5642 | m_mcu-> | |
| 5642 | m_mcu-> | |
| 5643 | 5643 | install_141_speedup(machine()); |
| 5644 | 5644 | } |
| 5645 | 5645 | |
| r17798 | r17799 | |
| 5647 | 5647 | { |
| 5648 | 5648 | namcos22_init(machine(), NAMCOS22_DIRT_DASH); |
| 5649 | 5649 | |
| 5650 | m_mcu-> | |
| 5650 | m_mcu-> | |
| 5651 | 5651 | install_141_speedup(machine()); |
| 5652 | 5652 | |
| 5653 | 5653 | m_keycus_id = 0x01a2; |
| r17798 | r17799 | |
|---|---|---|
| 2533 | 2533 | { |
| 2534 | 2534 | _8080bw_state *state = machine.driver_data<_8080bw_state>(); |
| 2535 | 2535 | |
| 2536 | state->invmulti_bank_w(*state->m_maincpu-> | |
| 2536 | state->invmulti_bank_w(*state->m_maincpu-> | |
| 2537 | 2537 | |
| 2538 | 2538 | MACHINE_RESET_CALL(mw8080bw); |
| 2539 | 2539 | } |
| r17798 | r17799 | |
|---|---|---|
| 3999 | 3999 | /* install handlers for the compact driving games' inputs */ |
| 4000 | 4000 | if (compact_inputs) |
| 4001 | 4001 | { |
| 4002 | state->m_maincpu->memory().space(AS_PROGRAM)->install_legacy_read_handler(0x400000, 0x400001, FUNC(hdc68k_wheel_r)); | |
| 4003 | state->m_maincpu->memory().space(AS_PROGRAM)->install_legacy_write_handler(0x408000, 0x408001, FUNC(hdc68k_wheel_edge_reset_w)); | |
| 4004 | state->m_maincpu->memory().space(AS_PROGRAM)->install_legacy_read_handler(0xa80000, 0xafffff, FUNC(hdc68k_port1_r)); | |
| 4002 | state->m_maincpu->space(AS_PROGRAM)->install_legacy_read_handler(0x400000, 0x400001, FUNC(hdc68k_wheel_r)); | |
| 4003 | state->m_maincpu->space(AS_PROGRAM)->install_legacy_write_handler(0x408000, 0x408001, FUNC(hdc68k_wheel_edge_reset_w)); | |
| 4004 | state->m_maincpu->space(AS_PROGRAM)->install_legacy_read_handler(0xa80000, 0xafffff, FUNC(hdc68k_port1_r)); | |
| 4005 | 4005 | } |
| 4006 | 4006 | } |
| 4007 | 4007 | |
| r17798 | r17799 | |
| 4012 | 4012 | harddriv_state *state = machine.driver_data<harddriv_state>(); |
| 4013 | 4013 | |
| 4014 | 4014 | /* install ADSP program RAM */ |
| 4015 | state->m_maincpu-> | |
| 4015 | state->m_maincpu-> | |
| 4016 | 4016 | |
| 4017 | 4017 | /* install ADSP data RAM */ |
| 4018 | state->m_maincpu-> | |
| 4018 | state->m_maincpu-> | |
| 4019 | 4019 | |
| 4020 | 4020 | /* install ADSP serial buffer RAM */ |
| 4021 | state->m_maincpu-> | |
| 4021 | state->m_maincpu-> | |
| 4022 | 4022 | |
| 4023 | 4023 | /* install ADSP control locations */ |
| 4024 | state->m_maincpu->memory().space(AS_PROGRAM)->install_legacy_write_handler(0x818000, 0x81801f, FUNC(hd68k_adsp_control_w)); | |
| 4025 | state->m_maincpu->memory().space(AS_PROGRAM)->install_legacy_write_handler(0x818060, 0x81807f, FUNC(hd68k_adsp_irq_clear_w)); | |
| 4026 | state->m_maincpu->memory().space(AS_PROGRAM)->install_legacy_read_handler(0x838000, 0x83ffff, FUNC(hd68k_adsp_irq_state_r)); | |
| 4024 | state->m_maincpu->space(AS_PROGRAM)->install_legacy_write_handler(0x818000, 0x81801f, FUNC(hd68k_adsp_control_w)); | |
| 4025 | state->m_maincpu->space(AS_PROGRAM)->install_legacy_write_handler(0x818060, 0x81807f, FUNC(hd68k_adsp_irq_clear_w)); | |
| 4026 | state->m_maincpu->space(AS_PROGRAM)->install_legacy_read_handler(0x838000, 0x83ffff, FUNC(hd68k_adsp_irq_state_r)); | |
| 4027 | 4027 | } |
| 4028 | 4028 | |
| 4029 | 4029 | |
| r17798 | r17799 | |
| 4033 | 4033 | harddriv_state *state = machine.driver_data<harddriv_state>(); |
| 4034 | 4034 | |
| 4035 | 4035 | /* install ADSP program RAM */ |
| 4036 | state->m_maincpu-> | |
| 4036 | state->m_maincpu-> | |
| 4037 | 4037 | |
| 4038 | 4038 | /* install ADSP data RAM */ |
| 4039 | state->m_maincpu->memory().space(AS_PROGRAM)->install_legacy_readwrite_handler(0x808000, 0x80bfff, FUNC(hd68k_adsp_data_r), FUNC(hd68k_adsp_data_w)); | |
| 4040 | state->m_maincpu->memory().space(AS_PROGRAM)->install_legacy_readwrite_handler(0x80c000, 0x80dfff, FUNC(hdds3_special_r), FUNC(hdds3_special_w)); | |
| 4039 | state->m_maincpu->space(AS_PROGRAM)->install_legacy_readwrite_handler(0x808000, 0x80bfff, FUNC(hd68k_adsp_data_r), FUNC(hd68k_adsp_data_w)); | |
| 4040 | state->m_maincpu->space(AS_PROGRAM)->install_legacy_readwrite_handler(0x80c000, 0x80dfff, FUNC(hdds3_special_r), FUNC(hdds3_special_w)); | |
| 4041 | 4041 | |
| 4042 | 4042 | /* install ADSP control locations */ |
| 4043 | state->m_maincpu->memory().space(AS_PROGRAM)->install_legacy_read_handler(0x820000, 0x8207ff, FUNC(hd68k_ds3_gdata_r)); | |
| 4044 | state->m_maincpu->memory().space(AS_PROGRAM)->install_legacy_read_handler(0x820800, 0x820fff, FUNC(hd68k_ds3_girq_state_r)); | |
| 4045 | state->m_maincpu->memory().space(AS_PROGRAM)->install_legacy_write_handler(0x820000, 0x8207ff, FUNC(hd68k_ds3_gdata_w)); | |
| 4046 | state->m_maincpu->memory().space(AS_PROGRAM)->install_legacy_write_handler(0x821000, 0x8217ff, FUNC(hd68k_adsp_irq_clear_w)); | |
| 4047 | state->m_maincpu->memory().space(AS_PROGRAM)->install_legacy_read_handler(0x822000, 0x8227ff, FUNC(hd68k_ds3_sdata_r)); | |
| 4048 | state->m_maincpu->memory().space(AS_PROGRAM)->install_legacy_read_handler(0x822800, 0x822fff, FUNC(hd68k_ds3_sirq_state_r)); | |
| 4049 | state->m_maincpu->memory().space(AS_PROGRAM)->install_legacy_write_handler(0x822000, 0x8227ff, FUNC(hd68k_ds3_sdata_w)); | |
| 4050 | state->m_maincpu->memory().space(AS_PROGRAM)->install_legacy_write_handler(0x823800, 0x823fff, FUNC(hd68k_ds3_control_w)); | |
| 4043 | state->m_maincpu->space(AS_PROGRAM)->install_legacy_read_handler(0x820000, 0x8207ff, FUNC(hd68k_ds3_gdata_r)); | |
| 4044 | state->m_maincpu->space(AS_PROGRAM)->install_legacy_read_handler(0x820800, 0x820fff, FUNC(hd68k_ds3_girq_state_r)); | |
| 4045 | state->m_maincpu->space(AS_PROGRAM)->install_legacy_write_handler(0x820000, 0x8207ff, FUNC(hd68k_ds3_gdata_w)); | |
| 4046 | state->m_maincpu->space(AS_PROGRAM)->install_legacy_write_handler(0x821000, 0x8217ff, FUNC(hd68k_adsp_irq_clear_w)); | |
| 4047 | state->m_maincpu->space(AS_PROGRAM)->install_legacy_read_handler(0x822000, 0x8227ff, FUNC(hd68k_ds3_sdata_r)); | |
| 4048 | state->m_maincpu->space(AS_PROGRAM)->install_legacy_read_handler(0x822800, 0x822fff, FUNC(hd68k_ds3_sirq_state_r)); | |
| 4049 | state->m_maincpu->space(AS_PROGRAM)->install_legacy_write_handler(0x822000, 0x8227ff, FUNC(hd68k_ds3_sdata_w)); | |
| 4050 | state->m_maincpu->space(AS_PROGRAM)->install_legacy_write_handler(0x823800, 0x823fff, FUNC(hd68k_ds3_control_w)); | |
| 4051 | 4051 | |
| 4052 | 4052 | /* if we have a sound DSP, boot it */ |
| 4053 | 4053 | if (state->m_ds4cpu1 != NULL) |
| r17798 | r17799 | |
| 4132 | 4132 | UINT8 *usr3 = state->memregion("user3")->base(); |
| 4133 | 4133 | |
| 4134 | 4134 | /* install ASIC61 */ |
| 4135 | state->m_maincpu-> | |
| 4135 | state->m_maincpu-> | |
| 4136 | 4136 | |
| 4137 | 4137 | /* install control registers */ |
| 4138 | state->m_maincpu-> | |
| 4138 | state->m_maincpu-> | |
| 4139 | 4139 | |
| 4140 | 4140 | /* install extra RAM */ |
| 4141 | state->m_maincpu-> | |
| 4141 | state->m_maincpu-> | |
| 4142 | 4142 | state->m_dsk_ram = (UINT16 *)(usr3 + 0x40000); |
| 4143 | 4143 | |
| 4144 | 4144 | /* install extra ZRAM */ |
| 4145 | state->m_maincpu-> | |
| 4145 | state->m_maincpu-> | |
| 4146 | 4146 | state->m_dsk_zram = (UINT16 *)(usr3 + 0x50000); |
| 4147 | 4147 | |
| 4148 | 4148 | /* install ASIC65 */ |
| 4149 | state->m_maincpu->memory().space(AS_PROGRAM)->install_legacy_write_handler(0x914000, 0x917fff, FUNC(asic65_data_w)); | |
| 4150 | state->m_maincpu->memory().space(AS_PROGRAM)->install_legacy_read_handler(0x914000, 0x917fff, FUNC(asic65_r)); | |
| 4151 | state->m_maincpu->memory().space(AS_PROGRAM)->install_legacy_read_handler(0x918000, 0x91bfff, FUNC(asic65_io_r)); | |
| 4149 | state->m_maincpu->space(AS_PROGRAM)->install_legacy_write_handler(0x914000, 0x917fff, FUNC(asic65_data_w)); | |
| 4150 | state->m_maincpu->space(AS_PROGRAM)->install_legacy_read_handler(0x914000, 0x917fff, FUNC(asic65_r)); | |
| 4151 | state->m_maincpu->space(AS_PROGRAM)->install_legacy_read_handler(0x918000, 0x91bfff, FUNC(asic65_io_r)); | |
| 4152 | 4152 | |
| 4153 | 4153 | /* install extra ROM */ |
| 4154 | state->m_maincpu-> | |
| 4154 | state->m_maincpu-> | |
| 4155 | 4155 | state->m_dsk_rom = (UINT16 *)(usr3 + 0x00000); |
| 4156 | 4156 | |
| 4157 | 4157 | /* set up the ASIC65 */ |
| r17798 | r17799 | |
| 4166 | 4166 | UINT8 *usr3 = state->memregion("user3")->base(); |
| 4167 | 4167 | |
| 4168 | 4168 | /* install ASIC65 */ |
| 4169 | state->m_maincpu->memory().space(AS_PROGRAM)->install_legacy_write_handler(0x824000, 0x824003, FUNC(asic65_data_w)); | |
| 4170 | state->m_maincpu->memory().space(AS_PROGRAM)->install_legacy_read_handler(0x824000, 0x824003, FUNC(asic65_r)); | |
| 4171 | state->m_maincpu->memory().space(AS_PROGRAM)->install_legacy_read_handler(0x825000, 0x825001, FUNC(asic65_io_r)); | |
| 4169 | state->m_maincpu->space(AS_PROGRAM)->install_legacy_write_handler(0x824000, 0x824003, FUNC(asic65_data_w)); | |
| 4170 | state->m_maincpu->space(AS_PROGRAM)->install_legacy_read_handler(0x824000, 0x824003, FUNC(asic65_r)); | |
| 4171 | state->m_maincpu->space(AS_PROGRAM)->install_legacy_read_handler(0x825000, 0x825001, FUNC(asic65_io_r)); | |
| 4172 | 4172 | |
| 4173 | 4173 | /* install ASIC61 */ |
| 4174 | state->m_maincpu-> | |
| 4174 | state->m_maincpu-> | |
| 4175 | 4175 | |
| 4176 | 4176 | /* install control registers */ |
| 4177 | state->m_maincpu-> | |
| 4177 | state->m_maincpu-> | |
| 4178 | 4178 | |
| 4179 | 4179 | /* install extra RAM */ |
| 4180 | state->m_maincpu-> | |
| 4180 | state->m_maincpu-> | |
| 4181 | 4181 | state->m_dsk_ram = (UINT16 *)(usr3 + 0x100000); |
| 4182 | 4182 | |
| 4183 | 4183 | /* install extra ROM */ |
| 4184 | state->m_maincpu-> | |
| 4184 | state->m_maincpu-> | |
| 4185 | 4185 | state->m_dsk_rom = (UINT16 *)(usr3 + 0x000000); |
| 4186 | 4186 | |
| 4187 | 4187 | /* set up the ASIC65 */ |
| r17798 | r17799 | |
| 4195 | 4195 | harddriv_state *state = machine.driver_data<harddriv_state>(); |
| 4196 | 4196 | |
| 4197 | 4197 | /* install ASIC65 */ |
| 4198 | state->m_maincpu->memory().space(AS_PROGRAM)->install_legacy_write_handler(0x900000, 0x900003, FUNC(asic65_data_w)); | |
| 4199 | state->m_maincpu->memory().space(AS_PROGRAM)->install_legacy_read_handler(0x900000, 0x900003, FUNC(asic65_r)); | |
| 4200 | state->m_maincpu->memory().space(AS_PROGRAM)->install_legacy_read_handler(0x901000, 0x910001, FUNC(asic65_io_r)); | |
| 4198 | state->m_maincpu->space(AS_PROGRAM)->install_legacy_write_handler(0x900000, 0x900003, FUNC(asic65_data_w)); | |
| 4199 | state->m_maincpu->space(AS_PROGRAM)->install_legacy_read_handler(0x900000, 0x900003, FUNC(asic65_r)); | |
| 4200 | state->m_maincpu->space(AS_PROGRAM)->install_legacy_read_handler(0x901000, 0x910001, FUNC(asic65_io_r)); | |
| 4201 | 4201 | |
| 4202 | 4202 | /* set up the ASIC65 */ |
| 4203 | 4203 | asic65_config(machine, ASIC65_STEELTAL); |
| 4204 | 4204 | |
| 4205 | 4205 | /* install DSPCOM control */ |
| 4206 | state->m_maincpu-> | |
| 4206 | state->m_maincpu-> | |
| 4207 | 4207 | } |
| 4208 | 4208 | |
| 4209 | 4209 | |
| r17798 | r17799 | |
| 4215 | 4215 | hdsnd_init(machine); |
| 4216 | 4216 | |
| 4217 | 4217 | /* install sound handlers */ |
| 4218 | state->m_maincpu->memory().space(AS_PROGRAM)->install_readwrite_handler(0x840000, 0x840001, read16_delegate(FUNC(harddriv_state::hd68k_snd_data_r),state), write16_delegate(FUNC(harddriv_state::hd68k_snd_data_w),state)); | |
| 4219 | state->m_maincpu->memory().space(AS_PROGRAM)->install_read_handler(0x844000, 0x844001, read16_delegate(FUNC(harddriv_state::hd68k_snd_status_r),state)); | |
| 4220 | state->m_maincpu->memory().space(AS_PROGRAM)->install_write_handler(0x84c000, 0x84c001, write16_delegate(FUNC(harddriv_state::hd68k_snd_reset_w),state)); | |
| 4218 | state->m_maincpu->space(AS_PROGRAM)->install_readwrite_handler(0x840000, 0x840001, read16_delegate(FUNC(harddriv_state::hd68k_snd_data_r),state), write16_delegate(FUNC(harddriv_state::hd68k_snd_data_w),state)); | |
| 4219 | state->m_maincpu->space(AS_PROGRAM)->install_read_handler(0x844000, 0x844001, read16_delegate(FUNC(harddriv_state::hd68k_snd_status_r),state)); | |
| 4220 | state->m_maincpu->space(AS_PROGRAM)->install_write_handler(0x84c000, 0x84c001, write16_delegate(FUNC(harddriv_state::hd68k_snd_reset_w),state)); | |
| 4221 | 4221 | } |
| 4222 | 4222 | |
| 4223 | 4223 | |
| r17798 | r17799 | |
| 4238 | 4238 | init_driver_sound(machine()); |
| 4239 | 4239 | |
| 4240 | 4240 | /* set up gsp speedup handler */ |
| 4241 | m_gsp_speedup_addr[0] = m_gsp->memory().space(AS_PROGRAM)->install_legacy_write_handler(0xfff9fc00, 0xfff9fc0f, FUNC(hdgsp_speedup1_w)); | |
| 4242 | m_gsp_speedup_addr[1] = m_gsp->memory().space(AS_PROGRAM)->install_legacy_write_handler(0xfffcfc00, 0xfffcfc0f, FUNC(hdgsp_speedup2_w)); | |
| 4243 | m_gsp->memory().space(AS_PROGRAM)->install_legacy_read_handler(0xfff9fc00, 0xfff9fc0f, FUNC(hdgsp_speedup_r)); | |
| 4241 | m_gsp_speedup_addr[0] = m_gsp->space(AS_PROGRAM)->install_legacy_write_handler(0xfff9fc00, 0xfff9fc0f, FUNC(hdgsp_speedup1_w)); | |
| 4242 | m_gsp_speedup_addr[1] = m_gsp->space(AS_PROGRAM)->install_legacy_write_handler(0xfffcfc00, 0xfffcfc0f, FUNC(hdgsp_speedup2_w)); | |
| 4243 | m_gsp->space(AS_PROGRAM)->install_legacy_read_handler(0xfff9fc00, 0xfff9fc0f, FUNC(hdgsp_speedup_r)); | |
| 4244 | 4244 | m_gsp_speedup_pc = 0xffc00f10; |
| 4245 | 4245 | |
| 4246 | 4246 | /* set up msp speedup handler */ |
| 4247 | m_msp_speedup_addr = m_msp->memory().space(AS_PROGRAM)->install_legacy_write_handler(0x00751b00, 0x00751b0f, FUNC(hdmsp_speedup_w)); | |
| 4248 | m_msp->memory().space(AS_PROGRAM)->install_legacy_read_handler(0x00751b00, 0x00751b0f, FUNC(hdmsp_speedup_r)); | |
| 4247 | m_msp_speedup_addr = m_msp->space(AS_PROGRAM)->install_legacy_write_handler(0x00751b00, 0x00751b0f, FUNC(hdmsp_speedup_w)); | |
| 4248 | m_msp->space(AS_PROGRAM)->install_legacy_read_handler(0x00751b00, 0x00751b0f, FUNC(hdmsp_speedup_r)); | |
| 4249 | 4249 | m_msp_speedup_pc = 0x00723b00; |
| 4250 | 4250 | |
| 4251 | 4251 | /* set up adsp speedup handlers */ |
| 4252 | m_adsp-> | |
| 4252 | m_adsp-> | |
| 4253 | 4253 | } |
| 4254 | 4254 | |
| 4255 | 4255 | |
| r17798 | r17799 | |
| 4262 | 4262 | init_driver_sound(machine()); |
| 4263 | 4263 | |
| 4264 | 4264 | /* set up gsp speedup handler */ |
| 4265 | m_gsp_speedup_addr[0] = m_gsp->memory().space(AS_PROGRAM)->install_legacy_write_handler(0xfff9fc00, 0xfff9fc0f, FUNC(hdgsp_speedup1_w)); | |
| 4266 | m_gsp_speedup_addr[1] = m_gsp->memory().space(AS_PROGRAM)->install_legacy_write_handler(0xfffcfc00, 0xfffcfc0f, FUNC(hdgsp_speedup2_w)); | |
| 4267 | m_gsp->memory().space(AS_PROGRAM)->install_legacy_read_handler(0xfff9fc00, 0xfff9fc0f, FUNC(hdgsp_speedup_r)); | |
| 4265 | m_gsp_speedup_addr[0] = m_gsp->space(AS_PROGRAM)->install_legacy_write_handler(0xfff9fc00, 0xfff9fc0f, FUNC(hdgsp_speedup1_w)); | |
| 4266 | m_gsp_speedup_addr[1] = m_gsp->space(AS_PROGRAM)->install_legacy_write_handler(0xfffcfc00, 0xfffcfc0f, FUNC(hdgsp_speedup2_w)); | |
| 4267 | m_gsp->space(AS_PROGRAM)->install_legacy_read_handler(0xfff9fc00, 0xfff9fc0f, FUNC(hdgsp_speedup_r)); | |
| 4268 | 4268 | m_gsp_speedup_pc = 0xfff40ff0; |
| 4269 | 4269 | |
| 4270 | 4270 | /* set up msp speedup handler */ |
| 4271 | m_msp_speedup_addr = m_msp->memory().space(AS_PROGRAM)->install_legacy_write_handler(0x00751b00, 0x00751b0f, FUNC(hdmsp_speedup_w)); | |
| 4272 | m_msp->memory().space(AS_PROGRAM)->install_legacy_read_handler(0x00751b00, 0x00751b0f, FUNC(hdmsp_speedup_r)); | |
| 4271 | m_msp_speedup_addr = m_msp->space(AS_PROGRAM)->install_legacy_write_handler(0x00751b00, 0x00751b0f, FUNC(hdmsp_speedup_w)); | |
| 4272 | m_msp->space(AS_PROGRAM)->install_legacy_read_handler(0x00751b00, 0x00751b0f, FUNC(hdmsp_speedup_r)); | |
| 4273 | 4273 | m_msp_speedup_pc = 0x00723b00; |
| 4274 | 4274 | |
| 4275 | 4275 | /* set up adsp speedup handlers */ |
| 4276 | m_adsp-> | |
| 4276 | m_adsp-> | |
| 4277 | 4277 | } |
| 4278 | 4278 | |
| 4279 | 4279 | |
| r17798 | r17799 | |
| 4286 | 4286 | atarijsa_init(machine(), "IN0", 0x0020); |
| 4287 | 4287 | |
| 4288 | 4288 | /* set up gsp speedup handler */ |
| 4289 | m_gsp_speedup_addr[0] = m_gsp->memory().space(AS_PROGRAM)->install_legacy_write_handler(0xfff9fc00, 0xfff9fc0f, FUNC(hdgsp_speedup1_w)); | |
| 4290 | m_gsp_speedup_addr[1] = m_gsp->memory().space(AS_PROGRAM)->install_legacy_write_handler(0xfffcfc00, 0xfffcfc0f, FUNC(hdgsp_speedup2_w)); | |
| 4291 | m_gsp->memory().space(AS_PROGRAM)->install_legacy_read_handler(0xfff9fc00, 0xfff9fc0f, FUNC(hdgsp_speedup_r)); | |
| 4289 | m_gsp_speedup_addr[0] = m_gsp->space(AS_PROGRAM)->install_legacy_write_handler(0xfff9fc00, 0xfff9fc0f, FUNC(hdgsp_speedup1_w)); | |
| 4290 | m_gsp_speedup_addr[1] = m_gsp->space(AS_PROGRAM)->install_legacy_write_handler(0xfffcfc00, 0xfffcfc0f, FUNC(hdgsp_speedup2_w)); | |
| 4291 | m_gsp->space(AS_PROGRAM)->install_legacy_read_handler(0xfff9fc00, 0xfff9fc0f, FUNC(hdgsp_speedup_r)); | |
| 4292 | 4292 | m_gsp_speedup_pc = 0xfff41070; |
| 4293 | 4293 | |
| 4294 | 4294 | /* set up adsp speedup handlers */ |
| 4295 | m_adsp-> | |
| 4295 | m_adsp-> | |
| 4296 | 4296 | } |
| 4297 | 4297 | |
| 4298 | 4298 | |
| r17798 | r17799 | |
| 4307 | 4307 | |
| 4308 | 4308 | /* set up the slapstic */ |
| 4309 | 4309 | slapstic_init(machine(), 117); |
| 4310 | m_m68k_slapstic_base = m_maincpu-> | |
| 4310 | m_m68k_slapstic_base = m_maincpu-> | |
| 4311 | 4311 | |
| 4312 | 4312 | /* synchronization */ |
| 4313 | m_rddsp32_sync[0] = m_dsp32->memory().space(AS_PROGRAM)->install_legacy_write_handler(0x613c00, 0x613c03, FUNC(rddsp32_sync0_w)); | |
| 4314 | m_rddsp32_sync[1] = m_dsp32->memory().space(AS_PROGRAM)->install_legacy_write_handler(0x613e00, 0x613e03, FUNC(rddsp32_sync1_w)); | |
| 4313 | m_rddsp32_sync[0] = m_dsp32->space(AS_PROGRAM)->install_legacy_write_handler(0x613c00, 0x613c03, FUNC(rddsp32_sync0_w)); | |
| 4314 | m_rddsp32_sync[1] = m_dsp32->space(AS_PROGRAM)->install_legacy_write_handler(0x613e00, 0x613e03, FUNC(rddsp32_sync1_w)); | |
| 4315 | 4315 | |
| 4316 | 4316 | /* set up adsp speedup handlers */ |
| 4317 | m_adsp-> | |
| 4317 | m_adsp-> | |
| 4318 | 4318 | } |
| 4319 | 4319 | |
| 4320 | 4320 | |
| r17798 | r17799 | |
| 4330 | 4330 | |
| 4331 | 4331 | /* set up the slapstic */ |
| 4332 | 4332 | slapstic_init(machine, 117); |
| 4333 | state->m_m68k_slapstic_base = state->m_maincpu-> | |
| 4333 | state->m_m68k_slapstic_base = state->m_maincpu-> | |
| 4334 | 4334 | |
| 4335 | 4335 | /* synchronization */ |
| 4336 | state->m_rddsp32_sync[0] = state->m_dsp32->memory().space(AS_PROGRAM)->install_legacy_write_handler(0x613c00, 0x613c03, FUNC(rddsp32_sync0_w)); | |
| 4337 | state->m_rddsp32_sync[1] = state->m_dsp32->memory().space(AS_PROGRAM)->install_legacy_write_handler(0x613e00, 0x613e03, FUNC(rddsp32_sync1_w)); | |
| 4336 | state->m_rddsp32_sync[0] = state->m_dsp32->space(AS_PROGRAM)->install_legacy_write_handler(0x613c00, 0x613c03, FUNC(rddsp32_sync0_w)); | |
| 4337 | state->m_rddsp32_sync[1] = state->m_dsp32->space(AS_PROGRAM)->install_legacy_write_handler(0x613e00, 0x613e03, FUNC(rddsp32_sync1_w)); | |
| 4338 | 4338 | |
| 4339 | 4339 | /* set up protection hacks */ |
| 4340 | state->m_gsp_protection = state->m_gsp-> | |
| 4340 | state->m_gsp_protection = state->m_gsp-> | |
| 4341 | 4341 | |
| 4342 | 4342 | /* set up gsp speedup handler */ |
| 4343 | state->m_gsp_speedup_addr[0] = state->m_gsp->memory().space(AS_PROGRAM)->install_legacy_write_handler(0xfff76f60, 0xfff76f6f, FUNC(rdgsp_speedup1_w)); | |
| 4344 | state->m_gsp->memory().space(AS_PROGRAM)->install_legacy_read_handler(0xfff76f60, 0xfff76f6f, FUNC(rdgsp_speedup1_r)); | |
| 4343 | state->m_gsp_speedup_addr[0] = state->m_gsp->space(AS_PROGRAM)->install_legacy_write_handler(0xfff76f60, 0xfff76f6f, FUNC(rdgsp_speedup1_w)); | |
| 4344 | state->m_gsp->space(AS_PROGRAM)->install_legacy_read_handler(0xfff76f60, 0xfff76f6f, FUNC(rdgsp_speedup1_r)); | |
| 4345 | 4345 | state->m_gsp_speedup_pc = 0xfff43a00; |
| 4346 | 4346 | |
| 4347 | 4347 | /* set up adsp speedup handlers */ |
| 4348 | state->m_adsp-> | |
| 4348 | state->m_adsp-> | |
| 4349 | 4349 | } |
| 4350 | 4350 | |
| 4351 | 4351 | DRIVER_INIT_MEMBER(harddriv_state,racedrivc) { racedrivc_init_common(machine(), 0xfff95cd0); } |
| r17798 | r17799 | |
| 4357 | 4357 | /* this unpleasantness prevents racedrivb1 and racedrivg1 from crashing MAME during boot */ |
| 4358 | 4358 | /* both clear the DSP32C's RAM and then release it from reset, causing it to run through */ |
| 4359 | 4359 | /* its address space recursively executing instructions */ |
| 4360 | m_dsp32->memory().space(AS_PROGRAM)->install_read_handler(0x002000, 0x5fffff, read32_delegate(FUNC(harddriv_state::rddsp_unmap_r),this)); | |
| 4361 | m_dsp32->memory().space(AS_PROGRAM)->install_read_handler(0x640000, 0xfff7ff, read32_delegate(FUNC(harddriv_state::rddsp_unmap_r),this)); | |
| 4360 | m_dsp32->space(AS_PROGRAM)->install_read_handler(0x002000, 0x5fffff, read32_delegate(FUNC(harddriv_state::rddsp_unmap_r),this)); | |
| 4361 | m_dsp32->space(AS_PROGRAM)->install_read_handler(0x640000, 0xfff7ff, read32_delegate(FUNC(harddriv_state::rddsp_unmap_r),this)); | |
| 4362 | 4362 | |
| 4363 | 4363 | DRIVER_INIT_CALL(racedriv); |
| 4364 | 4364 | } |
| r17798 | r17799 | |
| 4385 | 4385 | init_dspcom(machine); |
| 4386 | 4386 | atarijsa_init(machine, "IN0", 0x0020); |
| 4387 | 4387 | |
| 4388 | state->m_maincpu-> | |
| 4388 | state->m_maincpu-> | |
| 4389 | 4389 | |
| 4390 | 4390 | /* set up the SLOOP */ |
| 4391 | 4391 | if (!proto_sloop) |
| 4392 | 4392 | { |
| 4393 | state->m_m68k_slapstic_base = state->m_maincpu->memory().space(AS_PROGRAM)->install_legacy_readwrite_handler(0xe0000, 0xfffff, FUNC(st68k_sloop_r), FUNC(st68k_sloop_w)); | |
| 4394 | state->m_m68k_sloop_alt_base = state->m_maincpu->memory().space(AS_PROGRAM)->install_legacy_read_handler(0x4e000, 0x4ffff, FUNC(st68k_sloop_alt_r)); | |
| 4393 | state->m_m68k_slapstic_base = state->m_maincpu->space(AS_PROGRAM)->install_legacy_readwrite_handler(0xe0000, 0xfffff, FUNC(st68k_sloop_r), FUNC(st68k_sloop_w)); | |
| 4394 | state->m_m68k_sloop_alt_base = state->m_maincpu->space(AS_PROGRAM)->install_legacy_read_handler(0x4e000, 0x4ffff, FUNC(st68k_sloop_alt_r)); | |
| 4395 | 4395 | } |
| 4396 | 4396 | else |
| 4397 | state->m_m68k_slapstic_base = state->m_maincpu-> | |
| 4397 | state->m_m68k_slapstic_base = state->m_maincpu-> | |
| 4398 | 4398 | |
| 4399 | 4399 | /* set up protection hacks */ |
| 4400 | state->m_gsp_protection = state->m_gsp-> | |
| 4400 | state->m_gsp_protection = state->m_gsp-> | |
| 4401 | 4401 | |
| 4402 | 4402 | /* set up adsp speedup handlers */ |
| 4403 | state->m_adsp->memory().space(AS_DATA)->install_legacy_read_handler(0x1fff, 0x1fff, FUNC(hdadsp_speedup_r)); | |
| 4404 | state->m_adsp->memory().space(AS_DATA)->install_legacy_read_handler(0x1f99, 0x1f99, FUNC(hdds3_speedup_r)); | |
| 4403 | state->m_adsp->space(AS_DATA)->install_legacy_read_handler(0x1fff, 0x1fff, FUNC(hdadsp_speedup_r)); | |
| 4404 | state->m_adsp->space(AS_DATA)->install_legacy_read_handler(0x1f99, 0x1f99, FUNC(hdds3_speedup_r)); | |
| 4405 | 4405 | state->m_ds3_speedup_addr = &state->m_adsp_data_memory[0x1f99]; |
| 4406 | 4406 | state->m_ds3_speedup_pc = 0xff; |
| 4407 | 4407 | state->m_ds3_transfer_pc = ds3_transfer_pc; |
| r17798 | r17799 | |
| 4423 | 4423 | |
| 4424 | 4424 | /* set up the slapstic */ |
| 4425 | 4425 | slapstic_init(machine(), 117); |
| 4426 | m_m68k_slapstic_base = m_maincpu-> | |
| 4426 | m_m68k_slapstic_base = m_maincpu-> | |
| 4427 | 4427 | |
| 4428 | m_maincpu-> | |
| 4428 | m_maincpu-> | |
| 4429 | 4429 | |
| 4430 | 4430 | /* synchronization */ |
| 4431 | m_rddsp32_sync[0] = m_dsp32->memory().space(AS_PROGRAM)->install_legacy_write_handler(0x613c00, 0x613c03, FUNC(rddsp32_sync0_w)); | |
| 4432 | m_rddsp32_sync[1] = m_dsp32->memory().space(AS_PROGRAM)->install_legacy_write_handler(0x613e00, 0x613e03, FUNC(rddsp32_sync1_w)); | |
| 4431 | m_rddsp32_sync[0] = m_dsp32->space(AS_PROGRAM)->install_legacy_write_handler(0x613c00, 0x613c03, FUNC(rddsp32_sync0_w)); | |
| 4432 | m_rddsp32_sync[1] = m_dsp32->space(AS_PROGRAM)->install_legacy_write_handler(0x613e00, 0x613e03, FUNC(rddsp32_sync1_w)); | |
| 4433 | 4433 | |
| 4434 | 4434 | /* set up protection hacks */ |
| 4435 | m_gsp_protection = m_gsp-> | |
| 4435 | m_gsp_protection = m_gsp-> | |
| 4436 | 4436 | |
| 4437 | 4437 | /* set up adsp speedup handlers */ |
| 4438 | m_adsp->memory().space(AS_DATA)->install_legacy_read_handler(0x1fff, 0x1fff, FUNC(hdadsp_speedup_r)); | |
| 4439 | m_adsp->memory().space(AS_DATA)->install_legacy_read_handler(0x1f99, 0x1f99, FUNC(hdds3_speedup_r)); | |
| 4438 | m_adsp->space(AS_DATA)->install_legacy_read_handler(0x1fff, 0x1fff, FUNC(hdadsp_speedup_r)); | |
| 4439 | m_adsp->space(AS_DATA)->install_legacy_read_handler(0x1f99, 0x1f99, FUNC(hdds3_speedup_r)); | |
| 4440 | 4440 | m_ds3_speedup_addr = &m_adsp_data_memory[0x1f99]; |
| 4441 | 4441 | m_ds3_speedup_pc = 0xff; |
| 4442 | 4442 | m_ds3_transfer_pc = 0x43672; |
| r17798 | r17799 | |
| 4451 | 4451 | init_ds3(machine()); |
| 4452 | 4452 | init_dsk2(machine()); |
| 4453 | 4453 | |
| 4454 | m_maincpu-> | |
| 4454 | m_maincpu-> | |
| 4455 | 4455 | |
| 4456 | 4456 | /* synchronization */ |
| 4457 | m_rddsp32_sync[0] = m_dsp32->memory().space(AS_PROGRAM)->install_legacy_write_handler(0x21fe00, 0x21fe03, FUNC(rddsp32_sync0_w)); | |
| 4458 | m_rddsp32_sync[1] = m_dsp32->memory().space(AS_PROGRAM)->install_legacy_write_handler(0x21ff00, 0x21ff03, FUNC(rddsp32_sync1_w)); | |
| 4457 | m_rddsp32_sync[0] = m_dsp32->space(AS_PROGRAM)->install_legacy_write_handler(0x21fe00, 0x21fe03, FUNC(rddsp32_sync0_w)); | |
| 4458 | m_rddsp32_sync[1] = m_dsp32->space(AS_PROGRAM)->install_legacy_write_handler(0x21ff00, 0x21ff03, FUNC(rddsp32_sync1_w)); | |
| 4459 | 4459 | |
| 4460 | 4460 | /* set up protection hacks */ |
| 4461 | m_gsp_protection = m_gsp-> | |
| 4461 | m_gsp_protection = m_gsp-> | |
| 4462 | 4462 | |
| 4463 | 4463 | /* set up adsp speedup handlers */ |
| 4464 | m_adsp->memory().space(AS_DATA)->install_legacy_read_handler(0x1fff, 0x1fff, FUNC(hdadsp_speedup_r)); | |
| 4465 | m_adsp->memory().space(AS_DATA)->install_legacy_read_handler(0x1f99, 0x1f99, FUNC(hdds3_speedup_r)); | |
| 4464 | m_adsp->space(AS_DATA)->install_legacy_read_handler(0x1fff, 0x1fff, FUNC(hdadsp_speedup_r)); | |
| 4465 | m_adsp->space(AS_DATA)->install_legacy_read_handler(0x1f99, 0x1f99, FUNC(hdds3_speedup_r)); | |
| 4466 | 4466 | m_ds3_speedup_addr = &m_adsp_data_memory[0x1f99]; |
| 4467 | 4467 | m_ds3_speedup_pc = 0x2da; |
| 4468 | 4468 | m_ds3_transfer_pc = 0x407b8; |
| r17798 | r17799 | |
| 4477 | 4477 | init_ds3(machine()); |
| 4478 | 4478 | init_dsk2(machine()); |
| 4479 | 4479 | |
| 4480 | m_maincpu-> | |
| 4480 | m_maincpu-> | |
| 4481 | 4481 | |
| 4482 | 4482 | /* synchronization */ |
| 4483 | m_rddsp32_sync[0] = m_dsp32->memory().space(AS_PROGRAM)->install_legacy_write_handler(0x21fe00, 0x21fe03, FUNC(rddsp32_sync0_w)); | |
| 4484 | m_rddsp32_sync[1] = m_dsp32->memory().space(AS_PROGRAM)->install_legacy_write_handler(0x21ff00, 0x21ff03, FUNC(rddsp32_sync1_w)); | |
| 4483 | m_rddsp32_sync[0] = m_dsp32->space(AS_PROGRAM)->install_legacy_write_handler(0x21fe00, 0x21fe03, FUNC(rddsp32_sync0_w)); | |
| 4484 | m_rddsp32_sync[1] = m_dsp32->space(AS_PROGRAM)->install_legacy_write_handler(0x21ff00, 0x21ff03, FUNC(rddsp32_sync1_w)); | |
| 4485 | 4485 | |
| 4486 | 4486 | /* set up protection hacks */ |
| 4487 | m_gsp_protection = m_gsp-> | |
| 4487 | m_gsp_protection = m_gsp-> | |
| 4488 | 4488 | |
| 4489 | 4489 | /* set up adsp speedup handlers */ |
| 4490 | m_adsp->memory().space(AS_DATA)->install_legacy_read_handler(0x1fff, 0x1fff, FUNC(hdadsp_speedup_r)); | |
| 4491 | m_adsp->memory().space(AS_DATA)->install_legacy_read_handler(0x1f9a, 0x1f9a, FUNC(hdds3_speedup_r)); | |
| 4490 | m_adsp->space(AS_DATA)->install_legacy_read_handler(0x1fff, 0x1fff, FUNC(hdadsp_speedup_r)); | |
| 4491 | m_adsp->space(AS_DATA)->install_legacy_read_handler(0x1f9a, 0x1f9a, FUNC(hdds3_speedup_r)); | |
| 4492 | 4492 | m_ds3_speedup_addr = &m_adsp_data_memory[0x1f9a]; |
| 4493 | 4493 | m_ds3_speedup_pc = 0x2d9; |
| 4494 | 4494 | m_ds3_transfer_pc = 0X407da; |
| r17798 | r17799 | |
|---|---|---|
| 443 | 443 | DRIVER_INIT_MEMBER(gunbustr_state,gunbustr) |
| 444 | 444 | { |
| 445 | 445 | /* Speedup handler */ |
| 446 | m_maincpu-> | |
| 446 | m_maincpu-> | |
| 447 | 447 | } |
| 448 | 448 | |
| 449 | 449 | DRIVER_INIT_MEMBER(gunbustr_state,gunbustrj) |
| r17798 | r17799 | |
|---|---|---|
| 323 | 323 | |
| 324 | 324 | /* TODO: change this! */ |
| 325 | 325 | if(newval) |
| 326 | generic_pulse_irq_line(m_maincpu | |
| 326 | generic_pulse_irq_line(*m_maincpu | |
| 327 | 327 | } |
| 328 | 328 | |
| 329 | 329 | static INPUT_PORTS_START( pntnpuzl ) |
| r17798 | r17799 | |
|---|---|---|
| 389 | 389 | static MACHINE_RESET( superabc ) |
| 390 | 390 | { |
| 391 | 391 | pacman_state *state = machine.driver_data<pacman_state>(); |
| 392 | state->superabc_bank_w(*state->m_maincpu-> | |
| 392 | state->superabc_bank_w(*state->m_maincpu-> | |
| 393 | 393 | } |
| 394 | 394 | |
| 395 | 395 | |
| r17798 | r17799 | |
| 5745 | 5745 | static void maketrax_rom_decode(running_machine &machine) |
| 5746 | 5746 | { |
| 5747 | 5747 | pacman_state *state = machine.driver_data<pacman_state>(); |
| 5748 | address_space *space = state->m_maincpu-> | |
| 5748 | address_space *space = state->m_maincpu-> | |
| 5749 | 5749 | UINT8 *decrypted = auto_alloc_array(machine, UINT8, 0x4000); |
| 5750 | 5750 | UINT8 *rom = machine.root_device().memregion("maincpu")->base(); |
| 5751 | 5751 | |
| r17798 | r17799 | |
| 5769 | 5769 | DRIVER_INIT_MEMBER(pacman_state,maketrax) |
| 5770 | 5770 | { |
| 5771 | 5771 | /* set up protection handlers */ |
| 5772 | m_maincpu->memory().space(AS_PROGRAM)->install_read_handler(0x5080, 0x50bf, read8_delegate(FUNC(pacman_state::maketrax_special_port2_r),this)); | |
| 5773 | m_maincpu->memory().space(AS_PROGRAM)->install_read_handler(0x50c0, 0x50ff, read8_delegate(FUNC(pacman_state::maketrax_special_port3_r),this)); | |
| 5772 | m_maincpu->space(AS_PROGRAM)->install_read_handler(0x5080, 0x50bf, read8_delegate(FUNC(pacman_state::maketrax_special_port2_r),this)); | |
| 5773 | m_maincpu->space(AS_PROGRAM)->install_read_handler(0x50c0, 0x50ff, read8_delegate(FUNC(pacman_state::maketrax_special_port3_r),this)); | |
| 5774 | 5774 | |
| 5775 | 5775 | maketrax_rom_decode(machine()); |
| 5776 | 5776 | } |
| r17798 | r17799 | |
| 5778 | 5778 | static void korosuke_rom_decode(running_machine &machine) |
| 5779 | 5779 | { |
| 5780 | 5780 | pacman_state *state = machine.driver_data<pacman_state>(); |
| 5781 | address_space *space = state->m_maincpu-> | |
| 5781 | address_space *space = state->m_maincpu-> | |
| 5782 | 5782 | UINT8 *decrypted = auto_alloc_array(machine, UINT8, 0x4000); |
| 5783 | 5783 | UINT8 *rom = machine.root_device().memregion("maincpu")->base(); |
| 5784 | 5784 | |
| r17798 | r17799 | |
| 5802 | 5802 | DRIVER_INIT_MEMBER(pacman_state,korosuke) |
| 5803 | 5803 | { |
| 5804 | 5804 | /* set up protection handlers */ |
| 5805 | m_maincpu->memory().space(AS_PROGRAM)->install_read_handler(0x5080, 0x5080, read8_delegate(FUNC(pacman_state::korosuke_special_port2_r),this)); | |
| 5806 | m_maincpu->memory().space(AS_PROGRAM)->install_read_handler(0x50c0, 0x50ff, read8_delegate(FUNC(pacman_state::korosuke_special_port3_r),this)); | |
| 5805 | m_maincpu->space(AS_PROGRAM)->install_read_handler(0x5080, 0x5080, read8_delegate(FUNC(pacman_state::korosuke_special_port2_r),this)); | |
| 5806 | m_maincpu->space(AS_PROGRAM)->install_read_handler(0x50c0, 0x50ff, read8_delegate(FUNC(pacman_state::korosuke_special_port3_r),this)); | |
| 5807 | 5807 | |
| 5808 | 5808 | korosuke_rom_decode(machine()); |
| 5809 | 5809 | } |
| r17798 | r17799 | |
| 6105 | 6105 | DRIVER_INIT_MEMBER(pacman_state,mspacii) |
| 6106 | 6106 | { |
| 6107 | 6107 | // protection |
| 6108 | m_maincpu-> | |
| 6108 | m_maincpu-> | |
| 6109 | 6109 | } |
| 6110 | 6110 | |
| 6111 | 6111 | DRIVER_INIT_MEMBER(pacman_state,superabc) |
| r17798 | r17799 | |
| 6166 | 6166 | { |
| 6167 | 6167 | |
| 6168 | 6168 | /* extra memory */ |
| 6169 | m_maincpu-> | |
| 6169 | m_maincpu-> | |
| 6170 | 6170 | |
| 6171 | 6171 | /* protection? */ |
| 6172 | m_maincpu-> | |
| 6172 | m_maincpu-> | |
| 6173 | 6173 | } |
| 6174 | 6174 | |
| 6175 | 6175 |
| r17798 | r17799 | |
|---|---|---|
| 329 | 329 | static VIDEO_START( pc_cga ) |
| 330 | 330 | { |
| 331 | 331 | int buswidth; |
| 332 | address_space *space = machine.firstcpu->memory().space(AS_PROGRAM); | |
| 333 | address_space *spaceio = machine.firstcpu->memory().space(AS_IO); | |
| 332 | address_space *space = machine.firstcpu->space(AS_PROGRAM); | |
| 333 | address_space *spaceio = machine.firstcpu->space(AS_IO); | |
| 334 | 334 | |
| 335 | 335 | space->install_readwrite_bank(0xb8000, 0xbbfff, 0, 0x04000, "bank11" ); |
| 336 | buswidth = machine.firstcpu-> | |
| 336 | buswidth = machine.firstcpu-> | |
| 337 | 337 | UINT64 mask = 0; |
| 338 | 338 | switch(buswidth) |
| 339 | 339 | { |
| r17798 | r17799 | |
| 370 | 370 | static VIDEO_START( pc_cga32k ) |
| 371 | 371 | { |
| 372 | 372 | int buswidth; |
| 373 | address_space *space = machine.firstcpu->memory().space(AS_PROGRAM); | |
| 374 | address_space *spaceio = machine.firstcpu->memory().space(AS_IO); | |
| 373 | address_space *space = machine.firstcpu->space(AS_PROGRAM); | |
| 374 | address_space *spaceio = machine.firstcpu->space(AS_IO); | |
| 375 | 375 | |
| 376 | 376 | |
| 377 | 377 | space->install_readwrite_bank(0xb8000, 0xbffff, "bank11" ); |
| 378 | buswidth = machine.firstcpu-> | |
| 378 | buswidth = machine.firstcpu-> | |
| 379 | 379 | UINT64 mask = 0; |
| 380 | 380 | switch(buswidth) |
| 381 | 381 | { |
| r17798 | r17799 | |
| 1201 | 1201 | case 0x0f: |
| 1202 | 1202 | // Not sure if some all CGA cards have ability to upload char definition |
| 1203 | 1203 | // The original CGA card had a char rom |
| 1204 | UINT8 buswidth = space->machine().firstcpu->memory().space_config(AS_PROGRAM)->m_databus_width; | |
| 1205 | address_space *space_prg = space->machine().firstcpu->memory().space(AS_PROGRAM); | |
| 1204 | UINT8 buswidth = space->machine().firstcpu->space_config(AS_PROGRAM)->m_databus_width; | |
| 1205 | address_space *space_prg = space->machine().firstcpu->space(AS_PROGRAM); | |
| 1206 | 1206 | cga.p3df = data; |
| 1207 | 1207 | if (data & 1) { |
| 1208 | 1208 | UINT64 mask = 0; |
| r17798 | r17799 | |
| 1635 | 1635 | cga.videoram_size = 0x10000; |
| 1636 | 1636 | cga.videoram = auto_alloc_array(machine, UINT8, 0x10000 ); |
| 1637 | 1637 | |
| 1638 | address_space *space = machine.firstcpu->memory().space( AS_PROGRAM ); | |
| 1639 | address_space *io_space = machine.firstcpu->memory().space( AS_IO ); | |
| 1638 | address_space *space = machine.firstcpu->space( AS_PROGRAM ); | |
| 1639 | address_space *io_space = machine.firstcpu->space( AS_IO ); | |
| 1640 | 1640 | |
| 1641 | 1641 | space->install_read_bank( 0xb8000, 0xbbfff, 0, 0x0C000, "bank1" ); |
| 1642 | 1642 | machine.root_device().membank("bank1")->set_base(cga.videoram + videoram_offset[0]); |
| r17798 | r17799 | |
|---|---|---|
| 2015 | 2015 | int buswidth; |
| 2016 | 2016 | UINT64 mask = 0; |
| 2017 | 2017 | |
| 2018 | buswidth = machine.firstcpu-> | |
| 2018 | buswidth = machine.firstcpu-> | |
| 2019 | 2019 | switch(buswidth) |
| 2020 | 2020 | { |
| 2021 | 2021 | case 8: |
| r17798 | r17799 | |
| 2440 | 2440 | int buswidth; |
| 2441 | 2441 | UINT64 mask = 0; |
| 2442 | 2442 | |
| 2443 | buswidth = machine.firstcpu-> | |
| 2443 | buswidth = machine.firstcpu-> | |
| 2444 | 2444 | switch(buswidth) |
| 2445 | 2445 | { |
| 2446 | 2446 | case 8: |
| r17798 | r17799 | |
| 4461 | 4461 | int buswidth; |
| 4462 | 4462 | UINT64 mask = 0; |
| 4463 | 4463 | |
| 4464 | buswidth = machine.firstcpu-> | |
| 4464 | buswidth = machine.firstcpu-> | |
| 4465 | 4465 | switch(buswidth) |
| 4466 | 4466 | { |
| 4467 | 4467 | case 8: |
| r17798 | r17799 | |
|---|---|---|
| 233 | 233 | } |
| 234 | 234 | |
| 235 | 235 | |
| 236 | //------------------------------------------------- | |
| 237 | // device_state - return a pointer to the device | |
| 238 | // state interface for this device | |
| 239 | //------------------------------------------------- | |
| 240 | ||
| 241 | inline device_state_interface *device_state(device_t *device) | |
| 242 | { | |
| 243 | device_state_interface *intf; | |
| 244 | if (!device->interface(intf)) | |
| 245 | throw emu_fatalerror("Device '%s' does not have state interface", device->tag()); | |
| 246 | return intf; | |
| 247 | } | |
| 248 | ||
| 249 | ||
| 250 | 236 | #endif /* __DISTATE_H__ */ |
| r17798 | r17799 | |
|---|---|---|
| 702 | 702 | static void SCSP_UpdateReg(scsp_state *scsp, int reg) |
| 703 | 703 | { |
| 704 | 704 | /* temporary hack until this is converted to a device */ |
| 705 | address_space *space = scsp->device->machine().firstcpu-> | |
| 705 | address_space *space = scsp->device->machine().firstcpu-> | |
| 706 | 706 | |
| 707 | 707 | switch(reg&0x3f) |
| 708 | 708 | { |
| r17798 | r17799 | |
| 1325 | 1325 | case 0x416: |
| 1326 | 1326 | COMBINE_DATA(&scsp->dma_regs[((offset-0x412)/2) & 3]); |
| 1327 | 1327 | if(ACCESSING_BITS_8_15 && offset*2 == 0x416) |
| 1328 | dma_scsp(device->machine().firstcpu-> | |
| 1328 | dma_scsp(device->machine().firstcpu-> | |
| 1329 | 1329 | break; |
| 1330 | 1330 | case 0x42a: //check main cpu IRQ |
| 1331 | 1331 | scsp->main_irq(1); |
| r17798 | r17799 | |
|---|---|---|
| 82 | 82 | if (latch8->has_read) |
| 83 | 83 | { |
| 84 | 84 | /* temporary hack until all relevant systems are devices */ |
| 85 | address_space *space = device->machine().firstcpu-> | |
| 85 | address_space *space = device->machine().firstcpu-> | |
| 86 | 86 | int i; |
| 87 | 87 | for (i=0; i<8; i++) |
| 88 | 88 | { |
| r17798 | r17799 | |
|---|---|---|
| 220 | 220 | // required operation overrides |
| 221 | 221 | void run() { execute_run(); } |
| 222 | 222 | |
| 223 | // deliberately ambiguous functions; if you have the execute interface | |
| 224 | // just use it | |
| 225 | device_execute_interface &execute() { return *this; } | |
| 226 | ||
| 223 | 227 | protected: |
| 224 | 228 | // internal helpers |
| 225 | 229 | void run_thread_wrapper(); |
| r17798 | r17799 | |
|---|---|---|
| 123 | 123 | bool write(address_spacenum spacenum, offs_t offset, int size, UINT64 value) { return memory_write(spacenum, offset, size, value); } |
| 124 | 124 | bool readop(offs_t offset, int size, UINT64 &value) { return memory_readop(offset, size, value); } |
| 125 | 125 | |
| 126 | // deliberately ambiguous functions; if you have the memory interface | |
| 127 | // just use it | |
| 128 | device_memory_interface &memory() { return *this; } | |
| 129 | ||
| 126 | 130 | protected: |
| 127 | 131 | // required overrides |
| 128 | 132 | virtual const address_space_config *memory_space_config(address_spacenum spacenum) const = 0; |
| r17798 | r17799 | |
|---|---|---|
| 222 | 222 | |
| 223 | 223 | WRITE8_MEMBER( mbee_state::mbee_04_w ) // address |
| 224 | 224 | { |
| 225 | address_space *mem = m_maincpu-> | |
| 225 | address_space *mem = m_maincpu-> | |
| 226 | 226 | machine().device<mc146818_device>("rtc")->write(*mem, 0, data); |
| 227 | 227 | } |
| 228 | 228 | |
| 229 | 229 | WRITE8_MEMBER( mbee_state::mbee_06_w ) // write |
| 230 | 230 | { |
| 231 | address_space *mem = m_maincpu-> | |
| 231 | address_space *mem = m_maincpu-> | |
| 232 | 232 | machine().device<mc146818_device>("rtc")->write(*mem, 1, data); |
| 233 | 233 | } |
| 234 | 234 | |
| 235 | 235 | READ8_MEMBER( mbee_state::mbee_07_r ) // read |
| 236 | 236 | { |
| 237 | address_space *mem = m_maincpu-> | |
| 237 | address_space *mem = m_maincpu-> | |
| 238 | 238 | return machine().device<mc146818_device>("rtc")->read(*mem, 1); |
| 239 | 239 | } |
| 240 | 240 | |
| r17798 | r17799 | |
| 263 | 263 | |
| 264 | 264 | WRITE8_MEMBER( mbee_state::mbee256_50_w ) |
| 265 | 265 | { |
| 266 | address_space *mem = m_maincpu-> | |
| 266 | address_space *mem = m_maincpu-> | |
| 267 | 267 | |
| 268 | 268 | // primary low banks |
| 269 | 269 | membank("boot")->set_entry((data & 3) | ((data & 0x20) >> 3)); |
| r17798 | r17799 | |
| 345 | 345 | |
| 346 | 346 | WRITE8_MEMBER( mbee_state::mbee128_50_w ) |
| 347 | 347 | { |
| 348 | address_space *mem = m_maincpu-> | |
| 348 | address_space *mem = m_maincpu-> | |
| 349 | 349 | |
| 350 | 350 | // primary low banks |
| 351 | 351 | membank("boot")->set_entry((data & 3)); |
| r17798 | r17799 | |
|---|---|---|
| 216 | 216 | d0 Select bit 0 */ |
| 217 | 217 | |
| 218 | 218 | /* get address space instead of io space */ |
| 219 | address_space *mem = m_maincpu-> | |
| 219 | address_space *mem = m_maincpu-> | |
| 220 | 220 | UINT8 *base = memregion("maincpu")->base(); |
| 221 | 221 | |
| 222 | 222 | m_mode = (m_mode & 0x73) | (data & 0x8c); |
| r17798 | r17799 | |
| 561 | 561 | d0 inverse video (entire screen) */ |
| 562 | 562 | |
| 563 | 563 | /* get address space instead of io space */ |
| 564 | address_space *mem = m_maincpu-> | |
| 564 | address_space *mem = m_maincpu-> | |
| 565 | 565 | |
| 566 | 566 | m_mode = (m_mode & 0x87) | ((data & 0x0f) << 3); |
| 567 | 567 | |
| r17798 | r17799 | |
| 867 | 867 | MACHINE_RESET( trs80m4 ) |
| 868 | 868 | { |
| 869 | 869 | trs80_state *state = machine.driver_data<trs80_state>(); |
| 870 | address_space *mem = state->m_maincpu-> | |
| 870 | address_space *mem = state->m_maincpu-> | |
| 871 | 871 | state->m_cassette_data = 0; |
| 872 | 872 | |
| 873 | 873 | mem->install_read_bank (0x0000, 0x0fff, "bank1"); |
| r17798 | r17799 | |
| 896 | 896 | MACHINE_RESET( lnw80 ) |
| 897 | 897 | { |
| 898 | 898 | trs80_state *state = machine.driver_data<trs80_state>(); |
| 899 | address_space *space = state->m_maincpu-> | |
| 899 | address_space *space = state->m_maincpu-> | |
| 900 | 900 | state->m_cassette_data = 0; |
| 901 | 901 | state->m_reg_load = 1; |
| 902 | 902 | state->lnw80_fe_w(*space, 0, 0); |
| r17798 | r17799 | |
|---|---|---|
| 357 | 357 | |
| 358 | 358 | WRITE8_MEMBER( wswan_state::wswan_port_w ) |
| 359 | 359 | { |
| 360 | address_space *mem = m_maincpu-> | |
| 360 | address_space *mem = m_maincpu-> | |
| 361 | 361 | wswan_state *state = machine().driver_data<wswan_state>(); |
| 362 | 362 | UINT8 input; |
| 363 | 363 | logerror( "PC=%X: port write %02X <- %02X\n", mem->device().safe_pc(), offset, data ); |
| r17798 | r17799 | |
|---|---|---|
| 42 | 42 | d0 drive A */ |
| 43 | 43 | |
| 44 | 44 | /* get address space */ |
| 45 | address_space *mem = m_maincpu-> | |
| 45 | address_space *mem = m_maincpu-> | |
| 46 | 46 | |
| 47 | 47 | if (data & 0x80) |
| 48 | 48 | { |
| r17798 | r17799 | |
| 329 | 329 | MACHINE_RESET( kaypro2x ) |
| 330 | 330 | { |
| 331 | 331 | kaypro_state *state = machine.driver_data<kaypro_state>(); |
| 332 | address_space *space = state->m_maincpu-> | |
| 332 | address_space *space = state->m_maincpu-> | |
| 333 | 333 | state->kaypro2x_system_port_w(*space, 0, 0x80); |
| 334 | 334 | MACHINE_RESET_CALL(kay_kbd); |
| 335 | 335 | } |
| r17798 | r17799 | |
| 348 | 348 | QUICKLOAD_LOAD( kayproii ) |
| 349 | 349 | { |
| 350 | 350 | kaypro_state *state = image.device().machine().driver_data<kaypro_state>(); |
| 351 | address_space *space = state->m_maincpu-> | |
| 351 | address_space *space = state->m_maincpu-> | |
| 352 | 352 | UINT8 *RAM = state->memregion("rambank")->base(); |
| 353 | 353 | UINT16 i; |
| 354 | 354 | UINT8 data; |
| r17798 | r17799 | |
| 371 | 371 | QUICKLOAD_LOAD( kaypro2x ) |
| 372 | 372 | { |
| 373 | 373 | kaypro_state *state = image.device().machine().driver_data<kaypro_state>(); |
| 374 | address_space *space = state->m_maincpu-> | |
| 374 | address_space *space = state->m_maincpu-> | |
| 375 | 375 | UINT8 *RAM = state->memregion("rambank")->base(); |
| 376 | 376 | UINT16 i; |
| 377 | 377 | UINT8 data; |
| r17798 | r17799 | |
|---|---|---|
| 1260 | 1260 | ***************************************************************************/ |
| 1261 | 1261 | |
| 1262 | 1262 | #define install_write_handler(_start, _end, _handler) \ |
| 1263 | image.device().machine().firstcpu-> | |
| 1263 | image.device().machine().firstcpu-> | |
| 1264 | 1264 | |
| 1265 | 1265 | #define install_io1_handler(_handler) \ |
| 1266 | image.device().machine().firstcpu-> | |
| 1266 | image.device().machine().firstcpu-> | |
| 1267 | 1267 | |
| 1268 | 1268 | #define install_io2_handler(_handler) \ |
| 1269 | image.device().machine().firstcpu-> | |
| 1269 | image.device().machine().firstcpu-> | |
| 1270 | 1270 | |
| 1271 | 1271 | #define allocate_cartridge_timer(_period, _func) \ |
| 1272 | 1272 | legacy_c64_state *state = image.device().machine().driver_data<legacy_c64_state>(); \ |
| r17798 | r17799 | |
| 1577 | 1577 | |
| 1578 | 1578 | map_cartridge_roml(image.device().machine(), 0x0000); |
| 1579 | 1579 | |
| 1580 | address_space *space = image.device().machine().firstcpu-> | |
| 1580 | address_space *space = image.device().machine().firstcpu-> | |
| 1581 | 1581 | space->install_legacy_read_handler(0xdf00, 0xdfff, FUNC(super_explode_r)); |
| 1582 | 1582 | |
| 1583 | 1583 | install_io2_handler(super_explode_bank_w); |
| r17798 | r17799 | |
|---|---|---|
| 239 | 239 | |
| 240 | 240 | static void dma_transfer_start(device_t* device, int channel, int dir) |
| 241 | 241 | { |
| 242 | address_space *space = device->machine().firstcpu-> | |
| 242 | address_space *space = device->machine().firstcpu-> | |
| 243 | 243 | hd63450_t* dmac = get_safe_token(device); |
| 244 | 244 | dmac->in_progress[channel] = 1; |
| 245 | 245 | dmac->reg[channel].csr &= ~0xe0; |
| r17798 | r17799 | |
| 316 | 316 | |
| 317 | 317 | void hd63450_single_transfer(device_t* device, int x) |
| 318 | 318 | { |
| 319 | address_space *space = device->machine().firstcpu-> | |
| 319 | address_space *space = device->machine().firstcpu-> | |
| 320 | 320 | int data; |
| 321 | 321 | int datasize = 1; |
| 322 | 322 | hd63450_t* dmac = get_safe_token(device); |
| r17798 | r17799 | |
|---|---|---|
| 1409 | 1409 | |
| 1410 | 1410 | DRIVER_INIT_MEMBER(pc_state,pc1640) |
| 1411 | 1411 | { |
| 1412 | address_space *io_space = machine().firstcpu-> | |
| 1412 | address_space *io_space = machine().firstcpu-> | |
| 1413 | 1413 | |
| 1414 | 1414 | io_space->install_legacy_read_handler(0x278, 0x27b, FUNC(pc1640_port278_r), 0xffff); |
| 1415 | 1415 | io_space->install_legacy_read_handler(0x4278, 0x427b, FUNC(pc1640_port4278_r), 0xffff); |
| r17798 | r17799 | |
|---|---|---|
| 251 | 251 | |
| 252 | 252 | UINT8 comx_clm_device::comx_mrd_r(offs_t offset, int *extrom) |
| 253 | 253 | { |
| 254 | address_space *space = machine().firstcpu-> | |
| 254 | address_space *space = machine().firstcpu-> | |
| 255 | 255 | |
| 256 | 256 | UINT8 data = 0xff; |
| 257 | 257 | |
| r17798 | r17799 | |
| 278 | 278 | |
| 279 | 279 | void comx_clm_device::comx_mwr_w(offs_t offset, UINT8 data) |
| 280 | 280 | { |
| 281 | address_space *space = machine().firstcpu-> | |
| 281 | address_space *space = machine().firstcpu-> | |
| 282 | 282 | |
| 283 | 283 | if (offset >= 0xd000 && offset < 0xd800) |
| 284 | 284 | { |
| r17798 | r17799 | |
|---|---|---|
| 30 | 30 | /* configure EA banking */ |
| 31 | 31 | membank("bank1")->configure_entry(0, memregion("bios")->base()); |
| 32 | 32 | membank("bank1")->configure_entry(1, memregion(I8048_TAG)->base()); |
| 33 | m_maincpu-> | |
| 33 | m_maincpu-> | |
| 34 | 34 | membank("bank1")->set_entry(0); |
| 35 | 35 | |
| 36 | 36 | /* allocate external RAM */ |
| r17798 | r17799 | |
|---|---|---|
| 452 | 452 | |
| 453 | 453 | if ((!m_game && m_exrom) || (charen && (loram || hiram))) |
| 454 | 454 | { |
| 455 | m_subcpu-> | |
| 455 | m_subcpu-> | |
| 456 | 456 | m_write_io = 1; |
| 457 | 457 | } |
| 458 | 458 | else |
| 459 | 459 | { |
| 460 | m_subcpu-> | |
| 460 | m_subcpu-> | |
| 461 | 461 | m_write_io = 0; |
| 462 | 462 | if ((!charen && (loram || hiram))) |
| 463 | 463 | membank("bank13")->set_base(m_chargen); |
| r17798 | r17799 | |
| 636 | 636 | else |
| 637 | 637 | m_ram_top = 0x10000; |
| 638 | 638 | |
| 639 | m_subcpu-> | |
| 639 | m_subcpu-> | |
| 640 | 640 | |
| 641 | 641 | if (MMU_IO_ON) |
| 642 | 642 | { |
| 643 | 643 | m_write_io = 1; |
| 644 | m_subcpu-> | |
| 644 | m_subcpu-> | |
| 645 | 645 | } |
| 646 | 646 | else |
| 647 | 647 | { |
| 648 | 648 | m_write_io = 0; |
| 649 | m_subcpu-> | |
| 649 | m_subcpu-> | |
| 650 | 650 | } |
| 651 | 651 | |
| 652 | 652 | |
| r17798 | r17799 | |
| 1025 | 1025 | |
| 1026 | 1026 | bankswitch_64(0); |
| 1027 | 1027 | |
| 1028 | m_memory[0x000] = m_subcpu->memory().space(AS_PROGRAM)->read_byte(0); | |
| 1029 | m_memory[0x001] = m_subcpu->memory().space(AS_PROGRAM)->read_byte(1); | |
| 1028 | m_memory[0x000] = m_subcpu->space(AS_PROGRAM)->read_byte(0); | |
| 1029 | m_memory[0x001] = m_subcpu->space(AS_PROGRAM)->read_byte(1); | |
| 1030 | 1030 | } |
| 1031 | 1031 | |
| 1032 | 1032 | READ8_MEMBER( c128_state::cpu_r) |
| r17798 | r17799 | |
|---|---|---|
| 570 | 570 | |
| 571 | 571 | void ibm5160_mb_device::install_device(device_t *dev, offs_t start, offs_t end, offs_t mask, offs_t mirror, read8_device_func rhandler, const char* rhandler_name, write8_device_func whandler, const char *whandler_name) |
| 572 | 572 | { |
| 573 | int buswidth = machine().firstcpu-> | |
| 573 | int buswidth = machine().firstcpu-> | |
| 574 | 574 | switch(buswidth) |
| 575 | 575 | { |
| 576 | 576 | case 8: |
| 577 | m_maincpu-> | |
| 577 | m_maincpu-> | |
| 578 | 578 | break; |
| 579 | 579 | case 16: |
| 580 | m_maincpu-> | |
| 580 | m_maincpu-> | |
| 581 | 581 | break; |
| 582 | 582 | default: |
| 583 | 583 | fatalerror("IBM5160_MOTHERBOARD: Bus width %d not supported\n", buswidth); |
| r17798 | r17799 | |
| 587 | 587 | |
| 588 | 588 | void ibm5160_mb_device::install_device_write(device_t *dev, offs_t start, offs_t end, offs_t mask, offs_t mirror, write8_device_func whandler, const char *whandler_name) |
| 589 | 589 | { |
| 590 | int buswidth = machine().firstcpu-> | |
| 590 | int buswidth = machine().firstcpu-> | |
| 591 | 591 | switch(buswidth) |
| 592 | 592 | { |
| 593 | 593 | case 8: |
| 594 | m_maincpu-> | |
| 594 | m_maincpu-> | |
| 595 | 595 | break; |
| 596 | 596 | case 16: |
| 597 | m_maincpu-> | |
| 597 | m_maincpu-> | |
| 598 | 598 | break; |
| 599 | 599 | default: |
| 600 | 600 | fatalerror("IBM5160_MOTHERBOARD: Bus width %d not supported\n", buswidth); |
| r17798 | r17799 | |
| 604 | 604 | |
| 605 | 605 | void ibm5160_mb_device::install_device(offs_t start, offs_t end, offs_t mask, offs_t mirror, read8_delegate rhandler, write8_delegate whandler) |
| 606 | 606 | { |
| 607 | int buswidth = m_maincpu-> | |
| 607 | int buswidth = m_maincpu-> | |
| 608 | 608 | switch(buswidth) |
| 609 | 609 | { |
| 610 | 610 | case 8: |
| 611 | m_maincpu-> | |
| 611 | m_maincpu-> | |
| 612 | 612 | break; |
| 613 | 613 | case 16: |
| 614 | m_maincpu-> | |
| 614 | m_maincpu-> | |
| 615 | 615 | break; |
| 616 | 616 | default: |
| 617 | 617 | fatalerror("IBM5160_MOTHERBOARD: Bus width %d not supported\n", buswidth); |
| r17798 | r17799 | |
| 631 | 631 | install_device(m_pit8253, 0x0040, 0x0043, 0, 0, FUNC(pit8253_r), FUNC(pit8253_w) ); |
| 632 | 632 | |
| 633 | 633 | // install_device(m_ppi8255, 0x0060, 0x0063, 0, 0, FUNC(i8255a_r), FUNC(i8255a_w) ); |
| 634 | int buswidth = machine().firstcpu-> | |
| 634 | int buswidth = machine().firstcpu-> | |
| 635 | 635 | switch(buswidth) |
| 636 | 636 | { |
| 637 | 637 | case 8: |
| 638 | m_maincpu-> | |
| 638 | m_maincpu-> | |
| 639 | 639 | break; |
| 640 | 640 | case 16: |
| 641 | m_maincpu-> | |
| 641 | m_maincpu-> | |
| 642 | 642 | break; |
| 643 | 643 | default: |
| 644 | 644 | fatalerror("IBM5160_MOTHERBOARD: Bus width %d not supported\n", buswidth); |
| r17798 | r17799 | |
|---|---|---|
| 361 | 361 | |
| 362 | 362 | UINT16 endmem = 0xbfff; |
| 363 | 363 | |
| 364 | address_space *space = state->m_maincpu-> | |
| 364 | address_space *space = state->m_maincpu-> | |
| 365 | 365 | /* configure RAM */ |
| 366 | 366 | switch (state->m_ram->size()) |
| 367 | 367 | { |
| r17798 | r17799 | |
| 389 | 389 | |
| 390 | 390 | UINT16 endmem = 0xbbff; |
| 391 | 391 | |
| 392 | address_space *space = state->m_maincpu-> | |
| 392 | address_space *space = state->m_maincpu-> | |
| 393 | 393 | /* configure RAM */ |
| 394 | 394 | switch (state->m_ram->size()) |
| 395 | 395 | { |
| r17798 | r17799 | |
|---|---|---|
| 1197 | 1197 | } |
| 1198 | 1198 | else // CPC+/GX4000 |
| 1199 | 1199 | { |
| 1200 | //address_space *space = state->m_maincpu-> | |
| 1200 | //address_space *space = state->m_maincpu-> | |
| 1201 | 1201 | |
| 1202 | 1202 | /* if ( state->m_asic.enabled && ( state->m_asic.rmr2 & 0x18 ) == 0x18 ) |
| 1203 | 1203 | { |
| r17798 | r17799 | |
| 2176 | 2176 | static void amstrad_handle_snapshot(running_machine &machine, unsigned char *pSnapshot) |
| 2177 | 2177 | { |
| 2178 | 2178 | amstrad_state *state = machine.driver_data<amstrad_state>(); |
| 2179 | address_space* space = state->m_maincpu-> | |
| 2179 | address_space* space = state->m_maincpu-> | |
| 2180 | 2180 | mc6845_device *mc6845 = state->m_crtc; |
| 2181 | 2181 | device_t *ay8910 = state->m_ay; |
| 2182 | 2182 | int RegData; |
| r17798 | r17799 | |
| 2459 | 2459 | static void update_psg(running_machine &machine) |
| 2460 | 2460 | { |
| 2461 | 2461 | amstrad_state *state = machine.driver_data<amstrad_state>(); |
| 2462 | address_space *space = state->m_maincpu-> | |
| 2462 | address_space *space = state->m_maincpu-> | |
| 2463 | 2463 | device_t *ay8910 = state->m_ay; |
| 2464 | 2464 | mc146818_device *rtc = state->m_rtc; |
| 2465 | 2465 | |
| r17798 | r17799 | |
| 2833 | 2833 | static void amstrad_common_init(running_machine &machine) |
| 2834 | 2834 | { |
| 2835 | 2835 | amstrad_state *state = machine.driver_data<amstrad_state>(); |
| 2836 | address_space *space = state->m_maincpu-> | |
| 2836 | address_space *space = state->m_maincpu-> | |
| 2837 | 2837 | device_t* romexp; |
| 2838 | 2838 | rom_image_device* romimage; |
| 2839 | 2839 | char str[20]; |
| r17798 | r17799 | |
| 2982 | 2982 | MACHINE_RESET( plus ) |
| 2983 | 2983 | { |
| 2984 | 2984 | amstrad_state *state = machine.driver_data<amstrad_state>(); |
| 2985 | address_space *space = state->m_maincpu-> | |
| 2985 | address_space *space = state->m_maincpu-> | |
| 2986 | 2986 | int i; |
| 2987 | 2987 | UINT8 *rom = state->memregion("maincpu")->base(); |
| 2988 | 2988 | |
| r17798 | r17799 | |
| 3034 | 3034 | MACHINE_RESET( gx4000 ) |
| 3035 | 3035 | { |
| 3036 | 3036 | amstrad_state *state = machine.driver_data<amstrad_state>(); |
| 3037 | address_space *space = state->m_maincpu-> | |
| 3037 | address_space *space = state->m_maincpu-> | |
| 3038 | 3038 | int i; |
| 3039 | 3039 | UINT8 *rom = state->memregion("maincpu")->base(); |
| 3040 | 3040 |
| r17798 | r17799 | |
|---|---|---|
| 336 | 336 | if (data & 0x02) |
| 337 | 337 | { |
| 338 | 338 | for (int i=0; i<0xfc00; i++) |
| 339 | m_cpu-> | |
| 339 | m_cpu-> | |
| 340 | 340 | |
| 341 | 341 | device_set_input_line(m_cpu, INPUT_LINE_RESET, ASSERT_LINE); |
| 342 | 342 | } |
| r17798 | r17799 | |
|---|---|---|
| 60 | 60 | static void update_ti83p_memory (running_machine &machine) |
| 61 | 61 | { |
| 62 | 62 | ti85_state *state = machine.driver_data<ti85_state>(); |
| 63 | address_space *space = state->m_maincpu-> | |
| 63 | address_space *space = state->m_maincpu-> | |
| 64 | 64 | |
| 65 | 65 | if (state->m_ti8x_memory_page_1 & 0x40) |
| 66 | 66 | { |
| r17798 | r17799 | |
| 84 | 84 | static void update_ti86_memory (running_machine &machine) |
| 85 | 85 | { |
| 86 | 86 | ti85_state *state = machine.driver_data<ti85_state>(); |
| 87 | address_space *space = state->m_maincpu-> | |
| 87 | address_space *space = state->m_maincpu-> | |
| 88 | 88 | |
| 89 | 89 | if (state->m_ti8x_memory_page_1 & 0x40) |
| 90 | 90 | { |
| r17798 | r17799 | |
| 113 | 113 | MACHINE_START( ti81 ) |
| 114 | 114 | { |
| 115 | 115 | ti85_state *state = machine.driver_data<ti85_state>(); |
| 116 | address_space *space = state->m_maincpu-> | |
| 116 | address_space *space = state->m_maincpu-> | |
| 117 | 117 | state->m_bios = state->memregion("bios")->base(); |
| 118 | 118 | |
| 119 | 119 | state->m_timer_interrupt_mask = 0; |
| r17798 | r17799 | |
| 152 | 152 | MACHINE_START( ti83p ) |
| 153 | 153 | { |
| 154 | 154 | ti85_state *state = machine.driver_data<ti85_state>(); |
| 155 | address_space *space = state->m_maincpu-> | |
| 155 | address_space *space = state->m_maincpu-> | |
| 156 | 156 | state->m_bios = state->memregion("bios")->base(); |
| 157 | 157 | |
| 158 | 158 | state->m_timer_interrupt_mask = 0; |
| r17798 | r17799 | |
| 191 | 191 | MACHINE_START( ti86 ) |
| 192 | 192 | { |
| 193 | 193 | ti85_state *state = machine.driver_data<ti85_state>(); |
| 194 | address_space *space = state->m_maincpu-> | |
| 194 | address_space *space = state->m_maincpu-> | |
| 195 | 195 | state->m_bios = state->memregion("bios")->base(); |
| 196 | 196 | |
| 197 | 197 | state->m_timer_interrupt_mask = 0; |
| r17798 | r17799 | |
| 612 | 612 | static void ti85_setup_snapshot (running_machine &machine, UINT8 * data) |
| 613 | 613 | { |
| 614 | 614 | ti85_state *state = machine.driver_data<ti85_state>(); |
| 615 | address_space *space = state->m_maincpu-> | |
| 615 | address_space *space = state->m_maincpu-> | |
| 616 | 616 | int i; |
| 617 | 617 | unsigned char lo,hi; |
| 618 | 618 | unsigned char * hdw = data + 0x8000 + 0x94; |
| r17798 | r17799 | |
|---|---|---|
| 1054 | 1054 | |
| 1055 | 1055 | WRITE16_MEMBER( compis_state::compis_i186_internal_port_w ) |
| 1056 | 1056 | { |
| 1057 | address_space *mem = m_maincpu->memory().space(AS_PROGRAM); | |
| 1058 | address_space *io = m_maincpu->memory().space(AS_IO); | |
| 1057 | address_space *mem = m_maincpu->space(AS_PROGRAM); | |
| 1058 | address_space *io = m_maincpu->space(AS_IO); | |
| 1059 | 1059 | int temp, which, data16 = data; |
| 1060 | 1060 | |
| 1061 | 1061 | switch (offset) |
| r17798 | r17799 | |
|---|---|---|
| 1814 | 1814 | |
| 1815 | 1815 | if (m_model >= MODEL_MAC_POWERMAC_6100 && m_model <= MODEL_MAC_POWERMAC_8100) |
| 1816 | 1816 | { |
| 1817 | m_awacs->set_dma_base(m_maincpu-> | |
| 1817 | m_awacs->set_dma_base(m_maincpu-> | |
| 1818 | 1818 | } |
| 1819 | 1819 | |
| 1820 | 1820 | // start 60.15 Hz timer for most systems |
| r17798 | r17799 | |
|---|---|---|
| 137 | 137 | |
| 138 | 138 | void special_state::specimx_set_bank(offs_t i, UINT8 data) |
| 139 | 139 | { |
| 140 | address_space *space = m_maincpu-> | |
| 140 | address_space *space = m_maincpu-> | |
| 141 | 141 | UINT8 *ram = m_ram->pointer(); |
| 142 | 142 | |
| 143 | 143 | space->install_write_bank(0xc000, 0xffbf, "bank3"); |
| r17798 | r17799 | |
| 276 | 276 | UINT8 bank4 = (m_RR_register >> 6) & 3; |
| 277 | 277 | UINT8 *mem = memregion("maincpu")->base(); |
| 278 | 278 | UINT8 *ram = m_ram->pointer(); |
| 279 | address_space *space = m_maincpu-> | |
| 279 | address_space *space = m_maincpu-> | |
| 280 | 280 | |
| 281 | 281 | space->install_write_bank(0x0000, 0x3fff, "bank1"); |
| 282 | 282 | space->install_write_bank(0x4000, 0x8fff, "bank2"); |
| r17798 | r17799 | |
|---|---|---|
| 61 | 61 | datasize = image.length() - 128; |
| 62 | 62 | } |
| 63 | 63 | |
| 64 | address_space *space = state->m_maincpu-> | |
| 64 | address_space *space = state->m_maincpu-> | |
| 65 | 65 | |
| 66 | 66 | for (i=0; i<datasize; i++) |
| 67 | 67 | space->write_byte((addr+i) & 0xffff, data[i+128]); |
| r17798 | r17799 | |
| 290 | 290 | /* update status of memory area 0x0000-0x03fff */ |
| 291 | 291 | void kc_state::update_0x00000() |
| 292 | 292 | { |
| 293 | address_space *space = m_maincpu-> | |
| 293 | address_space *space = m_maincpu-> | |
| 294 | 294 | |
| 295 | 295 | /* access ram? */ |
| 296 | 296 | if (m_pio_data[0] & (1<<1)) |
| r17798 | r17799 | |
| 330 | 330 | /* update status of memory area 0x4000-0x07fff */ |
| 331 | 331 | void kc_state::update_0x04000() |
| 332 | 332 | { |
| 333 | address_space *space = m_maincpu-> | |
| 333 | address_space *space = m_maincpu-> | |
| 334 | 334 | |
| 335 | 335 | LOG(("Module at 0x4000\n")); |
| 336 | 336 | |
| r17798 | r17799 | |
| 343 | 343 | /* update memory address 0x0c000-0x0e000 */ |
| 344 | 344 | void kc_state::update_0x0c000() |
| 345 | 345 | { |
| 346 | address_space *space = m_maincpu-> | |
| 346 | address_space *space = m_maincpu-> | |
| 347 | 347 | |
| 348 | 348 | if ((m_pio_data[0] & (1<<7)) && memregion("basic")->base() != NULL) |
| 349 | 349 | { |
| r17798 | r17799 | |
| 366 | 366 | /* update memory address 0x0e000-0x0ffff */ |
| 367 | 367 | void kc_state::update_0x0e000() |
| 368 | 368 | { |
| 369 | address_space *space = m_maincpu-> | |
| 369 | address_space *space = m_maincpu-> | |
| 370 | 370 | |
| 371 | 371 | if (m_pio_data[0] & (1<<0)) |
| 372 | 372 | { |
| r17798 | r17799 | |
| 390 | 390 | /* update status of memory area 0x08000-0x0ffff */ |
| 391 | 391 | void kc_state::update_0x08000() |
| 392 | 392 | { |
| 393 | address_space *space = m_maincpu-> | |
| 393 | address_space *space = m_maincpu-> | |
| 394 | 394 | |
| 395 | 395 | if (m_pio_data[0] & (1<<2)) |
| 396 | 396 | { |
| r17798 | r17799 | |
| 413 | 413 | /* update status of memory area 0x4000-0x07fff */ |
| 414 | 414 | void kc85_4_state::update_0x04000() |
| 415 | 415 | { |
| 416 | address_space *space = m_maincpu-> | |
| 416 | address_space *space = m_maincpu-> | |
| 417 | 417 | |
| 418 | 418 | /* access ram? */ |
| 419 | 419 | if (m_port_86_data & (1<<0)) |
| r17798 | r17799 | |
| 455 | 455 | /* update memory address 0x0c000-0x0e000 */ |
| 456 | 456 | void kc85_4_state::update_0x0c000() |
| 457 | 457 | { |
| 458 | address_space *space = m_maincpu-> | |
| 458 | address_space *space = m_maincpu-> | |
| 459 | 459 | |
| 460 | 460 | if (m_port_86_data & (1<<7)) |
| 461 | 461 | { |
| r17798 | r17799 | |
| 491 | 491 | |
| 492 | 492 | void kc85_4_state::update_0x08000() |
| 493 | 493 | { |
| 494 | address_space *space = m_maincpu-> | |
| 494 | address_space *space = m_maincpu-> | |
| 495 | 495 | |
| 496 | 496 | if (m_pio_data[0] & (1<<2)) |
| 497 | 497 | { |
| r17798 | r17799 | |
|---|---|---|
| 1595 | 1595 | // TODO: This should be moved to card implementations that actually had this feature |
| 1596 | 1596 | m_p3df = data; |
| 1597 | 1597 | if (data & 1) { |
| 1598 | address_space *space_prg = machine().firstcpu-> | |
| 1598 | address_space *space_prg = machine().firstcpu-> | |
| 1599 | 1599 | |
| 1600 | 1600 | space_prg->install_readwrite_handler(0xb8000, 0xb87ff, read8_delegate( FUNC(isa8_cga_device::char_ram_read), this), write8_delegate(FUNC(isa8_cga_device::char_ram_write), this) ); |
| 1601 | 1601 | } else { |
| r17798 | r17799 | |
| 2013 | 2013 | m_isa->install_device(0x3d0, 0x3df, 0, 0, read8_delegate( FUNC(isa8_cga_pc1512_device::io_read), this ), write8_delegate( FUNC(isa8_cga_pc1512_device::io_write), this ) ); |
| 2014 | 2014 | m_isa->install_bank(0xb8000, 0xbbfff, 0, 0, "bank1", m_vram); |
| 2015 | 2015 | |
| 2016 | address_space *space = machine().firstcpu-> | |
| 2016 | address_space *space = machine().firstcpu-> | |
| 2017 | 2017 | |
| 2018 | 2018 | space->install_write_handler( 0xb8000, 0xbbfff, 0, 0x0C000, write8_delegate( FUNC(isa8_cga_pc1512_device::vram_w), this ) ); |
| 2019 | 2019 | } |
| r17798 | r17799 | |
|---|---|---|
| 180 | 180 | |
| 181 | 181 | inline void st_state::shifter_load() |
| 182 | 182 | { |
| 183 | address_space *program = m_maincpu-> | |
| 183 | address_space *program = m_maincpu-> | |
| 184 | 184 | UINT16 data = program->read_word(m_shifter_ofs); |
| 185 | 185 | |
| 186 | 186 | m_shifter_ir[m_shifter_bitplane] = data; |
| r17798 | r17799 | |
| 619 | 619 | |
| 620 | 620 | void st_state::blitter_source() |
| 621 | 621 | { |
| 622 | address_space *program = m_maincpu-> | |
| 622 | address_space *program = m_maincpu-> | |
| 623 | 623 | UINT16 data = program->read_word(m_blitter_src); |
| 624 | 624 | |
| 625 | 625 | if (m_blitter_src_inc_x < 0) |
| r17798 | r17799 | |
| 669 | 669 | |
| 670 | 670 | void st_state::blitter_op(UINT16 s, UINT32 dstaddr, UINT16 mask) |
| 671 | 671 | { |
| 672 | address_space *program = m_maincpu-> | |
| 672 | address_space *program = m_maincpu-> | |
| 673 | 673 | |
| 674 | 674 | UINT16 d = program->read_word(dstaddr); |
| 675 | 675 | UINT16 result = 0; |
| r17798 | r17799 | |
|---|---|---|
| 922 | 922 | static VIDEO_START( pc_t1t ) |
| 923 | 923 | { |
| 924 | 924 | int buswidth; |
| 925 | address_space *space = machine.firstcpu->memory().space(AS_PROGRAM); | |
| 926 | address_space *spaceio = machine.firstcpu->memory().space(AS_IO); | |
| 925 | address_space *space = machine.firstcpu->space(AS_PROGRAM); | |
| 926 | address_space *spaceio = machine.firstcpu->space(AS_IO); | |
| 927 | 927 | |
| 928 | 928 | pcjr.chr_gen = machine.root_device().memregion("gfx1")->base(); |
| 929 | 929 | pcjr.update_row = NULL; |
| 930 | 930 | pcjr.bank = 0; |
| 931 | 931 | pcjr.chr_size = 16; |
| 932 | 932 | |
| 933 | buswidth = machine.firstcpu-> | |
| 933 | buswidth = machine.firstcpu-> | |
| 934 | 934 | switch(buswidth) |
| 935 | 935 | { |
| 936 | 936 | case 8: |
| r17798 | r17799 | |
| 953 | 953 | static VIDEO_START( pc_pcjr ) |
| 954 | 954 | { |
| 955 | 955 | int buswidth; |
| 956 | address_space *spaceio = machine.firstcpu-> | |
| 956 | address_space *spaceio = machine.firstcpu-> | |
| 957 | 957 | |
| 958 | 958 | pcjr.chr_gen = machine.root_device().memregion("gfx1")->base(); |
| 959 | 959 | pcjr.update_row = NULL; |
| r17798 | r17799 | |
| 961 | 961 | pcjr.mode_control = 0x08; |
| 962 | 962 | pcjr.chr_size = 8; |
| 963 | 963 | |
| 964 | buswidth = machine.firstcpu-> | |
| 964 | buswidth = machine.firstcpu-> | |
| 965 | 965 | switch(buswidth) |
| 966 | 966 | { |
| 967 | 967 | case 8: |
| r17798 | r17799 | |
|---|---|---|
| 15 | 15 | |
| 16 | 16 | void newbrain_state::screen_update(bitmap_ind16 &bitmap, const rectangle &cliprect) |
| 17 | 17 | { |
| 18 | address_space *program = m_maincpu-> | |
| 18 | address_space *program = m_maincpu-> | |
| 19 | 19 | |
| 20 | 20 | int y, sx; |
| 21 | 21 | int columns = (m_tvctl & NEWBRAIN_VIDEO_80L) ? 80 : 40; |
| r17798 | r17799 | |
|---|---|---|
| 689 | 689 | |
| 690 | 690 | VIDEO_START( pc_aga ) |
| 691 | 691 | { |
| 692 | address_space *space = machine.firstcpu->memory().space(AS_PROGRAM); | |
| 693 | address_space *spaceio = machine.firstcpu->memory().space(AS_IO); | |
| 694 | int buswidth = machine.firstcpu->memory().space_config(AS_PROGRAM)->m_databus_width; | |
| 692 | address_space *space = machine.firstcpu->space(AS_PROGRAM); | |
| 693 | address_space *spaceio = machine.firstcpu->space(AS_IO); | |
| 694 | int buswidth = machine.firstcpu->space_config(AS_PROGRAM)->m_databus_width; | |
| 695 | 695 | switch(buswidth) |
| 696 | 696 | { |
| 697 | 697 | case 8: |
| r17798 | r17799 | |
| 720 | 720 | |
| 721 | 721 | VIDEO_START( pc200 ) |
| 722 | 722 | { |
| 723 | address_space *space = machine.firstcpu->memory().space(AS_PROGRAM); | |
| 724 | address_space *spaceio = machine.firstcpu->memory().space(AS_IO); | |
| 725 | int buswidth = machine.firstcpu->memory().space_config(AS_PROGRAM)->m_databus_width; | |
| 723 | address_space *space = machine.firstcpu->space(AS_PROGRAM); | |
| 724 | address_space *spaceio = machine.firstcpu->space(AS_IO); | |
| 725 | int buswidth = machine.firstcpu->space_config(AS_PROGRAM)->m_databus_width; | |
| 726 | 726 | switch(buswidth) |
| 727 | 727 | { |
| 728 | 728 | case 8: |
| r17798 | r17799 | |
|---|---|---|
| 151 | 151 | SCREEN_UPDATE_IND16( ti85 ) |
| 152 | 152 | { |
| 153 | 153 | ti85_state *state = screen.machine().driver_data<ti85_state>(); |
| 154 | address_space *space = state->m_maincpu-> | |
| 154 | address_space *space = state->m_maincpu-> | |
| 155 | 155 | int x,y,b; |
| 156 | 156 | int brightnes; |
| 157 | 157 | int lcdmem; |
| r17798 | r17799 | |
|---|---|---|
| 27 | 27 | { |
| 28 | 28 | cpu_device *cpu = image.device().machine().firstcpu; |
| 29 | 29 | UINT8 *RAM = image.device().machine().root_device().memregion(cpu->tag())->base(); |
| 30 | address_space *space = cpu-> | |
| 30 | address_space *space = cpu-> | |
| 31 | 31 | unsigned char ace_repeat, ace_byte, loop; |
| 32 | 32 | int done=0, ace_index=0x2000; |
| 33 | 33 |
| r17798 | r17799 | |
|---|---|---|
| 26 | 26 | |
| 27 | 27 | static void image_fread_memory(device_image_interface &image, UINT16 addr, UINT32 count) |
| 28 | 28 | { |
| 29 | void *ptr = image.device().machine().firstcpu-> | |
| 29 | void *ptr = image.device().machine().firstcpu-> | |
| 30 | 30 | |
| 31 | 31 | image.fread( ptr, count); |
| 32 | 32 | } |
| r17798 | r17799 | |
|---|---|---|
| 47 | 47 | |
| 48 | 48 | QUICKLOAD_LOAD( comx35_comx ) |
| 49 | 49 | { |
| 50 | address_space *program = image.device().machine().firstcpu-> | |
| 50 | address_space *program = image.device().machine().firstcpu-> | |
| 51 | 51 | |
| 52 | 52 | UINT8 header[16] = {0}; |
| 53 | 53 | int size = image.length(); |
| r17798 | r17799 | |
|---|---|---|
| 35 | 35 | |
| 36 | 36 | QUICKLOAD_LOAD( trs80_cmd ) |
| 37 | 37 | { |
| 38 | address_space *program = image.device().machine().firstcpu-> | |
| 38 | address_space *program = image.device().machine().firstcpu-> | |
| 39 | 39 | |
| 40 | 40 | UINT8 type, length; |
| 41 | 41 | UINT8 data[0x100]; |
| r17798 | r17799 | |
|---|---|---|
| 30 | 30 | UINT32 bytesread; |
| 31 | 31 | UINT16 address = 0; |
| 32 | 32 | int i; |
| 33 | address_space *space = image.device().machine().firstcpu-> | |
| 33 | address_space *space = image.device().machine().firstcpu-> | |
| 34 | 34 | |
| 35 | 35 | if (!file_type) |
| 36 | 36 | goto error; |
| r17798 | r17799 | |
| 93 | 93 | |
| 94 | 94 | static void cbm_quick_sethiaddress( running_machine &machine, UINT16 hiaddress ) |
| 95 | 95 | { |
| 96 | address_space *space = machine.firstcpu-> | |
| 96 | address_space *space = machine.firstcpu-> | |
| 97 | 97 | |
| 98 | 98 | space->write_byte(0x31, hiaddress & 0xff); |
| 99 | 99 | space->write_byte(0x2f, hiaddress & 0xff); |
| r17798 | r17799 | |
| 120 | 120 | |
| 121 | 121 | static void cbm_pet_quick_sethiaddress( running_machine &machine, UINT16 hiaddress ) |
| 122 | 122 | { |
| 123 | address_space *space = machine.firstcpu-> | |
| 123 | address_space *space = machine.firstcpu-> | |
| 124 | 124 | |
| 125 | 125 | space->write_byte(0x2e, hiaddress & 0xff); |
| 126 | 126 | space->write_byte(0x2c, hiaddress & 0xff); |
| r17798 | r17799 | |
| 137 | 137 | |
| 138 | 138 | static void cbm_pet1_quick_sethiaddress(running_machine &machine, UINT16 hiaddress) |
| 139 | 139 | { |
| 140 | address_space *space = machine.firstcpu-> | |
| 140 | address_space *space = machine.firstcpu-> | |
| 141 | 141 | |
| 142 | 142 | space->write_byte(0x80, hiaddress & 0xff); |
| 143 | 143 | space->write_byte(0x7e, hiaddress & 0xff); |
| r17798 | r17799 | |
| 154 | 154 | |
| 155 | 155 | static void cbmb_quick_sethiaddress(running_machine &machine, UINT16 hiaddress) |
| 156 | 156 | { |
| 157 | address_space *space = machine.firstcpu-> | |
| 157 | address_space *space = machine.firstcpu-> | |
| 158 | 158 | |
| 159 | 159 | space->write_byte(0xf0046, hiaddress & 0xff); |
| 160 | 160 | space->write_byte(0xf0047, hiaddress >> 8); |
| r17798 | r17799 | |
| 172 | 172 | |
| 173 | 173 | static void cbm_c65_quick_sethiaddress( running_machine &machine, UINT16 hiaddress ) |
| 174 | 174 | { |
| 175 | address_space *space = machine.firstcpu-> | |
| 175 | address_space *space = machine.firstcpu-> | |
| 176 | 176 | |
| 177 | 177 | space->write_byte(0x82, hiaddress & 0xff); |
| 178 | 178 | space->write_byte(0x83, hiaddress >> 8); |
| r17798 | r17799 | |
|---|---|---|
| 236 | 236 | |
| 237 | 237 | void elf2_state::machine_start() |
| 238 | 238 | { |
| 239 | address_space *program = m_maincpu-> | |
| 239 | address_space *program = m_maincpu-> | |
| 240 | 240 | |
| 241 | 241 | /* initialize LED displays */ |
| 242 | 242 | m_led_l->rbi_w(1); |
| r17798 | r17799 | |
|---|---|---|
| 72 | 72 | |
| 73 | 73 | void pc8401a_state::bankswitch(UINT8 data) |
| 74 | 74 | { |
| 75 | address_space *program = m_maincpu-> | |
| 75 | address_space *program = m_maincpu-> | |
| 76 | 76 | |
| 77 | 77 | int rombank = data & 0x03; |
| 78 | 78 | int ram0000 = (data >> 2) & 0x03; |
| r17798 | r17799 | |
|---|---|---|
| 26 | 26 | |
| 27 | 27 | void mc1000_state::bankswitch() |
| 28 | 28 | { |
| 29 | address_space *program = m_maincpu-> | |
| 29 | address_space *program = m_maincpu-> | |
| 30 | 30 | |
| 31 | 31 | /* MC6845 video RAM */ |
| 32 | 32 | membank("bank2")->set_entry(m_mc6845_bank); |
| r17798 | r17799 | |
| 323 | 323 | |
| 324 | 324 | void mc1000_state::machine_start() |
| 325 | 325 | { |
| 326 | address_space *program = m_maincpu-> | |
| 326 | address_space *program = m_maincpu-> | |
| 327 | 327 | |
| 328 | 328 | /* setup memory banking */ |
| 329 | 329 | UINT8 *rom = memregion(Z80_TAG)->base(); |
| r17798 | r17799 | |
|---|---|---|
| 245 | 245 | |
| 246 | 246 | void adam_state::bankswitch() |
| 247 | 247 | { |
| 248 | address_space *program = m_maincpu-> | |
| 248 | address_space *program = m_maincpu-> | |
| 249 | 249 | UINT8 *ram = m_ram->pointer(); |
| 250 | 250 | |
| 251 | 251 | switch (m_mioc & 0x03) |
| r17798 | r17799 | |
|---|---|---|
| 65 | 65 | |
| 66 | 66 | void msbc1_state::machine_reset() |
| 67 | 67 | { |
| 68 | void *ram = machine().firstcpu-> | |
| 68 | void *ram = machine().firstcpu-> | |
| 69 | 69 | UINT8 *rom = memregion(MC68000R12_TAG)->base(); |
| 70 | 70 | |
| 71 | 71 | memcpy(ram, rom, 8); |
| r17798 | r17799 | |
|---|---|---|
| 71 | 71 | |
| 72 | 72 | void unixpc_state::machine_reset() |
| 73 | 73 | { |
| 74 | address_space *program = m_maincpu-> | |
| 74 | address_space *program = m_maincpu-> | |
| 75 | 75 | |
| 76 | 76 | // force ROM into lower mem on reset |
| 77 | 77 | romlmap_w(*program, 0, 0, 0xffff); |
| r17798 | r17799 | |
|---|---|---|
| 888 | 888 | |
| 889 | 889 | READ8_MEMBER( pc1512_state::memr_r ) |
| 890 | 890 | { |
| 891 | address_space *program = m_maincpu-> | |
| 891 | address_space *program = m_maincpu-> | |
| 892 | 892 | offs_t page_offset = m_dma_page[m_dma_channel] << 16; |
| 893 | 893 | |
| 894 | 894 | return program->read_byte(page_offset + offset); |
| r17798 | r17799 | |
| 896 | 896 | |
| 897 | 897 | WRITE8_MEMBER( pc1512_state::memw_w ) |
| 898 | 898 | { |
| 899 | address_space *program = m_maincpu-> | |
| 899 | address_space *program = m_maincpu-> | |
| 900 | 900 | offs_t page_offset = m_dma_page[m_dma_channel] << 16; |
| 901 | 901 | |
| 902 | 902 | program->write_byte(page_offset + offset, data); |
| r17798 | r17799 | |
| 1210 | 1210 | |
| 1211 | 1211 | if (ram_size < 640 * 1024) |
| 1212 | 1212 | { |
| 1213 | address_space *program = m_maincpu-> | |
| 1213 | address_space *program = m_maincpu-> | |
| 1214 | 1214 | program->unmap_readwrite(ram_size, 0x9ffff); |
| 1215 | 1215 | } |
| 1216 | 1216 |
| r17798 | r17799 | |
|---|---|---|
| 441 | 441 | |
| 442 | 442 | void vii_state::vii_do_dma(UINT32 len) |
| 443 | 443 | { |
| 444 | address_space *mem = m_maincpu-> | |
| 444 | address_space *mem = m_maincpu-> | |
| 445 | 445 | UINT32 src = m_video_regs[0x70]; |
| 446 | 446 | UINT32 dst = m_video_regs[0x71] + 0x2c00; |
| 447 | 447 | UINT32 j; |
| r17798 | r17799 | |
| 612 | 612 | |
| 613 | 613 | void vii_state::spg_do_dma(UINT32 len) |
| 614 | 614 | { |
| 615 | address_space *mem = m_maincpu-> | |
| 615 | address_space *mem = m_maincpu-> | |
| 616 | 616 | |
| 617 | 617 | UINT32 src = ((m_io_regs[0x101] & 0x3f) << 16) | m_io_regs[0x100]; |
| 618 | 618 | UINT32 dst = m_io_regs[0x103] & 0x3fff; |
| r17798 | r17799 | |
|---|---|---|
| 57 | 57 | |
| 58 | 58 | void xor100_state::bankswitch() |
| 59 | 59 | { |
| 60 | address_space *program = m_maincpu-> | |
| 60 | address_space *program = m_maincpu-> | |
| 61 | 61 | int banks = m_ram->size() / 0x10000; |
| 62 | 62 | |
| 63 | 63 | switch (m_mode) |
| r17798 | r17799 | |
|---|---|---|
| 171 | 171 | irq_mask = data; |
| 172 | 172 | ///printf("%02x\n",data); |
| 173 | 173 | // FIXME - the below 2 lines are needed, otherwise nothing ever gets written to videoram |
| 174 | address_space *mem = m_subcpu-> | |
| 174 | address_space *mem = m_subcpu-> | |
| 175 | 175 | data = mem->read_byte(0xe800); |
| 176 | 176 | } |
| 177 | 177 |
| r17798 | r17799 | |
|---|---|---|
| 237 | 237 | |
| 238 | 238 | void tmc600_state::machine_start() |
| 239 | 239 | { |
| 240 | address_space *program = m_maincpu-> | |
| 240 | address_space *program = m_maincpu-> | |
| 241 | 241 | |
| 242 | 242 | /* configure RAM */ |
| 243 | 243 | switch (m_ram->size()) |
| r17798 | r17799 | |
|---|---|---|
| 165 | 165 | { |
| 166 | 166 | m_term_data = data; |
| 167 | 167 | //m_term_key = 1; |
| 168 | address_space *mem = m_maincpu-> | |
| 168 | address_space *mem = m_maincpu-> | |
| 169 | 169 | mem->write_byte(0xebec, data); // this has to be 0xecf1 for bios 1 |
| 170 | 170 | mem->write_byte(0xebd0, 1); // any non-zero here |
| 171 | 171 | } |
| r17798 | r17799 | |
|---|---|---|
| 590 | 590 | |
| 591 | 591 | void ace_state::machine_start() |
| 592 | 592 | { |
| 593 | address_space *program = m_maincpu-> | |
| 593 | address_space *program = m_maincpu-> | |
| 594 | 594 | |
| 595 | 595 | /* configure RAM */ |
| 596 | 596 | switch (m_ram->size()) |
| r17798 | r17799 | |
|---|---|---|
| 479 | 479 | DRIVER_INIT_MEMBER(mpf1_state,mpf1) |
| 480 | 480 | { |
| 481 | 481 | |
| 482 | m_maincpu-> | |
| 482 | m_maincpu-> | |
| 483 | 483 | } |
| 484 | 484 | |
| 485 | 485 | COMP( 1979, mpf1, 0, 0, mpf1, mpf1, mpf1_state, mpf1, "Multitech", "Micro Professor 1", 0) |
| r17798 | r17799 | |
|---|---|---|
| 802 | 802 | |
| 803 | 803 | READ8_MEMBER( plus4_state::exp_dma_r ) |
| 804 | 804 | { |
| 805 | return m_maincpu-> | |
| 805 | return m_maincpu-> | |
| 806 | 806 | } |
| 807 | 807 | |
| 808 | 808 | WRITE8_MEMBER( plus4_state::exp_dma_w ) |
| 809 | 809 | { |
| 810 | m_maincpu-> | |
| 810 | m_maincpu-> | |
| 811 | 811 | } |
| 812 | 812 | |
| 813 | 813 | WRITE_LINE_MEMBER( plus4_state::exp_irq_w ) |
| r17798 | r17799 | |
|---|---|---|
| 67 | 67 | if (m_fdc_fifo_empty[m_fdc_fifo_sel]) return; |
| 68 | 68 | |
| 69 | 69 | if (m_fdc_dmabytes) { |
| 70 | address_space *program = m_maincpu-> | |
| 70 | address_space *program = m_maincpu-> | |
| 71 | 71 | for (int i = 0; i < 8; i++) { |
| 72 | 72 | UINT16 data = m_fdc_fifo[m_fdc_fifo_sel][i]; |
| 73 | 73 | |
| r17798 | r17799 | |
| 98 | 98 | void st_state::fill_dma_fifo() |
| 99 | 99 | { |
| 100 | 100 | if (m_fdc_dmabytes) { |
| 101 | address_space *program = m_maincpu-> | |
| 101 | address_space *program = m_maincpu-> | |
| 102 | 102 | for (int i = 0; i < 8; i++) { |
| 103 | 103 | UINT16 data = program->read_word(m_dma_base); |
| 104 | 104 | |
| r17798 | r17799 | |
| 2142 | 2142 | |
| 2143 | 2143 | void st_state::configure_memory() |
| 2144 | 2144 | { |
| 2145 | address_space *program = m_maincpu-> | |
| 2145 | address_space *program = m_maincpu-> | |
| 2146 | 2146 | |
| 2147 | 2147 | switch (m_ram->size()) |
| 2148 | 2148 | { |
| r17798 | r17799 | |
| 2292 | 2292 | void stbook_state::machine_start() |
| 2293 | 2293 | { |
| 2294 | 2294 | /* configure RAM banking */ |
| 2295 | address_space *program = m_maincpu-> | |
| 2295 | address_space *program = m_maincpu-> | |
| 2296 | 2296 | |
| 2297 | 2297 | switch (m_ram->size()) |
| 2298 | 2298 | { |
| r17798 | r17799 | |
|---|---|---|
| 642 | 642 | |
| 643 | 643 | void sg1000_state::install_cartridge(UINT8 *ptr, int size) |
| 644 | 644 | { |
| 645 | address_space *program = m_maincpu-> | |
| 645 | address_space *program = m_maincpu-> | |
| 646 | 646 | |
| 647 | 647 | switch (size) |
| 648 | 648 | { |
| r17798 | r17799 | |
| 825 | 825 | |
| 826 | 826 | void sc3000_state::install_cartridge(UINT8 *ptr, int size) |
| 827 | 827 | { |
| 828 | address_space *program = m_maincpu-> | |
| 828 | address_space *program = m_maincpu-> | |
| 829 | 829 | |
| 830 | 830 | /* include SG-1000 mapping */ |
| 831 | 831 | sg1000_state::install_cartridge(ptr, size); |
| r17798 | r17799 | |
|---|---|---|
| 75 | 75 | |
| 76 | 76 | void px8_state::bankswitch() |
| 77 | 77 | { |
| 78 | address_space *program = m_maincpu-> | |
| 78 | address_space *program = m_maincpu-> | |
| 79 | 79 | UINT8 *ram = m_ram->pointer(); |
| 80 | 80 | UINT8 *ipl_rom = memregion(UPD70008_TAG)->base(); |
| 81 | 81 |
| r17798 | r17799 | |
|---|---|---|
| 757 | 757 | |
| 758 | 758 | void mm1_state::machine_reset() |
| 759 | 759 | { |
| 760 | address_space *program = m_maincpu-> | |
| 760 | address_space *program = m_maincpu-> | |
| 761 | 761 | int i; |
| 762 | 762 | |
| 763 | 763 | // reset LS259 |
| r17798 | r17799 | |
|---|---|---|
| 674 | 674 | |
| 675 | 675 | void sb2m600_state::machine_start() |
| 676 | 676 | { |
| 677 | address_space *program = m_maincpu-> | |
| 677 | address_space *program = m_maincpu-> | |
| 678 | 678 | |
| 679 | 679 | /* configure RAM banking */ |
| 680 | 680 | membank("bank1")->configure_entry(0, memregion(M6502_TAG)->base()); |
| r17798 | r17799 | |
| 699 | 699 | |
| 700 | 700 | void c1p_state::machine_start() |
| 701 | 701 | { |
| 702 | address_space *program = m_maincpu-> | |
| 702 | address_space *program = m_maincpu-> | |
| 703 | 703 | |
| 704 | 704 | /* configure RAM banking */ |
| 705 | 705 | membank("bank1")->configure_entry(0, memregion(M6502_TAG)->base()); |
| r17798 | r17799 | |
|---|---|---|
| 153 | 153 | |
| 154 | 154 | WRITE8_MEMBER( rex6000_state::bankswitch_w ) |
| 155 | 155 | { |
| 156 | address_space* program = m_maincpu-> | |
| 156 | address_space* program = m_maincpu-> | |
| 157 | 157 | |
| 158 | 158 | m_bank[offset&3] = data; |
| 159 | 159 | |
| r17798 | r17799 | |
| 451 | 451 | } |
| 452 | 452 | void rex6000_state::machine_reset() |
| 453 | 453 | { |
| 454 | address_space* program = m_maincpu-> | |
| 454 | address_space* program = m_maincpu-> | |
| 455 | 455 | |
| 456 | 456 | program->install_readwrite_handler(0x8000, 0x9fff, 0, 0, read8_delegate(FUNC(rex6000_state::flash_0x8000_r), this), write8_delegate(FUNC(rex6000_state::flash_0x8000_w), this)); |
| 457 | 457 | program->install_readwrite_handler(0xa000, 0xbfff, 0, 0, read8_delegate(FUNC(rex6000_state::flash_0xa000_r), this), write8_delegate(FUNC(rex6000_state::flash_0xa000_w), this)); |
| r17798 | r17799 | |
| 492 | 492 | } |
| 493 | 493 | else |
| 494 | 494 | { |
| 495 | data = m_flash[mem_type]-> | |
| 495 | data = m_flash[mem_type]-> | |
| 496 | 496 | } |
| 497 | 497 | |
| 498 | 498 |
| r17798 | r17799 | |
|---|---|---|
| 126 | 126 | |
| 127 | 127 | void v1050_state::bankswitch() |
| 128 | 128 | { |
| 129 | address_space *program = m_maincpu-> | |
| 129 | address_space *program = m_maincpu-> | |
| 130 | 130 | |
| 131 | 131 | int bank = (m_bank >> 1) & 0x03; |
| 132 | 132 | |
| r17798 | r17799 | |
| 1020 | 1020 | |
| 1021 | 1021 | void v1050_state::machine_start() |
| 1022 | 1022 | { |
| 1023 | address_space *program = m_maincpu-> | |
| 1023 | address_space *program = m_maincpu-> | |
| 1024 | 1024 | |
| 1025 | 1025 | // initialize SASI bus |
| 1026 | 1026 | m_sasibus->init_scsibus(256); |
| r17798 | r17799 | |
|---|---|---|
| 941 | 941 | |
| 942 | 942 | void ql_state::machine_reset() |
| 943 | 943 | { |
| 944 | address_space *program = m_maincpu-> | |
| 944 | address_space *program = m_maincpu-> | |
| 945 | 945 | |
| 946 | 946 | m_disk_type=ioport(QL_CONFIG_PORT)->read() & DISK_TYPE_MASK; |
| 947 | 947 | logerror("disktype=%d\n",m_disk_type); |
| r17798 | r17799 | |
|---|---|---|
| 192 | 192 | |
| 193 | 193 | void abc800_state::bankswitch() |
| 194 | 194 | { |
| 195 | address_space *program = m_maincpu-> | |
| 195 | address_space *program = m_maincpu-> | |
| 196 | 196 | |
| 197 | 197 | if (m_fetch_charram) |
| 198 | 198 | { |
| r17798 | r17799 | |
| 213 | 213 | |
| 214 | 214 | void abc802_state::bankswitch() |
| 215 | 215 | { |
| 216 | address_space *program = m_maincpu-> | |
| 216 | address_space *program = m_maincpu-> | |
| 217 | 217 | |
| 218 | 218 | if (m_lrs) |
| 219 | 219 | { |
| r17798 | r17799 | |
| 235 | 235 | |
| 236 | 236 | void abc806_state::bankswitch() |
| 237 | 237 | { |
| 238 | address_space *program = m_maincpu-> | |
| 238 | address_space *program = m_maincpu-> | |
| 239 | 239 | UINT32 videoram_mask = m_ram->size() - (32 * 1024) - 1; |
| 240 | 240 | int bank; |
| 241 | 241 | char bank_name[10]; |
| r17798 | r17799 | |
|---|---|---|
| 604 | 604 | |
| 605 | 605 | void a7000_state::viddma_transfer_start() |
| 606 | 606 | { |
| 607 | address_space *mem = m_maincpu-> | |
| 607 | address_space *mem = m_maincpu-> | |
| 608 | 608 | UINT32 src = m_viddma_addr_start; |
| 609 | 609 | UINT32 dst = 0; |
| 610 | 610 | UINT32 size = m_viddma_addr_end; |
| r17798 | r17799 | |
|---|---|---|
| 415 | 415 | |
| 416 | 416 | WRITE_LINE_MEMBER( bigbord2_state::frame ) |
| 417 | 417 | { |
| 418 | address_space *space = m_maincpu-> | |
| 418 | address_space *space = m_maincpu-> | |
| 419 | 419 | static UINT8 framecnt; |
| 420 | 420 | framecnt++; |
| 421 | 421 |
| r17798 | r17799 | |
|---|---|---|
| 32 | 32 | |
| 33 | 33 | void tvc_state::tvc_set_mem_page(UINT8 data) |
| 34 | 34 | { |
| 35 | address_space *space = m_maincpu-> | |
| 35 | address_space *space = m_maincpu-> | |
| 36 | 36 | switch(data & 0x18) |
| 37 | 37 | { |
| 38 | 38 | case 0x00 : // system ROM selected |
| r17798 | r17799 | |
|---|---|---|
| 167 | 167 | |
| 168 | 168 | void tmc2000_state::bankswitch() |
| 169 | 169 | { |
| 170 | address_space *program = m_maincpu-> | |
| 170 | address_space *program = m_maincpu-> | |
| 171 | 171 | UINT8 *ram = m_ram->pointer(); |
| 172 | 172 | UINT8 *rom = memregion(CDP1802_TAG)->base(); |
| 173 | 173 | |
| r17798 | r17799 | |
| 220 | 220 | WRITE8_MEMBER( nano_state::bankswitch_w ) |
| 221 | 221 | { |
| 222 | 222 | /* enable RAM */ |
| 223 | address_space *program = m_maincpu-> | |
| 223 | address_space *program = m_maincpu-> | |
| 224 | 224 | UINT8 *ram = m_ram->pointer(); |
| 225 | 225 | program->install_ram(0x0000, 0x0fff, 0, 0x7000, ram); |
| 226 | 226 | |
| r17798 | r17799 | |
| 745 | 745 | m_cti->reset(); |
| 746 | 746 | |
| 747 | 747 | /* enable ROM */ |
| 748 | address_space *program = m_maincpu-> | |
| 748 | address_space *program = m_maincpu-> | |
| 749 | 749 | UINT8 *rom = memregion(CDP1802_TAG)->base(); |
| 750 | 750 | program->install_rom(0x0000, 0x01ff, 0, 0x7e00, rom); |
| 751 | 751 | } |
| r17798 | r17799 | |
|---|---|---|
| 66 | 66 | |
| 67 | 67 | void newbrain_eim_state::bankswitch() |
| 68 | 68 | { |
| 69 | address_space *program = m_maincpu-> | |
| 69 | address_space *program = m_maincpu-> | |
| 70 | 70 | int bank; |
| 71 | 71 | |
| 72 | 72 | for (bank = 1; bank < 9; bank++) |
| r17798 | r17799 | |
| 104 | 104 | |
| 105 | 105 | void newbrain_state::bankswitch() |
| 106 | 106 | { |
| 107 | address_space *program = m_maincpu-> | |
| 107 | address_space *program = m_maincpu-> | |
| 108 | 108 | int bank; |
| 109 | 109 | |
| 110 | 110 | for (bank = 1; bank < 9; bank++) |
| r17798 | r17799 | |
|---|---|---|
| 696 | 696 | |
| 697 | 697 | READ8_MEMBER( wangpc_state::memr_r ) |
| 698 | 698 | { |
| 699 | address_space *program = m_maincpu-> | |
| 699 | address_space *program = m_maincpu-> | |
| 700 | 700 | offs_t addr = (m_dma_page[m_dack] << 16) | offset; |
| 701 | 701 | |
| 702 | 702 | return program->read_byte(addr); |
| r17798 | r17799 | |
| 704 | 704 | |
| 705 | 705 | WRITE8_MEMBER( wangpc_state::memw_w ) |
| 706 | 706 | { |
| 707 | address_space *program = m_maincpu-> | |
| 707 | address_space *program = m_maincpu-> | |
| 708 | 708 | offs_t addr = (m_dma_page[m_dack] << 16) | offset; |
| 709 | 709 | |
| 710 | 710 | program->write_byte(addr, data); |
| r17798 | r17799 | |
|---|---|---|
| 295 | 295 | |
| 296 | 296 | READ8_MEMBER( fk1_state::fk1_bank_ram_r ) |
| 297 | 297 | { |
| 298 | address_space *space_mem = m_maincpu-> | |
| 298 | address_space *space_mem = m_maincpu-> | |
| 299 | 299 | UINT8 *ram = machine().device<ram_device>(RAM_TAG)->pointer(); |
| 300 | 300 | |
| 301 | 301 | space_mem->install_write_bank(0x0000, 0x3fff, "bank1"); |
| r17798 | r17799 | |
| 306 | 306 | |
| 307 | 307 | READ8_MEMBER( fk1_state::fk1_bank_rom_r ) |
| 308 | 308 | { |
| 309 | address_space *space_mem = m_maincpu-> | |
| 309 | address_space *space_mem = m_maincpu-> | |
| 310 | 310 | space_mem->unmap_write(0x0000, 0x3fff); |
| 311 | 311 | membank("bank1")->set_base(machine().root_device().memregion("maincpu")->base()); |
| 312 | 312 | membank("bank2")->set_base(machine().device<ram_device>(RAM_TAG)->pointer() + 0x10000); |
| r17798 | r17799 | |
| 425 | 425 | |
| 426 | 426 | MACHINE_RESET_MEMBER( fk1_state ) |
| 427 | 427 | { |
| 428 | address_space *space = m_maincpu-> | |
| 428 | address_space *space = m_maincpu-> | |
| 429 | 429 | UINT8 *ram = machine().device<ram_device>(RAM_TAG)->pointer(); |
| 430 | 430 | |
| 431 | 431 | space->unmap_write(0x0000, 0x3fff); |
| r17798 | r17799 | |
|---|---|---|
| 127 | 127 | WRITE8_MEMBER( camplynx_state::lynx128k_bank_w ) |
| 128 | 128 | { |
| 129 | 129 | /* get address space */ |
| 130 | address_space *mem = m_maincpu-> | |
| 130 | address_space *mem = m_maincpu-> | |
| 131 | 131 | UINT8 *base = mem->machine().root_device().memregion("maincpu")->base(); |
| 132 | 132 | |
| 133 | 133 | /* Set read banks */ |
| r17798 | r17799 | |
| 328 | 328 | static MACHINE_RESET( lynx128k ) |
| 329 | 329 | { |
| 330 | 330 | camplynx_state *state = machine.driver_data<camplynx_state>(); |
| 331 | address_space *mem = state->m_maincpu-> | |
| 331 | address_space *mem = state->m_maincpu-> | |
| 332 | 332 | mem->install_read_bank (0x0000, 0x1fff, "bank1"); |
| 333 | 333 | mem->install_read_bank (0x2000, 0x3fff, "bank2"); |
| 334 | 334 | mem->install_read_bank (0x4000, 0x5fff, "bank3"); |
| r17798 | r17799 | |
|---|---|---|
| 104 | 104 | |
| 105 | 105 | void pc8201_state::bankswitch(UINT8 data) |
| 106 | 106 | { |
| 107 | address_space *program = m_maincpu-> | |
| 107 | address_space *program = m_maincpu-> | |
| 108 | 108 | |
| 109 | 109 | int rom_bank = data & 0x03; |
| 110 | 110 | int ram_bank = (data >> 2) & 0x03; |
| r17798 | r17799 | |
| 454 | 454 | |
| 455 | 455 | void tandy200_state::bankswitch(UINT8 data) |
| 456 | 456 | { |
| 457 | address_space *program = m_maincpu-> | |
| 457 | address_space *program = m_maincpu-> | |
| 458 | 458 | |
| 459 | 459 | int rom_bank = data & 0x03; |
| 460 | 460 | int ram_bank = (data >> 2) & 0x03; |
| r17798 | r17799 | |
| 1127 | 1127 | |
| 1128 | 1128 | void kc85_state::machine_start() |
| 1129 | 1129 | { |
| 1130 | address_space *program = m_maincpu-> | |
| 1130 | address_space *program = m_maincpu-> | |
| 1131 | 1131 | |
| 1132 | 1132 | /* initialize RTC */ |
| 1133 | 1133 | m_rtc->cs_w(1); |
| r17798 | r17799 | |
| 1194 | 1194 | |
| 1195 | 1195 | void trsm100_state::machine_start() |
| 1196 | 1196 | { |
| 1197 | address_space *program = m_maincpu-> | |
| 1197 | address_space *program = m_maincpu-> | |
| 1198 | 1198 | |
| 1199 | 1199 | /* initialize RTC */ |
| 1200 | 1200 | m_rtc->cs_w(1); |
| r17798 | r17799 | |
|---|---|---|
| 634 | 634 | |
| 635 | 635 | void bml3_state::machine_reset() |
| 636 | 636 | { |
| 637 | address_space *mem = m_maincpu-> | |
| 637 | address_space *mem = m_maincpu-> | |
| 638 | 638 | |
| 639 | 639 | /* defaults */ |
| 640 | 640 | mem->install_rom(0xa000, 0xfeff,mem->machine().root_device().memregion("maincpu")->base() + 0xa000); |
| r17798 | r17799 | |
| 698 | 698 | |
| 699 | 699 | WRITE8_MEMBER(bml3_state::bml3_piaA_w) |
| 700 | 700 | { |
| 701 | address_space *mem = m_maincpu-> | |
| 701 | address_space *mem = m_maincpu-> | |
| 702 | 702 | /* ROM banking: |
| 703 | 703 | -0-- --0- 0xa000 - 0xbfff ROM R RAM W |
| 704 | 704 | -1-- --0- 0xa000 - 0xbfff RAM R/W |
| r17798 | r17799 | |
|---|---|---|
| 44 | 44 | |
| 45 | 45 | void tiki100_state::bankswitch() |
| 46 | 46 | { |
| 47 | address_space *program = m_maincpu-> | |
| 47 | address_space *program = m_maincpu-> | |
| 48 | 48 | |
| 49 | 49 | if (m_vire) |
| 50 | 50 | { |
| r17798 | r17799 | |
|---|---|---|
| 182 | 182 | else if (offset < 0x180000) |
| 183 | 183 | { |
| 184 | 184 | // video RAM |
| 185 | address_space *program = m_maincpu-> | |
| 185 | address_space *program = m_maincpu-> | |
| 186 | 186 | data = video_ram_r(*program, offset); |
| 187 | 187 | } |
| 188 | 188 | else |
| r17798 | r17799 | |
| 209 | 209 | else if (offset < 0x180000) |
| 210 | 210 | { |
| 211 | 211 | // video RAM |
| 212 | address_space *program = m_maincpu-> | |
| 212 | address_space *program = m_maincpu-> | |
| 213 | 213 | video_ram_w(*program, offset, data); |
| 214 | 214 | } |
| 215 | 215 | else |
| r17798 | r17799 | |
| 242 | 242 | |
| 243 | 243 | UINT8 abc1600_state::read_internal_io(offs_t offset) |
| 244 | 244 | { |
| 245 | address_space *program = m_maincpu-> | |
| 245 | address_space *program = m_maincpu-> | |
| 246 | 246 | UINT8 data = 0; |
| 247 | 247 | |
| 248 | 248 | if (X11) |
| r17798 | r17799 | |
| 467 | 467 | |
| 468 | 468 | void abc1600_state::write_internal_io(offs_t offset, UINT8 data) |
| 469 | 469 | { |
| 470 | address_space *program = m_maincpu-> | |
| 470 | address_space *program = m_maincpu-> | |
| 471 | 471 | |
| 472 | 472 | if (X11) |
| 473 | 473 | { |
| r17798 | r17799 | |
| 770 | 770 | |
| 771 | 771 | UINT8 abc1600_state::read_supervisor_memory(offs_t offset) |
| 772 | 772 | { |
| 773 | address_space *program = m_maincpu-> | |
| 773 | address_space *program = m_maincpu-> | |
| 774 | 774 | UINT8 data = 0; |
| 775 | 775 | |
| 776 | 776 | if (!A2 && !A1) |
| r17798 | r17799 | |
| 799 | 799 | |
| 800 | 800 | void abc1600_state::write_supervisor_memory(offs_t offset, UINT8 data) |
| 801 | 801 | { |
| 802 | address_space *program = m_maincpu-> | |
| 802 | address_space *program = m_maincpu-> | |
| 803 | 803 | |
| 804 | 804 | if (!A2 && !A1) |
| 805 | 805 | { |
| r17798 | r17799 | |
| 1879 | 1879 | |
| 1880 | 1880 | void abc1600_state::machine_reset() |
| 1881 | 1881 | { |
| 1882 | address_space *program = m_maincpu-> | |
| 1882 | address_space *program = m_maincpu-> | |
| 1883 | 1883 | |
| 1884 | 1884 | // clear special control register |
| 1885 | 1885 | for (int i = 0; i < 8; i++) |
| r17798 | r17799 | |
|---|---|---|
| 288 | 288 | |
| 289 | 289 | void ob68k1a_state::machine_start() |
| 290 | 290 | { |
| 291 | address_space *program = m_maincpu-> | |
| 291 | address_space *program = m_maincpu-> | |
| 292 | 292 | |
| 293 | 293 | // configure RAM |
| 294 | 294 | switch (m_ram->size()) |
| r17798 | r17799 | |
| 306 | 306 | |
| 307 | 307 | void ob68k1a_state::machine_reset() |
| 308 | 308 | { |
| 309 | address_space *program = m_maincpu-> | |
| 309 | address_space *program = m_maincpu-> | |
| 310 | 310 | |
| 311 | 311 | // initialize COM8116 |
| 312 | 312 | // m_dbrg->stt_w(program, 0, 0x01); |
| r17798 | r17799 | |
|---|---|---|
| 49 | 49 | |
| 50 | 50 | READ8_MEMBER( tandy2k_state::videoram_r ) |
| 51 | 51 | { |
| 52 | address_space *program = m_maincpu-> | |
| 52 | address_space *program = m_maincpu-> | |
| 53 | 53 | |
| 54 | 54 | offs_t addr = (m_vram_base << 15) | (offset << 1); |
| 55 | 55 | UINT16 data = program->read_word(addr); |
| r17798 | r17799 | |
| 319 | 319 | static CRT9007_DRAW_SCANLINE( tandy2k_crt9007_display_pixels ) |
| 320 | 320 | { |
| 321 | 321 | tandy2k_state *state = device->machine().driver_data<tandy2k_state>(); |
| 322 | address_space *program = state->m_maincpu-> | |
| 322 | address_space *program = state->m_maincpu-> | |
| 323 | 323 | |
| 324 | 324 | for (int sx = 0; sx < x_count; sx++) |
| 325 | 325 | { |
| r17798 | r17799 | |
| 670 | 670 | void tandy2k_state::machine_start() |
| 671 | 671 | { |
| 672 | 672 | // memory banking |
| 673 | address_space *program = m_maincpu-> | |
| 673 | address_space *program = m_maincpu-> | |
| 674 | 674 | UINT8 *ram = m_ram->pointer(); |
| 675 | 675 | int ram_size = m_ram->size(); |
| 676 | 676 |
| r17798 | r17799 | |
|---|---|---|
| 1042 | 1042 | { |
| 1043 | 1043 | running_machine &machine = image.device().machine(); |
| 1044 | 1044 | x07_state *state = machine.driver_data<x07_state>(); |
| 1045 | address_space *space = state->m_maincpu-> | |
| 1045 | address_space *space = state->m_maincpu-> | |
| 1046 | 1046 | UINT16 ram_size = state->m_ram->size(); |
| 1047 | 1047 | |
| 1048 | 1048 | if (image.software_entry() == NULL) |
| r17798 | r17799 | |
| 1454 | 1454 | save_item(NAME(m_cursor.on)); |
| 1455 | 1455 | |
| 1456 | 1456 | /* install RAM */ |
| 1457 | address_space *program = m_maincpu-> | |
| 1457 | address_space *program = m_maincpu-> | |
| 1458 | 1458 | program->install_ram(0x0000, m_ram->size() - 1, m_ram->pointer()); |
| 1459 | 1459 | } |
| 1460 | 1460 |
| r17798 | r17799 | |
|---|---|---|
| 147 | 147 | static TIMER_DEVICE_CALLBACK( timer_callback ) |
| 148 | 148 | { |
| 149 | 149 | z9001_state *state = timer.machine().driver_data<z9001_state>(); |
| 150 | state->m_maincpu-> | |
| 150 | state->m_maincpu-> | |
| 151 | 151 | } |
| 152 | 152 | |
| 153 | 153 | MACHINE_RESET_MEMBER( z9001_state ) |
| r17798 | r17799 | |
| 221 | 221 | |
| 222 | 222 | WRITE8_MEMBER( z9001_state::kbd_put ) |
| 223 | 223 | { |
| 224 | m_maincpu-> | |
| 224 | m_maincpu-> | |
| 225 | 225 | } |
| 226 | 226 | |
| 227 | 227 | static ASCII_KEYBOARD_INTERFACE( keyboard_intf ) |
| r17798 | r17799 | |
|---|---|---|
| 576 | 576 | |
| 577 | 577 | if(m_mio_sel) |
| 578 | 578 | { |
| 579 | address_space *ram_space = m_maincpu-> | |
| 579 | address_space *ram_space = m_maincpu-> | |
| 580 | 580 | |
| 581 | 581 | m_mio_sel = 0; |
| 582 | 582 | //printf("%08x\n",offset); |
| r17798 | r17799 | |
| 627 | 627 | |
| 628 | 628 | if(m_mio_sel) |
| 629 | 629 | { |
| 630 | address_space *ram_space = m_maincpu-> | |
| 630 | address_space *ram_space = m_maincpu-> | |
| 631 | 631 | m_mio_sel = 0; |
| 632 | 632 | ram_space->write_byte(offset, data); |
| 633 | 633 | return; |
| r17798 | r17799 | |
|---|---|---|
| 190 | 190 | |
| 191 | 191 | void exp85_state::machine_start() |
| 192 | 192 | { |
| 193 | address_space *program = m_maincpu-> | |
| 193 | address_space *program = m_maincpu-> | |
| 194 | 194 | |
| 195 | 195 | /* setup memory banking */ |
| 196 | 196 | program->install_read_bank(0x0000, 0x07ff, "bank1"); |
| r17798 | r17799 | |
|---|---|---|
| 617 | 617 | |
| 618 | 618 | void m5_state::machine_start() |
| 619 | 619 | { |
| 620 | address_space *program = m_maincpu-> | |
| 620 | address_space *program = m_maincpu-> | |
| 621 | 621 | |
| 622 | 622 | // configure RAM |
| 623 | 623 | switch (m_ram->size()) |
| r17798 | r17799 | |
|---|---|---|
| 220 | 220 | |
| 221 | 221 | WRITE8_MEMBER( a5105_state::a5105_memsel_w ) |
| 222 | 222 | { |
| 223 | address_space *prog = m_maincpu-> | |
| 223 | address_space *prog = m_maincpu-> | |
| 224 | 224 | |
| 225 | 225 | if (m_memsel[0] != ((data & 0x03) >> 0)) |
| 226 | 226 | { |
| r17798 | r17799 | |
| 455 | 455 | |
| 456 | 456 | MACHINE_RESET_MEMBER(a5105_state) |
| 457 | 457 | { |
| 458 | address_space *space = m_maincpu-> | |
| 458 | address_space *space = m_maincpu-> | |
| 459 | 459 | a5105_ab_w(*space, 0, 9); // turn motor off |
| 460 | 460 | beep_set_frequency(m_beep, 500); |
| 461 | 461 |
| r17798 | r17799 | |
|---|---|---|
| 51 | 51 | |
| 52 | 52 | void bw12_state::bankswitch() |
| 53 | 53 | { |
| 54 | address_space *program = m_maincpu-> | |
| 54 | address_space *program = m_maincpu-> | |
| 55 | 55 | |
| 56 | 56 | switch (m_bank) |
| 57 | 57 | { |
| r17798 | r17799 | |
|---|---|---|
| 120 | 120 | |
| 121 | 121 | WRITE8_MEMBER( prestige_state::bankswitch_w ) |
| 122 | 122 | { |
| 123 | address_space *program = m_maincpu-> | |
| 123 | address_space *program = m_maincpu-> | |
| 124 | 124 | |
| 125 | 125 | switch (offset) |
| 126 | 126 | { |
| r17798 | r17799 | |
|---|---|---|
| 67 | 67 | // install read bank |
| 68 | 68 | if (m_bank_type[bank] != Z88_BANK_ROM) |
| 69 | 69 | { |
| 70 | m_maincpu->memory().space(AS_PROGRAM)->install_read_bank(bank<<14, (bank<<14) + 0x3fff, bank_tag); | |
| 71 | m_maincpu->memory().space(AS_PROGRAM)->unmap_write(bank<<14, (bank<<14) + 0x3fff); | |
| 70 | m_maincpu->space(AS_PROGRAM)->install_read_bank(bank<<14, (bank<<14) + 0x3fff, bank_tag); | |
| 71 | m_maincpu->space(AS_PROGRAM)->unmap_write(bank<<14, (bank<<14) + 0x3fff); | |
| 72 | 72 | m_bank_type[bank] = Z88_BANK_ROM; |
| 73 | 73 | } |
| 74 | 74 | |
| r17798 | r17799 | |
| 81 | 81 | // install readwrite bank |
| 82 | 82 | if (m_bank_type[bank] != Z88_BANK_RAM) |
| 83 | 83 | { |
| 84 | m_maincpu-> | |
| 84 | m_maincpu-> | |
| 85 | 85 | m_bank_type[bank] = Z88_BANK_RAM; |
| 86 | 86 | } |
| 87 | 87 | |
| r17798 | r17799 | |
| 92 | 92 | { |
| 93 | 93 | if (m_bank_type[bank] != Z88_BANK_UNMAP) |
| 94 | 94 | { |
| 95 | m_maincpu-> | |
| 95 | m_maincpu-> | |
| 96 | 96 | m_bank_type[bank] = Z88_BANK_UNMAP; |
| 97 | 97 | } |
| 98 | 98 | } |
| r17798 | r17799 | |
| 107 | 107 | switch (bank) |
| 108 | 108 | { |
| 109 | 109 | case 0: |
| 110 | m_maincpu-> | |
| 110 | m_maincpu-> | |
| 111 | 111 | break; |
| 112 | 112 | case 1: |
| 113 | m_maincpu-> | |
| 113 | m_maincpu-> | |
| 114 | 114 | break; |
| 115 | 115 | case 2: |
| 116 | m_maincpu-> | |
| 116 | m_maincpu-> | |
| 117 | 117 | break; |
| 118 | 118 | case 3: |
| 119 | m_maincpu-> | |
| 119 | m_maincpu-> | |
| 120 | 120 | break; |
| 121 | 121 | } |
| 122 | 122 | |
| r17798 | r17799 | |
| 128 | 128 | // override setting for lower 8k of bank 0 |
| 129 | 129 | if (bank == 0) |
| 130 | 130 | { |
| 131 | m_maincpu-> | |
| 131 | m_maincpu-> | |
| 132 | 132 | |
| 133 | 133 | // enable RAM |
| 134 | 134 | if (rams) |
| 135 | m_maincpu-> | |
| 135 | m_maincpu-> | |
| 136 | 136 | else |
| 137 | m_maincpu-> | |
| 137 | m_maincpu-> | |
| 138 | 138 | |
| 139 | 139 | membank("bank1")->set_entry(rams & 1); |
| 140 | 140 | } |
| r17798 | r17799 | |
|---|---|---|
| 337 | 337 | // set to 1 after boot for restore the ram in the first bank |
| 338 | 338 | if (data & 0x01) |
| 339 | 339 | { |
| 340 | address_space *space_prg = m_maincpu-> | |
| 340 | address_space *space_prg = m_maincpu-> | |
| 341 | 341 | space_prg->install_write_bank(0x0000, 0x3fff, "bank1"); |
| 342 | 342 | membank("bank1")->set_entry(0); |
| 343 | 343 | } |
| r17798 | r17799 | |
| 469 | 469 | |
| 470 | 470 | WRITE8_MEMBER( pcg850v_state::g850v_bank_w ) |
| 471 | 471 | { |
| 472 | address_space *space_prg = m_maincpu-> | |
| 472 | address_space *space_prg = m_maincpu-> | |
| 473 | 473 | |
| 474 | 474 | if (data < 0x16) |
| 475 | 475 | { |
| r17798 | r17799 | |
| 872 | 872 | |
| 873 | 873 | void pce220_state::machine_reset() |
| 874 | 874 | { |
| 875 | address_space *space = m_maincpu-> | |
| 875 | address_space *space = m_maincpu-> | |
| 876 | 876 | space->unmap_write(0x0000, 0x3fff); |
| 877 | 877 | |
| 878 | 878 | // install the boot code into the first bank |
| r17798 | r17799 | |
|---|---|---|
| 154 | 154 | //we're in disabled debug_printf |
| 155 | 155 | unsigned char* buf = (unsigned char *)alloca(200); |
| 156 | 156 | unsigned char temp; |
| 157 | address_space *program = m_maincpu-> | |
| 157 | address_space *program = m_maincpu-> | |
| 158 | 158 | |
| 159 | 159 | memset(buf,0,200); |
| 160 | 160 |
| r17798 | r17799 | |
|---|---|---|
| 304 | 304 | dma_slot &ds = dma_slots[slot]; |
| 305 | 305 | ds.drq = state; |
| 306 | 306 | if(state && (ds.state & DMA_ENABLE)) { |
| 307 | address_space *space = maincpu-> | |
| 307 | address_space *space = maincpu-> | |
| 308 | 308 | if(ds.state & DMA_READ) { |
| 309 | 309 | while(ds.drq) { |
| 310 | 310 | dma_check_update(slot); |
| r17798 | r17799 | |
|---|---|---|
| 48 | 48 | |
| 49 | 49 | void prof80_state::bankswitch() |
| 50 | 50 | { |
| 51 | address_space *program = m_maincpu-> | |
| 51 | address_space *program = m_maincpu-> | |
| 52 | 52 | UINT8 *ram = m_ram->pointer(); |
| 53 | 53 | UINT8 *rom = memregion(Z80_TAG)->base(); |
| 54 | 54 | int bank; |
| r17798 | r17799 | |
|---|---|---|
| 75 | 75 | static MC6845_UPDATE_ROW( victor9k_update_row ) |
| 76 | 76 | { |
| 77 | 77 | victor9k_state *state = device->machine().driver_data<victor9k_state>(); |
| 78 | address_space *program = state->m_maincpu-> | |
| 78 | address_space *program = state->m_maincpu-> | |
| 79 | 79 | const rgb_t *palette = palette_entry_list_raw(bitmap.palette()); |
| 80 | 80 | |
| 81 | 81 | if (BIT(ma, 13)) |
| r17798 | r17799 | |
| 926 | 926 | device_set_irq_callback(m_maincpu, victor9k_irq_callback); |
| 927 | 927 | |
| 928 | 928 | // memory banking |
| 929 | address_space *program = m_maincpu-> | |
| 929 | address_space *program = m_maincpu-> | |
| 930 | 930 | program->install_ram(0x00000, m_ram->size() - 1, m_ram->pointer()); |
| 931 | 931 | } |
| 932 | 932 |
| r17798 | r17799 | |
|---|---|---|
| 448 | 448 | |
| 449 | 449 | READ8_MEMBER( pc8001_state::dma_io_r ) |
| 450 | 450 | { |
| 451 | address_space *program = m_maincpu-> | |
| 451 | address_space *program = m_maincpu-> | |
| 452 | 452 | |
| 453 | 453 | return program->read_byte(offset); |
| 454 | 454 | } |
| 455 | 455 | |
| 456 | 456 | WRITE8_MEMBER( pc8001_state::dma_io_w ) |
| 457 | 457 | { |
| 458 | address_space *program = m_maincpu-> | |
| 458 | address_space *program = m_maincpu-> | |
| 459 | 459 | |
| 460 | 460 | program->write_byte(offset, data); |
| 461 | 461 | } |
| r17798 | r17799 | |
| 483 | 483 | |
| 484 | 484 | void pc8001_state::machine_start() |
| 485 | 485 | { |
| 486 | address_space *program = m_maincpu-> | |
| 486 | address_space *program = m_maincpu-> | |
| 487 | 487 | |
| 488 | 488 | /* initialize RTC */ |
| 489 | 489 | m_rtc->cs_w(1); |
| r17798 | r17799 | |
|---|---|---|
| 51 | 51 | |
| 52 | 52 | */ |
| 53 | 53 | |
| 54 | address_space *program = m_maincpu-> | |
| 54 | address_space *program = m_maincpu-> | |
| 55 | 55 | |
| 56 | 56 | int max_ram_bank = 0; |
| 57 | 57 | |
| r17798 | r17799 | |
| 133 | 133 | |
| 134 | 134 | */ |
| 135 | 135 | |
| 136 | address_space *program = m_maincpu-> | |
| 136 | address_space *program = m_maincpu-> | |
| 137 | 137 | |
| 138 | 138 | int max_ram_bank = BANK_RAM1; |
| 139 | 139 | |
| r17798 | r17799 | |
| 200 | 200 | |
| 201 | 201 | WRITE8_MEMBER( bw2_state::ramcard_bank_w ) |
| 202 | 202 | { |
| 203 | address_space *program = m_maincpu-> | |
| 203 | address_space *program = m_maincpu-> | |
| 204 | 204 | |
| 205 | 205 | UINT8 ramcard_bank = data & 0x0f; |
| 206 | 206 | UINT32 bank_offset = ramcard_bank * 0x8000; |
| r17798 | r17799 | |
|---|---|---|
| 438 | 438 | |
| 439 | 439 | WRITE8_MEMBER( portfolio_state::ncc1_w ) |
| 440 | 440 | { |
| 441 | address_space *program = m_maincpu-> | |
| 441 | address_space *program = m_maincpu-> | |
| 442 | 442 | |
| 443 | 443 | if (BIT(data, 0)) |
| 444 | 444 | { |
| r17798 | r17799 | |
| 763 | 763 | |
| 764 | 764 | void portfolio_state::machine_start() |
| 765 | 765 | { |
| 766 | address_space *program = m_maincpu-> | |
| 766 | address_space *program = m_maincpu-> | |
| 767 | 767 | |
| 768 | 768 | /* set CPU interrupt vector callback */ |
| 769 | 769 | device_set_irq_callback(m_maincpu, portfolio_int_ack); |
| r17798 | r17799 | |
| 801 | 801 | |
| 802 | 802 | void portfolio_state::machine_reset() |
| 803 | 803 | { |
| 804 | address_space *io = m_maincpu-> | |
| 804 | address_space *io = m_maincpu-> | |
| 805 | 805 | |
| 806 | 806 | // peripherals |
| 807 | 807 | m_pid = ioport("PERIPHERAL")->read(); |
| r17798 | r17799 | |
|---|---|---|
| 123 | 123 | |
| 124 | 124 | void atom_state::bankswitch() |
| 125 | 125 | { |
| 126 | address_space *program = m_maincpu-> | |
| 126 | address_space *program = m_maincpu-> | |
| 127 | 127 | |
| 128 | 128 | UINT8 *eprom = memregion(EXTROM_TAG)->base() + (m_eprom << 12); |
| 129 | 129 | |
| r17798 | r17799 | |
| 648 | 648 | generator. I don't know if this is hardware, or random data because the |
| 649 | 649 | ram chips are not cleared at start-up. So at this time, these numbers |
| 650 | 650 | are poked into the memory to simulate it. When I have more details I will fix it */ |
| 651 | UINT8 *m_baseram = (UINT8 *)m_maincpu-> | |
| 651 | UINT8 *m_baseram = (UINT8 *)m_maincpu-> | |
| 652 | 652 | |
| 653 | 653 | m_baseram[0x08] = machine().rand() & 0x0ff; |
| 654 | 654 | m_baseram[0x09] = machine().rand() & 0x0ff; |
| r17798 | r17799 | |
|---|---|---|
| 256 | 256 | |
| 257 | 257 | DRIVER_INIT_MEMBER(apricot_state,apricot) |
| 258 | 258 | { |
| 259 | address_space *prg = m_maincpu-> | |
| 259 | address_space *prg = m_maincpu-> | |
| 260 | 260 | |
| 261 | 261 | UINT8 *ram = m_ram->pointer(); |
| 262 | 262 | UINT32 ram_size = m_ram->size(); |
| r17798 | r17799 | |
|---|---|---|
| 296 | 296 | |
| 297 | 297 | void lc80_state::machine_start() |
| 298 | 298 | { |
| 299 | address_space *program = m_maincpu-> | |
| 299 | address_space *program = m_maincpu-> | |
| 300 | 300 | |
| 301 | 301 | /* setup memory banking */ |
| 302 | 302 | membank("bank1")->configure_entry(0, memregion(Z80_TAG)->base()); // TODO |
| r17798 | r17799 | |
|---|---|---|
| 990 | 990 | { |
| 991 | 991 | acan_dma_regs_t *acan_dma_regs = &m_acan_dma_regs; |
| 992 | 992 | int ch = (offset < 0x10/2) ? 0 : 1; |
| 993 | address_space *mem = m_maincpu-> | |
| 993 | address_space *mem = m_maincpu-> | |
| 994 | 994 | |
| 995 | 995 | switch(offset) |
| 996 | 996 | { |
| r17798 | r17799 | |
| 1125 | 1125 | |
| 1126 | 1126 | READ8_MEMBER( supracan_state::supracan_6502_soundmem_r ) |
| 1127 | 1127 | { |
| 1128 | address_space *mem = m_maincpu-> | |
| 1128 | address_space *mem = m_maincpu-> | |
| 1129 | 1129 | UINT8 data = m_soundram[offset]; |
| 1130 | 1130 | |
| 1131 | 1131 | switch(offset) |
| r17798 | r17799 | |
| 1354 | 1354 | |
| 1355 | 1355 | WRITE16_MEMBER( supracan_state::supracan_68k_soundram_w ) |
| 1356 | 1356 | { |
| 1357 | address_space *mem = m_maincpu-> | |
| 1357 | address_space *mem = m_maincpu-> | |
| 1358 | 1358 | m_soundram[offset*2 + 1] = data & 0xff; |
| 1359 | 1359 | m_soundram[offset*2 + 0] = data >> 8; |
| 1360 | 1360 | |
| r17798 | r17799 | |
| 1377 | 1377 | |
| 1378 | 1378 | READ16_MEMBER( supracan_state::supracan_68k_soundram_r ) |
| 1379 | 1379 | { |
| 1380 | address_space *mem = m_maincpu-> | |
| 1380 | address_space *mem = m_maincpu-> | |
| 1381 | 1381 | UINT16 val = m_soundram[offset*2 + 0] << 8; |
| 1382 | 1382 | val |= m_soundram[offset*2 + 1]; |
| 1383 | 1383 | |
| r17798 | r17799 | |
| 1451 | 1451 | |
| 1452 | 1452 | READ16_MEMBER( supracan_state::supracan_video_r ) |
| 1453 | 1453 | { |
| 1454 | address_space *mem = m_maincpu-> | |
| 1454 | address_space *mem = m_maincpu-> | |
| 1455 | 1455 | UINT16 data = m_video_regs[offset]; |
| 1456 | 1456 | |
| 1457 | 1457 | switch(offset) |
| r17798 | r17799 | |
| 1554 | 1554 | |
| 1555 | 1555 | WRITE16_MEMBER( supracan_state::supracan_video_w ) |
| 1556 | 1556 | { |
| 1557 | address_space *mem = m_maincpu-> | |
| 1557 | address_space *mem = m_maincpu-> | |
| 1558 | 1558 | acan_sprdma_regs_t *acan_sprdma_regs = &m_acan_sprdma_regs; |
| 1559 | 1559 | int i; |
| 1560 | 1560 |
| r17798 | r17799 | |
|---|---|---|
| 117 | 117 | |
| 118 | 118 | void tek4051_state::bankswitch(UINT8 data) |
| 119 | 119 | { |
| 120 | address_space *program = m_maincpu-> | |
| 120 | address_space *program = m_maincpu-> | |
| 121 | 121 | |
| 122 | 122 | //int d = data & 0x07; |
| 123 | 123 | int lbs = (data >> 3) & 0x07; |
| r17798 | r17799 | |
| 1167 | 1167 | |
| 1168 | 1168 | void tek4051_state::machine_start() |
| 1169 | 1169 | { |
| 1170 | address_space *program = m_maincpu-> | |
| 1170 | address_space *program = m_maincpu-> | |
| 1171 | 1171 | |
| 1172 | 1172 | // configure RAM |
| 1173 | 1173 | switch (m_ram->size()) |
| r17798 | r17799 | |
|---|---|---|
| 32 | 32 | |
| 33 | 33 | UINT32 f1_state::screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect) |
| 34 | 34 | { |
| 35 | address_space *program = m_maincpu-> | |
| 35 | address_space *program = m_maincpu-> | |
| 36 | 36 | int lines = m_200_256 ? 200 : 256; |
| 37 | 37 | |
| 38 | 38 | for (int y = 0; y < lines; y++) |
| r17798 | r17799 | |
|---|---|---|
| 173 | 173 | |
| 174 | 174 | void mstation_state::refresh_memory(UINT8 bank, UINT8 chip_select) |
| 175 | 175 | { |
| 176 | address_space* program = m_maincpu-> | |
| 176 | address_space* program = m_maincpu-> | |
| 177 | 177 | int &active_flash = (bank == 1 ? m_flash_at_0x4000 : m_flash_at_0x8000); |
| 178 | 178 | char bank_tag[6]; |
| 179 | 179 |
| r17798 | r17799 | |
|---|---|---|
| 67 | 67 | |
| 68 | 68 | READ8_MEMBER(pcfx_state::extio_r) |
| 69 | 69 | { |
| 70 | address_space *io_space = m_maincpu-> | |
| 70 | address_space *io_space = m_maincpu-> | |
| 71 | 71 | |
| 72 | 72 | return io_space->read_byte(offset); |
| 73 | 73 | } |
| 74 | 74 | |
| 75 | 75 | WRITE8_MEMBER(pcfx_state::extio_w) |
| 76 | 76 | { |
| 77 | address_space *io_space = m_maincpu-> | |
| 77 | address_space *io_space = m_maincpu-> | |
| 78 | 78 | |
| 79 | 79 | io_space->write_byte(offset, data); |
| 80 | 80 | } |
| r17798 | r17799 | |
|---|---|---|
| 158 | 158 | |
| 159 | 159 | void avigo_state::refresh_memory(UINT8 bank, UINT8 chip_select) |
| 160 | 160 | { |
| 161 | address_space* space = m_maincpu-> | |
| 161 | address_space* space = m_maincpu-> | |
| 162 | 162 | int &active_flash = (bank == 1 ? m_flash_at_0x4000 : m_flash_at_0x8000); |
| 163 | 163 | char bank_tag[6]; |
| 164 | 164 | |
| r17798 | r17799 | |
| 830 | 830 | static QUICKLOAD_LOAD(avigo) |
| 831 | 831 | { |
| 832 | 832 | avigo_state *state = image.device().machine().driver_data<avigo_state>(); |
| 833 | address_space* flash1 = state->m_flashes[1]-> | |
| 833 | address_space* flash1 = state->m_flashes[1]-> | |
| 834 | 834 | const char *systemname = image.device().machine().system().name; |
| 835 | 835 | UINT32 first_app_page = (0x50000>>14); |
| 836 | 836 | int app_page; |
| r17798 | r17799 | |
|---|---|---|
| 30 | 30 | |
| 31 | 31 | void super6_state::bankswitch() |
| 32 | 32 | { |
| 33 | address_space *program = m_maincpu-> | |
| 33 | address_space *program = m_maincpu-> | |
| 34 | 34 | UINT8 *ram = m_ram->pointer(); |
| 35 | 35 | UINT8 *rom = memregion(Z80_TAG)->base(); |
| 36 | 36 |
| r17798 | r17799 | |
|---|---|---|
| 849 | 849 | |
| 850 | 850 | READ8_MEMBER( c64_state::exp_dma_r ) |
| 851 | 851 | { |
| 852 | return m_maincpu-> | |
| 852 | return m_maincpu-> | |
| 853 | 853 | } |
| 854 | 854 | |
| 855 | 855 | WRITE8_MEMBER( c64_state::exp_dma_w ) |
| 856 | 856 | { |
| 857 | m_maincpu-> | |
| 857 | m_maincpu-> | |
| 858 | 858 | } |
| 859 | 859 | |
| 860 | 860 | WRITE_LINE_MEMBER( c64_state::exp_irq_w ) |
| r17798 | r17799 | |
|---|---|---|
| 143 | 143 | |
| 144 | 144 | void xerox820_state::bankswitch(int bank) |
| 145 | 145 | { |
| 146 | address_space *program = m_maincpu-> | |
| 146 | address_space *program = m_maincpu-> | |
| 147 | 147 | UINT8 *ram = m_ram->pointer(); |
| 148 | 148 | |
| 149 | 149 | if (bank) |
| r17798 | r17799 | |
| 162 | 162 | |
| 163 | 163 | void xerox820ii_state::bankswitch(int bank) |
| 164 | 164 | { |
| 165 | address_space *program = m_maincpu-> | |
| 165 | address_space *program = m_maincpu-> | |
| 166 | 166 | UINT8 *ram = m_ram->pointer(); |
| 167 | 167 | |
| 168 | 168 | if (bank) |
| r17798 | r17799 | |
|---|---|---|
| 164 | 164 | if (data < 2) |
| 165 | 165 | { |
| 166 | 166 | membank("bank1")->set_entry(data); |
| 167 | m_maincpu-> | |
| 167 | m_maincpu-> | |
| 168 | 168 | } |
| 169 | 169 | else |
| 170 | 170 | { |
| 171 | 171 | membank("bank1")->set_entry((data <= m_banks_num) ? data : m_banks_num); |
| 172 | m_maincpu-> | |
| 172 | m_maincpu-> | |
| 173 | 173 | } |
| 174 | 174 | } |
| 175 | 175 | |
| r17798 | r17799 | |
| 342 | 342 | void micronic_state::machine_reset() |
| 343 | 343 | { |
| 344 | 344 | membank("bank1")->set_entry(0); |
| 345 | m_maincpu-> | |
| 345 | m_maincpu-> | |
| 346 | 346 | } |
| 347 | 347 | |
| 348 | 348 |
| r17798 | r17799 | |
|---|---|---|
| 252 | 252 | |
| 253 | 253 | void cosmicos_state::set_ram_mode() |
| 254 | 254 | { |
| 255 | address_space *program = m_maincpu-> | |
| 255 | address_space *program = m_maincpu-> | |
| 256 | 256 | UINT8 *ram = m_ram->pointer(); |
| 257 | 257 | |
| 258 | 258 | if (m_ram_disable) |
| r17798 | r17799 | |
| 486 | 486 | |
| 487 | 487 | void cosmicos_state::machine_start() |
| 488 | 488 | { |
| 489 | address_space *program = m_maincpu-> | |
| 489 | address_space *program = m_maincpu-> | |
| 490 | 490 | |
| 491 | 491 | /* initialize LED display */ |
| 492 | 492 | m_led->rbi_w(1); |
| r17798 | r17799 | |
|---|---|---|
| 124 | 124 | |
| 125 | 125 | READ8_MEMBER( vic10_state::vic_videoram_r ) |
| 126 | 126 | { |
| 127 | address_space *program = m_maincpu-> | |
| 127 | address_space *program = m_maincpu-> | |
| 128 | 128 | |
| 129 | 129 | if (offset < 0x3000) |
| 130 | 130 | return program->read_byte(offset); |
| r17798 | r17799 | |
|---|---|---|
| 809 | 809 | |
| 810 | 810 | void vixen_state::machine_reset() |
| 811 | 811 | { |
| 812 | address_space *program = m_maincpu-> | |
| 812 | address_space *program = m_maincpu-> | |
| 813 | 813 | |
| 814 | 814 | program->install_read_bank(0x0000, 0xefff, 0xfff, 0, "bank1"); |
| 815 | 815 | program->install_write_bank(0x0000, 0xefff, 0xfff, 0, "bank2"); |
| r17798 | r17799 | |
| 910 | 910 | { |
| 911 | 911 | if (m_reset) |
| 912 | 912 | { |
| 913 | address_space *program = m_maincpu-> | |
| 913 | address_space *program = m_maincpu-> | |
| 914 | 914 | |
| 915 | 915 | program->install_read_bank(0x0000, 0xefff, "bank1"); |
| 916 | 916 | program->install_write_bank(0x0000, 0xefff, "bank2"); |
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