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r17734 Saturday 8th September, 2012 at 21:27:33 UTC by O. Galibert
(mess) pc hardware: cleanup the end-of-dma notifications [O. Galibert]
[src/emu/machine]8237dma.c am9517a.c
[src/mess/includes]at.h genpc.h
[src/mess/machine]at.c genpc.c isa.c isa.h isa_gus.c southbridge.c southbridge.h

trunk/src/emu/machine/8237dma.c
r17733r17734
127127void i8237_device::device_reset()
128128{
129129   m_status = 0x0F;
130   m_eop = 1;
130   m_eop = ASSERT_LINE;
131131   m_state = DMA8237_SI;
132132   m_last_service_channel = 3;
133133    m_service_channel = 0;
r17733r17734
269269   case DMA8237_SI:
270270   {
271271      /* Make sure EOP is high */
272      if ( !m_eop )
272      if ( m_eop == CLEAR_LINE )
273273      {
274         m_eop = 1;
275         m_out_eop_func(m_eop ? ASSERT_LINE : CLEAR_LINE);
274         m_eop = ASSERT_LINE;
275         m_out_eop_func(m_eop);
276276      }
277277
278278      /* Check if a new DMA request has been received. */
r17733r17734
363363      /* Check if EOP output needs to be asserted  */
364364      if ( m_status & ( 0x01 << m_service_channel ) )
365365      {
366         m_eop = 0;
367         m_out_eop_func(m_eop ? ASSERT_LINE : CLEAR_LINE);
366         m_eop = CLEAR_LINE;
367         m_out_eop_func(m_eop);
368368      }
369369      break;
370370
r17733r17734
413413         {
414414         case DMA8237_DEMAND_MODE:
415415            /* Check for terminal count or EOP signal or DREQ begin de-asserted */
416            if ( ( m_status & ( 0x01 << channel ) ) || !m_eop || !( m_drq & ( 0x01 << channel ) ) )
416            if ( ( m_status & ( 0x01 << channel ) ) || m_eop == CLEAR_LINE || !( m_drq & ( 0x01 << channel ) ) )
417417            {
418418               m_hrq = 0;
419419               m_hlda = 0;
r17733r17734
435435
436436         case DMA8237_BLOCK_MODE:
437437            /* Check for terminal count or EOP signal */
438            if ( ( m_status & ( 0x01 << channel ) ) || !m_eop )
438            if ( ( m_status & ( 0x01 << channel ) ) || m_eop == CLEAR_LINE )
439439            {
440440               m_hrq = 0;
441441               m_hlda = 0;
r17733r17734
452452         /* Check if EOP output needs to be asserted */
453453         if ( m_status & ( 0x01 << channel ) )
454454         {
455            m_eop = 0;
456            m_out_eop_func(m_eop ? ASSERT_LINE : CLEAR_LINE);
455            m_eop = CLEAR_LINE;
456            m_out_eop_func(m_eop);
457457         }
458458      }
459459
trunk/src/emu/machine/am9517a.c
r17733r17734
350350   }
351351
352352   // signal end of process
353   set_eop(0);
353   set_eop(ASSERT_LINE);
354354   set_hreq(0);
355355
356356   m_current_channel = -1;
r17733r17734
454454   m_last_channel = 3;
455455
456456   set_hreq(0);
457   set_eop(1);
457   set_eop(ASSERT_LINE);
458458
459459   set_dack();
460460}
r17733r17734
471471      switch (m_state)
472472      {
473473      case STATE_SI:
474         set_eop(1);
474         set_eop(CLEAR_LINE);
475475
476476         if (!COMMAND_DISABLE)
477477         {
trunk/src/mess/machine/at.c
r17733r17734
163163
164164READ8_MEMBER(at_state::pc_dma_read_byte)
165165{
166   if(m_dma_channel == -1)
167      return 0xff;
166168   UINT8 result;
167169   offs_t page_offset = (((offs_t) m_dma_offset[0][m_dma_channel]) << 16) & 0xFF0000;
168170
r17733r17734
173175
174176WRITE8_MEMBER(at_state::pc_dma_write_byte)
175177{
178   if(m_dma_channel == -1)
179      return;
176180   offs_t page_offset = (((offs_t) m_dma_offset[0][m_dma_channel]) << 16) & 0xFF0000;
177181
178182   space.write_byte(page_offset + offset, data);
r17733r17734
181185
182186READ8_MEMBER(at_state::pc_dma_read_word)
183187{
188   if(m_dma_channel == -1)
189      return 0xff;
184190   UINT16 result;
185191   offs_t page_offset = (((offs_t) m_dma_offset[1][m_dma_channel & 3]) << 16) & 0xFE0000;
186192
r17733r17734
193199
194200WRITE8_MEMBER(at_state::pc_dma_write_word)
195201{
202   if(m_dma_channel == -1)
203      return;
196204   offs_t page_offset = (((offs_t) m_dma_offset[1][m_dma_channel & 3]) << 16) & 0xFE0000;
197205
198206   space.write_word(page_offset + ( offset << 1 ), m_dma_high_byte | data);
r17733r17734
215223WRITE8_MEMBER( at_state::pc_dma8237_6_dack_w ){ m_isabus->dack16_w(6, m_dma_high_byte | data); }
216224WRITE8_MEMBER( at_state::pc_dma8237_7_dack_w ){ m_isabus->dack16_w(7, m_dma_high_byte | data); }
217225
218WRITE_LINE_MEMBER( at_state::at_dma8237_out_eop ) { m_isabus->eop_w(state == ASSERT_LINE ? 0 : 1 ); }
226WRITE_LINE_MEMBER( at_state::at_dma8237_out_eop )
227{
228   m_cur_eop = state == ASSERT_LINE;
229   if(m_dma_channel != -1)
230      m_isabus->eop_w(m_dma_channel, ASSERT_LINE );
231}
219232
220static void set_dma_channel(device_t *device, int channel, int state)
233void at_state::pc_set_dma_channel(int channel, int state)
221234{
222   at_state *st = device->machine().driver_data<at_state>();
223   if (!state)
224      st->m_dma_channel = channel;
235   if(!state) {
236      m_dma_channel = channel;
237      if(m_cur_eop)
238         m_isabus->eop_w(channel, ASSERT_LINE );
239
240   } else if(m_dma_channel == channel) {
241      m_dma_channel = -1;
242      if(m_cur_eop)
243         m_isabus->eop_w(channel, CLEAR_LINE );
244   }
225245}
226246
227WRITE_LINE_MEMBER( at_state::pc_dack0_w ) { set_dma_channel(m_dma8237_1, 0, state); }
228WRITE_LINE_MEMBER( at_state::pc_dack1_w ) { set_dma_channel(m_dma8237_1, 1, state); }
229WRITE_LINE_MEMBER( at_state::pc_dack2_w ) { set_dma_channel(m_dma8237_1, 2, state); }
230WRITE_LINE_MEMBER( at_state::pc_dack3_w ) { set_dma_channel(m_dma8237_1, 3, state); }
247WRITE_LINE_MEMBER( at_state::pc_dack0_w ) { pc_set_dma_channel(0, state); }
248WRITE_LINE_MEMBER( at_state::pc_dack1_w ) { pc_set_dma_channel(1, state); }
249WRITE_LINE_MEMBER( at_state::pc_dack2_w ) { pc_set_dma_channel(2, state); }
250WRITE_LINE_MEMBER( at_state::pc_dack3_w ) { pc_set_dma_channel(3, state); }
231251WRITE_LINE_MEMBER( at_state::pc_dack4_w ) { m_dma8237_1->hack_w(state ? 0 : 1); } // it's inverted
232WRITE_LINE_MEMBER( at_state::pc_dack5_w ) { set_dma_channel(m_dma8237_2, 5, state); }
233WRITE_LINE_MEMBER( at_state::pc_dack6_w ) { set_dma_channel(m_dma8237_2, 6, state); }
234WRITE_LINE_MEMBER( at_state::pc_dack7_w ) { set_dma_channel(m_dma8237_2, 7, state); }
252WRITE_LINE_MEMBER( at_state::pc_dack5_w ) { pc_set_dma_channel(5, state); }
253WRITE_LINE_MEMBER( at_state::pc_dack6_w ) { pc_set_dma_channel(6, state); }
254WRITE_LINE_MEMBER( at_state::pc_dack7_w ) { pc_set_dma_channel(7, state); }
235255
236256I8237_INTERFACE( at_dma8237_1_config )
237257{
r17733r17734
343363   st->m_poll_delay = 4;
344364   st->m_at_spkrdata = 0;
345365   st->m_at_speaker_input = 0;
366   st->m_dma_channel = -1;
367   st->m_cur_eop = false;
346368}
trunk/src/mess/machine/genpc.c
r17733r17734
6969
7070READ8_MEMBER( ibm5160_mb_device::pc_dma_read_byte )
7171{
72   if(m_dma_channel == -1)
73      return 0xff;
7274   address_space *spaceio = m_maincpu->space(AS_PROGRAM);
7375   offs_t page_offset = (((offs_t) m_dma_offset[m_dma_channel]) << 16) & 0x0F0000;
7476   return spaceio->read_byte( page_offset + offset);
r17733r17734
7779
7880WRITE8_MEMBER( ibm5160_mb_device::pc_dma_write_byte )
7981{
82   if(m_dma_channel == -1)
83      return;
8084   address_space *spaceio = m_maincpu->space(AS_PROGRAM);
8185   offs_t page_offset = (((offs_t) m_dma_offset[m_dma_channel]) << 16) & 0x0F0000;
8286
r17733r17734
127131
128132WRITE_LINE_MEMBER( ibm5160_mb_device::pc_dma8237_out_eop )
129133{
130   return m_isabus->eop_w(state == ASSERT_LINE ? 0 : 1 );
134   m_cur_eop = state == ASSERT_LINE;
135   if(m_dma_channel != -1 && m_cur_eop)
136      m_isabus->eop_w(m_dma_channel, m_cur_eop ? ASSERT_LINE : CLEAR_LINE );
131137}
132138
133WRITE_LINE_MEMBER( ibm5160_mb_device::pc_dack0_w ) { if (!state) m_dma_channel = 0; }
134WRITE_LINE_MEMBER( ibm5160_mb_device::pc_dack1_w ) { if (!state) m_dma_channel = 1; }
135WRITE_LINE_MEMBER( ibm5160_mb_device::pc_dack2_w ) { if (!state) m_dma_channel = 2; }
136WRITE_LINE_MEMBER( ibm5160_mb_device::pc_dack3_w ) { if (!state) m_dma_channel = 3; }
139void ibm5160_mb_device::pc_select_dma_channel(int channel, bool state)
140{
141   if(!state) {
142      m_dma_channel = channel;
143      if(m_cur_eop)
144         m_isabus->eop_w(channel, ASSERT_LINE );
137145
146   } else if(m_dma_channel == channel) {
147      m_dma_channel = -1;
148      if(m_cur_eop)
149         m_isabus->eop_w(channel, CLEAR_LINE );
150   }
151}
152
153WRITE_LINE_MEMBER( ibm5160_mb_device::pc_dack0_w ) { pc_select_dma_channel(0, state); }
154WRITE_LINE_MEMBER( ibm5160_mb_device::pc_dack1_w ) { pc_select_dma_channel(1, state); }
155WRITE_LINE_MEMBER( ibm5160_mb_device::pc_dack2_w ) { pc_select_dma_channel(2, state); }
156WRITE_LINE_MEMBER( ibm5160_mb_device::pc_dack3_w ) { pc_select_dma_channel(3, state); }
157
138158I8237_INTERFACE( pc_dma8237_config )
139159{
140160   DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER, ibm5160_mb_device, pc_dma_hrq_changed),
r17733r17734
651671   m_out1 = 2; // initial state of pit output is undefined
652672   m_pc_spkrdata = 0;
653673   m_pc_input = 0;
654   m_dma_channel = 0;
674   m_dma_channel = -1;
675   m_cur_eop = false;
655676   memset(m_dma_offset,0,sizeof(m_dma_offset));
656677   m_ppi_portc_switch_high = 0;
657678   m_ppi_speaker = 0;
trunk/src/mess/machine/isa_gus.c
r17733r17734
11811181
11821182void gf1_device::eop_w(int state)
11831183{
1184   // end of transfer
1185   m_dmatimer->reset();
1186   //m_drq1(0);
1187   if(m_dma_dram_ctrl & 0x20)
1188   {
1189      m_dma_dram_ctrl |= 0x40;
1190      m_dma_irq_func(1);
1184   if(state == ASSERT_LINE) {
1185      // end of transfer
1186      m_dmatimer->reset();
1187      //m_drq1(0);
1188      if(m_dma_dram_ctrl & 0x20)
1189      {
1190         m_dma_dram_ctrl |= 0x40;
1191         m_dma_irq_func(1);
1192      }
1193      logerror("GUS: End of transfer. (%05x)\n",m_dma_current);
11911194   }
1192   logerror("GUS: End of transfer. (%05x)\n",m_dma_current);
11931195}
11941196
11951197
trunk/src/mess/machine/isa.c
r17733r17734
394394      return m_dma_device[line]->dack_w(line,data);
395395}
396396
397void isa8_device::eop_w(int state)
397void isa8_device::eop_w(int channel, int state)
398398{
399   for (int i=0;i<8;i++) {
400      if (m_dma_eop[i]==TRUE && m_dma_device[i])
401         m_dma_device[i]->eop_w(state);
402   }
399   if (m_dma_eop[channel] && m_dma_device[channel])
400      m_dma_device[channel]->eop_w(state);
403401}
404402
405403void isa8_device::nmi()
trunk/src/mess/machine/isa.h
r17733r17734
173173
174174   UINT8 dack_r(int line);
175175   void dack_w(int line,UINT8 data);
176   void eop_w(int state);
176   void eop_w(int channels, int state);
177177
178178   void nmi();
179179   void set_nmi_state(bool enabled) { m_nmi_enabled = enabled; }
trunk/src/mess/machine/southbridge.c
r17733r17734
221221   m_poll_delay = 4;
222222   m_at_spkrdata = 0;
223223   m_at_speaker_input = 0;
224   m_dma_channel = -1;
225   m_cur_eop = false;
224226}
225227
226228
r17733r17734
336338
337339READ8_MEMBER(southbridge_device::pc_dma_read_byte)
338340{
341   if(m_dma_channel == -1)
342      return 0xff;
339343   UINT8 result;
340344   offs_t page_offset = (((offs_t) m_dma_offset[0][m_dma_channel]) << 16) & 0xFF0000;
341345
r17733r17734
346350
347351WRITE8_MEMBER(southbridge_device::pc_dma_write_byte)
348352{
353   if(m_dma_channel == -1)
354      return;
349355   offs_t page_offset = (((offs_t) m_dma_offset[0][m_dma_channel]) << 16) & 0xFF0000;
350356
351357   space.write_byte(page_offset + offset, data);
r17733r17734
354360
355361READ8_MEMBER(southbridge_device::pc_dma_read_word)
356362{
363   if(m_dma_channel == -1)
364      return 0xff;
357365   UINT16 result;
358366   offs_t page_offset = (((offs_t) m_dma_offset[1][m_dma_channel & 3]) << 16) & 0xFF0000;
359367
r17733r17734
366374
367375WRITE8_MEMBER(southbridge_device::pc_dma_write_word)
368376{
377   if(m_dma_channel == -1)
378      return;
369379   offs_t page_offset = (((offs_t) m_dma_offset[1][m_dma_channel & 3]) << 16) & 0xFF0000;
370380
371381   space.write_word(page_offset + ( offset << 1 ), m_dma_high_byte | data);
r17733r17734
389399WRITE8_MEMBER( southbridge_device::pc_dma8237_6_dack_w ){ m_isabus->dack_w(6, data); }
390400WRITE8_MEMBER( southbridge_device::pc_dma8237_7_dack_w ){ m_isabus->dack_w(7, data); }
391401
392WRITE_LINE_MEMBER( southbridge_device::at_dma8237_out_eop ) { m_isabus->eop_w(state == ASSERT_LINE ? 0 : 1 ); }
402WRITE_LINE_MEMBER( southbridge_device::at_dma8237_out_eop )
403{
404   m_cur_eop = state == ASSERT_LINE;
405   if(m_dma_channel != -1)
406      m_isabus->eop_w(m_dma_channel, ASSERT_LINE );
407}
393408
394WRITE_LINE_MEMBER( southbridge_device::pc_dack0_w ) { if (!state) m_dma_channel = 0; }
395WRITE_LINE_MEMBER( southbridge_device::pc_dack1_w ) { if (!state) m_dma_channel = 1; }
396WRITE_LINE_MEMBER( southbridge_device::pc_dack2_w ) { if (!state) m_dma_channel = 2; }
397WRITE_LINE_MEMBER( southbridge_device::pc_dack3_w ) { if (!state) m_dma_channel = 3; }
409void southbridge_device::pc_select_dma_channel(int channel, bool state)
410{
411   if(!state) {
412      m_dma_channel = channel;
413      if(m_cur_eop)
414         m_isabus->eop_w(channel, ASSERT_LINE );
415
416   } else if(m_dma_channel == channel) {
417      m_dma_channel = -1;
418      if(m_cur_eop)
419         m_isabus->eop_w(channel, CLEAR_LINE );
420   }
421}
422
423
424WRITE_LINE_MEMBER( southbridge_device::pc_dack0_w ) { pc_select_dma_channel(0, state); }
425WRITE_LINE_MEMBER( southbridge_device::pc_dack1_w ) { pc_select_dma_channel(1, state); }
426WRITE_LINE_MEMBER( southbridge_device::pc_dack2_w ) { pc_select_dma_channel(2, state); }
427WRITE_LINE_MEMBER( southbridge_device::pc_dack3_w ) { pc_select_dma_channel(3, state); }
398428WRITE_LINE_MEMBER( southbridge_device::pc_dack4_w ) { i8237_hlda_w( m_dma8237_1, state ? 0 : 1); } // it's inverted
399WRITE_LINE_MEMBER( southbridge_device::pc_dack5_w ) { if (!state) m_dma_channel = 5; }
400WRITE_LINE_MEMBER( southbridge_device::pc_dack6_w ) { if (!state) m_dma_channel = 6; }
401WRITE_LINE_MEMBER( southbridge_device::pc_dack7_w ) { if (!state) m_dma_channel = 7; }
429WRITE_LINE_MEMBER( southbridge_device::pc_dack5_w ) { pc_select_dma_channel(5, state); }
430WRITE_LINE_MEMBER( southbridge_device::pc_dack6_w ) { pc_select_dma_channel(6, state); }
431WRITE_LINE_MEMBER( southbridge_device::pc_dack7_w ) { pc_select_dma_channel(7, state); }
402432
403433READ8_MEMBER( southbridge_device::at_portb_r )
404434{
trunk/src/mess/machine/southbridge.h
r17733r17734
132132      UINT8 m_at_spkrdata;
133133      UINT8 m_at_speaker_input;
134134      int m_dma_channel;
135      bool m_cur_eop;
135136      UINT8 m_dma_offset[2][4];
136137      UINT8 m_at_pages[0x10];
137138      UINT16 m_dma_high_byte;
r17733r17734
142143
143144      UINT8 m_channel_check;
144145      UINT8 m_nmi_enabled;
146
147      void pc_select_dma_channel(int channel, bool state);
145148};
146149
147150#endif  /* __SOUTHBRIDGE_H__ */
trunk/src/mess/includes/genpc.h
r17733r17734
5656   UINT8 m_dma_offset[4];
5757   UINT8 m_pc_spkrdata;
5858   UINT8 m_pc_input;
59   bool m_cur_eop;
5960
6061   UINT8 m_nmi_enabled;
6162
r17733r17734
102103   DECLARE_WRITE_LINE_MEMBER( pc_speaker_set_spkrdata );
103104
104105   const char *m_cputag;
106
107private:
108   void pc_select_dma_channel(int channel, bool state);
105109};
106110
107111
trunk/src/mess/includes/at.h
r17733r17734
159159   UINT8 m_at_spkrdata;
160160   UINT8 m_at_speaker_input;
161161   int m_dma_channel;
162   bool m_cur_eop;
162163   UINT8 m_dma_offset[2][4];
163164   UINT8 m_at_pages[0x10];
164165   UINT16 m_dma_high_byte;
r17733r17734
176177
177178   DECLARE_DRIVER_INIT(atcga);
178179   DECLARE_DRIVER_INIT(atvga);
180
181   void pc_set_dma_channel(int channel, int state);
179182};
180183
181184

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