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r17733 Saturday 8th September, 2012 at 21:20:54 UTC by Curt Coder
(MESS) c128: Cleanup (nw)

[src/mess/drivers]	c128.c
[src/mess/includes]	c128.h
[src/mess/machine]	c128.c

trunk/src/mess/machine/c128.c

r17732	r17733
21	21	#include "video/mos6566.h"
22	22	#include "video/mc6845.h"
23	23
24		#define MMU_PAGE1 ((((state->m_mmu[10]&0xf)<<8)|state->m_mmu[9])<<8)
25		#define MMU_PAGE0 ((((state->m_mmu[8]&0xf)<<8)|state->m_mmu[7])<<8)
26		#define MMU_VIC_ADDR ((state->m_mmu[6]&0xc0)<<10)
27		#define MMU_RAM_RCR_ADDR ((state->m_mmu[6]&0x30)<<14)
28		#define MMU_SIZE (c128_mmu_helper[state->m_mmu[6]&3])
29		#define MMU_BOTTOM (state->m_mmu[6]&4)
30		#define MMU_TOP (state->m_mmu[6]&8)
31		#define MMU_CPU8502 (state->m_mmu[5]&1)      /* else z80 */
	24	#define MMU_PAGE1 ((((m_mmu[10]&0xf)<<8)|m_mmu[9])<<8)
	25	#define MMU_PAGE0 ((((m_mmu[8]&0xf)<<8)|m_mmu[7])<<8)
	26	#define MMU_VIC_ADDR ((m_mmu[6]&0xc0)<<10)
	27	#define MMU_RAM_RCR_ADDR ((m_mmu[6]&0x30)<<14)
	28	#define MMU_SIZE (c128_mmu_helper[m_mmu[6]&3])
	29	#define MMU_BOTTOM (m_mmu[6]&4)
	30	#define MMU_TOP (m_mmu[6]&8)
	31	#define MMU_CPU8502 (m_mmu[5]&1)      /* else z80 */
32	32	/* fastio output (c128_mmu[5]&8) else input */
33		#define MMU_FSDIR(s) ((s)->m_mmu[5]&0x08)
34		#define MMU_GAME_IN (state->m_mmu[5]&0x10)
35		#define MMU_EXROM_IN (state->m_mmu[5]&0x20)
36		#define MMU_64MODE (state->m_mmu[5]&0x40)
37		#define MMU_40_IN (state->m_mmu[5]&0x80)
	33	#define MMU_FSDIR (m_mmu[5]&0x08)
	34	#define MMU_GAME_IN (m_mmu[5]&0x10)
	35	#define MMU_EXROM_IN (m_mmu[5]&0x20)
	36	#define MMU_64MODE (m_mmu[5]&0x40)
	37	#define MMU_40_IN (m_mmu[5]&0x80)
38	38
39		#define MMU_RAM_CR_ADDR ((state->m_mmu[0]&0xc0)<<10)
40		#define MMU_RAM_LO (state->m_mmu[0]&2)      /* else rom at 0x4000 */
41		#define MMU_RAM_MID ((state->m_mmu[0]&0xc)==0xc)   /* 0x8000 - 0xbfff */
42		#define MMU_ROM_MID ((state->m_mmu[0]&0xc)==0)
43		#define MMU_EXTERNAL_ROM_MID ((state->m_mmu[0]&0xc)==8)
44		#define MMU_INTERNAL_ROM_MID ((state->m_mmu[0]&0xc)==4)
	39	#define MMU_RAM_CR_ADDR ((m_mmu[0]&0xc0)<<10)
	40	#define MMU_RAM_LO (m_mmu[0]&2)      /* else rom at 0x4000 */
	41	#define MMU_RAM_MID ((m_mmu[0]&0xc)==0xc)   /* 0x8000 - 0xbfff */
	42	#define MMU_ROM_MID ((m_mmu[0]&0xc)==0)
	43	#define MMU_EXTERNAL_ROM_MID ((m_mmu[0]&0xc)==8)
	44	#define MMU_INTERNAL_ROM_MID ((m_mmu[0]&0xc)==4)
45	45
46		#define MMU_IO_ON (!(state->m_mmu[0]&1))   /* io window at 0xd000 */
47		#define MMU_ROM_HI ((state->m_mmu[0]&0x30)==0)   /* rom at 0xc000 */
48		#define MMU_EXTERNAL_ROM_HI ((state->m_mmu[0]&0x30)==0x20)
49		#define MMU_INTERNAL_ROM_HI ((state->m_mmu[0]&0x30)==0x10)
50		#define MMU_RAM_HI ((state->m_mmu[0]&0x30)==0x30)
	46	#define MMU_IO_ON (!(m_mmu[0]&1))   /* io window at 0xd000 */
	47	#define MMU_ROM_HI ((m_mmu[0]&0x30)==0)   /* rom at 0xc000 */
	48	#define MMU_EXTERNAL_ROM_HI ((m_mmu[0]&0x30)==0x20)
	49	#define MMU_INTERNAL_ROM_HI ((m_mmu[0]&0x30)==0x10)
	50	#define MMU_RAM_HI ((m_mmu[0]&0x30)==0x30)
51	51
52	52	#define MMU_RAM_ADDR (MMU_RAM_RCR_ADDR|MMU_RAM_CR_ADDR)
53	53
r17732	r17733
88	88
89	89
90	90
91		static void c128_nmi( running_machine &machine )
	91	void c128_state::nmi()
92	92	{
93		c128_state *state = machine.driver_data<c128_state>();
94		device_t *cia_1 = machine.device("cia_1");
95		int cia1irq = mos6526_irq_r(cia_1);
	93	int cia1irq = mos6526_irq_r(m_cia2);
96	94
97		if (state->m_nmilevel != (machine.root_device().ioport("SPECIAL")->read() & 0x80) || cia1irq)   /* KEY_RESTORE */
	95	if (m_nmilevel != (ioport("SPECIAL")->read() & 0x80) || cia1irq)   /* KEY_RESTORE */
98	96	{
99	97	if (1) // this was never valid, there is no active CPU during a timer firing!  cpu_getactivecpu() == 0)
100	98	{
101	99	/* z80 */
102		cputag_set_input_line(machine, "maincpu", INPUT_LINE_NMI, (machine.root_device().ioport("SPECIAL")->read() & 0x80) || cia1irq);
	100	m_maincpu->set_input_line(INPUT_LINE_NMI, (ioport("SPECIAL")->read() & 0x80) || cia1irq);
103	101	}
104	102	else
105	103	{
106		cputag_set_input_line(machine, "m8502", INPUT_LINE_NMI, (machine.root_device().ioport("SPECIAL")->read() & 0x80) || cia1irq);
	104	m_subcpu->set_input_line(INPUT_LINE_NMI, (ioport("SPECIAL")->read() & 0x80) || cia1irq);
107	105	}
108	106
109		state->m_nmilevel = (machine.root_device().ioport("SPECIAL")->read() & 0x80) || cia1irq;
	107	m_nmilevel = (ioport("SPECIAL")->read() & 0x80) || cia1irq;
110	108	}
111	109	}
112	110
r17732	r17733
126	124	*  see machine/cbm.c
127	125	*/
128	126
129		static READ8_DEVICE_HANDLER( c128_cia0_port_a_r )
	127	READ8_MEMBER( c128_state::cia1_pa_r )
130	128	{
131		UINT8 cia0portb = mos6526_pb_r(device->machine().device("cia_0"), 0);
	129	UINT8 cia0portb = mos6526_pb_r(m_cia1, 0);
132	130
133		return cbm_common_cia0_port_a_r(device, cia0portb);
	131	return cbm_common_cia0_port_a_r(m_cia1, cia0portb);
134	132	}
135	133
136		static READ8_DEVICE_HANDLER( c128_cia0_port_b_r )
	134	READ8_MEMBER( c128_state::cia1_pb_r )
137	135	{
138		c128_state *state = device->machine().driver_data<c128_state>();
139	136	UINT8 value = 0xff;
140		UINT8 cia0porta = mos6526_pa_r(device->machine().device("cia_0"), 0);
141		device_t *vic2e = device->machine().device("vic2e");
142		vic2e_device_interface *intf = dynamic_cast<vic2e_device_interface*>(vic2e);
	137	UINT8 cia0porta = mos6526_pa_r(m_cia1, 0);
	138	//vic2e_device_interface *intf = dynamic_cast<vic2e_device_interface*>(&m_vic);
143	139
144		value &= cbm_common_cia0_port_b_r(device, cia0porta);
145
	140	value &= cbm_common_cia0_port_b_r(m_cia1, cia0porta);
	141	/*
146	142	if (!intf->k0_r())
147		value &= state->m_keyline[0];
	143	value &= m_keyline[0];
148	144	if (!intf->k1_r())
149		value &= state->m_keyline[1];
	145	value &= m_keyline[1];
150	146	if (!intf->k2_r())
151		value &= state->m_keyline[2];
152
	147	value &= m_keyline[2];
	148	*/
153	149	return value;
154	150	}
155	151
156		static WRITE8_DEVICE_HANDLER( c128_cia0_port_b_w )
	152	WRITE8_MEMBER( c128_state::cia1_pb_w )
157	153	{
158		mos6566_device *vic2e = device->machine().device<mos6566_device>("vic2e");
159
160		vic2e->lp_w(BIT(data, 4));
	154	m_vic->lp_w(BIT(data, 4));
161	155	}
162	156
163		static void c128_irq( running_machine &machine, int level )
	157	void c128_state::irq(int level)
164	158	{
165		c128_state *state = machine.driver_data<c128_state>();
166		if (level != state->m_old_level)
	159	if (level != m_old_level)
167	160	{
168		DBG_LOG(machine, 3, "mos6510", ("irq %s\n", level ? "start" : "end"));
	161	DBG_LOG(machine(), 3, "mos6510", ("irq %s\n", level ? "start" : "end"));
169	162
170	163	if (0) // && (cpu_getactivecpu() == 0))
171	164	{
172		cputag_set_input_line(machine, "maincpu", 0, level);
	165	m_maincpu->set_input_line(0, level);
173	166	}
174	167	else
175	168	{
176		cputag_set_input_line(machine, "m8502", M6510_IRQ_LINE, level);
	169	m_subcpu->set_input_line(M6510_IRQ_LINE, level);
177	170	}
178	171
179		state->m_old_level = level;
	172	m_old_level = level;
180	173	}
181	174	}
182	175
183		static void c128_cia0_interrupt( device_t *device, int level )
	176	WRITE_LINE_MEMBER( c128_state::cia1_irq_w )
184	177	{
185		c128_state *state = device->machine().driver_data<c128_state>();
186		c128_irq(device->machine(), level || state->m_vicirq);
	178	irq(state || m_vicirq);
187	179	}
188	180
189	181	WRITE_LINE_MEMBER( c128_state::vic_interrupt )
190	182	{
191		device_t *cia_0 = machine().device("cia_0");
192		#if 1
193	183	if (state  != m_vicirq)
194	184	{
195		c128_irq (machine(), state || mos6526_irq_r(cia_0));
	185	irq(state || mos6526_irq_r(m_cia1));
196	186	m_vicirq = state;
197	187	}
198		#endif
199	188	}
200	189
201		static void c128_iec_data_out_w(running_machine &machine)
	190	void c128_state::iec_data_out_w()
202	191	{
203		c128_state *state = machine.driver_data<c128_state>();
204		int data = !state->m_data_out;
	192	int data = !m_data_out;
205	193
206	194	/* fast serial data */
207		if (MMU_FSDIR(state)) data &= state->m_sp1;
	195	if (MMU_FSDIR) data &= m_sp1;
208	196
209		state->m_iec->data_w(data);
	197	m_iec->data_w(data);
210	198	}
211	199
212		static void c128_iec_srq_out_w(running_machine &machine)
	200	void c128_state::iec_srq_out_w()
213	201	{
214		c128_state *state = machine.driver_data<c128_state>();
215	202	int srq = 1;
216	203
217	204	/* fast serial clock */
218		if (MMU_FSDIR(state)) srq &= state->m_cnt1;
	205	if (MMU_FSDIR) srq &= m_cnt1;
219	206
220		state->m_iec->srq_w(srq);
	207	m_iec->srq_w(srq);
221	208	}
222	209
223		static WRITE_LINE_DEVICE_HANDLER( cia0_cnt_w )
	210	WRITE_LINE_MEMBER( c128_state::cia1_cnt_w )
224	211	{
225		c128_state *drvstate = device->machine().driver_data<c128_state>();
226	212	/* fast clock out */
227		drvstate->m_cnt1 = state;
228		c128_iec_srq_out_w(device->machine());
	213	m_cnt1 = state;
	214
	215	iec_srq_out_w();
229	216	}
230	217
231		static WRITE_LINE_DEVICE_HANDLER( cia0_sp_w )
	218	WRITE_LINE_MEMBER( c128_state::cia1_sp_w )
232	219	{
233		c128_state *drvstate = device->machine().driver_data<c128_state>();
234	220	/* fast data out */
235		drvstate->m_sp1 = state;
236		c128_iec_data_out_w(device->machine());
	221	m_sp1 = state;
	222
	223	iec_data_out_w();
237	224	}
238	225
239	226	const mos6526_interface c128_ntsc_cia0 =
240	227	{
241	228	60,
242		DEVCB_LINE(c128_cia0_interrupt),
	229	DEVCB_DRIVER_LINE_MEMBER(c128_state, cia1_irq_w),
243	230	DEVCB_NULL,   /* pc_func */
244		DEVCB_LINE(cia0_cnt_w),
245		DEVCB_LINE(cia0_sp_w),
246		DEVCB_HANDLER(c128_cia0_port_a_r),
	231	DEVCB_DRIVER_LINE_MEMBER(c128_state, cia1_cnt_w),
	232	DEVCB_DRIVER_LINE_MEMBER(c128_state, cia1_sp_w),
	233	DEVCB_DRIVER_MEMBER(c128_state, cia1_pa_r),
247	234	DEVCB_NULL,
248		DEVCB_HANDLER(c128_cia0_port_b_r),
249		DEVCB_HANDLER(c128_cia0_port_b_w)
	235	DEVCB_DRIVER_MEMBER(c128_state, cia1_pb_r),
	236	DEVCB_DRIVER_MEMBER(c128_state, cia1_pb_w)
250	237	};
251	238
252	239	const mos6526_interface c128_pal_cia0 =
253	240	{
254	241	50,
255		DEVCB_LINE(c128_cia0_interrupt),
	242	DEVCB_DRIVER_LINE_MEMBER(c128_state, cia1_irq_w),
256	243	DEVCB_NULL,   /* pc_func */
	244	DEVCB_DRIVER_LINE_MEMBER(c128_state, cia1_cnt_w),
	245	DEVCB_DRIVER_LINE_MEMBER(c128_state, cia1_sp_w),
	246	DEVCB_DRIVER_MEMBER(c128_state, cia1_pa_r),
257	247	DEVCB_NULL,
258		DEVCB_NULL,
259		DEVCB_HANDLER(c128_cia0_port_a_r),
260		DEVCB_NULL,
261		DEVCB_HANDLER(c128_cia0_port_b_r),
262		DEVCB_HANDLER(c128_cia0_port_b_w)
	248	DEVCB_DRIVER_MEMBER(c128_state, cia1_pb_r),
	249	DEVCB_DRIVER_MEMBER(c128_state, cia1_pb_w)
263	250	};
264	251
265		WRITE_LINE_DEVICE_HANDLER( c128_iec_srq_w )
	252	WRITE_LINE_MEMBER( c128_state::iec_srq_w )
266	253	{
267		c128_state *drvstate = device->machine().driver_data<c128_state>();
268
269		if (!MMU_FSDIR(drvstate))
	254	if (!MMU_FSDIR)
270	255	{
271		mos6526_flag_w(device, state);
272		mos6526_cnt_w(device, state);
	256	mos6526_flag_w(m_cia1, state);
	257	mos6526_cnt_w(m_cia1, state);
273	258	}
274	259	}
275	260
276		WRITE_LINE_DEVICE_HANDLER( c128_iec_data_w )
	261	WRITE_LINE_MEMBER( c128_state::iec_data_w )
277	262	{
278		c128_state *drvstate = device->machine().driver_data<c128_state>();
279
280		if (!MMU_FSDIR(drvstate))
	263	if (!MMU_FSDIR)
281	264	{
282		mos6526_sp_w(device, state);
	265	mos6526_sp_w(m_cia1, state);
283	266	}
284	267	}
285	268
r17732	r17733
306	289	* flag restore key or rs232 received data input
307	290	* irq to nmi connected ?
308	291	*/
309		static READ8_DEVICE_HANDLER( c128_cia1_port_a_r )
	292	READ8_MEMBER( c128_state::cia2_pa_r )
310	293	{
311		c128_state *state = device->machine().driver_data<c128_state>();
312	294	UINT8 value = 0xff;
313	295
314		if (!state->m_iec->clk_r())
	296	if (!m_iec->clk_r())
315	297	value &= ~0x40;
316	298
317		if (!state->m_iec->data_r())
	299	if (!m_iec->data_r())
318	300	value &= ~0x80;
319	301
320	302	return value;
321	303	}
322	304
323		static WRITE8_DEVICE_HANDLER( c128_cia1_port_a_w )
	305	WRITE8_MEMBER( c128_state::cia2_pa_w )
324	306	{
325		c128_state *state = device->machine().driver_data<c128_state>();
326	307	static const int helper[4] = {0xc000, 0x8000, 0x4000, 0x0000};
327	308
328		state->m_data_out = BIT(data, 5);
329		c128_iec_data_out_w(device->machine());
	309	m_data_out = BIT(data, 5);
	310	iec_data_out_w();
330	311
331		state->m_iec->clk_w(!BIT(data, 4));
	312	m_iec->clk_w(!BIT(data, 4));
332	313
333		state->m_iec->atn_w(!BIT(data, 3));
	314	m_iec->atn_w(!BIT(data, 3));
334	315
335		state->m_vicaddr = state->m_memory + helper[data & 0x03];
336		state->m_c128_vicaddr = state->m_memory + helper[data & 0x03] + state->m_va1617;
	316	m_vicaddr = m_memory + helper[data & 0x03];
	317	m_c128_vicaddr = m_memory + helper[data & 0x03] + m_va1617;
337	318	}
338	319
339		static void c128_cia1_interrupt( device_t *device, int level )
	320	WRITE_LINE_MEMBER( c128_state::cia2_irq_w )
340	321	{
341		c128_nmi(device->machine());
	322	nmi();
342	323	}
343	324
344	325	const mos6526_interface c128_ntsc_cia1 =
345	326	{
346	327	60,
347		DEVCB_LINE(c128_cia1_interrupt),
	328	DEVCB_DRIVER_LINE_MEMBER(c128_state, cia2_irq_w),
348	329	DEVCB_NULL,   /* pc_func */
349	330	DEVCB_NULL,
350	331	DEVCB_NULL,
351		DEVCB_HANDLER(c128_cia1_port_a_r),
352		DEVCB_HANDLER(c128_cia1_port_a_w),
	332	DEVCB_DRIVER_MEMBER(c128_state, cia2_pa_r),
	333	DEVCB_DRIVER_MEMBER(c128_state, cia2_pa_w),
353	334	DEVCB_NULL,
354	335	DEVCB_NULL
355	336	};
r17732	r17733
357	338	const mos6526_interface c128_pal_cia1 =
358	339	{
359	340	50,
360		DEVCB_LINE(c128_cia1_interrupt),
	341	DEVCB_DRIVER_LINE_MEMBER(c128_state, cia2_irq_w),
361	342	DEVCB_NULL,   /* pc_func */
362	343	DEVCB_NULL,
363	344	DEVCB_NULL,
364		DEVCB_HANDLER(c128_cia1_port_a_r),
365		DEVCB_HANDLER(c128_cia1_port_a_w),
	345	DEVCB_DRIVER_MEMBER(c128_state, cia2_pa_r),
	346	DEVCB_DRIVER_MEMBER(c128_state, cia2_pa_w),
366	347	DEVCB_NULL,
367	348	DEVCB_NULL
368	349	};
r17732	r17733
372	353	Memory Handlers
373	354
374	355	***********************************************/
375		static WRITE8_HANDLER( c128_dma8726_port_w )
	356	WRITE8_MEMBER( c128_state::dma8726_port_w )
376	357	{
377		DBG_LOG(space->machine(), 1, "dma write", ("%.3x %.2x\n",offset,data));
	358	DBG_LOG(machine(), 1, "dma write", ("%.3x %.2x\n",offset,data));
378	359	}
379	360
380		static READ8_HANDLER( c128_dma8726_port_r )
	361	READ8_MEMBER( c128_state::dma8726_port_r )
381	362	{
382		DBG_LOG(space->machine(), 1, "dma read", ("%.3x\n",offset));
	363	DBG_LOG(machine(), 1, "dma read", ("%.3x\n",offset));
383	364	return 0xff;
384	365	}
385	366
386		WRITE8_HANDLER( c128_write_d000 )
	367	WRITE8_MEMBER( c128_state::write_d000 )
387	368	{
388		c128_state *state = space->machine().driver_data<c128_state>();
389		device_t *cia_0 = space->machine().device("cia_0");
390		device_t *cia_1 = space->machine().device("cia_1");
391		device_t *sid = space->machine().device("sid6581");
392		mos6566_device *vic2e = space->machine().device<mos6566_device>("vic2e");
393		mos8563_device *vdc8563 = space->machine().device<mos8563_device>("vdc8563");
	369	UINT8 c64_port6510 = m6510_get_port(m_subcpu);
394	370
395		UINT8 c64_port6510 = m6510_get_port(space->machine().device<legacy_cpu_device>("m8502"));
396
397		if (!state->m_write_io)
	371	if (!m_write_io)
398	372	{
399		if (offset + 0xd000 >= state->m_ram_top)
400		state->m_memory[0xd000 + offset] = data;
	373	if (offset + 0xd000 >= m_ram_top)
	374	m_memory[0xd000 + offset] = data;
401	375	else
402		state->m_ram[0xd000 + offset] = data;
	376	m_ram[0xd000 + offset] = data;
403	377	}
404	378	else
405	379	{
406	380	switch ((offset&0xf00)>>8)
407	381	{
408	382	case 0:case 1: case 2: case 3:
409		vic2e->write(*space, offset & 0x3f, data);
	383	m_vic->write(space, offset & 0x3f, data);
410	384	break;
411	385	case 4:
412		sid6581_w(sid, offset & 0x3f, data);
	386	sid6581_w(m_sid, offset & 0x3f, data);
413	387	break;
414	388	case 5:
415		c128_mmu8722_port_w(space, offset & 0xff, data);
	389	mmu8722_port_w(space, offset & 0xff, data);
416	390	break;
417	391	case 6: case 7:
418	392	if (offset & 0x01)
419		vdc8563->register_w(*space, 0, data);
	393	m_vdc->register_w(space, 0, data);
420	394	else
421		vdc8563->address_w(*space, 0, data);
	395	m_vdc->address_w(space, 0, data);
422	396	break;
423	397	case 8: case 9: case 0xa: case 0xb:
424		if (state->m_c64mode)
425		state->m_colorram[(offset & 0x3ff)] = data | 0xf0;
	398	if (m_c64mode)
	399	m_colorram[(offset & 0x3ff)] = data | 0xf0;
426	400	else
427		state->m_colorram[(offset & 0x3ff)|((c64_port6510&3)<<10)] = data | 0xf0; // maybe all 8 bit connected!
	401	m_colorram[(offset & 0x3ff)|((c64_port6510&3)<<10)] = data | 0xf0; // maybe all 8 bit connected!
428	402	break;
429	403	case 0xc:
430		mos6526_w(cia_0, offset, data);
	404	mos6526_w(m_cia1, offset, data);
431	405	break;
432	406	case 0xd:
433		mos6526_w(cia_1, offset, data);
	407	mos6526_w(m_cia2, offset, data);
434	408	break;
435	409	case 0xf:
436		c128_dma8726_port_w(space, offset&0xff,data);
	410	dma8726_port_w(space, offset&0xff,data);
437	411	break;
438	412	case 0xe:
439		DBG_LOG(space->machine(), 1, "io write", ("%.3x %.2x\n", offset, data));
	413	DBG_LOG(machine(), 1, "io write", ("%.3x %.2x\n", offset, data));
440	414	break;
441	415	}
442	416	}
r17732	r17733
444	418
445	419
446	420
447		static READ8_HANDLER( c128_read_io )
	421	READ8_MEMBER( c128_state::read_io )
448	422	{
449		c128_state *state = space->machine().driver_data<c128_state>();
450		device_t *cia_0 = space->machine().device("cia_0");
451		device_t *cia_1 = space->machine().device("cia_1");
452		device_t *sid = space->machine().device("sid6581");
453		mos6566_device *vic2e = space->machine().device<mos6566_device>("vic2e");
454		mos8563_device *vdc8563 = space->machine().device<mos8563_device>("vdc8563");
455
456	423	if (offset < 0x400)
457		return vic2e->read(*space, offset & 0x3f);
	424	return m_vic->read(space, offset & 0x3f);
458	425	else if (offset < 0x500)
459		return sid6581_r(sid, offset & 0xff);
	426	return sid6581_r(m_sid, offset & 0xff);
460	427	else if (offset < 0x600)
461		return c128_mmu8722_port_r(space, offset & 0xff);
	428	return mmu8722_port_r(space, offset & 0xff);
462	429	else if (offset < 0x800)
463	430	if (offset & 0x01)
464		return vdc8563->register_r(*space, 0);
	431	return m_vdc->register_r(space, 0);
465	432	else
466		return vdc8563->status_r(*space, 0);
	433	return m_vdc->status_r(space, 0);
467	434	else if (offset < 0xc00)
468		return state->m_colorram[offset & 0x3ff];
	435	return m_colorram[offset & 0x3ff];
469	436	else if (offset == 0xc00)
470	437	{
471		cia_set_port_mask_value(cia_0, 0, state->ioport("CTRLSEL")->read() & 0x80 ? c64_keyline[8] : c64_keyline[9] );
472		return mos6526_r(cia_0, offset);
	438	cia_set_port_mask_value(m_cia1, 0, ioport("CTRLSEL")->read() & 0x80 ? c64_keyline[8] : c64_keyline[9] );
	439	return mos6526_r(m_cia1, offset);
473	440	}
474	441	else if (offset == 0xc01)
475	442	{
476		cia_set_port_mask_value(cia_0, 1, space->machine().root_device().ioport("CTRLSEL")->read() & 0x80 ? c64_keyline[9] : c64_keyline[8] );
477		return mos6526_r(cia_0, offset);
	443	cia_set_port_mask_value(m_cia1, 1, ioport("CTRLSEL")->read() & 0x80 ? c64_keyline[9] : c64_keyline[8] );
	444	return mos6526_r(m_cia1, offset);
478	445	}
479	446	else if (offset < 0xd00)
480		return mos6526_r(cia_0, offset);
	447	return mos6526_r(m_cia1, offset);
481	448	else if (offset < 0xe00)
482		return mos6526_r(cia_1, offset);
	449	return mos6526_r(m_cia2, offset);
483	450	else if ((offset >= 0xf00) & (offset <= 0xfff))
484		return c128_dma8726_port_r(space, offset&0xff);
485		DBG_LOG(space->machine(), 1, "io read", ("%.3x\n", offset));
	451	return dma8726_port_r(space, offset&0xff);
	452	DBG_LOG(machine(), 1, "io read", ("%.3x\n", offset));
486	453	return 0xff;
487	454	}
488	455
489		void c128_bankswitch_64( running_machine &machine, int reset )
	456	void c128_state::bankswitch_64(int reset)
490	457	{
491		c128_state *state = machine.driver_data<c128_state>();
492	458	int data, loram, hiram, charen;
493	459
494		if (!state->m_c64mode)
	460	if (!m_c64mode)
495	461	return;
496	462
497		data = m6510_get_port(machine.device<legacy_cpu_device>("m8502")) & 0x07;
498		if ((state->m_old_data == data) && (state->m_old_exrom == state->m_exrom) && (state->m_old_game == state->m_game) && !reset)
	463	data = m6510_get_port(m_subcpu) & 0x07;
	464	if ((m_old_data == data) && (m_old_exrom == m_exrom) && (m_old_game == m_game) && !reset)
499	465	return;
500	466
501		DBG_LOG(machine, 1, "bankswitch", ("%d\n", data & 7));
	467	DBG_LOG(machine(), 1, "bankswitch", ("%d\n", data & 7));
502	468	loram = (data & 1) ? 1 : 0;
503	469	hiram = (data & 2) ? 1 : 0;
504	470	charen = (data & 4) ? 1 : 0;
505	471
506		if ((!state->m_game && state->m_exrom) || (loram && hiram && !state->m_exrom))
507		state->membank("bank8")->set_base(state->m_roml);
	472	if ((!m_game && m_exrom) || (loram && hiram && !m_exrom))
	473	membank("bank8")->set_base(m_roml);
508	474	else
509		state->membank("bank8")->set_base(state->m_memory + 0x8000);
	475	membank("bank8")->set_base(m_memory + 0x8000);
510	476
511		if ((!state->m_game && state->m_exrom && hiram) || (!state->m_exrom))
512		state->membank("bank9")->set_base(state->m_romh);
	477	if ((!m_game && m_exrom && hiram) || (!m_exrom))
	478	membank("bank9")->set_base(m_romh);
513	479	else if (loram && hiram)
514		state->membank("bank9")->set_base(state->m_basic);
	480	membank("bank9")->set_base(m_basic);
515	481	else
516		state->membank("bank9")->set_base(state->m_memory + 0xa000);
	482	membank("bank9")->set_base(m_memory + 0xa000);
517	483
518		if ((!state->m_game && state->m_exrom) || (charen && (loram || hiram)))
	484	if ((!m_game && m_exrom) || (charen && (loram || hiram)))
519	485	{
520		machine.device("m8502")->memory().space(AS_PROGRAM)->install_legacy_read_handler(0xd000, 0xdfff, FUNC(c128_read_io));
521		state->m_write_io = 1;
	486	m_subcpu->memory().space(AS_PROGRAM)->install_read_handler(0xd000, 0xdfff, read8_delegate(FUNC(c128_state::read_io), this));
	487	m_write_io = 1;
522	488	}
523	489	else
524	490	{
525		machine.device("m8502")->memory().space(AS_PROGRAM)->install_read_bank(0xd000, 0xdfff, "bank5");
526		state->m_write_io = 0;
	491	m_subcpu->memory().space(AS_PROGRAM)->install_read_bank(0xd000, 0xdfff, "bank5");
	492	m_write_io = 0;
527	493	if ((!charen && (loram || hiram)))
528		state->membank("bank13")->set_base(state->m_chargen);
	494	membank("bank13")->set_base(m_chargen);
529	495	else
530		state->membank("bank13")->set_base(state->m_memory + 0xd000);
	496	membank("bank13")->set_base(m_memory + 0xd000);
531	497	}
532	498
533		if (!state->m_game && state->m_exrom)
	499	if (!m_game && m_exrom)
534	500	{
535		state->membank("bank14")->set_base(state->m_romh);
536		state->membank("bank15")->set_base(state->m_romh+0x1f00);
537		state->membank("bank16")->set_base(state->m_romh+0x1f05);
	501	membank("bank14")->set_base(m_romh);
	502	membank("bank15")->set_base(m_romh+0x1f00);
	503	membank("bank16")->set_base(m_romh+0x1f05);
538	504	}
539	505	else
540	506	{
541	507	if (hiram)
542	508	{
543		state->membank("bank14")->set_base(state->m_kernal);
544		state->membank("bank15")->set_base(state->m_kernal+0x1f00);
545		state->membank("bank16")->set_base(state->m_kernal+0x1f05);
	509	membank("bank14")->set_base(m_kernal);
	510	membank("bank15")->set_base(m_kernal+0x1f00);
	511	membank("bank16")->set_base(m_kernal+0x1f05);
546	512	}
547	513	else
548	514	{
549		state->membank("bank14")->set_base(state->m_memory + 0xe000);
550		state->membank("bank15")->set_base(state->m_memory + 0xff00);
551		state->membank("bank16")->set_base(state->m_memory + 0xff05);
	515	membank("bank14")->set_base(m_memory + 0xe000);
	516	membank("bank15")->set_base(m_memory + 0xff00);
	517	membank("bank16")->set_base(m_memory + 0xff05);
552	518	}
553	519	}
554		state->m_old_data = data;
555		state->m_old_exrom = state->m_exrom;
556		state->m_old_game =state->m_game;
	520	m_old_data = data;
	521	m_old_exrom = m_exrom;
	522	m_old_game =m_game;
557	523	}
558	524
559	525	/* typical z80 configuration
560	526	0x3f 0x3f 0x7f 0x3e 0x7e 0xb0 0x0b 0x00 0x00 0x01 0x00 */
561		static void c128_bankswitch_z80( running_machine &machine )
	527	void c128_state::bankswitch_z80()
562	528	{
563		c128_state *state = machine.driver_data<c128_state>();
564		state->m_ram = state->m_memory + MMU_RAM_ADDR;
565		state->m_va1617 = MMU_VIC_ADDR;
	529	m_ram = m_memory + MMU_RAM_ADDR;
	530	m_va1617 = MMU_VIC_ADDR;
566	531	#if 1
567		state->membank("bank10")->set_base(state->m_z80);
568		state->membank("bank11")->set_base(state->m_ram + 0x1000);
569		if ( (( (machine.root_device().ioport("SPECIAL")->read() & 0x06) == 0x02 ) && (MMU_RAM_ADDR >= 0x40000))
570		|| (( (machine.root_device().ioport("SPECIAL")->read() & 0x06) == 0x00) && (MMU_RAM_ADDR >= 0x20000)) )
571		state->m_ram = NULL;
	532	membank("bank10")->set_base(m_z80);
	533	membank("bank11")->set_base(m_ram + 0x1000);
	534	if ( (( (ioport("SPECIAL")->read() & 0x06) == 0x02 ) && (MMU_RAM_ADDR >= 0x40000))
	535	|| (( (ioport("SPECIAL")->read() & 0x06) == 0x00) && (MMU_RAM_ADDR >= 0x20000)) )
	536	m_ram = NULL;
572	537	#else
573	538	if (MMU_BOTTOM)
574		state->m_ram_bottom = MMU_SIZE;
	539	m_ram_bottom = MMU_SIZE;
575	540	else
576		state->m_ram_bottom = 0;
	541	m_ram_bottom = 0;
577	542
578	543	if (MMU_RAM_ADDR==0) { /* this is used in z80 mode for rom on/off switching !*/
579		state->membank("bank10")->set_base(state->m_z80);
580		state->membank("bank11")->set_base(state->m_z80 + 0x400);
	544	membank("bank10")->set_base(m_z80);
	545	membank("bank11")->set_base(m_z80 + 0x400);
581	546	}
582	547	else
583	548	{
584		state->membank("bank10")->set_base((state->m_ram_bottom > 0 ? state->m_memory : state->m_ram));
585		state->membank("bank11")->set_base((state->m_ram_bottom > 0x400 ? state->m_memory : state->m_ram) + 0x400);
	549	membank("bank10")->set_base((m_ram_bottom > 0 ? m_memory : m_ram));
	550	membank("bank11")->set_base((m_ram_bottom > 0x400 ? m_memory : m_ram) + 0x400);
586	551	}
587	552
588		state->membank("bank1")->set_base((state->m_ram_bottom > 0 ? state->m_memory : state->m_ram));
589		state->membank("bank2")->set_base((state->m_ram_bottom > 0x400 ? state->m_memory : state->m_ram) + 0x400);
	553	membank("bank1")->set_base((m_ram_bottom > 0 ? m_memory : m_ram));
	554	membank("bank2")->set_base((m_ram_bottom > 0x400 ? m_memory : m_ram) + 0x400);
590	555
591		state->membank("bank3")->set_base((state->m_ram_bottom > 0x1000 ? state->m_memory : state->m_ram) + 0x1000);
592		state->membank("bank4")->set_base((state->m_ram_bottom > 0x2000 ? state->m_memory : state->m_ram) + 0x2000);
593		state->membank("bank5")->set_base(state->m_ram + 0x4000);
	556	membank("bank3")->set_base((m_ram_bottom > 0x1000 ? m_memory : m_ram) + 0x1000);
	557	membank("bank4")->set_base((m_ram_bottom > 0x2000 ? m_memory : m_ram) + 0x2000);
	558	membank("bank5")->set_base(m_ram + 0x4000);
594	559
595	560	if (MMU_TOP)
596		state->m_ram_top = 0x10000 - MMU_SIZE;
	561	m_ram_top = 0x10000 - MMU_SIZE;
597	562	else
598		state->m_ram_top = 0x10000;
	563	m_ram_top = 0x10000;
599	564
600		if (state->m_ram_top > 0xc000)
601		state->membank("bank6")->set_base(state->m_ram + 0xc000);
	565	if (m_ram_top > 0xc000)
	566	membank("bank6")->set_base(m_ram + 0xc000);
602	567	else
603		state->membank("bank6")->set_base(state->m_memory + 0xc000);
	568	membank("bank6")->set_base(m_memory + 0xc000);
604	569
605		if (state->m_ram_top > 0xe000)
606		state->membank("bank7")->set_base(state->m_ram + 0xe000);
	570	if (m_ram_top > 0xe000)
	571	membank("bank7")->set_base(m_ram + 0xe000);
607	572	else
608		state->membank("bank7")->set_base(state->m_memory + 0xd000);
	573	membank("bank7")->set_base(m_memory + 0xd000);
609	574
610		if (state->m_ram_top > 0xf000)
611		state->membank("bank8")->set_base(state->m_ram + 0xf000);
	575	if (m_ram_top > 0xf000)
	576	membank("bank8")->set_base(m_ram + 0xf000);
612	577	else
613		state->membank("bank8")->set_base(state->m_memory + 0xe000);
	578	membank("bank8")->set_base(m_memory + 0xe000);
614	579
615		if (state->m_ram_top > 0xff05)
616		state->membank("bank9")->set_base(state->m_ram + 0xff05);
	580	if (m_ram_top > 0xff05)
	581	membank("bank9")->set_base(m_ram + 0xff05);
617	582	else
618		state->membank("bank9")->set_base(state->m_memory + 0xff05);
	583	membank("bank9")->set_base(m_memory + 0xff05);
619	584
620		if ( (( (machine.root_device().ioport("SPECIAL")->read() & 0x06) == 0x02 ) && (MMU_RAM_ADDR >= 0x40000))
621		|| (( (machine.root_device().ioport("SPECIAL")->read() & 0x06) == 0x00) && (MMU_RAM_ADDR >= 0x20000)) )
622		state->m_ram = NULL;
	585	if ( (( (ioport("SPECIAL")->read() & 0x06) == 0x02 ) && (MMU_RAM_ADDR >= 0x40000))
	586	|| (( (ioport("SPECIAL")->read() & 0x06) == 0x00) && (MMU_RAM_ADDR >= 0x20000)) )
	587	m_ram = NULL;
623	588	#endif
624	589	}
625	590
626		static void c128_bankswitch_128( running_machine &machine, int reset )
	591	void c128_state::bankswitch_128(int reset)
627	592	{
628		c128_state *state = machine.driver_data<c128_state>();
629		state->m_c64mode = MMU_64MODE;
630		if (state->m_c64mode)
	593	m_c64mode = MMU_64MODE;
	594	if (m_c64mode)
631	595	{
632	596	/* mmu works also in c64 mode, but this can wait */
633		state->m_ram = state->m_memory;
634		state->m_va1617 = 0;
635		state->m_ram_bottom = 0;
636		state->m_ram_top = 0x10000;
	597	m_ram = m_memory;
	598	m_va1617 = 0;
	599	m_ram_bottom = 0;
	600	m_ram_top = 0x10000;
637	601
638		state->membank("bank1")->set_base(state->m_memory);
639		state->membank("bank2")->set_base(state->m_memory + 0x100);
	602	membank("bank1")->set_base(m_memory);
	603	membank("bank2")->set_base(m_memory + 0x100);
640	604
641		state->membank("bank3")->set_base(state->m_memory + 0x200);
642		state->membank("bank4")->set_base(state->m_memory + 0x400);
643		state->membank("bank5")->set_base(state->m_memory + 0x1000);
644		state->membank("bank6")->set_base(state->m_memory + 0x2000);
	605	membank("bank3")->set_base(m_memory + 0x200);
	606	membank("bank4")->set_base(m_memory + 0x400);
	607	membank("bank5")->set_base(m_memory + 0x1000);
	608	membank("bank6")->set_base(m_memory + 0x2000);
645	609
646		state->membank("bank7")->set_base(state->m_memory + 0x4000);
	610	membank("bank7")->set_base(m_memory + 0x4000);
647	611
648		state->membank("bank12")->set_base(state->m_memory + 0xc000);
	612	membank("bank12")->set_base(m_memory + 0xc000);
649	613
650		c128_bankswitch_64(machine, reset);
	614	bankswitch_64(reset);
651	615	}
652	616	else
653	617	{
654		state->m_ram = state->m_memory + MMU_RAM_ADDR;
655		state->m_va1617 = MMU_VIC_ADDR;
656		state->membank("bank1")->set_base(state->m_memory + state->m_mmu_page0);
657		state->membank("bank2")->set_base(state->m_memory + state->m_mmu_page1);
	618	m_ram = m_memory + MMU_RAM_ADDR;
	619	m_va1617 = MMU_VIC_ADDR;
	620	membank("bank1")->set_base(m_memory + m_mmu_page0);
	621	membank("bank2")->set_base(m_memory + m_mmu_page1);
658	622	if (MMU_BOTTOM)
659	623	{
660		state->m_ram_bottom = MMU_SIZE;
	624	m_ram_bottom = MMU_SIZE;
661	625	}
662	626	else
663		state->m_ram_bottom = 0;
664		state->membank("bank3")->set_base((state->m_ram_bottom > 0x200 ? state->m_memory : state->m_ram) + 0x200);
665		state->membank("bank4")->set_base((state->m_ram_bottom > 0x400 ? state->m_memory : state->m_ram) + 0x400);
666		state->membank("bank5")->set_base((state->m_ram_bottom > 0x1000 ? state->m_memory : state->m_ram) + 0x1000);
667		state->membank("bank6")->set_base((state->m_ram_bottom > 0x2000 ? state->m_memory : state->m_ram) + 0x2000);
	627	m_ram_bottom = 0;
	628	membank("bank3")->set_base((m_ram_bottom > 0x200 ? m_memory : m_ram) + 0x200);
	629	membank("bank4")->set_base((m_ram_bottom > 0x400 ? m_memory : m_ram) + 0x400);
	630	membank("bank5")->set_base((m_ram_bottom > 0x1000 ? m_memory : m_ram) + 0x1000);
	631	membank("bank6")->set_base((m_ram_bottom > 0x2000 ? m_memory : m_ram) + 0x2000);
668	632
669	633	if (MMU_RAM_LO)
670	634	{
671		state->membank("bank7")->set_base(state->m_ram + 0x4000);
	635	membank("bank7")->set_base(m_ram + 0x4000);
672	636	}
673	637	else
674	638	{
675		state->membank("bank7")->set_base(state->m_c128_basic);
	639	membank("bank7")->set_base(m_c128_basic);
676	640	}
677	641
678	642	if (MMU_RAM_MID)
679	643	{
680		state->membank("bank8")->set_base(state->m_ram + 0x8000);
681		state->membank("bank9")->set_base(state->m_ram + 0xa000);
	644	membank("bank8")->set_base(m_ram + 0x8000);
	645	membank("bank9")->set_base(m_ram + 0xa000);
682	646	}
683	647	else if (MMU_ROM_MID)
684	648	{
685		state->membank("bank8")->set_base(state->m_c128_basic + 0x4000);
686		state->membank("bank9")->set_base(state->m_c128_basic + 0x6000);
	649	membank("bank8")->set_base(m_c128_basic + 0x4000);
	650	membank("bank9")->set_base(m_c128_basic + 0x6000);
687	651	}
688	652	else if (MMU_INTERNAL_ROM_MID)
689	653	{
690		state->membank("bank8")->set_base(state->m_internal_function);
691		state->membank("bank9")->set_base(state->m_internal_function + 0x2000);
	654	membank("bank8")->set_base(m_internal_function);
	655	membank("bank9")->set_base(m_internal_function + 0x2000);
692	656	}
693	657	else
694	658	{
695		state->membank("bank8")->set_base(state->m_external_function);
696		state->membank("bank9")->set_base(state->m_external_function + 0x2000);
	659	membank("bank8")->set_base(m_external_function);
	660	membank("bank9")->set_base(m_external_function + 0x2000);
697	661	}
698	662
699	663	if (MMU_TOP)
700	664	{
701		state->m_ram_top = 0x10000 - MMU_SIZE;
	665	m_ram_top = 0x10000 - MMU_SIZE;
702	666	}
703	667	else
704		state->m_ram_top = 0x10000;
	668	m_ram_top = 0x10000;
705	669
706		machine.device("m8502")->memory().space(AS_PROGRAM)->install_legacy_read_handler(0xff00, 0xff04, FUNC(c128_mmu8722_ff00_r));
	670	m_subcpu->memory().space(AS_PROGRAM)->install_read_handler(0xff00, 0xff04, read8_delegate(FUNC(c128_state::mmu8722_ff00_r), this));
707	671
708	672	if (MMU_IO_ON)
709	673	{
710		state->m_write_io = 1;
711		machine.device("m8502")->memory().space(AS_PROGRAM)->install_legacy_read_handler(0xd000, 0xdfff, FUNC(c128_read_io));
	674	m_write_io = 1;
	675	m_subcpu->memory().space(AS_PROGRAM)->install_read_handler(0xd000, 0xdfff, read8_delegate(FUNC(c128_state::read_io), this));
712	676	}
713	677	else
714	678	{
715		state->m_write_io = 0;
716		machine.device("m8502")->memory().space(AS_PROGRAM)->install_read_bank(0xd000, 0xdfff, "bank13");
	679	m_write_io = 0;
	680	m_subcpu->memory().space(AS_PROGRAM)->install_read_bank(0xd000, 0xdfff, "bank13");
717	681	}
718	682
719	683
720	684	if (MMU_RAM_HI)
721	685	{
722		if (state->m_ram_top > 0xc000)
	686	if (m_ram_top > 0xc000)
723	687	{
724		state->membank("bank12")->set_base(state->m_ram + 0xc000);
	688	membank("bank12")->set_base(m_ram + 0xc000);
725	689	}
726	690	else
727	691	{
728		state->membank("bank12")->set_base(state->m_memory + 0xc000);
	692	membank("bank12")->set_base(m_memory + 0xc000);
729	693	}
730	694	if (!MMU_IO_ON)
731	695	{
732		if (state->m_ram_top > 0xd000)
	696	if (m_ram_top > 0xd000)
733	697	{
734		state->membank("bank13")->set_base(state->m_ram + 0xd000);
	698	membank("bank13")->set_base(m_ram + 0xd000);
735	699	}
736	700	else
737	701	{
738		state->membank("bank13")->set_base(state->m_memory + 0xd000);
	702	membank("bank13")->set_base(m_memory + 0xd000);
739	703	}
740	704	}
741		if (state->m_ram_top > 0xe000)
	705	if (m_ram_top > 0xe000)
742	706	{
743		state->membank("bank14")->set_base(state->m_ram + 0xe000);
	707	membank("bank14")->set_base(m_ram + 0xe000);
744	708	}
745	709	else
746	710	{
747		state->membank("bank14")->set_base(state->m_memory + 0xe000);
	711	membank("bank14")->set_base(m_memory + 0xe000);
748	712	}
749		if (state->m_ram_top > 0xff05)
	713	if (m_ram_top > 0xff05)
750	714	{
751		state->membank("bank16")->set_base(state->m_ram + 0xff05);
	715	membank("bank16")->set_base(m_ram + 0xff05);
752	716	}
753	717	else
754	718	{
755		state->membank("bank16")->set_base(state->m_memory + 0xff05);
	719	membank("bank16")->set_base(m_memory + 0xff05);
756	720	}
757	721	}
758	722	else if (MMU_ROM_HI)
759	723	{
760		state->membank("bank12")->set_base(state->m_editor);
	724	membank("bank12")->set_base(m_editor);
761	725	if (!MMU_IO_ON) {
762		state->membank("bank13")->set_base(state->m_c128_chargen);
	726	membank("bank13")->set_base(m_c128_chargen);
763	727	}
764		state->membank("bank14")->set_base(state->m_c128_kernal);
765		state->membank("bank16")->set_base(state->m_c128_kernal + 0x1f05);
	728	membank("bank14")->set_base(m_c128_kernal);
	729	membank("bank16")->set_base(m_c128_kernal + 0x1f05);
766	730	}
767	731	else if (MMU_INTERNAL_ROM_HI)
768	732	{
769		state->membank("bank12")->set_base(state->m_internal_function);
	733	membank("bank12")->set_base(m_internal_function);
770	734	if (!MMU_IO_ON) {
771		state->membank("bank13")->set_base(state->m_internal_function + 0x1000);
	735	membank("bank13")->set_base(m_internal_function + 0x1000);
772	736	}
773		state->membank("bank14")->set_base(state->m_internal_function + 0x2000);
774		state->membank("bank16")->set_base(state->m_internal_function + 0x3f05);
	737	membank("bank14")->set_base(m_internal_function + 0x2000);
	738	membank("bank16")->set_base(m_internal_function + 0x3f05);
775	739	}
776	740	else                  /*if (MMU_EXTERNAL_ROM_HI) */
777	741	{
778		state->membank("bank12")->set_base(state->m_external_function);
	742	membank("bank12")->set_base(m_external_function);
779	743	if (!MMU_IO_ON) {
780		state->membank("bank13")->set_base(state->m_external_function + 0x1000);
	744	membank("bank13")->set_base(m_external_function + 0x1000);
781	745	}
782		state->membank("bank14")->set_base(state->m_external_function + 0x2000);
783		state->membank("bank16")->set_base(state->m_external_function + 0x3f05);
	746	membank("bank14")->set_base(m_external_function + 0x2000);
	747	membank("bank16")->set_base(m_external_function + 0x3f05);
784	748	}
785	749
786		if ( (( (machine.root_device().ioport("SPECIAL")->read() & 0x06) == 0x02 ) && (MMU_RAM_ADDR >= 0x40000))
787		|| (( (machine.root_device().ioport("SPECIAL")->read() & 0x06) == 0x00) && (MMU_RAM_ADDR >= 0x20000)) )
788		state->m_ram = NULL;
	750	if ( (( (ioport("SPECIAL")->read() & 0x06) == 0x02 ) && (MMU_RAM_ADDR >= 0x40000))
	751	|| (( (ioport("SPECIAL")->read() & 0x06) == 0x00) && (MMU_RAM_ADDR >= 0x20000)) )
	752	m_ram = NULL;
789	753	}
790	754	}
791	755
792	756	// 128u4
793	757	// FIX-ME: are the bankswitch functions working in the expected way without the memory_set_context?
794		static void c128_bankswitch( running_machine &machine, int reset )
	758	void c128_state::bankswitch(int reset)
795	759	{
796		c128_state *state = machine.driver_data<c128_state>();
797		if (state->m_mmu_cpu != MMU_CPU8502)
	760	if (m_mmu_cpu != MMU_CPU8502)
798	761	{
799	762	if (!MMU_CPU8502)
800	763	{
801	764	//          DBG_LOG(machine, 1, "switching to z80", ("active %d\n",cpu_getactivecpu()) );
802	765	//          memory_set_context(machine, 0);
803		c128_bankswitch_z80(machine);
	766	bankswitch_z80();
804	767	//          memory_set_context(machine, 1);
805		cputag_set_input_line(machine, "maincpu", INPUT_LINE_HALT, CLEAR_LINE);
806		cputag_set_input_line(machine, "m8502", INPUT_LINE_HALT, ASSERT_LINE);
	768	m_maincpu->set_input_line(INPUT_LINE_HALT, CLEAR_LINE);
	769	m_subcpu->set_input_line(INPUT_LINE_HALT, ASSERT_LINE);
807	770	}
808	771	else
809	772	{
810	773	//          DBG_LOG(machine, 1, "switching to m6502", ("active %d\n",cpu_getactivecpu()) );
811	774	//          memory_set_context(machine, 1);
812		c128_bankswitch_128(machine, reset);
	775	bankswitch_128(reset);
813	776	//          memory_set_context(machine, 0);
814		cputag_set_input_line(machine, "maincpu", INPUT_LINE_HALT, ASSERT_LINE);
815		cputag_set_input_line(machine, "m8502", INPUT_LINE_HALT, CLEAR_LINE);
	777	m_maincpu->set_input_line(INPUT_LINE_HALT, ASSERT_LINE);
	778	m_subcpu->set_input_line(INPUT_LINE_HALT, CLEAR_LINE);
816	779
817	780	/* NPW 19-Nov-2005 - In the C128, CPU #0 starts out and hands over
818	781	* control to CPU #1.  CPU #1 seems to execute garbage from 0x0000
r17732	r17733
826	789	* driver used to work with this behavior, so I am doing this hack
827	790	* where I set CPU #1's PC to 0x1100 on reset.
828	791	*/
829		if (cpu_get_reg(machine.device("m8502"), STATE_GENPC) == 0x0000)
830		cpu_set_reg(machine.device("m8502"), STATE_GENPC, 0x1100);
	792	if (cpu_get_reg(m_subcpu, STATE_GENPC) == 0x0000)
	793	cpu_set_reg(m_subcpu, STATE_GENPC, 0x1100);
831	794	}
832		state->m_mmu_cpu = MMU_CPU8502;
	795	m_mmu_cpu = MMU_CPU8502;
833	796	return;
834	797	}
835	798	if (!MMU_CPU8502)
836		c128_bankswitch_z80(machine);
	799	bankswitch_z80();
837	800	else
838		c128_bankswitch_128(machine, reset);
	801	bankswitch_128(reset);
839	802	}
840	803
841		static void c128_mmu8722_reset( running_machine &machine )
	804	void c128_state::mmu8722_reset()
842	805	{
843		c128_state *state = machine.driver_data<c128_state>();
844		memset(state->m_mmu, 0, sizeof (state->m_mmu));
845		state->m_mmu[5] |= 0x38;
846		state->m_mmu[10] = 1;
847		state->m_mmu_cpu = 0;
848		state->m_mmu_page0 = 0;
849		state->m_mmu_page1 = 0x0100;
850		c128_bankswitch (machine, 1);
	806	memset(m_mmu, 0, sizeof (m_mmu));
	807	m_mmu[5] |= 0x38;
	808	m_mmu[10] = 1;
	809	m_mmu_cpu = 0;
	810	m_mmu_page0 = 0;
	811	m_mmu_page1 = 0x0100;
	812	bankswitch(1);
851	813	}
852	814
853		WRITE8_HANDLER( c128_mmu8722_port_w )
	815	WRITE8_MEMBER( c128_state::mmu8722_port_w )
854	816	{
855		c128_state *state = space->machine().driver_data<c128_state>();
856	817	offset &= 0xf;
857	818	switch (offset)
858	819	{
r17732	r17733
862	823	case 4:
863	824	case 8:
864	825	case 10:
865		state->m_mmu[offset] = data;
	826	m_mmu[offset] = data;
866	827	break;
867	828	case 5:
868		state->m_mmu[offset] = data;
869		c128_bankswitch (space->machine(), 0);
870		c128_iec_srq_out_w(space->machine());
871		c128_iec_data_out_w(space->machine());
	829	m_mmu[offset] = data;
	830	bankswitch(0);
	831	iec_srq_out_w();
	832	iec_data_out_w();
872	833	break;
873	834	case 0:
874	835	case 6:
875		state->m_mmu[offset] = data;
876		c128_bankswitch (space->machine(), 0);
	836	m_mmu[offset] = data;
	837	bankswitch(0);
877	838	break;
878	839	case 7:
879		state->m_mmu[offset] = data;
880		state->m_mmu_page0=MMU_PAGE0;
	840	m_mmu[offset] = data;
	841	m_mmu_page0=MMU_PAGE0;
881	842	break;
882	843	case 9:
883		state->m_mmu[offset] = data;
884		state->m_mmu_page1=MMU_PAGE1;
885		c128_bankswitch (space->machine(), 0);
	844	m_mmu[offset] = data;
	845	m_mmu_page1=MMU_PAGE1;
	846	bankswitch(0);
886	847	break;
887	848	case 0xb:
888	849	break;
r17732	r17733
894	855	}
895	856	}
896	857
897		READ8_HANDLER( c128_mmu8722_port_r )
	858	READ8_MEMBER( c128_state::mmu8722_port_r )
898	859	{
899		c128_state *state = space->machine().driver_data<c128_state>();
900	860	int data;
901	861
902	862	offset &= 0x0f;
903	863	switch (offset)
904	864	{
905	865	case 5:
906		data = state->m_mmu[offset] | 6;
	866	data = m_mmu[offset] | 6;
907	867	if ( /*disk enable signal */ 0)
908	868	data &= ~8;
909		if (!state->m_game)
	869	if (!m_game)
910	870	data &= ~0x10;
911		if (!state->m_exrom)
	871	if (!m_exrom)
912	872	data &= ~0x20;
913		if (space->machine().root_device().ioport("SPECIAL")->read() & 0x10)
	873	if (ioport("SPECIAL")->read() & 0x10)
914	874	data &= ~0x80;
915	875	break;
916	876	case 0xb:
917	877	/* hinybble number of 64 kb memory blocks */
918		if ((space->machine().root_device().ioport("SPECIAL")->read() & 0x06) == 0x02)      // 256KB RAM
	878	if ((ioport("SPECIAL")->read() & 0x06) == 0x02)      // 256KB RAM
919	879	data = 0x4f;
920		else if ((state->ioport("SPECIAL")->read() & 0x06) == 0x04)   //  1MB
	880	else if ((ioport("SPECIAL")->read() & 0x06) == 0x04)   //  1MB
921	881	data = 0xf;
922	882	else
923	883	data = 0x2f;
r17732	r17733
929	889	data=0xff;
930	890	break;
931	891	default:
932		data=state->m_mmu[offset];
	892	data=m_mmu[offset];
933	893	}
934	894	return data;
935	895	}
936	896
937		WRITE8_HANDLER( c128_mmu8722_ff00_w )
	897	WRITE8_MEMBER( c128_state::mmu8722_ff00_w )
938	898	{
939		c128_state *state = space->machine().driver_data<c128_state>();
940	899	switch (offset)
941	900	{
942	901	case 0:
943		state->m_mmu[offset] = data;
944		c128_bankswitch (space->machine(), 0);
	902	m_mmu[offset] = data;
	903	bankswitch(0);
945	904	break;
946	905	case 1:
947	906	case 2:
948	907	case 3:
949	908	case 4:
950	909	#if 1
951		state->m_mmu[0]= state->m_mmu[offset];
	910	m_mmu[0]= m_mmu[offset];
952	911	#else
953		state->m_mmu[0]|= state->m_mmu[offset];
	912	m_mmu[0]|= m_mmu[offset];
954	913	#endif
955		c128_bankswitch (space->machine(), 0);
	914	bankswitch(0);
956	915	break;
957	916	}
958	917	}
959	918
960		READ8_HANDLER( c128_mmu8722_ff00_r )
	919	READ8_MEMBER( c128_state::mmu8722_ff00_r )
961	920	{
962		c128_state *state = space->machine().driver_data<c128_state>();
963		return state->m_mmu[offset];
	921	return m_mmu[offset];
964	922	}
965	923
966		WRITE8_HANDLER( c128_write_0000 )
	924	WRITE8_MEMBER( c128_state::write_0000 )
967	925	{
968		c128_state *state = space->machine().driver_data<c128_state>();
969		if (state->m_ram != NULL)
970		state->m_ram[0x0000 + offset] = data;
	926	if (m_ram != NULL)
	927	m_ram[0x0000 + offset] = data;
971	928	}
972	929
973		WRITE8_HANDLER( c128_write_1000 )
	930	WRITE8_MEMBER( c128_state::write_1000 )
974	931	{
975		c128_state *state = space->machine().driver_data<c128_state>();
976		if (state->m_ram != NULL)
977		state->m_ram[0x1000 + offset] = data;
	932	if (m_ram != NULL)
	933	m_ram[0x1000 + offset] = data;
978	934	}
979	935
980		WRITE8_HANDLER( c128_write_4000 )
	936	WRITE8_MEMBER( c128_state::write_4000 )
981	937	{
982		c128_state *state = space->machine().driver_data<c128_state>();
983		if (state->m_ram != NULL)
984		state->m_ram[0x4000 + offset] = data;
	938	if (m_ram != NULL)
	939	m_ram[0x4000 + offset] = data;
985	940	}
986	941
987		WRITE8_HANDLER( c128_write_8000 )
	942	WRITE8_MEMBER( c128_state::write_8000 )
988	943	{
989		c128_state *state = space->machine().driver_data<c128_state>();
990		if (state->m_ram != NULL)
991		state->m_ram[0x8000 + offset] = data;
	944	if (m_ram != NULL)
	945	m_ram[0x8000 + offset] = data;
992	946	}
993	947
994		WRITE8_HANDLER( c128_write_a000 )
	948	WRITE8_MEMBER( c128_state::write_a000 )
995	949	{
996		c128_state *state = space->machine().driver_data<c128_state>();
997		if (state->m_ram != NULL)
998		state->m_ram[0xa000 + offset] = data;
	950	if (m_ram != NULL)
	951	m_ram[0xa000 + offset] = data;
999	952	}
1000	953
1001		WRITE8_HANDLER( c128_write_c000 )
	954	WRITE8_MEMBER( c128_state::write_c000 )
1002	955	{
1003		c128_state *state = space->machine().driver_data<c128_state>();
1004		if (state->m_ram != NULL)
1005		state->m_ram[0xc000 + offset] = data;
	956	if (m_ram != NULL)
	957	m_ram[0xc000 + offset] = data;
1006	958	}
1007	959
1008		WRITE8_HANDLER( c128_write_e000 )
	960	WRITE8_MEMBER( c128_state::write_e000 )
1009	961	{
1010		c128_state *state = space->machine().driver_data<c128_state>();
1011		if (offset + 0xe000 >= state->m_ram_top)
1012		state->m_memory[0xe000 + offset] = data;
1013		else if (state->m_ram != NULL)
1014		state->m_ram[0xe000 + offset] = data;
	962	if (offset + 0xe000 >= m_ram_top)
	963	m_memory[0xe000 + offset] = data;
	964	else if (m_ram != NULL)
	965	m_ram[0xe000 + offset] = data;
1015	966	}
1016	967
1017		WRITE8_HANDLER( c128_write_ff00 )
	968	WRITE8_MEMBER( c128_state::write_ff00 )
1018	969	{
1019		c128_state *state = space->machine().driver_data<c128_state>();
1020		if (!state->m_c64mode)
1021		c128_mmu8722_ff00_w(space, offset, data);
1022		else if (state->m_ram!=NULL)
1023		state->m_memory[0xff00 + offset] = data;
	970	if (!m_c64mode)
	971	mmu8722_ff00_w(space, offset, data);
	972	else if (m_ram!=NULL)
	973	m_memory[0xff00 + offset] = data;
1024	974	}
1025	975
1026		WRITE8_HANDLER( c128_write_ff05 )
	976	WRITE8_MEMBER( c128_state::write_ff05 )
1027	977	{
1028		c128_state *state = space->machine().driver_data<c128_state>();
1029		if (offset + 0xff05 >= state->m_ram_top)
1030		state->m_memory[0xff05 + offset] = data;
1031		else if (state->m_ram!=NULL)
1032		state->m_ram[0xff05 + offset] = data;
	978	if (offset + 0xff05 >= m_ram_top)
	979	m_memory[0xff05 + offset] = data;
	980	else if (m_ram!=NULL)
	981	m_ram[0xff05 + offset] = data;
1033	982	}
1034	983
1035	984	/*
r17732	r17733
1039	988	*/
1040	989	READ8_MEMBER( c128_state::vic_dma_read )
1041	990	{
1042		UINT8 c64_port6510 = m6510_get_port(machine().device<legacy_cpu_device>("m8502"));
	991	UINT8 c64_port6510 = m6510_get_port(m_subcpu);
1043	992
1044	993	/* main memory configuration to include */
1045	994	if (m_c64mode)
r17732	r17733
1061	1010
1062	1011	READ8_MEMBER( c128_state::vic_dma_read_color )
1063	1012	{
1064		UINT8 c64_port6510 = m6510_get_port(machine().device<legacy_cpu_device>("m8502"));
	1013	UINT8 c64_port6510 = m6510_get_port(m_subcpu);
1065	1014
1066	1015	if (m_c64mode)
1067	1016	return m_colorram[offset & 0x3ff] & 0xf;
r17732	r17733
1076	1025	*/
1077	1026
1078	1027
1079		WRITE8_DEVICE_HANDLER(c128_m6510_port_write)
	1028	WRITE8_MEMBER( c128_state::cpu_w )
1080	1029	{
1081		c128_state *state = device->machine().driver_data<c128_state>();
	1030	m_cassette->write(BIT(data, 3));
1082	1031
1083		if (state->m_tape_on)
1084		{
1085		device->machine().device<cassette_image_device>(CASSETTE_TAG)->output((data & 0x08) ? -(0x5a9e >> 1) : +(0x5a9e >> 1));
	1032	m_cassette->motor_w(BIT(data, 5));
1086	1033
1087		if (!(data & 0x20))
1088		{
1089		device->machine().device<cassette_image_device>(CASSETTE_TAG)->change_state(CASSETTE_MOTOR_ENABLED,CASSETTE_MASK_MOTOR);
1090		state->m_datasette_timer->adjust(attotime::zero, 0, attotime::from_hz(44100));
1091		}
1092		else
1093		{
1094		device->machine().device<cassette_image_device>(CASSETTE_TAG)->change_state(CASSETTE_MOTOR_DISABLED ,CASSETTE_MASK_MOTOR);
1095		state->m_datasette_timer->reset();
1096		}
1097		}
	1034	bankswitch_64(0);
1098	1035
1099		c128_bankswitch_64(device->machine(), 0);
	1036	m_memory[0x000] = m_subcpu->memory().space(AS_PROGRAM)->read_byte(0);
	1037	m_memory[0x001] = m_subcpu->memory().space(AS_PROGRAM)->read_byte(1);
1100	1038
1101		state->m_memory[0x000] = device->memory().space(AS_PROGRAM)->read_byte(0);
1102		state->m_memory[0x001] = device->memory().space(AS_PROGRAM)->read_byte(1);
1103
1104	1039	}
1105	1040
1106		READ8_DEVICE_HANDLER(c128_m6510_port_read)
	1041	READ8_MEMBER( c128_state::cpu_r)
1107	1042	{
1108		c128_state *state = device->machine().driver_data<c128_state>();
1109	1043	UINT8 data = 0x07;
1110	1044
1111		if ((device->machine().device<cassette_image_device>(CASSETTE_TAG)->get_state() & CASSETTE_MASK_UISTATE) != CASSETTE_STOPPED)
	1045	if (m_cassette->sense_r())
1112	1046	data &= ~0x10;
1113	1047	else
1114	1048	data |=  0x10;
1115	1049
1116		if (state->ioport("SPECIAL")->read() & 0x20)      /* Check Caps Lock */
	1050	if (ioport("SPECIAL")->read() & 0x20)      /* Check Caps Lock */
1117	1051	data &= ~0x40;
1118	1052	else
1119	1053	data |=  0x40;
r17732	r17733
1121	1055	return data;
1122	1056	}
1123	1057
1124		static void c128_common_driver_init( running_machine &machine )
	1058	DRIVER_INIT_MEMBER(c128_state,c128)
1125	1059	{
1126		c128_state *state = machine.driver_data<c128_state>();
1127		UINT8 *gfx=machine.root_device().memregion("gfx1")->base();
1128		UINT8 *ram = state->memregion("maincpu")->base();
1129		int i;
	1060	UINT8 *ram = memregion(Z80A_TAG)->base();
1130	1061
1131		state->m_memory = ram;
	1062	m_memory = ram;
1132	1063
1133		state->m_c128_basic = ram + 0x100000;
1134		state->m_basic = ram + 0x108000;
1135		state->m_kernal = ram + 0x10a000;
1136		state->m_editor = ram + 0x10c000;
1137		state->m_z80 = ram + 0x10d000;
1138		state->m_c128_kernal = ram + 0x10e000;
1139		state->m_internal_function = ram + 0x110000;
1140		state->m_external_function = ram + 0x118000;
1141		state->m_chargen = ram + 0x120000;
1142		state->m_c128_chargen = ram + 0x121000;
1143		state->m_colorram = ram + 0x122000;
1144		state->m_vdcram = ram + 0x122800;
1145		state->m_c64_roml = auto_alloc_array(machine, UINT8, 0x2000);
1146		state->m_c64_romh = auto_alloc_array(machine, UINT8, 0x2000);
	1064	m_c128_basic = ram + 0x100000;
	1065	m_basic = ram + 0x108000;
	1066	m_kernal = ram + 0x10a000;
	1067	m_editor = ram + 0x10c000;
	1068	m_z80 = ram + 0x10d000;
	1069	m_c128_kernal = ram + 0x10e000;
	1070	m_internal_function = ram + 0x110000;
	1071	m_external_function = ram + 0x118000;
	1072	m_chargen = ram + 0x120000;
	1073	m_c128_chargen = ram + 0x121000;
	1074	m_colorram = ram + 0x122000;
	1075	m_vdcram = ram + 0x122800;
	1076	m_c64_roml = auto_alloc_array(machine(), UINT8, 0x2000);
	1077	m_c64_romh = auto_alloc_array(machine(), UINT8, 0x2000);
1147	1078
1148		state->m_tape_on = 1;
1149		state->m_game = 1;
1150		state->m_exrom = 1;
1151		state->m_pal = 0;
1152		state->m_c64mode = 0;
1153		state->m_vicirq = 0;
	1079	m_game = 1;
	1080	m_exrom = 1;
	1081	m_pal = 0;
	1082	m_c64mode = 0;
	1083	m_vicirq = 0;
1154	1084
1155		state->m_monitor = -1;
1156		state->m_cnt1 = 1;
1157		state->m_sp1 = 1;
	1085	m_monitor = -1;
	1086	m_cnt1 = 1;
	1087	m_sp1 = 1;
1158	1088	cbm_common_init();
1159		state->m_keyline[0] = state->m_keyline[1] = state->m_keyline[2] = 0xff;
1160
1161		for (i = 0; i < 0x100; i++)
1162		gfx[i] = i;
1163
1164		if (state->m_tape_on)
1165		state->m_datasette_timer = machine.scheduler().timer_alloc(FUNC(c64_tape_timer));
	1089	m_keyline[0] = m_keyline[1] = m_keyline[2] = 0xff;
1166	1090	}
1167	1091
1168		DRIVER_INIT_MEMBER(c128_state,c128)
1169		{
1170		//device_t *vic2e = machine().device("vic2e");
1171		//device_t *vdc8563 = machine().device("vdc8563");
1172
1173		c128_common_driver_init(machine());
1174
1175		//vic2_set_rastering(vic2e, 0);
1176		//vdc8563_set_rastering(vdc8563, 1);
1177		}
1178
1179	1092	DRIVER_INIT_MEMBER(c128_state,c128pal)
1180	1093	{
1181		//device_t *vic2e = machine().device("vic2e");
1182		//device_t *vdc8563 = machine().device("vdc8563");
	1094	DRIVER_INIT_CALL( c128 );
1183	1095
1184		c128_common_driver_init(machine());
1185	1096	m_pal = 1;
1186
1187		//vic2_set_rastering(vic2e, 1);
1188		//vdc8563_set_rastering(vdc8563, 0);
1189	1097	}
1190	1098
1191	1099	DRIVER_INIT_MEMBER(c128_state,c128d)
r17732	r17733
1213	1121	DRIVER_INIT_CALL( c128 );
1214	1122	}
1215	1123
1216		MACHINE_START( c128 )
	1124	void c128_state::machine_start()
1217	1125	{
1218		c128_state *state = machine.driver_data<c128_state>();
1219	1126	// This was in MACHINE_START( c64 ), but never called
1220	1127	// TO DO: find its correct use, when fixing c64 mode
1221		if (state->m_c64mode)
1222		c128_bankswitch_64(machine, 1);
	1128	if (m_c64mode)
	1129	bankswitch_64(1);
1223	1130	}
1224	1131
1225		MACHINE_RESET( c128 )
	1132	void c128_state::machine_reset()
1226	1133	{
1227		c128_state *state = machine.driver_data<c128_state>();
1228		state->m_c128_vicaddr = state->m_vicaddr = state->m_memory;
1229		state->m_c64mode = 0;
1230		c128_mmu8722_reset(machine);
1231		cputag_set_input_line(machine, "maincpu", INPUT_LINE_HALT, CLEAR_LINE);
1232		cputag_set_input_line(machine, "m8502", INPUT_LINE_HALT, ASSERT_LINE);
	1134	m_c128_vicaddr = m_vicaddr = m_memory;
	1135	m_c64mode = 0;
	1136	mmu8722_reset();
	1137	m_maincpu->set_input_line(INPUT_LINE_HALT, CLEAR_LINE);
	1138	m_subcpu->set_input_line(INPUT_LINE_HALT, ASSERT_LINE);
1233	1139	}
1234	1140
1235	1141
r17732	r17733
1241	1147	//device_t *vic2e = device->machine().device("vic2e");
1242	1148	//device_t *vdc8563 = device->machine().device("vdc8563");
1243	1149
1244		c128_nmi(device->machine());
	1150	state->nmi();
1245	1151
1246	1152	if ((device->machine().root_device().ioport("SPECIAL")->read() & 0x08) != state->m_monitor)
1247	1153	{

trunk/src/mess/includes/c128.h

r17732	r17733
14	14	#ifndef __C128_H__
15	15	#define __C128_H__
16	16
17		#include "includes/c64_legacy.h"
	17	#include "emu.h"
	18	#include "formats/cbm_snqk.h"
	19	#include "includes/cbm.h"
18	20	#include "machine/6526cia.h"
	21	#include "machine/c64exp.h"
	22	#include "machine/c64user.h"
	23	#include "machine/cbmiec.h"
	24	#include "machine/cbmipt.h"
	25	#include "machine/petcass.h"
	26	#include "machine/ram.h"
	27	#include "machine/vcsctrl.h"
	28	#include "sound/dac.h"
	29	#include "sound/sid6581.h"
	30	#include "video/mos6566.h"
	31	#include "video/vdc8563.h"
19	32
	33	// TODO remove
	34	#include "includes/c64_legacy.h"
	35
	36	#define Z80A_TAG      "u10"
	37	#define M8502_TAG      "u6"
	38	#define MOS8563_TAG      "u22"
	39	#define MOS8564_TAG      "u21"
	40	#define MOS8566_TAG      "u21"
	41	#define MOS6581_TAG      "u5"
	42	#define MOS6526_1_TAG   "u1"
	43	#define MOS6526_2_TAG   "u4"
	44	#define MOS8721_TAG      "u11"
	45	#define MOS8722_TAG      "u7"
	46	#define SCREEN_VIC_TAG   "screen"
	47	#define SCREEN_VDC_TAG   "screen80"
	48	#define CONTROL1_TAG   "joy1"
	49	#define CONTROL2_TAG   "joy2"
	50
20	51	class c128_state : public legacy_c64_state
21	52	{
22	53	public:
23	54	c128_state(const machine_config &mconfig, device_type type, const char *tag)
24		: legacy_c64_state(mconfig, type, tag) { }
	55	: legacy_c64_state(mconfig, type, tag),
	56	m_maincpu(*this, Z80A_TAG),
	57	m_subcpu(*this, M8502_TAG),
	58	m_vdc(*this, MOS8563_TAG),
	59	m_vic(*this, MOS8564_TAG),
	60	m_sid(*this, MOS6581_TAG),
	61	m_cia1(*this, MOS6526_1_TAG),
	62	m_cia2(*this, MOS6526_2_TAG),
	63	//m_iec(*this, CBM_IEC_TAG),
	64	//m_joy1(*this, CONTROL1_TAG),
	65	//m_joy2(*this, CONTROL2_TAG),
	66	//m_exp(*this, C128_EXPANSION_SLOT_TAG),
	67	//m_user(*this, C128_USER_PORT_TAG),
	68	//m_ram(*this, RAM_TAG),
	69	m_cassette(*this, PET_DATASSETTE_PORT_TAG)
	70	{ }
25	71
	72	required_device<legacy_cpu_device> m_maincpu;
	73	required_device<legacy_cpu_device> m_subcpu;
	74	required_device<mos8563_device> m_vdc;
	75	required_device<mos6566_device> m_vic;
	76	required_device<sid6581_device> m_sid;
	77	required_device<mos6526_device> m_cia1;
	78	required_device<mos6526_device> m_cia2;
	79	//required_device<cbm_iec_device> m_iec;
	80	//required_device<vcs_control_port_device> m_joy1;
	81	//required_device<vcs_control_port_device> m_joy2;
	82	//required_device<c64_expansion_slot_device> m_exp;
	83	//required_device<c64_user_port_device> m_user;
	84	//required_device<ram_device> m_ram;
	85	required_device<pet_datassette_port_device> m_cassette;
	86
	87	virtual void machine_start();
	88	virtual void machine_reset();
	89
	90	DECLARE_READ8_MEMBER( read_io );
	91	DECLARE_READ8_MEMBER( mmu8722_port_r );
	92	DECLARE_WRITE8_MEMBER( mmu8722_port_w );
	93	DECLARE_READ8_MEMBER( mmu8722_ff00_r );
	94	DECLARE_WRITE8_MEMBER( mmu8722_ff00_w );
	95	DECLARE_READ8_MEMBER( dma8726_port_r );
	96	DECLARE_WRITE8_MEMBER( dma8726_port_w );
	97	DECLARE_WRITE8_MEMBER( write_0000 );
	98	DECLARE_WRITE8_MEMBER( write_1000 );
	99	DECLARE_WRITE8_MEMBER( write_4000 );
	100	DECLARE_WRITE8_MEMBER( write_8000 );
	101	DECLARE_WRITE8_MEMBER( write_a000 );
	102	DECLARE_WRITE8_MEMBER( write_c000 );
	103	DECLARE_WRITE8_MEMBER( write_d000 );
	104	DECLARE_WRITE8_MEMBER( write_e000 );
	105	DECLARE_WRITE8_MEMBER( write_ff00 );
	106	DECLARE_WRITE8_MEMBER( write_ff05 );
	107
26	108	DECLARE_READ8_MEMBER( vic_lightpen_x_cb );
27	109	DECLARE_READ8_MEMBER( vic_lightpen_y_cb );
28	110	DECLARE_READ8_MEMBER( vic_lightpen_button_cb );
r17732	r17733
34	116	DECLARE_READ8_MEMBER( sid_potx_r );
35	117	DECLARE_READ8_MEMBER( sid_poty_r );
36	118
	119	DECLARE_WRITE_LINE_MEMBER( cia1_irq_w );
	120	DECLARE_WRITE_LINE_MEMBER( cia1_cnt_w );
	121	DECLARE_WRITE_LINE_MEMBER( cia1_sp_w );
	122	DECLARE_READ8_MEMBER( cia1_pa_r );
	123	DECLARE_READ8_MEMBER( cia1_pb_r );
	124	DECLARE_WRITE8_MEMBER( cia1_pb_w );
	125
	126	DECLARE_WRITE_LINE_MEMBER( cia2_irq_w );
	127	DECLARE_READ8_MEMBER( cia2_pa_r );
	128	DECLARE_WRITE8_MEMBER( cia2_pa_w );
	129
	130	DECLARE_WRITE_LINE_MEMBER( iec_srq_w );
	131	DECLARE_WRITE_LINE_MEMBER( iec_data_w );
	132
	133	DECLARE_READ8_MEMBER( cpu_r );
	134	DECLARE_WRITE8_MEMBER( cpu_w );
	135
	136	void nmi();
	137	void irq(int level);
	138	void iec_data_out_w();
	139	void iec_srq_out_w();
	140	void bankswitch_64(int reset);
	141	void bankswitch_z80();
	142	void bankswitch_128(int reset);
	143	void bankswitch(int reset);
	144	void mmu8722_reset();
	145
37	146	UINT8 *m_c128_basic;
38	147	UINT8 *m_c128_kernal;
39	148	UINT8 *m_c128_chargen;

trunk/src/mess/drivers/c128.c

r17732	r17733
211	211	* 0x0000-0xedff ram (dram bank 1?)
212	212	* 0xe000-0xffff ram as bank 0
213	213	*/
214		static ADDRESS_MAP_START(c128_z80_mem , AS_PROGRAM, 8, c128_state )
215		#if 1
216		AM_RANGE(0x0000, 0x0fff) AM_READ_BANK("bank10") AM_WRITE_LEGACY(c128_write_0000)
217		AM_RANGE(0x1000, 0xbfff) AM_READ_BANK("bank11") AM_WRITE_LEGACY(c128_write_1000)
	214	//**************************************************************************
	215	//  ADDRESS MAPS
	216	//**************************************************************************
	217
	218	//-------------------------------------------------
	219	//  ADDRESS_MAP( z80_mem )
	220	//-------------------------------------------------
	221
	222	static ADDRESS_MAP_START( z80_mem, AS_PROGRAM, 8, c128_state )
	223	AM_RANGE(0x0000, 0x0fff) AM_READ_BANK("bank10") AM_WRITE(write_0000)
	224	AM_RANGE(0x1000, 0xbfff) AM_READ_BANK("bank11") AM_WRITE(write_1000)
218	225	AM_RANGE(0xc000, 0xffff) AM_RAM
219		#else
220		/* best to do reuse bankswitching numbers */
221		AM_RANGE(0x0000, 0x03ff) AM_READ_BANK("bank10") AM_WRITE_BANK("bank1")
222		AM_RANGE(0x0400, 0x0fff) AM_READ_BANK("bank11") AM_WRITE_BANK("bank2")
223		AM_RANGE(0x1000, 0x1fff) AM_RAMBANK("bank3")
224		AM_RANGE(0x2000, 0x3fff) AM_RAMBANK("bank4")
225		AM_RANGE(0x4000, 0xbfff) AM_RAMBANK("bank5")
226		AM_RANGE(0xc000, 0xdfff) AM_RAMBANK("bank6")
227		AM_RANGE(0xe000, 0xefff) AM_RAMBANK("bank7")
228		AM_RANGE(0xf000, 0xfeff) AM_RAMBANK("bank8")
229		AM_RANGE(0xff00, 0xff04) AM_READWRITE_LEGACY(c128_mmu8722_ff00_r, c128_mmu8722_ff00_w)
230		AM_RANGE(0xff05, 0xffff) AM_RAMBANK("bank9")
231		#endif
232
233		#if 0
234		AM_RANGE(0x10000, 0x1ffff) AM_WRITEONLY
235		AM_RANGE(0x20000, 0xfffff) AM_WRITEONLY      /* or nothing */
236		AM_RANGE(0x100000, 0x107fff) AM_SHARE("c128_basic")   /* maps to 0x4000 */
237		AM_RANGE(0x108000, 0x109fff) AM_SHARE("basic")   /* maps to 0xa000 */
238		AM_RANGE(0x10a000, 0x10bfff) AM_SHARE("kernal")   /* maps to 0xe000 */
239		AM_RANGE(0x10c000, 0x10cfff) AM_SHARE("editor")
240		AM_RANGE(0x10d000, 0x10dfff) AM_SHARE("z80")      /* maps to z80 0 */
241		AM_RANGE(0x10e000, 0x10ffff) AM_SHARE("c128_kernal")
242		AM_RANGE(0x110000, 0x117fff) AM_SHARE("internal_function")
243		AM_RANGE(0x118000, 0x11ffff) AM_SHARE("external_function")
244		AM_RANGE(0x120000, 0x120fff) AM_SHARE("chargen")
245		AM_RANGE(0x121000, 0x121fff) AM_SHARE("c128_chargen")
246		AM_RANGE(0x122000, 0x1227ff) AM_SHARE("colorram")
247		AM_RANGE(0x122800, 0x1327ff) AM_SHARE("vdcram")
248		/* 2 kbyte by 8 bits, only 1 kbyte by 4 bits used) */
249		#endif
250	226	ADDRESS_MAP_END
251	227
252		static ADDRESS_MAP_START( c128_z80_io , AS_IO, 8, c128_state )
	228
	229	//-------------------------------------------------
	230	//  ADDRESS_MAP( z80_io )
	231	//-------------------------------------------------
	232
	233	static ADDRESS_MAP_START( z80_io, AS_IO, 8, c128_state )
253	234	AM_RANGE(0x1000, 0x13ff) AM_READWRITE_LEGACY(c64_colorram_read, c64_colorram_write)
254		AM_RANGE(0xd000, 0xd3ff) AM_DEVREADWRITE("vic2e", mos6566_device, read, write)
255		AM_RANGE(0xd400, 0xd4ff) AM_DEVREADWRITE_LEGACY("sid6581", sid6581_r, sid6581_w)
256		AM_RANGE(0xd500, 0xd5ff) AM_READWRITE_LEGACY(c128_mmu8722_port_r, c128_mmu8722_port_w)
257		//AM_RANGE(0xd600, 0xd7ff) AM_DEVREADWRITE_LEGACY("vdc8563", vdc8563_port_r, vdc8563_port_w)
258		AM_RANGE(0xd600, 0xd600) AM_MIRROR(0x1fe) AM_DEVREADWRITE("vdc8563", mos8563_device, status_r, address_w)
259		AM_RANGE(0xd601, 0xd601) AM_MIRROR(0x1fe) AM_DEVREADWRITE("vdc8563", mos8563_device, register_r, register_w)
260		AM_RANGE(0xdc00, 0xdcff) AM_DEVREADWRITE_LEGACY("cia_0", mos6526_r, mos6526_w)
261		AM_RANGE(0xdd00, 0xddff) AM_DEVREADWRITE_LEGACY("cia_1", mos6526_r, mos6526_w)
	235	AM_RANGE(0xd000, 0xd3ff) AM_DEVREADWRITE(MOS8564_TAG, mos6566_device, read, write)
	236	AM_RANGE(0xd400, 0xd4ff) AM_DEVREADWRITE_LEGACY(MOS6581_TAG, sid6581_r, sid6581_w)
	237	AM_RANGE(0xd500, 0xd5ff) AM_READWRITE(mmu8722_port_r, mmu8722_port_w)
	238	//AM_RANGE(0xd600, 0xd7ff) AM_DEVREADWRITE_LEGACY(MOS8563_TAG, vdc8563_port_r, vdc8563_port_w)
	239	AM_RANGE(0xd600, 0xd600) AM_MIRROR(0x1fe) AM_DEVREADWRITE(MOS8563_TAG, mos8563_device, status_r, address_w)
	240	AM_RANGE(0xd601, 0xd601) AM_MIRROR(0x1fe) AM_DEVREADWRITE(MOS8563_TAG, mos8563_device, register_r, register_w)
	241	AM_RANGE(0xdc00, 0xdcff) AM_DEVREADWRITE_LEGACY(MOS6526_1_TAG, mos6526_r, mos6526_w)
	242	AM_RANGE(0xdd00, 0xddff) AM_DEVREADWRITE_LEGACY(MOS6526_2_TAG, mos6526_r, mos6526_w)
262	243	/*  AM_RANGE(0xdf00, 0xdfff) AM_READWRITE_LEGACY(dma_port_r, dma_port_w) */
263	244	ADDRESS_MAP_END
264	245
265		static ADDRESS_MAP_START( c128_mem, AS_PROGRAM, 8, c128_state )
	246
	247	//-------------------------------------------------
	248	//  ADDRESS_MAP( m8502_mem )
	249	//-------------------------------------------------
	250
	251	static ADDRESS_MAP_START( m8502_mem, AS_PROGRAM, 8, c128_state )
266	252	AM_RANGE(0x0000, 0x00ff) AM_RAMBANK("bank1")
267	253	AM_RANGE(0x0100, 0x01ff) AM_RAMBANK("bank2")
268	254	AM_RANGE(0x0200, 0x03ff) AM_RAMBANK("bank3")
r17732	r17733
270	256	AM_RANGE(0x1000, 0x1fff) AM_RAMBANK("bank5")
271	257	AM_RANGE(0x2000, 0x3fff) AM_RAMBANK("bank6")
272	258
273		AM_RANGE(0x4000, 0x7fff) AM_READ_BANK( "bank7") AM_WRITE_LEGACY(c128_write_4000 )
274		AM_RANGE(0x8000, 0x9fff) AM_READ_BANK( "bank8") AM_WRITE_LEGACY(c128_write_8000 )
275		AM_RANGE(0xa000, 0xbfff) AM_READ_BANK( "bank9") AM_WRITE_LEGACY(c128_write_a000 )
	259	AM_RANGE(0x4000, 0x7fff) AM_READ_BANK( "bank7") AM_WRITE(write_4000 )
	260	AM_RANGE(0x8000, 0x9fff) AM_READ_BANK( "bank8") AM_WRITE(write_8000 )
	261	AM_RANGE(0xa000, 0xbfff) AM_READ_BANK( "bank9") AM_WRITE(write_a000 )
276	262
277		AM_RANGE(0xc000, 0xcfff) AM_READ_BANK( "bank12") AM_WRITE_LEGACY(c128_write_c000 )
278		AM_RANGE(0xd000, 0xdfff) AM_READ_BANK( "bank13") AM_WRITE_LEGACY(c128_write_d000 )
279		AM_RANGE(0xe000, 0xfeff) AM_READ_BANK( "bank14") AM_WRITE_LEGACY(c128_write_e000 )
280		AM_RANGE(0xff00, 0xff04) AM_READ_BANK( "bank15") AM_WRITE_LEGACY(c128_write_ff00 )      /* mmu c128 modus */
281		AM_RANGE(0xff05, 0xffff) AM_READ_BANK( "bank16") AM_WRITE_LEGACY(c128_write_ff05 )
	263	AM_RANGE(0xc000, 0xcfff) AM_READ_BANK( "bank12") AM_WRITE(write_c000 )
	264	AM_RANGE(0xd000, 0xdfff) AM_READ_BANK( "bank13") AM_WRITE(write_d000)
	265	AM_RANGE(0xe000, 0xfeff) AM_READ_BANK( "bank14") AM_WRITE(write_e000 )
	266	AM_RANGE(0xff00, 0xff04) AM_READ_BANK( "bank15") AM_WRITE(write_ff00 )      /* mmu c128 modus */
	267	AM_RANGE(0xff05, 0xffff) AM_READ_BANK( "bank16") AM_WRITE(write_ff05 )
282	268	ADDRESS_MAP_END
283	269
284	270
285		/*************************************
286		*
287		*  Input Ports
288		*
289		*************************************/
	271	//-------------------------------------------------
	272	//  ADDRESS_MAP( vic_videoram_map )
	273	//-------------------------------------------------
290	274
	275	static ADDRESS_MAP_START( vic_videoram_map, AS_0, 8, c128_state )
	276	AM_RANGE(0x0000, 0x3fff) AM_READ(vic_dma_read)
	277	ADDRESS_MAP_END
291	278
	279
	280	//-------------------------------------------------
	281	//  ADDRESS_MAP( vic_colorram_map )
	282	//-------------------------------------------------
	283
	284	static ADDRESS_MAP_START( vic_colorram_map, AS_1, 8, c128_state )
	285	AM_RANGE(0x000, 0x3ff) AM_READ(vic_dma_read_color)
	286	ADDRESS_MAP_END
	287
	288
	289	//-------------------------------------------------
	290	//  ADDRESS_MAP( vdc_videoram_map )
	291	//-------------------------------------------------
	292
	293	static ADDRESS_MAP_START( vdc_videoram_map, AS_0, 8, c128_state )
	294	AM_RANGE(0x0000, 0xffff) AM_RAM
	295	ADDRESS_MAP_END
	296
	297
	298
	299	//**************************************************************************
	300	//  INPUT PORTS
	301	//**************************************************************************
	302
	303	//-------------------------------------------------
	304	//  INPUT_PORTS( c128 )
	305	//-------------------------------------------------
	306
292	307	static INPUT_PORTS_START( c128 )
293	308	PORT_INCLUDE( common_cbm_keyboard )      /* ROW0 -> ROW7 */
294	309
r17732	r17733
330	345	INPUT_PORTS_END
331	346
332	347
	348	//-------------------------------------------------
	349	//  INPUT_PORTS( c128ger )
	350	//-------------------------------------------------
	351
333	352	static INPUT_PORTS_START( c128ger )
334	353	PORT_INCLUDE( c128 )
335	354
r17732	r17733
370	389	INPUT_PORTS_END
371	390
372	391
	392	//-------------------------------------------------
	393	//  INPUT_PORTS( c128fra )
	394	//-------------------------------------------------
	395
373	396	static INPUT_PORTS_START( c128fra )
374	397	PORT_INCLUDE( c128 )
375	398
r17732	r17733
423	446	INPUT_PORTS_END
424	447
425	448
	449	//-------------------------------------------------
	450	//  INPUT_PORTS( c128ita )
	451	//-------------------------------------------------
	452
426	453	static INPUT_PORTS_START( c128ita )
427	454	PORT_INCLUDE( c128 )
428	455
r17732	r17733
473	500	INPUT_PORTS_END
474	501
475	502
	503	//-------------------------------------------------
	504	//  INPUT_PORTS( c128swe )
	505	//-------------------------------------------------
	506
476	507	static INPUT_PORTS_START( c128swe )
477	508	PORT_INCLUDE( c128 )
478	509
r17732	r17733
503	534	PORT_CONFSETTING( 0x20, "Swedish/Finnish" )
504	535	INPUT_PORTS_END
505	536
506		/*************************************
507		*
508		*  Sound definitions
509		*
510		*************************************/
511	537
512	538
513		READ8_MEMBER( c128_state::sid_potx_r )
514		{
515		device_t *sid = machine().device("sid6581");
	539	//**************************************************************************
	540	//  DEVICE CONFIGURATION
	541	//**************************************************************************
516	542
517		return c64_paddle_read(sid, 0);
518		}
	543	//-------------------------------------------------
	544	//  MOS8564_INTERFACE( vic_intf )
	545	//-------------------------------------------------
519	546
520		READ8_MEMBER( c128_state::sid_poty_r )
521		{
522		device_t *sid = machine().device("sid6581");
523
524		return c64_paddle_read(sid, 1);
525		}
526
527		static const sid6581_interface c128_sound_interface =
528		{
529		DEVCB_DRIVER_MEMBER(c128_state, sid_potx_r),
530		DEVCB_DRIVER_MEMBER(c128_state, sid_poty_r)
531		};
532
533
534		static M6510_INTERFACE( c128_m8502_interface )
535		{
536		DEVCB_NULL,               /* read_indexed_func */
537		DEVCB_NULL,               /* write_indexed_func */
538		DEVCB_HANDLER(c128_m6510_port_read),   /* port_read_func */
539		DEVCB_HANDLER(c128_m6510_port_write),   /* port_write_func */
540		0x07,
541		0x20
542		};
543
544		static CBM_IEC_INTERFACE( cbm_iec_intf )
545		{
546		DEVCB_DEVICE_LINE("cia_0", c128_iec_srq_w),
547		DEVCB_NULL,
548		DEVCB_NULL,
549		DEVCB_DEVICE_LINE("cia_0", c128_iec_data_w),
550		DEVCB_NULL
551		};
552
553		/*************************************
554		*
555		*  VIC II / VDC interfaces
556		*
557		*************************************/
558
559	547	READ8_MEMBER( c128_state::vic_lightpen_x_cb )
560	548	{
561	549	return ioport("LIGHTX")->read() & ~0x01;
r17732	r17733
576	564	return ioport("CTRLSEL")->read() & 0x08;
577	565	}
578	566
579		static ADDRESS_MAP_START( vic_videoram_map, AS_0, 8, c128_state )
580		AM_RANGE(0x0000, 0x3fff) AM_READ(vic_dma_read)
581		ADDRESS_MAP_END
582
583		static ADDRESS_MAP_START( vic_colorram_map, AS_1, 8, c128_state )
584		AM_RANGE(0x000, 0x3ff) AM_READ(vic_dma_read_color)
585		ADDRESS_MAP_END
586
587	567	static MOS8564_INTERFACE( vic_intf )
588	568	{
589		"screen",
590		"maincpu",
	569	SCREEN_VIC_TAG,
	570	Z80A_TAG,
591	571	DEVCB_DRIVER_LINE_MEMBER(c128_state, vic_interrupt),
592	572	DEVCB_NULL,
593	573	DEVCB_DRIVER_MEMBER(c128_state, vic_lightpen_x_cb),
r17732	r17733
596	576	DEVCB_DRIVER_MEMBER(c128_state, vic_rdy_cb)
597	577	};
598	578
	579
	580	//-------------------------------------------------
	581	//  mc6845_interface vdc_intf
	582	//-------------------------------------------------
	583
599	584	static MC6845_UPDATE_ROW( vdc_update_row )
600	585	{
601	586	mos8563_device *mos8563 = static_cast<mos8563_device *>(device);
r17732	r17733
605	590
606	591	static const mc6845_interface vdc_intf =
607	592	{
608		"screen80",
	593	SCREEN_VDC_TAG,
609	594	8,
610	595	NULL,
611	596	vdc_update_row,
r17732	r17733
617	602	NULL
618	603	};
619	604
620		static ADDRESS_MAP_START( vdc_videoram_map, AS_0, 8, c128_state )
621		AM_RANGE(0x0000, 0xffff) AM_RAM
622		ADDRESS_MAP_END
623	605
624		/*************************************
	606	//-------------------------------------------------
	607	//  sid6581_interface sid_intf
	608	//-------------------------------------------------
625	609
626		*
627		*  Machine driver
628		*
629		*************************************/
	610	READ8_MEMBER( c128_state::sid_potx_r )
	611	{
	612	return c64_paddle_read(m_sid, 0);
	613	}
630	614
	615	READ8_MEMBER( c128_state::sid_poty_r )
	616	{
	617	return c64_paddle_read(m_sid, 1);
	618	}
	619
	620	static const sid6581_interface sid_intf =
	621	{
	622	DEVCB_DRIVER_MEMBER(c128_state, sid_potx_r),
	623	DEVCB_DRIVER_MEMBER(c128_state, sid_poty_r)
	624	};
	625
	626
	627	//-------------------------------------------------
	628	//  M6510_INTERFACE( cpu_intf )
	629	//-------------------------------------------------
	630
	631	static M6510_INTERFACE( cpu_intf )
	632	{
	633	DEVCB_NULL,               /* read_indexed_func */
	634	DEVCB_NULL,               /* write_indexed_func */
	635	DEVCB_DRIVER_MEMBER(c128_state, cpu_r),   /* port_read_func */
	636	DEVCB_DRIVER_MEMBER(c128_state, cpu_w),   /* port_write_func */
	637	0x07,
	638	0x20
	639	};
	640
	641	//-------------------------------------------------
	642	//  CBM_IEC_INTERFACE( cbm_iec_intf )
	643	//-------------------------------------------------
	644
	645	static CBM_IEC_INTERFACE( cbm_iec_intf )
	646	{
	647	DEVCB_DRIVER_LINE_MEMBER(c128_state, iec_srq_w),
	648	DEVCB_NULL,
	649	DEVCB_NULL,
	650	DEVCB_DRIVER_LINE_MEMBER(c128_state, iec_data_w),
	651	DEVCB_NULL
	652	};
	653
	654
	655	//-------------------------------------------------
	656	//  PET_DATASSETTE_PORT_INTERFACE( datassette_intf )
	657	//-------------------------------------------------
	658
	659	static PET_DATASSETTE_PORT_INTERFACE( datassette_intf )
	660	{
	661	DEVCB_DEVICE_LINE(MOS6526_1_TAG, mos6526_flag_w)
	662	};
	663
	664
	665
	666	//**************************************************************************
	667	//  MACHINE DRIVERS
	668	//**************************************************************************
	669
	670	//-------------------------------------------------
	671	//  MACHINE_CONFIG( ntsc )
	672	//-------------------------------------------------
	673
631	674	static MACHINE_CONFIG_START( ntsc, c128_state )
632	675	/* basic machine hardware */
633		MCFG_CPU_ADD("maincpu", Z80, VIC6567_CLOCK)
634		MCFG_CPU_PROGRAM_MAP( c128_z80_mem)
635		MCFG_CPU_IO_MAP( c128_z80_io)
636		MCFG_CPU_VBLANK_INT("screen", c128_frame_interrupt)
	676	MCFG_CPU_ADD(Z80A_TAG, Z80, VIC6567_CLOCK)
	677	MCFG_CPU_PROGRAM_MAP( z80_mem)
	678	MCFG_CPU_IO_MAP( z80_io)
	679	MCFG_CPU_VBLANK_INT(SCREEN_VIC_TAG, c128_frame_interrupt)
637	680	//MCFG_CPU_PERIODIC_INT(vic2_raster_irq, VIC6567_HRETRACERATE)
638	681
639		MCFG_CPU_ADD("m8502", M8502, VIC6567_CLOCK)
640		MCFG_CPU_PROGRAM_MAP( c128_mem)
641		MCFG_CPU_CONFIG( c128_m8502_interface )
642		MCFG_CPU_VBLANK_INT("screen", c128_frame_interrupt)
	682	MCFG_CPU_ADD(M8502_TAG, M8502, VIC6567_CLOCK)
	683	MCFG_CPU_PROGRAM_MAP( m8502_mem)
	684	MCFG_CPU_CONFIG( cpu_intf )
	685	MCFG_CPU_VBLANK_INT(SCREEN_VIC_TAG, c128_frame_interrupt)
643	686	// MCFG_CPU_PERIODIC_INT(vic2_raster_irq, VIC6567_HRETRACERATE)
644	687
645		MCFG_MACHINE_START( c128 )
646		MCFG_MACHINE_RESET( c128 )
647
648	688	/* video hardware */
649		MCFG_MOS8564_ADD("vic2e", "screen", VIC6567_CLOCK, vic_intf, vic_videoram_map, vic_colorram_map)
650		MCFG_MOS8563_ADD("vdc8563", "screen80", 2000000, vdc_intf, vdc_videoram_map)
	689	MCFG_MOS8564_ADD(MOS8564_TAG, SCREEN_VIC_TAG, VIC6567_CLOCK, vic_intf, vic_videoram_map, vic_colorram_map)
	690	MCFG_MOS8563_ADD(MOS8563_TAG, SCREEN_VDC_TAG, 2000000, vdc_intf, vdc_videoram_map)
651	691
652	692	/* sound hardware */
653	693	MCFG_SPEAKER_STANDARD_MONO("mono")
654		MCFG_SOUND_ADD("sid6581", SID6581, VIC6567_CLOCK)
655		MCFG_SOUND_CONFIG(c128_sound_interface)
	694	MCFG_SOUND_ADD(MOS6581_TAG, SID6581, VIC6567_CLOCK)
	695	MCFG_SOUND_CONFIG(sid_intf)
656	696	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.50)
657	697	MCFG_SOUND_ADD("dac", DAC, 0)
658	698	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.25)
r17732	r17733
661	701	MCFG_QUICKLOAD_ADD("quickload", cbm_c64, "p00,prg", CBM_QUICKLOAD_DELAY_SECONDS)
662	702
663	703	/* cassette */
664		MCFG_CASSETTE_ADD( CASSETTE_TAG, cbm_cassette_interface )
	704	MCFG_PET_DATASSETTE_PORT_ADD(PET_DATASSETTE_PORT_TAG, datassette_intf, cbm_datassette_devices, "c1530", NULL)
665	705
666	706	/* cia */
667		MCFG_MOS6526R1_ADD("cia_0", VIC6567_CLOCK, c128_ntsc_cia0)
668		MCFG_MOS6526R1_ADD("cia_1", VIC6567_CLOCK, c128_ntsc_cia1)
	707	MCFG_MOS6526R1_ADD(MOS6526_1_TAG, VIC6567_CLOCK, c128_ntsc_cia0)
	708	MCFG_MOS6526R1_ADD(MOS6526_2_TAG, VIC6567_CLOCK, c128_ntsc_cia1)
669	709
670	710	MCFG_FRAGMENT_ADD(c64_cartslot)
671	711	MCFG_SOFTWARE_LIST_ADD("c64_disk_list", "c64_flop")
672	712	MCFG_SOFTWARE_LIST_ADD("c128_disk_list", "c128_flop")
673	713	MACHINE_CONFIG_END
674	714
	715
	716	//-------------------------------------------------
	717	//  MACHINE_CONFIG( c128 )
	718	//-------------------------------------------------
	719
675	720	static MACHINE_CONFIG_DERIVED( c128, ntsc )
676	721	MCFG_CBM_IEC_ADD(cbm_iec_intf, "c1571")
677	722	MACHINE_CONFIG_END
678	723
	724
	725	//-------------------------------------------------
	726	//  MACHINE_CONFIG( c128d )
	727	//-------------------------------------------------
679	728	static MACHINE_CONFIG_DERIVED( c128d, ntsc )
680	729	MCFG_CBM_IEC_ADD(cbm_iec_intf, "c1571")
681	730	MACHINE_CONFIG_END
682	731
	732
	733	//-------------------------------------------------
	734	//  MACHINE_CONFIG( c128dcr )
	735	//-------------------------------------------------
	736
683	737	static MACHINE_CONFIG_DERIVED( c128dcr, ntsc )
684	738	MCFG_CBM_IEC_BUS_ADD(cbm_iec_intf)
685	739	MCFG_CBM_IEC_SLOT_ADD("iec4", 4, cbm_iec_devices, NULL, NULL)
r17732	r17733
689	743	MCFG_CBM_IEC_SLOT_ADD("iec11", 11, cbm_iec_devices, NULL, NULL)
690	744	MACHINE_CONFIG_END
691	745
	746
	747	//-------------------------------------------------
	748	//  MACHINE_CONFIG( c128d81 )
	749	//-------------------------------------------------
	750
692	751	static MACHINE_CONFIG_DERIVED( c128d81, ntsc )
693	752	MCFG_CBM_IEC_BUS_ADD(cbm_iec_intf)
694	753	MCFG_CBM_IEC_SLOT_ADD("iec4", 4, cbm_iec_devices, NULL, NULL)
r17732	r17733
698	757	MCFG_CBM_IEC_SLOT_ADD("iec11", 11, cbm_iec_devices, NULL, NULL)
699	758	MACHINE_CONFIG_END
700	759
	760
	761	//-------------------------------------------------
	762	//  MACHINE_CONFIG( ntsc )
	763	//-------------------------------------------------
	764
701	765	static MACHINE_CONFIG_START( pal, c128_state )
702	766	/* basic machine hardware */
703		MCFG_CPU_ADD("maincpu", Z80, VIC6569_CLOCK)
704		MCFG_CPU_PROGRAM_MAP( c128_z80_mem)
705		MCFG_CPU_IO_MAP( c128_z80_io)
706		MCFG_CPU_VBLANK_INT("screen", c128_frame_interrupt)
	767	MCFG_CPU_ADD(Z80A_TAG, Z80, VIC6569_CLOCK)
	768	MCFG_CPU_PROGRAM_MAP( z80_mem)
	769	MCFG_CPU_IO_MAP( z80_io)
	770	MCFG_CPU_VBLANK_INT(SCREEN_VIC_TAG, c128_frame_interrupt)
707	771	//MCFG_CPU_PERIODIC_INT(vic2_raster_irq, VIC6569_HRETRACERATE)
708	772
709		MCFG_CPU_ADD("m8502", M8502, VIC6569_CLOCK)
710		MCFG_CPU_PROGRAM_MAP( c128_mem)
711		MCFG_CPU_CONFIG( c128_m8502_interface )
712		MCFG_CPU_VBLANK_INT("screen", c128_frame_interrupt)
	773	MCFG_CPU_ADD(M8502_TAG, M8502, VIC6569_CLOCK)
	774	MCFG_CPU_PROGRAM_MAP( m8502_mem)
	775	MCFG_CPU_CONFIG( cpu_intf )
	776	MCFG_CPU_VBLANK_INT(SCREEN_VIC_TAG, c128_frame_interrupt)
713	777	// MCFG_CPU_PERIODIC_INT(vic2_raster_irq, VIC6569_HRETRACERATE)
714	778
715		MCFG_MACHINE_START( c128 )
716		MCFG_MACHINE_RESET( c128 )
717
718	779	/* video hardware */
719		MCFG_MOS8566_ADD("vic2e", "screen", VIC6569_CLOCK, vic_intf, vic_videoram_map, vic_colorram_map)
720		MCFG_MOS8563_ADD("vdc8563", "screen80", 2000000, vdc_intf, vdc_videoram_map)
	780	MCFG_MOS8566_ADD(MOS8566_TAG, SCREEN_VIC_TAG, VIC6569_CLOCK, vic_intf, vic_videoram_map, vic_colorram_map)
	781	MCFG_MOS8563_ADD(MOS8563_TAG, SCREEN_VDC_TAG, 2000000, vdc_intf, vdc_videoram_map)
721	782
722	783	/* sound hardware */
723	784	MCFG_SPEAKER_STANDARD_MONO("mono")
724		MCFG_SOUND_ADD("sid6581", SID6581, VIC6569_CLOCK)
725		MCFG_SOUND_CONFIG(c128_sound_interface)
	785	MCFG_SOUND_ADD(MOS6581_TAG, SID6581, VIC6569_CLOCK)
	786	MCFG_SOUND_CONFIG(sid_intf)
726	787	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.50)
727	788	MCFG_SOUND_ADD("dac", DAC, 0)
728	789	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.25)
r17732	r17733
731	792	MCFG_QUICKLOAD_ADD("quickload", cbm_c64, "p00,prg", CBM_QUICKLOAD_DELAY_SECONDS)
732	793
733	794	/* cassette */
734		MCFG_CASSETTE_ADD( CASSETTE_TAG, cbm_cassette_interface )
	795	MCFG_PET_DATASSETTE_PORT_ADD(PET_DATASSETTE_PORT_TAG, datassette_intf, cbm_datassette_devices, "c1530", NULL)
735	796
736	797	/* cia */
737		MCFG_MOS6526R1_ADD("cia_0", VIC6569_CLOCK, c128_ntsc_cia0)
738		MCFG_MOS6526R1_ADD("cia_1", VIC6569_CLOCK, c128_ntsc_cia1)
	798	MCFG_MOS6526R1_ADD(MOS6526_1_TAG, VIC6569_CLOCK, c128_ntsc_cia0)
	799	MCFG_MOS6526R1_ADD(MOS6526_2_TAG, VIC6569_CLOCK, c128_ntsc_cia1)
739	800
740	801	MCFG_FRAGMENT_ADD(c64_cartslot)
741	802	MCFG_SOFTWARE_LIST_ADD("c64_disk_list", "c64_flop")
742	803	MCFG_SOFTWARE_LIST_ADD("c128_disk_list", "c128_flop")
743	804	MACHINE_CONFIG_END
744	805
	806
	807	//-------------------------------------------------
	808	//  MACHINE_CONFIG( c128pal )
	809	//-------------------------------------------------
	810
745	811	static MACHINE_CONFIG_DERIVED( c128pal, pal )
746	812	MCFG_CBM_IEC_ADD(cbm_iec_intf, "c1571")
747	813	MACHINE_CONFIG_END
748	814
	815
	816	//-------------------------------------------------
	817	//  MACHINE_CONFIG( c128dpal )
	818	//-------------------------------------------------
	819
749	820	static MACHINE_CONFIG_DERIVED( c128dpal, pal )
750	821	MCFG_CBM_IEC_ADD(cbm_iec_intf, "c1571")
751	822	MACHINE_CONFIG_END
752	823
	824
	825	//-------------------------------------------------
	826	//  MACHINE_CONFIG( c128dcrp )
	827	//-------------------------------------------------
	828
753	829	static MACHINE_CONFIG_DERIVED( c128dcrp, pal )
754	830	MCFG_CBM_IEC_BUS_ADD(cbm_iec_intf)
755	831	MCFG_CBM_IEC_SLOT_ADD("iec4", 4, cbm_iec_devices, NULL, NULL)
r17732	r17733
761	837
762	838
763	839
764		/*************************************
765		*
766		*  ROM definition(s)
767		*
768		*************************************/
	840	//**************************************************************************
	841	//  ROMS
	842	//**************************************************************************
769	843
	844	//-------------------------------------------------
	845	//  ROM( c128 )
	846	//-------------------------------------------------
770	847
771	848	ROM_START( c128 )
772		ROM_REGION( 0x132800, "maincpu", 0 )
	849	ROM_REGION( 0x132800, Z80A_TAG, 0 )
773	850	ROM_DEFAULT_BIOS("r1")
774	851	ROM_SYSTEM_BIOS( 0, "r0", "rev. 0" )
775	852	ROMX_LOAD( "318018-02.bin", 0x100000, 0x4000, CRC(2ee6e2fa) SHA1(60e1491e1d5782e3cf109f518eb73427609badc6), ROM_BIOS(1) )         // BASIC lo
r17732	r17733
787	864	ROM_LOAD( "251913-01.bin", 0x108000, 0x4000, CRC(0010ec31) SHA1(765372a0e16cbb0adf23a07b80f6b682b39fbf88) )      // C64 OS ROM
788	865	ROM_LOAD( "390059-01.bin", 0x120000, 0x2000, CRC(6aaaafe6) SHA1(29ed066d513f2d5c09ff26d9166ba23c2afb2b3f) )      // Character
789	866
790		ROM_REGION( 0x10000, "m8502", ROMREGION_ERASEFF )
791		ROM_REGION( 0x2000, "gfx1", ROMREGION_ERASEFF )
792		ROM_REGION( 0x100, "gfx2", ROMREGION_ERASEFF )
	867	ROM_REGION( 0x10000, M8502_TAG, ROMREGION_ERASEFF )
793	868	ROM_END
794	869
795	870
	871	//-------------------------------------------------
	872	//  ROM( c128cr )
	873	//-------------------------------------------------
	874
796	875	ROM_START( c128cr )
797	876	/* C128CR prototype, owned by Bo Zimmers
798	877	PCB markings: "COMMODORE 128CR REV.3 // PCB NO.252270" and "PCB ASSY NO.250783"
r17732	r17733
801	880	6526A-1 CIAs
802	881	?prototype? 2568R1X VDC w/ 1186 datecode
803	882	*/
804		ROM_REGION( 0x132800, "maincpu", 0 )
	883	ROM_REGION( 0x132800, Z80A_TAG, 0 )
805	884	ROM_LOAD( "252343-03.u34", 0x100000, 0x8000, CRC(bc07ed87) SHA1(0eec437994a3f2212343a712847213a8a39f4a7b) )         // BASIC lo + hi, "252343-03 // U34"
806	885	ROM_LOAD( "252343-04.u32", 0x108000, 0x8000, CRC(cc6bdb69) SHA1(36286b2e8bea79f7767639fd85e12c5447c7041b) )         // C64 OS ROM + Kernal, "252343-04 // US // U32"
807	886	ROM_LOAD( "390059-01.u18", 0x120000, 0x2000, CRC(6aaaafe6) SHA1(29ed066d513f2d5c09ff26d9166ba23c2afb2b3f) )         // Character, "MOS // (C)1985 CBM // 390059-01 // M468613 8547H"
808	887
809		ROM_REGION( 0x10000, "m8502", ROMREGION_ERASEFF )
810		ROM_REGION( 0x2000, "gfx1", ROMREGION_ERASEFF )
811		ROM_REGION( 0x100, "gfx2", ROMREGION_ERASEFF )
	888	ROM_REGION( 0x10000, M8502_TAG, ROMREGION_ERASEFF )
812	889	ROM_END
813	890
814	891
815		/* See notes at the top of the driver about PAL dumps */
	892	//-------------------------------------------------
	893	//  ROM( c128ger )
	894	//-------------------------------------------------
816	895
817	896	ROM_START( c128ger )
818		ROM_REGION( 0x132800, "maincpu", 0 )
	897	ROM_REGION( 0x132800, Z80A_TAG, 0 )
819	898	ROM_SYSTEM_BIOS( 0, "default", "rev. 1" )
820	899	ROMX_LOAD( "318018-04.bin", 0x100000, 0x4000, CRC(9f9c355b) SHA1(d53a7884404f7d18ebd60dd3080c8f8d71067441), ROM_BIOS(1) )         // BASIC lo
821	900	ROMX_LOAD( "318019-04.bin", 0x104000, 0x4000, CRC(6e2c91a7) SHA1(c4fb4a714e48a7bf6c28659de0302183a0e0d6c0), ROM_BIOS(1) )         // BASIC hi
r17732	r17733
828	907	ROM_LOAD( "251913-01.bin", 0x108000, 0x4000, CRC(0010ec31) SHA1(765372a0e16cbb0adf23a07b80f6b682b39fbf88) )      // C64 OS ROM
829	908	ROM_LOAD( "390059-01.bin", 0x120000, 0x2000, CRC(6aaaafe6) SHA1(29ed066d513f2d5c09ff26d9166ba23c2afb2b3f) )      // Character
830	909
831		ROM_REGION( 0x10000, "m8502", ROMREGION_ERASEFF )
832		ROM_REGION( 0x2000, "gfx1", ROMREGION_ERASEFF )
833		ROM_REGION( 0x100, "gfx2", ROMREGION_ERASEFF )
	910	ROM_REGION( 0x10000, M8502_TAG, ROMREGION_ERASEFF )
834	911	ROM_END
835	912
	913
	914	//-------------------------------------------------
	915	//  ROM( c128sfi )
	916	//-------------------------------------------------
	917
836	918	ROM_START( c128sfi )
837		ROM_REGION( 0x132800, "maincpu", 0 )
	919	ROM_REGION( 0x132800, Z80A_TAG, 0 )
838	920	ROM_LOAD( "318018-02.u33", 0x100000, 0x4000, CRC(2ee6e2fa) SHA1(60e1491e1d5782e3cf109f518eb73427609badc6) )
839	921	ROM_LOAD( "318019-02.u34", 0x104000, 0x4000, CRC(d551fce0) SHA1(4d223883e866645328f86a904b221464682edc4f) )
840	922	ROM_LOAD( "325182-01.u32", 0x108000, 0x4000, CRC(2aff27d3) SHA1(267654823c4fdf2167050f41faa118218d2569ce) ) // C128 64 Sw/Fi
r17732	r17733
843	925	/* This was not included in the submission, unfortunately */
844	926	ROM_LOAD( "325181-02.u18", 0x120000, 0x2000, BAD_DUMP CRC(7a70d9b8) SHA1(aca3f7321ee7e6152f1f0afad646ae41964de4fb) ) // C128 Char Sw/Fi
845	927
846		ROM_REGION( 0x10000, "m8502", ROMREGION_ERASEFF )
847		ROM_REGION( 0x2000, "gfx1", ROMREGION_ERASEFF )
848		ROM_REGION( 0x100, "gfx2", ROMREGION_ERASEFF )
	928	ROM_REGION( 0x10000, M8502_TAG, ROMREGION_ERASEFF )
849	929	ROM_END
850	930
	931
	932	//-------------------------------------------------
	933	//  ROM( c128fra )
	934	//-------------------------------------------------
	935
851	936	ROM_START( c128fra )
852		ROM_REGION( 0x132800, "maincpu", 0 )
	937	ROM_REGION( 0x132800, Z80A_TAG, 0 )
853	938	ROM_LOAD( "318018-04.bin", 0x100000, 0x4000, BAD_DUMP CRC(9f9c355b) SHA1(d53a7884404f7d18ebd60dd3080c8f8d71067441) )         // BASIC lo
854	939	ROM_LOAD( "318019-04.bin", 0x104000, 0x4000, BAD_DUMP CRC(6e2c91a7) SHA1(c4fb4a714e48a7bf6c28659de0302183a0e0d6c0) )         // BASIC hi
855	940	ROM_LOAD( "251913-01.bin", 0x108000, 0x4000, BAD_DUMP CRC(0010ec31) SHA1(765372a0e16cbb0adf23a07b80f6b682b39fbf88) )         // C64 OS ROM
r17732	r17733
858	943	ROM_LOAD( "kernalpart.french.bin", 0x10e000, 0x2000, BAD_DUMP CRC(ca5e1179) SHA1(d234a031caf59a0f66871f2babe1644783e66cf7) )
859	944	ROM_LOAD( "325167-01.bin", 0x120000, 0x2000, BAD_DUMP CRC(bad36b88) SHA1(9119b27a1bf885fa4c76fff5d858c74c194dd2b8) )
860	945
861		ROM_REGION( 0x10000, "m8502", ROMREGION_ERASEFF )
862		ROM_REGION( 0x2000, "gfx1", ROMREGION_ERASEFF )
863		ROM_REGION( 0x100, "gfx2", ROMREGION_ERASEFF )
	946	ROM_REGION( 0x10000, M8502_TAG, ROMREGION_ERASEFF )
864	947	ROM_END
865	948
866	949
	950	//-------------------------------------------------
	951	//  ROM( c128nor )
	952	//-------------------------------------------------
	953
867	954	ROM_START( c128nor )
868		ROM_REGION( 0x132800, "maincpu", 0 )
	955	ROM_REGION( 0x132800, Z80A_TAG, 0 )
869	956	ROM_LOAD( "318018-04.bin", 0x100000, 0x4000, BAD_DUMP CRC(9f9c355b) SHA1(d53a7884404f7d18ebd60dd3080c8f8d71067441) )         // BASIC lo
870	957	ROM_LOAD( "318019-04.bin", 0x104000, 0x4000, BAD_DUMP CRC(6e2c91a7) SHA1(c4fb4a714e48a7bf6c28659de0302183a0e0d6c0) )         // BASIC hi
871	958	ROM_LOAD( "251913-01.bin", 0x108000, 0x4000, BAD_DUMP CRC(0010ec31) SHA1(765372a0e16cbb0adf23a07b80f6b682b39fbf88) )         // C64 OS ROM
r17732	r17733
875	962	/* standard vic20 based norwegian */
876	963	ROM_LOAD( "char.nor", 0x120000, 0x2000, BAD_DUMP CRC(ba95c625) SHA1(5a87faa457979e7b6f434251a9e32f4483b337b3) )
877	964
878		ROM_REGION( 0x10000, "m8502", ROMREGION_ERASEFF )
879		ROM_REGION( 0x2000, "gfx1", ROMREGION_ERASEFF )
880		ROM_REGION( 0x100, "gfx2", ROMREGION_ERASEFF )
	965	ROM_REGION( 0x10000, M8502_TAG, ROMREGION_ERASEFF )
881	966	ROM_END
882	967
883	968
	969	//-------------------------------------------------
	970	//  ROM( c128d )
	971	//-------------------------------------------------
	972
884	973	/* C128D Board is basically the same as C128 + a second board for the disk drive */
885	974	ROM_START( c128d )
886		ROM_REGION( 0x132800, "maincpu", 0 )
	975	ROM_REGION( 0x132800, Z80A_TAG, 0 )
887	976	ROM_LOAD( "318018-04.bin", 0x100000, 0x4000, CRC(9f9c355b) SHA1(d53a7884404f7d18ebd60dd3080c8f8d71067441) )         // BASIC lo
888	977	ROM_LOAD( "318019-04.bin", 0x104000, 0x4000, CRC(6e2c91a7) SHA1(c4fb4a714e48a7bf6c28659de0302183a0e0d6c0) )         // BASIC hi
889	978	ROM_LOAD( "251913-01.bin", 0x108000, 0x4000, CRC(0010ec31) SHA1(765372a0e16cbb0adf23a07b80f6b682b39fbf88) )         // C64 OS ROM
890	979	ROM_LOAD( "318020-05.bin", 0x10c000, 0x4000, CRC(ba456b8e) SHA1(ceb6e1a1bf7e08eb9cbc651afa29e26adccf38ab) )         // Kernal
891	980	ROM_LOAD( "390059-01.bin", 0x120000, 0x2000, CRC(6aaaafe6) SHA1(29ed066d513f2d5c09ff26d9166ba23c2afb2b3f) )
892	981
893		ROM_REGION( 0x10000, "m8502", ROMREGION_ERASEFF )
894		ROM_REGION( 0x2000, "gfx1", ROMREGION_ERASEFF )
895		ROM_REGION( 0x100, "gfx2", ROMREGION_ERASEFF )
	982	ROM_REGION( 0x10000, M8502_TAG, ROMREGION_ERASEFF )
896	983	ROM_END
897	984
	985
	986	//-------------------------------------------------
	987	//  ROM( c128dpr )
	988	//-------------------------------------------------
	989
898	990	#define rom_c128dpr      rom_c128d
899	991
	992
	993	//-------------------------------------------------
	994	//  ROM( c128dcr )
	995	//-------------------------------------------------
	996
900	997	/* This BIOS is exactly the same as C128 rev. 1, but on two ROMs only */
901	998	ROM_START( c128dcr )
902		ROM_REGION( 0x132800, "maincpu", 0 )
	999	ROM_REGION( 0x132800, Z80A_TAG, 0 )
903	1000	ROM_LOAD( "318022-02.bin", 0x100000, 0x8000, CRC(af1ae1e8) SHA1(953dcdf5784a6b39ef84dd6fd968c7a03d8d6816) )         // BASIC lo + hi
904	1001	ROM_LOAD( "318023-02.bin", 0x108000, 0x8000, CRC(eedc120a) SHA1(f98c5a986b532c78bb68df9ec6dbcf876913b99f) )         // C64 OS ROM + Kernal
905	1002	ROM_LOAD( "390059-01.bin", 0x120000, 0x2000, CRC(6aaaafe6) SHA1(29ed066d513f2d5c09ff26d9166ba23c2afb2b3f) )         // Character
906	1003
907		ROM_REGION( 0x10000, "m8502", ROMREGION_ERASEFF )
908		ROM_REGION( 0x2000, "gfx1", ROMREGION_ERASEFF )
909		ROM_REGION( 0x100, "gfx2", ROMREGION_ERASEFF )
	1004	ROM_REGION( 0x10000, M8502_TAG, ROMREGION_ERASEFF )
910	1005	ROM_END
911	1006
912	1007
913		/* See notes at the top of the driver about PAL dumps */
	1008	//-------------------------------------------------
	1009	//  ROM( c128drde )
	1010	//-------------------------------------------------
914	1011
915	1012	ROM_START( c128drde )
916		ROM_REGION( 0x132800, "maincpu", 0 )
	1013	ROM_REGION( 0x132800, Z80A_TAG, 0 )
917	1014	ROM_LOAD( "318022-02.bin", 0x100000, 0x8000, CRC(af1ae1e8) SHA1(953dcdf5784a6b39ef84dd6fd968c7a03d8d6816) )         // BASIC lo + hi
918	1015	ROM_LOAD( "318077-01.bin", 0x108000, 0x8000, CRC(eb6e2c8f) SHA1(6b3d891fedabb5335f388a5d2a71378472ea60f4) )         // C64 OS ROM + Kernal Ger
919	1016	ROM_LOAD( "315079-01.bin", 0x120000, 0x2000, CRC(fe5a2db1) SHA1(638f8aff51c2ac4f99a55b12c4f8c985ef4bebd3) )
920	1017
921		ROM_REGION( 0x10000, "m8502", ROMREGION_ERASEFF )
922		ROM_REGION( 0x2000, "gfx1", ROMREGION_ERASEFF )
923		ROM_REGION( 0x100, "gfx2", ROMREGION_ERASEFF )
	1018	ROM_REGION( 0x10000, M8502_TAG, ROMREGION_ERASEFF )
924	1019	ROM_END
925	1020
926	1021
	1022	//-------------------------------------------------
	1023	//  ROM( c128drsw )
	1024	//-------------------------------------------------
	1025
927	1026	ROM_START( c128drsw )
928		ROM_REGION( 0x132800, "maincpu", 0 )
	1027	ROM_REGION( 0x132800, Z80A_TAG, 0 )
929	1028	ROM_LOAD( "318022-02.bin", 0x100000, 0x8000, CRC(af1ae1e8) SHA1(953dcdf5784a6b39ef84dd6fd968c7a03d8d6816) )         // BASIC lo + hi
930	1029	ROM_LOAD( "318034-01.bin", 0x108000, 0x8000, CRC(cb4e1719) SHA1(9b0a0cef56d00035c611e07170f051ee5e63aa3a) )         // C64 OS ROM + Kernal Sw/Fi
931	1030	ROM_LOAD( "325181-01.bin", 0x120000, 0x2000, CRC(7a70d9b8) SHA1(aca3f7321ee7e6152f1f0afad646ae41964de4fb) )
932	1031
933		ROM_REGION( 0x10000, "m8502", ROMREGION_ERASEFF )
934		ROM_REGION( 0x2000, "gfx1", ROMREGION_ERASEFF )
935		ROM_REGION( 0x100, "gfx2", ROMREGION_ERASEFF )
	1032	ROM_REGION( 0x10000, M8502_TAG, ROMREGION_ERASEFF )
936	1033	ROM_END
937	1034
938	1035
	1036	//-------------------------------------------------
	1037	//  ROM( c128drit )
	1038	//-------------------------------------------------
	1039
939	1040	ROM_START( c128drit )
940		ROM_REGION( 0x132800, "maincpu", 0 )
	1041	ROM_REGION( 0x132800, Z80A_TAG, 0 )
941	1042	ROM_LOAD( "318022-01.bin", 0x100000, 0x8000, CRC(e857df90) SHA1(5c2d7bbda2c3f9a926bd76ad19dc0c8c733c41cd) )         // BASIC lo + hi - based on BASIC rev.0
942	1043	ROM_LOAD( "251913-01.bin", 0x108000, 0x4000, BAD_DUMP CRC(0010ec31) SHA1(765372a0e16cbb0adf23a07b80f6b682b39fbf88) )         // C64 OS ROM
943	1044	ROM_LOAD( "editor.italian.bin", 0x10c000, 0x1000, BAD_DUMP CRC(8df58148) SHA1(39add4c0adda7a64f68a09ae8742599091228017) )
r17732	r17733
945	1046	ROM_LOAD( "kernalpart.italian.bin", 0x10e000, 0x2000, BAD_DUMP CRC(7b0d2140) SHA1(f5d604d89daedb47a1abe4b0aa41ea762829e71e) )
946	1047	ROM_LOAD( "325167-01.bin", 0x120000, 0x2000, BAD_DUMP CRC(bad36b88) SHA1(9119b27a1bf885fa4c76fff5d858c74c194dd2b8) )
947	1048
948		ROM_REGION( 0x10000, "m8502", ROMREGION_ERASEFF )
949		ROM_REGION( 0x2000, "gfx1", ROMREGION_ERASEFF )
950		ROM_REGION( 0x100, "gfx2", ROMREGION_ERASEFF )
	1049	ROM_REGION( 0x10000, M8502_TAG, ROMREGION_ERASEFF )
951	1050	ROM_END
952	1051
953	1052
	1053	//-------------------------------------------------
	1054	//  ROM( c128d81 )
	1055	//-------------------------------------------------
	1056
954	1057	ROM_START( c128d81 )
955		ROM_REGION( 0x132800, "maincpu", 0 )
	1058	ROM_REGION( 0x132800, Z80A_TAG, 0 )
956	1059	ROM_LOAD( "318018-04.bin", 0x100000, 0x4000, CRC(9f9c355b) SHA1(d53a7884404f7d18ebd60dd3080c8f8d71067441) )         // BASIC lo
957	1060	ROM_LOAD( "318019-04.bin", 0x104000, 0x4000, CRC(6e2c91a7) SHA1(c4fb4a714e48a7bf6c28659de0302183a0e0d6c0) )         // BASIC hi
958	1061	ROM_LOAD( "251913-01.bin", 0x108000, 0x4000, CRC(0010ec31) SHA1(765372a0e16cbb0adf23a07b80f6b682b39fbf88) )         // C64 OS ROM
959	1062	ROM_LOAD( "318020-05.bin", 0x10c000, 0x4000, CRC(ba456b8e) SHA1(ceb6e1a1bf7e08eb9cbc651afa29e26adccf38ab) )         // Kernal
960	1063	ROM_LOAD( "390059-01.bin", 0x120000, 0x2000, CRC(6aaaafe6) SHA1(29ed066d513f2d5c09ff26d9166ba23c2afb2b3f) )
961	1064
962		ROM_REGION( 0x10000, "m8502", ROMREGION_ERASEFF )
963		ROM_REGION( 0x2000, "gfx1", ROMREGION_ERASEFF )
964		ROM_REGION( 0x100, "gfx2", ROMREGION_ERASEFF )
	1065	ROM_REGION( 0x10000, M8502_TAG, ROMREGION_ERASEFF )
965	1066	ROM_END
966	1067
967	1068
968	1069
969		/***************************************************************************
	1070	//**************************************************************************
	1071	//  SYSTEM DRIVERS
	1072	//**************************************************************************
970	1073
971		Game driver(s)
972
973		***************************************************************************/
974
975		/*    YEAR  NAME     PARENT COMPAT MACHINE   INPUT    INIT      COMPANY                             FULLNAME            FLAGS */
976
	1074	//    YEAR  NAME    PARENT  COMPAT  MACHINE     INPUT   INIT                        COMPANY                        FULLNAME                                     FLAGS
977	1075	COMP( 1985, c128,      0,     0,   c128,     c128, c128_state,    c128,     "Commodore Business Machines", "Commodore 128 (NTSC)", 0)
978	1076	COMP( 1985, c128cr,    c128,  0,   c128,     c128, c128_state,    c128,     "Commodore Business Machines", "Commodore 128CR (NTSC, prototype?)", 0)
979	1077

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