trunk/src/mess/drivers/pc9801.c
r17680 | r17681 | |
22 | 22 | - fix CPU for some clones; |
23 | 23 | |
24 | 24 | TODO: (PC-486MU) |
| 25 | - Tries to read port C of i8255_sys (-> 0x35) at boot without setting up the control |
| 26 | port. This causes a jump to invalid program area; |
25 | 27 | - Dies on ARTIC check; |
26 | 28 | - Presumably one ROM is undumped? |
27 | 29 | |
r17680 | r17681 | |
311 | 313 | |
312 | 314 | /* PC9821 specific */ |
313 | 315 | UINT8 m_analog256,m_analog256e; |
| 316 | UINT8 m_sdip[24], m_sdip_bank; |
| 317 | |
314 | 318 | DECLARE_READ8_MEMBER(pc9801_xx_r); |
315 | 319 | DECLARE_WRITE8_MEMBER(pc9801_xx_w); |
316 | 320 | DECLARE_READ8_MEMBER(pc9801_00_r); |
r17680 | r17681 | |
374 | 378 | DECLARE_WRITE8_MEMBER(pc_dma_write_byte); |
375 | 379 | DECLARE_READ8_MEMBER(pc9801rs_access_ctrl_r); |
376 | 380 | DECLARE_WRITE8_MEMBER(pc9801rs_access_ctrl_w); |
| 381 | |
| 382 | DECLARE_READ8_MEMBER(sdip_0_r); |
| 383 | DECLARE_READ8_MEMBER(sdip_1_r); |
| 384 | DECLARE_READ8_MEMBER(sdip_2_r); |
| 385 | DECLARE_READ8_MEMBER(sdip_3_r); |
| 386 | DECLARE_READ8_MEMBER(sdip_4_r); |
| 387 | DECLARE_READ8_MEMBER(sdip_5_r); |
| 388 | DECLARE_READ8_MEMBER(sdip_6_r); |
| 389 | DECLARE_READ8_MEMBER(sdip_7_r); |
| 390 | DECLARE_READ8_MEMBER(sdip_8_r); |
| 391 | DECLARE_READ8_MEMBER(sdip_9_r); |
| 392 | DECLARE_READ8_MEMBER(sdip_a_r); |
| 393 | DECLARE_READ8_MEMBER(sdip_b_r); |
| 394 | |
| 395 | DECLARE_WRITE8_MEMBER(sdip_0_w); |
| 396 | DECLARE_WRITE8_MEMBER(sdip_1_w); |
| 397 | DECLARE_WRITE8_MEMBER(sdip_2_w); |
| 398 | DECLARE_WRITE8_MEMBER(sdip_3_w); |
| 399 | DECLARE_WRITE8_MEMBER(sdip_4_w); |
| 400 | DECLARE_WRITE8_MEMBER(sdip_5_w); |
| 401 | DECLARE_WRITE8_MEMBER(sdip_6_w); |
| 402 | DECLARE_WRITE8_MEMBER(sdip_7_w); |
| 403 | DECLARE_WRITE8_MEMBER(sdip_8_w); |
| 404 | DECLARE_WRITE8_MEMBER(sdip_9_w); |
| 405 | DECLARE_WRITE8_MEMBER(sdip_a_w); |
| 406 | DECLARE_WRITE8_MEMBER(sdip_b_w); |
| 407 | |
| 408 | private: |
| 409 | UINT8 m_sdip_read(UINT16 port, UINT8 sdip_offset); |
| 410 | void m_sdip_write(UINT16 port, UINT8 sdip_offset,UINT8 data); |
| 411 | |
377 | 412 | }; |
378 | 413 | |
379 | 414 | |
r17680 | r17681 | |
1652 | 1687 | return 0x50; // status |
1653 | 1688 | } |
1654 | 1689 | |
| 1690 | UINT8 pc9801_state::m_sdip_read(UINT16 port, UINT8 sdip_offset) |
| 1691 | { |
| 1692 | if(port == 2) |
| 1693 | return m_sdip[sdip_offset]; |
| 1694 | |
| 1695 | printf("Warning: read from unknown SDIP area %02x %04x\n",port,0x841c + port + (sdip_offset % 12)*0x100); |
| 1696 | return 0xff; |
| 1697 | } |
| 1698 | |
| 1699 | void pc9801_state::m_sdip_write(UINT16 port, UINT8 sdip_offset,UINT8 data) |
| 1700 | { |
| 1701 | if(port == 2) |
| 1702 | { |
| 1703 | m_sdip[sdip_offset] = data; |
| 1704 | return; |
| 1705 | } |
| 1706 | |
| 1707 | printf("Warning: write from unknown SDIP area %02x %04x %02x\n",port,0x841c + port + (sdip_offset % 12)*0x100,data); |
| 1708 | } |
| 1709 | |
| 1710 | READ8_MEMBER(pc9801_state::sdip_0_r) { return m_sdip_read(offset, 0+m_sdip_bank*12); } |
| 1711 | READ8_MEMBER(pc9801_state::sdip_1_r) { return m_sdip_read(offset, 1+m_sdip_bank*12); } |
| 1712 | READ8_MEMBER(pc9801_state::sdip_2_r) { return m_sdip_read(offset, 2+m_sdip_bank*12); } |
| 1713 | READ8_MEMBER(pc9801_state::sdip_3_r) { return m_sdip_read(offset, 3+m_sdip_bank*12); } |
| 1714 | READ8_MEMBER(pc9801_state::sdip_4_r) { return m_sdip_read(offset, 4+m_sdip_bank*12); } |
| 1715 | READ8_MEMBER(pc9801_state::sdip_5_r) { return m_sdip_read(offset, 5+m_sdip_bank*12); } |
| 1716 | READ8_MEMBER(pc9801_state::sdip_6_r) { return m_sdip_read(offset, 6+m_sdip_bank*12); } |
| 1717 | READ8_MEMBER(pc9801_state::sdip_7_r) { return m_sdip_read(offset, 7+m_sdip_bank*12); } |
| 1718 | READ8_MEMBER(pc9801_state::sdip_8_r) { return m_sdip_read(offset, 8+m_sdip_bank*12); } |
| 1719 | READ8_MEMBER(pc9801_state::sdip_9_r) { return m_sdip_read(offset, 9+m_sdip_bank*12); } |
| 1720 | READ8_MEMBER(pc9801_state::sdip_a_r) { return m_sdip_read(offset, 10+m_sdip_bank*12); } |
| 1721 | READ8_MEMBER(pc9801_state::sdip_b_r) { return m_sdip_read(offset, 11+m_sdip_bank*12); } |
| 1722 | |
| 1723 | WRITE8_MEMBER(pc9801_state::sdip_0_w) { m_sdip_write(offset,0+m_sdip_bank*12,data); } |
| 1724 | WRITE8_MEMBER(pc9801_state::sdip_1_w) { m_sdip_write(offset,1+m_sdip_bank*12,data); } |
| 1725 | WRITE8_MEMBER(pc9801_state::sdip_2_w) { m_sdip_write(offset,2+m_sdip_bank*12,data); } |
| 1726 | WRITE8_MEMBER(pc9801_state::sdip_3_w) { m_sdip_write(offset,3+m_sdip_bank*12,data); } |
| 1727 | WRITE8_MEMBER(pc9801_state::sdip_4_w) { m_sdip_write(offset,4+m_sdip_bank*12,data); } |
| 1728 | WRITE8_MEMBER(pc9801_state::sdip_5_w) { m_sdip_write(offset,5+m_sdip_bank*12,data); } |
| 1729 | WRITE8_MEMBER(pc9801_state::sdip_6_w) { m_sdip_write(offset,6+m_sdip_bank*12,data); } |
| 1730 | WRITE8_MEMBER(pc9801_state::sdip_7_w) { m_sdip_write(offset,7+m_sdip_bank*12,data); } |
| 1731 | WRITE8_MEMBER(pc9801_state::sdip_8_w) { m_sdip_write(offset,8+m_sdip_bank*12,data); } |
| 1732 | WRITE8_MEMBER(pc9801_state::sdip_9_w) { m_sdip_write(offset,9+m_sdip_bank*12,data); } |
| 1733 | WRITE8_MEMBER(pc9801_state::sdip_a_w) { m_sdip_write(offset,10+m_sdip_bank*12,data); } |
| 1734 | WRITE8_MEMBER(pc9801_state::sdip_b_w) |
| 1735 | { |
| 1736 | if(offset == 3) |
| 1737 | m_sdip_bank = (data & 0x40) >> 6; |
| 1738 | |
| 1739 | if(offset == 2) |
| 1740 | m_sdip_write(offset,11+m_sdip_bank*12,data); |
| 1741 | |
| 1742 | if((offset & 2) == 0) |
| 1743 | printf("SDIP area B write %02x %02x\n",offset,data); |
| 1744 | } |
| 1745 | |
1655 | 1746 | static ADDRESS_MAP_START( pc9821_map, AS_PROGRAM, 32, pc9801_state ) |
1656 | 1747 | AM_RANGE(0x00000000, 0xffffffff) AM_READWRITE8(pc9801rs_memory_r,pc9801rs_memory_w,0xffffffff) |
1657 | 1748 | ADDRESS_MAP_END |
r17680 | r17681 | |
1700 | 1791 | // AM_RANGE(0x0cfc, 0x0cff) PCI bus |
1701 | 1792 | // AM_RANGE(0x3fd8, 0x3fdf) <undefined> / pit mirror ports |
1702 | 1793 | // AM_RANGE(0x7fd8, 0x7fdf) <undefined> / mouse ppi8255 ports |
| 1794 | AM_RANGE(0x841c, 0x841f) AM_READWRITE8(sdip_0_r,sdip_0_w,0xffffffff) |
| 1795 | AM_RANGE(0x851c, 0x851f) AM_READWRITE8(sdip_1_r,sdip_1_w,0xffffffff) |
| 1796 | AM_RANGE(0x861c, 0x861f) AM_READWRITE8(sdip_2_r,sdip_2_w,0xffffffff) |
| 1797 | AM_RANGE(0x871c, 0x871f) AM_READWRITE8(sdip_3_r,sdip_3_w,0xffffffff) |
| 1798 | AM_RANGE(0x881c, 0x881f) AM_READWRITE8(sdip_4_r,sdip_4_w,0xffffffff) |
| 1799 | AM_RANGE(0x891c, 0x891f) AM_READWRITE8(sdip_5_r,sdip_5_w,0xffffffff) |
| 1800 | AM_RANGE(0x8a1c, 0x8a1f) AM_READWRITE8(sdip_6_r,sdip_6_w,0xffffffff) |
| 1801 | AM_RANGE(0x8b1c, 0x8b1f) AM_READWRITE8(sdip_7_r,sdip_7_w,0xffffffff) |
| 1802 | AM_RANGE(0x8c1c, 0x8c1f) AM_READWRITE8(sdip_8_r,sdip_8_w,0xffffffff) |
| 1803 | AM_RANGE(0x8d1c, 0x8d1f) AM_READWRITE8(sdip_9_r,sdip_9_w,0xffffffff) |
| 1804 | AM_RANGE(0x8e1c, 0x8e1f) AM_READWRITE8(sdip_a_r,sdip_a_w,0xffffffff) |
| 1805 | AM_RANGE(0x8f1c, 0x8f1f) AM_READWRITE8(sdip_b_r,sdip_b_w,0xffffffff) |
1703 | 1806 | // AM_RANGE(0xa460, 0xa46f) cs4231 PCM extended port / <undefined> |
1704 | 1807 | // AM_RANGE(0xbfdb, 0xbfdb) mouse timing port |
1705 | 1808 | // AM_RANGE(0xc0d0, 0xc0d3) MIDI port, option 0 / <undefined> |
r17680 | r17681 | |
2485 | 2588 | state->m_ram_size = machine.device<ram_device>(RAM_TAG)->size() - 0xa0000; |
2486 | 2589 | } |
2487 | 2590 | |
| 2591 | static MACHINE_START(pc9821) |
| 2592 | { |
| 2593 | pc9801_state *state = machine.driver_data<pc9801_state>(); |
| 2594 | |
| 2595 | MACHINE_START_CALL(pc9801); |
| 2596 | state_save_register_global_pointer(machine, state->m_sdip, 24); |
| 2597 | } |
| 2598 | |
2488 | 2599 | static INTERRUPT_GEN(pc9801_vrtc_irq) |
2489 | 2600 | { |
2490 | 2601 | pc9801_state *state = device->machine().driver_data<pc9801_state>(); |
r17680 | r17681 | |
2642 | 2753 | MCFG_CPU_IO_MAP(pc9821_io) |
2643 | 2754 | MCFG_CPU_VBLANK_INT("screen",pc9801_vrtc_irq) |
2644 | 2755 | |
2645 | | MCFG_MACHINE_START(pc9801) |
| 2756 | MCFG_MACHINE_START(pc9821) |
2646 | 2757 | MCFG_MACHINE_RESET(pc9801rs) |
2647 | 2758 | |
2648 | 2759 | MCFG_PIT8253_ADD( "pit8253", pc9801rs_pit8253_config ) |