trunk/src/mess/drivers/pc9801.c
| r17679 | r17680 | |
|---|
| 8 | 8 | - floppy interface doesn't seem to work at all with either floppy inserted or not, missing DMA irq? |
| 9 | 9 | - proper 8251 uart hook-up on keyboard |
| 10 | 10 | - boot is too slow right now, might be due of the floppy / HDD devices |
| 11 | - investigate on POR bit |
| 11 | 12 | |
| 12 | | TODO (PC-9801UX): |
| 13 | | - POR mechanism makes this to die very soon (hack is unsuited for what this needs); |
| 14 | | |
| 15 | 13 | TODO (PC-9801RS): |
| 16 | 14 | - floppy disk hook-up; |
| 17 | | - POR mechanism isn't fully understood; |
| 18 | 15 | - extra features; |
| 19 | 16 | - clean-up duplicating code; |
| 20 | 17 | |
| r17679 | r17680 | |
|---|
| 302 | 299 | |
| 303 | 300 | /* PC9801RS specific */ |
| 304 | 301 | UINT8 m_gate_a20; //A20 line |
| 305 | | UINT8 m_por; //Power-On Reset |
| 302 | UINT8 m_access_ctrl; |
| 306 | 303 | UINT8 m_rom_bank; |
| 307 | 304 | UINT8 m_fdc_ctrl; |
| 308 | 305 | UINT32 m_ram_size; |
| r17679 | r17680 | |
|---|
| 375 | 372 | DECLARE_READ8_MEMBER(ide_status_r); |
| 376 | 373 | DECLARE_READ8_MEMBER(pc_dma_read_byte); |
| 377 | 374 | DECLARE_WRITE8_MEMBER(pc_dma_write_byte); |
| 375 | DECLARE_READ8_MEMBER(pc9801rs_access_ctrl_r); |
| 376 | DECLARE_WRITE8_MEMBER(pc9801rs_access_ctrl_w); |
| 378 | 377 | }; |
| 379 | 378 | |
| 380 | 379 | |
| r17679 | r17680 | |
|---|
| 1285 | 1284 | |
| 1286 | 1285 | WRITE8_MEMBER(pc9801_state::pc9801rs_f0_w) |
| 1287 | 1286 | { |
| 1288 | | |
| 1289 | 1287 | if(offset == 0x00) |
| 1290 | 1288 | { |
| 1291 | | m_por = 0x00; |
| 1289 | UINT8 por; |
| 1290 | /* reset POR bit, TODO: is there any other way? */ |
| 1291 | por = machine().device<i8255_device>("ppi8255_sys")->read(space, 2) & ~0x20; |
| 1292 | machine().device<i8255_device>("ppi8255_sys")->write(space, 2,por); |
| 1292 | 1293 | cputag_set_input_line(machine(), "maincpu", INPUT_LINE_RESET, PULSE_LINE); |
| 1293 | 1294 | } |
| 1294 | 1295 | |
| r17679 | r17680 | |
|---|
| 1306 | 1307 | |
| 1307 | 1308 | READ8_MEMBER(pc9801_state::pc9801rs_30_r) |
| 1308 | 1309 | { |
| 1309 | | |
| 1310 | | if(offset == 5) |
| 1311 | | return (pc9801_30_r(space,offset) & ~0xa0) | m_por; //ppi bug? |
| 1312 | | |
| 1313 | 1310 | return pc9801_30_r(space,offset); |
| 1314 | 1311 | } |
| 1315 | 1312 | |
| r17679 | r17680 | |
|---|
| 1490 | 1487 | pc9801_a0_w(space,offset,data); |
| 1491 | 1488 | } |
| 1492 | 1489 | |
| 1490 | READ8_MEMBER( pc9801_state::pc9801rs_access_ctrl_r ) |
| 1491 | { |
| 1492 | if(offset == 1) |
| 1493 | return m_access_ctrl; |
| 1494 | |
| 1495 | return 0xff; |
| 1496 | } |
| 1497 | |
| 1498 | WRITE8_MEMBER( pc9801_state::pc9801rs_access_ctrl_w ) |
| 1499 | { |
| 1500 | if(offset == 1) |
| 1501 | m_access_ctrl = data; |
| 1502 | } |
| 1503 | |
| 1493 | 1504 | static ADDRESS_MAP_START( pc9801rs_map, AS_PROGRAM, 32, pc9801_state ) |
| 1494 | 1505 | AM_RANGE(0x00000000, 0xffffffff) AM_READWRITE8(pc9801rs_memory_r,pc9801rs_memory_w,0xffffffff) |
| 1495 | 1506 | ADDRESS_MAP_END |
| r17679 | r17680 | |
|---|
| 1508 | 1519 | AM_RANGE(0x00bc, 0x00bf) AM_READWRITE8(pc9810rs_fdc_ctrl_r,pc9810rs_fdc_ctrl_w,0xffffffff) |
| 1509 | 1520 | AM_RANGE(0x00c8, 0x00cf) AM_READWRITE8(pc9801rs_2dd_r, pc9801rs_2dd_w, 0xffffffff) |
| 1510 | 1521 | AM_RANGE(0x00f0, 0x00ff) AM_READWRITE8(pc9801rs_f0_r, pc9801rs_f0_w, 0xffffffff) |
| 1522 | AM_RANGE(0x0438, 0x043b) AM_READWRITE8(pc9801rs_access_ctrl_r,pc9801rs_access_ctrl_w,0xffffffff) |
| 1511 | 1523 | AM_RANGE(0x043c, 0x043f) AM_WRITE8(pc9801rs_bank_w, 0xffffffff) //ROM/RAM bank |
| 1512 | 1524 | |
| 1513 | 1525 | ADDRESS_MAP_END |
| r17679 | r17680 | |
|---|
| 1567 | 1579 | AM_RANGE(0x00bc, 0x00bf) AM_READWRITE8(pc9810rs_fdc_ctrl_r,pc9810rs_fdc_ctrl_w,0xffff) |
| 1568 | 1580 | AM_RANGE(0x00c8, 0x00cf) AM_READWRITE8(pc9801rs_2dd_r, pc9801rs_2dd_w, 0xffff) |
| 1569 | 1581 | AM_RANGE(0x00f0, 0x00ff) AM_READWRITE8(pc9801rs_f0_r, pc9801rs_f0_w, 0xffff) |
| 1582 | AM_RANGE(0x0438, 0x043b) AM_READWRITE8(pc9801rs_access_ctrl_r,pc9801rs_access_ctrl_w,0xffff) |
| 1570 | 1583 | AM_RANGE(0x043c, 0x043f) AM_WRITE8(pc9801rs_bank_w, 0xffff) //ROM/RAM bank |
| 1571 | 1584 | |
| 1572 | 1585 | ADDRESS_MAP_END |
| r17679 | r17680 | |
|---|
| 1667 | 1680 | // AM_RANGE(0x018c, 0x018f) YM2203 OPN extended ports / <undefined> |
| 1668 | 1681 | // AM_RANGE(0x0430, 0x0430) IDE bank register |
| 1669 | 1682 | // AM_RANGE(0x0432, 0x0432) IDE bank register (mirror) |
| 1670 | | // AM_RANGE(0x0439, 0x0439) ROM/RAM bank (NEC) |
| 1683 | |
| 1671 | 1684 | // AM_RANGE(0x043d, 0x043d) ROM/RAM bank (NEC) |
| 1672 | 1685 | AM_RANGE(0x043c, 0x043f) AM_WRITE8(pc9801rs_bank_w, 0xffffffff) //ROM/RAM bank (EPSON) |
| 1673 | 1686 | // AM_RANGE(0x04a0, 0x04af) EGC |
| r17679 | r17680 | |
|---|
| 2465 | 2478 | MACHINE_RESET_CALL(pc9801); |
| 2466 | 2479 | |
| 2467 | 2480 | state->m_gate_a20 = 0; |
| 2468 | | state->m_por = 0xa0; |
| 2469 | 2481 | state->m_rom_bank = 0; |
| 2470 | 2482 | state->m_fdc_ctrl = 3; |
| 2483 | state->m_access_ctrl = 0; |
| 2471 | 2484 | |
| 2472 | 2485 | state->m_ram_size = machine.device<ram_device>(RAM_TAG)->size() - 0xa0000; |
| 2473 | 2486 | } |