trunk/src/emu/cpu/m6502/m4510.c
| r17630 | r17631 | |
| 148 | 148 | direct_read_data *direct; |
| 149 | 149 | int icount; |
| 150 | 150 | |
| 151 | | read8_space_func rdmem_id; /* readmem callback for indexed instructions */ |
| 152 | | write8_space_func wrmem_id; /* writemem callback for indexed instructions */ |
| 151 | devcb_resolved_read8 rdmem_id; /* readmem callback for indexed instructions */ |
| 152 | devcb_resolved_write8 wrmem_id; /* writemem callback for indexed instructions */ |
| 153 | 153 | |
| 154 | 154 | UINT8 ddr; |
| 155 | 155 | UINT8 port; |
| r17630 | r17631 | |
| 184 | 184 | #define M4510 |
| 185 | 185 | #include "t65ce02.c" |
| 186 | 186 | |
| 187 | | static UINT8 default_rdmem_id(address_space *space, offs_t address) |
| 188 | | { |
| 189 | | m4510_Regs *cpustate = get_safe_token(&space->device()); |
| 190 | | return space->read_byte(M4510_MEM(address)); |
| 191 | | } |
| 192 | | static void default_wrmem_id(address_space *space, offs_t address, UINT8 data) |
| 193 | | { |
| 194 | | m4510_Regs *cpustate = get_safe_token(&space->device()); |
| 195 | | space->write_byte(M4510_MEM(address), data); |
| 196 | | } |
| 197 | | |
| 198 | 187 | static CPU_INIT( m4510 ) |
| 199 | 188 | { |
| 200 | 189 | m4510_Regs *cpustate = get_safe_token(device); |
| 201 | 190 | const m6502_interface *intf = (const m6502_interface *)device->static_config(); |
| 202 | 191 | |
| 203 | 192 | cpustate->interrupt_inhibit = 0; |
| 204 | | cpustate->rdmem_id = default_rdmem_id; |
| 205 | | cpustate->wrmem_id = default_wrmem_id; |
| 206 | 193 | cpustate->irq_callback = irqcallback; |
| 207 | 194 | cpustate->device = device; |
| 208 | 195 | cpustate->space = device->space(AS_PROGRAM); |
| r17630 | r17631 | |
| 210 | 197 | |
| 211 | 198 | if ( intf ) |
| 212 | 199 | { |
| 213 | | if ( intf->read_indexed_func ) |
| 214 | | cpustate->rdmem_id = intf->read_indexed_func; |
| 215 | | |
| 216 | | if ( intf->write_indexed_func ) |
| 217 | | cpustate->wrmem_id = intf->write_indexed_func; |
| 218 | | |
| 200 | cpustate->rdmem_id.resolve(intf->read_indexed_func, *device); |
| 201 | cpustate->wrmem_id.resolve(intf->write_indexed_func, *device); |
| 219 | 202 | cpustate->in_port_func.resolve(intf->in_port_func, *device); |
| 220 | 203 | cpustate->out_port_func.resolve(intf->out_port_func, *device); |
| 221 | 204 | } |
| r17630 | r17631 | |
| 223 | 206 | { |
| 224 | 207 | devcb_read8 nullrcb = DEVCB_NULL; |
| 225 | 208 | devcb_write8 nullwcb = DEVCB_NULL; |
| 209 | |
| 210 | cpustate->rdmem_id.resolve(nullrcb, *device); |
| 211 | cpustate->wrmem_id.resolve(nullwcb, *device); |
| 226 | 212 | cpustate->in_port_func.resolve(nullrcb, *device); |
| 227 | 213 | cpustate->out_port_func.resolve(nullwcb, *device); |
| 228 | 214 | } |
trunk/src/emu/cpu/m6502/m6502.c
| r17630 | r17631 | |
| 76 | 76 | int int_occured; |
| 77 | 77 | int icount; |
| 78 | 78 | |
| 79 | | read8_space_func rdmem_id; /* readmem callback for indexed instructions */ |
| 80 | | write8_space_func wrmem_id; /* writemem callback for indexed instructions */ |
| 79 | devcb_resolved_read8 rdmem_id; /* readmem callback for indexed instructions */ |
| 80 | devcb_resolved_write8 wrmem_id; /* writemem callback for indexed instructions */ |
| 81 | 81 | |
| 82 | 82 | UINT8 ddr; |
| 83 | 83 | UINT8 port; |
| r17630 | r17631 | |
| 105 | 105 | return (m6502_Regs *)downcast<legacy_cpu_device *>(device)->token(); |
| 106 | 106 | } |
| 107 | 107 | |
| 108 | | static UINT8 default_rdmem_id(address_space *space, offs_t offset) { return space->read_byte(offset); } |
| 109 | | static void default_wdmem_id(address_space *space, offs_t offset, UINT8 data) { space->write_byte(offset, data); } |
| 110 | | |
| 111 | 108 | /*************************************************************** |
| 112 | 109 | * include the opcode macros, functions and tables |
| 113 | 110 | ***************************************************************/ |
| r17630 | r17631 | |
| 144 | 141 | cpustate->direct = &cpustate->space->direct(); |
| 145 | 142 | cpustate->subtype = subtype; |
| 146 | 143 | cpustate->insn = insn; |
| 147 | | cpustate->rdmem_id = default_rdmem_id; |
| 148 | | cpustate->wrmem_id = default_wdmem_id; |
| 149 | 144 | |
| 150 | 145 | if ( intf ) |
| 151 | 146 | { |
| 152 | | if ( intf->read_indexed_func ) |
| 153 | | cpustate->rdmem_id = intf->read_indexed_func; |
| 154 | | |
| 155 | | if ( intf->write_indexed_func ) |
| 156 | | cpustate->wrmem_id = intf->write_indexed_func; |
| 157 | | |
| 147 | cpustate->rdmem_id.resolve(intf->read_indexed_func, *device); |
| 148 | cpustate->wrmem_id.resolve(intf->write_indexed_func, *device); |
| 158 | 149 | cpustate->in_port_func.resolve(intf->in_port_func, *device); |
| 159 | 150 | cpustate->out_port_func.resolve(intf->out_port_func, *device); |
| 151 | |
| 160 | 152 | cpustate->pullup = intf->external_port_pullup; |
| 161 | 153 | cpustate->pulldown = intf->external_port_pulldown; |
| 162 | 154 | } |
| 163 | 155 | else |
| 164 | 156 | { |
| 165 | | devcb_write8 nullcb = DEVCB_NULL; |
| 166 | | cpustate->out_port_func.resolve(nullcb, *device); |
| 157 | devcb_read8 nullrcb = DEVCB_NULL; |
| 158 | devcb_write8 nullwcb = DEVCB_NULL; |
| 159 | |
| 160 | cpustate->rdmem_id.resolve(nullrcb, *device); |
| 161 | cpustate->wrmem_id.resolve(nullwcb, *device); |
| 162 | cpustate->in_port_func.resolve(nullrcb, *device); |
| 163 | cpustate->out_port_func.resolve(nullwcb, *device); |
| 164 | |
| 167 | 165 | cpustate->pullup = 0; |
| 168 | 166 | cpustate->pulldown = 0; |
| 169 | 167 | } |
| r17630 | r17631 | |
| 393 | 391 | UINT8 output = cpustate->port & cpustate->ddr; |
| 394 | 392 | UINT8 pulldown = ~(cpustate->pulldown & ~cpustate->ddr); |
| 395 | 393 | |
| 396 | | result = (input | mask | output) & pulldown; |
| 394 | result = (input | mask | output) & (input | pulldown); |
| 397 | 395 | } |
| 398 | 396 | break; |
| 399 | 397 | } |
trunk/src/emu/cpu/m6502/m6509.c
| r17630 | r17631 | |
| 84 | 84 | |
| 85 | 85 | int icount; |
| 86 | 86 | |
| 87 | | read8_space_func rdmem_id; /* readmem callback for indexed instructions */ |
| 88 | | write8_space_func wrmem_id; /* writemem callback for indexed instructions */ |
| 87 | devcb_resolved_read8 rdmem_id; /* readmem callback for indexed instructions */ |
| 88 | devcb_resolved_write8 wrmem_id; /* writemem callback for indexed instructions */ |
| 89 | 89 | }; |
| 90 | 90 | |
| 91 | 91 | INLINE m6509_Regs *get_safe_token(device_t *device) |
| r17630 | r17631 | |
| 135 | 135 | AM_RANGE(0x00001, 0x00001) AM_MIRROR(0xF0000) AM_READWRITE_LEGACY(m6509_read_00001, m6509_write_00001) |
| 136 | 136 | ADDRESS_MAP_END |
| 137 | 137 | |
| 138 | | static UINT8 default_rdmem_id(address_space *space, offs_t address) { return space->read_byte(address); } |
| 139 | | static void default_wdmem_id(address_space *space, offs_t address, UINT8 data) { space->write_byte(address, data); } |
| 140 | | |
| 141 | 138 | static CPU_INIT( m6509 ) |
| 142 | 139 | { |
| 143 | 140 | m6509_Regs *cpustate = get_safe_token(device); |
| 144 | 141 | const m6502_interface *intf = (const m6502_interface *)device->static_config(); |
| 145 | 142 | |
| 146 | | cpustate->rdmem_id = default_rdmem_id; |
| 147 | | cpustate->wrmem_id = default_wdmem_id; |
| 148 | 143 | cpustate->irq_callback = irqcallback; |
| 149 | 144 | cpustate->device = device; |
| 150 | 145 | cpustate->space = device->space(AS_PROGRAM); |
| r17630 | r17631 | |
| 152 | 147 | |
| 153 | 148 | if ( intf ) |
| 154 | 149 | { |
| 155 | | if ( intf->read_indexed_func ) |
| 156 | | cpustate->rdmem_id = intf->read_indexed_func; |
| 150 | cpustate->rdmem_id.resolve(intf->read_indexed_func, *device); |
| 151 | cpustate->wrmem_id.resolve(intf->write_indexed_func, *device); |
| 152 | } |
| 153 | else |
| 154 | { |
| 155 | devcb_read8 nullrcb = DEVCB_NULL; |
| 156 | devcb_write8 nullwcb = DEVCB_NULL; |
| 157 | 157 | |
| 158 | | if ( intf->write_indexed_func ) |
| 159 | | cpustate->wrmem_id = intf->write_indexed_func; |
| 158 | cpustate->rdmem_id.resolve(nullrcb, *device); |
| 159 | cpustate->wrmem_id.resolve(nullwcb, *device); |
| 160 | 160 | } |
| 161 | 161 | } |
| 162 | 162 | |
trunk/src/emu/cpu/m6502/m65ce02.c
| r17630 | r17631 | |
| 78 | 78 | legacy_cpu_device *device; |
| 79 | 79 | address_space *space; |
| 80 | 80 | direct_read_data *direct; |
| 81 | | read8_space_func rdmem_id; /* readmem callback for indexed instructions */ |
| 82 | | write8_space_func wrmem_id; /* writemem callback for indexed instructions */ |
| 81 | devcb_resolved_read8 rdmem_id; /* readmem callback for indexed instructions */ |
| 82 | devcb_resolved_write8 wrmem_id; /* writemem callback for indexed instructions */ |
| 83 | 83 | }; |
| 84 | 84 | |
| 85 | 85 | INLINE m65ce02_Regs *get_safe_token(device_t *device) |
| r17630 | r17631 | |
| 95 | 95 | |
| 96 | 96 | #include "t65ce02.c" |
| 97 | 97 | |
| 98 | | static UINT8 default_rdmem_id(address_space *space, offs_t address) { return space->read_byte(address); } |
| 99 | | static void default_wdmem_id(address_space *space, offs_t address, UINT8 data) { space->write_byte(address, data); } |
| 100 | | |
| 101 | 98 | static CPU_INIT( m65ce02 ) |
| 102 | 99 | { |
| 103 | 100 | m65ce02_Regs *cpustate = get_safe_token(device); |
| 104 | 101 | const m6502_interface *intf = (const m6502_interface *)device->static_config(); |
| 105 | 102 | |
| 106 | | cpustate->rdmem_id = default_rdmem_id; |
| 107 | | cpustate->wrmem_id = default_wdmem_id; |
| 108 | 103 | cpustate->irq_callback = irqcallback; |
| 109 | 104 | cpustate->device = device; |
| 110 | 105 | cpustate->space = device->space(AS_PROGRAM); |
| r17630 | r17631 | |
| 112 | 107 | |
| 113 | 108 | if ( intf ) |
| 114 | 109 | { |
| 115 | | if ( intf->read_indexed_func ) |
| 116 | | cpustate->rdmem_id = intf->read_indexed_func; |
| 110 | cpustate->rdmem_id.resolve(intf->read_indexed_func, *device); |
| 111 | cpustate->wrmem_id.resolve(intf->write_indexed_func, *device); |
| 112 | } |
| 113 | else |
| 114 | { |
| 115 | devcb_read8 nullrcb = DEVCB_NULL; |
| 116 | devcb_write8 nullwcb = DEVCB_NULL; |
| 117 | 117 | |
| 118 | | if ( intf->write_indexed_func ) |
| 119 | | cpustate->wrmem_id = intf->write_indexed_func; |
| 118 | cpustate->rdmem_id.resolve(nullrcb, *device); |
| 119 | cpustate->wrmem_id.resolve(nullwcb, *device); |
| 120 | 120 | } |
| 121 | 121 | } |
| 122 | 122 | |
trunk/src/mess/machine/c1551.c
| r17630 | r17631 | |
| 70 | 70 | |
| 71 | 71 | |
| 72 | 72 | //------------------------------------------------- |
| 73 | | // m6502_interface m6510t_intf |
| 73 | // M6510_INTERFACE( cpu_intf ) |
| 74 | 74 | //------------------------------------------------- |
| 75 | 75 | |
| 76 | 76 | READ8_MEMBER( c1551_device::port_r ) |
| r17630 | r17631 | |
| 131 | 131 | m_ga->ds_w((data >> 5) & 0x03); |
| 132 | 132 | } |
| 133 | 133 | |
| 134 | | static const m6502_interface m6510t_intf = |
| 134 | static M6510_INTERFACE( cpu_intf ) |
| 135 | 135 | { |
| 136 | | NULL, // read_indexed_func |
| 137 | | NULL, // write_indexed_func |
| 136 | DEVCB_NULL, // read_indexed_func |
| 137 | DEVCB_NULL, // write_indexed_func |
| 138 | 138 | DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, c1551_device, port_r), |
| 139 | | DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, c1551_device, port_w) |
| 139 | DEVCB_DEVICE_MEMBER(DEVICE_SELF_OWNER, c1551_device, port_w), |
| 140 | 0x00, |
| 141 | 0x00 |
| 140 | 142 | }; |
| 141 | 143 | |
| 142 | 144 | |
| r17630 | r17631 | |
| 406 | 408 | static MACHINE_CONFIG_FRAGMENT( c1551 ) |
| 407 | 409 | MCFG_CPU_ADD(M6510T_TAG, M6510T, XTAL_16MHz/8) |
| 408 | 410 | MCFG_CPU_PROGRAM_MAP(c1551_mem) |
| 409 | | MCFG_CPU_CONFIG(m6510t_intf) |
| 411 | MCFG_CPU_CONFIG(cpu_intf) |
| 410 | 412 | MCFG_QUANTUM_PERFECT_CPU(M6510T_TAG) |
| 411 | 413 | |
| 412 | 414 | MCFG_PLS100_ADD(PLA_TAG) |
trunk/src/mess/includes/vic10.h
| r17630 | r17631 | |
| 8 | 8 | #include "includes/cbm.h" |
| 9 | 9 | #include "machine/6526cia.h" |
| 10 | 10 | #include "machine/cbmipt.h" |
| 11 | #include "machine/petcass.h" |
| 11 | 12 | #include "machine/ram.h" |
| 12 | 13 | #include "sound/dac.h" |
| 13 | 14 | #include "sound/sid6581.h" |
| r17630 | r17631 | |
| 31 | 32 | m_cia(*this, MOS6526_TAG), |
| 32 | 33 | m_exp(*this, VIC10_EXPANSION_SLOT_TAG), |
| 33 | 34 | m_ram(*this, RAM_TAG), |
| 34 | | m_cassette(*this, CASSETTE_TAG), |
| 35 | | m_cassette_timer(*this, TIMER_C1531_TAG), |
| 35 | m_cassette(*this, PET_DATASSETTE_PORT_TAG), |
| 36 | 36 | m_cia_irq(CLEAR_LINE), |
| 37 | 37 | m_vic_irq(CLEAR_LINE), |
| 38 | 38 | m_exp_irq(CLEAR_LINE) |
| r17630 | r17631 | |
| 44 | 44 | required_device<mos6526_device> m_cia; |
| 45 | 45 | required_device<vic10_expansion_slot_device> m_exp; |
| 46 | 46 | required_device<ram_device> m_ram; |
| 47 | | optional_device<cassette_image_device> m_cassette; |
| 48 | | optional_device<timer_device> m_cassette_timer; |
| 47 | optional_device<pet_datassette_port_device> m_cassette; |
| 49 | 48 | |
| 50 | 49 | virtual void machine_start(); |
| 51 | 50 | virtual void machine_reset(); |
trunk/src/mess/drivers/apple3.c
| r17630 | r17631 | |
| 36 | 36 | * different memory locations */ |
| 37 | 37 | static const m6502_interface apple3_m6502_interface = |
| 38 | 38 | { |
| 39 | | NULL, /* read_indexed_func */ |
| 40 | | NULL, /* write_indexed_func */ |
| 41 | | DEVCB_DRIVER_MEMBER(apple3_state, apple3_indexed_read), /* port_read_func */ |
| 42 | | DEVCB_DRIVER_MEMBER(apple3_state, apple3_indexed_write) /* port_write_func */ |
| 39 | DEVCB_DRIVER_MEMBER(apple3_state, apple3_indexed_read), /* read_indexed_func */ |
| 40 | DEVCB_DRIVER_MEMBER(apple3_state, apple3_indexed_write), /* write_indexed_func */ |
| 41 | DEVCB_NULL, /* port_read_func */ |
| 42 | DEVCB_NULL, /* port_write_func */ |
| 43 | 0x00, |
| 44 | 0x00 |
| 43 | 45 | }; |
| 44 | 46 | |
| 45 | 47 | static const floppy_interface apple3_floppy_interface = |
trunk/src/mess/drivers/plus4.c
| r17630 | r17631 | |
| 438 | 438 | //************************************************************************** |
| 439 | 439 | |
| 440 | 440 | //------------------------------------------------- |
| 441 | | // m6502_interface cpu_intf |
| 441 | // M6510_INTERFACE( cpu_intf ) |
| 442 | 442 | //------------------------------------------------- |
| 443 | 443 | |
| 444 | 444 | READ8_MEMBER( plus4_state::cpu_r ) |
| r17630 | r17631 | |
| 489 | 489 | |
| 490 | 490 | */ |
| 491 | 491 | |
| 492 | | UINT8 data = 0x2f; |
| 492 | UINT8 data = 0; |
| 493 | 493 | |
| 494 | 494 | // cassette read |
| 495 | 495 | data |= m_cassette->read() << 4; |
| r17630 | r17631 | |
| 538 | 538 | m_cassette->write(!BIT(data, 1)); |
| 539 | 539 | } |
| 540 | 540 | |
| 541 | | static const m6502_interface cpu_intf = |
| 541 | static M6510_INTERFACE( cpu_intf ) |
| 542 | 542 | { |
| 543 | | NULL, |
| 544 | | NULL, |
| 543 | DEVCB_NULL, |
| 544 | DEVCB_NULL, |
| 545 | 545 | DEVCB_DRIVER_MEMBER(plus4_state, cpu_r), |
| 546 | | DEVCB_DRIVER_MEMBER(plus4_state, cpu_w) |
| 546 | DEVCB_DRIVER_MEMBER(plus4_state, cpu_w), |
| 547 | 0x00, |
| 548 | 0xc0 |
| 547 | 549 | }; |
| 548 | 550 | |
| 549 | | static const m6502_interface c16_cpu_intf = |
| 551 | static M6510_INTERFACE( c16_cpu_intf ) |
| 550 | 552 | { |
| 551 | | NULL, |
| 552 | | NULL, |
| 553 | DEVCB_NULL, |
| 554 | DEVCB_NULL, |
| 553 | 555 | DEVCB_DRIVER_MEMBER(plus4_state, c16_cpu_r), |
| 554 | | DEVCB_DRIVER_MEMBER(plus4_state, cpu_w) |
| 556 | DEVCB_DRIVER_MEMBER(plus4_state, cpu_w), |
| 557 | 0x00, |
| 558 | 0xc0 |
| 555 | 559 | }; |
| 556 | 560 | |
| 557 | 561 | //------------------------------------------------- |
trunk/src/mess/drivers/c128.c
| r17630 | r17631 | |
| 663 | 663 | }; |
| 664 | 664 | |
| 665 | 665 | |
| 666 | | static const m6502_interface c128_m8502_interface = |
| 666 | static M6510_INTERFACE( c128_m8502_interface ) |
| 667 | 667 | { |
| 668 | | NULL, /* read_indexed_func */ |
| 669 | | NULL, /* write_indexed_func */ |
| 668 | DEVCB_NULL, /* read_indexed_func */ |
| 669 | DEVCB_NULL, /* write_indexed_func */ |
| 670 | 670 | DEVCB_HANDLER(c128_m6510_port_read), /* port_read_func */ |
| 671 | | DEVCB_HANDLER(c128_m6510_port_write) /* port_write_func */ |
| 671 | DEVCB_HANDLER(c128_m6510_port_write), /* port_write_func */ |
| 672 | 0x00, |
| 673 | 0x00 |
| 672 | 674 | }; |
| 673 | 675 | |
| 674 | 676 | static CBM_IEC_INTERFACE( cbm_iec_intf ) |
trunk/src/mess/drivers/c64.c
| r17630 | r17631 | |
| 651 | 651 | |
| 652 | 652 | |
| 653 | 653 | //------------------------------------------------- |
| 654 | | // m6502_interface cpu_intf |
| 654 | // M6510_INTERFACE( cpu_intf ) |
| 655 | 655 | //------------------------------------------------- |
| 656 | 656 | |
| 657 | 657 | READ8_MEMBER( c64_state::cpu_r ) |
| r17630 | r17631 | |
| 705 | 705 | |
| 706 | 706 | static M6510_INTERFACE( cpu_intf ) |
| 707 | 707 | { |
| 708 | | NULL, |
| 709 | | NULL, |
| 708 | DEVCB_NULL, |
| 709 | DEVCB_NULL, |
| 710 | 710 | DEVCB_DRIVER_MEMBER(c64_state, cpu_r), |
| 711 | 711 | DEVCB_DRIVER_MEMBER(c64_state, cpu_w), |
| 712 | 712 | 0x17, |
| r17630 | r17631 | |
| 715 | 715 | |
| 716 | 716 | |
| 717 | 717 | //------------------------------------------------- |
| 718 | | // m6502_interface sx64_cpu_intf |
| 718 | // M6510_INTERFACE( sx64_cpu_intf ) |
| 719 | 719 | //------------------------------------------------- |
| 720 | 720 | |
| 721 | 721 | READ8_MEMBER( sx64_state::cpu_r ) |
| r17630 | r17631 | |
| 759 | 759 | |
| 760 | 760 | static M6510_INTERFACE( sx64_cpu_intf ) |
| 761 | 761 | { |
| 762 | | NULL, |
| 763 | | NULL, |
| 762 | DEVCB_NULL, |
| 763 | DEVCB_NULL, |
| 764 | 764 | DEVCB_DRIVER_MEMBER(sx64_state, cpu_r), |
| 765 | 765 | DEVCB_DRIVER_MEMBER(sx64_state, cpu_w), |
| 766 | 766 | 0x07, |
| r17630 | r17631 | |
| 769 | 769 | |
| 770 | 770 | |
| 771 | 771 | //------------------------------------------------- |
| 772 | | // m6502_interface c64gs_cpu_intf |
| 772 | // M6510_INTERFACE( c64gs_cpu_intf ) |
| 773 | 773 | //------------------------------------------------- |
| 774 | 774 | |
| 775 | 775 | READ8_MEMBER( c64gs_state::cpu_r ) |
| r17630 | r17631 | |
| 811 | 811 | m_charen = BIT(data, 2); |
| 812 | 812 | } |
| 813 | 813 | |
| 814 | | static const m6502_interface c64gs_cpu_intf = |
| 814 | static M6510_INTERFACE( c64gs_cpu_intf ) |
| 815 | 815 | { |
| 816 | | NULL, |
| 817 | | NULL, |
| 816 | DEVCB_NULL, |
| 817 | DEVCB_NULL, |
| 818 | 818 | DEVCB_DRIVER_MEMBER(c64gs_state, cpu_r), |
| 819 | 819 | DEVCB_DRIVER_MEMBER(c64gs_state, cpu_w), |
| 820 | 820 | 0x07, |
trunk/src/mess/drivers/vic10.c
| r17630 | r17631 | |
| 471 | 471 | |
| 472 | 472 | |
| 473 | 473 | //------------------------------------------------- |
| 474 | | // m6502_interface cpu_intf |
| 474 | // M6510_INTERFACE( cpu_intf ) |
| 475 | 475 | //------------------------------------------------- |
| 476 | 476 | |
| 477 | 477 | READ8_MEMBER( vic10_state::cpu_r ) |
| r17630 | r17631 | |
| 481 | 481 | bit description |
| 482 | 482 | |
| 483 | 483 | P0 EXPANSION PORT |
| 484 | | P1 1 |
| 485 | | P2 1 |
| 484 | P1 |
| 485 | P2 |
| 486 | 486 | P3 |
| 487 | 487 | P4 CASS SENS |
| 488 | | P5 |
| 488 | P5 0 |
| 489 | 489 | |
| 490 | 490 | */ |
| 491 | 491 | |
| 492 | | UINT8 data = 0x06; |
| 492 | UINT8 data = 0; |
| 493 | 493 | |
| 494 | // expansion port |
| 494 | 495 | data |= m_exp->p0_r(); |
| 495 | 496 | |
| 496 | | data |= ((m_cassette->get_state() & CASSETTE_MASK_UISTATE) == CASSETTE_STOPPED) << 4; |
| 497 | // cassette sense |
| 498 | data |= m_cassette->sense_r() << 4; |
| 497 | 499 | |
| 498 | 500 | return data; |
| 499 | 501 | } |
| r17630 | r17631 | |
| 519 | 521 | } |
| 520 | 522 | |
| 521 | 523 | // cassette write |
| 522 | | m_cassette->output(BIT(data, 3) ? -(0x5a9e >> 1) : +(0x5a9e >> 1)); |
| 524 | m_cassette->write(BIT(data, 3)); |
| 523 | 525 | |
| 524 | 526 | // cassette motor |
| 525 | | if (!BIT(data, 5)) |
| 526 | | { |
| 527 | | m_cassette->change_state(CASSETTE_MOTOR_ENABLED, CASSETTE_MASK_MOTOR); |
| 528 | | m_cassette_timer->adjust(attotime::zero, 0, attotime::from_hz(44100)); |
| 529 | | } |
| 530 | | else |
| 531 | | { |
| 532 | | m_cassette->change_state(CASSETTE_MOTOR_DISABLED, CASSETTE_MASK_MOTOR); |
| 533 | | m_cassette_timer->reset(); |
| 534 | | } |
| 527 | m_cassette->motor_w(BIT(data, 5)); |
| 535 | 528 | } |
| 536 | 529 | |
| 537 | | static const m6502_interface cpu_intf = |
| 530 | static M6510_INTERFACE( cpu_intf ) |
| 538 | 531 | { |
| 539 | | NULL, |
| 540 | | NULL, |
| 532 | DEVCB_NULL, |
| 533 | DEVCB_NULL, |
| 541 | 534 | DEVCB_DRIVER_MEMBER(vic10_state, cpu_r), |
| 542 | | DEVCB_DRIVER_MEMBER(vic10_state, cpu_w) |
| 535 | DEVCB_DRIVER_MEMBER(vic10_state, cpu_w), |
| 536 | 0x10, |
| 537 | 0x20 |
| 543 | 538 | }; |
| 544 | 539 | |
| 545 | 540 | |
| 546 | 541 | //------------------------------------------------- |
| 547 | | // TIMER_DEVICE_CALLBACK( cassette_tick ) |
| 542 | // PET_DATASSETTE_PORT_INTERFACE( datassette_intf ) |
| 548 | 543 | //------------------------------------------------- |
| 549 | 544 | |
| 550 | | static TIMER_DEVICE_CALLBACK( cassette_tick ) |
| 545 | static PET_DATASSETTE_PORT_INTERFACE( datassette_intf ) |
| 551 | 546 | { |
| 552 | | vic10_state *state = timer.machine().driver_data<vic10_state>(); |
| 547 | DEVCB_DEVICE_LINE(MOS6526_TAG, mos6526_flag_w) |
| 548 | }; |
| 553 | 549 | |
| 554 | | mos6526_flag_w(state->m_cia, state->m_cassette->input() > +0.0); |
| 555 | | } |
| 556 | 550 | |
| 557 | | |
| 558 | 551 | //------------------------------------------------- |
| 559 | 552 | // C64_EXPANSION_INTERFACE( expansion_intf ) |
| 560 | 553 | //------------------------------------------------- |
| r17630 | r17631 | |
| 638 | 631 | |
| 639 | 632 | // devices |
| 640 | 633 | MCFG_MOS6526R1_ADD(MOS6526_TAG, VIC6566_CLOCK, cia_intf) |
| 641 | | MCFG_CASSETTE_ADD(CASSETTE_TAG, cbm_cassette_interface) |
| 642 | | MCFG_TIMER_ADD(TIMER_C1531_TAG, cassette_tick) |
| 634 | MCFG_PET_DATASSETTE_PORT_ADD(PET_DATASSETTE_PORT_TAG, datassette_intf, cbm_datassette_devices, NULL, NULL) |
| 643 | 635 | MCFG_VIC10_EXPANSION_SLOT_ADD(VIC10_EXPANSION_SLOT_TAG, VIC6566_CLOCK, expansion_intf, vic10_expansion_cards, NULL, NULL) |
| 644 | 636 | |
| 645 | 637 | // software list |