trunk/src/emu/cpu/m6502/m6502.c
| r17629 | r17630 | |
| 80 | 80 | write8_space_func wrmem_id; /* writemem callback for indexed instructions */ |
| 81 | 81 | |
| 82 | 82 | UINT8 ddr; |
| 83 | | UINT8 port; |
| 83 | UINT8 port; |
| 84 | UINT8 mask; |
| 85 | UINT8 pullup; |
| 86 | UINT8 pulldown; |
| 84 | 87 | |
| 85 | 88 | devcb_resolved_read8 in_port_func; |
| 86 | 89 | devcb_resolved_write8 out_port_func; |
| r17629 | r17630 | |
| 154 | 157 | |
| 155 | 158 | cpustate->in_port_func.resolve(intf->in_port_func, *device); |
| 156 | 159 | cpustate->out_port_func.resolve(intf->out_port_func, *device); |
| 160 | cpustate->pullup = intf->external_port_pullup; |
| 161 | cpustate->pulldown = intf->external_port_pulldown; |
| 157 | 162 | } |
| 158 | 163 | else |
| 159 | 164 | { |
| 160 | 165 | devcb_write8 nullcb = DEVCB_NULL; |
| 161 | 166 | cpustate->out_port_func.resolve(nullcb, *device); |
| 167 | cpustate->pullup = 0; |
| 168 | cpustate->pulldown = 0; |
| 162 | 169 | } |
| 163 | 170 | |
| 164 | 171 | device->save_item(NAME(cpustate->pc.w.l)); |
| r17629 | r17630 | |
| 176 | 183 | if (subtype == SUBTYPE_6510) |
| 177 | 184 | { |
| 178 | 185 | device->save_item(NAME(cpustate->port)); |
| 186 | device->save_item(NAME(cpustate->mask)); |
| 179 | 187 | device->save_item(NAME(cpustate->ddr)); |
| 188 | device->save_item(NAME(cpustate->pullup)); |
| 189 | device->save_item(NAME(cpustate->pulldown)); |
| 180 | 190 | } |
| 181 | 191 | } |
| 182 | 192 | |
| r17629 | r17630 | |
| 355 | 365 | |
| 356 | 366 | CPU_RESET_CALL(m6502); |
| 357 | 367 | cpustate->port = 0xff; |
| 368 | cpustate->mask = 0xff; |
| 358 | 369 | cpustate->ddr = 0x00; |
| 359 | 370 | } |
| 360 | 371 | |
| r17629 | r17630 | |
| 374 | 385 | case 0x0000: /* DDR */ |
| 375 | 386 | result = cpustate->ddr; |
| 376 | 387 | break; |
| 388 | |
| 377 | 389 | case 0x0001: /* Data Port */ |
| 378 | | result = cpustate->in_port_func(cpustate->ddr); |
| 379 | | result = (cpustate->ddr & cpustate->port) | (~cpustate->ddr & result); |
| 390 | { |
| 391 | UINT8 input = cpustate->in_port_func(0) & ~cpustate->ddr; |
| 392 | UINT8 mask = cpustate->mask & ~cpustate->ddr; |
| 393 | UINT8 output = cpustate->port & cpustate->ddr; |
| 394 | UINT8 pulldown = ~(cpustate->pulldown & ~cpustate->ddr); |
| 395 | |
| 396 | result = (input | mask | output) & pulldown; |
| 397 | } |
| 380 | 398 | break; |
| 381 | 399 | } |
| 400 | |
| 382 | 401 | return result; |
| 383 | 402 | } |
| 384 | 403 | |
| r17629 | r17630 | |
| 389 | 408 | switch(offset) |
| 390 | 409 | { |
| 391 | 410 | case 0x0000: /* DDR */ |
| 392 | | cpustate->ddr = data; |
| 411 | if (cpustate->ddr != data) |
| 412 | { |
| 413 | cpustate->ddr = data; |
| 414 | cpustate->mask = cpustate->port; |
| 415 | } |
| 393 | 416 | break; |
| 417 | |
| 394 | 418 | case 0x0001: /* Data Port */ |
| 395 | 419 | cpustate->port = data; |
| 396 | 420 | break; |
| 397 | 421 | } |
| 398 | 422 | |
| 399 | | cpustate->out_port_func(cpustate->ddr, cpustate->port & cpustate->ddr); |
| 423 | UINT8 output = (cpustate->port & cpustate->ddr) | (cpustate->pullup & ~cpustate->ddr); |
| 424 | |
| 425 | cpustate->out_port_func(0, output); |
| 426 | |
| 427 | // TODO assert write with floating data lines |
| 428 | //WRMEM(offset, 0xff); |
| 400 | 429 | } |
| 401 | 430 | |
| 402 | 431 | static ADDRESS_MAP_START(m6510_mem, AS_PROGRAM, 8, legacy_cpu_device) |
trunk/src/emu/cpu/m6502/m6502.h
| r17629 | r17630 | |
| 53 | 53 | |
| 54 | 54 | |
| 55 | 55 | /* Optional interface to set callbacks */ |
| 56 | #define M6510_INTERFACE(name) \ |
| 57 | const m6502_interface (name) = |
| 58 | |
| 56 | 59 | typedef struct _m6502_interface m6502_interface; |
| 57 | 60 | struct _m6502_interface |
| 58 | 61 | { |
| r17629 | r17630 | |
| 60 | 63 | write8_space_func write_indexed_func; |
| 61 | 64 | devcb_read8 in_port_func; |
| 62 | 65 | devcb_write8 out_port_func; |
| 66 | UINT8 external_port_pullup; |
| 67 | UINT8 external_port_pulldown; |
| 63 | 68 | }; |
| 64 | 69 | |
| 65 | 70 | DECLARE_LEGACY_CPU_DEVICE(M6502, m6502); |
trunk/src/mess/drivers/c64.c
| r17629 | r17630 | |
| 2 | 2 | |
| 3 | 3 | TODO: |
| 4 | 4 | |
| 5 | - floating bus writes to peripheral registers in m6502.c |
| 5 | 6 | - sort out kernals between PAL/NTSC |
| 6 | 7 | - tsuit215 test failures |
| 7 | | |
| 8 | | - CPUPORT (0=FF 1=FF 0=00 1=FF 1=FF 1=FF, AFTER 00 17, RIGHT 00 DF) |
| 9 | 8 | - IRQ (WRONG $DC0D) |
| 10 | 9 | - NMI (WRONG $DD0D) |
| 11 | 10 | - all CIA tests |
| r17629 | r17630 | |
| 188 | 187 | |
| 189 | 188 | bankswitch(offset, va, rw, aec, ba, cas, &casram, &basic, &kernal, &charom, &grw, &io, &roml, &romh); |
| 190 | 189 | |
| 190 | if (offset < 0x0002) |
| 191 | { |
| 192 | // write to internal CPU register |
| 193 | data = m_vic->bus_r(); |
| 194 | } |
| 195 | |
| 191 | 196 | if (!casram) |
| 192 | 197 | { |
| 193 | 198 | m_ram->pointer()[offset] = data; |
| r17629 | r17630 | |
| 658 | 663 | P0 1 |
| 659 | 664 | P1 1 |
| 660 | 665 | P2 1 |
| 661 | | P3 |
| 666 | P3 |
| 662 | 667 | P4 CASS SENS |
| 663 | | P5 |
| 668 | P5 0 |
| 664 | 669 | |
| 665 | 670 | */ |
| 666 | 671 | |
| r17629 | r17630 | |
| 686 | 691 | |
| 687 | 692 | */ |
| 688 | 693 | |
| 689 | | // HACK apply pull-up resistors |
| 690 | | data |= (offset ^ 0x07) & 0x07; |
| 691 | | |
| 694 | // memory banking |
| 692 | 695 | m_loram = BIT(data, 0); |
| 693 | 696 | m_hiram = BIT(data, 1); |
| 694 | 697 | m_charen = BIT(data, 2); |
| r17629 | r17630 | |
| 700 | 703 | m_cassette->motor_w(BIT(data, 5)); |
| 701 | 704 | } |
| 702 | 705 | |
| 703 | | static const m6502_interface cpu_intf = |
| 706 | static M6510_INTERFACE( cpu_intf ) |
| 704 | 707 | { |
| 705 | 708 | NULL, |
| 706 | 709 | NULL, |
| 707 | 710 | DEVCB_DRIVER_MEMBER(c64_state, cpu_r), |
| 708 | | DEVCB_DRIVER_MEMBER(c64_state, cpu_w) |
| 711 | DEVCB_DRIVER_MEMBER(c64_state, cpu_w), |
| 712 | 0x17, |
| 713 | 0x20 |
| 709 | 714 | }; |
| 710 | 715 | |
| 711 | 716 | |
| r17629 | r17630 | |
| 722 | 727 | P0 1 |
| 723 | 728 | P1 1 |
| 724 | 729 | P2 1 |
| 725 | | P3 1 |
| 726 | | P4 1 |
| 727 | | P5 1 |
| 730 | P3 |
| 731 | P4 |
| 732 | P5 |
| 728 | 733 | |
| 729 | 734 | */ |
| 730 | 735 | |
| 731 | | return 0x3f; |
| 736 | return 0x07; |
| 732 | 737 | } |
| 733 | 738 | |
| 734 | 739 | WRITE8_MEMBER( sx64_state::cpu_w ) |
| r17629 | r17630 | |
| 746 | 751 | |
| 747 | 752 | */ |
| 748 | 753 | |
| 749 | | // HACK apply pull-up resistors |
| 750 | | data |= (offset ^ 0x07) & 0x07; |
| 751 | | |
| 754 | // memory banking |
| 752 | 755 | m_loram = BIT(data, 0); |
| 753 | 756 | m_hiram = BIT(data, 1); |
| 754 | 757 | m_charen = BIT(data, 2); |
| 755 | 758 | } |
| 756 | 759 | |
| 757 | | static const m6502_interface sx64_cpu_intf = |
| 760 | static M6510_INTERFACE( sx64_cpu_intf ) |
| 758 | 761 | { |
| 759 | 762 | NULL, |
| 760 | 763 | NULL, |
| 761 | 764 | DEVCB_DRIVER_MEMBER(sx64_state, cpu_r), |
| 762 | | DEVCB_DRIVER_MEMBER(sx64_state, cpu_w) |
| 765 | DEVCB_DRIVER_MEMBER(sx64_state, cpu_w), |
| 766 | 0x07, |
| 767 | 0x00 |
| 763 | 768 | }; |
| 764 | 769 | |
| 765 | 770 | |
| r17629 | r17630 | |
| 776 | 781 | P0 1 |
| 777 | 782 | P1 1 |
| 778 | 783 | P2 1 |
| 779 | | P3 1 |
| 780 | | P4 1 |
| 781 | | P5 1 |
| 784 | P3 |
| 785 | P4 |
| 786 | P5 |
| 782 | 787 | |
| 783 | 788 | */ |
| 784 | 789 | |
| 785 | | return 0x3f; |
| 790 | return 0x07; |
| 786 | 791 | } |
| 787 | 792 | |
| 788 | 793 | WRITE8_MEMBER( c64gs_state::cpu_w ) |
| r17629 | r17630 | |
| 800 | 805 | |
| 801 | 806 | */ |
| 802 | 807 | |
| 803 | | // HACK apply pull-up resistors |
| 804 | | data |= (offset ^ 0x07) & 0x07; |
| 805 | | |
| 808 | // memory banking |
| 806 | 809 | m_loram = BIT(data, 0); |
| 807 | 810 | m_hiram = BIT(data, 1); |
| 808 | 811 | m_charen = BIT(data, 2); |
| r17629 | r17630 | |
| 813 | 816 | NULL, |
| 814 | 817 | NULL, |
| 815 | 818 | DEVCB_DRIVER_MEMBER(c64gs_state, cpu_r), |
| 816 | | DEVCB_DRIVER_MEMBER(c64gs_state, cpu_w) |
| 819 | DEVCB_DRIVER_MEMBER(c64gs_state, cpu_w), |
| 820 | 0x07, |
| 821 | 0x00 |
| 817 | 822 | }; |
| 818 | 823 | |
| 819 | 824 | |