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r17425 Thursday 23rd August, 2012 at 16:04:33 UTC by Tafoid
Started making 32x a device, by creating a device and moving the cpus there.  From Haze. (nw)

[src/mame/includes]	megadriv.h
[src/mame/machine]	mega32x.c mega32x.h* megadriv.c
[src/mess/drivers]	megadriv.c

trunk/src/mame/machine/mega32x.c

r17424	r17425
195	195	#161 Runlength Mode
196	196
197	197	*/
198
	198	#include "emu.h"
199	199	#include "includes/megadriv.h"
200	200
201	201
	202
202	203	/* the main Megadrive emulation needs to know this */
203	204	int _32x_is_connected;
204	205	cpu_device *_32x_master_cpu;
r17424	r17425
251	252
252	253
253	254
	255	const device_type SEGA_32X_NTSC = &device_creator<sega_32x_ntsc_device>;
	256	const device_type SEGA_32X_PAL = &device_creator<sega_32x_pal_device>;
	257
	258	sega_32x_device::sega_32x_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock, device_type type)
	259	: device_t(mconfig, type, "sega_32x_device", tag, owner, clock),
	260	m_lch_pwm(*this, "lch_pwm"),
	261	m_rch_pwm(*this, "rch_pwm")
	262	{
	263
	264	}
	265
	266	sega_32x_ntsc_device::sega_32x_ntsc_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	267	: sega_32x_device(mconfig, tag, owner, clock, SEGA_32X_NTSC)
	268	{
	269
	270	}
	271
	272	sega_32x_pal_device::sega_32x_pal_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	273	: sega_32x_device(mconfig, tag, owner, clock, SEGA_32X_PAL)
	274	{
	275
	276	}
	277
	278	TIMER_CALLBACK( _32x_pwm_callback );
	279
254	280	/****************************************** 32X related ******************************************/
255	281
256	282	/**********************************************************************************************/
r17424	r17425
607	633	current_fifo_block = fifo_block_b;
608	634	current_fifo_readblock = fifo_block_a;
609	635	// incase we have a stalled DMA in progress, let the SH2 know there is data available
610		sh2_notify_dma_data_available(space->machine().device("32x_master_sh2"));
611		sh2_notify_dma_data_available(space->machine().device("32x_slave_sh2"));
	636	sh2_notify_dma_data_available(space->machine().device(_32X_MASTER_TAG));
	637	sh2_notify_dma_data_available(space->machine().device(_32X_SLAVE_TAG));
612	638
613	639	}
614	640	current_fifo_write_pos = 0;
r17424	r17425
622	648	current_fifo_block = fifo_block_a;
623	649	current_fifo_readblock = fifo_block_b;
624	650	// incase we have a stalled DMA in progress, let the SH2 know there is data available
625		sh2_notify_dma_data_available(space->machine().device("32x_master_sh2"));
626		sh2_notify_dma_data_available(space->machine().device("32x_slave_sh2"));
	651	sh2_notify_dma_data_available(space->machine().device(_32X_MASTER_TAG));
	652	sh2_notify_dma_data_available(space->machine().device(_32X_SLAVE_TAG));
627	653
628	654	}
629	655
r17424	r17425
847	873	static UINT8 lch_index_r,rch_index_r,lch_index_w,rch_index_w;
848	874	static UINT16 lch_fifo_state,rch_fifo_state;
849	875
850		emu_timer *_32x_pwm_timer;
851	876
852		static void calculate_pwm_timer(void)
	877
	878	static void calculate_pwm_timer(running_machine &machine)
853	879	{
	880	sega_32x_device* _32xdev = (sega_32x_device*)machine.device(":sega32x");
	881
	882
854	883	if(pwm_tm_reg == 0) { pwm_tm_reg = 16; } // zero gives max range
855	884	if(pwm_cycle == 0) { pwm_cycle = 4095; } // zero gives max range
856	885
857	886	/* if both RMD and LMD are set to OFF or pwm cycle register is one, then PWM timer ticks doesn't occur */
858	887	if(pwm_cycle == 1 || ((pwm_ctrl & 0xf) == 0))
859		_32x_pwm_timer->adjust(attotime::never);
	888	_32xdev->m_32x_pwm_timer->adjust(attotime::never);
860	889	else
861	890	{
862	891	pwm_timer_tick = 0;
863	892	lch_fifo_state = rch_fifo_state = 0x4000;
864	893	lch_index_r = rch_index_r = 0;
865	894	lch_index_w = rch_index_w = 0;
866		_32x_pwm_timer->adjust(attotime::from_hz((PWM_CLOCK) / (pwm_cycle - 1)));
	895	_32xdev->m_32x_pwm_timer->adjust(attotime::from_hz((PWM_CLOCK) / (pwm_cycle - 1)));
867	896	}
868	897	}
869	898
870	899	TIMER_CALLBACK( _32x_pwm_callback )
871	900	{
	901	sega_32x_device* _32xdev = (sega_32x_device*)ptr;
	902
	903
872	904	if(lch_index_r < PWM_FIFO_SIZE)
873	905	{
874	906	switch(pwm_ctrl & 3)
875	907	{
876	908	case 0: lch_index_r++; /*Speaker OFF*/ break;
877		case 1: machine.device<dac_device>("lch_pwm")->write_signed16(cur_lch[lch_index_r++]); break;
878		case 2: machine.device<dac_device>("rch_pwm")->write_signed16(cur_lch[lch_index_r++]); break;
	909	case 1: _32xdev->m_lch_pwm->write_signed16(cur_lch[lch_index_r++]); break;
	910	case 2: _32xdev->m_rch_pwm->write_signed16(cur_lch[lch_index_r++]); break;
879	911	case 3: popmessage("Undefined PWM Lch value 3, contact MESSdev"); break;
880	912	}
881	913
r17424	r17425
889	921	switch((pwm_ctrl & 0xc) >> 2)
890	922	{
891	923	case 0: rch_index_r++; /*Speaker OFF*/ break;
892		case 1: machine.device<dac_device>("rch_pwm")->write_signed16(cur_rch[rch_index_r++]); break;
893		case 2: machine.device<dac_device>("lch_pwm")->write_signed16(cur_rch[rch_index_r++]); break;
	924	case 1: _32xdev->m_rch_pwm->write_signed16(cur_rch[rch_index_r++]); break;
	925	case 2: _32xdev->m_lch_pwm->write_signed16(cur_rch[rch_index_r++]); break;
894	926	case 3: popmessage("Undefined PWM Rch value 3, contact MESSdev"); break;
895	927	}
896	928
r17424	r17425
908	940	if(sh2_slave_pwmint_enable) { device_set_input_line(_32x_slave_cpu, SH2_PINT_IRQ_LEVEL,ASSERT_LINE); }
909	941	}
910	942
911		_32x_pwm_timer->adjust(attotime::from_hz((PWM_CLOCK) / (pwm_cycle - 1)));
	943	_32xdev->m_32x_pwm_timer->adjust(attotime::from_hz((PWM_CLOCK) / (pwm_cycle - 1)));
912	944	}
913	945
914	946	static READ16_HANDLER( _32x_pwm_r )
r17424	r17425
928	960
929	961	static WRITE16_HANDLER( _32x_pwm_w )
930	962	{
	963
931	964	switch(offset)
932	965	{
933	966	case 0x00/2:
934	967	pwm_ctrl = data & 0xffff;
935	968	pwm_tm_reg = (pwm_ctrl & 0xf00) >> 8;
936		calculate_pwm_timer();
	969	calculate_pwm_timer(space->machine());
937	970	break;
938	971	case 0x02/2:
939	972	pwm_cycle = pwm_cycle_reg = data & 0xfff;
940		calculate_pwm_timer();
	973	calculate_pwm_timer(space->machine());
941	974	break;
942	975	case 0x04/2:
943	976	if(lch_index_w < PWM_FIFO_SIZE)
r17424	r17425
1426	1459	// these just map through to the 68k functions
1427	1460	/**********************************************************************************************/
1428	1461
1429		static READ16_HANDLER( _32x_sh2_commsram16_r ) { return _32x_68k_commsram_r(space, offset, mem_mask); }
1430		static WRITE16_HANDLER( _32x_sh2_commsram16_w ) { _32x_68k_commsram_w(space, offset, data, mem_mask); }
	1462	/* handled directly */
1431	1463
1432	1464	/**********************************************************************************************/
1433	1465	// SH2 side 4030
r17424	r17425
1463	1495	// maps through to 68k at a15200 - a153ff
1464	1496	/**********************************************************************************************/
1465	1497
1466		static READ16_HANDLER( _32x_sh2_paletteram16_r ) { return _32x_68k_palette_r(space,offset,mem_mask); }
1467		static WRITE16_HANDLER( _32x_sh2_paletteram16_w ) { _32x_68k_palette_w(space,offset,data,mem_mask); }
	1498	/* handled directly */
1468	1499
1469	1500	/**********************************************************************************************/
1470	1501	// SH2 side 4000000 - 401ffff
r17424	r17425
1472	1503	// maps through to 68k at 840000 - 85ffff
1473	1504	/**********************************************************************************************/
1474	1505
1475		static READ16_HANDLER( _32x_sh2_framebuffer_dram16_r ) { return _32x_68k_dram_r(space,offset,mem_mask); }
1476		static WRITE16_HANDLER( _32x_sh2_framebuffer_dram16_w ) { _32x_68k_dram_w(space,offset,data,mem_mask); }
	1506	/* handled directly */
1477	1507
1478	1508	/**********************************************************************************************/
1479	1509	// SH2 side 4020000 - 403ffff
r17424	r17425
1481	1511	// maps through to 68k at 860000 - 87ffff
1482	1512	/**********************************************************************************************/
1483	1513
1484		static READ16_HANDLER( _32x_sh2_framebuffer_overwrite_dram16_r ) { return _32x_68k_dram_overwrite_r(space,offset,mem_mask); }
1485		static WRITE16_HANDLER( _32x_sh2_framebuffer_overwrite_dram16_w ) { _32x_68k_dram_overwrite_w(space,offset,data,mem_mask); }
	1514	/* handled directly */
1486	1515
1487
1488
1489	1516	/**********************************************************************************************/
1490	1517	// SH2 access Macros
1491	1518	/**********************************************************************************************/
r17424	r17425
1495	1522	to 2x 16-bit handlers here (TODO: nuke this eventually) */
1496	1523
1497	1524	#define _32X_MAP_READHANDLERS(NAMEA,NAMEB)                                          \
1498		static READ32_HANDLER( _32x_sh2_##NAMEA##_##NAMEB##_r )                             \
	1525	READ32_MEMBER( sega_32x_device::_32x_sh2_##NAMEA##_##NAMEB##_r )                             \
1499	1526	{                                                                                   \
1500	1527	UINT32 retvalue = 0x00000000;                                                   \
1501	1528	if (ACCESSING_BITS_16_31)                                                       \
1502	1529	{                                                                               \
1503		UINT16 ret = _32x_sh2_##NAMEA##_r(space,0,(mem_mask>>16)&0xffff);         \
	1530	UINT16 ret = _32x_sh2_##NAMEA##_r(&space,0,(mem_mask>>16)&0xffff);         \
1504	1531	retvalue |= ret << 16;                                                      \
1505	1532	}                                                                               \
1506	1533	if (ACCESSING_BITS_0_15)                                                        \
1507	1534	{                                                                               \
1508		UINT16 ret = _32x_sh2_##NAMEB##_r(space,0,(mem_mask>>0)&0xffff);          \
	1535	UINT16 ret = _32x_sh2_##NAMEB##_r(&space,0,(mem_mask>>0)&0xffff);          \
1509	1536	retvalue |= ret << 0;                                                       \
1510	1537	}                                                                               \
1511	1538	\
r17424	r17425
1513	1540	}                                                                                   \
1514	1541
1515	1542	#define _32X_MAP_WRITEHANDLERS(NAMEA,NAMEB)                                             \
1516		static WRITE32_HANDLER( _32x_sh2_##NAMEA##_##NAMEB##_w)                                 \
	1543	WRITE32_MEMBER( sega_32x_device::_32x_sh2_##NAMEA##_##NAMEB##_w)                                 \
1517	1544	{                                                                                       \
1518	1545	if (ACCESSING_BITS_16_31)                                                           \
1519	1546	{                                                                                   \
1520		_32x_sh2_##NAMEA##_w(space,0,(data>>16)&0xffff,(mem_mask>>16)&0xffff);        \
	1547	_32x_sh2_##NAMEA##_w(&space,0,(data>>16)&0xffff,(mem_mask>>16)&0xffff);        \
1521	1548	}                                                                                   \
1522	1549	if (ACCESSING_BITS_0_15)                                                            \
1523	1550	{                                                                                   \
1524		_32x_sh2_##NAMEB##_w(space,0,(data>>0)&0xffff,(mem_mask>>0)&0xffff);          \
	1551	_32x_sh2_##NAMEB##_w(&space,0,(data>>0)&0xffff,(mem_mask>>0)&0xffff);          \
1525	1552	}                                                                                   \
1526	1553	}                                                                                       \
1527	1554
1528		/* for RAM ranges, eg. Framebuffer, Comms RAM etc. */
1529	1555
1530		#define _32X_MAP_RAM_READHANDLERS(NAMEA)                                            \
1531		static READ32_HANDLER( _32x_sh2_##NAMEA##_r )                                       \
1532		{                                                                                   \
1533		UINT32 retvalue = 0x00000000;                                                   \
1534		if (ACCESSING_BITS_16_31)                                                       \
1535		{                                                                               \
1536		UINT16 ret = _32x_sh2_##NAMEA##16_r(space,offset*2,(mem_mask>>16)&0xffff);  \
1537		retvalue |= ret << 16;                                                      \
1538		}                                                                               \
1539		if (ACCESSING_BITS_0_15)                                                        \
1540		{                                                                               \
1541		UINT16 ret = _32x_sh2_##NAMEA##16_r(space,offset*2+1,(mem_mask>>0)&0xffff); \
1542		retvalue |= ret << 0;                                                       \
1543		}                                                                               \
1544		\
1545		return retvalue;                                                                \
1546		}                                                                                   \
1547	1556
1548		#define _32X_MAP_RAM_WRITEHANDLERS(NAMEA)                                               \
1549		static WRITE32_HANDLER( _32x_sh2_##NAMEA##_w)                                           \
1550		{                                                                                       \
1551		if (ACCESSING_BITS_16_31)                                                           \
1552		{                                                                                   \
1553		_32x_sh2_##NAMEA##16_w(space,offset*2,(data>>16)&0xffff,(mem_mask>>16)&0xffff); \
1554		}                                                                                   \
1555		if (ACCESSING_BITS_0_15)                                                            \
1556		{                                                                                   \
1557		_32x_sh2_##NAMEA##16_w(space,offset*2+1,(data>>0)&0xffff,(mem_mask>>0)&0xffff); \
1558		}                                                                                   \
1559		}                                                                                       \
1560	1557
1561
1562
1563	1558	/**********************************************************************************************/
1564	1559	// SH2 access for Memory Map
1565	1560	/**********************************************************************************************/
1566	1561
1567
1568	1562	_32X_MAP_READHANDLERS(master_4000,common_4002)  // _32x_sh2_master_4000_common_4002_r
1569	1563	_32X_MAP_WRITEHANDLERS(master_4000,common_4002) // _32x_sh2_master_4000_common_4002_w
1570	1564
r17424	r17425
1582	1576	_32X_MAP_WRITEHANDLERS(slave_4018,slave_401a) // _32x_sh2_slave_4018_slave_401a_w
1583	1577	_32X_MAP_WRITEHANDLERS(slave_401c,slave_401e) // _32x_sh2_slave_401c_slave_401e_w
1584	1578
1585		_32X_MAP_RAM_READHANDLERS(commsram) // _32x_sh2_commsram_r
1586		_32X_MAP_RAM_WRITEHANDLERS(commsram) // _32x_sh2_commsram_w
1587	1579
1588		_32X_MAP_RAM_READHANDLERS(framebuffer_dram) // _32x_sh2_framebuffer_dram_r
1589		_32X_MAP_RAM_WRITEHANDLERS(framebuffer_dram) // _32x_sh2_framebuffer_dram_w
1590	1580
1591		_32X_MAP_RAM_READHANDLERS(framebuffer_overwrite_dram) // _32x_sh2_framebuffer_overwrite_dram_r
1592		_32X_MAP_RAM_WRITEHANDLERS(framebuffer_overwrite_dram) // _32x_sh2_framebuffer_overwrite_dram_w
1593
1594		_32X_MAP_RAM_READHANDLERS(paletteram) // _32x_sh2_paletteram_r
1595		_32X_MAP_RAM_WRITEHANDLERS(paletteram) // _32x_sh2_paletteram_w
1596
1597
1598	1581	/**********************************************************************************************/
1599	1582	// SH2 memory maps
1600	1583	/**********************************************************************************************/
1601	1584
1602		ADDRESS_MAP_START( sh2_main_map, AS_PROGRAM, 32, driver_device )
1603		AM_RANGE(0x00000000, 0x00003fff) AM_ROM
	1585	ADDRESS_MAP_START( sh2_main_map, AS_PROGRAM, 32, sega_32x_device )
	1586	AM_RANGE(0x00000000, 0x00003fff) AM_ROMBANK("masterbios")
1604	1587
1605		AM_RANGE(0x00004000, 0x00004003) AM_READWRITE_LEGACY(_32x_sh2_master_4000_common_4002_r, _32x_sh2_master_4000_common_4002_w )
1606		AM_RANGE(0x00004004, 0x00004007) AM_READWRITE_LEGACY(_32x_sh2_common_4004_common_4006_r, _32x_sh2_common_4004_common_4006_w)
	1588	AM_RANGE(0x00004000, 0x00004003) AM_READWRITE(_32x_sh2_master_4000_common_4002_r, _32x_sh2_master_4000_common_4002_w )
	1589	AM_RANGE(0x00004004, 0x00004007) AM_READWRITE(_32x_sh2_common_4004_common_4006_r, _32x_sh2_common_4004_common_4006_w)
1607	1590
1608	1591	AM_RANGE(0x00004008, 0x00004013) AM_READWRITE16_LEGACY(_32x_dreq_common_r, _32x_dreq_common_w, 0xffffffff )
1609	1592
1610		AM_RANGE(0x00004014, 0x00004017) AM_READNOP AM_WRITE_LEGACY(_32x_sh2_master_4014_master_4016_w ) // IRQ clear
1611		AM_RANGE(0x00004018, 0x0000401b) AM_READNOP AM_WRITE_LEGACY(_32x_sh2_master_4018_master_401a_w ) // IRQ clear
1612		AM_RANGE(0x0000401c, 0x0000401f) AM_READNOP AM_WRITE_LEGACY(_32x_sh2_master_401c_master_401e_w ) // IRQ clear
	1593	AM_RANGE(0x00004014, 0x00004017) AM_READNOP AM_WRITE(_32x_sh2_master_4014_master_4016_w ) // IRQ clear
	1594	AM_RANGE(0x00004018, 0x0000401b) AM_READNOP AM_WRITE(_32x_sh2_master_4018_master_401a_w ) // IRQ clear
	1595	AM_RANGE(0x0000401c, 0x0000401f) AM_READNOP AM_WRITE(_32x_sh2_master_401c_master_401e_w ) // IRQ clear
1613	1596
1614		AM_RANGE(0x00004020, 0x0000402f) AM_READWRITE_LEGACY(_32x_sh2_commsram_r, _32x_sh2_commsram_w )
	1597	AM_RANGE(0x00004020, 0x0000402f) AM_READWRITE16_LEGACY(_32x_68k_commsram_r, _32x_68k_commsram_w, 0xffffffff )
1615	1598	AM_RANGE(0x00004030, 0x0000403f) AM_READWRITE16_LEGACY(_32x_pwm_r, _32x_pwm_w, 0xffffffff )
1616	1599
1617	1600	AM_RANGE(0x00004100, 0x0000410b) AM_READWRITE16_LEGACY(_32x_common_vdp_regs_r, _32x_common_vdp_regs_w , 0xffffffff)
1618		AM_RANGE(0x00004200, 0x000043ff) AM_READWRITE_LEGACY(_32x_sh2_paletteram_r, _32x_sh2_paletteram_w)
	1601	AM_RANGE(0x00004200, 0x000043ff) AM_READWRITE16_LEGACY(_32x_68k_palette_r, _32x_68k_palette_w, 0xffffffff)
1619	1602
1620		AM_RANGE(0x04000000, 0x0401ffff) AM_READWRITE_LEGACY(_32x_sh2_framebuffer_dram_r, _32x_sh2_framebuffer_dram_w)
1621		AM_RANGE(0x04020000, 0x0403ffff) AM_READWRITE_LEGACY(_32x_sh2_framebuffer_overwrite_dram_r, _32x_sh2_framebuffer_overwrite_dram_w)
	1603	AM_RANGE(0x04000000, 0x0401ffff) AM_READWRITE16_LEGACY(_32x_68k_dram_r, _32x_68k_dram_w, 0xffffffff)
	1604	AM_RANGE(0x04020000, 0x0403ffff) AM_READWRITE16_LEGACY(_32x_68k_dram_overwrite_r, _32x_68k_dram_overwrite_w, 0xffffffff)
1622	1605
1623		AM_RANGE(0x06000000, 0x0603ffff) AM_RAM AM_SHARE("share10")
1624		AM_RANGE(0x02000000, 0x023fffff) AM_ROM AM_REGION("gamecart_sh2", 0) // program is writeable (wwfraw)
	1606	AM_RANGE(0x06000000, 0x0603ffff) AM_RAM AM_SHARE("sh2_shared")
	1607	AM_RANGE(0x02000000, 0x023fffff) AM_ROM AM_REGION(":gamecart_sh2", 0) // program is writeable (wwfraw)
1625	1608
1626		AM_RANGE(0x22000000, 0x223fffff) AM_ROM AM_REGION("gamecart_sh2", 0) // cart mirror (fifa96)
	1609	AM_RANGE(0x22000000, 0x223fffff) AM_ROM AM_REGION(":gamecart_sh2", 0) // cart mirror (fifa96)
1627	1610
1628	1611	AM_RANGE(0xc0000000, 0xc0000fff) AM_RAM
1629	1612	ADDRESS_MAP_END
1630	1613
1631		ADDRESS_MAP_START( sh2_slave_map, AS_PROGRAM, 32, driver_device )
1632		AM_RANGE(0x00000000, 0x00003fff) AM_ROM
	1614	ADDRESS_MAP_START( sh2_slave_map, AS_PROGRAM, 32, sega_32x_device )
	1615	AM_RANGE(0x00000000, 0x00003fff) AM_ROMBANK("slavebios")
1633	1616
1634		AM_RANGE(0x00004000, 0x00004003) AM_READWRITE_LEGACY(_32x_sh2_slave_4000_common_4002_r, _32x_sh2_slave_4000_common_4002_w )
1635		AM_RANGE(0x00004004, 0x00004007) AM_READWRITE_LEGACY(_32x_sh2_common_4004_common_4006_r, _32x_sh2_common_4004_common_4006_w)
	1617	AM_RANGE(0x00004000, 0x00004003) AM_READWRITE(_32x_sh2_slave_4000_common_4002_r, _32x_sh2_slave_4000_common_4002_w )
	1618	AM_RANGE(0x00004004, 0x00004007) AM_READWRITE(_32x_sh2_common_4004_common_4006_r, _32x_sh2_common_4004_common_4006_w)
1636	1619
1637	1620	AM_RANGE(0x00004008, 0x00004013) AM_READWRITE16_LEGACY(_32x_dreq_common_r, _32x_dreq_common_w, 0xffffffff )
1638	1621
1639		AM_RANGE(0x00004014, 0x00004017) AM_READNOP AM_WRITE_LEGACY(_32x_sh2_slave_4014_slave_4016_w ) // IRQ clear
1640		AM_RANGE(0x00004018, 0x0000401b) AM_READNOP AM_WRITE_LEGACY(_32x_sh2_slave_4018_slave_401a_w ) // IRQ clear
1641		AM_RANGE(0x0000401c, 0x0000401f) AM_READNOP AM_WRITE_LEGACY(_32x_sh2_slave_401c_slave_401e_w ) // IRQ clear
	1622	AM_RANGE(0x00004014, 0x00004017) AM_READNOP AM_WRITE(_32x_sh2_slave_4014_slave_4016_w ) // IRQ clear
	1623	AM_RANGE(0x00004018, 0x0000401b) AM_READNOP AM_WRITE(_32x_sh2_slave_4018_slave_401a_w ) // IRQ clear
	1624	AM_RANGE(0x0000401c, 0x0000401f) AM_READNOP AM_WRITE(_32x_sh2_slave_401c_slave_401e_w ) // IRQ clear
1642	1625
1643		AM_RANGE(0x00004020, 0x0000402f) AM_READWRITE_LEGACY(_32x_sh2_commsram_r, _32x_sh2_commsram_w )
	1626	AM_RANGE(0x00004020, 0x0000402f) AM_READWRITE16_LEGACY(_32x_68k_commsram_r, _32x_68k_commsram_w, 0xffffffff )
1644	1627	AM_RANGE(0x00004030, 0x0000403f) AM_READWRITE16_LEGACY(_32x_pwm_r, _32x_pwm_w, 0xffffffff )
1645	1628
1646	1629	AM_RANGE(0x00004100, 0x0000410b) AM_READWRITE16_LEGACY(_32x_common_vdp_regs_r, _32x_common_vdp_regs_w , 0xffffffff)
1647		AM_RANGE(0x00004200, 0x000043ff) AM_READWRITE_LEGACY(_32x_sh2_paletteram_r, _32x_sh2_paletteram_w)
	1630	AM_RANGE(0x00004200, 0x000043ff) AM_READWRITE16_LEGACY(_32x_68k_palette_r, _32x_68k_palette_w, 0xffffffff)
1648	1631
1649		AM_RANGE(0x04000000, 0x0401ffff) AM_READWRITE_LEGACY(_32x_sh2_framebuffer_dram_r, _32x_sh2_framebuffer_dram_w)
1650		AM_RANGE(0x04020000, 0x0403ffff) AM_READWRITE_LEGACY(_32x_sh2_framebuffer_overwrite_dram_r, _32x_sh2_framebuffer_overwrite_dram_w)
	1632	AM_RANGE(0x04000000, 0x0401ffff) AM_READWRITE16_LEGACY(_32x_68k_dram_r, _32x_68k_dram_w, 0xffffffff)
	1633	AM_RANGE(0x04020000, 0x0403ffff) AM_READWRITE16_LEGACY(_32x_68k_dram_overwrite_r, _32x_68k_dram_overwrite_w, 0xffffffff)
1651	1634
1652		AM_RANGE(0x06000000, 0x0603ffff) AM_RAM AM_SHARE("share10")
1653		AM_RANGE(0x02000000, 0x023fffff) AM_ROM AM_REGION("gamecart_sh2", 0) // program is writeable (wwfraw)
	1635	AM_RANGE(0x06000000, 0x0603ffff) AM_RAM AM_SHARE("sh2_shared")
	1636	AM_RANGE(0x02000000, 0x023fffff) AM_ROM AM_REGION(":gamecart_sh2", 0) // program is writeable (wwfraw)
1654	1637
1655		AM_RANGE(0x22000000, 0x223fffff) AM_ROM AM_REGION("gamecart_sh2", 0) // cart mirror (fifa96)
	1638	AM_RANGE(0x22000000, 0x223fffff) AM_ROM AM_REGION(":gamecart_sh2", 0) // cart mirror (fifa96)
1656	1639
1657	1640	AM_RANGE(0xc0000000, 0xc0000fff) AM_RAM
1658	1641	ADDRESS_MAP_END
r17424	r17425
1663	1646
1664	1647	DRIVER_INIT_MEMBER(md_cons_state,_32x)
1665	1648	{
1666		_32x_dram0 = auto_alloc_array(machine(), UINT16, 0x40000/2);
1667		_32x_dram1 = auto_alloc_array(machine(), UINT16, 0x40000/2);
1668	1649
1669		memset(_32x_dram0, 0x00, 0x40000);
1670		memset(_32x_dram1, 0x00, 0x40000);
1671	1650
1672		_32x_palette_lookup = auto_alloc_array(machine(), UINT16, 0x200/2);
1673		_32x_palette = auto_alloc_array(machine(), UINT16, 0x200/2);
1674	1651
1675		memset(_32x_palette_lookup, 0x00, 0x200);
1676		memset(_32x_palette, 0x00, 0x200);
1677
1678
1679		_32x_display_dram = _32x_dram0;
1680		_32x_access_dram = _32x_dram1;
1681
1682	1652	_32x_adapter_enabled = 0;
1683	1653
1684	1654	if (_32x_adapter_enabled == 0)
1685	1655	{
1686		machine().device("maincpu")->memory().space(AS_PROGRAM)->install_rom(0x0000000, 0x03fffff, machine().root_device().memregion("gamecart")->base());
1687		machine().device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_readwrite_handler(0x000070, 0x000073, FUNC(_32x_68k_hint_vector_r), FUNC(_32x_68k_hint_vector_w)); // h interrupt vector
	1656	machine().device(":maincpu")->memory().space(AS_PROGRAM)->install_rom(0x0000000, 0x03fffff, machine().root_device().memregion(":gamecart")->base());
	1657	machine().device(":maincpu")->memory().space(AS_PROGRAM)->install_legacy_readwrite_handler(0x000070, 0x000073, FUNC(_32x_68k_hint_vector_r), FUNC(_32x_68k_hint_vector_w)); // h interrupt vector
1688	1658	};
1689	1659
1690	1660
1691	1661	a15100_reg = 0x0000;
1692		machine().device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_readwrite_handler(0xa15100, 0xa15101, FUNC(_32x_68k_a15100_r), FUNC(_32x_68k_a15100_w)); // framebuffer control regs
1693		machine().device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_readwrite_handler(0xa15102, 0xa15103, FUNC(_32x_68k_a15102_r), FUNC(_32x_68k_a15102_w)); // send irq to sh2
1694		machine().device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_readwrite_handler(0xa15104, 0xa15105, FUNC(_32x_68k_a15104_r), FUNC(_32x_68k_a15104_w)); // 68k BANK rom set
1695		machine().device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_readwrite_handler(0xa15106, 0xa15107, FUNC(_32x_68k_a15106_r), FUNC(_32x_68k_a15106_w)); // dreq stuff
1696		machine().device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_readwrite_handler(0xa15108, 0xa15113, FUNC(_32x_dreq_common_r), FUNC(_32x_dreq_common_w)); // dreq src / dst / length /fifo
	1662	machine().device(":maincpu")->memory().space(AS_PROGRAM)->install_legacy_readwrite_handler(0xa15100, 0xa15101, FUNC(_32x_68k_a15100_r), FUNC(_32x_68k_a15100_w)); // framebuffer control regs
	1663	machine().device(":maincpu")->memory().space(AS_PROGRAM)->install_legacy_readwrite_handler(0xa15102, 0xa15103, FUNC(_32x_68k_a15102_r), FUNC(_32x_68k_a15102_w)); // send irq to sh2
	1664	machine().device(":maincpu")->memory().space(AS_PROGRAM)->install_legacy_readwrite_handler(0xa15104, 0xa15105, FUNC(_32x_68k_a15104_r), FUNC(_32x_68k_a15104_w)); // 68k BANK rom set
	1665	machine().device(":maincpu")->memory().space(AS_PROGRAM)->install_legacy_readwrite_handler(0xa15106, 0xa15107, FUNC(_32x_68k_a15106_r), FUNC(_32x_68k_a15106_w)); // dreq stuff
	1666	machine().device(":maincpu")->memory().space(AS_PROGRAM)->install_legacy_readwrite_handler(0xa15108, 0xa15113, FUNC(_32x_dreq_common_r), FUNC(_32x_dreq_common_w)); // dreq src / dst / length /fifo
1697	1667
1698		machine().device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_readwrite_handler(0xa1511a, 0xa1511b, FUNC(_32x_68k_a1511a_r), FUNC(_32x_68k_a1511a_w)); // SEGA TV
	1668	machine().device(":maincpu")->memory().space(AS_PROGRAM)->install_legacy_readwrite_handler(0xa1511a, 0xa1511b, FUNC(_32x_68k_a1511a_r), FUNC(_32x_68k_a1511a_w)); // SEGA TV
1699	1669
1700		machine().device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_readwrite_handler(0xa15120, 0xa1512f, FUNC(_32x_68k_commsram_r), FUNC(_32x_68k_commsram_w)); // comms reg 0-7
1701		machine().device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_readwrite_handler(0xa15130, 0xa1513f, FUNC(_32x_pwm_r), FUNC(_32x_68k_pwm_w));
	1670	machine().device(":maincpu")->memory().space(AS_PROGRAM)->install_legacy_readwrite_handler(0xa15120, 0xa1512f, FUNC(_32x_68k_commsram_r), FUNC(_32x_68k_commsram_w)); // comms reg 0-7
	1671	machine().device(":maincpu")->memory().space(AS_PROGRAM)->install_legacy_readwrite_handler(0xa15130, 0xa1513f, FUNC(_32x_pwm_r), FUNC(_32x_68k_pwm_w));
1702	1672
1703		machine().device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_read_handler(0x0a130ec, 0x0a130ef, FUNC(_32x_68k_MARS_r)); // system ID
	1673	machine().device(":maincpu")->memory().space(AS_PROGRAM)->install_legacy_read_handler(0x0a130ec, 0x0a130ef, FUNC(_32x_68k_MARS_r)); // system ID
1704	1674
1705	1675
1706		/* Interrupts are masked / disabled at first */
1707		sh2_master_vint_enable = sh2_slave_vint_enable = 0;
1708		sh2_master_hint_enable = sh2_slave_hint_enable = 0;
1709		sh2_master_cmdint_enable = sh2_slave_cmdint_enable = 0;
1710		sh2_master_pwmint_enable = sh2_slave_pwmint_enable = 0;
1711		sh2_master_vint_pending = sh2_slave_vint_pending = 0;
1712	1676
1713		// start in a reset state
1714		sh2_are_running = 0;
1715
1716		_32x_a1518a_reg = 0x00; // inital value
1717		_32x_68k_a15104_reg = 0x00;
1718
1719		_32x_autofill_length = 0;
1720		_32x_autofill_address = 0;
1721		_32x_autofill_data = 0;
1722		_32x_screenshift = 0;
1723		_32x_videopriority = 0; // MD priority
1724		_32x_displaymode = 0;
1725		_32x_240mode = 0;
1726
1727	1677	// checking if these help brutal, they don't.
1728		sh2drc_set_options(machine().device("32x_master_sh2"), SH2DRC_COMPATIBLE_OPTIONS);
1729		sh2drc_set_options(machine().device("32x_slave_sh2"), SH2DRC_COMPATIBLE_OPTIONS);
	1678	sh2drc_set_options(machine().device(_32X_MASTER_TAG), SH2DRC_COMPATIBLE_OPTIONS);
	1679	sh2drc_set_options(machine().device(_32X_SLAVE_TAG), SH2DRC_COMPATIBLE_OPTIONS);
1730	1680
1731	1681	DRIVER_INIT_CALL(megadriv);
1732	1682	}
r17424	r17425
1783	1733	return 1;
1784	1734	}
1785	1735
1786		MACHINE_RESET( _32x )
1787		{
1788		current_fifo_block = fifo_block_a;
1789		current_fifo_readblock = fifo_block_b;
1790		current_fifo_write_pos = 0;
1791		current_fifo_read_pos = 0;
1792		fifo_block_a_full = 0;
1793		fifo_block_b_full = 0;
1794	1736
1795		_32x_hcount_compare_val = -1;
1796		}
1797
1798	1737	static UINT32 _32x_linerender[320+258]; // tmp buffer (bigger than it needs to be to simplify RLE decode)
1799	1738
1800	1739	UINT32* _32x_render_videobuffer_to_screenbuffer_helper(running_machine &machine, int scanline)
r17424	r17425
1906	1845
1907	1846	return _32x_linerender;
1908	1847	}
	1848
	1849	static const sh2_cpu_core sh2_conf_master = { 0, NULL, _32x_fifo_available_callback };
	1850	static const sh2_cpu_core sh2_conf_slave  = { 1, NULL, _32x_fifo_available_callback };
	1851
	1852	#if 0
	1853	// for now we just use the regular loading because we have 2 different BIOS roms, and you can't use -bios within a device for obvious reasons
	1854	ROM_START( 32x )
	1855	ROM_REGION( 0x400000, "32x_master_sh2", 0 )
	1856	ROM_REGION( 0x400000, "32x_slave_sh2", 0 )
	1857	ROM_END
	1858
	1859	const rom_entry *sega_32x_device::device_rom_region() const
	1860	{
	1861	return ROM_NAME( 32x );
	1862	}
	1863
	1864	void sega_32x_device::device_config_complete()
	1865	{
	1866	m_shortname = "32x";
	1867	}
	1868	#endif
	1869
	1870
	1871	// brutal needs high levels of interleave or the background animations don't work
	1872	// and some stages simply freeze the game, the is not good for performance however.
	1873	//
	1874	// some games appear to dislike 'perfect' levels of interleave, probably due to
	1875	// non-emulated cache, ram waitstates and other issues?
	1876	#define _32X_INTERLEAVE_LEVEL \
	1877	MCFG_QUANTUM_TIME(attotime::from_hz(1800000)) \
	1878
	1879
	1880	static MACHINE_CONFIG_FRAGMENT( _32x_ntsc )
	1881
	1882	#ifndef _32X_SWAP_MASTER_SLAVE_HACK
	1883	MCFG_CPU_ADD("32x_master_sh2", SH2, (MASTER_CLOCK_NTSC*3)/7 )
	1884	MCFG_CPU_PROGRAM_MAP(sh2_main_map)
	1885	MCFG_CPU_CONFIG(sh2_conf_master)
	1886	#endif
	1887
	1888	MCFG_CPU_ADD("32x_slave_sh2", SH2, (MASTER_CLOCK_NTSC*3)/7 )
	1889	MCFG_CPU_PROGRAM_MAP(sh2_slave_map)
	1890	MCFG_CPU_CONFIG(sh2_conf_slave)
	1891
	1892	#ifdef _32X_SWAP_MASTER_SLAVE_HACK
	1893	MCFG_CPU_ADD("32x_master_sh2", SH2, (MASTER_CLOCK_NTSC*3)/7 )
	1894	MCFG_CPU_PROGRAM_MAP(sh2_main_map)
	1895	MCFG_CPU_CONFIG(sh2_conf_master)
	1896	#endif
	1897
	1898	MCFG_DAC_ADD("lch_pwm")
	1899	MCFG_SOUND_ROUTE(ALL_OUTPUTS, ":lspeaker", 0.40)
	1900
	1901	MCFG_DAC_ADD("rch_pwm")
	1902	MCFG_SOUND_ROUTE(ALL_OUTPUTS, ":rspeaker", 0.40)
	1903
	1904	_32X_INTERLEAVE_LEVEL
	1905	MACHINE_CONFIG_END
	1906
	1907	static MACHINE_CONFIG_FRAGMENT( _32x_pal )
	1908
	1909	#ifndef _32X_SWAP_MASTER_SLAVE_HACK
	1910	MCFG_CPU_ADD("32x_master_sh2", SH2, (MASTER_CLOCK_PAL*3)/7 )
	1911	MCFG_CPU_PROGRAM_MAP(sh2_main_map)
	1912	MCFG_CPU_CONFIG(sh2_conf_master)
	1913	#endif
	1914
	1915	MCFG_CPU_ADD("32x_slave_sh2", SH2, (MASTER_CLOCK_PAL*3)/7 )
	1916	MCFG_CPU_PROGRAM_MAP(sh2_slave_map)
	1917	MCFG_CPU_CONFIG(sh2_conf_slave)
	1918
	1919	#ifdef _32X_SWAP_MASTER_SLAVE_HACK
	1920	MCFG_CPU_ADD("32x_master_sh2", SH2, (MASTER_CLOCK_PAL*3)/7 )
	1921	MCFG_CPU_PROGRAM_MAP(sh2_main_map)
	1922	MCFG_CPU_CONFIG(sh2_conf_master)
	1923	#endif
	1924
	1925	MCFG_DAC_ADD("lch_pwm")
	1926	MCFG_SOUND_ROUTE(ALL_OUTPUTS, ":lspeaker", 0.40)
	1927
	1928	MCFG_DAC_ADD("rch_pwm")
	1929	MCFG_SOUND_ROUTE(ALL_OUTPUTS, ":rspeaker", 0.40)
	1930
	1931	_32X_INTERLEAVE_LEVEL
	1932	MACHINE_CONFIG_END
	1933
	1934
	1935
	1936	machine_config_constructor sega_32x_device::device_mconfig_additions() const
	1937	{
	1938	return MACHINE_CONFIG_NAME( _32x_ntsc );
	1939	}
	1940
	1941	machine_config_constructor sega_32x_pal_device::device_mconfig_additions() const
	1942	{
	1943	return MACHINE_CONFIG_NAME( _32x_pal );
	1944	}
	1945
	1946
	1947	void sega_32x_device::device_start()
	1948	{
	1949	m_32x_pwm_timer = machine().scheduler().timer_alloc(FUNC(_32x_pwm_callback), (void*)this);
	1950	m_32x_pwm_timer->adjust(attotime::never);
	1951
	1952	_32x_dram0 = auto_alloc_array(machine(), UINT16, 0x40000/2);
	1953	_32x_dram1 = auto_alloc_array(machine(), UINT16, 0x40000/2);
	1954
	1955	memset(_32x_dram0, 0x00, 0x40000);
	1956	memset(_32x_dram1, 0x00, 0x40000);
	1957
	1958	_32x_palette_lookup = auto_alloc_array(machine(), UINT16, 0x200/2);
	1959	_32x_palette = auto_alloc_array(machine(), UINT16, 0x200/2);
	1960
	1961	memset(_32x_palette_lookup, 0x00, 0x200);
	1962	memset(_32x_palette, 0x00, 0x200);
	1963
	1964	_32x_display_dram = _32x_dram0;
	1965	_32x_access_dram = _32x_dram1;
	1966	}
	1967
	1968	void sega_32x_device::device_reset()
	1969	{
	1970	/* Interrupts are masked / disabled at first */
	1971	sh2_master_vint_enable = sh2_slave_vint_enable = 0;
	1972	sh2_master_hint_enable = sh2_slave_hint_enable = 0;
	1973	sh2_master_cmdint_enable = sh2_slave_cmdint_enable = 0;
	1974	sh2_master_pwmint_enable = sh2_slave_pwmint_enable = 0;
	1975	sh2_master_vint_pending = sh2_slave_vint_pending = 0;
	1976
	1977	// start in a reset state
	1978	sh2_are_running = 0;
	1979
	1980	_32x_a1518a_reg = 0x00; // inital value
	1981	_32x_68k_a15104_reg = 0x00;
	1982
	1983	_32x_autofill_length = 0;
	1984	_32x_autofill_address = 0;
	1985	_32x_autofill_data = 0;
	1986	_32x_screenshift = 0;
	1987	_32x_videopriority = 0; // MD priority
	1988	_32x_displaymode = 0;
	1989	_32x_240mode = 0;
	1990
	1991
	1992	current_fifo_block = fifo_block_a;
	1993	current_fifo_readblock = fifo_block_b;
	1994	current_fifo_write_pos = 0;
	1995	current_fifo_read_pos = 0;
	1996	fifo_block_a_full = 0;
	1997	fifo_block_b_full = 0;
	1998
	1999	_32x_hcount_compare_val = -1;
	2000
	2001	// install these now, otherwise we'll get the following (incorrect) warnings on startup..
	2002	//   SH-2 device ':sega32x:32x_slave_sh2': program space memory map entry 0-3FFF references non-existant region ':slave'
	2003	//   SH-2 device ':sega32x:32x_master_sh2': program space memory map entry 0-3FFF references non-existant region ':master'
	2004	UINT8* masterbios = (UINT8*)machine().root_device().memregion(":master")->base();
	2005	UINT8* slavebios = (UINT8*)machine().root_device().memregion(":slave")->base();
	2006	membank("masterbios")->configure_entries(0, 1, masterbios, 0x4000);
	2007	membank("slavebios")->configure_entries(0, 1, slavebios, 0x4000);
	2008	membank("masterbios")->set_entry(0);
	2009	membank("slavebios")->set_entry(0);
	2010	}
	2011
	2012

trunk/src/mame/machine/mega32x.h

r0	r17425
	1	/* 32X */
	2
	3
	4	// Fifa96 needs the CPUs swapped for the gameplay to enter due to some race conditions
	5	// when using the DRC core.  Needs further investigation, the non-DRC core works either
	6	// way
	7	#define _32X_SWAP_MASTER_SLAVE_HACK
	8
	9
	10	#include "sound/dac.h"
	11
	12	#define _32X_MASTER_TAG (":sega32x:32x_master_sh2")
	13	#define _32X_SLAVE_TAG (":sega32x:32x_slave_sh2")
	14
	15
	16	class sega_32x_device : public device_t
	17	{
	18	public:
	19	sega_32x_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock, device_type type);
	20
	21	required_device<dac_device> m_lch_pwm;
	22	required_device<dac_device> m_rch_pwm;
	23
	24	DECLARE_READ32_MEMBER( _32x_sh2_master_4000_common_4002_r );
	25	DECLARE_READ32_MEMBER( _32x_sh2_slave_4000_common_4002_r );
	26	DECLARE_READ32_MEMBER( _32x_sh2_common_4004_common_4006_r );
	27	DECLARE_WRITE32_MEMBER( _32x_sh2_master_4000_common_4002_w );
	28	DECLARE_WRITE32_MEMBER( _32x_sh2_slave_4000_common_4002_w );
	29	DECLARE_WRITE32_MEMBER( _32x_sh2_common_4004_common_4006_w );
	30	DECLARE_WRITE32_MEMBER( _32x_sh2_master_4014_master_4016_w );
	31	DECLARE_WRITE32_MEMBER( _32x_sh2_master_4018_master_401a_w );
	32	DECLARE_WRITE32_MEMBER( _32x_sh2_master_401c_master_401e_w );
	33	DECLARE_WRITE32_MEMBER( _32x_sh2_slave_4014_slave_4016_w );
	34	DECLARE_WRITE32_MEMBER( _32x_sh2_slave_4018_slave_401a_w );
	35	DECLARE_WRITE32_MEMBER( _32x_sh2_slave_401c_slave_401e_w );
	36
	37
	38	emu_timer *m_32x_pwm_timer;
	39	protected:
	40	virtual void device_start();
	41	virtual void device_reset();
	42
	43	// optional information overrides
	44	//   virtual const rom_entry *device_rom_region() const;
	45	virtual machine_config_constructor device_mconfig_additions() const;
	46	private:
	47	//   virtual void device_config_complete();
	48	};
	49
	50
	51	class sega_32x_ntsc_device : public sega_32x_device
	52	{
	53	public:
	54	sega_32x_ntsc_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	55
	56	};
	57
	58	class sega_32x_pal_device : public sega_32x_device
	59	{
	60	public:
	61	sega_32x_pal_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	62	protected:
	63	virtual machine_config_constructor device_mconfig_additions() const;
	64	};
	65
	66
	67	extern const device_type SEGA_32X_NTSC;
	68	extern const device_type SEGA_32X_PAL;

trunk/src/mame/machine/megadriv.c

r17424	r17425
1032	1032	MACHINE_RESET_CALL( segacd );
1033	1033	}
1034	1034
1035
1036		if(_32x_is_connected)
1037		{
1038		MACHINE_RESET_CALL(_32x);
1039		}
1040	1035	}
1041	1036
1042	1037	void megadriv_stop_scanline_timer(running_machine &machine)
r17424	r17425
1237	1232	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "rspeaker",0.25) /* 3.58 MHz */
1238	1233	MACHINE_CONFIG_END
1239	1234
1240		MACHINE_CONFIG_START( megadpal, driver_device )
	1235	MACHINE_CONFIG_START( megadpal, md_cons_state )
1241	1236	MCFG_FRAGMENT_ADD(md_pal)
1242	1237	MACHINE_CONFIG_END
1243	1238
1244	1239
1245	1240
1246		static const sh2_cpu_core sh2_conf_master = { 0, NULL, _32x_fifo_available_callback };
1247		static const sh2_cpu_core sh2_conf_slave  = { 1, NULL, _32x_fifo_available_callback };
1248	1241
1249	1242	MACHINE_CONFIG_DERIVED( genesis_32x, megadriv )
1250	1243
1251		#ifndef _32X_SWAP_MASTER_SLAVE_HACK
1252		MCFG_CPU_ADD("32x_master_sh2", SH2, (MASTER_CLOCK_NTSC*3)/7 )
1253		MCFG_CPU_PROGRAM_MAP(sh2_main_map)
1254		MCFG_CPU_CONFIG(sh2_conf_master)
1255		#endif
	1244	MCFG_DEVICE_ADD("sega32x", SEGA_32X_NTSC, 0)
1256	1245
1257		MCFG_CPU_ADD("32x_slave_sh2", SH2, (MASTER_CLOCK_NTSC*3)/7 )
1258		MCFG_CPU_PROGRAM_MAP(sh2_slave_map)
1259		MCFG_CPU_CONFIG(sh2_conf_slave)
1260
1261		#ifdef _32X_SWAP_MASTER_SLAVE_HACK
1262		MCFG_CPU_ADD("32x_master_sh2", SH2, (MASTER_CLOCK_NTSC*3)/7 )
1263		MCFG_CPU_PROGRAM_MAP(sh2_main_map)
1264		MCFG_CPU_CONFIG(sh2_conf_master)
1265		#endif
1266
1267		// brutal needs at least 30000 or the backgrounds don't animate properly / lock up, and the game
1268		// freezes.  Some stage seem to need as high as 80000 ?   this *KILLS* performance
1269		//
1270		// boosting the interleave here actually makes Kolibri run incorrectly however, that
1271		// one works best just boosting the interleave on communications?!
1272		MCFG_QUANTUM_TIME(attotime::from_hz(1800000))
1273
1274	1246	// we need to remove and re-add the sound system because the balance is different
1275	1247	// due to MAME / MESS having severe issues if the dac output is > 0.40? (sound is corrupted even if DAC is slient?!)
1276	1248	MCFG_DEVICE_REMOVE("ymsnd")
1277	1249	MCFG_DEVICE_REMOVE("snsnd")
1278	1250
1279
1280	1251	MCFG_SOUND_ADD("ymsnd", YM2612, MASTER_CLOCK_NTSC/7)
1281	1252	MCFG_SOUND_ROUTE(0, "lspeaker", (0.50)/2)
1282	1253	MCFG_SOUND_ROUTE(1, "rspeaker", (0.50)/2)
r17424	r17425
1286	1257	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "lspeaker", (0.25)/2)
1287	1258	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "rspeaker", (0.25)/2)
1288	1259
1289		MCFG_DAC_ADD("lch_pwm")
1290		MCFG_SOUND_ROUTE(ALL_OUTPUTS, "lspeaker", 0.40)
1291
1292		MCFG_DAC_ADD("rch_pwm")
1293		MCFG_SOUND_ROUTE(ALL_OUTPUTS, "rspeaker", 0.40)
1294	1260	MACHINE_CONFIG_END
1295	1261
1296	1262
1297	1263	MACHINE_CONFIG_DERIVED( genesis_32x_pal, megadpal )
1298	1264
1299		#ifndef _32X_SWAP_MASTER_SLAVE_HACK
1300		MCFG_CPU_ADD("32x_master_sh2", SH2, (MASTER_CLOCK_PAL*3)/7 )
1301		MCFG_CPU_PROGRAM_MAP(sh2_main_map)
1302		MCFG_CPU_CONFIG(sh2_conf_master)
1303		#endif
	1265	MCFG_DEVICE_ADD("sega32x", SEGA_32X_PAL, 0)
1304	1266
1305		MCFG_CPU_ADD("32x_slave_sh2", SH2, (MASTER_CLOCK_PAL*3)/7 )
1306		MCFG_CPU_PROGRAM_MAP(sh2_slave_map)
1307		MCFG_CPU_CONFIG(sh2_conf_slave)
1308
1309		#ifdef _32X_SWAP_MASTER_SLAVE_HACK
1310		MCFG_CPU_ADD("32x_master_sh2", SH2, (MASTER_CLOCK_PAL*3)/7 )
1311		MCFG_CPU_PROGRAM_MAP(sh2_main_map)
1312		MCFG_CPU_CONFIG(sh2_conf_master)
1313		#endif
1314
1315		// brutal needs at least 30000 or the backgrounds don't animate properly / lock up, and the game
1316		// freezes.  Some stage seem to need as high as 80000 ?   this *KILLS* performance
1317		//
1318		// boosting the interleave here actually makes Kolibri run incorrectly however, that
1319		// one works best just boosting the interleave on communications?!
1320		MCFG_QUANTUM_TIME(attotime::from_hz(1800000))
1321
1322	1267	// we need to remove and re-add the sound system because the balance is different
1323	1268	// due to MAME / MESS having severe issues if the dac output is > 0.40? (sound is corrupted even if DAC is slient?!)
1324	1269	MCFG_DEVICE_REMOVE("ymsnd")
1325	1270	MCFG_DEVICE_REMOVE("snsnd")
1326	1271
1327
1328		MCFG_SOUND_ADD("ymsnd", YM2612, MASTER_CLOCK_PAL/7)
	1272	MCFG_SOUND_ADD("ymsnd", YM2612, MASTER_CLOCK_NTSC/7)
1329	1273	MCFG_SOUND_ROUTE(0, "lspeaker", (0.50)/2)
1330	1274	MCFG_SOUND_ROUTE(1, "rspeaker", (0.50)/2)
1331	1275
1332	1276	/* sound hardware */
1333		MCFG_SOUND_ADD("snsnd", SEGAPSG, MASTER_CLOCK_PAL/15)
	1277	MCFG_SOUND_ADD("snsnd", SEGAPSG, MASTER_CLOCK_NTSC/15)
1334	1278	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "lspeaker", (0.25)/2)
1335	1279	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "rspeaker", (0.25)/2)
1336	1280
1337		MCFG_DAC_ADD("lch_pwm")
1338		MCFG_SOUND_ROUTE(ALL_OUTPUTS, "lspeaker", 0.40)
1339
1340		MCFG_DAC_ADD("rch_pwm")
1341		MCFG_SOUND_ROUTE(ALL_OUTPUTS, "rspeaker", 0.40)
1342	1281	MACHINE_CONFIG_END
1343	1282
1344	1283
r17424	r17425
1410	1349	MCFG_CDROM_ADD( "cdrom", scd_cdrom)
1411	1350	MCFG_SOFTWARE_LIST_ADD("cd_list","segacd")
1412	1351
1413		MCFG_QUANTUM_PERFECT_CPU("32x_master_sh2")
	1352	//MCFG_QUANTUM_PERFECT_CPU("32x_master_sh2")
1414	1353	MACHINE_CONFIG_END
1415	1354
1416	1355
r17424	r17425
1434	1373	}
1435	1374
1436	1375	/* Look to see if this system has the 32x Master SH2 */
1437		_32x_master_cpu = machine.device<cpu_device>("32x_master_sh2");
	1376	_32x_master_cpu = machine.device<cpu_device>(_32X_MASTER_TAG);
1438	1377	if (_32x_master_cpu != NULL)
1439	1378	{
1440	1379	printf("32x MASTER SH2 cpu found '%s'\n", _32x_master_cpu->tag() );
1441	1380	}
1442	1381
1443	1382	/* Look to see if this system has the 32x Slave SH2 */
1444		_32x_slave_cpu = machine.device<cpu_device>("32x_slave_sh2");
	1383	_32x_slave_cpu = machine.device<cpu_device>(_32X_SLAVE_TAG);
1445	1384	if (_32x_slave_cpu != NULL)
1446	1385	{
1447	1386	printf("32x SLAVE SH2 cpu found '%s'\n", _32x_slave_cpu->tag() );
r17424	r17425
1456	1395	_32x_is_connected = 0;
1457	1396	}
1458	1397
1459		if(_32x_is_connected)
1460		{
1461		_32x_pwm_timer = machine.scheduler().timer_alloc(FUNC(_32x_pwm_callback));
1462		_32x_pwm_timer->adjust(attotime::never);
1463		}
1464	1398
	1399
1465	1400	sega_cd_connected = 0;
1466	1401	segacd_wordram_mapped = 0;
1467	1402	_segacd_68k_cpu = machine.device<cpu_device>("segacd_68k");

trunk/src/mame/includes/megadriv.h

r17424	r17425
15	15	#include "cpu/ssp1601/ssp1601.h"
16	16
17	17	#include "machine/megavdp.h"
	18	#include "machine/mega32x.h"
18	19	#include "video/315_5124.h"
19	20
20	21	#define MASTER_CLOCK_NTSC 53693175
r17424	r17425
420	421
421	422	};
422	423
423		// Fifa96 needs the CPUs swapped for the gameplay to enter due to some race conditions
424		// when using the DRC core.  Needs further investigation, the non-DRC core works either
425		// way
426		#define _32X_SWAP_MASTER_SLAVE_HACK
427	424
	425
428	426	extern int _32x_is_connected;
429	427	extern cpu_device *_32x_master_cpu;
430	428	extern cpu_device *_32x_slave_cpu;
431	429
432	430	// called from out main scanline timers...
433	431
434		extern int _32x_fifo_available_callback(device_t *device, UINT32 src, UINT32 dst, UINT32 data, int size);
435		extern MACHINE_RESET( _32x );
436		ADDRESS_MAP_EXTERN( sh2_main_map, driver_device );
437		ADDRESS_MAP_EXTERN( sh2_slave_map, driver_device );
438		extern emu_timer *_32x_pwm_timer;
439		extern TIMER_CALLBACK( _32x_pwm_callback );
440	432
	433
441	434	extern int megadrive_vblank_flag;
442	435	extern int genesis_scanline_counter;
443	436

trunk/src/mess/drivers/megadriv.c

r17424	r17425
487	487	/* temp, rom should only be visible here when one of the regs is set, tempo needs it */ \
488	488	/* ROM_CART_LOAD("cart", 0x000000, 0x400000, ROM_NOMIRROR) */ \
489	489	ROM_COPY( "32x_68k_bios", 0x0, 0x0, 0x100) \
490		ROM_REGION( 0x400000, "32x_master_sh2", 0 ) /* SH2 Code */ \
	490	ROM_REGION32_BE( 0x400000, "master", 0 ) /* SH2 Code */ \
491	491	ROM_SYSTEM_BIOS( 0, "retail", "Mars Version 1.0 (retail)" ) \
492	492	ROMX_LOAD( "32x_m_bios.bin", 0x000000,  0x000800, CRC(dd9c46b8) SHA1(1e5b0b2441a4979b6966d942b20cc76c413b8c5e), ROM_BIOS(1) ) \
493	493	ROM_SYSTEM_BIOS( 1, "sdk", "Mars Version 1.0 (early sdk)" ) \
494	494	ROMX_LOAD( "32x_m_bios_sdk.bin", 0x000000,  0x000800, BAD_DUMP CRC(c7102c53) SHA1(ed73a47f186b373b8eff765f84ef26c3d9ef6cb0), ROM_BIOS(2) ) \
495		ROM_REGION( 0x400000, "32x_slave_sh2", 0 ) /* SH2 Code */ \
	495	ROM_REGION32_BE( 0x400000, "slave", 0 ) /* SH2 Code */ \
496	496	ROM_LOAD( "32x_s_bios.bin", 0x000000,  0x000400, CRC(bfda1fe5) SHA1(4103668c1bbd66c5e24558e73d4f3f92061a109a) ) \
497	497
498	498
r17424	r17425
638	638	ROM_REGION16_BE( 0x400000, "32x_68k_bios", 0 ) /* 68000 Code */
639	639	ROM_LOAD( "32x_g_bios.bin", 0x000000,  0x000100, CRC(5c12eae8) SHA1(dbebd76a448447cb6e524ac3cb0fd19fc065d944) )
640	640
641		ROM_REGION( 0x400000, "32x_master_sh2", 0 ) /* SH2 Code */
	641	ROM_REGION32_BE( 0x400000, "32x_master_sh2", 0 ) /* SH2 Code */
642	642	ROM_LOAD( "32x_m_bios.bin", 0x000000,  0x000800, CRC(dd9c46b8) SHA1(1e5b0b2441a4979b6966d942b20cc76c413b8c5e) )
643	643
644		ROM_REGION( 0x400000, "32x_slave_sh2", 0 ) /* SH2 Code */
	644	ROM_REGION32_BE( 0x400000, "32x_slave_sh2", 0 ) /* SH2 Code */
645	645	ROM_LOAD( "32x_s_bios.bin", 0x000000,  0x000400, CRC(bfda1fe5) SHA1(4103668c1bbd66c5e24558e73d4f3f92061a109a) )
646	646	ROM_END
647	647

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