MAME SVN History

199869 Revisions

r16922 Sunday 22nd July, 2012 at 11:23:53 UTC by Couriersud
Implemented a generic implementation to model discrete net lists. [Couriersud] - Based on timeslot modelling, the implementation models gate delays in logic chips. - Design ready to be split into a generic and a MAME implementation part. - Design prepared to merge in discrete components from discrete.* - Supports code based as well as external net list parsing. Ultimately, net lists and discrete emulation should share one code base. The class design was set up to accomplish this. There is no point in having multiple 555, 7474 implementations around. Most of the code will be moved to lib/netlist going forward to allow usage in other projects.

r16922 Sunday 22nd July, 2012 at 11:23:53 UTC by Couriersud

Implemented a generic implementation to model discrete net lists. [Couriersud]

- Based on timeslot modelling, the implementation models gate delays in logic chips.
- Design ready to be split into a generic and a MAME implementation part.
- Design prepared to merge in discrete components from discrete.*
- Supports code based as well as external net list parsing.

Ultimately, net lists and discrete emulation should share one code base. The class design was set up to accomplish this. There is no point in having multiple 555, 7474 implementations around.
Most of the code will be moved to lib/netlist going forward to allow usage in other projects.

[src/emu]	emu.mak
[src/emu/machine]	net_lib.c* net_lib.h* netlist.c* netlist.h*

199869 Revisions