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r45175 Tuesday 23rd February, 2016 at 18:45:12 UTC by Jonathan Gevaryahu
Xerox NoteTaker: Finished IOCPU memory map documentation. Hooked up the two UARTS. Begin hookup of the screen/CRTC. Fixed an issue with writes to ROM-mapped areas shadowing to RAM. Added 960KHz xtal for the keyboard UART. [Lord Nightmare]

AY-3-1015 UART: Fixed two swapped pin functions. [Lord Nightmare]
[src/devices/machine]ay31015.cpp ay31015.h
[src/emu/drivers]xtal.h
[src/mame/drivers]notetaker.cpp

trunk/src/devices/machine/ay31015.cpp
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4040-- Pin 21 - XR - External Reset - resets all registers to initial state except for the control register
4141-- Pin 35 - NP - No Parity - "1" will kill any parity processing
4242-- Pin 36 - TSB - Number of Stop Bits - "0" = 1 stop bit; "1" = 2 stop bits. If "1", and 5 bits per character, then we have 1.5 stop bits
43-- pin 37 - NB1
44-- pin 38 - NB2 - Number of bits per character = NB1 + (NB2 * 2) + 5
43-- pin 37 - NB2
44-- pin 38 - NB1 - Number of bits per character = NB1 + (NB2 * 2) + 5
4545-- pin 39 - EPS - Odd or Even Parity Select - "0" = Odd parity; "1" = Even parity. Has no effect if NP is high.
4646-- Pin 34 - CS - Control Strobe - Read NP, TSB, EPS, NB1, NB2 into the control register.
4747
trunk/src/devices/machine/ay31015.h
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2323   AY31015_CS = 34,          /*  CS   - Pin 34 - Control strobe */
2424   AY31015_NP = 35,          /*  NP   - Pin 35 - No parity */
2525   AY31015_TSB = 36,         /*  TSB  - Pin 36 - Number of stop bits */
26   AY31015_NB1 = 37,         /*  NB1  - Pin 37 - Number of bits #1 */
27   AY31015_NB2 = 38,         /*  NB2  - Pin 38 - Number of bits #2 */
26   AY31015_NB2 = 37,         /*  NB2  - Pin 37 - Number of bits #2 */
27   AY31015_NB1 = 38,         /*  NB1  - Pin 38 - Number of bits #1 */
2828   AY31015_EPS = 39          /*  EPS  - Pin 39 - Odd/Even parity select */
2929};
3030
trunk/src/emu/drivers/xtal.h
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239239   XTAL_512kHz         = 512000,       /* Toshiba TC8830F */
240240   XTAL_600kHz         = 600000,
241241   XTAL_640kHz         = 640000,       /* NEC UPD7759, Texas Instruments Speech Chips @ 8khz */
242   XTAL_960kHz         = 960000,       /* Xerox Notetaker Keyboard UART */
242243   XTAL_1_056MHz       = 1056000       /* OKI M6295 on Trio The Punch h/w */
243244};
244245
trunk/src/mame/drivers/notetaker.cpp
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4040* figure out the correct memory maps for the 256kB of shared ram, and what part of ram constitutes the framebuffer
4141* figure out how the emulation-cpu boots and where its 4k of local ram maps to
4242* Get smalltalk-78 loaded as a rom and forced into ram on startup, since no boot disks have survived (or if any survived, they are not dumped)
43* floppy controller wd1791
44  According to [3] and [5] the format is double density/MFM, 128 bytes per sector, 16 sectors per track, 1 or 2 sided, for 170K or 340K per disk.
45  According to the schematics, we're missing an 82s147 DISKSEP.PROM used as a data separator
46* crt5027 video controller; we're missing a PROM used to handle memory arbitration between the crtc and the rest of the system, but the equations are on the schematic
47* Harris 6402 serial/EIA UART
48* Harris 6402 keyboard UART
43* crt5027 video controller
44* Harris 6402 keyboard UART (within keyboard, next to MCU)
45* The harris 6402 UART is pin compatible with WD TR1865 and TR1602 UARTs, as well as the AY-3-1015A/D
4946* HLE for the missing i8748[5] MCU in the keyboard which reads the mouse quadratures and buttons and talks serially to the Keyboard UART
5047
5148WIP:
5249* pic8259 interrupt controller - this is attached as a device, but the interrupts are not hooked to it yet.
53* i/o cpu i/o area needs the memory map worked out per the schematics - mostly done
50* Harris 6402 serial/EIA UART
51* Harris 6402 keyboard UART (within notetaker)
52* floppy controller wd1791
53  According to [3] and [5] the format is double density/MFM, 128 bytes per sector, 16 sectors per track, 1 or 2 sided, for 170K or 340K per disk. Drive spins at 300RPM.
54  According to the schematics, we're missing an 82s147 DISKSEP.PROM used as a data separator
55* we're missing a dump of the 82s126 SETMEMRQ PROM used to handle memory arbitration between the crtc and the rest of the system, but the equations are on the schematic and I'm planning to regenerate the prom contents from that, see ROM_LOAD section
56 
57DONE:
58* i/o cpu i/o area needs the memory map worked out per the schematics - done
5459*/
5560
5661#include "cpu/i86/i86.h"
5762#include "machine/pic8259.h"
58//#include "video/tms9927.h"
63#include "machine/ay31015.h"
64#include "video/tms9927.h"
5965
6066class notetaker_state : public driver_device
6167{
6268public:
6369   notetaker_state(const machine_config &mconfig, device_type type, const char *tag) :
6470      driver_device(mconfig, type, tag) ,
65      m_maincpu(*this, "maincpu"),
66      m_pic(*this, "pic8259")//,
67      //m_vtac(*this, "crt5027")
71      m_iocpu(*this, "iocpu"),
72      m_iopic(*this, "iopic8259"),
73      m_kbduart(*this, "kbduart"),
74      m_eiauart(*this, "eiauart"),
75      m_crtc(*this, "crt5027")
6876   {
6977   }
7078// devices
71   required_device<cpu_device> m_maincpu;
72   required_device<pic8259_device> m_pic;
73   //required_device<crt5027_device> m_vtac;
79   required_device<cpu_device> m_iocpu;
80   required_device<pic8259_device> m_iopic;
81   required_device<ay31015_device> m_kbduart;
82   required_device<ay31015_device> m_eiauart;
83   required_device<crt5027_device> m_crtc;
7484
7585//declarations
86   // screen
87   UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
88   // basic io
7689   DECLARE_WRITE16_MEMBER(IPConReg_w);
77   DECLARE_READ16_MEMBER(maincpu_r);
78   DECLARE_WRITE16_MEMBER(maincpu_w);
90   
91   // uarts
92   DECLARE_READ16_MEMBER(ReadKeyData_r);
93   DECLARE_READ16_MEMBER(ReadOPStatus_r);
94   DECLARE_WRITE16_MEMBER(LoadKeyData_w);
95   DECLARE_WRITE16_MEMBER(LoadKeyCtlReg_w);
96   DECLARE_WRITE16_MEMBER(KeyDataReset_w);
97   DECLARE_WRITE16_MEMBER(KeyChipReset_w);
98   DECLARE_READ16_MEMBER(ReadEIAData_r);
99   DECLARE_READ16_MEMBER(ReadEIAStatus_r);
100   DECLARE_WRITE16_MEMBER(LoadEIAData_w);
101   DECLARE_WRITE16_MEMBER(LoadEIACtlReg_w);
102   DECLARE_WRITE16_MEMBER(EIADataReset_w);
103   DECLARE_WRITE16_MEMBER(EIAChipReset_w);
104   // mem map stuff
105   DECLARE_READ16_MEMBER(iocpu_r);
106   DECLARE_WRITE16_MEMBER(iocpu_w);
79107   DECLARE_DRIVER_INIT(notetakr);
80
81108//variables
82109   UINT8 m_BootSeqDone;
83110   UINT8 m_DisableROM;
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86113   virtual void machine_reset() override;
87114};
88115
116UINT32 notetaker_state::screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
117{
118   // have to figure out what resolution we're drawing to here and draw appropriately to screen
119   return 0;
120}
121
89122WRITE16_MEMBER(notetaker_state::IPConReg_w)
90123{
91124   m_BootSeqDone = (data&0x80)?1:0;
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99132   popmessage("LEDS: CR1: %d, CR2: %d, CR3: %d, CR4: %d", (data&0x04)>>2, (data&0x08)>>3, (data&0x02)>>1, (data&0x01)); // cr1 and 2 are in the reverse order as expected, according to the schematic
100133}
101134
102READ16_MEMBER(notetaker_state::maincpu_r)
135/* handlers for the two system hd6402s (ay-5-1013 equivalent) */
136/* * Keyboard hd6402 */
137READ16_MEMBER( notetaker_state::ReadKeyData_r )
103138{
104   UINT16 *rom = (UINT16 *)(memregion("maincpu")->base());
139   return 0xFF00||m_kbduart->get_received_data();
140}
141
142READ16_MEMBER( notetaker_state::ReadOPStatus_r )
143{
144   UINT16 data = 0xFFF0;
145   // TODO: FIX HACK: set FIFOInRDY and FIFOOutRdy both to 1
146   data |= 0x0C;
147   /*
148   data |= (m_FIFOOutRdy) ? 0x08 : 0;
149   data |= (m_FIFOInRdy) ? 0x04 : 0;
150   */
151   // note /SWE is permanently enabled, so we don't enable it here for HD6402 reading
152   data |= m_kbduart->get_output_pin(AY31015_DAV ) ? 0x02 : 0; // DR - pin 19
153   data |= m_kbduart->get_output_pin(AY31015_TBMT) ? 0x01 : 0; // TBRE - pin 22
154   return data;
155}
156
157WRITE16_MEMBER( notetaker_state::LoadKeyData_w )
158{
159   m_kbduart->set_transmit_data(data&0xFF);
160}
161
162WRITE16_MEMBER( notetaker_state::LoadKeyCtlReg_w )
163{
164   m_kbduart->set_input_pin(AY31015_CS, 0);
165   m_kbduart->set_input_pin(AY31015_NP,  BIT(data, 4)); // PI - pin 35
166   m_kbduart->set_input_pin(AY31015_TSB, BIT(data, 3)); // SBS - pin 36
167   m_kbduart->set_input_pin(AY31015_NB2, BIT(data, 2)); // CLS2 - pin 37
168   m_kbduart->set_input_pin(AY31015_NB1, BIT(data, 1)); // CLS1 - pin 38
169   m_kbduart->set_input_pin(AY31015_EPS, BIT(data, 0)); // EPE - pin 39
170   m_kbduart->set_input_pin(AY31015_CS, 1);
171}
172
173WRITE16_MEMBER( notetaker_state::KeyDataReset_w )
174{
175   m_kbduart->set_input_pin(AY31015_RDAV, 0); // DDR - pin 18
176   m_kbduart->set_input_pin(AY31015_RDAV, 1); // ''
177}
178
179WRITE16_MEMBER( notetaker_state::KeyChipReset_w )
180{
181   m_kbduart->set_input_pin(AY31015_XR, 0); // MR - pin 21
182   m_kbduart->set_input_pin(AY31015_XR, 1); // ''
183}
184
185/* EIA hd6402 */
186READ16_MEMBER( notetaker_state::ReadEIAData_r )
187{
188   return 0xFF00||m_eiauart->get_received_data();
189}
190
191READ16_MEMBER( notetaker_state::ReadEIAStatus_r )
192{
193   UINT16 data = 0xFFFC;
194   // note /SWE is permanently enabled, so we don't enable it here for HD6402 reading
195   data |= m_eiauart->get_output_pin(AY31015_DAV ) ? 0x02 : 0; // DR - pin 19
196   data |= m_eiauart->get_output_pin(AY31015_TBMT) ? 0x01 : 0; // TBRE - pin 22
197   return data;
198}
199
200WRITE16_MEMBER( notetaker_state::LoadEIAData_w )
201{
202   m_eiauart->set_transmit_data(data&0xFF);
203}
204
205WRITE16_MEMBER( notetaker_state::LoadEIACtlReg_w )
206{
207   m_eiauart->set_input_pin(AY31015_CS, 0);
208   m_eiauart->set_input_pin(AY31015_NP,  BIT(data, 4)); // PI - pin 35
209   m_eiauart->set_input_pin(AY31015_TSB, BIT(data, 3)); // SBS - pin 36
210   m_eiauart->set_input_pin(AY31015_NB2, BIT(data, 2)); // CLS2 - pin 37
211   m_eiauart->set_input_pin(AY31015_NB1, BIT(data, 1)); // CLS1 - pin 38
212   m_eiauart->set_input_pin(AY31015_EPS, BIT(data, 0)); // EPE - pin 39
213   m_eiauart->set_input_pin(AY31015_CS, 1);
214}
215
216WRITE16_MEMBER( notetaker_state::EIADataReset_w )
217{
218   m_eiauart->set_input_pin(AY31015_RDAV, 0); // DDR - pin 18
219   m_eiauart->set_input_pin(AY31015_RDAV, 1); // ''
220}
221
222WRITE16_MEMBER( notetaker_state::EIAChipReset_w )
223{
224   m_eiauart->set_input_pin(AY31015_XR, 0); // MR - pin 21
225   m_eiauart->set_input_pin(AY31015_XR, 1); // ''
226}
227
228
229/* These next two members are memory map related for the iocpu */
230READ16_MEMBER(notetaker_state::iocpu_r)
231{
232   UINT16 *rom = (UINT16 *)(memregion("iocpu")->base());
105233   rom += 0x7f800;
106   UINT16 *ram = (UINT16 *)(memregion("ram")->base());
234   UINT16 *ram = (UINT16 *)(memregion("mainram")->base());
107235   if ( (m_BootSeqDone == 0) || ((m_DisableROM == 0) && ((offset&0x7F800) == 0)) )
108236   {
109237      rom += (offset&0x7FF);
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116244   }
117245}
118246
119WRITE16_MEMBER(notetaker_state::maincpu_w)
247WRITE16_MEMBER(notetaker_state::iocpu_w)
120248{
121   UINT16 *ram = (UINT16 *)(memregion("ram")->base());
249   UINT16 *ram = (UINT16 *)(memregion("mainram")->base());
250   if ( (m_BootSeqDone == 0) || ((m_DisableROM == 0) && ((offset&0x7F800) == 0)) )
251   {
252      logerror("attempt to write %04X to ROM-mapped area at %06X ignored\n", data, offset);
253      return;
254   }
122255   ram += offset;
123256   *ram = data;
124257}
125258
126259/* Address map comes from http://bitsavers.informatik.uni-stuttgart.de/pdf/xerox/notetaker/schematics/19790423_Notetaker_IO_Processor.pdf
127260a19 a18 a17 a16  a15 a14 a13 a12  a11 a10 a9  a8   a7  a6  a5  a4   a3  a2  a1  a0   BootSeqDone  DisableROM
128x   x   x   x    x   x   x   x    *   *   *   *    *   *   *   *    *   *   *   *    0            x          R   ROM
1290   0   0   0    0   0   0   0    *   *   *   *    *   *   *   *    *   *   *   *    1            0          R   ROM
130<  anything not all zeroes   >    *   *   *   *    *   *   *   *    *   *   *   *    1            0          RW  RAM
131x   x   x   x    ?   ?   *   *    *   *   *   *    *   *   *   *    *   *   *   *    x            x          W   RAM
132x   x   x   x    ?   ?   *   *    *   *   *   *    *   *   *   *    *   *   *   *    1            1          RW  RAM
261mode 0: (to get the boot vector and for maybe 1 or 2 instructions afterward)
262x   x   x   x    x   x   x   x    *   *   *   *    *   *   *   *    *   *   *   *    0            x          R   ROM (writes are open bus)
263mode 1: (during most of boot)
2640   0   0   0    0   0   0   0    *   *   *   *    *   *   *   *    *   *   *   *    1            0          R   ROM (writes are open bus)
2650   0   0   0    0   0   0   1    *   *   *   *    *   *   *   *    *   *   *   *    1            0          RW  RAM
2660   0   0   0    0   0   1   *    *   *   *   *    *   *   *   *    *   *   *   *    1            0          RW  RAM
267<anything not all zeroes>x   x    x   x   x   x    x   x   x   x    x   x   x   x    1            0          .   Open Bus
268mode 2: (during load of the emulatorcpu's firmware to the first 4k of shared ram which is on the emulatorcpu board)
2690   0   0   0    0   0   *   *    *   *   *   *    *   *   *   *    *   *   *   *    1            1          RW  RAM
270<anything not all zeroes>x   x    x   x   x   x    x   x   x   x    x   x   x   x    1            1          .   Open Bus
133271
134272More or less:
135BootSeqDone is 0, DisableROM is ignored, mem map is 0x00000-0xfffff reading is the 0x1000-long ROM, repeated every 0x1000 bytes. writing goes to RAM.
136BootSeqDone is 1, DisableROM is 0,       mem map is 0x00000-0x00fff reading is the 0x1000-long ROM, remainder of memory map goes to RAM or open bus. writing goes to RAM.
273BootSeqDone is 0, DisableROM is ignored, mem map is 0x00000-0xfffff reading is the 0x1000-long ROM, repeated every 0x1000 bytes. writing goes nowhere.
274BootSeqDone is 1, DisableROM is 0,       mem map is 0x00000-0x00fff reading is the 0x1000-long ROM, remainder of memory map goes to RAM or open bus. writing the ROM area goes nowhere, writing RAM goes to RAM.
137275BootSeqDone is 1, DisableROM is 1,       mem map is entirely RAM or open bus for both reading and writing.
138276*/
139static ADDRESS_MAP_START(notetaker_mem, AS_PROGRAM, 16, notetaker_state)
277static ADDRESS_MAP_START(notetaker_iocpu_mem, AS_PROGRAM, 16, notetaker_state)
140278   /*
141   AM_RANGE(0x00000, 0x00fff) AM_ROM AM_REGION("maincpu", 0xFF000) // rom is here if either BootSeqDone OR DisableROM are zero. the 1.5 source code implies writes here are ignored
279   AM_RANGE(0x00000, 0x00fff) AM_ROM AM_REGION("iocpu", 0xFF000) // rom is here if either BootSeqDone OR DisableROM are zero. the 1.5 source code implies writes here are ignored
142280   AM_RANGE(0x01000, 0x01fff) AM_RAM // 4k of ram, local to the io processor
143   AM_RANGE(0x02000, 0x3ffff) AM_RAM AM_BASE("sharedram") // 256k of ram (less 8k), shared between both processors
281   AM_RANGE(0x02000, 0x3ffff) AM_RAM AM_BASE("mainram") // 256k of ram (less 8k), shared between both processors
144282   // note 4000-8fff? is the framebuffer for the screen?
145283   AM_RANGE(0xff000, 0xfffff) AM_ROM // rom is only banked in here if bootseqdone is 0, so the reset vector is in the proper place
146284   */
147   AM_RANGE(0x00000, 0xfffff) AM_READWRITE(maincpu_r, maincpu_w) // bypass MAME's memory map system as we need finer grained control
285   AM_RANGE(0x00000, 0xfffff) AM_READWRITE(iocpu_r, iocpu_w) // bypass MAME's memory map system as we need finer grained control
148286ADDRESS_MAP_END
149287
150288/* io memory map comes from http://bitsavers.informatik.uni-stuttgart.de/pdf/xerox/notetaker/memos/19790605_Definition_of_8086_Ports.pdf
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161299x   x   x   x    0   x   x   x    x   x   x   0    0   1   0   x    1   1   0   .       W   KbdInt:KeyDataReset
162300x   x   x   x    0   x   x   x    x   x   x   0    0   1   0   x    1   1   1   .       W   KbdInt:KeyChipReset
163301x   x   x   x    0   x   x   x    x   x   x   0    0   1   1   x    x   x   x   .       W   FIFOReg
164x   x   x   x    0   x   x   x    x   x   x   0    1   0   0   x    x   x   x   .       .   Open Bus
165x   x   x   x    0   x   x   x    x   x   x   0    1   0   1   x    x   x   x   .       .   Open Bus
302x   x   x   x    0   x   x   x    x   x   x   0    1   0   0   x    x   x   x   .       .   Open Bus(originally ReadOpStatus)
303x   x   x   x    0   x   x   x    x   x   x   0    1   0   1   x    x   *   *   .       RW  SelPIA (debugger board 8255 PIA)[Open Bus on normal units]
166304x   x   x   x    0   x   x   x    x   x   x   0    1   1   0   x    x   x   x   .       W   FIFOBus
167305x   x   x   x    0   x   x   x    x   x   x   0    1   1   1   x    x   x   x   .       .   Open Bus
168x   x   x   x    0   x   x   x    x   x   x   1    0   0   0   x    x   x   x   .       RW  SelDiskReg
306x   x   x   x    0   x   x   x    x   x   x   1    0   0   0   x    x   x   x   .       RW  SelDiskReg
169307x   x   x   x    0   x   x   x    x   x   x   1    0   0   1   x    x   *   *   .       RW  SelDiskInt
170x   x   x   x    0   x   x   x    x   x   x   1    0   1   0   *    *   *   *   .       W   SelCrtInt   
308x   x   x   x    0   x   x   x    x   x   x   1    0   1   0   *    *   *   *   .       W   SelCrtInt
171309x   x   x   x    0   x   x   x    x   x   x   1    0   1   1   x    x   x   x   .       W   LoadDispAddr
172x   x   x   x    0   x   x   x    x   x   x   1    1   0   0   x    x   x   x   .       .   Open Bus
173x   x   x   x    0   x   x   x    x   x   x   0    1   0   1   x    0   0   0   .       R   SelEIA:ReadEIAStatus
174x   x   x   x    0   x   x   x    x   x   x   0    1   0   1   x    0   0   1   .       R   SelEIA:ReadEIAData
175x   x   x   x    0   x   x   x    x   x   x   0    1   0   1   x    0   1   0   .       .   SelEIA:Open Bus
176x   x   x   x    0   x   x   x    x   x   x   0    1   0   1   x    0   1   1   .       .   SelEIA:Open Bus
177x   x   x   x    0   x   x   x    x   x   x   0    1   0   1   x    1   0   0   .       W   SelEIA:LoadEIACtlReg
178x   x   x   x    0   x   x   x    x   x   x   0    1   0   1   x    1   0   1   .       W   SelEIA:LoadEIAData
179x   x   x   x    0   x   x   x    x   x   x   0    1   0   1   x    1   1   0   .       W   SelEIA:EIADataReset
180x   x   x   x    0   x   x   x    x   x   x   0    1   0   1   x    1   1   1   .       W   SelEIA:EIAChipReset
310x   x   x   x    0   x   x   x    x   x   x   1    1   0   0   x    x   x   x   .       .   Open Bus(originally ReadEIAStatus)
311x   x   x   x    0   x   x   x    x   x   x   1    1   0   1   x    0   0   0   .       R   SelEIA:ReadEIAStatus
312x   x   x   x    0   x   x   x    x   x   x   1    1   0   1   x    0   0   1   .       R   SelEIA:ReadEIAData
313x   x   x   x    0   x   x   x    x   x   x   1    1   0   1   x    0   1   0   .       .   SelEIA:Open Bus
314x   x   x   x    0   x   x   x    x   x   x   1    1   0   1   x    0   1   1   .       .   SelEIA:Open Bus
315x   x   x   x    0   x   x   x    x   x   x   1    1   0   1   x    1   0   0   .       W   SelEIA:LoadEIACtlReg
316x   x   x   x    0   x   x   x    x   x   x   1    1   0   1   x    1   0   1   .       W   SelEIA:LoadEIAData
317x   x   x   x    0   x   x   x    x   x   x   1    1   0   1   x    1   1   0   .       W   SelEIA:EIADataReset
318x   x   x   x    0   x   x   x    x   x   x   1    1   0   1   x    1   1   1   .       W   SelEIA:EIAChipReset
181319x   x   x   x    0   x   x   x    x   x   x   1    1   1   0   x    x   x   x   .       R   SelADCHi
182320x   x   x   x    0   x   x   x    x   x   x   1    1   1   1   x    x   x   x   .       W   CRTSwitch
183321*/
184static ADDRESS_MAP_START(notetaker_io, AS_IO, 16, notetaker_state)
322static ADDRESS_MAP_START(notetaker_iocpu_io, AS_IO, 16, notetaker_state)
185323   ADDRESS_MAP_UNMAP_HIGH
186   AM_RANGE(0x00, 0x03) AM_MIRROR(0x7E1C) AM_DEVREADWRITE8("pic8259", pic8259_device, read, write, 0x00ff)
187   AM_RANGE(0x20, 0x21) AM_MIRROR(0x7E1E) AM_WRITE(IPConReg_w) // processor (rom mapping, etc) control register
188   //AM_RANGE(0x42, 0x43) AM_MIRROR(0x7E10) AM_READ(ReadKeyData_r) // read keyboard data (high byte only) [from mcu?]
189   //AM_RANGE(0x44, 0x45) AM_MIRROR(0x7E10) AM_READ(ReadOPStatus_r) // read keyboard fifo state (high byte only) [from mcu?]
190   //AM_RANGE(0x48, 0x49) AM_MIRROR(0x7E10) AM_WRITE(LoadKeyCtlReg_w) // kbd uart control register
191   //AM_RANGE(0x4a, 0x4b) AM_MIRROR(0x7E10) AM_WRITE(LoadKeyData_w) // kbd uart data register
192   //AM_RANGE(0x4c, 0x4d) AM_MIRROR(0x7E10) AM_WRITE(KeyDataReset_w) // kbd uart ddr switch (data reset)
193   //AM_RANGE(0x4e, 0x4f) AM_MIRROR(0x7E10) AM_WRITE(KeyChipReset_w) // kbd uart reset
324   AM_RANGE(0x00, 0x03) AM_MIRROR(0x7E1C) AM_DEVREADWRITE8("iopic8259", pic8259_device, read, write, 0x00ff)
325   AM_RANGE(0x20, 0x21) AM_MIRROR(0x7E1E) AM_WRITE(IPConReg_w) // I/O processor (rom mapping, etc) control register
326   AM_RANGE(0x42, 0x43) AM_MIRROR(0x7E10) AM_READ(ReadKeyData_r) // read keyboard data
327   AM_RANGE(0x44, 0x45) AM_MIRROR(0x7E10) AM_READ(ReadOPStatus_r) // read keyboard fifo state
328   AM_RANGE(0x48, 0x49) AM_MIRROR(0x7E10) AM_WRITE(LoadKeyCtlReg_w) // kbd uart control register
329   AM_RANGE(0x4a, 0x4b) AM_MIRROR(0x7E10) AM_WRITE(LoadKeyData_w) // kbd uart data register
330   AM_RANGE(0x4c, 0x4d) AM_MIRROR(0x7E10) AM_WRITE(KeyDataReset_w) // kbd uart ddr switch (data reset)
331   AM_RANGE(0x4e, 0x4f) AM_MIRROR(0x7E10) AM_WRITE(KeyChipReset_w) // kbd uart reset
194332   //AM_RANGE(0x60, 0x61) AM_MIRROR(0x7E1E) AM_WRITE(FIFOReg_w) // DAC sample and hold and frequency setup
195   //AM_RANGE(0x100, 0x101) AM_WRITE I/O register (adc speed, crtc pixel clock enable, etc)
196   //AM_RANGE(0x140, 0x15f) AM_DEVREADWRITE("crt5027", crt5027_device, read, write)
333   //AM_RANGE(0xa0, 0xa1) AM_MIRROR(0x7E18) AM_DEVREADWRITE("debug8255", 8255_device, read, write) // debugger board 8255
334   //AM_RANGE(0xc0, 0xc1) AM_MIRROR(0x7E1E) AM_WRITE(FIFOBus_w) // DAC data write to FIFO
335   //AM_RANGE(0x100, 0x101) AM_MIRROR(0x7E1E) AM_WRITE(SelDiskReg_w) I/O register (adc speed, crtc pixel clock enable, +5 and +12v relays for floppy, etc)
336   //AM_RANGE(0x120, 0x121) AM_MIRROR(0x7E18) AM_DEVREADWRITE("wd1791", fd1971_device) // floppy controller
337   AM_RANGE(0x140, 0x15f) AM_MIRROR(0x7E00) AM_DEVREADWRITE8("crt5027", crt5027_device, read, write, 0x00FF) // crt controller
338   AM_RANGE(0x1a0, 0x1a1) AM_MIRROR(0x7E10) AM_READ(ReadEIAStatus_r) // read keyboard fifo state
339   AM_RANGE(0x1a2, 0x1a3) AM_MIRROR(0x7E10) AM_READ(ReadEIAData_r) // read keyboard data
340   AM_RANGE(0x1a8, 0x1a9) AM_MIRROR(0x7E10) AM_WRITE(LoadEIACtlReg_w) // kbd uart control register
341   AM_RANGE(0x1aa, 0x1ab) AM_MIRROR(0x7E10) AM_WRITE(LoadEIAData_w) // kbd uart data register
342   AM_RANGE(0x1ac, 0x1ad) AM_MIRROR(0x7E10) AM_WRITE(EIADataReset_w) // kbd uart ddr switch (data reset)
343   AM_RANGE(0x1ae, 0x1af) AM_MIRROR(0x7E10) AM_WRITE(EIAChipReset_w) // kbd uart reset
344   //AM_RANGE(0x1c0, 0x1c1) AM_MIRROR(0x7E1E) AM_READ(SelADCHi_r) // ADC read
345   //AM_RANGE(0x1e0, 0x1e1) AM_MIRROR(0x7E1E) AM_READ(CRTSwitch_w) // CRT power enable?
197346ADDRESS_MAP_END
198347
199/* writes during boot:
2000x88 to port 0x020 (PCR; boot sequence done(1), processor not locked(0), battery charger off(0), rom not disabled(0) correction off&cr4 off(1), cr3 on(0), cr2 on(0), cr1 on (0);)
2010x02 to port 0x100 (IOR write: enable 5v only relay control for powering up 4116 dram enabled)
2020x03 to port 0x100 (IOR write: in addition to above, enable 12v relay control for powering up 4116 dram enabled)
348/* iopic8259 interrupts:
349irq0   parity error (parity error syndrome data will be in fffdx/fffex) - currently ignored
350irq1   IPSysInt (interrupt triggered by the emulator cpu)
351irq2   DiskInt   (interrupt triggered by the IRQ or DRQ pins from the WD1791)
352irq3   EIAInt   (interrupt triggered by the datareceived pin from the eiauart)
353irq4   OddInt   (interrupt triggered by the O/E Odd/Even pin from the crt5027)
354irq5   ADCInt   (interrupt triggered at the ADCSpd rate interrupt from 74c161 counter on the disk/display module to indicate adc conversion finished)
355irq6   KbdInt   (interrupt triggered by the datareceived pin from the kbduart)
356irq7   VSync   (interrupt from the VSYN VSync pin from the crt5027)
357*/
358
359/* writes during boot of io roms v2.0:
3600x88 to port 0x020 (PCR; BootSeqDone(1), processor not locked(0), battery charger off(0), rom not disabled(0) correction off&cr4 off(1), cr3 on(0), cr2 on(0), cr1 on (0);)
3610x02 to port 0x100 (IOR write: enable 5v only relay control)
3620x03 to port 0x100 (IOR write: in addition to above, enable 12v relay control)
203363<dram memory 0x00000-0x3ffff is zeroed here>
2043640x13 to port 0x000 PIC (?????)
2053650x08 to port 0x002 PIC (UART int enabled)
r253686r253687
231391{
232392   m_BootSeqDone = 0;
233393   m_DisableROM = 0;
394   m_kbduart->set_input_pin(AY31015_SWE, 0); // status word outputs are permanently enabled (pin 16 SFD(SWE) tied low, active)
234395}
235396
236397/* Input ports */
r253686r253687
239400
240401static MACHINE_CONFIG_START( notetakr, notetaker_state )
241402   /* basic machine hardware */
242   MCFG_CPU_ADD("maincpu", I8086, XTAL_24MHz/3) /* iD8086-2 @ E4A; 24Mhz crystal divided down to 8Mhz by i8284 clock generator */
243   MCFG_CPU_PROGRAM_MAP(notetaker_mem)
244   MCFG_CPU_IO_MAP(notetaker_io)
245   MCFG_CPU_IRQ_ACKNOWLEDGE_DEVICE("pic8259", pic8259_device, inta_cb)
246   MCFG_PIC8259_ADD("pic8259", INPUTLINE("maincpu", 0), VCC, NULL) // iP8259A-2 @ E6
403   /* IO CPU: 8086@8MHz */
404   MCFG_CPU_ADD("iocpu", I8086, XTAL_24MHz/3) /* iD8086-2 @ E4A; 24Mhz crystal divided down to 8Mhz by i8284 clock generator */
405   MCFG_CPU_PROGRAM_MAP(notetaker_iocpu_mem)
406   MCFG_CPU_IO_MAP(notetaker_iocpu_io)
407   MCFG_CPU_IRQ_ACKNOWLEDGE_DEVICE("iopic8259", pic8259_device, inta_cb)
408   MCFG_PIC8259_ADD("iopic8259", INPUTLINE("iocpu", 0), VCC, NULL) // iP8259A-2 @ E6
247409
248   //Note there is a second i8086 cpu on the 'emulator board', which is probably loaded with code once smalltalk-78 loads
410   /* Emulator CPU: 8086@5MHz */
411   /*MCFG_CPU_ADD("emulatorcpu", I8086, XTAL_15MHz/3)
412   MCFG_CPU_PROGRAM_MAP(notetaker_emulatorcpu_mem)
413   MCFG_CPU_IO_MAP(notetaker_emulatorcpu_io)
414   MCFG_CPU_IRQ_ACKNOWLEDGE_DEVICE("emulatorpic8259", pic8259_device, inta_cb)
415   MCFG_PIC8259_ADD("emulatorpic8259", INPUTLINE("emulatorcpu", 0), VCC, NULL) // iP8259A-2 @ E6
416   */
249417
250418   /* video hardware */
251   /*MCFG_SCREEN_ADD("screen", RASTER)
419   MCFG_SCREEN_ADD("screen", RASTER)
252420   MCFG_SCREEN_REFRESH_RATE(60)
253421   MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(250))
254422   MCFG_SCREEN_UPDATE_DRIVER(notetaker_state, screen_update)
255423   MCFG_SCREEN_SIZE(64*6, 32*8)
256424   MCFG_SCREEN_VISIBLE_AREA(0, 64*6-1, 0, 32*8-1)
425   MCFG_SCREEN_PALETTE("palette")
257426
258   MCFG_PALETTE_ADD_3BIT_RGB("palette")
427   MCFG_PALETTE_ADD_BLACK_AND_WHITE("palette")
259428
260   MCFG_DEVICE_ADD("crt5027", CRT5027, XTAL_17_9712MHz/2)
261   //MCFG_TMS9927_CHAR_WIDTH(6)
262   //MCFG_TMS9927_VSYN_CALLBACK(DEVWRITELINE(TMS5501_TAG, tms5501_device, sens_w))
263   MCFG_VIDEO_SET_SCREEN("screen")*/
429   MCFG_DEVICE_ADD( "crt5027", CRT5027, XTAL_36MHz/14) // the clock for the crt5027 is configurable rate; 36MHz xtal divided by 1*,2,4,6,8,10,12, or 14 (* because this setting may actually oscillate unstably, or not clock at all)
430   MCFG_VIDEO_SET_SCREEN("screen")
431
432   MCFG_DEVICE_ADD( "kbduart", AY31015, 0 )
433   MCFG_AY31015_RX_CLOCK(XTAL_960kHz) // hard-wired to 960KHz xtal #f11 (60000 baud, 16 clocks per baud)
434   MCFG_AY31015_TX_CLOCK(XTAL_960kHz) // hard-wired to 960KHz xtal #f11 (60000 baud, 16 clocks per baud)
435
436   MCFG_DEVICE_ADD( "eiauart", AY31015, 0 )
437   MCFG_AY31015_RX_CLOCK((96000/4)/5) // hard-wired through an mc14568b divider set to divide by 4, the result set to divide by 5; this resulting 4800hz signal being 300 baud (16 clocks per baud)
438   MCFG_AY31015_TX_CLOCK((96000/4)/5) // hard-wired through an mc14568b divider set to divide by 4, the result set to divide by 5; this resulting 4800hz signal being 300 baud (16 clocks per baud)
264439   /* Devices */
265440
266441MACHINE_CONFIG_END
r253686r253687
271446   // interfacing with older xerox technologies which used A0 and D0 as the MSB bits
272447   // or maybe because someone screwed up somewhere along the line. we may never know.
273448   // see http://bitsavers.informatik.uni-stuttgart.de/pdf/xerox/notetaker/schematics/19790423_Notetaker_IO_Processor.pdf pages 12 and onward
274   UINT16 *romsrc = (UINT16 *)(memregion("maincpuload")->base());
275   UINT16 *romdst = (UINT16 *)(memregion("maincpu")->base());
449   UINT16 *romsrc = (UINT16 *)(memregion("iocpuload")->base());
450   UINT16 *romdst = (UINT16 *)(memregion("iocpu")->base());
276451   UINT16 *temppointer;
277452   UINT16 wordtemp;
278453   UINT16 addrtemp;
r253686r253687
290465
291466/* ROM definition */
292467ROM_START( notetakr )
293   ROM_REGION( 0x1000, "maincpuload", ROMREGION_ERASEFF ) // load roms here before descrambling
468   ROM_REGION( 0x1000, "iocpuload", ROMREGION_ERASEFF ) // load roms here before descrambling
294469   ROM_SYSTEM_BIOS( 0, "v2.00", "IO Monitor v2.00" ) // dumped from Notetaker
295470   ROMX_LOAD( "biop__2.00_hi.b2716.h1", 0x0000, 0x0800, CRC(1119691d) SHA1(4c20b595b554e6f5489ab2c3fb364b4a052f05e3), ROM_SKIP(1) | ROM_BIOS(1))
296471   ROMX_LOAD( "biop__2.00_lo.b2716.g1", 0x0001, 0x0800, CRC(b72aa4c7) SHA1(85dab2399f906c7695dc92e7c18f32e2303c5892), ROM_SKIP(1) | ROM_BIOS(1))
297472   ROM_SYSTEM_BIOS( 1, "v1.50", "IO Monitor v1.50" ) // typed from the source listing at http://bitsavers.trailing-edge.com/pdf/xerox/notetaker/memos/19790620_Z-IOP_1.5_ls.pdf and scrambled
298473   ROMX_LOAD( "z-iop_1.50_hi.h1", 0x0000, 0x0800, CRC(2994656e) SHA1(ca2bb38eb9075c5c2f3cc5439b209e7e216084da), ROM_SKIP(1) | ROM_BIOS(2))
299474   ROMX_LOAD( "z-iop_1.50_lo.g1", 0x0001, 0x0800, CRC(2cb79a67) SHA1(692aafd2aeea27533f6288dbb1cb8678ea08fade), ROM_SKIP(1) | ROM_BIOS(2))
300   ROM_REGION( 0x100000, "maincpu", ROMREGION_ERASEFF ) // area for descrambled roms
301   ROM_REGION( 0x100000, "ram", ROMREGION_ERASEFF ) // ram cards
475   ROM_REGION( 0x100000, "iocpu", ROMREGION_ERASEFF ) // area for descrambled roms
476   ROM_REGION( 0x100000, "mainram", ROMREGION_ERASEFF ) // ram cards
302477   ROM_REGION( 0x1000, "proms", ROMREGION_ERASEFF )
303478   ROM_LOAD( "disksep.prom.82s147.a4", 0x000, 0x200, NO_DUMP ) // disk data separator prom from the disk/display module board
304   ROM_LOAD( "setmemrq.prom.82s126.d9", 0x200, 0x100, NO_DUMP ) // SETMEMRQ memory timing prom from the disk/display module board; The equations for this one are actually listed on the schematic, so it should be pretty easy to recreate.
479   ROM_LOAD( "memcasraswrite.prom.82s147.b1", 0x200, 0x200, NO_DUMP ) // memory cas/ras/write prom from the memory address logic board
480   ROM_LOAD( "setmemrq.prom.82s126.d9", 0x400, 0x100, NO_DUMP ) // SETMEMRQ memory timing prom from the disk/display module board; The equations for this one are actually listed on the schematic and the prom dump can be generated from these:
481   /*
482   SetMemRq:
483   Address:
484   01234567
485   |||||||\- RCtr.3 (LSB)
486   ||||||\-- RCtr.2
487   |||||\--- RCtr.1
488   ||||\---- RCtr.0 (MSB)
489   |||\----- WCtr.3 (LSB)
490   ||\------ WCtr.2
491   |\------- WCtr.1
492   \-------- WCtr.0 (MSB)
493   
494   Data:
495   0123
496   |\\\- N/C (zero?)
497   \---- SetMemRq
498   
499   Equation: SETMEMRQ == (
500     ((Rctr == 0) && ((Wctr == 0)||(Wctr == 4)||(Wctr == 8)))
501   ||((Rctr == 4) && ((Wctr == 4)||(Wctr == 8)||(Wctr == 12)))
502   ||((Rctr == 8) && ((Wctr == 8)||(Wctr == 12)||(Wctr == 0)))
503   ||((Rctr == 12) && ((Wctr == 12)||(Wctr == 0)||(Wctr == 4)))
504   )
505   (the setmemrq output might be inverted, as well)
506   */
305507ROM_END
306508
307509/* Driver */

https://github.com/mamedev/mame/commit/e27949219d4c770b80e3cd519701e1afa07d1366

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