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r45086 Sunday 21st February, 2016 at 09:52:41 UTC by Sandro Ronco
Convert avigo.cpp, mstation.cpp and rex6000.cpp to use bankdev. (nw)

[src/mame/drivers]	avigo.cpp mstation.cpp rex6000.cpp
[src/mame/includes]	avigo.h

trunk/src/mame/drivers/avigo.cpp

r253597	r253598
77	77	#define LOG(x) do { if (AVIGO_LOG) logerror x; } while (0)
78	78
79	79
80		/* memory 0x0000-0x03fff */
81		READ8_MEMBER(avigo_state::flash_0x0000_read_handler)
82		{
83		return m_flashes[0]->read(offset);
84		}
85
86		/* memory 0x0000-0x03fff */
87		WRITE8_MEMBER(avigo_state::flash_0x0000_write_handler)
88		{
89		m_flashes[0]->write(offset, data);
90		}
91
92		/* memory 0x04000-0x07fff */
93		READ8_MEMBER(avigo_state::flash_0x4000_read_handler)
94		{
95		return m_flashes[m_flash_at_0x4000]->read((m_bank1_l<<14) | offset);
96		}
97
98		/* memory 0x04000-0x07fff */
99		WRITE8_MEMBER(avigo_state::flash_0x4000_write_handler)
100		{
101		m_flashes[m_flash_at_0x4000]->write((m_bank1_l<<14) | offset, data);
102		}
103
104		/* memory 0x08000-0x0bfff */
105		READ8_MEMBER(avigo_state::flash_0x8000_read_handler)
106		{
107		return m_flashes[m_flash_at_0x8000]->read((m_bank2_l<<14) | offset);
108		}
109
110		/* memory 0x08000-0x0bfff */
111		WRITE8_MEMBER(avigo_state::flash_0x8000_write_handler)
112		{
113		m_flashes[m_flash_at_0x8000]->write((m_bank2_l<<14) | offset, data);
114		}
115
116
117	80	/*
118	81	IRQ bits (port 3) ordered by priority:
119	82
r253597	r253598
150	113	//#endif
151	114	}
152	115
153		void avigo_state::refresh_memory(UINT8 bank, UINT8 chip_select)
154		{
155		address_space& space = m_maincpu->space(AS_PROGRAM);
156		int &active_flash = (bank == 1 ? m_flash_at_0x4000 : m_flash_at_0x8000);
157		char bank_tag[6];
158
159		LOG(("Chip %02x mapped at %04x - %04x\n", chip_select, bank * 0x4000, bank * 0x4000 + 0x3fff));
160
161		switch (chip_select)
162		{
163		case 0x06:  // videoram
164		space.install_readwrite_handler(bank * 0x4000, bank * 0x4000 + 0x3fff, read8_delegate(FUNC(avigo_state::vid_memory_r), this), write8_delegate(FUNC(avigo_state::vid_memory_w), this));
165		active_flash = -1;
166		break;
167
168		case 0x01: // banked RAM
169		sprintf(bank_tag,"bank%d", bank);
170		membank(bank_tag)->set_base(m_ram_base + (((bank == 1 ? m_bank1_l : m_bank2_l) & 0x07)<<14));
171		space.install_readwrite_bank (bank * 0x4000, bank * 0x4000 + 0x3fff, bank_tag);
172		active_flash = -1;
173		break;
174
175		case 0x00:  // flash 0
176		case 0x03:  // flash 1
177		case 0x05:  // flash 2
178		case 0x07:  // flash 0
179		if (active_flash < 0)   // to avoid useless calls to install_readwrite_handler that cause slowdowns
180		{
181		if (bank == 1)
182		space.install_readwrite_handler(0x4000, 0x7fff, read8_delegate(FUNC(avigo_state::flash_0x4000_read_handler), this), write8_delegate(FUNC(avigo_state::flash_0x4000_write_handler), this));
183		else
184		space.install_readwrite_handler(0x8000, 0xbfff, read8_delegate(FUNC(avigo_state::flash_0x8000_read_handler), this), write8_delegate(FUNC(avigo_state::flash_0x8000_write_handler), this));
185		}
186
187		switch (chip_select)
188		{
189		case 0x00:
190		case 0x07: active_flash = 0; break;
191		case 0x03: active_flash = 1; break;
192		case 0x05: active_flash = 2; break;
193		}
194		break;
195
196		default:
197		logerror("Unknown chip %02x mapped at %04x - %04x\n", chip_select, bank * 0x4000, bank * 0x4000 + 0x3fff);
198		space.unmap_readwrite(bank * 0x4000, bank * 0x4000 + 0x3fff);
199		active_flash = -1;
200		break;
201		}
202		}
203
204
205	116	WRITE_LINE_MEMBER( avigo_state::com_interrupt )
206	117	{
207	118	LOG(("com int\r\n"));
r253597	r253598
218	129
219	130	void avigo_state::machine_reset()
220	131	{
221		/* if is a cold start initialize flash contents */
222		if (!m_warm_start)
223		{
224		memcpy(m_flashes[0]->space().get_read_ptr(0), memregion("bios")->base() + 0x000000, 0x100000);
225		memcpy(m_flashes[1]->space().get_read_ptr(0), memregion("bios")->base() + 0x100000, 0x100000);
226		}
227
228	132	m_irq = 0;
229	133	m_bank1_l = 0;
230	134	m_bank1_h = 0;
231	135	m_bank2_l = 0;
232	136	m_bank2_h = 0;
233		m_flash_at_0x4000 = -1;
234		m_flash_at_0x8000 = -1;
235	137
236		refresh_memory(1, m_bank1_h & 0x07);
237		refresh_memory(2, m_bank2_h & 0x07);
	138	m_bankdev1->set_bank(0);
	139	m_bankdev2->set_bank(0);
238	140	}
239	141
240	142	void avigo_state::machine_start()
241	143	{
242		m_ram_base = (UINT8*)m_ram->pointer();
243
244	144	// bank3 always first ram bank
245		membank("bank3")->set_base(m_ram_base);
	145	membank("bank2")->set_base(m_nvram);
246	146
247		/* keep machine pointers to flash devices */
248		m_flashes[0] = machine().device<intelfsh8_device>("flash0");
249		m_flashes[1] = machine().device<intelfsh8_device>("flash1");
250		m_flashes[2] = machine().device<intelfsh8_device>("flash2");
251
252		machine().device<nvram_device>("nvram")->set_base(m_ram_base, m_ram->size());
253	147	m_warm_start = 1;
254	148
255	149	// register for state saving
r253597	r253598
261	155	save_item(NAME(m_bank1_l));
262	156	save_item(NAME(m_bank1_h));
263	157	save_item(NAME(m_ad_control_status));
264		save_item(NAME(m_flash_at_0x4000));
265		save_item(NAME(m_flash_at_0x8000));
266	158	save_item(NAME(m_ad_value));
267	159	save_item(NAME(m_screen_column));
268	160	save_item(NAME(m_warm_start));
	161	}
269	162
270		// save all flash contents
271		save_pointer(NAME((UINT8*)m_flashes[0]->space().get_read_ptr(0)), 0x100000);
272		save_pointer(NAME((UINT8*)m_flashes[1]->space().get_read_ptr(0)), 0x100000);
273		save_pointer(NAME((UINT8*)m_flashes[2]->space().get_read_ptr(0)), 0x100000);
	163	static ADDRESS_MAP_START(avigo_banked_map, AS_PROGRAM, 8, avigo_state)
	164	AM_RANGE(0x0000000, 0x00fffff) AM_MIRROR(0x0300000) AM_DEVREADWRITE("flash0", intelfsh8_device, read, write)
	165	AM_RANGE(0x0400000, 0x041ffff) AM_MIRROR(0x03e0000) AM_RAM AM_SHARE("nvram")
274	166
275		// register postload callback
276		machine().save().register_postload(save_prepost_delegate(FUNC(avigo_state::postload), this));
277		}
	167	AM_RANGE(0x0c00000, 0x0cfffff) AM_MIRROR(0x0300000) AM_DEVREADWRITE("flash1", intelfsh8_device, read, write)
	168	AM_RANGE(0x1400000, 0x14fffff) AM_MIRROR(0x0300000) AM_DEVREADWRITE("flash2", intelfsh8_device, read, write)
	169	AM_RANGE(0x1c00000, 0x1cfffff) AM_MIRROR(0x0300000) AM_DEVREADWRITE("flash0", intelfsh8_device, read, write)
278	170
279		void avigo_state::postload()
280		{
281		// refresh the bankswitch
282		refresh_memory(1, m_bank1_h & 0x07);
283		refresh_memory(2, m_bank2_h & 0x07);
284		}
	171	AM_RANGE(0x1800000, 0x1803fff) AM_MIRROR(0x03fc000) AM_READWRITE(vid_memory_r, vid_memory_w)
	172	ADDRESS_MAP_END
285	173
286	174	static ADDRESS_MAP_START( avigo_mem , AS_PROGRAM, 8, avigo_state)
287		AM_RANGE(0x0000, 0x3fff) AM_READWRITE(flash_0x0000_read_handler, flash_0x0000_write_handler)
288		AM_RANGE(0x4000, 0x7fff) AM_READWRITE_BANK("bank1")
289		AM_RANGE(0x8000, 0xbfff) AM_READWRITE_BANK("bank2")
290		AM_RANGE(0xc000, 0xffff) AM_READWRITE_BANK("bank3")
	175	AM_RANGE(0x0000, 0x3fff) AM_DEVREADWRITE("flash0", intelfsh8_device, read, write)
	176	AM_RANGE(0x4000, 0x7fff) AM_DEVREADWRITE("bank0", address_map_bank_device, read8, write8)
	177	AM_RANGE(0x8000, 0xbfff) AM_DEVREADWRITE("bank1", address_map_bank_device, read8, write8)
	178	AM_RANGE(0xc000, 0xffff) AM_RAMBANK("bank2")
291	179	ADDRESS_MAP_END
292	180
293	181
r253597	r253598
378	266	m_bank1_l = data & 0x3f;
379	267	}
380	268
381		refresh_memory(1, m_bank1_h & 0x07);
	269	m_bankdev1->set_bank(((m_bank1_h & 0x07) << 8) | m_bank1_l);
382	270	}
383	271
384	272	WRITE8_MEMBER(avigo_state::bank2_w)
r253597	r253598
394	282	m_bank2_l = data & 0x3f;
395	283	}
396	284
397		refresh_memory(2, m_bank2_h & 0x07);
	285	m_bankdev2->set_bank(((m_bank2_h & 0x07) << 8) | m_bank2_l);
398	286	}
399	287
400	288	READ8_MEMBER(avigo_state::ad_control_status_r)
r253597	r253598
775	663	};
776	664
777	665	static GFXDECODE_START( avigo )
778		GFXDECODE_ENTRY( "bios", 0x08992, avigo_charlayout, 0, 1 )
779		GFXDECODE_ENTRY( "bios", 0x0c020, avigo_8_by_14, 0, 1 )
780		GFXDECODE_ENTRY( "bios", 0x0c020, avigo_16_by_15, 0, 1 )
781		GFXDECODE_ENTRY( "bios", 0x14020, avigo_15_by_16, 0, 1 )
782		GFXDECODE_ENTRY( "bios", 0x1c020, avigo_8_by_8, 0, 1 )
783		GFXDECODE_ENTRY( "bios", 0x1e020, avigo_6_by_8, 0, 1 )
	666	GFXDECODE_ENTRY( "flash0", 0x08992, avigo_charlayout, 0, 1 )
	667	GFXDECODE_ENTRY( "flash0", 0x0c020, avigo_8_by_14, 0, 1 )
	668	GFXDECODE_ENTRY( "flash0", 0x0c020, avigo_16_by_15, 0, 1 )
	669	GFXDECODE_ENTRY( "flash0", 0x14020, avigo_15_by_16, 0, 1 )
	670	GFXDECODE_ENTRY( "flash0", 0x1c020, avigo_8_by_8, 0, 1 )
	671	GFXDECODE_ENTRY( "flash0", 0x1e020, avigo_6_by_8, 0, 1 )
784	672	GFXDECODE_END
785	673
786	674
r253597	r253598
800	688
801	689	QUICKLOAD_LOAD_MEMBER( avigo_state,avigo)
802	690	{
803		address_space& flash1 = m_flashes[1]->space(0);
	691	address_space& flash1 = m_flash1->space(0);
804	692	const char *systemname = machine().system().name;
805	693	UINT32 first_app_page = (0x50000>>14);
806	694	int app_page;
r253597	r253598
833	721	logerror("Application loaded at 0x%05x-0x%05x\n", app_page<<14, (app_page<<14) + (UINT32)image.length());
834	722
835	723	// copy app file into flash memory
836		image.fread((UINT8*)m_flashes[1]->space().get_read_ptr(app_page<<14), image.length());
	724	image.fread((UINT8*)flash1.get_read_ptr(app_page<<14), image.length());
837	725
838	726	// update the application ID
839	727	flash1.write_byte((app_page<<14) + 0x1a5, 0x80 + (app_page - (first_app_page>>14)));
r253597	r253598
907	795	MCFG_RAM_ADD(RAM_TAG)
908	796	MCFG_RAM_DEFAULT_SIZE("128K")
909	797
	798	MCFG_DEVICE_ADD("bank0", ADDRESS_MAP_BANK, 0)
	799	MCFG_DEVICE_PROGRAM_MAP(avigo_banked_map)
	800	MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
	801	MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
	802	MCFG_ADDRESS_MAP_BANK_STRIDE(0x4000)
	803
	804	MCFG_DEVICE_ADD("bank1", ADDRESS_MAP_BANK, 0)
	805	MCFG_DEVICE_PROGRAM_MAP(avigo_banked_map)
	806	MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
	807	MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
	808	MCFG_ADDRESS_MAP_BANK_STRIDE(0x4000)
	809
910	810	MCFG_NVRAM_ADD_CUSTOM_DRIVER("nvram", avigo_state, nvram_init)
911	811
912	812	// IRQ 1 is used for scan the pen and for cursor blinking
r253597	r253598
926	826
927	827	***************************************************************************/
928	828	ROM_START(avigo)
929		ROM_REGION(0x200000, "bios", ROMREGION_ERASEFF)
930
	829	ROM_REGION(0x100000, "flash0", ROMREGION_ERASEFF)
931	830	ROM_SYSTEM_BIOS( 0, "v1004", "v1.004" )
932	831	ROMX_LOAD("os_1004.rom", 0x000000, 0x0100000, CRC(62acd55c) SHA1(b2be12f5cc1053b6026bff2a265146ba831a7ffa), ROM_BIOS(1))
933		ROMX_LOAD("english_1004.rom", 0x100000, 0x050000, CRC(c9c3a225) SHA1(7939993a5615ca59ff2047e69b6d85122d437dca), ROM_BIOS(1))
934
935	832	ROM_SYSTEM_BIOS( 1, "v1002", "v1.002" )
936	833	ROMX_LOAD("os_1002.rom", 0x000000, 0x0100000, CRC(484bb95c) SHA1(ddc28f22f8cbc99f60f91c58ee0e2d15170024fb), ROM_BIOS(2))
937		ROMX_LOAD("english_1002.rom", 0x100000, 0x050000, CRC(31cab0ac) SHA1(87d337830506a12514a4beb9a8502a0de94816f2), ROM_BIOS(2))
938
939	834	ROM_SYSTEM_BIOS( 2, "v100", "v1.00" )
940	835	ROMX_LOAD("os_100.rom", 0x000000, 0x0100000, CRC(13ea7b38) SHA1(85566ff142d86d504ac72613f169d8758e2daa09), ROM_BIOS(3))
941		ROMX_LOAD("english_100.rom", 0x100000, 0x050000, CRC(e2824b44) SHA1(3252454b05c3d3a4d7df1cb48dc3441ae82f2b1c), ROM_BIOS(3))
942	836
	837	ROM_REGION(0x100000, "flash1", ROMREGION_ERASEFF)
	838	ROMX_LOAD("english_1004.rom", 0x000000, 0x050000, CRC(c9c3a225) SHA1(7939993a5615ca59ff2047e69b6d85122d437dca), ROM_BIOS(1))
	839	ROMX_LOAD("english_1002.rom", 0x000000, 0x050000, CRC(31cab0ac) SHA1(87d337830506a12514a4beb9a8502a0de94816f2), ROM_BIOS(2))
	840	ROMX_LOAD("english_100.rom",  0x000000, 0x050000, CRC(e2824b44) SHA1(3252454b05c3d3a4d7df1cb48dc3441ae82f2b1c), ROM_BIOS(3))
943	841	ROM_END
944	842
945	843	ROM_START(avigo_de)
946		ROM_REGION(0x200000, "bios", ROMREGION_ERASEFF)
947
	844	ROM_REGION(0x100000, "flash0", ROMREGION_ERASEFF)
948	845	ROM_SYSTEM_BIOS( 0, "v1004", "v1.004" )
949	846	ROMX_LOAD("os_1004.rom", 0x000000, 0x0100000, CRC(62acd55c) SHA1(b2be12f5cc1053b6026bff2a265146ba831a7ffa), ROM_BIOS(1))
950		ROMX_LOAD("german_1004.rom", 0x100000, 0x060000, CRC(0fa437b3) SHA1(e9352aa8fee6d93b898412bd129452b82baa9a21), ROM_BIOS(1))
951
952	847	ROM_SYSTEM_BIOS( 1, "v1002", "v1.002" )
953	848	ROMX_LOAD("os_1002.rom", 0x000000, 0x0100000, CRC(484bb95c) SHA1(ddc28f22f8cbc99f60f91c58ee0e2d15170024fb), ROM_BIOS(2))
954		ROMX_LOAD("german_1002.rom", 0x100000, 0x060000, CRC(c6bf07ba) SHA1(d3185687aa510f6c3b3ab3baaabe7e8ce1a79e3b), ROM_BIOS(2))
955
956	849	ROM_SYSTEM_BIOS( 2, "v100", "v1.00" )
957	850	ROMX_LOAD("os_100.rom", 0x000000, 0x0100000, CRC(13ea7b38) SHA1(85566ff142d86d504ac72613f169d8758e2daa09), ROM_BIOS(3))
958		ROMX_LOAD("german_100.rom", 0x100000, 0x060000, CRC(117d9189) SHA1(7e959ab1381ba831821fcf87973b25d87f12d34e), ROM_BIOS(3))
959	851
	852	ROM_REGION(0x100000, "flash1", ROMREGION_ERASEFF)
	853	ROMX_LOAD("german_1004.rom", 0x000000, 0x060000, CRC(0fa437b3) SHA1(e9352aa8fee6d93b898412bd129452b82baa9a21), ROM_BIOS(1))
	854	ROMX_LOAD("german_1002.rom", 0x000000, 0x060000, CRC(c6bf07ba) SHA1(d3185687aa510f6c3b3ab3baaabe7e8ce1a79e3b), ROM_BIOS(2))
	855	ROMX_LOAD("german_100.rom",  0x000000, 0x060000, CRC(117d9189) SHA1(7e959ab1381ba831821fcf87973b25d87f12d34e), ROM_BIOS(3))
960	856	ROM_END
961	857
962	858	ROM_START(avigo_fr)
963		ROM_REGION(0x200000, "bios", ROMREGION_ERASEFF)
964
	859	ROM_REGION(0x100000, "flash0", ROMREGION_ERASEFF)
965	860	ROM_SYSTEM_BIOS( 0, "v1004", "v1.004" )
966	861	ROMX_LOAD("os_1004.rom", 0x000000, 0x0100000, CRC(62acd55c) SHA1(b2be12f5cc1053b6026bff2a265146ba831a7ffa), ROM_BIOS(1))
967		ROMX_LOAD("french_1004.rom", 0x100000, 0x050000, CRC(5e4d90f7) SHA1(07df3af8a431ba65e079d6c987fb5d544f6541d8), ROM_BIOS(1))
968
969	862	ROM_SYSTEM_BIOS( 1, "v1002", "v1.002" )
970	863	ROMX_LOAD("os_1002.rom", 0x000000, 0x0100000, CRC(484bb95c) SHA1(ddc28f22f8cbc99f60f91c58ee0e2d15170024fb), ROM_BIOS(2))
971		ROMX_LOAD("french_1002.rom", 0x100000, 0x050000,CRC(caa3eb91) SHA1(ab199986de301d933f069a5e1f5150967e1d7f59), ROM_BIOS(2))
972
973	864	ROM_SYSTEM_BIOS( 2, "v100", "v1.00" )
974	865	ROMX_LOAD("os_100.rom", 0x000000, 0x0100000, CRC(13ea7b38) SHA1(85566ff142d86d504ac72613f169d8758e2daa09), ROM_BIOS(3))
975		ROMX_LOAD("french_100.rom", 0x100000, 0x050000, CRC(fffa2345) SHA1(399447cede3cdd0be768952cb24f7e4431147e3d), ROM_BIOS(3))
976	866
	867	ROM_REGION(0x100000, "flash1", ROMREGION_ERASEFF)
	868	ROMX_LOAD("french_1004.rom", 0x000000, 0x050000, CRC(5e4d90f7) SHA1(07df3af8a431ba65e079d6c987fb5d544f6541d8), ROM_BIOS(1))
	869	ROMX_LOAD("french_1002.rom", 0x000000, 0x050000,CRC(caa3eb91) SHA1(ab199986de301d933f069a5e1f5150967e1d7f59), ROM_BIOS(2))
	870	ROMX_LOAD("french_100.rom",  0x000000, 0x050000, CRC(fffa2345) SHA1(399447cede3cdd0be768952cb24f7e4431147e3d), ROM_BIOS(3))
977	871	ROM_END
978	872
979	873	ROM_START(avigo_es)
980		ROM_REGION(0x200000, "bios", ROMREGION_ERASEFF)
981
	874	ROM_REGION(0x100000, "flash0", ROMREGION_ERASEFF)
982	875	ROM_SYSTEM_BIOS( 0, "v1004", "v1.004" )
983	876	ROMX_LOAD("os_1004.rom", 0x000000, 0x0100000, CRC(62acd55c) SHA1(b2be12f5cc1053b6026bff2a265146ba831a7ffa), ROM_BIOS(1))
984		ROMX_LOAD("spanish_1004.rom", 0x100000, 0x060000, CRC(235a7f8d) SHA1(94da4ecafb54dcd5d80bc5063cb4024e66e6a21f), ROM_BIOS(1))
985
986	877	ROM_SYSTEM_BIOS( 1, "v1002", "v1.002" )
987	878	ROMX_LOAD("os_1002.rom", 0x000000, 0x0100000, CRC(484bb95c) SHA1(ddc28f22f8cbc99f60f91c58ee0e2d15170024fb), ROM_BIOS(2))
988		ROMX_LOAD("spanish_1002.rom", 0x100000, 0x060000, CRC(a6e80cc4) SHA1(e741657558c11f7bce646ba3d7b5f845bfa275b7), ROM_BIOS(2))
989
990	879	ROM_SYSTEM_BIOS( 2, "v100", "v1.00" )
991	880	ROMX_LOAD("os_100.rom", 0x000000, 0x0100000, CRC(13ea7b38) SHA1(85566ff142d86d504ac72613f169d8758e2daa09), ROM_BIOS(3))
992		ROMX_LOAD("spanish_100.rom", 0x100000, 0x060000, CRC(953a5276) SHA1(b9ba1dbdc2127b1ef419c911ef66313024a7351a), ROM_BIOS(3))
993	881
	882	ROM_REGION(0x100000, "flash1", ROMREGION_ERASEFF)
	883	ROMX_LOAD("spanish_1004.rom", 0x000000, 0x060000, CRC(235a7f8d) SHA1(94da4ecafb54dcd5d80bc5063cb4024e66e6a21f), ROM_BIOS(1))
	884	ROMX_LOAD("spanish_1002.rom", 0x000000, 0x060000, CRC(a6e80cc4) SHA1(e741657558c11f7bce646ba3d7b5f845bfa275b7), ROM_BIOS(2))
	885	ROMX_LOAD("spanish_100.rom",  0x000000, 0x060000, CRC(953a5276) SHA1(b9ba1dbdc2127b1ef419c911ef66313024a7351a), ROM_BIOS(3))
994	886	ROM_END
995	887
996	888	ROM_START(avigo_it)
997		ROM_REGION(0x200000, "bios", ROMREGION_ERASEFF)
998
	889	ROM_REGION(0x100000, "flash0", ROMREGION_ERASEFF)
999	890	ROM_SYSTEM_BIOS( 0, "v1004", "v1.004" )
1000	891	ROMX_LOAD("os_1004.rom", 0x000000, 0x0100000, CRC(62acd55c) SHA1(b2be12f5cc1053b6026bff2a265146ba831a7ffa), ROM_BIOS(1))
1001		ROMX_LOAD("italian_1004.rom", 0x100000, 0x050000, CRC(fb7941ec) SHA1(230e8346a3b0da1ee24568ec090ce6860ebfe995), ROM_BIOS(1))
1002
1003	892	ROM_SYSTEM_BIOS( 1, "v1002", "v1.002" )
1004	893	ROMX_LOAD("os_1002.rom", 0x000000, 0x0100000, CRC(484bb95c) SHA1(ddc28f22f8cbc99f60f91c58ee0e2d15170024fb), ROM_BIOS(2))
1005		ROMX_LOAD("italian_1002.rom", 0x100000, 0x050000, CRC(093bc032) SHA1(2c75d950d356a7fd1d058808e5f0be8e15b8ea2a), ROM_BIOS(2))
1006
1007	894	ROM_SYSTEM_BIOS( 2, "v100", "v1.00" )
1008	895	ROMX_LOAD("os_100.rom", 0x000000, 0x0100000, CRC(13ea7b38) SHA1(85566ff142d86d504ac72613f169d8758e2daa09), ROM_BIOS(3))
1009		ROMX_LOAD("italian_100.rom", 0x100000, 0x050000, CRC(de359218) SHA1(6185727aba8ffc98723f2df74dda388fd0d70cc9), ROM_BIOS(3))
	896
	897	ROM_REGION(0x100000, "flash1", ROMREGION_ERASEFF)
	898	ROMX_LOAD("italian_1004.rom", 0x000000, 0x050000, CRC(fb7941ec) SHA1(230e8346a3b0da1ee24568ec090ce6860ebfe995), ROM_BIOS(1))
	899	ROMX_LOAD("italian_1002.rom", 0x000000, 0x050000, CRC(093bc032) SHA1(2c75d950d356a7fd1d058808e5f0be8e15b8ea2a), ROM_BIOS(2))
	900	ROMX_LOAD("italian_100.rom",  0x000000, 0x050000, CRC(de359218) SHA1(6185727aba8ffc98723f2df74dda388fd0d70cc9), ROM_BIOS(3))
1010	901	ROM_END
1011	902
1012	903	/*    YEAR  NAME    PARENT  COMPAT  MACHINE INPUT   INIT    COMPANY   FULLNAME */

trunk/src/mame/drivers/mstation.cpp

r253597	r253598
28	28
29	29	#include "emu.h"
30	30	#include "cpu/z80/z80.h"
	31	#include "machine/bankdev.h"
31	32	#include "machine/intelfsh.h"
32	33	#include "machine/rp5c01.h"
33	34	#include "machine/ram.h"
r253597	r253598
39	40	mstation_state(const machine_config &mconfig, device_type type, const char *tag)
40	41	: driver_device(mconfig, type, tag),
41	42	m_maincpu(*this, "maincpu"),
42		m_ram(*this, RAM_TAG)
	43	m_ram(*this, RAM_TAG),
	44	m_bankdev1(*this, "bank0"),
	45	m_bankdev2(*this, "bank1"),
	46	m_keyboard(*this, "LINE"),
	47	m_nvram(*this, "nvram")
43	48	{ }
44	49
45	50	required_device<cpu_device> m_maincpu;
46	51	required_device<ram_device> m_ram;
	52	required_device<address_map_bank_device> m_bankdev1;
	53	required_device<address_map_bank_device> m_bankdev2;
	54	required_ioport_array<10> m_keyboard;
	55	required_shared_ptr<UINT8> m_nvram;
47	56
48		intelfsh8_device *m_flashes[2];
49	57	UINT8 m_bank1[2];
50	58	UINT8 m_bank2[2];
51		UINT8 *m_ram_base;
52		int m_flash_at_0x4000;
53		int m_flash_at_0x8000;
54	59	UINT8 *m_vram;
55	60	UINT8 m_screen_column;
56	61	UINT8 m_port2;
57	62	UINT8 m_irq;
58	63	UINT16 m_kb_matrix;
59	64
60		DECLARE_READ8_MEMBER( flash_0x0000_read_handler );
61		DECLARE_WRITE8_MEMBER( flash_0x0000_write_handler );
62		DECLARE_READ8_MEMBER( flash_0x4000_read_handler );
63		DECLARE_WRITE8_MEMBER( flash_0x4000_write_handler );
64		DECLARE_READ8_MEMBER( flash_0x8000_read_handler );
65		DECLARE_WRITE8_MEMBER( flash_0x8000_write_handler );
66	65	DECLARE_READ8_MEMBER( modem_r );
67	66	DECLARE_WRITE8_MEMBER( modem_w );
68	67
r253597	r253598
73	72	DECLARE_READ8_MEMBER( lcd_left_r );
74	73	DECLARE_WRITE8_MEMBER( lcd_left_w );
75	74
76		void refresh_memory(UINT8 bank, UINT8 chip_select);
77	75	DECLARE_READ8_MEMBER( bank1_r );
78	76	DECLARE_WRITE8_MEMBER( bank1_w );
79	77	DECLARE_READ8_MEMBER( bank2_r );
r253597	r253598
97	95	TIMER_DEVICE_CALLBACK_MEMBER(mstation_kb_timer);
98	96	};
99	97
100		READ8_MEMBER( mstation_state::flash_0x0000_read_handler )
101		{
102		return m_flashes[0]->read(offset);
103		}
104	98
105		WRITE8_MEMBER( mstation_state::flash_0x0000_write_handler )
106		{
107		m_flashes[0]->write(offset, data);
108		}
109
110		READ8_MEMBER( mstation_state::flash_0x4000_read_handler )
111		{
112		return m_flashes[m_flash_at_0x4000]->read(((m_bank1[0] & 0x3f)<<14) | offset);
113		}
114
115		WRITE8_MEMBER( mstation_state::flash_0x4000_write_handler )
116		{
117		m_flashes[m_flash_at_0x4000]->write(((m_bank1[0] & 0x3f)<<14) | offset, data);
118		}
119
120		READ8_MEMBER( mstation_state::flash_0x8000_read_handler )
121		{
122		return m_flashes[m_flash_at_0x8000]->read(((m_bank2[0] & 0x3f)<<14) | offset);
123		}
124
125		WRITE8_MEMBER( mstation_state::flash_0x8000_write_handler )
126		{
127		m_flashes[m_flash_at_0x8000]->write(((m_bank2[0] & 0x3f)<<14) | offset, data);
128		}
129
130	99	READ8_MEMBER( mstation_state::modem_r )
131	100	{
132	101	return 0xff;
r253597	r253598
185	154	//  Bankswitch
186	155	//***************************************************************************/
187	156
188		void mstation_state::refresh_memory(UINT8 bank, UINT8 chip_select)
189		{
190		address_space& program = m_maincpu->space(AS_PROGRAM);
191		int &active_flash = (bank == 1 ? m_flash_at_0x4000 : m_flash_at_0x8000);
192		char bank_tag[6];
193
194		switch (chip_select)
195		{
196		case 0: // flash 0
197		case 3: // flash 1
198		if (active_flash < 0)
199		{
200		if (bank == 1)
201		program.install_readwrite_handler(0x4000, 0x7fff, 0, 0, read8_delegate(FUNC(mstation_state::flash_0x4000_read_handler), this), write8_delegate(FUNC(mstation_state::flash_0x4000_write_handler), this));
202		else
203		program.install_readwrite_handler(0x8000, 0xbfff, 0, 0, read8_delegate(FUNC(mstation_state::flash_0x8000_read_handler), this), write8_delegate(FUNC(mstation_state::flash_0x8000_write_handler), this));
204		}
205
206		active_flash = chip_select ? 1 : 0;
207		break;
208		case 1: // banked RAM
209		sprintf(bank_tag,"bank%d", bank);
210		membank(bank_tag)->set_base(m_ram_base + (((bank == 1 ? m_bank1[0] : m_bank2[0]) & 0x07)<<14));
211		program.install_readwrite_bank (bank * 0x4000, bank * 0x4000 + 0x3fff, bank_tag);
212		active_flash = -1;
213		break;
214		case 2: // left LCD panel
215		program.install_readwrite_handler(bank * 0x4000, bank * 0x4000 + 0x3fff, 0, 0, read8_delegate(FUNC(mstation_state::lcd_left_r), this), write8_delegate(FUNC(mstation_state::lcd_left_w), this));
216		active_flash = -1;
217		break;
218		case 4: // right LCD panel
219		program.install_readwrite_handler(bank * 0x4000, bank * 0x4000 + 0x3fff, 0, 0, read8_delegate(FUNC(mstation_state::lcd_right_r), this), write8_delegate(FUNC(mstation_state::lcd_right_w), this));
220		active_flash = -1;
221		break;
222		case 5: // modem
223		program.install_readwrite_handler(bank * 0x4000, bank * 0x4000 + 0x3fff, 0x07, 0, read8_delegate(FUNC(mstation_state::modem_r), this), write8_delegate(FUNC(mstation_state::modem_w), this));
224		active_flash = -1;
225		break;
226
227		default:
228		logerror("Unknown chip %02x mapped at %04x - %04x\n", chip_select, bank * 0x4000, bank * 0x4000 + 0x3fff);
229		program.unmap_readwrite(bank * 0x4000, bank * 0x4000 + 0x3fff);
230		active_flash = -1;
231		break;
232		}
233		}
234
235	157	READ8_MEMBER( mstation_state::bank1_r )
236	158	{
237	159	return m_bank1[offset];
r253597	r253598
246	168	{
247	169	m_bank1[offset] = data;
248	170
249		refresh_memory(1, m_bank1[1] & 0x07);
	171	m_bankdev1->set_bank(((m_bank1[1] & 0x07) << 8) | m_bank1[0]);
250	172	}
251	173
252	174	WRITE8_MEMBER( mstation_state::bank2_w )
253	175	{
254	176	m_bank2[offset] = data;
255	177
256		refresh_memory(2, m_bank2[1] & 0x07);
	178	m_bankdev2->set_bank(((m_bank2[1] & 0x07) << 8) | m_bank2[0]);
257	179	}
258	180
259	181
r253597	r253598
314	236
315	237	READ8_MEMBER( mstation_state::kb_r )
316	238	{
317		static const char *const bitnames[] =   { "LINE0", "LINE1", "LINE2", "LINE3", "LINE4",
318		"LINE5", "LINE6", "LINE7", "LINE8", "LINE9" };
319	239	UINT8 data = 0xff;
320	240
321	241	for (int i=0; i<10; i++)
322	242	{
323	243	if (!(m_kb_matrix & (1<<i)))
324		data &= ioport(bitnames[i])->read();
	244	data &= m_keyboard[i]->read();
325	245	}
326	246
327	247	return data;
328	248	}
329	249
330	250
	251	static ADDRESS_MAP_START(mstation_banked_map, AS_PROGRAM, 8, mstation_state)
	252	AM_RANGE(0x0000000, 0x00fffff) AM_MIRROR(0x0300000) AM_DEVREADWRITE("flash0", intelfsh8_device, read, write)
	253	AM_RANGE(0x0400000, 0x041ffff) AM_MIRROR(0x03e0000) AM_RAM AM_SHARE("nvram")
	254	AM_RANGE(0x0c00000, 0x0c7ffff) AM_MIRROR(0x0380000) AM_DEVREADWRITE("flash1", intelfsh8_device, read, write)
	255	AM_RANGE(0x0800000, 0x0803fff) AM_MIRROR(0x03fc000) AM_READWRITE(lcd_left_r, lcd_left_w)
	256	AM_RANGE(0x1000000, 0x1003fff) AM_MIRROR(0x03fc000) AM_READWRITE(lcd_right_r, lcd_right_w)
	257	AM_RANGE(0x1400000, 0x1403fff) AM_MIRROR(0x03fc000) AM_READWRITE(modem_r, modem_w)
	258	ADDRESS_MAP_END
	259
331	260	static ADDRESS_MAP_START(mstation_mem, AS_PROGRAM, 8, mstation_state)
332		AM_RANGE(0x0000, 0x3fff) AM_READWRITE(flash_0x0000_read_handler, flash_0x0000_write_handler)
333		AM_RANGE(0x4000, 0x7fff) AM_READWRITE_BANK("bank1")     // bank 1
334		AM_RANGE(0x8000, 0xbfff) AM_READWRITE_BANK("bank2")     // bank 2
335		AM_RANGE(0xc000, 0xffff) AM_READWRITE_BANK("sysram")    // system ram always first RAM bank
	261	AM_RANGE(0x0000, 0x3fff) AM_DEVREADWRITE("flash0", intelfsh8_device, read, write)
	262	AM_RANGE(0x4000, 0x7fff) AM_DEVREADWRITE("bank0", address_map_bank_device, read8, write8)
	263	AM_RANGE(0x8000, 0xbfff) AM_DEVREADWRITE("bank1", address_map_bank_device, read8, write8)
	264	AM_RANGE(0xc000, 0xffff) AM_RAMBANK("sysram")    // system ram always first RAM bank
336	265	ADDRESS_MAP_END
337	266
338	267	static ADDRESS_MAP_START(mstation_io , AS_IO, 8, mstation_state)
r253597	r253598
350	279
351	280	/* Input ports */
352	281	static INPUT_PORTS_START( mstation )
353		PORT_START( "LINE0" )
	282	PORT_START( "LINE.0" )
354	283	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD )   PORT_NAME("Main Menu")  PORT_CODE( KEYCODE_HOME )   PORT_CHAR(UCHAR_MAMEKEY(HOME))
355	284	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD )   PORT_NAME("Back")   PORT_CODE( KEYCODE_DEL )    PORT_CHAR(UCHAR_MAMEKEY(END))
356	285	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD )   PORT_NAME("Print")  PORT_CODE( KEYCODE_F6 )
r253597	r253598
360	289	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD )   PORT_NAME("F4")     PORT_CODE( KEYCODE_F4 )     PORT_CHAR(UCHAR_MAMEKEY(F4))
361	290	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD )   PORT_NAME("F5")     PORT_CODE( KEYCODE_F5 )     PORT_CHAR(UCHAR_MAMEKEY(F5))
362	291
363		PORT_START( "LINE1" )
	292	PORT_START( "LINE.1" )
364	293	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNUSED )
365	294	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNUSED )
366	295	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNUSED )
r253597	r253598
370	299	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD )   PORT_NAME("Get E-Mail")     PORT_CODE( KEYCODE_F9 )
371	300	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD )   PORT_NAME("PG Up")      PORT_CODE( KEYCODE_PGUP )   PORT_CHAR(UCHAR_MAMEKEY(PGUP))
372	301
373		PORT_START( "LINE2" )
	302	PORT_START( "LINE.2" )
374	303	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD )   PORT_NAME("\xc2\xb4")       PORT_CODE( KEYCODE_0_PAD )
375	304	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD )   PORT_CODE( KEYCODE_1 )      PORT_CHAR('1')      PORT_CHAR('!')
376	305	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD )   PORT_CODE( KEYCODE_2 )      PORT_CHAR('2')      PORT_CHAR('@')
r253597	r253598
380	309	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD )   PORT_CODE( KEYCODE_6 )      PORT_CHAR('6')      PORT_CHAR('^')
381	310	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD )   PORT_CODE( KEYCODE_7 )      PORT_CHAR('7')      PORT_CHAR('&')
382	311
383		PORT_START( "LINE3" )
	312	PORT_START( "LINE.3" )
384	313	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD )   PORT_CODE( KEYCODE_8 )      PORT_CHAR('8')      PORT_CHAR('*')
385	314	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD )   PORT_CODE( KEYCODE_9 )      PORT_CHAR('9')      PORT_CHAR('(')
386	315	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD )   PORT_CODE( KEYCODE_0 )      PORT_CHAR('0')      PORT_CHAR(')')
r253597	r253598
390	319	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD )   PORT_CODE( KEYCODE_BACKSLASH )  PORT_CHAR('\\')     PORT_CHAR('|')
391	320	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD )   PORT_NAME("PG Down")        PORT_CODE( KEYCODE_PGDN )       PORT_CHAR(UCHAR_MAMEKEY(PGDN))
392	321
393		PORT_START( "LINE4" )
	322	PORT_START( "LINE.4" )
394	323	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD )   PORT_NAME("Tab")    PORT_CODE( KEYCODE_TAB )        PORT_CHAR(9)
395	324	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD )   PORT_CODE( KEYCODE_Q )      PORT_CHAR('q')      PORT_CHAR('Q')
396	325	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD )   PORT_CODE( KEYCODE_W )      PORT_CHAR('w')      PORT_CHAR('W')
r253597	r253598
400	329	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD )   PORT_CODE( KEYCODE_Y )      PORT_CHAR('y')      PORT_CHAR('Y')
401	330	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD )   PORT_CODE( KEYCODE_U )      PORT_CHAR('u')      PORT_CHAR('U')
402	331
403		PORT_START( "LINE5" )
	332	PORT_START( "LINE.5" )
404	333	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD )   PORT_CODE( KEYCODE_I )      PORT_CHAR('i')      PORT_CHAR('I')
405	334	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD )   PORT_CODE( KEYCODE_O )      PORT_CHAR('o')      PORT_CHAR('O')
406	335	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD )   PORT_CODE( KEYCODE_P )      PORT_CHAR('p')      PORT_CHAR('P')
r253597	r253598
410	339	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD )   PORT_CODE( KEYCODE_QUOTE )      PORT_CHAR('\'')     PORT_CHAR('\"')
411	340	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD )   PORT_NAME("Enter")      PORT_CODE( KEYCODE_ENTER )  PORT_CHAR(UCHAR_MAMEKEY(ENTER))
412	341
413		PORT_START( "LINE6" )
	342	PORT_START( "LINE.6" )
414	343	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD )   PORT_NAME("CapsLock")       PORT_CODE( KEYCODE_CAPSLOCK )       PORT_CHAR(UCHAR_MAMEKEY(CAPSLOCK))
415	344	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD )   PORT_CODE( KEYCODE_A )      PORT_CHAR('a')      PORT_CHAR('A')
416	345	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD )   PORT_CODE( KEYCODE_S )      PORT_CHAR('s')      PORT_CHAR('S')
r253597	r253598
420	349	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD )   PORT_CODE( KEYCODE_H )      PORT_CHAR('h')      PORT_CHAR('H')
421	350	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD )   PORT_CODE( KEYCODE_J )      PORT_CHAR('j')      PORT_CHAR('J')
422	351
423		PORT_START( "LINE7" )
	352	PORT_START( "LINE.7" )
424	353	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD )   PORT_CODE( KEYCODE_K )      PORT_CHAR('K')      PORT_CHAR('K')
425	354	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD )   PORT_CODE( KEYCODE_L )      PORT_CHAR('l')      PORT_CHAR('L')
426	355	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD )   PORT_CODE( KEYCODE_COMMA )  PORT_CHAR(',')      PORT_CHAR('<')
r253597	r253598
430	359	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD )   PORT_NAME("Down")       PORT_CODE( KEYCODE_DOWN )   PORT_CHAR(UCHAR_MAMEKEY(DOWN))
431	360	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD )   PORT_NAME("Right")      PORT_CODE( KEYCODE_RIGHT )  PORT_CHAR(UCHAR_MAMEKEY(RIGHT))
432	361
433		PORT_START( "LINE8" )
	362	PORT_START( "LINE.8" )
434	363	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD )   PORT_NAME("Left Shift")     PORT_CODE( KEYCODE_LSHIFT )         PORT_CHAR(UCHAR_MAMEKEY(LSHIFT))
435	364	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD )   PORT_CODE( KEYCODE_Z )      PORT_CHAR('z')      PORT_CHAR('Z')
436	365	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD )   PORT_CODE( KEYCODE_X )      PORT_CHAR('x')      PORT_CHAR('X')
r253597	r253598
440	369	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD )   PORT_CODE( KEYCODE_N )      PORT_CHAR('n')      PORT_CHAR('N')
441	370	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD )   PORT_CODE( KEYCODE_M )      PORT_CHAR('m')      PORT_CHAR('M')
442	371
443		PORT_START( "LINE9" )
	372	PORT_START( "LINE.9" )
444	373	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD )   PORT_NAME("Function")       PORT_CODE( KEYCODE_LCONTROL )   PORT_CHAR(UCHAR_MAMEKEY(LCONTROL))
445	374	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNUSED )
446	375	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNUSED )
r253597	r253598
453	382
454	383	void mstation_state::machine_start()
455	384	{
456		m_flashes[0] = machine().device<intelfsh8_device>("flash0");
457		m_flashes[1] = machine().device<intelfsh8_device>("flash1");
458
459	385	// allocate the videoram
460	386	m_vram = (UINT8*)machine().memory().region_alloc( "vram", 9600, 1, ENDIANNESS_LITTLE )->base();
461		m_ram_base = (UINT8*)m_ram->pointer();
462	387
463	388	// map firsh RAM bank at 0xc000-0xffff
464		membank("sysram")->set_base(m_ram_base);
	389	membank("sysram")->set_base(m_nvram);
465	390	}
466	391
467	392
468	393	void mstation_state::machine_reset()
469	394	{
470		m_flash_at_0x4000 = 0;
471		m_flash_at_0x8000 = 0;
472	395	m_bank1[0] =  m_bank1[1] = 0;
473	396	m_bank2[0] =  m_bank2[1] = 0;
474	397	memset(m_vram, 0, 9600);
475	398
476	399	// reset banks
477		refresh_memory(1, m_bank1[1]);
478		refresh_memory(2, m_bank2[1]);
	400	m_bankdev1->set_bank(0);
	401	m_bankdev2->set_bank(0);
479	402	}
480	403
481	404	WRITE_LINE_MEMBER( mstation_state::rtc_irq )
r253597	r253598
540	463	MCFG_DEVICE_ADD("rtc", RP5C01, XTAL_32_768kHz)
541	464	MCFG_RP5C01_OUT_ALARM_CB(WRITELINE(mstation_state, rtc_irq))
542	465
	466	MCFG_DEVICE_ADD("bank0", ADDRESS_MAP_BANK, 0)
	467	MCFG_DEVICE_PROGRAM_MAP(mstation_banked_map)
	468	MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
	469	MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
	470	MCFG_ADDRESS_MAP_BANK_STRIDE(0x4000)
	471
	472	MCFG_DEVICE_ADD("bank1", ADDRESS_MAP_BANK, 0)
	473	MCFG_DEVICE_PROGRAM_MAP(mstation_banked_map)
	474	MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
	475	MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
	476	MCFG_ADDRESS_MAP_BANK_STRIDE(0x4000)
	477
543	478	/* internal ram */
544	479	MCFG_RAM_ADD(RAM_TAG)
545	480	MCFG_RAM_DEFAULT_SIZE("128K")

trunk/src/mame/drivers/rex6000.cpp

r253597	r253598
29	29	#include "emu.h"
30	30	#include "cpu/z80/z80.h"
31	31	#include "machine/rp5c01.h"
	32	#include "machine/bankdev.h"
32	33	#include "machine/ram.h"
33	34	#include "machine/intelfsh.h"
34	35	#include "imagedev/snapquik.h"
r253597	r253598
46	47	#define IRQ_FLAG_IRQ1       0x40
47	48	#define IRQ_FLAG_EVENT      0x80
48	49
49		//memory bank types
50		#define BANK_FLASH0_B0      0x00
51		#define BANK_FLASH0_B1      0x01
52		#define BANK_FLASH1_B0      0x02
53		#define BANK_FLASH1_B1      0x03
54		#define BANK_RAM            0x10
55		#define BANK_UNKNOWN        0xff
56
57	50	#define TC8521_TAG  "rtc"
58	51
59	52	class rex6000_state : public driver_device
r253597	r253598
63	56	: driver_device(mconfig, type, tag),
64	57	m_maincpu(*this, "maincpu"),
65	58	m_ram(*this, RAM_TAG),
66		m_beep(*this, "beeper")
	59	m_beep(*this, "beeper"),
	60	m_bankdev0(*this, "bank0"),
	61	m_bankdev1(*this, "bank1"),
	62	m_flash0b(*this, "flash0b"),
	63	m_nvram(*this, "nvram")
67	64	{ }
68	65
69	66	required_device<cpu_device> m_maincpu;
70	67	required_device<ram_device> m_ram;
71	68	required_device<beep_device> m_beep;
72		fujitsu_29dl16x_device *m_flash[4];
	69	required_device<address_map_bank_device> m_bankdev0;
	70	required_device<address_map_bank_device> m_bankdev1;
	71	optional_device<intelfsh8_device> m_flash0b;
	72	required_shared_ptr<UINT8> m_nvram;
73	73
74	74	UINT8 m_bank[4];
75	75	UINT8 m_beep_io[5];
r253597	r253598
77	77	UINT8 m_touchscreen[0x10];
78	78	UINT8 m_lcd_enabled;
79	79	UINT8 m_lcd_cmd;
80		UINT8 *m_ram_base;
81	80
82	81	UINT8 m_irq_mask;
83	82	UINT8 m_irq_flag;
84	83	UINT8 m_port6;
85	84	UINT8 m_beep_mode;
86	85
87		struct
88		{
89		UINT8 type;
90		UINT16 page;
91		} m_banks[2];
92
93	86	virtual void machine_start() override;
94	87	virtual void machine_reset() override;
95	88	UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
r253597	r253598
108	101	DECLARE_WRITE8_MEMBER( touchscreen_w );
109	102	DECLARE_WRITE_LINE_MEMBER( alarm_irq );
110	103
111		DECLARE_READ8_MEMBER( flash_0x0000_r );
112		DECLARE_WRITE8_MEMBER( flash_0x0000_w );
113		DECLARE_READ8_MEMBER( flash_0x8000_r );
114		DECLARE_WRITE8_MEMBER( flash_0x8000_w );
115		DECLARE_READ8_MEMBER( flash_0xa000_r );
116		DECLARE_WRITE8_MEMBER( flash_0xa000_w );
117
118		UINT8 identify_bank_type(UINT32 bank);
119	104	DECLARE_PALETTE_INIT(rex6000);
120	105	DECLARE_INPUT_CHANGED_MEMBER(trigger_irq);
121	106	TIMER_DEVICE_CALLBACK_MEMBER(irq_timer1);
r253597	r253598
125	110	};
126	111
127	112
128		UINT8 rex6000_state::identify_bank_type(UINT32 bank)
129		{
130		if (bank < 0x080)
131		{
132		return BANK_FLASH0_B0;
133		}
134		else if (bank >= 0x080 && bank < 0x100)
135		{
136		return BANK_FLASH0_B1;
137		}
138		else if ((bank >= 0xb00 && bank < 0xb80) || (bank >= 0x600 && bank < 0x680))
139		{
140		return BANK_FLASH1_B0;
141		}
142		else if ((bank >= 0xb80 && bank < 0xc00) || (bank >= 0x680 && bank < 0x700))
143		{
144		return BANK_FLASH1_B1;
145		}
146		else if (bank >= 0x1000 && bank < 0x1004)
147		{
148		return BANK_RAM;
149		}
150		else
151		{
152		//logerror("%04x: unkonwn memory bank %x\n", m_maincpu->pc(), bank);
153		return BANK_UNKNOWN;
154		}
155		}
156	113
157	114	READ8_MEMBER( rex6000_state::bankswitch_r )
158	115	{
r253597	r253598
161	118
162	119	WRITE8_MEMBER( rex6000_state::bankswitch_w )
163	120	{
164		address_space& program = m_maincpu->space(AS_PROGRAM);
165
166	121	m_bank[offset&3] = data;
167	122
168	123	switch (offset)
r253597	r253598
171	126	case 1:     //bank 1 high
172	127	{
173	128	//bank 1 start at 0x8000
174		m_banks[0].page = (MAKE_BANK(m_bank[0], m_bank[1]&0x0f) + 4);
175		m_banks[0].type = identify_bank_type(m_banks[0].page);
176
177		if (m_banks[0].type != BANK_UNKNOWN)
178		{
179		program.install_readwrite_handler(0x8000, 0x9fff, 0, 0, read8_delegate(FUNC(rex6000_state::flash_0x8000_r), this), write8_delegate(FUNC(rex6000_state::flash_0x8000_w), this));
180		}
181		else
182		{
183		program.unmap_readwrite(0x8000, 0x9fff);
184		}
185
	129	m_bankdev0->set_bank(MAKE_BANK(m_bank[0], m_bank[1]) + 4);
186	130	break;
187	131	}
188	132	case 2:     //bank 2 low
189	133	case 3:     //bank 2 high
190	134	{
191		m_banks[1].page = MAKE_BANK(m_bank[2], m_bank[3]&0x1f);
192		m_banks[1].type = identify_bank_type(m_banks[1].page);
193
194		if (m_banks[1].type == BANK_RAM)
195		{
196		program.install_ram(0xa000, 0xbfff, m_ram_base + ((m_banks[1].page & 0x03)<<13));
197		}
198		else if (m_banks[1].type != BANK_UNKNOWN)
199		{
200		program.install_readwrite_handler(0xa000, 0xbfff, 0, 0, read8_delegate(FUNC(rex6000_state::flash_0xa000_r), this), write8_delegate(FUNC(rex6000_state::flash_0xa000_w), this));
201		}
202		else
203		{
204		program.unmap_readwrite(0xa000, 0xbfff);
205		}
206
	135	m_bankdev1->set_bank(MAKE_BANK(m_bank[2], m_bank[3]));
207	136	break;
208	137	}
209	138	}
r253597	r253598
362	291	m_touchscreen[offset&0x0f] = data;
363	292	}
364	293
365		READ8_MEMBER( rex6000_state::flash_0x0000_r )
366		{
367		return m_flash[0]->read(offset);
368		}
369	294
370		WRITE8_MEMBER( rex6000_state::flash_0x0000_w )
371		{
372		m_flash[0]->write(offset, data);
373		}
	295	static ADDRESS_MAP_START(rex6000_banked_map, AS_PROGRAM, 8, rex6000_state)
	296	AM_RANGE( 0x0000000, 0x00fffff ) AM_DEVREADWRITE("flash0a", intelfsh8_device, read, write)
	297	AM_RANGE( 0x0100000, 0x01fffff ) AM_DEVREADWRITE("flash0b", intelfsh8_device, read, write)
	298	AM_RANGE( 0x0c00000, 0x0cfffff ) AM_DEVREADWRITE("flash1a", intelfsh8_device, read, write)
	299	AM_RANGE( 0x0d00000, 0x0dfffff ) AM_DEVREADWRITE("flash1b", intelfsh8_device, read, write)
	300	AM_RANGE( 0x1600000, 0x16fffff ) AM_DEVREADWRITE("flash1a", intelfsh8_device, read, write)
	301	AM_RANGE( 0x1700000, 0x17fffff ) AM_DEVREADWRITE("flash1b", intelfsh8_device, read, write)
	302	AM_RANGE( 0x2000000, 0x2007fff ) AM_RAM AM_SHARE("nvram")
	303	ADDRESS_MAP_END
374	304
375		READ8_MEMBER( rex6000_state::flash_0x8000_r )
376		{
377		return m_flash[m_banks[0].type]->read(((m_banks[0].page & 0x7f)<<13) | offset);
378		}
379	305
380		WRITE8_MEMBER( rex6000_state::flash_0x8000_w )
381		{
382		m_flash[m_banks[0].type]->write(((m_banks[0].page & 0x7f)<<13) | offset, data);
383		}
384	306
385		READ8_MEMBER( rex6000_state::flash_0xa000_r )
386		{
387		return m_flash[m_banks[1].type]->read(((m_banks[1].page & 0x7f)<<13) | offset);
388		}
389
390		WRITE8_MEMBER( rex6000_state::flash_0xa000_w )
391		{
392		m_flash[m_banks[1].type]->write(((m_banks[1].page & 0x7f)<<13) | offset, data);
393		}
394
395
396	307	static ADDRESS_MAP_START(rex6000_mem, AS_PROGRAM, 8, rex6000_state)
397	308	ADDRESS_MAP_UNMAP_HIGH
398		AM_RANGE( 0x0000, 0x7fff ) AM_READWRITE(flash_0x0000_r, flash_0x0000_w)
399		AM_RANGE( 0x8000, 0x9fff ) AM_READWRITE(flash_0x8000_r, flash_0x8000_w)
400		AM_RANGE( 0xa000, 0xbfff ) AM_READWRITE(flash_0xa000_r, flash_0xa000_w)
	309	AM_RANGE( 0x0000, 0x7fff ) AM_DEVREADWRITE("flash0a", intelfsh8_device, read, write)
	310	AM_RANGE( 0x8000, 0x9fff ) AM_DEVREADWRITE("bank0", address_map_bank_device, read8, write8)
	311	AM_RANGE( 0xa000, 0xbfff ) AM_DEVREADWRITE("bank1", address_map_bank_device, read8, write8)
401	312	AM_RANGE( 0xc000, 0xffff ) AM_RAMBANK("ram")            //system RAM
402	313	ADDRESS_MAP_END
403	314
r253597	r253598
450	361
451	362	void rex6000_state::machine_start()
452	363	{
453		m_flash[0] = machine().device<fujitsu_29dl16x_device>("flash0a");
454		m_flash[1] = machine().device<fujitsu_29dl16x_device>("flash0b");
455		m_flash[2] = machine().device<fujitsu_29dl16x_device>("flash1a");
456		m_flash[3] = machine().device<fujitsu_29dl16x_device>("flash1b");
457
458		m_ram_base = m_ram->pointer();
459		membank("ram")->set_base(m_ram_base + 0x4000);
	364	membank("ram")->set_base((UINT8*)m_nvram + 0x4000);
460	365	}
	366
461	367	void rex6000_state::machine_reset()
462	368	{
463		address_space& program = m_maincpu->space(AS_PROGRAM);
464
465		program.install_readwrite_handler(0x8000, 0x9fff, 0, 0, read8_delegate(FUNC(rex6000_state::flash_0x8000_r), this), write8_delegate(FUNC(rex6000_state::flash_0x8000_w), this));
466		program.install_readwrite_handler(0xa000, 0xbfff, 0, 0, read8_delegate(FUNC(rex6000_state::flash_0xa000_r), this), write8_delegate(FUNC(rex6000_state::flash_0xa000_w), this));
467
468		m_banks[0].type = 0x04;
469		m_banks[0].type = 0;
470		m_banks[1].type = 0x00;
471		m_banks[1].type = 0;
472
473		memset(m_ram_base, 0, m_ram->size());
474	369	memset(m_bank, 0, sizeof(m_bank));
475	370	memset(m_beep_io, 0, sizeof(m_beep_io));
476	371	memset(m_lcd_base, 0, sizeof(m_lcd_base));
r253597	r253598
485	380
486	381	UINT32 rex6000_state::screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
487	382	{
488		UINT16 lcd_bank = MAKE_BANK(m_lcd_base[0], m_lcd_base[1]&0x1f);
489		UINT8 mem_type = identify_bank_type(lcd_bank);
	383	UINT16 lcd_bank = MAKE_BANK(m_lcd_base[0], m_lcd_base[1]);
490	384
491		if (m_lcd_enabled && mem_type != BANK_UNKNOWN)
	385	if (m_lcd_enabled)
492	386	{
493	387	for (int y=0; y<120; y++)
494	388	for (int x=0; x<30; x++)
495	389	{
496		UINT8 data = 0;
	390	UINT8 data = m_bankdev0->space(AS_PROGRAM).read_byte((lcd_bank << 13) + y*30 + x);
497	391
498		if (mem_type == BANK_RAM)
499		{
500		data = (m_ram_base + ((lcd_bank & 0x03)<<13))[y*30 + x];
501		}
502		else
503		{
504		data =  m_flash[mem_type]->space(0).read_byte(((lcd_bank & 0x7f)<<13) | (y*30 + x));
505		}
506
507
508	392	for (int b=0; b<8; b++)
509	393	{
510	394	bitmap.pix16(y, (x * 8) + b) = BIT(data, 7);
r253597	r253598
570	454	QUICKLOAD_LOAD_MEMBER( rex6000_state,rex6000)
571	455	{
572	456	static const char magic[] = "ApplicationName:Addin";
573		address_space& flash = machine().device("flash0b")->memory().space(0);
	457	address_space& flash = m_flash0b->space(0);
574	458	UINT32 img_start = 0;
575	459
576	460	dynamic_buffer data(image.length());
r253597	r253598
661	545	MCFG_PALETTE_INIT_OWNER(rex6000_state, rex6000)
662	546	MCFG_GFXDECODE_ADD("gfxdecode", "palette", rex6000)
663	547
	548	MCFG_DEVICE_ADD("bank0", ADDRESS_MAP_BANK, 0)
	549	MCFG_DEVICE_PROGRAM_MAP(rex6000_banked_map)
	550	MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
	551	MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
	552	MCFG_ADDRESS_MAP_BANK_STRIDE(0x2000)
	553
	554	MCFG_DEVICE_ADD("bank1", ADDRESS_MAP_BANK, 0)
	555	MCFG_DEVICE_PROGRAM_MAP(rex6000_banked_map)
	556	MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
	557	MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
	558	MCFG_ADDRESS_MAP_BANK_STRIDE(0x2000)
	559
664	560	/* quickload */
665	561	MCFG_QUICKLOAD_ADD("quickload", rex6000_state, rex6000, "rex,ds2", 0)
666	562

trunk/src/mame/includes/avigo.h

r253597	r253598
14	14	#include "machine/rp5c01.h"
15	15	#include "machine/ins8250.h"
16	16	#include "machine/intelfsh.h"
	17	#include "machine/bankdev.h"
17	18	#include "machine/nvram.h"
18	19	#include "sound/speaker.h"
19	20	#include "machine/ram.h"
r253597	r253598
36	37	m_speaker(*this, "speaker"),
37	38	m_uart(*this, "ns16550"),
38	39	m_serport(*this, "serport"),
39		m_palette(*this, "palette")
	40	m_palette(*this, "palette"),
	41	m_bankdev1(*this, "bank0"),
	42	m_bankdev2(*this, "bank1"),
	43	m_flash1(*this, "flash1"),
	44	m_nvram(*this, "nvram")
40	45	{ }
41	46
42	47	required_device<cpu_device> m_maincpu;
r253597	r253598
45	50	required_device<ns16550_device> m_uart;
46	51	required_device<rs232_port_device> m_serport;
47	52	required_device<palette_device> m_palette;
	53	required_device<address_map_bank_device> m_bankdev1;
	54	required_device<address_map_bank_device> m_bankdev2;
	55	required_device<intelfsh8_device> m_flash1;
	56	required_shared_ptr<UINT8> m_nvram;
48	57
49	58	// defined in drivers/avigo.c
50	59	virtual void machine_start() override;
51	60	virtual void machine_reset() override;
52		void postload();
53		void refresh_memory(UINT8 bank, UINT8 chip_select);
54	61	void refresh_ints();
55	62	void nvram_init(nvram_device &nvram, void *base, size_t size);
56	63
57	64	DECLARE_WRITE_LINE_MEMBER( tc8521_alarm_int );
58	65	DECLARE_WRITE_LINE_MEMBER( com_interrupt );
59	66
60		DECLARE_READ8_MEMBER(flash_0x0000_read_handler);
61		DECLARE_WRITE8_MEMBER(flash_0x0000_write_handler);
62		DECLARE_READ8_MEMBER(flash_0x4000_read_handler);
63		DECLARE_WRITE8_MEMBER(flash_0x4000_write_handler);
64		DECLARE_READ8_MEMBER(flash_0x8000_read_handler);
65		DECLARE_WRITE8_MEMBER(flash_0x8000_write_handler);
66
67	67	DECLARE_READ8_MEMBER(key_data_read_r);
68	68	DECLARE_WRITE8_MEMBER(set_key_line_w);
69	69	DECLARE_WRITE8_MEMBER(port2_w);
r253597	r253598
99	99	UINT8               m_bank1_l;
100	100	UINT8               m_bank1_h;
101	101	UINT8               m_ad_control_status;
102		intelfsh8_device *  m_flashes[3];
103		int                 m_flash_at_0x4000;
104		int                 m_flash_at_0x8000;
105	102	UINT16              m_ad_value;
106	103	UINT8 *             m_video_memory;
107	104	UINT8               m_screen_column;
108	105	UINT8               m_warm_start;
109		UINT8 *             m_ram_base;
110	106	DECLARE_PALETTE_INIT(avigo);
111	107	TIMER_DEVICE_CALLBACK_MEMBER(avigo_scan_timer);
112	108	TIMER_DEVICE_CALLBACK_MEMBER(avigo_1hz_timer);

https://github.com/mamedev/mame/commit/2e6abeccfab9b165675308943e82ee5aeec76395

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