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r45072 Sunday 21st February, 2016 at 04:24:44 UTC by Carl
pc9801: some refactoring (nw)
mess: fix build (nw)
[src/mame]mess.cpp
[src/mame/drivers]pc9801.cpp

trunk/src/mame/drivers/pc9801.cpp
r253583r253584
536536
537537   /* PC9801RS specific */
538538   UINT8 m_gate_a20; //A20 line
539   UINT8 m_nmi_enable;
540539   UINT8 m_access_ctrl; // DMA related
541540   UINT8 m_rom_bank;
542541   UINT8 m_fdc_ctrl;
r253583r253584
584583   DECLARE_WRITE16_MEMBER(egc_w);
585584   DECLARE_READ8_MEMBER(pc9801_a0_r);
586585   DECLARE_WRITE8_MEMBER(pc9801_a0_w);
587   DECLARE_READ8_MEMBER(pc9801_fdc_2hd_r);
588   DECLARE_WRITE8_MEMBER(pc9801_fdc_2hd_w);
589   DECLARE_READ8_MEMBER(pc9801_fdc_2dd_r);
590   DECLARE_WRITE8_MEMBER(pc9801_fdc_2dd_w);
586   DECLARE_READ8_MEMBER(fdc_2hd_ctrl_r);
587   DECLARE_WRITE8_MEMBER(fdc_2hd_ctrl_w);
588   DECLARE_READ8_MEMBER(fdc_2dd_ctrl_r);
589   DECLARE_WRITE8_MEMBER(fdc_2dd_ctrl_w);
591590   DECLARE_READ16_MEMBER(tvram_r);
592591   DECLARE_WRITE16_MEMBER(tvram_w);
593592   DECLARE_READ8_MEMBER(gvram_r);
r253583r253584
602601   DECLARE_WRITE16_MEMBER(upd7220_grcg_w);
603602   void egc_blit_w(UINT32 offset, UINT16 data, UINT16 mem_mask);
604603   UINT16 egc_blit_r(UINT32 offset, UINT16 mem_mask);
605   UINT32 pc9801_286_a20(bool state);
604   UINT32 a20_286(bool state);
606605
607606   DECLARE_READ8_MEMBER(ide_ctrl_r);
608607   DECLARE_WRITE8_MEMBER(ide_ctrl_w);
r253583r253584
633632   DECLARE_WRITE8_MEMBER(pc9801rs_bank_w);
634633   DECLARE_READ8_MEMBER(a20_ctrl_r);
635634   DECLARE_WRITE8_MEMBER(a20_ctrl_w);
636   DECLARE_READ8_MEMBER(pc9810rs_fdc_ctrl_r);
637   DECLARE_WRITE8_MEMBER(pc9810rs_fdc_ctrl_w);
638   DECLARE_READ8_MEMBER(pc9801rs_2hd_r);
639   DECLARE_WRITE8_MEMBER(pc9801rs_2hd_w);
635   DECLARE_READ8_MEMBER(fdc_mode_ctrl_r);
636   DECLARE_WRITE8_MEMBER(fdc_mode_ctrl_w);
640637//  DECLARE_READ8_MEMBER(pc9801rs_2dd_r);
641638//  DECLARE_WRITE8_MEMBER(pc9801rs_2dd_w);
642639   DECLARE_WRITE8_MEMBER(pc9801rs_video_ff_w);
r253583r253584
644641   DECLARE_WRITE8_MEMBER(pc9821_video_ff_w);
645642   DECLARE_READ8_MEMBER(pc9821_a0_r);
646643   DECLARE_WRITE8_MEMBER(pc9821_a0_w);
647   DECLARE_READ8_MEMBER(pc9801rs_access_ctrl_r);
648   DECLARE_WRITE8_MEMBER(pc9801rs_access_ctrl_w);
649   DECLARE_WRITE8_MEMBER(pc9801rs_nmi_w);
650   DECLARE_READ8_MEMBER(pc9801rs_midi_r);
644   DECLARE_READ8_MEMBER(access_ctrl_r);
645   DECLARE_WRITE8_MEMBER(access_ctrl_w);
646   DECLARE_READ8_MEMBER(midi_r);
651647//  DECLARE_READ8_MEMBER(winram_r);
652648//  DECLARE_WRITE8_MEMBER(winram_w);
653649//  DECLARE_READ8_MEMBER(pc9801_ext_opna_r);
r253583r253584
681677   DECLARE_WRITE8_MEMBER(sdip_a_w);
682678   DECLARE_WRITE8_MEMBER(sdip_b_w);
683679
684   DECLARE_READ8_MEMBER(pc9821_window_bank_r);
685   DECLARE_WRITE8_MEMBER(pc9821_window_bank_w);
686   DECLARE_READ16_MEMBER(pc9821_timestamp_r);
687   DECLARE_READ8_MEMBER(pc9821_ext2_video_ff_r);
688   DECLARE_WRITE8_MEMBER(pc9821_ext2_video_ff_w);
680   DECLARE_READ8_MEMBER(window_bank_r);
681   DECLARE_WRITE8_MEMBER(window_bank_w);
682   DECLARE_READ16_MEMBER(timestamp_r);
683   DECLARE_READ8_MEMBER(ext2_video_ff_r);
684   DECLARE_WRITE8_MEMBER(ext2_video_ff_w);
689685
690686   DECLARE_FLOPPY_FORMATS( floppy_formats );
691687   UPD7220_DISPLAY_PIXELS_MEMBER( hgdc_display_pixels );
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709705   DECLARE_MACHINE_RESET(pc9821);
710706
711707   DECLARE_PALETTE_INIT(pc9801);
712   INTERRUPT_GEN_MEMBER(pc9801_vrtc_irq);
708   INTERRUPT_GEN_MEMBER(vrtc_irq);
713709   DECLARE_READ8_MEMBER(get_slave_ack);
714710   DECLARE_WRITE_LINE_MEMBER(dma_hrq_changed);
715711   DECLARE_WRITE_LINE_MEMBER(tc_w);
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12001196   m_sio->write_rxc(state);
12011197}
12021198
1203READ8_MEMBER(pc9801_state::pc9801_fdc_2hd_r)
1199READ8_MEMBER(pc9801_state::fdc_2hd_ctrl_r)
12041200{
1205   if((offset & 1) == 0)
1206   {
1207      switch(offset & 6)
1208      {
1209         case 0: return m_fdc_2hd->msr_r(space, 0, 0xff);
1210         case 2: return m_fdc_2hd->fifo_r(space, 0, 0xff);
1211         case 4: return 0x5f; //unknown port meaning
1212      }
1213   }
1214   else
1215   {
1216      switch((offset & 6) + 1)
1217      {
1218         case 1: return m_sio->data_r(space, 0);
1219         case 3: return m_sio->status_r(space, 0);
1220      }
1221      logerror("Read to undefined port [%02x]\n",offset+0x90);
1222      return 0xff;
1223   }
1224
1225   return 0xff;
1201   return 0x44; //unknown port meaning 2hd flag?
12261202}
12271203
1228WRITE8_MEMBER(pc9801_state::pc9801_fdc_2hd_w)
1204WRITE8_MEMBER(pc9801_state::fdc_2hd_ctrl_w)
12291205{
1230   if((offset & 1) == 0)
1231   {
1232      switch(offset & 6)
1233      {
1234         case 0: logerror("Write to undefined port [%02x] <- %02x\n",offset+0x90,data); return;
1235         case 2: m_fdc_2hd->fifo_w(space, 0, data, 0xff); return;
1236         case 4:
1237            //logerror("%02x ctrl\n",data);
1238            if(((m_fdc_2hd_ctrl & 0x80) == 0) && (data & 0x80))
1239               m_fdc_2hd->soft_reset();
1206   //logerror("%02x ctrl\n",data);
1207   if(((m_fdc_2hd_ctrl & 0x80) == 0) && (data & 0x80))
1208      m_fdc_2hd->soft_reset();
12401209
1241            m_fdc_2hd_ctrl = data;
1210   m_fdc_2hd_ctrl = data;
12421211
1243            if(data & 0x40)
1244            {
1245               m_fdc_2hd->set_ready_line_connected(0);
1246               m_fdc_2hd->ready_w(0);
1247            }
1248            else
1249               m_fdc_2hd->set_ready_line_connected(1);
1250
1251            // TODO: is the motor control bit really inverted relative to the other fdcs?
1252            m_fdc_2hd->subdevice<floppy_connector>("0")->get_device()->mon_w(data & 8 ? ASSERT_LINE : CLEAR_LINE);
1253            m_fdc_2hd->subdevice<floppy_connector>("1")->get_device()->mon_w(data & 8 ? ASSERT_LINE : CLEAR_LINE);
1254            break;
1255      }
1256   }
1257   else
1212   if(data & 0x40)
12581213   {
1259      switch((offset & 6) + 1)
1260      {
1261         case 1: m_sio->data_w(space, 0, data); return;
1262         case 3: m_sio->control_w(space, 0, data); return;
1263      }
1264      logerror("Write to undefined port [%02x] <- %02x\n",offset+0x90,data);
1214      m_fdc_2hd->set_ready_line_connected(0);
1215      m_fdc_2hd->ready_w(0);
12651216   }
1266}
1217   else
1218      m_fdc_2hd->set_ready_line_connected(1);
12671219
1268
1269READ8_MEMBER(pc9801_state::pc9801_fdc_2dd_r)
1270{
1271   if((offset & 1) == 0)
1220   if(!m_sys_type) // required for 9801f 2hd adapter bios
12721221   {
1273      switch(offset & 6)
1274      {
1275         case 0: return m_fdc_2dd->msr_r(space, 0, 0xff);
1276         case 2: return m_fdc_2dd->fifo_r(space, 0, 0xff);
1277         case 4:
1278         {
1279            int ret = (!m_fdc_2dd->subdevice<floppy_connector>("0")->get_device()->ready_r()) ? 0x10 : 0;
1280            ret |= (m_fdc_2dd->subdevice<floppy_connector>("1")->get_device()->ready_r()) ? 0x10 : 0;
1281            return ret | 0x40; //unknown port meaning, might be 0x70
1282         }
1283      }
1222      m_fdc_2hd->subdevice<floppy_connector>("0")->get_device()->mon_w(data & 8 ? ASSERT_LINE : CLEAR_LINE);
1223      m_fdc_2hd->subdevice<floppy_connector>("1")->get_device()->mon_w(data & 8 ? ASSERT_LINE : CLEAR_LINE);
12841224   }
1285   else
1225   else if(!(m_fdc_ctrl & 4)) // required for 9821
12861226   {
1287      logerror("Read to undefined port [%02x]\n",offset+0xc8);
1288      return 0xff;
1227      m_fdc_2hd->subdevice<floppy_connector>("0")->get_device()->mon_w(data & 8 ? CLEAR_LINE : ASSERT_LINE);
1228      m_fdc_2hd->subdevice<floppy_connector>("1")->get_device()->mon_w(data & 8 ? CLEAR_LINE : ASSERT_LINE);
12891229   }
1230}
12901231
1291   return 0xff;
1232
1233READ8_MEMBER(pc9801_state::fdc_2dd_ctrl_r)
1234{
1235      int ret = (!m_fdc_2dd->subdevice<floppy_connector>("0")->get_device()->ready_r()) ? 0x10 : 0;
1236      ret |= (m_fdc_2dd->subdevice<floppy_connector>("1")->get_device()->ready_r()) ? 0x10 : 0;
1237      return ret | 0x40; //unknown port meaning, might be 0x70
12921238}
12931239
1294WRITE8_MEMBER(pc9801_state::pc9801_fdc_2dd_w)
1240WRITE8_MEMBER(pc9801_state::fdc_2dd_ctrl_w)
12951241{
1296   if((offset & 1) == 0)
1297   {
1298      switch(offset & 6)
1299      {
1300         case 0: logerror("Write to undefined port [%02x] <- %02x\n",offset+0xc8,data); return;
1301         case 2: m_fdc_2dd->fifo_w(space, 0, data, 0xff); return;
1302         case 4:
1303            logerror("%02x ctrl\n",data);
1304            if(((m_fdc_2dd_ctrl & 0x80) == 0) && (data & 0x80))
1305               m_fdc_2dd->soft_reset();
1242      logerror("%02x ctrl\n",data);
1243      if(((m_fdc_2dd_ctrl & 0x80) == 0) && (data & 0x80))
1244         m_fdc_2dd->soft_reset();
13061245
1307            m_fdc_2dd_ctrl = data;
1308            m_fdc_2dd->subdevice<floppy_connector>("0")->get_device()->mon_w(data & 8 ? CLEAR_LINE : ASSERT_LINE);
1309            m_fdc_2dd->subdevice<floppy_connector>("1")->get_device()->mon_w(data & 8 ? CLEAR_LINE : ASSERT_LINE);
1310            break;
1311      }
1312   }
1313   else
1314   {
1315      logerror("Write to undefined port [%02x] <- %02x\n",offset+0xc8,data);
1316   }
1246      m_fdc_2dd_ctrl = data;
1247      m_fdc_2dd->subdevice<floppy_connector>("0")->get_device()->mon_w(data & 8 ? CLEAR_LINE : ASSERT_LINE);
1248      m_fdc_2dd->subdevice<floppy_connector>("1")->get_device()->mon_w(data & 8 ? CLEAR_LINE : ASSERT_LINE);
13171249}
13181250
13191251
r253583r253584
14301362   }
14311363
14321364   // mask off the bits past the end of the blit
1433   if((m_egc.count < 8) && (mem_mask != 0xffff))
1365   if(((m_egc.count < 8) && (mem_mask != 0xffff)) || ((m_egc.count < 16) && (mem_mask == 0xffff)))
14341366   {
1435      UINT16 end_mask = dir ? ((1 << m_egc.count) - 1) : ~((1 << (8 - m_egc.count)) - 1);
1436      // if the blit is less than 8 bits, adjust the masks
1437      if(m_egc.first)
1438      {
1439         if(dir)
1440            end_mask <<= dst_off & 7;
1441         else
1442            end_mask >>= dst_off & 7;
1443      }
1444      mask &= end_mask;
1445   }
1446   else if((m_egc.count < 16) && (mem_mask == 0xffff))
1447   {
14481367      UINT16 end_mask = dir ? ((1 << m_egc.count) - 1) : ~((1 << (16 - m_egc.count)) - 1);
1449      // if the blit is less than 16 bits, adjust the masks
1368      // if the blit is less than the write size, adjust the masks
14501369      if(m_egc.first)
14511370      {
14521371         if(dir)
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14611380   {
14621381      if(!BIT(m_egc.regs[0], i))
14631382      {
1464         UINT16 src = m_egc.src[i] & mem_mask, pat = m_egc.pat[i];
1383         UINT16 src = m_egc.src[i], pat = m_egc.pat[i];
14651384         if(BIT(m_egc.regs[2], 10))
14661385            src = egc_shift(i, data);
14671386
r253583r253584
17821701ADDRESS_MAP_END
17831702
17841703/* first device is even offsets, second one is odd offsets */
1785static ADDRESS_MAP_START( pc9801_io, AS_IO, 16, pc9801_state )
1704static ADDRESS_MAP_START( pc9801_common_io, AS_IO, 16, pc9801_state )
17861705   ADDRESS_MAP_UNMAP_HIGH
17871706   AM_RANGE(0x0000, 0x001f) AM_DEVREADWRITE8("i8237", am9517a_device, read, write, 0xff00)
17881707   AM_RANGE(0x0000, 0x000f) AM_READWRITE8(pic_r, pic_w, 0x00ff) // i8259 PIC (bit 3 ON slave / master) / i8237 DMA
17891708   AM_RANGE(0x0020, 0x0021) AM_WRITE8(rtc_w,0x00ff)
1790   AM_RANGE(0x0020, 0x0027) AM_WRITE8(dmapg4_w,0xff00)
17911709   AM_RANGE(0x0030, 0x0037) AM_DEVREADWRITE8("ppi8255_sys", i8255_device, read, write, 0xff00) //i8251 RS232c / i8255 system port
17921710   AM_RANGE(0x0040, 0x0047) AM_DEVREADWRITE8("ppi8255_prn", i8255_device, read, write, 0x00ff)
17931711   AM_RANGE(0x0040, 0x0043) AM_DEVREADWRITE8("keyb", pc9801_kbd_device, rx_r, tx_w, 0xff00) //i8255 printer port / i8251 keyboard
r253583r253584
17951713   AM_RANGE(0x0050, 0x0053) AM_WRITE8(nmi_ctrl_w,0x00ff) // NMI FF / i8255 floppy port (2d?)
17961714   AM_RANGE(0x0060, 0x0063) AM_DEVREADWRITE8("upd7220_chr", upd7220_device, read, write, 0x00ff) //upd7220 character ports / <undefined>
17971715   AM_RANGE(0x0064, 0x0065) AM_WRITE8(vrtc_clear_w,0x00ff)
1798   AM_RANGE(0x0068, 0x0069) AM_WRITE8(pc9801_video_ff_w,0x00ff) //mode FF / <undefined>
17991716//  AM_RANGE(0x006c, 0x006f) border color / <undefined>
18001717   AM_RANGE(0x0070, 0x007f) AM_DEVREADWRITE8("pit8253", pit8253_device, read, write, 0xff00)
18011718   AM_RANGE(0x0070, 0x007b) AM_READWRITE8(txt_scrl_r,txt_scrl_w,0x00ff) //display registers / i8253 pit
18021719   AM_RANGE(0x0080, 0x0081) AM_READWRITE8(sasi_data_r, sasi_data_w, 0x00ff)
18031720   AM_RANGE(0x0082, 0x0083) AM_READWRITE8(sasi_status_r, sasi_ctrl_w,0x00ff)
1804   AM_RANGE(0x0090, 0x0097) AM_READWRITE8(pc9801_fdc_2hd_r,pc9801_fdc_2hd_w,0xffff) //upd765a 2hd / cmt
1805   AM_RANGE(0x00a0, 0x00af) AM_READWRITE8(pc9801_a0_r,pc9801_a0_w,0xffff) //upd7220 bitmap ports / display registers
1806   AM_RANGE(0x00c8, 0x00cd) AM_READWRITE8(pc9801_fdc_2dd_r,pc9801_fdc_2dd_w,0xffff) //upd765a 2dd / <undefined>
1807//  AM_RANGE(0x0188, 0x018b) AM_READWRITE8(pc9801_opn_r,pc9801_opn_w,0xffff) //ym2203 opn / <undefined>
1721   AM_RANGE(0x0090, 0x0091) AM_DEVREAD8("upd765_2hd", upd765a_device, msr_r, 0x00ff)
1722   AM_RANGE(0x0092, 0x0093) AM_DEVREADWRITE8("upd765_2hd", upd765a_device, fifo_r, fifo_w, 0x00ff)
1723   AM_RANGE(0x0094, 0x0095) AM_READWRITE8(fdc_2hd_ctrl_r, fdc_2hd_ctrl_w, 0x00ff)
1724   AM_RANGE(0x0090, 0x0091) AM_DEVREADWRITE8(UPD8251_TAG, i8251_device, data_r, data_w, 0xff00)
1725   AM_RANGE(0x0092, 0x0093) AM_DEVREADWRITE8(UPD8251_TAG, i8251_device, status_r, control_w, 0xff00)
18081726   AM_RANGE(0x7fd8, 0x7fdf) AM_DEVREADWRITE8("ppi8255_mouse", i8255_device, read, write, 0xff00)
18091727ADDRESS_MAP_END
18101728
1729static ADDRESS_MAP_START( pc9801_io, AS_IO, 16, pc9801_state )
1730   AM_RANGE(0x0020, 0x0027) AM_WRITE8(dmapg4_w,0xff00)
1731   AM_RANGE(0x0068, 0x0069) AM_WRITE8(pc9801_video_ff_w,0x00ff) //mode FF / <undefined>
1732   AM_RANGE(0x00a0, 0x00af) AM_READWRITE8(pc9801_a0_r,pc9801_a0_w,0xffff) //upd7220 bitmap ports / display registers
1733   AM_RANGE(0x00c8, 0x00cb) AM_DEVICE8("upd765_2dd", upd765a_device, map, 0x00ff)
1734   AM_RANGE(0x00cc, 0x00cd) AM_READWRITE8(fdc_2dd_ctrl_r, fdc_2dd_ctrl_w, 0x00ff) //upd765a 2dd / <undefined>
1735   AM_IMPORT_FROM(pc9801_common_io)
1736ADDRESS_MAP_END
1737
1738
18111739/*************************************
18121740 *
18131741 * PC-9801RS specific handlers (IA-32)
r253583r253584
18901818   if(offset == 0x01)
18911819      return (m_gate_a20 ^ 1) | 0xfe;
18921820   else if(offset == 0x03)
1893      return (m_gate_a20 ^ 1) | (m_nmi_enable << 1);
1821      return (m_gate_a20 ^ 1) | (m_nmi_ff << 1);
18941822
18951823   return 0x00;
18961824}
r253583r253584
19991927   }
20001928}
20011929
2002READ8_MEMBER(pc9801_state::pc9810rs_fdc_ctrl_r)
1930READ8_MEMBER(pc9801_state::fdc_mode_ctrl_r)
20031931{
20041932   return (m_fdc_ctrl & 3) | 0xf0 | 8 | 4;
20051933}
20061934
2007WRITE8_MEMBER(pc9801_state::pc9810rs_fdc_ctrl_w)
1935WRITE8_MEMBER(pc9801_state::fdc_mode_ctrl_w)
20081936{
20091937   /*
20101938   ---- x--- ready line?
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20221950   //  logerror("FDC ctrl called with %02x\n",data);
20231951}
20241952
2025READ8_MEMBER(pc9801_state::pc9801rs_2hd_r)
2026{
2027   if((offset & 1) == 0)
2028   {
2029      switch(offset & 6)
2030      {
2031         case 0: return m_fdc_2hd->msr_r(space, 0, 0xff);
2032         case 2: return m_fdc_2hd->fifo_r(space, 0, 0xff);
2033         case 4: return 0x44; //2hd flag
2034      }
2035   }
2036
2037   logerror("Read to undefined port [%02x]\n",offset+0x90);
2038
2039   return 0xff;
2040}
2041
2042WRITE8_MEMBER(pc9801_state::pc9801rs_2hd_w)
2043{
2044   if((offset & 1) == 0)
2045   {
2046      switch(offset & 6)
2047      {
2048         case 2: m_fdc_2hd->fifo_w(space, 0, data, 0xff); return;
2049         case 4:
2050            if(data & 0x80)
2051               m_fdc_2hd->soft_reset();
2052
2053            if(data & 0x40)
2054            {
2055               m_fdc_2hd->set_ready_line_connected(0);
2056               m_fdc_2hd->ready_w(0);
2057            }
2058            else
2059               m_fdc_2hd->set_ready_line_connected(1);
2060
2061            //TODO: verify
2062            if(!(m_fdc_ctrl & 4))
2063            {
2064               m_fdc_2hd->subdevice<floppy_connector>("0")->get_device()->mon_w(data & 8 ? CLEAR_LINE : ASSERT_LINE);
2065               m_fdc_2hd->subdevice<floppy_connector>("1")->get_device()->mon_w(data & 8 ? CLEAR_LINE : ASSERT_LINE);
2066            }
2067            return;
2068      }
2069   }
2070
2071   logerror("Write to undefined port [%02x] %02x\n",offset+0x90,data);
2072}
2073
20741953#if 0
20751954READ8_MEMBER(pc9801_state::pc9801rs_2dd_r)
20761955{
r253583r253584
21602039   pc9801_a0_w(space,offset,data);
21612040}
21622041
2163READ8_MEMBER( pc9801_state::pc9801rs_access_ctrl_r )
2042READ8_MEMBER( pc9801_state::access_ctrl_r )
21642043{
21652044   if(offset == 1)
21662045      return m_access_ctrl;
r253583r253584
21682047   return 0xff;
21692048}
21702049
2171WRITE8_MEMBER( pc9801_state::pc9801rs_access_ctrl_w )
2050WRITE8_MEMBER( pc9801_state::access_ctrl_w )
21722051{
21732052   if(offset == 1)
21742053      m_access_ctrl = data;
r253583r253584
21842063   }
21852064}
21862065
2187
2188WRITE8_MEMBER( pc9801_state::pc9801rs_nmi_w )
2066READ8_MEMBER( pc9801_state::midi_r )
21892067{
2190   if(offset == 0)
2191      m_nmi_enable = 0;
2192
2193   if(offset == 2)
2194      m_nmi_enable = 1;
2195}
2196
2197READ8_MEMBER( pc9801_state::pc9801rs_midi_r )
2198{
21992068   /* unconnect, needed by Amaranth KH to boot */
22002069   return 0xff;
22012070}
r253583r253584
22472116   ADDRESS_MAP_UNMAP_HIGH
22482117   AM_RANGE(0x0020, 0x002f) AM_WRITE8(dmapg8_w,0xff00)
22492118   AM_RANGE(0x0050, 0x0057) AM_NOP // 2dd ppi?
2250   AM_RANGE(0x005c, 0x005f) AM_READ(pc9821_timestamp_r) AM_WRITENOP // artic
2119   AM_RANGE(0x005c, 0x005f) AM_READ(timestamp_r) AM_WRITENOP // artic
22512120   AM_RANGE(0x0068, 0x006b) AM_WRITE8(pc9801rs_video_ff_w,0x00ff) //mode FF / <undefined>
22522121   AM_RANGE(0x0070, 0x007f) AM_READWRITE8(grcg_r,      grcg_w,      0x00ff) //display registers "GRCG" / i8253 pit
2253   AM_RANGE(0x0090, 0x0097) AM_READWRITE8(pc9801rs_2hd_r,     pc9801rs_2hd_w,     0xffff)
22542122   AM_RANGE(0x00a0, 0x00af) AM_READWRITE8(pc9801_a0_r,        pc9801rs_a0_w,      0xffff) //upd7220 bitmap ports / display registers
2255   AM_RANGE(0x00bc, 0x00bf) AM_READWRITE8(pc9810rs_fdc_ctrl_r,pc9810rs_fdc_ctrl_w,0xffff)
2256   AM_RANGE(0x00c8, 0x00cf) AM_READWRITE8(pc9801rs_2hd_r,     pc9801rs_2hd_w,     0xffff)
2123   AM_RANGE(0x00bc, 0x00bf) AM_READWRITE8(fdc_mode_ctrl_r,fdc_mode_ctrl_w,0xffff)
2124   AM_RANGE(0x00c8, 0x00cb) AM_DEVICE8("upd765_2hd", upd765a_device, map, 0x00ff)
2125   AM_RANGE(0x00cc, 0x00cd) AM_READWRITE8(fdc_2hd_ctrl_r, fdc_2hd_ctrl_w, 0x00ff)
22572126   AM_RANGE(0x00f0, 0x00ff) AM_READWRITE8(a20_ctrl_r,      a20_ctrl_w,      0x00ff)
2258   AM_RANGE(0x0438, 0x043b) AM_READWRITE8(pc9801rs_access_ctrl_r,pc9801rs_access_ctrl_w,0xffff)
2259   AM_RANGE(0x043c, 0x043f) AM_WRITE8(pc9801rs_bank_w,    0xffff) //ROM/RAM bank
2127   AM_RANGE(0x0438, 0x043b) AM_READWRITE8(access_ctrl_r,access_ctrl_w,0xffff)
2128   AM_RANGE(0x043c, 0x043f) AM_WRITE8(pc9801rs_bank_w, 0xffff) //ROM/RAM bank
22602129   AM_RANGE(0x04a0, 0x04af) AM_WRITE(egc_w)
22612130   AM_RANGE(0x3fd8, 0x3fdf) AM_DEVREADWRITE8("pit8253", pit8253_device, read, write, 0xff00)
2262//  AM_RANGE(0xa460, 0xa463) AM_READWRITE8(pc9801_ext_opna_r,  pc9801_ext_opna_w,  0xffff)
2263   AM_IMPORT_FROM(pc9801_io)
2131   AM_IMPORT_FROM(pc9801_common_io)
22642132ADDRESS_MAP_END
22652133
22662134static ADDRESS_MAP_START( pc9801rs_map, AS_PROGRAM, 16, pc9801_state )
r253583r253584
22732141
22742142static ADDRESS_MAP_START( pc9801rs_io, AS_IO, 16, pc9801_state )
22752143   ADDRESS_MAP_UNMAP_HIGH
2276   AM_RANGE(0x0050, 0x0053) AM_WRITE8(pc9801rs_nmi_w, 0xffff)
22772144   AM_RANGE(0x0430, 0x0433) AM_READWRITE8(ide_ctrl_r, ide_ctrl_w, 0x00ff)
22782145   AM_RANGE(0x0640, 0x064f) AM_READWRITE(ide_cs0_r, ide_cs0_w)
22792146   AM_RANGE(0x0740, 0x074f) AM_READWRITE(ide_cs1_r, ide_cs1_w)
22802147   AM_RANGE(0x1e8c, 0x1e8f) AM_NOP // temp
22812148   AM_RANGE(0xbfd8, 0xbfdf) AM_WRITE8(pc9801rs_mouse_freq_w, 0xffff)
2282   AM_RANGE(0xe0d0, 0xe0d3) AM_READ8(pc9801rs_midi_r, 0xffff)
2149   AM_RANGE(0xe0d0, 0xe0d3) AM_READ8(midi_r, 0xffff)
22832150   AM_IMPORT_FROM(pc9801ux_io)
22842151ADDRESS_MAP_END
22852152
r253583r253584
23552222   pc9801rs_a0_w(space,offset,data);
23562223}
23572224
2358READ8_MEMBER(pc9801_state::pc9821_window_bank_r)
2225READ8_MEMBER(pc9801_state::window_bank_r)
23592226{
23602227   if(offset == 1)
23612228      return m_pc9821_window_bank & 0xfe;
r253583r253584
23632230   return 0xff;
23642231}
23652232
2366WRITE8_MEMBER(pc9801_state::pc9821_window_bank_w)
2233WRITE8_MEMBER(pc9801_state::window_bank_w)
23672234{
23682235   if(offset == 1)
23692236      m_pc9821_window_bank = data & 0xfe;
r253583r253584
24272294      logerror("SDIP area B write %02x %02x\n",offset,data);
24282295}
24292296
2430READ16_MEMBER(pc9801_state::pc9821_timestamp_r)
2297READ16_MEMBER(pc9801_state::timestamp_r)
24312298{
24322299   return (m_maincpu->total_cycles() >> (16 * offset));
24332300}
24342301
24352302/* basically a read-back of various registers */
2436READ8_MEMBER(pc9801_state::pc9821_ext2_video_ff_r)
2303READ8_MEMBER(pc9801_state::ext2_video_ff_r)
24372304{
24382305   UINT8 res;
24392306
r253583r253584
24492316   return res;
24502317}
24512318
2452WRITE8_MEMBER(pc9801_state::pc9821_ext2_video_ff_w)
2319WRITE8_MEMBER(pc9801_state::ext2_video_ff_w)
24532320{
24542321   m_ext2_ff = data;
24552322}
r253583r253584
24912358   AM_RANGE(0x0030, 0x0037) AM_DEVREADWRITE8("ppi8255_sys", i8255_device, read, write, 0xff00ff00) //i8251 RS232c / i8255 system port
24922359   AM_RANGE(0x0040, 0x0047) AM_DEVREADWRITE8("ppi8255_prn", i8255_device, read, write, 0x00ff00ff)
24932360   AM_RANGE(0x0040, 0x0043) AM_DEVREADWRITE8("keyb", pc9801_kbd_device, rx_r, tx_w, 0xff00ff00) //i8255 printer port / i8251 keyboard
2494   AM_RANGE(0x0050, 0x0053) AM_WRITE8(pc9801rs_nmi_w, 0xffffffff)
2495   AM_RANGE(0x005c, 0x005f) AM_READ16(pc9821_timestamp_r,0xffffffff) AM_WRITENOP // artic
2361   AM_RANGE(0x0050, 0x0053) AM_WRITE8(nmi_ctrl_w, 0x00ff00ff)
2362   AM_RANGE(0x005c, 0x005f) AM_READ16(timestamp_r,0xffffffff) AM_WRITENOP // artic
24962363   AM_RANGE(0x0060, 0x0063) AM_DEVREADWRITE8("upd7220_chr", upd7220_device, read, write, 0x00ff00ff) //upd7220 character ports / <undefined>
24972364   AM_RANGE(0x0060, 0x0063) AM_READ8(unk_r, 0xff00ff00) // mouse related (unmapped checking for AT keyb controller\PS/2 mouse?)
24982365   AM_RANGE(0x0064, 0x0067) AM_WRITE8(vrtc_clear_w, 0x000000ff)
24992366   AM_RANGE(0x0068, 0x006b) AM_WRITE8(pc9821_video_ff_w,  0x00ff00ff) //mode FF / <undefined>
25002367   AM_RANGE(0x0070, 0x007f) AM_DEVREADWRITE8("pit8253", pit8253_device, read, write, 0xff00ff00)
25012368   AM_RANGE(0x0070, 0x007f) AM_READWRITE8(grcg_r,      grcg_w,      0x00ff00ff) //display registers "GRCG" / i8253 pit
2502   AM_RANGE(0x0090, 0x0097) AM_READWRITE8(pc9801rs_2hd_r,     pc9801rs_2hd_w,     0xffffffff)
2369   AM_RANGE(0x0090, 0x0093) AM_DEVICE8("upd765_2hd", upd765a_device, map, 0x00ff00ff)
2370   AM_RANGE(0x0094, 0x0097) AM_READWRITE8(fdc_2hd_ctrl_r, fdc_2hd_ctrl_w, 0x000000ff)
25032371   AM_RANGE(0x00a0, 0x00af) AM_READWRITE8(pc9821_a0_r,        pc9821_a0_w,        0xffffffff) //upd7220 bitmap ports / display registers
25042372//  AM_RANGE(0x00b0, 0x00b3) PC9861k (serial port?)
25052373//  AM_RANGE(0x00b9, 0x00b9) PC9861k
25062374//  AM_RANGE(0x00bb, 0x00bb) PC9861k
2507   AM_RANGE(0x00bc, 0x00bf) AM_READWRITE8(pc9810rs_fdc_ctrl_r,pc9810rs_fdc_ctrl_w,0xffffffff)
2508   AM_RANGE(0x00c8, 0x00cf) AM_READWRITE8(pc9801rs_2hd_r,     pc9801rs_2hd_w,     0xffffffff)
2509//  AM_RANGE(0x00d8, 0x00df) AMD98 (sound?) board
2375   AM_RANGE(0x00bc, 0x00bf) AM_READWRITE8(fdc_mode_ctrl_r,fdc_mode_ctrl_w,0xffffffff)
2376   AM_RANGE(0x00c8, 0x00cb) AM_DEVICE8("upd765_2hd", upd765a_device, map, 0x00ff00ff)
2377   AM_RANGE(0x00cc, 0x00cf) AM_READWRITE8(fdc_2hd_ctrl_r, fdc_2hd_ctrl_w, 0x000000ff)
2378   //  AM_RANGE(0x00d8, 0x00df) AMD98 (sound?) board
25102379   AM_RANGE(0x00f0, 0x00ff) AM_READWRITE8(a20_ctrl_r,      a20_ctrl_w,      0x00ff00ff)
25112380//  AM_RANGE(0x0188, 0x018f) AM_READWRITE8(pc9801_opn_r,       pc9801_opn_w,       0xffffffff) //ym2203 opn / <undefined>
25122381//  AM_RANGE(0x018c, 0x018f) YM2203 OPN extended ports / <undefined>
25132382   AM_RANGE(0x0430, 0x0433) AM_READWRITE8(ide_ctrl_r, ide_ctrl_w, 0x00ff00ff)
2514   AM_RANGE(0x0438, 0x043b) AM_READWRITE8(pc9801rs_access_ctrl_r,pc9801rs_access_ctrl_w,0xffffffff)
2383   AM_RANGE(0x0438, 0x043b) AM_READWRITE8(access_ctrl_r,access_ctrl_w,0xffffffff)
25152384//  AM_RANGE(0x043d, 0x043d) ROM/RAM bank (NEC)
25162385   AM_RANGE(0x043c, 0x043f) AM_WRITE8(pc9801rs_bank_w,    0xffffffff) //ROM/RAM bank (EPSON)
2517   AM_RANGE(0x0460, 0x0463) AM_READWRITE8(pc9821_window_bank_r,pc9821_window_bank_w, 0xffffffff)
2386   AM_RANGE(0x0460, 0x0463) AM_READWRITE8(window_bank_r,window_bank_w, 0xffffffff)
25182387   AM_RANGE(0x04a0, 0x04af) AM_WRITE16(egc_w, 0xffffffff)
25192388//  AM_RANGE(0x04be, 0x04be) FDC "RPM" register
25202389   AM_RANGE(0x0640, 0x064f) AM_READWRITE16(ide_cs0_r, ide_cs0_w, 0xffffffff)
25212390   AM_RANGE(0x0740, 0x074f) AM_READWRITE16(ide_cs1_r, ide_cs1_w, 0xffffffff)
25222391//  AM_RANGE(0x08e0, 0x08ea) <undefined> / EMM SIO registers
2523   AM_RANGE(0x09a0, 0x09a3) AM_READWRITE8(pc9821_ext2_video_ff_r, pc9821_ext2_video_ff_w, 0x000000ff) // GDC extended register r/w
2392   AM_RANGE(0x09a0, 0x09a3) AM_READWRITE8(ext2_video_ff_r, ext2_video_ff_w, 0x000000ff) // GDC extended register r/w
25242393//  AM_RANGE(0x09a8, 0x09a8) GDC 31KHz register r/w
25252394//  AM_RANGE(0x0c07, 0x0c07) EPSON register w
25262395//  AM_RANGE(0x0c03, 0x0c03) EPSON register 0 r
r253583r253584
25452414   AM_RANGE(0x8d1c, 0x8d1f) AM_READWRITE8(sdip_9_r,sdip_9_w,0xffffffff)
25462415   AM_RANGE(0x8e1c, 0x8e1f) AM_READWRITE8(sdip_a_r,sdip_a_w,0xffffffff)
25472416   AM_RANGE(0x8f1c, 0x8f1f) AM_READWRITE8(sdip_b_r,sdip_b_w,0xffffffff)
2548//  AM_RANGE(0xa460, 0xa463) AM_READWRITE8(pc9801_ext_opna_r,  pc9801_ext_opna_w,  0xffffffff)
25492417//  AM_RANGE(0xa460, 0xa46f) cs4231 PCM extended port / <undefined>
25502418//  AM_RANGE(0xbfdb, 0xbfdb) mouse timing port
25512419//  AM_RANGE(0xc0d0, 0xc0d3) MIDI port, option 0 / <undefined>
r253583r253584
25562424//  AM_RANGE(0xd4d0, 0xd4d3) MIDI port, option 5 / <undefined>
25572425//  AM_RANGE(0xd8d0, 0xd8d3) MIDI port, option 6 / <undefined>
25582426//  AM_RANGE(0xdcd0, 0xdcd3) MIDI port, option 7 / <undefined>
2559   AM_RANGE(0xe0d0, 0xe0d3) AM_READ8(pc9801rs_midi_r, 0xffffffff) // MIDI port, option 8 / <undefined>
2427   AM_RANGE(0xe0d0, 0xe0d3) AM_READ8(midi_r, 0xffffffff) // MIDI port, option 8 / <undefined>
25602428//  AM_RANGE(0xe4d0, 0xe4d3) MIDI port, option 9 / <undefined>
25612429//  AM_RANGE(0xe8d0, 0xe8d3) MIDI port, option A / <undefined>
25622430//  AM_RANGE(0xecd0, 0xecd3) MIDI port, option B / <undefined>
r253583r253584
30702938      m_dmac->dreq3_w(state ^ 1);
30712939}
30722940
3073UINT32 pc9801_state::pc9801_286_a20(bool state)
2941UINT32 pc9801_state::a20_286(bool state)
30742942{
30752943   return (state ? 0xffffff : 0x0fffff);
30762944}
r253583r253584
32403108      ide0->identify_device_buffer()[47] = 0;
32413109}
32423110
3243INTERRUPT_GEN_MEMBER(pc9801_state::pc9801_vrtc_irq)
3111INTERRUPT_GEN_MEMBER(pc9801_state::vrtc_irq)
32443112{
32453113   m_pic1->ir2_w(1);
32463114   m_vbirq->adjust(m_screen->time_until_vblank_end());
r253583r253584
34083276   MCFG_CPU_ADD("maincpu", I8086, 5000000) //unknown clock
34093277   MCFG_CPU_PROGRAM_MAP(pc9801_map)
34103278   MCFG_CPU_IO_MAP(pc9801_io)
3411   MCFG_CPU_VBLANK_INT_DRIVER("screen", pc9801_state, pc9801_vrtc_irq)
3279   MCFG_CPU_VBLANK_INT_DRIVER("screen", pc9801_state, vrtc_irq)
34123280   MCFG_CPU_IRQ_ACKNOWLEDGE_DEVICE("pic8259_master", pic8259_device, inta_cb)
34133281
34143282   MCFG_FRAGMENT_ADD(pc9801_common)
r253583r253584
34423310   MCFG_CPU_REPLACE("maincpu",V30,10000000)
34433311   MCFG_CPU_PROGRAM_MAP(pc9801ux_map)
34443312   MCFG_CPU_IO_MAP(pc9801ux_io)
3445   MCFG_CPU_VBLANK_INT_DRIVER("screen", pc9801_state, pc9801_vrtc_irq)
3313   MCFG_CPU_VBLANK_INT_DRIVER("screen", pc9801_state, vrtc_irq)
34463314
34473315   MCFG_MACHINE_START_OVERRIDE(pc9801_state,pc9801_common)
34483316   MCFG_MACHINE_RESET_OVERRIDE(pc9801_state,pc9801_common)
r253583r253584
34523320   MCFG_CPU_ADD("maincpu", I386SX, MAIN_CLOCK_X1*8) // unknown clock.
34533321   MCFG_CPU_PROGRAM_MAP(pc9801rs_map)
34543322   MCFG_CPU_IO_MAP(pc9801rs_io)
3455   MCFG_CPU_VBLANK_INT_DRIVER("screen", pc9801_state, pc9801_vrtc_irq)
3323   MCFG_CPU_VBLANK_INT_DRIVER("screen", pc9801_state, vrtc_irq)
34563324   MCFG_CPU_IRQ_ACKNOWLEDGE_DEVICE("pic8259_master", pic8259_device, inta_cb)
34573325
34583326   MCFG_FRAGMENT_ADD(pc9801_common)
r253583r253584
34813349   MCFG_CPU_REPLACE("maincpu",I80286,10000000)
34823350   MCFG_CPU_PROGRAM_MAP(pc9801ux_map)
34833351   MCFG_CPU_IO_MAP(pc9801ux_io)
3484   MCFG_80286_A20(pc9801_state, pc9801_286_a20)
3485   MCFG_CPU_VBLANK_INT_DRIVER("screen", pc9801_state, pc9801_vrtc_irq)
3352   MCFG_80286_A20(pc9801_state, a20_286)
3353   MCFG_CPU_VBLANK_INT_DRIVER("screen", pc9801_state, vrtc_irq)
34863354   MCFG_CPU_IRQ_ACKNOWLEDGE_DEVICE("pic8259_master", pic8259_device, inta_cb)
34873355//  MCFG_DEVICE_MODIFY("i8237", AM9157A, 10000000) // unknown clock
34883356MACHINE_CONFIG_END
r253583r253584
34913359   MCFG_CPU_REPLACE("maincpu",I486,25000000)
34923360   MCFG_CPU_PROGRAM_MAP(pc9821_map)
34933361   MCFG_CPU_IO_MAP(pc9821_io)
3494   MCFG_CPU_VBLANK_INT_DRIVER("screen", pc9801_state, pc9801_vrtc_irq)
3362   MCFG_CPU_VBLANK_INT_DRIVER("screen", pc9801_state, vrtc_irq)
34953363   MCFG_CPU_IRQ_ACKNOWLEDGE_DEVICE("pic8259_master", pic8259_device, inta_cb)
34963364
34973365   MCFG_MACHINE_START_OVERRIDE(pc9801_state,pc9801bx2)
r253583r253584
35013369   MCFG_CPU_REPLACE("maincpu", I486, 16000000) // unknown clock
35023370   MCFG_CPU_PROGRAM_MAP(pc9821_map)
35033371   MCFG_CPU_IO_MAP(pc9821_io)
3504   MCFG_CPU_VBLANK_INT_DRIVER("screen", pc9801_state, pc9801_vrtc_irq)
3372   MCFG_CPU_VBLANK_INT_DRIVER("screen", pc9801_state, vrtc_irq)
35053373   MCFG_CPU_IRQ_ACKNOWLEDGE_DEVICE("pic8259_master", pic8259_device, inta_cb)
35063374
35073375   MCFG_DEVICE_MODIFY("pit8253")
r253583r253584
35243392   MCFG_CPU_REPLACE("maincpu", I486, 66666667) // unknown clock
35253393   MCFG_CPU_PROGRAM_MAP(pc9821_map)
35263394   MCFG_CPU_IO_MAP(pc9821_io)
3527   MCFG_CPU_VBLANK_INT_DRIVER("screen", pc9801_state, pc9801_vrtc_irq)
3395   MCFG_CPU_VBLANK_INT_DRIVER("screen", pc9801_state, vrtc_irq)
35283396   MCFG_CPU_IRQ_ACKNOWLEDGE_DEVICE("pic8259_master", pic8259_device, inta_cb)
35293397
35303398   MCFG_MACHINE_START_OVERRIDE(pc9801_state,pc9821ap2)
r253583r253584
35343402   MCFG_CPU_REPLACE("maincpu",PENTIUM,32000000) /* TODO: clock */
35353403   MCFG_CPU_PROGRAM_MAP(pc9821_map)
35363404   MCFG_CPU_IO_MAP(pc9821_io)
3537   MCFG_CPU_VBLANK_INT_DRIVER("screen", pc9801_state, pc9801_vrtc_irq)
3405   MCFG_CPU_VBLANK_INT_DRIVER("screen", pc9801_state, vrtc_irq)
35383406   MCFG_CPU_IRQ_ACKNOWLEDGE_DEVICE("pic8259_master", pic8259_device, inta_cb)
35393407MACHINE_CONFIG_END
35403408
trunk/src/mame/mess.cpp
r253583r253584
1919const char * emulator_info::get_appname() { return APPNAME;}
2020const char * emulator_info::get_appname_lower() { return APPNAME_LOWER;}
2121const char * emulator_info::get_configname() { return CONFIGNAME;}
22const char * emulator_info::get_copyright() { return COPYRIGHT;}
23const char * emulator_info::get_copyright_info() { return COPYRIGHT_INFO;}

https://github.com/mamedev/mame/commit/ff627a41390256e2c9f74d39f1639d4165b3d47e

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