trunk/src/devices/cpu/i86/i86.cpp
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| 144 | 144 | m_seg_prefix = false; |
| 145 | 145 | |
| 146 | 146 | /* Dispatch IRQ */ |
| 147 | | if ( m_pending_irq && m_no_interrupt == 0 ) |
| 147 | if ( m_pending_irq && (m_no_interrupt == 0) ) |
| 148 | 148 | { |
| 149 | 149 | if ( m_pending_irq & NMI_IRQ ) |
| 150 | 150 | { |
| r252993 | r252994 | |
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| 159 | 159 | } |
| 160 | 160 | } |
| 161 | 161 | |
| 162 | | /* No interrupt allowed between last instruction and this one */ |
| 163 | | if ( m_no_interrupt ) |
| 162 | /* Trap should allow one instruction to be executed. |
| 163 | CPUID.ASM (by Bob Smith, 1985) suggests that in situations where m_no_interrupt is 1, |
| 164 | (directly after POP SS / MOV_SREG), single step IRQs don't fire. |
| 165 | */ |
| 166 | if (m_fire_trap ) |
| 164 | 167 | { |
| 165 | | m_no_interrupt--; |
| 166 | | } |
| 167 | | |
| 168 | | /* trap should allow one instruction to be executed */ |
| 169 | | if ( m_fire_trap ) |
| 170 | | { |
| 171 | | if ( m_fire_trap >= 2 ) |
| 168 | if ( (m_fire_trap >= 2) && (m_no_interrupt == 0) ) |
| 172 | 169 | { |
| 170 | m_fire_trap = 0; // reset trap flag upon entry |
| 173 | 171 | interrupt(1); |
| 174 | | m_fire_trap = 0; |
| 175 | 172 | } |
| 176 | 173 | else |
| 177 | 174 | { |
| 178 | 175 | m_fire_trap++; |
| 179 | 176 | } |
| 180 | 177 | } |
| 178 | |
| 179 | /* No interrupt allowed between last instruction and this one */ |
| 180 | if ( m_no_interrupt ) |
| 181 | { |
| 182 | m_no_interrupt--; |
| 183 | } |
| 184 | |
| 181 | 185 | } |
| 182 | 186 | |
| 183 | 187 | if (!m_seg_prefix) |
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| 1404 | 1408 | m_src = GetRMWord(); |
| 1405 | 1409 | m_sregs[(m_modrm & 0x18) >> 3] = m_src; // confirmed on hw: modrm bit 5 ignored |
| 1406 | 1410 | CLKM(MOV_SR,MOV_SM); |
| 1411 | m_no_interrupt = 1; // Disable IRQ after load segment register. |
| 1407 | 1412 | break; |
| 1408 | 1413 | |
| 1409 | 1414 | case 0x8f: // i_popw |