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r44364 Saturday 23rd January, 2016 at 16:30:14 UTC by Ryan Holtz
Fix remainder of this == NULL checks from Tafoids run
[src/mame/drivers]aleck64.cpp arsystems.cpp n64.cpp ninjakd2.cpp prestige.cpp segas16a.cpp
[src/mame/includes]n64.h ninjakd2.h vsnes.h
[src/mame/machine]n64.cpp vsnes.cpp
[src/mame/video]n64.cpp n64.h rdptpipe.cpp sega16sp.cpp sega16sp.h

trunk/src/mame/drivers/aleck64.cpp
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184184         m_e90_pal(*this,"e90pal"),
185185         m_dip_read_offset(0) { }
186186
187   optional_shared_ptr<UINT32> m_e90_vram;
188   optional_shared_ptr<UINT32> m_e90_pal;
189187   DECLARE_DRIVER_INIT(aleck64);
190188   DECLARE_WRITE32_MEMBER(aleck_dips_w);
191189   DECLARE_READ32_MEMBER(aleck_dips_r);
192190   DECLARE_READ16_MEMBER(e90_prot_r);
193191   DECLARE_WRITE16_MEMBER(e90_prot_w);
192
194193   UINT32 screen_update_e90(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
195194
195protected:
196   optional_shared_ptr<UINT32> m_e90_vram;
197   optional_shared_ptr<UINT32> m_e90_pal;
198
196199private:
197200   UINT32 m_dip_read_offset;
198201};
trunk/src/mame/drivers/arsystems.cpp
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6262{
6363public:
6464   arcadia_amiga_state(const machine_config &mconfig, device_type type, const char *tag)
65      : amiga_state(mconfig, type, tag) { }
65      : amiga_state(mconfig, type, tag)
66      , m_bios_region(*this, "user2")
67   {
68   }
6669
6770   UINT8 m_coin_counter[2];
6871
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9194
9295protected:
9396   virtual void machine_reset() override;
97
98   optional_memory_region m_bios_region;
99
100   UINT8 m_coin_counter[2];
94101};
95102
96103
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922929   m_agnus_id = AGNUS_HR_NTSC;
923930   m_denise_id = DENISE;
924931
925   /* OnePlay bios is encrypted, TenPlay is not */
926   UINT16 *biosrom = (UINT16 *)memregion("user2")->base();
932   if (m_bios_region != NULL)
933   {
934      /* OnePlay bios is encrypted, TenPlay is not */
935      UINT16 *rom = (UINT16 *)m_bios_region->base();
927936
928   if (biosrom)
929      if (biosrom[0] != 0x4afc)
937      if (rom[0] != 0x4afc)
938      {
930939         generic_decode("user2", 6, 1, 0, 2, 3, 4, 5, 7);
940      }
941   }
931942}
932943
933944
trunk/src/mame/drivers/n64.cpp
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334334      //printf("Loading\n");
335335      UINT8 data[0x30800];
336336      battery_image->battery_load(data, 0x30800, 0x00);
337      //memcpy(n64_sram, data, 0x20000);
338      memcpy(memshare("sram")->ptr(), data, 0x20000);
337      if (m_sram != NULL)
338      {
339         memcpy(m_sram, data, 0x20000);
340      }
339341      memcpy(periphs->m_save_data.eeprom, data + 0x20000, 0x800);
340342      memcpy(periphs->m_save_data.mempak[0], data + 0x20800, 0x8000);
341343      memcpy(periphs->m_save_data.mempak[1], data + 0x28800, 0x8000);
trunk/src/mame/drivers/ninjakd2.cpp
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172172
173173SAMPLES_START_CB_MEMBER(ninjakd2_state::ninjakd2_init_samples)
174174{
175   const UINT8* const rom = memregion("pcm")->base();
176   const int length = memregion("pcm")->bytes();
175   if (m_pcm_region == NULL)
176   {
177      return;
178   }
179
180   const UINT8* const rom = m_pcm_region->base();
181   const int length = m_pcm_region->bytes();
177182   INT16* sampledata = auto_alloc_array(machine(), INT16, length);
178183
179184   // convert unsigned 8-bit PCM to signed 16-bit
180185   for (int i = 0; i < length; ++i)
186   {
181187      sampledata[i] = rom[i] << 7;
188   }
182189
183190   m_sampledata = sampledata;
184191}
185192
186193WRITE8_MEMBER(ninjakd2_state::ninjakd2_pcm_play_w)
187194{
188   const UINT8* const rom = memregion("pcm")->base();
189
190195   // only Ninja Kid II uses this
191   if (rom)
196   if (m_pcm_region == NULL)
192197   {
193      const int length = memregion("pcm")->bytes();
194      const int start = data << 8;
198      return;
199   }
195200
196      // find end of sample
197      int end = start;
198      while (end < length && rom[end] != 0x00)
199         ++end;
201   const UINT8* const rom = m_pcm_region->base();
202   const int length = m_pcm_region->bytes();
203   const int start = data << 8;
200204
201      if (end - start)
202         m_pcm->start_raw(0, &m_sampledata[start], end - start, NE555_FREQUENCY);
203      else
204         m_pcm->stop(0);
205   // find end of sample
206   int end = start;
207   while (end < length && rom[end] != 0x00)
208   {
209      ++end;
205210   }
211
212   if (end - start)
213   {
214      m_pcm->start_raw(0, &m_sampledata[start], end - start, NE555_FREQUENCY);
215   }
216   else
217   {
218      m_pcm->stop(0);
219   }
206220}
207221
208222
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453467   AM_RANGE(0xf000, 0xf000) AM_WRITE(ninjakd2_pcm_play_w)
454468ADDRESS_MAP_END
455469
470static ADDRESS_MAP_START( ninjakid_nopcm_sound_cpu, AS_PROGRAM, 8, ninjakd2_state )
471   AM_RANGE(0x0000, 0x7fff) AM_ROM
472   AM_RANGE(0x8000, 0xbfff) AM_ROM
473   AM_RANGE(0xc000, 0xc7ff) AM_RAM
474   AM_RANGE(0xe000, 0xe000) AM_READ(soundlatch_byte_r)
475   AM_RANGE(0xf000, 0xf000) AM_NOP
476ADDRESS_MAP_END
456477
457478static ADDRESS_MAP_START( decrypted_opcodes_map, AS_DECRYPTED_OPCODES, 8, ninjakd2_state )
458479   AM_RANGE(0x0000, 0x7fff) AM_ROM AM_SHARE("decrypted_opcodes")
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972993   MCFG_CPU_MODIFY("maincpu")
973994   MCFG_CPU_PROGRAM_MAP(mnight_main_cpu)
974995
996   MCFG_CPU_MODIFY("soundcpu")
997   MCFG_CPU_PROGRAM_MAP(ninjakid_nopcm_sound_cpu)
998
975999   /* video hardware */
9761000   MCFG_VIDEO_START_OVERRIDE(ninjakd2_state,mnight)
9771001
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9801004MACHINE_CONFIG_END
9811005
9821006static MACHINE_CONFIG_DERIVED( arkarea, ninjakd2_core )
983
9841007   /* basic machine hardware */
9851008   MCFG_CPU_MODIFY("maincpu")
9861009   MCFG_CPU_PROGRAM_MAP(mnight_main_cpu)
9871010
1011   MCFG_CPU_MODIFY("soundcpu")
1012   MCFG_CPU_PROGRAM_MAP(ninjakid_nopcm_sound_cpu)
1013
9881014   /* video hardware */
9891015   MCFG_VIDEO_START_OVERRIDE(ninjakd2_state,arkarea)
9901016
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9981024   MCFG_CPU_MODIFY("maincpu")
9991025   MCFG_CPU_PROGRAM_MAP(robokid_main_cpu)
10001026
1027   MCFG_CPU_MODIFY("soundcpu")
1028   MCFG_CPU_PROGRAM_MAP(ninjakid_nopcm_sound_cpu)
1029
10011030   /* video hardware */
10021031   MCFG_GFXDECODE_MODIFY("gfxdecode", robokid)
10031032   MCFG_PALETTE_MODIFY("palette")
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10161045   MCFG_CPU_MODIFY("maincpu")
10171046   MCFG_CPU_PROGRAM_MAP(omegaf_main_cpu)
10181047
1048   MCFG_CPU_MODIFY("soundcpu")
1049   MCFG_CPU_PROGRAM_MAP(ninjakid_nopcm_sound_cpu)
1050
10191051   MCFG_MACHINE_START_OVERRIDE(ninjakd2_state,omegaf)
10201052   MCFG_MACHINE_RESET_OVERRIDE(ninjakd2_state,omegaf)
10211053
trunk/src/mame/drivers/prestige.cpp
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625625   m_cart_rom = memregion(region_tag.assign(m_cart->tag()).append(GENERIC_ROM_REGION_TAG).c_str());
626626
627627   UINT8 *rom = memregion("maincpu")->base();
628   UINT8 *cart = m_cart_rom->base();
629   if (cart == nullptr)
628   UINT8 *cart = NULL;
629   if (m_cart_rom != NULL)
630   {
631      cart = m_cart_rom->base();
632   }
633   else
634   {
630635      cart = rom + 0x40000;   // internal ROM also includes extra contents that are activated by a cartridge that works as a jumper
636   }
631637   UINT8 *ram = m_ram->pointer();
632638   memset(ram, 0x00, m_ram->size());
633639
trunk/src/mame/drivers/segas16a.cpp
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988988   AM_RANGE(0xc0, 0xc0) AM_MIRROR(0x3f) AM_READ(sound_data_r)
989989ADDRESS_MAP_END
990990
991static ADDRESS_MAP_START( sound_no7751_portmap, AS_IO, 8, segas16a_state )
992   ADDRESS_MAP_UNMAP_HIGH
993   ADDRESS_MAP_GLOBAL_MASK(0xff)
994   AM_RANGE(0x00, 0x01) AM_MIRROR(0x3e) AM_DEVREADWRITE("ymsnd", ym2151_device, read, write)
995   AM_RANGE(0x80, 0x80) AM_MIRROR(0x3f) AM_NOP
996   AM_RANGE(0xc0, 0xc0) AM_MIRROR(0x3f) AM_READ(sound_data_r)
997ADDRESS_MAP_END
991998
992999
9931000//**************************************************************************
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19641971
19651972
19661973static MACHINE_CONFIG_DERIVED( system16a_no7751, system16a )
1974   MCFG_CPU_MODIFY("soundcpu")
1975   MCFG_CPU_IO_MAP(sound_no7751_portmap)
1976
19671977   MCFG_DEVICE_REMOVE("n7751")
19681978   MCFG_DEVICE_REMOVE("dac")
19691979
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19871997*/
19881998
19891999static MACHINE_CONFIG_DERIVED( system16a_fd1089a_no7751, system16a_fd1089a )
2000   MCFG_CPU_MODIFY("soundcpu")
2001   MCFG_CPU_IO_MAP(sound_no7751_portmap)
2002
19902003   MCFG_DEVICE_REMOVE("n7751")
19912004   MCFG_DEVICE_REMOVE("dac")
19922005
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19952008MACHINE_CONFIG_END
19962009
19972010static MACHINE_CONFIG_DERIVED( system16a_fd1089b_no7751, system16a_fd1089b )
2011   MCFG_CPU_MODIFY("soundcpu")
2012   MCFG_CPU_IO_MAP(sound_no7751_portmap)
2013
19982014   MCFG_DEVICE_REMOVE("n7751")
19992015   MCFG_DEVICE_REMOVE("dac")
20002016
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20032019MACHINE_CONFIG_END
20042020
20052021static MACHINE_CONFIG_DERIVED( system16a_fd1094_no7751, system16a_fd1094 )
2022   MCFG_CPU_MODIFY("soundcpu")
2023   MCFG_CPU_IO_MAP(sound_no7751_portmap)
2024
20062025   MCFG_DEVICE_REMOVE("n7751")
20072026   MCFG_DEVICE_REMOVE("dac")
20082027
trunk/src/mame/includes/n64.h
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44#define _INCLUDES_N64_H_
55
66#include "cpu/rsp/rsp.h"
7#include "cpu/mips/mips3.h"
78#include "sound/dmadac.h"
89
9/*----------- forward decls -----------*/
10
1110/*----------- driver state -----------*/
1211
1312class n64_rdp;
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1615{
1716public:
1817   n64_state(const machine_config &mconfig, device_type type, const char *tag)
19      : driver_device(mconfig, type, tag) ,
20      m_maincpu(*this, "maincpu") { }
18      : driver_device(mconfig, type, tag)
19      , m_vr4300(*this, "maincpu")
20      , m_rsp(*this, "rsp")
21      , m_sram(*this, "sram")
22      , m_rdram(*this, "rdram")
23      , m_rsp_imem(*this, "rsp_imem")
24      , m_rsp_dmem(*this, "rsp_dmem")
25   {
26   }
2127
2228   /* video-related */
2329   n64_rdp *m_rdp;
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2935
3036   UINT32 screen_update_n64(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
3137   void screen_eof_n64(screen_device &screen, bool state);
32   required_device<cpu_device> m_maincpu;
38
39   // Getters
40   n64_rdp* rdp() { return m_rdp; }
41   UINT32* rdram() { return m_rdram; }
42   UINT32* sram() { return m_sram; }
43   UINT32* rsp_imem() { return m_rsp_imem; }
44   UINT32* rsp_dmem() { return m_rsp_dmem; }
45
46protected:
47   required_device<mips3_device> m_vr4300;
48   required_device<rsp_device> m_rsp;
49
50   optional_shared_ptr<UINT32> m_sram;
51   required_shared_ptr<UINT32> m_rdram;
52   required_shared_ptr<UINT32> m_rsp_imem;
53   required_shared_ptr<UINT32> m_rsp_dmem;
54
55   /* video-related */
56   n64_rdp *m_rdp;
3357};
3458
3559/*----------- devices -----------*/
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98122   void ai_timer_tick();
99123   void pi_dma_tick();
100124   void si_dma_tick();
101   void vi_scanline_tick();
102125   void reset_tick();
103126   void video_update(bitmap_rgb32 &bitmap);
104127
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137160   void poll_reset_button(bool button);
138161
139162   UINT32 dp_clock;
163
140164protected:
141165   // device-level overrides
142166   virtual void device_start() override;
143167   virtual void device_reset() override;
144168
145169private:
146   address_space *mem_map;
147   device_t *maincpu;
148   device_t *rspcpu;
170   n64_state* m_n64;
171   address_space *m_mem_map;
172   mips3_device *m_vr4300;
173   rsp_device *m_rsp;
149174
175   UINT32 *m_rdram;
176   UINT32 *m_sram;
177   UINT32 *m_rsp_imem;
178   UINT32 *m_rsp_dmem;
179
150180   void clear_rcp_interrupt(int interrupt);
151181
152182   bool reset_held;
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370400   {0x0,0x5F15E0,0xB79D00,0x10801A0,0x1523720,0x1963D80,0x1D414C0,0x20BBCE0,
371401      0x23196E0,0x28A1E00,0x2DF5DC0,0x3299340,0x36D99A0,0x3AB70E0,0x3E31900,0x4149200};
372402
373
374
375extern UINT32 *n64_sram;
376extern UINT32 *rdram;
377extern UINT32 *rsp_imem;
378extern UINT32 *rsp_dmem;
379
380403extern void dp_full_sync(running_machine &machine);
381404
382405#endif
trunk/src/mame/includes/ninjakd2.h
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1616      m_maincpu(*this,"maincpu"),
1717      m_soundcpu(*this, "soundcpu"),
1818      m_pcm(*this, "pcm"),
19      m_pcm_region(*this, "pcm"),
1920      m_bg_videoram(*this, "bg_videoram"),
2021      m_fg_videoram(*this, "fg_videoram"),
2122      m_spriteram(*this, "spriteram"),
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2829   required_device<cpu_device> m_maincpu;
2930   required_device<cpu_device> m_soundcpu;
3031   optional_device<samples_device> m_pcm;
32   optional_memory_region m_pcm_region;
3133   optional_shared_ptr<UINT8> m_bg_videoram;
3234   required_shared_ptr<UINT8> m_fg_videoram;
3335   required_shared_ptr<UINT8> m_spriteram;
trunk/src/mame/includes/vsnes.h
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66{
77public:
88   vsnes_state(const machine_config &mconfig, device_type type, const char *tag)
9      : driver_device(mconfig, type, tag),
10      m_maincpu(*this, "maincpu"),
11      m_subcpu(*this, "sub"),
12      m_ppu1(*this, "ppu1"),
13      m_ppu2(*this, "ppu2"),
14      m_work_ram(*this, "work_ram"),
15      m_work_ram_1(*this, "work_ram_1"),
16      m_palette(*this, "palette")
17      { }
9      : driver_device(mconfig, type, tag)
10      , m_maincpu(*this, "maincpu")
11      , m_subcpu(*this, "sub")
12      , m_ppu1(*this, "ppu1")
13      , m_ppu2(*this, "ppu2")
14      , m_work_ram(*this, "work_ram")
15      , m_work_ram_1(*this, "work_ram_1")
16      , m_palette(*this, "palette")
17      , m_gfx1_rom(*this, "gfx1")
18   {
19   }
1820
1921   required_device<cpu_device> m_maincpu;
2022   optional_device<cpu_device> m_subcpu;
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2426   required_shared_ptr<UINT8> m_work_ram;
2527   optional_shared_ptr<UINT8> m_work_ram_1;
2628   required_device<palette_device> m_palette;
29
30   optional_memory_region m_gfx1_rom;
31
2732   int m_coin;
2833   int m_do_vrom_bank;
2934   int m_input_latch[4];
trunk/src/mame/machine/n64.cpp
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99#include "includes/n64.h"
1010#include "video/n64.h"
1111
12UINT32 *n64_sram;
13UINT32 *rdram;
14UINT32 *rsp_imem;
15UINT32 *rsp_dmem;
16
1712// device type definition
1813const device_type N64PERIPH = &device_creator<n64_periphs>;
1914
20
21
22
2315n64_periphs::n64_periphs(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
2416   : device_t(mconfig, N64PERIPH, "N64 Periphal Chips", tag, owner, clock, "n64_periphs", __FILE__)
2517   , device_video_interface(mconfig, *this)
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4941void n64_periphs::reset_tick()
5042{
5143   reset_timer->adjust(attotime::never);
52   maincpu->reset();
53   maincpu->execute().set_input_line(INPUT_LINE_IRQ2, CLEAR_LINE);
54   rspcpu->reset();
55   rspcpu->execute().set_input_line(INPUT_LINE_HALT, ASSERT_LINE);
56   rspcpu->state().set_state_int(RSP_SR, rspcpu->state().state_int(RSP_SR) | RSP_STATUS_HALT);
44   m_vr4300->reset();
45   m_vr4300->set_input_line(INPUT_LINE_IRQ2, CLEAR_LINE);
46   m_rsp->reset();
47   m_rsp->set_input_line(INPUT_LINE_HALT, ASSERT_LINE);
48   m_rsp->set_state_int(RSP_SR, m_rsp->state_int(RSP_SR) | RSP_STATUS_HALT);
5749   reset_held = false;
5850   cic_status = 0;
5951   memset(pif_ram, 0, sizeof(pif_ram));
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10496   reset_held = button;
10597   if(!old_held && reset_held)
10698   {
107      machine().device("maincpu")->execute().set_input_line(INPUT_LINE_IRQ2, ASSERT_LINE);
99      m_vr4300->set_input_line(INPUT_LINE_IRQ2, ASSERT_LINE);
108100   }
109101   else if(old_held && reset_held)
110102   {
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123115   si_dma_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(n64_periphs::si_dma_callback),this));
124116   vi_scanline_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(n64_periphs::vi_scanline_callback),this));
125117   reset_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(n64_periphs::reset_timer_callback),this));
118   m_n64 = machine().driver_data<n64_state>();
126119}
127120
128121void n64_periphs::device_reset()
129122{
130123   UINT32 *cart = (UINT32*)machine().root_device().memregion("user2")->base();
131124
132   maincpu = machine().device("maincpu");
133   rspcpu = machine().device("rsp");
134   mem_map = &maincpu->memory().space(AS_PROGRAM);
125   m_vr4300 = machine().device<mips3_device>("maincpu");
126   m_rsp = machine().device<rsp_device>("rsp");
127   m_mem_map = &m_vr4300->space(AS_PROGRAM);
135128
129   m_rdram = m_n64->rdram();
130   m_rsp_imem = m_n64->rsp_imem();
131   m_rsp_dmem = m_n64->rsp_dmem();
132   m_sram = m_n64->sram();
133
136134   mi_version = 0x01010101;
137135   mi_interrupt = 0;
138136   mi_intr_mask = 0;
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238236   pif_ram[0x26] = 0x3f;
239237   pif_ram[0x27] = 0x3f;
240238   cic_type=2;
241   mem_map->write_dword(0x00000318, 0x800000); /* RDRAM Size */
239   m_mem_map->write_dword(0x00000318, 0x800000); /* RDRAM Size */
242240
243241   if (boot_checksum == U64(0x00000000001ff230))
244242   {
r252875r252876
274272      pif_ram[0x26] = 0x91;
275273      pif_ram[0x27] = 0x3f;
276274      cic_type=5;
277      mem_map->write_dword(0x000003f0, 0x800000);
275      m_mem_map->write_dword(0x000003f0, 0x800000);
278276   }
279277   else if (boot_checksum == U64(0x000000d6d5de4ba0))
280278   {
r252875r252876
329327         break;
330328
331329      default:
332         logerror("mi_reg_r: %08X, %08X at %08X\n", offset, mem_mask, mem_map->device().safe_pc());
330         logerror("mi_reg_r: %08X, %08X at %08X\n", offset, mem_mask, m_vr4300->pc());
333331         break;
334332   }
335333
r252875r252876
414412      }
415413
416414      default:
417         logerror("mi_reg_w: %08X, %08X, %08X at %08X\n", data, offset, mem_mask, maincpu->safe_pc());
415         logerror("mi_reg_w: %08X, %08X, %08X at %08X\n", data, offset, mem_mask, m_vr4300->pc());
418416         break;
419417   }
420418}
r252875r252876
428426{
429427   if (mi_intr_mask & mi_interrupt)
430428   {
431      machine().device("maincpu")->execute().set_input_line(INPUT_LINE_IRQ0, ASSERT_LINE);
429      m_vr4300->set_input_line(INPUT_LINE_IRQ0, ASSERT_LINE);
432430   }
433431   else
434432   {
435      machine().device("maincpu")->execute().set_input_line(INPUT_LINE_IRQ0, CLEAR_LINE);
433      m_vr4300->set_input_line(INPUT_LINE_IRQ0, CLEAR_LINE);
436434   }
437435}
438436
r252875r252876
529527{
530528   if(offset > 0x24/4)
531529   {
532      logerror("rdram_reg_r: %08X, %08X at %08X\n", offset, mem_mask, maincpu->safe_pc());
530      logerror("rdram_reg_r: %08X, %08X at %08X\n", offset, mem_mask, m_vr4300->pc());
533531      return 0;
534532   }
535533   return rdram_regs[offset];
r252875r252876
539537{
540538   if(offset > 0x24/4)
541539   {
542      logerror("rdram_reg_w: %08X, %08X, %08X at %08X\n", data, offset, mem_mask, maincpu->safe_pc());
540      logerror("rdram_reg_w: %08X, %08X, %08X at %08X\n", data, offset, mem_mask, m_vr4300->pc());
543541      return;
544542   }
545543   COMBINE_DATA(&rdram_regs[offset]);
r252875r252876
570568      length = 0x1000 - (sp_mem_addr & 0xfff);
571569   }
572570
573   UINT32 *sp_mem[2] = { rsp_dmem, rsp_imem };
571   UINT32 *sp_mem[2] = { m_rsp_dmem, m_rsp_imem };
574572
575573   int sp_mem_page = (sp_mem_addr >> 12) & 1;
576574   if(direction == 0)// RDRAM -> I/DMEM
r252875r252876
582580
583581         for(int i = 0; i < length / 4; i++)
584582         {
585            sp_mem[sp_mem_page][(dst + i) & 0x3ff] = rdram[src + i];
583            sp_mem[sp_mem_page][(dst + i) & 0x3ff] = m_rdram[src + i];
586584         }
587585
588586         sp_mem_addr += length;
r252875r252876
600598
601599         for(int i = 0; i < length / 4; i++)
602600         {
603            rdram[dst + i] = sp_mem[sp_mem_page][(src + i) & 0x3ff];
601            m_rdram[dst + i] = sp_mem[sp_mem_page][(src + i) & 0x3ff];
604602         }
605603
606604         sp_mem_addr += length;
r252875r252876
615613{
616614   if (data & 0x1)
617615   {
618      rspcpu->execute().set_input_line(INPUT_LINE_HALT, ASSERT_LINE);
619      rspcpu->state().set_state_int(RSP_SR, rspcpu->state().state_int(RSP_SR) | RSP_STATUS_HALT);
616      m_rsp->set_input_line(INPUT_LINE_HALT, ASSERT_LINE);
617      m_rsp->set_state_int(RSP_SR, m_rsp->state_int(RSP_SR) | RSP_STATUS_HALT);
620618   }
621619
622620   if (data & 0x2)
623621   {
624      rspcpu->state().set_state_int(RSP_SR, rspcpu->state().state_int(RSP_SR) | RSP_STATUS_BROKE);
622      m_rsp->set_state_int(RSP_SR, m_rsp->state_int(RSP_SR) | RSP_STATUS_BROKE);
625623
626      if (rspcpu->state().state_int(RSP_SR) & RSP_STATUS_INTR_BREAK)
624      if (m_rsp->state_int(RSP_SR) & RSP_STATUS_INTR_BREAK)
627625      {
628626         signal_rcp_interrupt(SP_INTERRUPT);
629627      }
r252875r252876
632630
633631READ32_MEMBER(n64_periphs::sp_reg_r)
634632{
635   UINT32 ret = 0;
636633   switch (offset)
637634   {
638635      case 0x00/4:        // SP_MEM_ADDR_REG
639         ret = sp_mem_addr;
640         break;
636         return sp_mem_addr;
641637
642638      case 0x04/4:        // SP_DRAM_ADDR_REG
643         ret = sp_dram_addr;
644         break;
639         return sp_dram_addr;
645640
646641      case 0x08/4:        // SP_RD_LEN_REG
647         ret = (sp_dma_skip << 20) | (sp_dma_count << 12) | sp_dma_length;
648         break;
642         return (sp_dma_skip << 20) | (sp_dma_count << 12) | sp_dma_length;
649643
650644      case 0x10/4:        // SP_STATUS_REG
651         ret = rspcpu->state().state_int(RSP_SR);
652         break;
645         return m_rsp->state_int(RSP_SR);
653646
654647      case 0x14/4:        // SP_DMA_FULL_REG
655         ret = 0;
656         break;
648         return 0;
657649
658650      case 0x18/4:        // SP_DMA_BUSY_REG
659         ret = 0;
660         break;
651         return 0;
661652
662653      case 0x1c/4:        // SP_SEMAPHORE_REG
663         machine().device("maincpu")->execute().yield();
654         m_vr4300->yield();
664655         if( sp_semaphore )
665656         {
666            ret = 1;
657            return 1;
667658         }
668659         else
669660         {
670661            sp_semaphore = 1;
671            ret = 0;
662            return 0;
672663         }
673664         break;
674665
675666      case 0x20/4:        // DP_CMD_START
676      {
677         n64_state *state = machine().driver_data<n64_state>();
678         ret = state->m_rdp->get_start();
679         break;
680      }
667         return m_n64->rdp()->get_start();
681668
682669      case 0x24/4:        // DP_CMD_END
683      {
684         n64_state *state = machine().driver_data<n64_state>();
685         ret = state->m_rdp->get_end();
686         break;
687      }
670         return m_n64->rdp()->get_end();
688671
689672      case 0x28/4:        // DP_CMD_CURRENT
690      {
691         n64_state *state = machine().driver_data<n64_state>();
692         ret = state->m_rdp->get_current();
693         break;
694      }
673         return m_n64->rdp()->get_current();
695674
696675      case 0x34/4:        // DP_CMD_BUSY
697676      case 0x38/4:        // DP_CMD_PIPE_BUSY
698677      case 0x3c/4:        // DP_CMD_TMEM_BUSY
699         break;
678         return 0;
700679
701680      case 0x2c/4:        // DP_CMD_STATUS
702      {
703         n64_state *state = machine().driver_data<n64_state>();
704         ret = state->m_rdp->get_status();
705         break;
706      }
681         return m_n64->rdp()->get_status();
707682
708683      case 0x30/4:        // DP_CMD_CLOCK
709      {
710         if(!(machine().driver_data<n64_state>()->m_rdp->get_status() & DP_STATUS_FREEZE))
684         if(!(m_n64->rdp()->get_status() & DP_STATUS_FREEZE))
711685         {
712686            dp_clock += 13;
713            ret = dp_clock;
687            return dp_clock;
714688         }
715689         break;
716      }
717690
718691      case 0x40000/4:     // PC
719         ret = rspcpu->state().state_int(RSP_PC) & 0x00000fff;
720         break;
692         return m_rsp->state_int(RSP_PC) & 0x00000fff;
721693
722694      default:
723         logerror("sp_reg_r: %08X at %08X\n", offset, maincpu->safe_pc());
695         logerror("sp_reg_r: %08X at %08X\n", offset, m_vr4300->pc());
724696         break;
725697   }
726698
727   return ret;
699   return 0;
728700}
729701
730702
r252875r252876
758730
759731         case 0x10/4:        // RSP_STATUS_REG
760732         {
761            UINT32 oldstatus = rspcpu->state().state_int(RSP_SR);
733            UINT32 oldstatus = m_rsp->state_int(RSP_SR);
762734            UINT32 newstatus = oldstatus;
763735
764736            if (data & 0x00000001)      // clear halt
765737            {
766               rspcpu->execute().set_input_line(INPUT_LINE_HALT, CLEAR_LINE);
738               m_rsp->set_input_line(INPUT_LINE_HALT, CLEAR_LINE);
767739               newstatus &= ~RSP_STATUS_HALT;
768740            }
769741            if (data & 0x00000002)      // set halt
770742            {
771               rspcpu->execute().set_input_line(INPUT_LINE_HALT, ASSERT_LINE);
743               m_rsp->set_input_line(INPUT_LINE_HALT, ASSERT_LINE);
772744               newstatus |= RSP_STATUS_HALT;
773745            }
774746            if (data & 0x00000004)
r252875r252876
792764               newstatus |= RSP_STATUS_SSTEP;  // set single step
793765               if(!(oldstatus & (RSP_STATUS_BROKE | RSP_STATUS_HALT)))
794766               {
795                  rspcpu->state().set_state_int(RSP_STEPCNT, 1 );
796                  machine().device("rsp")->execute().yield();
767                  m_rsp->set_state_int(RSP_STEPCNT, 1 );
768                  m_rsp->yield();
797769               }
798770            }
799771            if (data & 0x00000080)
r252875r252876
868840            {
869841               newstatus |= RSP_STATUS_SIGNAL7;        // set signal 7
870842            }
871            rspcpu->state().set_state_int(RSP_SR, newstatus);
843            m_rsp->set_state_int(RSP_SR, newstatus);
872844            break;
873845         }
874846
r252875r252876
880852            break;
881853
882854         default:
883            logerror("sp_reg_w: %08X, %08X, %08X at %08X\n", data, offset, mem_mask, maincpu->safe_pc());
855            logerror("sp_reg_w: %08X, %08X, %08X at %08X\n", data, offset, mem_mask, m_vr4300->pc());
884856            break;
885857      }
886858   }
r252875r252876
889861      switch (offset & 0xffff)
890862      {
891863         case 0x00/4:        // SP_PC_REG
892            if( rspcpu->state().state_int(RSP_NEXTPC) != 0xffffffff )
864            if( m_rsp->state_int(RSP_NEXTPC) != 0xffffffff )
893865            {
894               rspcpu->state().set_state_int(RSP_NEXTPC, 0x1000 | (data & 0xfff));
866               m_rsp->set_state_int(RSP_NEXTPC, 0x1000 | (data & 0xfff));
895867            }
896868            else
897869            {
898               rspcpu->state().set_state_int(RSP_PC, 0x1000 | (data & 0xfff));
870               m_rsp->set_state_int(RSP_PC, 0x1000 | (data & 0xfff));
899871            }
900872            break;
901873
902874         default:
903            logerror("sp_reg_w: %08X, %08X, %08X at %08X\n", data, offset, mem_mask, maincpu->safe_pc());
875            logerror("sp_reg_w: %08X, %08X, %08X at %08X\n", data, offset, mem_mask, m_vr4300->pc());
904876            break;
905877      }
906878   }
r252875r252876
916888
917889READ32_MEMBER( n64_periphs::dp_reg_r )
918890{
919   n64_state *state = space.machine().driver_data<n64_state>();
920   UINT32 ret = 0;
921
922891   switch (offset)
923892   {
924893      case 0x00/4:        // DP_START_REG
925         ret = state->m_rdp->get_start();
926         break;
894         return m_n64->rdp()->get_start();
927895
928896      case 0x04/4:        // DP_END_REG
929         ret = state->m_rdp->get_end();
930         break;
897         return m_n64->rdp()->get_end();
931898
932899      case 0x08/4:        // DP_CURRENT_REG
933         ret = state->m_rdp->get_current();
934         break;
900         return m_n64->rdp()->get_current();
935901
936902      case 0x0c/4:        // DP_STATUS_REG
937         ret = state->m_rdp->get_status();
938         break;
903         return m_n64->rdp()->get_status();
939904
940905      case 0x10/4:        // DP_CLOCK_REG
941      {
942         if(!(state->m_rdp->get_status() & DP_STATUS_FREEZE))
906         if(!(m_n64->rdp()->get_status() & DP_STATUS_FREEZE))
943907         {
944908            dp_clock += 13;
945            ret = dp_clock;
909            return dp_clock;
946910         }
947911         break;
948      }
949912
950913      default:
951         logerror("dp_reg_r: %08X, %08X at %08X\n", offset, mem_mask, safe_pc());
914         logerror("dp_reg_r: %08X, %08X at %08X\n", offset, mem_mask, m_vr4300->pc());
952915         break;
953916   }
954917
955   return ret;
918   return 0;
956919}
957920
958921WRITE32_MEMBER( n64_periphs::dp_reg_w )
959922{
960   n64_state *state = space.machine().driver_data<n64_state>();
961   UINT32 status = state->m_rdp->get_status();
923   UINT32 status = m_n64->rdp()->get_status();
962924
963925   switch (offset)
964926   {
965927      case 0x00/4:        // DP_START_REG
966928         if(status & DP_STATUS_START_VALID)
929         {
967930            break;
931         }
968932         else
969933         {
970            state->m_rdp->set_status(status | DP_STATUS_START_VALID);
971            state->m_rdp->set_start(data & ~7);
934            m_n64->rdp()->set_status(status | DP_STATUS_START_VALID);
935            m_n64->rdp()->set_start(data & ~7);
972936         }
973937         break;
974938
975939      case 0x04/4:        // DP_END_REG
976940         if(status & DP_STATUS_START_VALID)
977941         {
978            state->m_rdp->set_status(status & ~DP_STATUS_START_VALID);
979            state->m_rdp->set_current(state->m_rdp->get_start());
980            state->m_rdp->set_end(data & ~7);
942            m_n64->rdp()->set_status(status & ~DP_STATUS_START_VALID);
943            m_n64->rdp()->set_current(m_n64->rdp()->get_start());
944            m_n64->rdp()->set_end(data & ~7);
981945            g_profiler.start(PROFILER_USER1);
982            state->m_rdp->process_command_list();
946            m_n64->rdp()->process_command_list();
983947            g_profiler.stop();
984948            break;
985949         }
986950         else
987951         {
988            state->m_rdp->set_end(data & ~7);
952            m_n64->rdp()->set_end(data & ~7);
989953            g_profiler.start(PROFILER_USER1);
990            state->m_rdp->process_command_list();
954            m_n64->rdp()->process_command_list();
991955            g_profiler.stop();
992956            break;
993957         }
994958
995959      case 0x0c/4:        // DP_STATUS_REG
996960      {
997         UINT32 current_status = state->m_rdp->get_status();
961         UINT32 current_status = m_n64->rdp()->get_status();
998962         if (data & 0x00000001)  current_status &= ~DP_STATUS_XBUS_DMA;
999963         if (data & 0x00000002)  current_status |= DP_STATUS_XBUS_DMA;
1000964         if (data & 0x00000004)  current_status &= ~DP_STATUS_FREEZE;
r252875r252876
1002966         if (data & 0x00000010)  current_status &= ~DP_STATUS_FLUSH;
1003967         if (data & 0x00000020)  current_status |= DP_STATUS_FLUSH;
1004968         if (data & 0x00000200)  dp_clock = 0;
1005         state->m_rdp->set_status(current_status);
969         m_n64->rdp()->set_status(current_status);
1006970         break;
1007971      }
1008972
1009973      default:
1010         logerror("dp_reg_w: %08X, %08X, %08X at %08X\n", data, offset, mem_mask, safe_pc());
974         logerror("dp_reg_w: %08X, %08X, %08X at %08X\n", data, offset, mem_mask, m_vr4300->pc());
1011975         break;
1012976   }
1013977}
1014978
1015979TIMER_CALLBACK_MEMBER(n64_periphs::vi_scanline_callback)
1016980{
1017   machine().device<n64_periphs>("rcp")->vi_scanline_tick();
1018}
1019
1020void n64_periphs::vi_scanline_tick()
1021{
1022981   signal_rcp_interrupt(VI_INTERRUPT);
1023982   vi_scanline_timer->adjust(m_screen->time_until_pos(vi_intr >> 1));
1024983}
r252875r252876
11241083         break;
11251084
11261085      default:
1127         logerror("vi_reg_r: %08X, %08X at %08X\n", offset, mem_mask, maincpu->safe_pc());
1086         logerror("vi_reg_r: %08X, %08X at %08X\n", offset, mem_mask, m_vr4300->pc());
11281087         break;
11291088   }
11301089
r252875r252876
11521111            vi_recalculate_resolution();
11531112         }
11541113         vi_width = data;
1155         //state->m_rdp->m_misc_state.m_fb_width = data;
11561114         break;
11571115
11581116      case 0x0c/4:        // VI_INTR_REG
r252875r252876
12141172      */
12151173
12161174      default:
1217         logerror("vi_reg_w: %08X, %08X, %08X at %08X\n", data, offset, mem_mask, maincpu->safe_pc());
1175         logerror("vi_reg_w: %08X, %08X, %08X at %08X\n", data, offset, mem_mask, m_vr4300->pc());
12181176         break;
12191177   }
12201178}
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12891247
12901248void n64_periphs::ai_dma()
12911249{
1292   INT16 *ram = (INT16*)rdram;
1250   INT16 *ram = (INT16*)m_rdram;
12931251   AUDIO_DMA *current = ai_fifo_get_top();
12941252   attotime period;
12951253
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13651323         break;
13661324
13671325      default:
1368         logerror("ai_reg_r: %08X, %08X at %08X\n", offset, mem_mask, maincpu->safe_pc());
1326         logerror("ai_reg_r: %08X, %08X at %08X\n", offset, mem_mask, m_vr4300->pc());
13691327         break;
13701328   }
13711329
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14041362         break;
14051363
14061364      default:
1407         logerror("ai_reg_w: %08X, %08X, %08X at %08X\n", data, offset, mem_mask, maincpu->safe_pc());
1365         logerror("ai_reg_w: %08X, %08X, %08X at %08X\n", data, offset, mem_mask, m_vr4300->pc());
14081366         break;
14091367   }
14101368}
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14141372
14151373TIMER_CALLBACK_MEMBER(n64_periphs::pi_dma_callback)
14161374{
1417   machine().device<n64_periphs>("rcp")->pi_dma_tick();
1418   machine().device("rsp")->execute().yield();
1375   pi_dma_tick();
1376   m_rsp->yield();
14191377}
14201378
14211379void n64_periphs::pi_dma_tick()
14221380{
14231381   bool update_bm = false;
14241382   UINT16 *cart16;
1425   UINT16 *dram16 = (UINT16*)rdram;
1383   UINT16 *dram16 = (UINT16*)m_rdram;
14261384
14271385   UINT32 cart_addr = (pi_cart_addr & 0x0fffffff) >> 1;
14281386   UINT32 dram_addr = (pi_dram_addr & 0x007fffff) >> 1;
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14411399   }
14421400   else if((cart_addr & 0x04000000) == 0x04000000)
14431401   {
1444      cart16 = (UINT16*)n64_sram;
1402      cart16 = (UINT16*)m_sram;
14451403      cart_addr = (pi_cart_addr & 0x0001ffff) >> 1;
14461404   }
14471405   else if((cart_addr & 0x03000000) == 0x03000000 && dd_present)
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15491507         break;
15501508
15511509      default:
1552         logerror("pi_reg_r: %08X, %08X at %08X\n", offset, mem_mask, maincpu->safe_pc());
1510         logerror("pi_reg_r: %08X, %08X at %08X\n", offset, mem_mask, m_vr4300->pc());
15531511         break;
15541512   }
15551513
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15741532            dd_status_reg &= ~DD_ASIC_STATUS_DREQ;
15751533            dd_status_reg &= ~DD_ASIC_STATUS_BM_INT;
15761534            //logerror("Clearing DREQ, INT\n");
1577            machine().device("maincpu")->execute().set_input_line(INPUT_LINE_IRQ1, CLEAR_LINE);
1535            m_vr4300->set_input_line(INPUT_LINE_IRQ1, CLEAR_LINE);
15781536         }
15791537         if(pi_cart_addr == 0x05000000 && dd_present)
15801538         {
15811539            dd_status_reg &= ~DD_ASIC_STATUS_C2_XFER;
15821540            dd_status_reg &= ~DD_ASIC_STATUS_BM_INT;
15831541            //logerror("Clearing C2, INT\n");
1584            machine().device("maincpu")->execute().set_input_line(INPUT_LINE_IRQ1, CLEAR_LINE);
1542            m_vr4300->set_input_line(INPUT_LINE_IRQ1, CLEAR_LINE);
15851543         }
15861544         break;
15871545      }
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16581616         break;
16591617
16601618      default:
1661         logerror("pi_reg_w: %08X, %08X, %08X at %08X\n", data, offset, mem_mask, maincpu->safe_pc());
1619         logerror("pi_reg_w: %08X, %08X, %08X at %08X\n", data, offset, mem_mask, m_vr4300->pc());
16621620         break;
16631621   }
16641622}
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16781636      time recommended for letting the SI devices settle after startup.
16791637      This allows the initialization routines for the SI to see that a
16801638      proper amount of time has passed since system startup. */
1681      machine().device<mips3_device>("maincpu")->burn_cycles(93750000/2);
1639      m_vr4300->burn_cycles(93750000/2);
16821640   }
16831641
16841642   if(offset > 0x1c/4)
16851643   {
1686      logerror("ri_reg_r: %08X, %08X at %08X\n", offset, mem_mask, maincpu->safe_pc());
1644      logerror("ri_reg_r: %08X, %08X at %08X\n", offset, mem_mask, m_vr4300->pc());
16871645      return 0;
16881646   }
16891647   return ri_regs[offset];
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16931651{
16941652   if(offset > 0x1c/4)
16951653   {
1696      logerror("ri_reg_w: %08X, %08X, %08X at %08X\n", data, offset, mem_mask, maincpu->safe_pc());
1654      logerror("ri_reg_w: %08X, %08X, %08X at %08X\n", data, offset, mem_mask, m_vr4300->pc());
16971655      return;
16981656   }
16991657   COMBINE_DATA(&ri_regs[offset]);
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21382096
21392097   if (direction)      // RDRAM -> PIF RAM
21402098   {
2141      UINT32 *src = (UINT32*)&rdram[(si_dram_addr & 0x1fffffff) / 4];
2099      UINT32 *src = m_rdram + ((si_dram_addr & 0x1fffffff) / 4);
21422100
21432101      for(int i = 0; i < 64; i+=4)
21442102      {
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21552113   {
21562114      handle_pif();
21572115
2158      UINT32 *dst = (UINT32*)&rdram[(si_dram_addr & 0x1fffffff) / 4];
2116      UINT32 *dst = m_rdram + ((si_dram_addr & 0x1fffffff) / 4);
21592117
21602118      for(int i = 0; i < 64; i+=4)
21612119      {
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23152273      }
23162274      //logerror("DD Write, Sending Interrupt\n");
23172275      dd_status_reg |= DD_ASIC_STATUS_BM_INT;
2318      machine().device("maincpu")->execute().set_input_line(INPUT_LINE_IRQ1, ASSERT_LINE);
2276      m_vr4300->set_input_line(INPUT_LINE_IRQ1, ASSERT_LINE);
23192277      return;
23202278   }
23212279   else // dd read, BM Mode 1
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23592317      }
23602318      //logerror("DD Read, Sending Interrupt\n");
23612319      dd_status_reg |= DD_ASIC_STATUS_BM_INT;
2362      machine().device("maincpu")->execute().set_input_line(INPUT_LINE_IRQ1, ASSERT_LINE);
2320      m_vr4300->set_input_line(INPUT_LINE_IRQ1, ASSERT_LINE);
23632321      return;
23642322   }
23652323}
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24522410         {
24532411            dd_status_reg &= ~DD_ASIC_STATUS_BM_INT;
24542412            //logerror("DD Read Gap, Clearing INT\n");
2455            machine().device("maincpu")->execute().set_input_line(INPUT_LINE_IRQ1, CLEAR_LINE);
2413            m_vr4300->set_input_line(INPUT_LINE_IRQ1, CLEAR_LINE);
24562414            dd_update_bm();
24572415         }
24582416         break;
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26232581         }
26242582         //logerror("Sending MECHA Int\n");
26252583         dd_status_reg |= DD_ASIC_STATUS_MECHA_INT;
2626         machine().device("maincpu")->execute().set_input_line(INPUT_LINE_IRQ1, ASSERT_LINE);
2584         m_vr4300->set_input_line(INPUT_LINE_IRQ1, ASSERT_LINE);
26272585         break;
26282586
26292587      case 0x10/4: // BM Status
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26642622         if(!(dd_status_reg & DD_ASIC_STATUS_BM_INT) && !(dd_status_reg & DD_ASIC_STATUS_MECHA_INT))
26652623         {
26662624            //logerror("DD Status, Clearing INT\n");
2667            machine().device("maincpu")->execute().set_input_line(INPUT_LINE_IRQ1, CLEAR_LINE);
2625            m_vr4300->set_input_line(INPUT_LINE_IRQ1, CLEAR_LINE);
26682626         }
26692627         if(data & DD_BM_START)
26702628         {
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27422700   device_image_interface *image = dynamic_cast<device_image_interface *>(periphs->m_nvram_image);
27432701
27442702   UINT8 data[0x30800];
2745   memcpy(data, n64_sram, 0x20000);
2703   if (m_sram != NULL)
2704   {
2705      memset(data, 0, 0x20000);
2706   }
2707   else
2708   {
2709      memcpy(data, m_sram, 0x20000);
2710   }
27462711   memcpy(data + 0x20000, periphs->m_save_data.eeprom, 0x800);
27472712   memcpy(data + 0x20800, periphs->m_save_data.mempak[0], 0x8000);
27482713   memcpy(data + 0x28800, periphs->m_save_data.mempak[1], 0x8000);
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27512716
27522717void n64_state::machine_start()
27532718{
2754   rdram = reinterpret_cast<UINT32 *>(memshare("rdram")->ptr());
2755   n64_sram = reinterpret_cast<UINT32 *>(memshare("sram")->ptr());
2756   rsp_imem = reinterpret_cast<UINT32 *>(memshare("rsp_imem")->ptr());
2757   rsp_dmem = reinterpret_cast<UINT32 *>(memshare("rsp_dmem")->ptr());
2719   m_vr4300->mips3drc_set_options(MIPS3DRC_COMPATIBLE_OPTIONS);
27582720
2759   dynamic_cast<mips3_device *>(machine().device("maincpu"))->mips3drc_set_options(MIPS3DRC_COMPATIBLE_OPTIONS);
2760
27612721   /* configure fast RAM regions */
2762   dynamic_cast<mips3_device *>(machine().device("maincpu"))->add_fastram(0x00000000, 0x007fffff, FALSE, rdram);
2722   m_vr4300->add_fastram(0x00000000, 0x007fffff, FALSE, m_rdram);
27632723
27642724   rsp_device *rsp = machine().device<rsp_device>("rsp");
27652725   rsp->rspdrc_set_options(RSPDRC_STRICT_VERIFY);
27662726   rsp->rspdrc_flush_drc_cache();
2767   rsp->rsp_add_dmem(rsp_dmem);
2768   rsp->rsp_add_imem(rsp_imem);
2727   rsp->rsp_add_dmem(m_rsp_dmem);
2728   rsp->rsp_add_imem(m_rsp_imem);
27692729
27702730   /* add a hook for battery save */
27712731   machine().add_notifier(MACHINE_NOTIFY_EXIT, machine_notify_delegate(FUNC(n64_state::n64_machine_stop),this));
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27732733
27742734void n64_state::machine_reset()
27752735{
2776   machine().device("rsp")->execute().set_input_line(INPUT_LINE_HALT, ASSERT_LINE);
2736   m_rsp->set_input_line(INPUT_LINE_HALT, ASSERT_LINE);
27772737}
trunk/src/mame/machine/vsnes.cpp
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197197
198198   ppu1_space.install_readwrite_handler(0x2000, 0x3eff, read8_delegate(FUNC(vsnes_state::vsnes_nt0_r),this), write8_delegate(FUNC(vsnes_state::vsnes_nt0_w),this));
199199
200   m_vrom[0] = memregion("gfx1")->base();
201   m_vrom_size[0] = memregion("gfx1")->bytes();
202   m_vrom_banks = m_vrom_size[0] / 0x400;
200   if (m_gfx1_rom != NULL)
201   {
202      m_vrom[0] = memregion("gfx1")->base();
203      m_vrom_size[0] = memregion("gfx1")->bytes();
204      m_vrom_banks = m_vrom_size[0] / 0x400;
205   }
206   else
207   {
208      m_vrom[0] = NULL;
209      m_vrom_size[0] = 0;
210      m_vrom_banks = 0;
211   }
203212
204213   /* establish chr banks */
205214   /* bank 1 is used already! */
206215   /* DRIVER_INIT is called first - means we can handle this different for VRAM games! */
207   if (nullptr != m_vrom[0])
216   if (m_vrom[0] != nullptr)
208217   {
209218      for (i = 0; i < 8; i++)
210219      {
trunk/src/mame/video/n64.cpp
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9191
9292void n64_state::video_start()
9393{
94   m_rdp = auto_alloc(machine(), n64_rdp(*this));
94   m_rdp = auto_alloc(machine(), n64_rdp(*this, m_rdram, m_rsp_dmem));
9595
9696   m_rdp->set_machine(machine());
9797   m_rdp->init_internal_state();
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203203   //INT32 dither_filter = (n64->vi_control >> 16) & 1;
204204   //INT32 vibuffering = ((n64->vi_control & 2) && fsaa && divot);
205205
206   UINT16* frame_buffer = (UINT16*)&rdram[(vi_origin & 0xffffff) >> 2];
206   UINT16* frame_buffer = (UINT16*)&m_rdram[(vi_origin & 0xffffff) >> 2];
207207   //UINT32 hb = ((n64->vi_origin & 0xffffff) >> 2) >> 1;
208208   //UINT8* hidden_buffer = &m_hidden_bits[hb];
209209
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261261   INT32 gamma_dither = (vi_control >> 2) & 1;
262262   //INT32 vibuffering = ((n64->vi_control & 2) && fsaa && divot);
263263
264   UINT32* frame_buffer32 = (UINT32*)&rdram[(vi_origin & 0xffffff) >> 2];
264   UINT32* frame_buffer32 = (UINT32*)&m_rdram[(vi_origin & 0xffffff) >> 2];
265265
266266   const INT32 hdiff = (vi_hstart & 0x3ff) - ((vi_hstart >> 16) & 0x3ff);
267267   const float hcoeff = ((float)(vi_xscale & 0xfff) / (1 << 10));
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843843   UINT16 zval = m_z_com_table[z & 0x3ffff]|(enc >> 2);
844844   if(zcurpixel <= MEM16_LIMIT)
845845   {
846      ((UINT16*)rdram)[zcurpixel ^ WORD_ADDR_XOR] = zval;
846      ((UINT16*)m_rdram)[zcurpixel ^ WORD_ADDR_XOR] = zval;
847847   }
848848   if(dzcurpixel <= MEM8_LIMIT)
849849   {
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10991099{
11001100   if (m_status & 0x1)     // XBUS_DMEM_DMA enabled
11011101   {
1102      return rsp_dmem[(address & 0xfff) / 4];
1102      return m_dmem[(address & 0xfff) / 4];
11031103   }
11041104   else
11051105   {
1106      return rdram[((address & 0xffffff) / 4)];
1106      return m_rdram[((address & 0xffffff) / 4)];
11071107   }
11081108}
11091109
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31243124
31253125/*****************************************************************************/
31263126
3127n64_rdp::n64_rdp(n64_state &state) : poly_manager<UINT32, rdp_poly_state, 8, 32000>(state.machine())
3127n64_rdp::n64_rdp(n64_state &state, UINT32* rdram, UINT32* dmem) : poly_manager<UINT32, rdp_poly_state, 8, 32000>(state.machine())
31283128{
31293129   ignore = false;
31303130   dolog = false;
3131
3132   m_rdram = rdram;
3133   m_dmem = dmem;
3134
31313135   m_aux_buf_ptr = 0;
31323136   m_aux_buf = nullptr;
31333137   m_pipe_clean = true;
trunk/src/mame/video/n64.h
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6969#endif
7070
7171#if RDP_RANGE_CHECK
72#define RREADADDR8(in) ((rdp_range_check((in))) ? 0 : (((UINT8*)rdram)[(in) ^ BYTE_ADDR_XOR]))
73#define RREADIDX16(in) ((rdp_range_check((in) << 1)) ? 0 : (((UINT16*)rdram)[(in) ^ WORD_ADDR_XOR]))
74#define RREADIDX32(in) ((rdp_range_check((in) << 2)) ? 0 : rdram[(in)])
72#define RREADADDR8(in) ((rdp_range_check((in))) ? 0 : (((UINT8*)m_rdram)[(in) ^ BYTE_ADDR_XOR]))
73#define RREADIDX16(in) ((rdp_range_check((in) << 1)) ? 0 : (((UINT16*)m_rdram)[(in) ^ WORD_ADDR_XOR]))
74#define RREADIDX32(in) ((rdp_range_check((in) << 2)) ? 0 : m_rdram[(in)])
7575
76#define RWRITEADDR8(in, val)    if(rdp_range_check((in))) { printf("Write8: Address %08x out of range!\n", (in)); fflush(stdout); fatalerror("Address %08x out of range!\n", (in)); } else { ((UINT8*)rdram)[(in) ^ BYTE_ADDR_XOR] = val;}
77#define RWRITEIDX16(in, val)    if(rdp_range_check((in) << 1)) { printf("Write16: Address %08x out of range!\n", ((object.m_misc_state.m_fb_address >> 1) + curpixel) << 1); fflush(stdout); fatalerror("Address out of range\n"); } else { ((UINT16*)rdram)[(in) ^ WORD_ADDR_XOR] = val;}
78#define RWRITEIDX32(in, val)    if(rdp_range_check((in) << 2)) { printf("Write32: Address %08x out of range!\n", (in) << 2); fflush(stdout); fatalerror("Address %08x out of range!\n", (in) << 2); } else { rdram[(in)] = val;}
76#define RWRITEADDR8(in, val)    if(rdp_range_check((in))) { printf("Write8: Address %08x out of range!\n", (in)); fflush(stdout); fatalerror("Address %08x out of range!\n", (in)); } else { ((UINT8*)m_rdram)[(in) ^ BYTE_ADDR_XOR] = val;}
77#define RWRITEIDX16(in, val)    if(rdp_range_check((in) << 1)) { printf("Write16: Address %08x out of range!\n", ((object.m_misc_state.m_fb_address >> 1) + curpixel) << 1); fflush(stdout); fatalerror("Address out of range\n"); } else { ((UINT16*)m_rdram)[(in) ^ WORD_ADDR_XOR] = val;}
78#define RWRITEIDX32(in, val)    if(rdp_range_check((in) << 2)) { printf("Write32: Address %08x out of range!\n", (in) << 2); fflush(stdout); fatalerror("Address %08x out of range!\n", (in) << 2); } else { m_rdram[(in)] = val;}
7979#else
80#define RREADADDR8(in) (((UINT8*)rdram)[(in) ^ BYTE_ADDR_XOR])
81#define RREADIDX16(in) (((UINT16*)rdram)[(in) ^ WORD_ADDR_XOR])
82#define RREADIDX32(in) (rdram[(in)])
80#define RREADADDR8(in) (((UINT8*)m_rdram)[(in) ^ BYTE_ADDR_XOR])
81#define RREADIDX16(in) (((UINT16*)m_rdram)[(in) ^ WORD_ADDR_XOR])
82#define RREADIDX32(in) (m_rdram[(in)])
8383
84#define RWRITEADDR8(in, val)    ((UINT8*)rdram)[(in) ^ BYTE_ADDR_XOR] = val;
85#define RWRITEIDX16(in, val)    ((UINT16*)rdram)[(in) ^ WORD_ADDR_XOR] = val;
86#define RWRITEIDX32(in, val)    rdram[(in)] = val
84#define RWRITEADDR8(in, val)    ((UINT8*)m_rdram)[(in) ^ BYTE_ADDR_XOR] = val;
85#define RWRITEIDX16(in, val)    ((UINT16*)m_rdram)[(in) ^ WORD_ADDR_XOR] = val;
86#define RWRITEIDX32(in, val)    m_rdram[(in)] = val
8787#endif
8888
89#define U_RREADADDR8(in) (((UINT8*)rdram)[(in) ^ BYTE_ADDR_XOR])
90#define U_RREADIDX16(in) (((UINT16*)rdram)[(in) ^ WORD_ADDR_XOR])
91#define U_RREADIDX32(in) (rdram[(in)])
89#define U_RREADADDR8(in) (((UINT8*)m_rdram)[(in) ^ BYTE_ADDR_XOR])
90#define U_RREADIDX16(in) (((UINT16*)m_rdram)[(in) ^ WORD_ADDR_XOR])
91#define U_RREADIDX32(in) (m_rdram[(in)])
9292
9393#define GETLOWCOL(x)    (((x) & 0x3e) << 2)
9494#define GETMEDCOL(x)    (((x) & 0x7c0) >> 3)
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133133class n64_rdp : public poly_manager<UINT32, rdp_poly_state, 8, 32000>
134134{
135135public:
136   n64_rdp(n64_state &state);
136   n64_rdp(n64_state &state, UINT32* rdram, UINT32* dmem);
137137
138138   running_machine &machine() const { assert(m_machine != nullptr); return *m_machine; }
139139
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331331   compute_cvg_t   m_compute_cvg[2];
332332
333333   running_machine* m_machine;
334   UINT32*         m_rdram;
335   UINT32*         m_dmem;
334336
335337   combine_modes_t m_combine;
336338   bool            m_pending_mode_block;
trunk/src/mame/video/rdptpipe.cpp
r252875r252876
2525{
2626   n64_state* state = machine.driver_data<n64_state>();
2727
28   m_rdp = state->m_rdp;
28   m_rdp = state->rdp();
2929
3030   for(INT32 i = 0; i < 0x10000; i++)
3131   {
trunk/src/mame/video/sega16sp.cpp
r252875r252876
826826
827827sega_sys16b_sprite_device::sega_sys16b_sprite_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
828828   : sega_16bit_sprite_device(mconfig, SEGA_SYS16B_SPRITES, "Sega System 16B Sprites", tag, owner, "sega_16bit_sprite", __FILE__)
829   , m_sprite_region(*this, tag)
829830{
830831   set_local_origin(184, 0x00, -184, 0);
831832}
r252875r252876
867868   //  Note that the zooming described below is 100% accurate to the real board.
868869   //
869870
871   // if the game does not have sprites, don't try to draw anything
872   if (m_sprite_region == NULL)
873   {
874      return;
875   }
876
870877   // render the sprites in order
871   const UINT16 *spritebase = reinterpret_cast<const UINT16 *>(region()->base());
872   UINT8 numbanks = region()->bytes() / 0x20000;
878   const UINT16 *spritebase = reinterpret_cast<const UINT16 *>(m_sprite_region->base());
879   UINT8 numbanks = m_sprite_region->bytes() / 0x20000;
873880   UINT16 *ramend = spriteram() + spriteram_elements();
874881   for (UINT16 *data = spriteram(); data < ramend; data += 8)
875882   {
trunk/src/mame/video/sega16sp.h
r252875r252876
201201protected:
202202   // subclass overrides
203203   virtual void draw(bitmap_ind16 &bitmap, const rectangle &cliprect) override;
204
205   // memory regions
206   optional_memory_region      m_sprite_region;
204207};
205208
206209

https://github.com/mamedev/mame/commit/177eaa42089e1cfb8f3a553bfc40704365d15984

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