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r41808 Friday 20th November, 2015 at 16:15:30 UTC by Ryan Holtz
Fix remainder of this == NULL checks from Tafoids run

[/branches/code_cleanup/src/mame/drivers]	aleck64.cpp arsystems.cpp n64.cpp ninjakd2.cpp prestige.cpp segas16a.cpp
[/branches/code_cleanup/src/mame/includes]	n64.h ninjakd2.h vsnes.h
[/branches/code_cleanup/src/mame/machine]	n64.cpp vsnes.cpp
[/branches/code_cleanup/src/mame/video]	n64.cpp n64.h rdptpipe.cpp sega16sp.cpp sega16sp.h

branches/code_cleanup/src/mame/drivers/aleck64.cpp

r250319	r250320
184	184	m_e90_pal(*this,"e90pal"),
185	185	m_dip_read_offset(0) { }
186	186
187		optional_shared_ptr<UINT32> m_e90_vram;
188		optional_shared_ptr<UINT32> m_e90_pal;
189	187	DECLARE_DRIVER_INIT(aleck64);
190	188	DECLARE_WRITE32_MEMBER(aleck_dips_w);
191	189	DECLARE_READ32_MEMBER(aleck_dips_r);
192	190	DECLARE_READ16_MEMBER(e90_prot_r);
193	191	DECLARE_WRITE16_MEMBER(e90_prot_w);
	192
194	193	UINT32 screen_update_e90(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
195	194
	195	protected:
	196	optional_shared_ptr<UINT32> m_e90_vram;
	197	optional_shared_ptr<UINT32> m_e90_pal;
	198
196	199	private:
197	200	UINT32 m_dip_read_offset;
198	201	};

branches/code_cleanup/src/mame/drivers/arsystems.cpp

r250319	r250320
62	62	{
63	63	public:
64	64	arcadia_amiga_state(const machine_config &mconfig, device_type type, const char *tag)
65		: amiga_state(mconfig, type, tag) { }
	65	: amiga_state(mconfig, type, tag)
	66	, m_bios_region(*this, "user2")
	67	{
	68	}
66	69
67		UINT8 m_coin_counter[2];
68
69	70	DECLARE_WRITE16_MEMBER(arcadia_multibios_change_game);
70	71	DECLARE_CUSTOM_INPUT_MEMBER(coin_counter_r);
71	72	DECLARE_INPUT_CHANGED_MEMBER(coin_changed_callback);
r250319	r250320
91	92
92	93	protected:
93	94	virtual void machine_reset();
	95
	96	optional_memory_region m_bios_region;
	97
	98	UINT8 m_coin_counter[2];
94	99	};
95	100
96	101
r250319	r250320
922	927	m_agnus_id = AGNUS_HR_NTSC;
923	928	m_denise_id = DENISE;
924	929
925		/* OnePlay bios is encrypted, TenPlay is not */
926		UINT16 *biosrom = (UINT16 *)memregion("user2")->base();
	930	if (m_bios_region != NULL)
	931	{
	932	/* OnePlay bios is encrypted, TenPlay is not */
	933	UINT16 *rom = (UINT16 *)m_bios_region->base();
927	934
928		if (biosrom)
929		if (biosrom[0] != 0x4afc)
	935	if (rom[0] != 0x4afc)
	936	{
930	937	generic_decode("user2", 6, 1, 0, 2, 3, 4, 5, 7);
	938	}
	939	}
931	940	}
932	941
933	942

branches/code_cleanup/src/mame/drivers/n64.cpp

r250319	r250320
334	334	//printf("Loading\n");
335	335	UINT8 data[0x30800];
336	336	battery_image->battery_load(data, 0x30800, 0x00);
337		//memcpy(n64_sram, data, 0x20000);
338		memcpy(memshare("sram")->ptr(), data, 0x20000);
	337	if (m_sram != NULL)
	338	{
	339	memcpy(m_sram, data, 0x20000);
	340	}
339	341	memcpy(periphs->m_save_data.eeprom, data + 0x20000, 0x800);
340	342	memcpy(periphs->m_save_data.mempak[0], data + 0x20800, 0x8000);
341	343	memcpy(periphs->m_save_data.mempak[1], data + 0x28800, 0x8000);

branches/code_cleanup/src/mame/drivers/ninjakd2.cpp

r250319	r250320
172	172
173	173	SAMPLES_START_CB_MEMBER(ninjakd2_state::ninjakd2_init_samples)
174	174	{
175		const UINT8* const rom = memregion("pcm")->base();
176		const int length = memregion("pcm")->bytes();
	175	if (m_pcm_region == NULL)
	176	{
	177	return;
	178	}
	179
	180	const UINT8* const rom = m_pcm_region->base();
	181	const int length = m_pcm_region->bytes();
177	182	INT16* sampledata = auto_alloc_array(machine(), INT16, length);
178	183
179	184	// convert unsigned 8-bit PCM to signed 16-bit
180	185	for (int i = 0; i < length; ++i)
	186	{
181	187	sampledata[i] = rom[i] << 7;
	188	}
182	189
183	190	m_sampledata = sampledata;
184	191	}
185	192
186	193	WRITE8_MEMBER(ninjakd2_state::ninjakd2_pcm_play_w)
187	194	{
188		const UINT8* const rom = memregion("pcm")->base();
189
190	195	// only Ninja Kid II uses this
191		if (rom)
	196	if (m_pcm_region == NULL)
192	197	{
193		const int length = memregion("pcm")->bytes();
194		const int start = data << 8;
	198	return;
	199	}
195	200
196		// find end of sample
197		int end = start;
198		while (end < length && rom[end] != 0x00)
199		++end;
	201	const UINT8* const rom = m_pcm_region->base();
	202	const int length = m_pcm_region->bytes();
	203	const int start = data << 8;
200	204
201		if (end - start)
202		m_pcm->start_raw(0, &m_sampledata[start], end - start, NE555_FREQUENCY);
203		else
204		m_pcm->stop(0);
	205	// find end of sample
	206	int end = start;
	207	while (end < length && rom[end] != 0x00)
	208	{
	209	++end;
205	210	}
	211
	212	if (end - start)
	213	{
	214	m_pcm->start_raw(0, &m_sampledata[start], end - start, NE555_FREQUENCY);
	215	}
	216	else
	217	{
	218	m_pcm->stop(0);
	219	}
206	220	}
207	221
208	222
r250319	r250320
453	467	AM_RANGE(0xf000, 0xf000) AM_WRITE(ninjakd2_pcm_play_w)
454	468	ADDRESS_MAP_END
455	469
	470	static ADDRESS_MAP_START( ninjakid_nopcm_sound_cpu, AS_PROGRAM, 8, ninjakd2_state )
	471	AM_RANGE(0x0000, 0x7fff) AM_ROM
	472	AM_RANGE(0x8000, 0xbfff) AM_ROM
	473	AM_RANGE(0xc000, 0xc7ff) AM_RAM
	474	AM_RANGE(0xe000, 0xe000) AM_READ(soundlatch_byte_r)
	475	AM_RANGE(0xf000, 0xf000) AM_NOP
	476	ADDRESS_MAP_END
456	477
457	478	static ADDRESS_MAP_START( decrypted_opcodes_map, AS_DECRYPTED_OPCODES, 8, ninjakd2_state )
458	479	AM_RANGE(0x0000, 0x7fff) AM_ROM AM_SHARE("decrypted_opcodes")
r250319	r250320
972	993	MCFG_CPU_MODIFY("maincpu")
973	994	MCFG_CPU_PROGRAM_MAP(mnight_main_cpu)
974	995
	996	MCFG_CPU_MODIFY("soundcpu")
	997	MCFG_CPU_PROGRAM_MAP(ninjakid_nopcm_sound_cpu)
	998
975	999	/* video hardware */
976	1000	MCFG_VIDEO_START_OVERRIDE(ninjakd2_state,mnight)
977	1001
r250319	r250320
980	1004	MACHINE_CONFIG_END
981	1005
982	1006	static MACHINE_CONFIG_DERIVED( arkarea, ninjakd2_core )
983
984	1007	/* basic machine hardware */
985	1008	MCFG_CPU_MODIFY("maincpu")
986	1009	MCFG_CPU_PROGRAM_MAP(mnight_main_cpu)
987	1010
	1011	MCFG_CPU_MODIFY("soundcpu")
	1012	MCFG_CPU_PROGRAM_MAP(ninjakid_nopcm_sound_cpu)
	1013
988	1014	/* video hardware */
989	1015	MCFG_VIDEO_START_OVERRIDE(ninjakd2_state,arkarea)
990	1016
r250319	r250320
998	1024	MCFG_CPU_MODIFY("maincpu")
999	1025	MCFG_CPU_PROGRAM_MAP(robokid_main_cpu)
1000	1026
	1027	MCFG_CPU_MODIFY("soundcpu")
	1028	MCFG_CPU_PROGRAM_MAP(ninjakid_nopcm_sound_cpu)
	1029
1001	1030	/* video hardware */
1002	1031	MCFG_GFXDECODE_MODIFY("gfxdecode", robokid)
1003	1032	MCFG_PALETTE_MODIFY("palette")
r250319	r250320
1016	1045	MCFG_CPU_MODIFY("maincpu")
1017	1046	MCFG_CPU_PROGRAM_MAP(omegaf_main_cpu)
1018	1047
	1048	MCFG_CPU_MODIFY("soundcpu")
	1049	MCFG_CPU_PROGRAM_MAP(ninjakid_nopcm_sound_cpu)
	1050
1019	1051	MCFG_MACHINE_START_OVERRIDE(ninjakd2_state,omegaf)
1020	1052	MCFG_MACHINE_RESET_OVERRIDE(ninjakd2_state,omegaf)
1021	1053

branches/code_cleanup/src/mame/drivers/prestige.cpp

r250319	r250320
622	622	m_cart_rom = memregion(region_tag.assign(m_cart->tag()).append(GENERIC_ROM_REGION_TAG).c_str());
623	623
624	624	UINT8 *rom = memregion("maincpu")->base();
625		UINT8 *cart = m_cart_rom->base();
	625	UINT8 *cart = NULL;
	626	if (m_cart_rom != NULL)
	627	{
	628	cart = m_cart_rom->base();
	629	}
626	630	UINT8 *ram = m_ram->pointer();
627	631	memset(ram, 0x00, m_ram->size());
628	632

branches/code_cleanup/src/mame/drivers/segas16a.cpp

r250319	r250320
988	988	AM_RANGE(0xc0, 0xc0) AM_MIRROR(0x3f) AM_READ(sound_data_r)
989	989	ADDRESS_MAP_END
990	990
	991	static ADDRESS_MAP_START( sound_no7751_portmap, AS_IO, 8, segas16a_state )
	992	ADDRESS_MAP_UNMAP_HIGH
	993	ADDRESS_MAP_GLOBAL_MASK(0xff)
	994	AM_RANGE(0x00, 0x01) AM_MIRROR(0x3e) AM_DEVREADWRITE("ymsnd", ym2151_device, read, write)
	995	AM_RANGE(0x80, 0x80) AM_MIRROR(0x3f) AM_NOP
	996	AM_RANGE(0xc0, 0xc0) AM_MIRROR(0x3f) AM_READ(sound_data_r)
	997	ADDRESS_MAP_END
991	998
992	999
993	1000	//**************************************************************************
r250319	r250320
1964	1971
1965	1972
1966	1973	static MACHINE_CONFIG_DERIVED( system16a_no7751, system16a )
	1974	MCFG_CPU_MODIFY("soundcpu")
	1975	MCFG_CPU_IO_MAP(sound_no7751_portmap)
	1976
1967	1977	MCFG_DEVICE_REMOVE("n7751")
1968	1978	MCFG_DEVICE_REMOVE("dac")
1969	1979
r250319	r250320
1987	1997	*/
1988	1998
1989	1999	static MACHINE_CONFIG_DERIVED( system16a_fd1089a_no7751, system16a_fd1089a )
	2000	MCFG_CPU_MODIFY("soundcpu")
	2001	MCFG_CPU_IO_MAP(sound_no7751_portmap)
	2002
1990	2003	MCFG_DEVICE_REMOVE("n7751")
1991	2004	MCFG_DEVICE_REMOVE("dac")
1992	2005
r250319	r250320
1995	2008	MACHINE_CONFIG_END
1996	2009
1997	2010	static MACHINE_CONFIG_DERIVED( system16a_fd1089b_no7751, system16a_fd1089b )
	2011	MCFG_CPU_MODIFY("soundcpu")
	2012	MCFG_CPU_IO_MAP(sound_no7751_portmap)
	2013
1998	2014	MCFG_DEVICE_REMOVE("n7751")
1999	2015	MCFG_DEVICE_REMOVE("dac")
2000	2016
r250319	r250320
2003	2019	MACHINE_CONFIG_END
2004	2020
2005	2021	static MACHINE_CONFIG_DERIVED( system16a_fd1094_no7751, system16a_fd1094 )
	2022	MCFG_CPU_MODIFY("soundcpu")
	2023	MCFG_CPU_IO_MAP(sound_no7751_portmap)
	2024
2006	2025	MCFG_DEVICE_REMOVE("n7751")
2007	2026	MCFG_DEVICE_REMOVE("dac")
2008	2027

branches/code_cleanup/src/mame/includes/n64.h

r250319	r250320
4	4	#define _INCLUDES_N64_H_
5	5
6	6	#include "cpu/rsp/rsp.h"
	7	#include "cpu/mips/mips3.h"
7	8	#include "sound/dmadac.h"
8	9
9		/*----------- forward decls -----------*/
10
11	10	/*----------- driver state -----------*/
12	11
13	12	class n64_rdp;
r250319	r250320
16	15	{
17	16	public:
18	17	n64_state(const machine_config &mconfig, device_type type, const char *tag)
19		: driver_device(mconfig, type, tag) ,
20		m_maincpu(*this, "maincpu") { }
	18	: driver_device(mconfig, type, tag)
	19	, m_vr4300(*this, "maincpu")
	20	, m_rsp(*this, "rsp")
	21	, m_sram(*this, "sram")
	22	, m_rdram(*this, "rdram")
	23	, m_rsp_imem(*this, "rsp_imem")
	24	, m_rsp_dmem(*this, "rsp_dmem")
	25	{
	26	}
21	27
22		/* video-related */
23		n64_rdp *m_rdp;
24
25	28	virtual void machine_start();
26	29	virtual void machine_reset();
27	30	virtual void video_start();
r250319	r250320
29	32
30	33	UINT32 screen_update_n64(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
31	34	void screen_eof_n64(screen_device &screen, bool state);
32		required_device<cpu_device> m_maincpu;
	35
	36	// Getters
	37	n64_rdp* rdp() { return m_rdp; }
	38	UINT32* rdram() { return m_rdram; }
	39	UINT32* sram() { return m_sram; }
	40	UINT32* rsp_imem() { return m_rsp_imem; }
	41	UINT32* rsp_dmem() { return m_rsp_dmem; }
	42
	43	protected:
	44	required_device<mips3_device> m_vr4300;
	45	required_device<rsp_device> m_rsp;
	46
	47	optional_shared_ptr<UINT32> m_sram;
	48	required_shared_ptr<UINT32> m_rdram;
	49	required_shared_ptr<UINT32> m_rsp_imem;
	50	required_shared_ptr<UINT32> m_rsp_dmem;
	51
	52	/* video-related */
	53	n64_rdp *m_rdp;
33	54	};
34	55
35	56	/*----------- devices -----------*/
r250319	r250320
98	119	void ai_timer_tick();
99	120	void pi_dma_tick();
100	121	void si_dma_tick();
101		void vi_scanline_tick();
102	122	void reset_tick();
103	123	void video_update(bitmap_rgb32 &bitmap);
104	124
r250319	r250320
137	157	void poll_reset_button(bool button);
138	158
139	159	UINT32 dp_clock;
	160
140	161	protected:
141	162	// device-level overrides
142	163	virtual void device_start();
143	164	virtual void device_reset();
144	165
145	166	private:
146		address_space *mem_map;
147		device_t *maincpu;
148		device_t *rspcpu;
	167	n64_state* m_n64;
	168	address_space *m_mem_map;
	169	mips3_device *m_vr4300;
	170	rsp_device *m_rsp;
149	171
	172	UINT32 *m_rdram;
	173	UINT32 *m_sram;
	174	UINT32 *m_rsp_imem;
	175	UINT32 *m_rsp_dmem;
	176
150	177	void clear_rcp_interrupt(int interrupt);
151	178
152	179	bool reset_held;
r250319	r250320
371	398	{0x0,0x5F15E0,0xB79D00,0x10801A0,0x1523720,0x1963D80,0x1D414C0,0x20BBCE0,
372	399	0x23196E0,0x28A1E00,0x2DF5DC0,0x3299340,0x36D99A0,0x3AB70E0,0x3E31900,0x4149200};
373	400
374
375
376		extern UINT32 *n64_sram;
377		extern UINT32 *rdram;
378		extern UINT32 *rsp_imem;
379		extern UINT32 *rsp_dmem;
380
381	401	extern void dp_full_sync(running_machine &machine);
382	402
383	403	#endif

branches/code_cleanup/src/mame/includes/ninjakd2.h

r250319	r250320
16	16	m_maincpu(*this,"maincpu"),
17	17	m_soundcpu(*this, "soundcpu"),
18	18	m_pcm(*this, "pcm"),
	19	m_pcm_region(*this, "pcm"),
19	20	m_bg_videoram(*this, "bg_videoram"),
20	21	m_fg_videoram(*this, "fg_videoram"),
21	22	m_spriteram(*this, "spriteram"),
r250319	r250320
28	29	required_device<cpu_device> m_maincpu;
29	30	required_device<cpu_device> m_soundcpu;
30	31	optional_device<samples_device> m_pcm;
	32	optional_memory_region m_pcm_region;
31	33	optional_shared_ptr<UINT8> m_bg_videoram;
32	34	required_shared_ptr<UINT8> m_fg_videoram;
33	35	required_shared_ptr<UINT8> m_spriteram;

branches/code_cleanup/src/mame/includes/vsnes.h

r250319	r250320
6	6	{
7	7	public:
8	8	vsnes_state(const machine_config &mconfig, device_type type, const char *tag)
9		: driver_device(mconfig, type, tag),
10		m_maincpu(*this, "maincpu"),
11		m_subcpu(*this, "sub"),
12		m_ppu1(*this, "ppu1"),
13		m_ppu2(*this, "ppu2"),
14		m_work_ram(*this, "work_ram"),
15		m_work_ram_1(*this, "work_ram_1")
16		{ }
	9	: driver_device(mconfig, type, tag)
	10	, m_maincpu(*this, "maincpu")
	11	, m_subcpu(*this, "sub")
	12	, m_ppu1(*this, "ppu1")
	13	, m_ppu2(*this, "ppu2")
	14	, m_work_ram(*this, "work_ram")
	15	, m_work_ram_1(*this, "work_ram_1")
	16	, m_gfx1_rom(*this, "gfx1")
	17	{
	18	}
17	19
18	20	required_device<cpu_device> m_maincpu;
19	21	optional_device<cpu_device> m_subcpu;
r250319	r250320
22	24
23	25	required_shared_ptr<UINT8> m_work_ram;
24	26	optional_shared_ptr<UINT8> m_work_ram_1;
	27
	28	optional_memory_region m_gfx1_rom;
	29
25	30	int m_coin;
26	31	int m_do_vrom_bank;
27	32	int m_input_latch[4];

branches/code_cleanup/src/mame/machine/n64.cpp

r250319	r250320
9	9	#include "includes/n64.h"
10	10	#include "video/n64.h"
11	11
12		UINT32 *n64_sram;
13		UINT32 *rdram;
14		UINT32 *rsp_imem;
15		UINT32 *rsp_dmem;
16
17	12	// device type definition
18	13	const device_type N64PERIPH = &device_creator<n64_periphs>;
19	14
20
21
22
23	15	n64_periphs::n64_periphs(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
24	16	: device_t(mconfig, N64PERIPH, "N64 Periphal Chips", tag, owner, clock, "n64_periphs", __FILE__)
25	17	, device_video_interface(mconfig, *this)
r250319	r250320
49	41	void n64_periphs::reset_tick()
50	42	{
51	43	reset_timer->adjust(attotime::never);
52		maincpu->reset();
53		maincpu->execute().set_input_line(INPUT_LINE_IRQ2, CLEAR_LINE);
54		rspcpu->reset();
55		rspcpu->execute().set_input_line(INPUT_LINE_HALT, ASSERT_LINE);
56		rspcpu->state().set_state_int(RSP_SR, rspcpu->state().state_int(RSP_SR) | RSP_STATUS_HALT);
	44	m_vr4300->reset();
	45	m_vr4300->set_input_line(INPUT_LINE_IRQ2, CLEAR_LINE);
	46	m_rsp->reset();
	47	m_rsp->set_input_line(INPUT_LINE_HALT, ASSERT_LINE);
	48	m_rsp->set_state_int(RSP_SR, m_rsp->state_int(RSP_SR) | RSP_STATUS_HALT);
57	49	reset_held = false;
58	50	cic_status = 0;
59	51	memset(pif_ram, 0, sizeof(pif_ram));
r250319	r250320
104	96	reset_held = button;
105	97	if(!old_held && reset_held)
106	98	{
107		machine().device("maincpu")->execute().set_input_line(INPUT_LINE_IRQ2, ASSERT_LINE);
	99	m_vr4300->set_input_line(INPUT_LINE_IRQ2, ASSERT_LINE);
108	100	}
109	101	else if(old_held && reset_held)
110	102	{
r250319	r250320
123	115	si_dma_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(n64_periphs::si_dma_callback),this));
124	116	vi_scanline_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(n64_periphs::vi_scanline_callback),this));
125	117	reset_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(n64_periphs::reset_timer_callback),this));
	118	m_n64 = machine().driver_data<n64_state>();
126	119	}
127	120
128	121	void n64_periphs::device_reset()
129	122	{
130	123	UINT32 *cart = (UINT32*)machine().root_device().memregion("user2")->base();
131	124
132		maincpu = machine().device("maincpu");
133		rspcpu = machine().device("rsp");
134		mem_map = &maincpu->memory().space(AS_PROGRAM);
	125	m_vr4300 = machine().device<mips3_device>("maincpu");
	126	m_rsp = machine().device<rsp_device>("rsp");
	127	m_mem_map = &m_vr4300->space(AS_PROGRAM);
135	128
	129	m_rdram = m_n64->rdram();
	130	m_rsp_imem = m_n64->rsp_imem();
	131	m_rsp_dmem = m_n64->rsp_dmem();
	132	m_sram = m_n64->sram();
	133
136	134	mi_version = 0x01010101;
137	135	mi_interrupt = 0;
138	136	mi_intr_mask = 0;
r250319	r250320
238	236	pif_ram[0x26] = 0x3f;
239	237	pif_ram[0x27] = 0x3f;
240	238	cic_type=2;
241		mem_map->write_dword(0x00000318, 0x800000); /* RDRAM Size */
	239	m_mem_map->write_dword(0x00000318, 0x800000); /* RDRAM Size */
242	240
243	241	if (boot_checksum == U64(0x00000000001ff230))
244	242	{
r250319	r250320
274	272	pif_ram[0x26] = 0x91;
275	273	pif_ram[0x27] = 0x3f;
276	274	cic_type=5;
277		mem_map->write_dword(0x000003f0, 0x800000);
	275	m_mem_map->write_dword(0x000003f0, 0x800000);
278	276	}
279	277	else if (boot_checksum == U64(0x000000d6d5de4ba0))
280	278	{
r250319	r250320
329	327	break;
330	328
331	329	default:
332		logerror("mi_reg_r: %08X, %08X at %08X\n", offset, mem_mask, mem_map->device().safe_pc());
	330	logerror("mi_reg_r: %08X, %08X at %08X\n", offset, mem_mask, m_vr4300->pc());
333	331	break;
334	332	}
335	333
r250319	r250320
414	412	}
415	413
416	414	default:
417		logerror("mi_reg_w: %08X, %08X, %08X at %08X\n", data, offset, mem_mask, maincpu->safe_pc());
	415	logerror("mi_reg_w: %08X, %08X, %08X at %08X\n", data, offset, mem_mask, m_vr4300->pc());
418	416	break;
419	417	}
420	418	}
r250319	r250320
428	426	{
429	427	if (mi_intr_mask & mi_interrupt)
430	428	{
431		machine().device("maincpu")->execute().set_input_line(INPUT_LINE_IRQ0, ASSERT_LINE);
	429	m_vr4300->set_input_line(INPUT_LINE_IRQ0, ASSERT_LINE);
432	430	}
433	431	else
434	432	{
435		machine().device("maincpu")->execute().set_input_line(INPUT_LINE_IRQ0, CLEAR_LINE);
	433	m_vr4300->set_input_line(INPUT_LINE_IRQ0, CLEAR_LINE);
436	434	}
437	435	}
438	436
r250319	r250320
529	527	{
530	528	if(offset > 0x24/4)
531	529	{
532		logerror("rdram_reg_r: %08X, %08X at %08X\n", offset, mem_mask, maincpu->safe_pc());
	530	logerror("rdram_reg_r: %08X, %08X at %08X\n", offset, mem_mask, m_vr4300->pc());
533	531	return 0;
534	532	}
535	533	return rdram_regs[offset];
r250319	r250320
539	537	{
540	538	if(offset > 0x24/4)
541	539	{
542		logerror("rdram_reg_w: %08X, %08X, %08X at %08X\n", data, offset, mem_mask, maincpu->safe_pc());
	540	logerror("rdram_reg_w: %08X, %08X, %08X at %08X\n", data, offset, mem_mask, m_vr4300->pc());
543	541	return;
544	542	}
545	543	COMBINE_DATA(&rdram_regs[offset]);
r250319	r250320
570	568	length = 0x1000 - (sp_mem_addr & 0xfff);
571	569	}
572	570
573		UINT32 *sp_mem[2] = { rsp_dmem, rsp_imem };
	571	UINT32 *sp_mem[2] = { m_rsp_dmem, m_rsp_imem };
574	572
575	573	int sp_mem_page = (sp_mem_addr >> 12) & 1;
576	574	if(direction == 0)// RDRAM -> I/DMEM
r250319	r250320
582	580
583	581	for(int i = 0; i < length / 4; i++)
584	582	{
585		sp_mem[sp_mem_page][(dst + i) & 0x3ff] = rdram[src + i];
	583	sp_mem[sp_mem_page][(dst + i) & 0x3ff] = m_rdram[src + i];
586	584	}
587	585
588	586	sp_mem_addr += length;
r250319	r250320
600	598
601	599	for(int i = 0; i < length / 4; i++)
602	600	{
603		rdram[dst + i] = sp_mem[sp_mem_page][(src + i) & 0x3ff];
	601	m_rdram[dst + i] = sp_mem[sp_mem_page][(src + i) & 0x3ff];
604	602	}
605	603
606	604	sp_mem_addr += length;
r250319	r250320
615	613	{
616	614	if (data & 0x1)
617	615	{
618		rspcpu->execute().set_input_line(INPUT_LINE_HALT, ASSERT_LINE);
619		rspcpu->state().set_state_int(RSP_SR, rspcpu->state().state_int(RSP_SR) | RSP_STATUS_HALT);
	616	m_rsp->set_input_line(INPUT_LINE_HALT, ASSERT_LINE);
	617	m_rsp->set_state_int(RSP_SR, m_rsp->state_int(RSP_SR) | RSP_STATUS_HALT);
620	618	}
621	619
622	620	if (data & 0x2)
623	621	{
624		rspcpu->state().set_state_int(RSP_SR, rspcpu->state().state_int(RSP_SR) | RSP_STATUS_BROKE);
	622	m_rsp->set_state_int(RSP_SR, m_rsp->state_int(RSP_SR) | RSP_STATUS_BROKE);
625	623
626		if (rspcpu->state().state_int(RSP_SR) & RSP_STATUS_INTR_BREAK)
	624	if (m_rsp->state_int(RSP_SR) & RSP_STATUS_INTR_BREAK)
627	625	{
628	626	signal_rcp_interrupt(SP_INTERRUPT);
629	627	}
r250319	r250320
632	630
633	631	READ32_MEMBER(n64_periphs::sp_reg_r)
634	632	{
635		UINT32 ret = 0;
636	633	switch (offset)
637	634	{
638	635	case 0x00/4:        // SP_MEM_ADDR_REG
639		ret = sp_mem_addr;
640		break;
	636	return sp_mem_addr;
641	637
642	638	case 0x04/4:        // SP_DRAM_ADDR_REG
643		ret = sp_dram_addr;
644		break;
	639	return sp_dram_addr;
645	640
646	641	case 0x08/4:        // SP_RD_LEN_REG
647		ret = (sp_dma_skip << 20) | (sp_dma_count << 12) | sp_dma_length;
648		break;
	642	return (sp_dma_skip << 20) | (sp_dma_count << 12) | sp_dma_length;
649	643
650	644	case 0x10/4:        // SP_STATUS_REG
651		ret = rspcpu->state().state_int(RSP_SR);
652		break;
	645	return m_rsp->state_int(RSP_SR);
653	646
654	647	case 0x14/4:        // SP_DMA_FULL_REG
655		ret = 0;
656		break;
	648	return 0;
657	649
658	650	case 0x18/4:        // SP_DMA_BUSY_REG
659		ret = 0;
660		break;
	651	return 0;
661	652
662	653	case 0x1c/4:        // SP_SEMAPHORE_REG
663		machine().device("maincpu")->execute().yield();
	654	m_vr4300->yield();
664	655	if( sp_semaphore )
665	656	{
666		ret = 1;
	657	return 1;
667	658	}
668	659	else
669	660	{
670	661	sp_semaphore = 1;
671		ret = 0;
	662	return 0;
672	663	}
673	664	break;
674	665
675	666	case 0x20/4:        // DP_CMD_START
676		{
677		n64_state *state = machine().driver_data<n64_state>();
678		ret = state->m_rdp->get_start();
679		break;
680		}
	667	return m_n64->rdp()->get_start();
681	668
682	669	case 0x24/4:        // DP_CMD_END
683		{
684		n64_state *state = machine().driver_data<n64_state>();
685		ret = state->m_rdp->get_end();
686		break;
687		}
	670	return m_n64->rdp()->get_end();
688	671
689	672	case 0x28/4:        // DP_CMD_CURRENT
690		{
691		n64_state *state = machine().driver_data<n64_state>();
692		ret = state->m_rdp->get_current();
693		break;
694		}
	673	return m_n64->rdp()->get_current();
695	674
696	675	case 0x34/4:        // DP_CMD_BUSY
697	676	case 0x38/4:        // DP_CMD_PIPE_BUSY
698	677	case 0x3c/4:        // DP_CMD_TMEM_BUSY
699		break;
	678	return 0;
700	679
701	680	case 0x2c/4:        // DP_CMD_STATUS
702		{
703		n64_state *state = machine().driver_data<n64_state>();
704		ret = state->m_rdp->get_status();
705		break;
706		}
	681	return m_n64->rdp()->get_status();
707	682
708	683	case 0x30/4:        // DP_CMD_CLOCK
709		{
710		if(!(machine().driver_data<n64_state>()->m_rdp->get_status() & DP_STATUS_FREEZE))
	684	if(!(m_n64->rdp()->get_status() & DP_STATUS_FREEZE))
711	685	{
712	686	dp_clock += 13;
713		ret = dp_clock;
	687	return dp_clock;
714	688	}
715	689	break;
716		}
717	690
718	691	case 0x40000/4:     // PC
719		ret = rspcpu->state().state_int(RSP_PC) & 0x00000fff;
720		break;
	692	return m_rsp->state_int(RSP_PC) & 0x00000fff;
721	693
722	694	default:
723		logerror("sp_reg_r: %08X at %08X\n", offset, maincpu->safe_pc());
	695	logerror("sp_reg_r: %08X at %08X\n", offset, m_vr4300->pc());
724	696	break;
725	697	}
726	698
727		return ret;
	699	return 0;
728	700	}
729	701
730	702
r250319	r250320
758	730
759	731	case 0x10/4:        // RSP_STATUS_REG
760	732	{
761		UINT32 oldstatus = rspcpu->state().state_int(RSP_SR);
	733	UINT32 oldstatus = m_rsp->state_int(RSP_SR);
762	734	UINT32 newstatus = oldstatus;
763	735
764	736	if (data & 0x00000001)      // clear halt
765	737	{
766		rspcpu->execute().set_input_line(INPUT_LINE_HALT, CLEAR_LINE);
	738	m_rsp->set_input_line(INPUT_LINE_HALT, CLEAR_LINE);
767	739	newstatus &= ~RSP_STATUS_HALT;
768	740	}
769	741	if (data & 0x00000002)      // set halt
770	742	{
771		rspcpu->execute().set_input_line(INPUT_LINE_HALT, ASSERT_LINE);
	743	m_rsp->set_input_line(INPUT_LINE_HALT, ASSERT_LINE);
772	744	newstatus |= RSP_STATUS_HALT;
773	745	}
774	746	if (data & 0x00000004)
r250319	r250320
792	764	newstatus |= RSP_STATUS_SSTEP;  // set single step
793	765	if(!(oldstatus & (RSP_STATUS_BROKE | RSP_STATUS_HALT)))
794	766	{
795		rspcpu->state().set_state_int(RSP_STEPCNT, 1 );
796		machine().device("rsp")->execute().yield();
	767	m_rsp->set_state_int(RSP_STEPCNT, 1 );
	768	m_rsp->yield();
797	769	}
798	770	}
799	771	if (data & 0x00000080)
r250319	r250320
868	840	{
869	841	newstatus |= RSP_STATUS_SIGNAL7;        // set signal 7
870	842	}
871		rspcpu->state().set_state_int(RSP_SR, newstatus);
	843	m_rsp->set_state_int(RSP_SR, newstatus);
872	844	break;
873	845	}
874	846
r250319	r250320
880	852	break;
881	853
882	854	default:
883		logerror("sp_reg_w: %08X, %08X, %08X at %08X\n", data, offset, mem_mask, maincpu->safe_pc());
	855	logerror("sp_reg_w: %08X, %08X, %08X at %08X\n", data, offset, mem_mask, m_vr4300->pc());
884	856	break;
885	857	}
886	858	}
r250319	r250320
889	861	switch (offset & 0xffff)
890	862	{
891	863	case 0x00/4:        // SP_PC_REG
892		if( rspcpu->state().state_int(RSP_NEXTPC) != 0xffffffff )
	864	if( m_rsp->state_int(RSP_NEXTPC) != 0xffffffff )
893	865	{
894		rspcpu->state().set_state_int(RSP_NEXTPC, 0x1000 | (data & 0xfff));
	866	m_rsp->set_state_int(RSP_NEXTPC, 0x1000 | (data & 0xfff));
895	867	}
896	868	else
897	869	{
898		rspcpu->state().set_state_int(RSP_PC, 0x1000 | (data & 0xfff));
	870	m_rsp->set_state_int(RSP_PC, 0x1000 | (data & 0xfff));
899	871	}
900	872	break;
901	873
902	874	default:
903		logerror("sp_reg_w: %08X, %08X, %08X at %08X\n", data, offset, mem_mask, maincpu->safe_pc());
	875	logerror("sp_reg_w: %08X, %08X, %08X at %08X\n", data, offset, mem_mask, m_vr4300->pc());
904	876	break;
905	877	}
906	878	}
r250319	r250320
916	888
917	889	READ32_MEMBER( n64_periphs::dp_reg_r )
918	890	{
919		n64_state *state = space.machine().driver_data<n64_state>();
920		UINT32 ret = 0;
921
922	891	switch (offset)
923	892	{
924	893	case 0x00/4:        // DP_START_REG
925		ret = state->m_rdp->get_start();
926		break;
	894	return m_n64->rdp()->get_start();
927	895
928	896	case 0x04/4:        // DP_END_REG
929		ret = state->m_rdp->get_end();
930		break;
	897	return m_n64->rdp()->get_end();
931	898
932	899	case 0x08/4:        // DP_CURRENT_REG
933		ret = state->m_rdp->get_current();
934		break;
	900	return m_n64->rdp()->get_current();
935	901
936	902	case 0x0c/4:        // DP_STATUS_REG
937		ret = state->m_rdp->get_status();
938		break;
	903	return m_n64->rdp()->get_status();
939	904
940	905	case 0x10/4:        // DP_CLOCK_REG
941		{
942		if(!(state->m_rdp->get_status() & DP_STATUS_FREEZE))
	906	if(!(m_n64->rdp()->get_status() & DP_STATUS_FREEZE))
943	907	{
944	908	dp_clock += 13;
945		ret = dp_clock;
	909	return dp_clock;
946	910	}
947	911	break;
948		}
949	912
950	913	default:
951		logerror("dp_reg_r: %08X, %08X at %08X\n", offset, mem_mask, safe_pc());
	914	logerror("dp_reg_r: %08X, %08X at %08X\n", offset, mem_mask, m_vr4300->pc());
952	915	break;
953	916	}
954	917
955		return ret;
	918	return 0;
956	919	}
957	920
958	921	WRITE32_MEMBER( n64_periphs::dp_reg_w )
959	922	{
960		n64_state *state = space.machine().driver_data<n64_state>();
961		UINT32 status = state->m_rdp->get_status();
	923	UINT32 status = m_n64->rdp()->get_status();
962	924
963	925	switch (offset)
964	926	{
965	927	case 0x00/4:        // DP_START_REG
966	928	if(status & DP_STATUS_START_VALID)
	929	{
967	930	break;
	931	}
968	932	else
969	933	{
970		state->m_rdp->set_status(status | DP_STATUS_START_VALID);
971		state->m_rdp->set_start(data & ~7);
	934	m_n64->rdp()->set_status(status | DP_STATUS_START_VALID);
	935	m_n64->rdp()->set_start(data & ~7);
972	936	}
973	937	break;
974	938
975	939	case 0x04/4:        // DP_END_REG
976	940	if(status & DP_STATUS_START_VALID)
977	941	{
978		state->m_rdp->set_status(status & ~DP_STATUS_START_VALID);
979		state->m_rdp->set_current(state->m_rdp->get_start());
980		state->m_rdp->set_end(data & ~7);
	942	m_n64->rdp()->set_status(status & ~DP_STATUS_START_VALID);
	943	m_n64->rdp()->set_current(m_n64->rdp()->get_start());
	944	m_n64->rdp()->set_end(data & ~7);
981	945	g_profiler.start(PROFILER_USER1);
982		state->m_rdp->process_command_list();
	946	m_n64->rdp()->process_command_list();
983	947	g_profiler.stop();
984	948	break;
985	949	}
986	950	else
987	951	{
988		state->m_rdp->set_end(data & ~7);
	952	m_n64->rdp()->set_end(data & ~7);
989	953	g_profiler.start(PROFILER_USER1);
990		state->m_rdp->process_command_list();
	954	m_n64->rdp()->process_command_list();
991	955	g_profiler.stop();
992	956	break;
993	957	}
994	958
995	959	case 0x0c/4:        // DP_STATUS_REG
996	960	{
997		UINT32 current_status = state->m_rdp->get_status();
	961	UINT32 current_status = m_n64->rdp()->get_status();
998	962	if (data & 0x00000001)  current_status &= ~DP_STATUS_XBUS_DMA;
999	963	if (data & 0x00000002)  current_status |= DP_STATUS_XBUS_DMA;
1000	964	if (data & 0x00000004)  current_status &= ~DP_STATUS_FREEZE;
r250319	r250320
1002	966	if (data & 0x00000010)  current_status &= ~DP_STATUS_FLUSH;
1003	967	if (data & 0x00000020)  current_status |= DP_STATUS_FLUSH;
1004	968	if (data & 0x00000200)  dp_clock = 0;
1005		state->m_rdp->set_status(current_status);
	969	m_n64->rdp()->set_status(current_status);
1006	970	break;
1007	971	}
1008	972
1009	973	default:
1010		logerror("dp_reg_w: %08X, %08X, %08X at %08X\n", data, offset, mem_mask, safe_pc());
	974	logerror("dp_reg_w: %08X, %08X, %08X at %08X\n", data, offset, mem_mask, m_vr4300->pc());
1011	975	break;
1012	976	}
1013	977	}
1014	978
1015	979	TIMER_CALLBACK_MEMBER(n64_periphs::vi_scanline_callback)
1016	980	{
1017		machine().device<n64_periphs>("rcp")->vi_scanline_tick();
1018		}
1019
1020		void n64_periphs::vi_scanline_tick()
1021		{
1022	981	signal_rcp_interrupt(VI_INTERRUPT);
1023	982	vi_scanline_timer->adjust(m_screen->time_until_pos(vi_intr >> 1));
1024	983	}
r250319	r250320
1124	1083	break;
1125	1084
1126	1085	default:
1127		logerror("vi_reg_r: %08X, %08X at %08X\n", offset, mem_mask, maincpu->safe_pc());
	1086	logerror("vi_reg_r: %08X, %08X at %08X\n", offset, mem_mask, m_vr4300->pc());
1128	1087	break;
1129	1088	}
1130	1089
r250319	r250320
1152	1111	vi_recalculate_resolution();
1153	1112	}
1154	1113	vi_width = data;
1155		//state->m_rdp->m_misc_state.m_fb_width = data;
1156	1114	break;
1157	1115
1158	1116	case 0x0c/4:        // VI_INTR_REG
r250319	r250320
1214	1172	*/
1215	1173
1216	1174	default:
1217		logerror("vi_reg_w: %08X, %08X, %08X at %08X\n", data, offset, mem_mask, maincpu->safe_pc());
	1175	logerror("vi_reg_w: %08X, %08X, %08X at %08X\n", data, offset, mem_mask, m_vr4300->pc());
1218	1176	break;
1219	1177	}
1220	1178	}
r250319	r250320
1289	1247
1290	1248	void n64_periphs::ai_dma()
1291	1249	{
1292		INT16 *ram = (INT16*)rdram;
	1250	INT16 *ram = (INT16*)m_rdram;
1293	1251	AUDIO_DMA *current = ai_fifo_get_top();
1294	1252	attotime period;
1295	1253
r250319	r250320
1365	1323	break;
1366	1324
1367	1325	default:
1368		logerror("ai_reg_r: %08X, %08X at %08X\n", offset, mem_mask, maincpu->safe_pc());
	1326	logerror("ai_reg_r: %08X, %08X at %08X\n", offset, mem_mask, m_vr4300->pc());
1369	1327	break;
1370	1328	}
1371	1329
r250319	r250320
1404	1362	break;
1405	1363
1406	1364	default:
1407		logerror("ai_reg_w: %08X, %08X, %08X at %08X\n", data, offset, mem_mask, maincpu->safe_pc());
	1365	logerror("ai_reg_w: %08X, %08X, %08X at %08X\n", data, offset, mem_mask, m_vr4300->pc());
1408	1366	break;
1409	1367	}
1410	1368	}
r250319	r250320
1414	1372
1415	1373	TIMER_CALLBACK_MEMBER(n64_periphs::pi_dma_callback)
1416	1374	{
1417		machine().device<n64_periphs>("rcp")->pi_dma_tick();
1418		machine().device("rsp")->execute().yield();
	1375	pi_dma_tick();
	1376	m_rsp->yield();
1419	1377	}
1420	1378
1421	1379	void n64_periphs::pi_dma_tick()
1422	1380	{
1423	1381	bool update_bm = false;
1424	1382	UINT16 *cart16;
1425		UINT16 *dram16 = (UINT16*)rdram;
	1383	UINT16 *dram16 = (UINT16*)m_rdram;
1426	1384
1427	1385	UINT32 cart_addr = (pi_cart_addr & 0x0fffffff) >> 1;
1428	1386	UINT32 dram_addr = (pi_dram_addr & 0x007fffff) >> 1;
r250319	r250320
1441	1399	}
1442	1400	else if((cart_addr & 0x04000000) == 0x04000000)
1443	1401	{
1444		cart16 = (UINT16*)n64_sram;
	1402	cart16 = (UINT16*)m_sram;
1445	1403	cart_addr = (pi_cart_addr & 0x0001ffff) >> 1;
1446	1404	}
1447	1405	else if((cart_addr & 0x03000000) == 0x03000000 && dd_present)
r250319	r250320
1549	1507	break;
1550	1508
1551	1509	default:
1552		logerror("pi_reg_r: %08X, %08X at %08X\n", offset, mem_mask, maincpu->safe_pc());
	1510	logerror("pi_reg_r: %08X, %08X at %08X\n", offset, mem_mask, m_vr4300->pc());
1553	1511	break;
1554	1512	}
1555	1513
r250319	r250320
1574	1532	dd_status_reg &= ~DD_ASIC_STATUS_DREQ;
1575	1533	dd_status_reg &= ~DD_ASIC_STATUS_BM_INT;
1576	1534	//logerror("Clearing DREQ, INT\n");
1577		machine().device("maincpu")->execute().set_input_line(INPUT_LINE_IRQ1, CLEAR_LINE);
	1535	m_vr4300->set_input_line(INPUT_LINE_IRQ1, CLEAR_LINE);
1578	1536	}
1579	1537	if(pi_cart_addr == 0x05000000 && dd_present)
1580	1538	{
1581	1539	dd_status_reg &= ~DD_ASIC_STATUS_C2_XFER;
1582	1540	dd_status_reg &= ~DD_ASIC_STATUS_BM_INT;
1583	1541	//logerror("Clearing C2, INT\n");
1584		machine().device("maincpu")->execute().set_input_line(INPUT_LINE_IRQ1, CLEAR_LINE);
	1542	m_vr4300->set_input_line(INPUT_LINE_IRQ1, CLEAR_LINE);
1585	1543	}
1586	1544	break;
1587	1545	}
r250319	r250320
1658	1616	break;
1659	1617
1660	1618	default:
1661		logerror("pi_reg_w: %08X, %08X, %08X at %08X\n", data, offset, mem_mask, maincpu->safe_pc());
	1619	logerror("pi_reg_w: %08X, %08X, %08X at %08X\n", data, offset, mem_mask, m_vr4300->pc());
1662	1620	break;
1663	1621	}
1664	1622	}
r250319	r250320
1669	1627	{
1670	1628	if(offset == 0x0C/4) // RI_SELECT
1671	1629	{
1672		/* This is to 'simulate' the time that RDRAM initialization
	1630	/* This is to 'simulate' the time that RDRAM initialization
1673	1631	would take if the RI registers were not set to skip the RDRAM
1674	1632	testing during device reset.  Proper simulation would require
1675		emulating the RDRAM modules and bus stalls for the mips cpu.
	1633	emulating the RDRAM modules and bus stalls for the mips cpu.
1676	1634	The cycle amount chosen represents 1/2 second, which is not
1677	1635	necessarily the time for RDRAM initialization, but rather the
1678	1636	time recommended for letting the SI devices settle after startup.
1679	1637	This allows the initialization routines for the SI to see that a
1680	1638	proper amount of time has passed since system startup. */
1681		machine().device<mips3_device>("maincpu")->burn_cycles(93750000/2);
	1639	m_vr4300->burn_cycles(93750000/2);
1682	1640	}
1683	1641
1684	1642	if(offset > 0x1c/4)
1685	1643	{
1686		logerror("ri_reg_r: %08X, %08X at %08X\n", offset, mem_mask, maincpu->safe_pc());
	1644	logerror("ri_reg_r: %08X, %08X at %08X\n", offset, mem_mask, m_vr4300->pc());
1687	1645	return 0;
1688	1646	}
1689	1647	return ri_regs[offset];
r250319	r250320
1693	1651	{
1694	1652	if(offset > 0x1c/4)
1695	1653	{
1696		logerror("ri_reg_w: %08X, %08X, %08X at %08X\n", data, offset, mem_mask, maincpu->safe_pc());
	1654	logerror("ri_reg_w: %08X, %08X, %08X at %08X\n", data, offset, mem_mask, m_vr4300->pc());
1697	1655	return;
1698	1656	}
1699	1657	COMBINE_DATA(&ri_regs[offset]);
r250319	r250320
2138	2096
2139	2097	if (direction)      // RDRAM -> PIF RAM
2140	2098	{
2141		UINT32 *src = (UINT32*)&rdram[(si_dram_addr & 0x1fffffff) / 4];
	2099	UINT32 *src = m_rdram + ((si_dram_addr & 0x1fffffff) / 4);
2142	2100
2143	2101	for(int i = 0; i < 64; i+=4)
2144	2102	{
r250319	r250320
2155	2113	{
2156	2114	handle_pif();
2157	2115
2158		UINT32 *dst = (UINT32*)&rdram[(si_dram_addr & 0x1fffffff) / 4];
	2116	UINT32 *dst = m_rdram + ((si_dram_addr & 0x1fffffff) / 4);
2159	2117
2160	2118	for(int i = 0; i < 64; i+=4)
2161	2119	{
r250319	r250320
2315	2273	}
2316	2274	//logerror("DD Write, Sending Interrupt\n");
2317	2275	dd_status_reg |= DD_ASIC_STATUS_BM_INT;
2318		machine().device("maincpu")->execute().set_input_line(INPUT_LINE_IRQ1, ASSERT_LINE);
	2276	m_vr4300->set_input_line(INPUT_LINE_IRQ1, ASSERT_LINE);
2319	2277	return;
2320	2278	}
2321	2279	else // dd read, BM Mode 1
r250319	r250320
2359	2317	}
2360	2318	//logerror("DD Read, Sending Interrupt\n");
2361	2319	dd_status_reg |= DD_ASIC_STATUS_BM_INT;
2362		machine().device("maincpu")->execute().set_input_line(INPUT_LINE_IRQ1, ASSERT_LINE);
	2320	m_vr4300->set_input_line(INPUT_LINE_IRQ1, ASSERT_LINE);
2363	2321	return;
2364	2322	}
2365	2323	}
r250319	r250320
2452	2410	{
2453	2411	dd_status_reg &= ~DD_ASIC_STATUS_BM_INT;
2454	2412	//logerror("DD Read Gap, Clearing INT\n");
2455		machine().device("maincpu")->execute().set_input_line(INPUT_LINE_IRQ1, CLEAR_LINE);
	2413	m_vr4300->set_input_line(INPUT_LINE_IRQ1, CLEAR_LINE);
2456	2414	dd_update_bm();
2457	2415	}
2458	2416	break;
r250319	r250320
2623	2581	}
2624	2582	//logerror("Sending MECHA Int\n");
2625	2583	dd_status_reg |= DD_ASIC_STATUS_MECHA_INT;
2626		machine().device("maincpu")->execute().set_input_line(INPUT_LINE_IRQ1, ASSERT_LINE);
	2584	m_vr4300->set_input_line(INPUT_LINE_IRQ1, ASSERT_LINE);
2627	2585	break;
2628	2586
2629	2587	case 0x10/4: // BM Status
r250319	r250320
2664	2622	if(!(dd_status_reg & DD_ASIC_STATUS_BM_INT) && !(dd_status_reg & DD_ASIC_STATUS_MECHA_INT))
2665	2623	{
2666	2624	//logerror("DD Status, Clearing INT\n");
2667		machine().device("maincpu")->execute().set_input_line(INPUT_LINE_IRQ1, CLEAR_LINE);
	2625	m_vr4300->set_input_line(INPUT_LINE_IRQ1, CLEAR_LINE);
2668	2626	}
2669	2627	if(data & DD_BM_START)
2670	2628	{
r250319	r250320
2742	2700	device_image_interface *image = dynamic_cast<device_image_interface *>(periphs->m_nvram_image);
2743	2701
2744	2702	UINT8 data[0x30800];
2745		memcpy(data, n64_sram, 0x20000);
	2703	if (m_sram != NULL)
	2704	{
	2705	memset(data, 0, 0x20000);
	2706	}
	2707	else
	2708	{
	2709	memcpy(data, m_sram, 0x20000);
	2710	}
2746	2711	memcpy(data + 0x20000, periphs->m_save_data.eeprom, 0x800);
2747	2712	memcpy(data + 0x20800, periphs->m_save_data.mempak[0], 0x8000);
2748	2713	memcpy(data + 0x28800, periphs->m_save_data.mempak[1], 0x8000);
r250319	r250320
2751	2716
2752	2717	void n64_state::machine_start()
2753	2718	{
2754		rdram = reinterpret_cast<UINT32 *>(memshare("rdram")->ptr());
2755		n64_sram = reinterpret_cast<UINT32 *>(memshare("sram")->ptr());
2756		rsp_imem = reinterpret_cast<UINT32 *>(memshare("rsp_imem")->ptr());
2757		rsp_dmem = reinterpret_cast<UINT32 *>(memshare("rsp_dmem")->ptr());
	2719	m_vr4300->mips3drc_set_options(MIPS3DRC_COMPATIBLE_OPTIONS);
2758	2720
2759		dynamic_cast<mips3_device *>(machine().device("maincpu"))->mips3drc_set_options(MIPS3DRC_COMPATIBLE_OPTIONS);
2760
2761	2721	/* configure fast RAM regions */
2762		dynamic_cast<mips3_device *>(machine().device("maincpu"))->add_fastram(0x00000000, 0x007fffff, FALSE, rdram);
	2722	m_vr4300->add_fastram(0x00000000, 0x007fffff, FALSE, m_rdram);
2763	2723
2764	2724	rsp_device *rsp = machine().device<rsp_device>("rsp");
2765	2725	rsp->rspdrc_set_options(RSPDRC_STRICT_VERIFY);
2766	2726	rsp->rspdrc_flush_drc_cache();
2767		rsp->rsp_add_dmem(rsp_dmem);
2768		rsp->rsp_add_imem(rsp_imem);
	2727	rsp->rsp_add_dmem(m_rsp_dmem);
	2728	rsp->rsp_add_imem(m_rsp_imem);
2769	2729
2770	2730	/* add a hook for battery save */
2771	2731	machine().add_notifier(MACHINE_NOTIFY_EXIT, machine_notify_delegate(FUNC(n64_state::n64_machine_stop),this));
r250319	r250320
2773	2733
2774	2734	void n64_state::machine_reset()
2775	2735	{
2776		machine().device("rsp")->execute().set_input_line(INPUT_LINE_HALT, ASSERT_LINE);
	2736	m_rsp->set_input_line(INPUT_LINE_HALT, ASSERT_LINE);
2777	2737	}

branches/code_cleanup/src/mame/machine/vsnes.cpp

r250319	r250320
197	197
198	198	ppu1_space.install_readwrite_handler(0x2000, 0x3eff, read8_delegate(FUNC(vsnes_state::vsnes_nt0_r),this), write8_delegate(FUNC(vsnes_state::vsnes_nt0_w),this));
199	199
200		m_vrom[0] = memregion("gfx1")->base();
201		m_vrom_size[0] = memregion("gfx1")->bytes();
202		m_vrom_banks = m_vrom_size[0] / 0x400;
	200	if (m_gfx1_rom != NULL)
	201	{
	202	m_vrom[0] = memregion("gfx1")->base();
	203	m_vrom_size[0] = memregion("gfx1")->bytes();
	204	m_vrom_banks = m_vrom_size[0] / 0x400;
	205	}
	206	else
	207	{
	208	m_vrom[0] = NULL;
	209	m_vrom_size[0] = 0;
	210	m_vrom_banks = 0;
	211	}
203	212
204	213	/* establish chr banks */
205	214	/* bank 1 is used already! */
206	215	/* DRIVER_INIT is called first - means we can handle this different for VRAM games! */
207		if (NULL != m_vrom[0])
	216	if (m_vrom[0] != NULL)
208	217	{
209	218	for (i = 0; i < 8; i++)
210	219	{

branches/code_cleanup/src/mame/video/n64.cpp

r250319	r250320
91	91
92	92	void n64_state::video_start()
93	93	{
94		m_rdp = auto_alloc(machine(), n64_rdp(*this));
	94	m_rdp = auto_alloc(machine(), n64_rdp(*this, m_rdram, m_rsp_dmem));
95	95
96	96	m_rdp->set_machine(machine());
97	97	m_rdp->init_internal_state();
r250319	r250320
203	203	//INT32 dither_filter = (n64->vi_control >> 16) & 1;
204	204	//INT32 vibuffering = ((n64->vi_control & 2) && fsaa && divot);
205	205
206		UINT16* frame_buffer = (UINT16*)&rdram[(vi_origin & 0xffffff) >> 2];
	206	UINT16* frame_buffer = (UINT16*)&m_rdram[(vi_origin & 0xffffff) >> 2];
207	207	//UINT32 hb = ((n64->vi_origin & 0xffffff) >> 2) >> 1;
208	208	//UINT8* hidden_buffer = &m_hidden_bits[hb];
209	209
r250319	r250320
261	261	INT32 gamma_dither = (vi_control >> 2) & 1;
262	262	//INT32 vibuffering = ((n64->vi_control & 2) && fsaa && divot);
263	263
264		UINT32* frame_buffer32 = (UINT32*)&rdram[(vi_origin & 0xffffff) >> 2];
	264	UINT32* frame_buffer32 = (UINT32*)&m_rdram[(vi_origin & 0xffffff) >> 2];
265	265
266	266	const INT32 hdiff = (vi_hstart & 0x3ff) - ((vi_hstart >> 16) & 0x3ff);
267	267	const float hcoeff = ((float)(vi_xscale & 0xfff) / (1 << 10));
r250319	r250320
843	843	UINT16 zval = m_z_com_table[z & 0x3ffff]|(enc >> 2);
844	844	if(zcurpixel <= MEM16_LIMIT)
845	845	{
846		((UINT16*)rdram)[zcurpixel ^ WORD_ADDR_XOR] = zval;
	846	((UINT16*)m_rdram)[zcurpixel ^ WORD_ADDR_XOR] = zval;
847	847	}
848	848	if(dzcurpixel <= MEM8_LIMIT)
849	849	{
r250319	r250320
1099	1099	{
1100	1100	if (m_status & 0x1)     // XBUS_DMEM_DMA enabled
1101	1101	{
1102		return rsp_dmem[(address & 0xfff) / 4];
	1102	return m_dmem[(address & 0xfff) / 4];
1103	1103	}
1104	1104	else
1105	1105	{
1106		return rdram[((address & 0xffffff) / 4)];
	1106	return m_rdram[((address & 0xffffff) / 4)];
1107	1107	}
1108	1108	}
1109	1109
r250319	r250320
3124	3124
3125	3125	/*****************************************************************************/
3126	3126
3127		n64_rdp::n64_rdp(n64_state &state) : poly_manager<UINT32, rdp_poly_state, 8, 32000>(state.machine())
	3127	n64_rdp::n64_rdp(n64_state &state, UINT32* rdram, UINT32* dmem) : poly_manager<UINT32, rdp_poly_state, 8, 32000>(state.machine())
3128	3128	{
3129	3129	ignore = false;
3130	3130	dolog = false;
	3131
	3132	m_rdram = rdram;
	3133	m_dmem = dmem;
	3134
3131	3135	m_aux_buf_ptr = 0;
3132	3136	m_aux_buf = NULL;
3133	3137	m_pipe_clean = true;

branches/code_cleanup/src/mame/video/n64.h

r250319	r250320
69	69	#endif
70	70
71	71	#if RDP_RANGE_CHECK
72		#define RREADADDR8(in) ((rdp_range_check((in))) ? 0 : (((UINT8*)rdram)[(in) ^ BYTE_ADDR_XOR]))
73		#define RREADIDX16(in) ((rdp_range_check((in) << 1)) ? 0 : (((UINT16*)rdram)[(in) ^ WORD_ADDR_XOR]))
74		#define RREADIDX32(in) ((rdp_range_check((in) << 2)) ? 0 : rdram[(in)])
	72	#define RREADADDR8(in) ((rdp_range_check((in))) ? 0 : (((UINT8*)m_rdram)[(in) ^ BYTE_ADDR_XOR]))
	73	#define RREADIDX16(in) ((rdp_range_check((in) << 1)) ? 0 : (((UINT16*)m_rdram)[(in) ^ WORD_ADDR_XOR]))
	74	#define RREADIDX32(in) ((rdp_range_check((in) << 2)) ? 0 : m_rdram[(in)])
75	75
76		#define RWRITEADDR8(in, val)    if(rdp_range_check((in))) { printf("Write8: Address %08x out of range!\n", (in)); fflush(stdout); fatalerror("Address %08x out of range!\n", (in)); } else { ((UINT8*)rdram)[(in) ^ BYTE_ADDR_XOR] = val;}
77		#define RWRITEIDX16(in, val)    if(rdp_range_check((in) << 1)) { printf("Write16: Address %08x out of range!\n", ((object.m_misc_state.m_fb_address >> 1) + curpixel) << 1); fflush(stdout); fatalerror("Address out of range\n"); } else { ((UINT16*)rdram)[(in) ^ WORD_ADDR_XOR] = val;}
78		#define RWRITEIDX32(in, val)    if(rdp_range_check((in) << 2)) { printf("Write32: Address %08x out of range!\n", (in) << 2); fflush(stdout); fatalerror("Address %08x out of range!\n", (in) << 2); } else { rdram[(in)] = val;}
	76	#define RWRITEADDR8(in, val)    if(rdp_range_check((in))) { printf("Write8: Address %08x out of range!\n", (in)); fflush(stdout); fatalerror("Address %08x out of range!\n", (in)); } else { ((UINT8*)m_rdram)[(in) ^ BYTE_ADDR_XOR] = val;}
	77	#define RWRITEIDX16(in, val)    if(rdp_range_check((in) << 1)) { printf("Write16: Address %08x out of range!\n", ((object.m_misc_state.m_fb_address >> 1) + curpixel) << 1); fflush(stdout); fatalerror("Address out of range\n"); } else { ((UINT16*)m_rdram)[(in) ^ WORD_ADDR_XOR] = val;}
	78	#define RWRITEIDX32(in, val)    if(rdp_range_check((in) << 2)) { printf("Write32: Address %08x out of range!\n", (in) << 2); fflush(stdout); fatalerror("Address %08x out of range!\n", (in) << 2); } else { m_rdram[(in)] = val;}
79	79	#else
80		#define RREADADDR8(in) (((UINT8*)rdram)[(in) ^ BYTE_ADDR_XOR])
81		#define RREADIDX16(in) (((UINT16*)rdram)[(in) ^ WORD_ADDR_XOR])
82		#define RREADIDX32(in) (rdram[(in)])
	80	#define RREADADDR8(in) (((UINT8*)m_rdram)[(in) ^ BYTE_ADDR_XOR])
	81	#define RREADIDX16(in) (((UINT16*)m_rdram)[(in) ^ WORD_ADDR_XOR])
	82	#define RREADIDX32(in) (m_rdram[(in)])
83	83
84		#define RWRITEADDR8(in, val)    ((UINT8*)rdram)[(in) ^ BYTE_ADDR_XOR] = val;
85		#define RWRITEIDX16(in, val)    ((UINT16*)rdram)[(in) ^ WORD_ADDR_XOR] = val;
86		#define RWRITEIDX32(in, val)    rdram[(in)] = val
	84	#define RWRITEADDR8(in, val)    ((UINT8*)m_rdram)[(in) ^ BYTE_ADDR_XOR] = val;
	85	#define RWRITEIDX16(in, val)    ((UINT16*)m_rdram)[(in) ^ WORD_ADDR_XOR] = val;
	86	#define RWRITEIDX32(in, val)    m_rdram[(in)] = val
87	87	#endif
88	88
89		#define U_RREADADDR8(in) (((UINT8*)rdram)[(in) ^ BYTE_ADDR_XOR])
90		#define U_RREADIDX16(in) (((UINT16*)rdram)[(in) ^ WORD_ADDR_XOR])
91		#define U_RREADIDX32(in) (rdram[(in)])
	89	#define U_RREADADDR8(in) (((UINT8*)m_rdram)[(in) ^ BYTE_ADDR_XOR])
	90	#define U_RREADIDX16(in) (((UINT16*)m_rdram)[(in) ^ WORD_ADDR_XOR])
	91	#define U_RREADIDX32(in) (m_rdram[(in)])
92	92
93	93	#define GETLOWCOL(x)    (((x) & 0x3e) << 2)
94	94	#define GETMEDCOL(x)    (((x) & 0x7c0) >> 3)
r250319	r250320
133	133	class n64_rdp : public poly_manager<UINT32, rdp_poly_state, 8, 32000>
134	134	{
135	135	public:
136		n64_rdp(n64_state &state);
	136	n64_rdp(n64_state &state, UINT32* rdram, UINT32* dmem);
137	137
138	138	running_machine &machine() const { assert(m_machine != NULL); return *m_machine; }
139	139
r250319	r250320
334	334	compute_cvg_t   m_compute_cvg[2];
335	335
336	336	running_machine* m_machine;
	337	UINT32*         m_rdram;
	338	UINT32*         m_dmem;
337	339
338	340	combine_modes_t m_combine;
339	341	bool            m_pending_mode_block;

branches/code_cleanup/src/mame/video/rdptpipe.cpp

r250319	r250320
25	25	{
26	26	n64_state* state = machine.driver_data<n64_state>();
27	27
28		m_rdp = state->m_rdp;
	28	m_rdp = state->rdp();
29	29
30	30	for(INT32 i = 0; i < 0x10000; i++)
31	31	{

branches/code_cleanup/src/mame/video/sega16sp.cpp

r250319	r250320
826	826
827	827	sega_sys16b_sprite_device::sega_sys16b_sprite_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
828	828	: sega_16bit_sprite_device(mconfig, SEGA_SYS16B_SPRITES, "Sega System 16B Sprites", tag, owner, "sega_16bit_sprite", __FILE__)
	829	, m_sprite_region(*this, tag)
829	830	{
830	831	set_local_origin(184, 0x00, -184, 0);
831	832	}
r250319	r250320
867	868	//  Note that the zooming described below is 100% accurate to the real board.
868	869	//
869	870
	871	// if the game does not have sprites, don't try to draw anything
	872	if (m_sprite_region == NULL)
	873	{
	874	return;
	875	}
	876
870	877	// render the sprites in order
871		const UINT16 *spritebase = reinterpret_cast<const UINT16 *>(region()->base());
872		UINT8 numbanks = region()->bytes() / 0x20000;
	878	const UINT16 *spritebase = reinterpret_cast<const UINT16 *>(m_sprite_region->base());
	879	UINT8 numbanks = m_sprite_region->bytes() / 0x20000;
873	880	UINT16 *ramend = spriteram() + spriteram_elements();
874	881	for (UINT16 *data = spriteram(); data < ramend; data += 8)
875	882	{

branches/code_cleanup/src/mame/video/sega16sp.h

r250319	r250320
201	201	protected:
202	202	// subclass overrides
203	203	virtual void draw(bitmap_ind16 &bitmap, const rectangle &cliprect);
	204
	205	// memory regions
	206	optional_memory_region      m_sprite_region;
204	207	};
205	208
206	209

https://github.com/mamedev/mame/commit/33d35d3658976e9c8a4e69844b0b4b73b6e2d851

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