trunk/src/devices/cpu/z8000/z8000tbl.inc
r250310 | r250311 | |
81 | 81 | {0x2100,0x210f, 1,2, 7,&z8002_device::Z21_0000_dddd_imm16, "ld %rw3,%#w1", 0}, |
82 | 82 | {0x2110,0x21ff, 1,1, 7,&z8002_device::Z21_ssN0_dddd, "ld %rw3,@%rw2", 0}, |
83 | 83 | {0x2200,0x220f, 1,2, 10,&z8002_device::Z22_0000_ssss_0000_dddd_0000_0000, "resb %rb5,%rw3", 0}, |
84 | | {0x2210,0x22ff, 1,1, 11,&z8002_device::Z22_ddN0_imm4, "resb @%rw3,%3", 0}, |
| 84 | {0x2210,0x22ff, 1,1, 11,&z8002_device::Z22_ddN0_imm4, "resb @%rw2,%3", 0}, |
85 | 85 | {0x2300,0x230f, 1,2, 10,&z8002_device::Z23_0000_ssss_0000_dddd_0000_0000, "res %rw5,%rw3", 0}, |
86 | | {0x2310,0x23ff, 1,1, 11,&z8002_device::Z23_ddN0_imm4, "res @%rw3,%3", 0}, |
| 86 | {0x2310,0x23ff, 1,1, 11,&z8002_device::Z23_ddN0_imm4, "res @%rw2,%3", 0}, |
87 | 87 | {0x2400,0x240f, 1,2, 10,&z8002_device::Z24_0000_ssss_0000_dddd_0000_0000, "setb %rb5,%rw3", 0}, |
88 | | {0x2410,0x24ff, 1,1, 11,&z8002_device::Z24_ddN0_imm4, "setb @%rw3,%3", 0}, |
| 88 | {0x2410,0x24ff, 1,1, 11,&z8002_device::Z24_ddN0_imm4, "setb @%rw2,%3", 0}, |
89 | 89 | {0x2500,0x250f, 1,2, 10,&z8002_device::Z25_0000_ssss_0000_dddd_0000_0000, "set %rw5,%rw3", 0}, |
90 | | {0x2510,0x25ff, 1,1, 11,&z8002_device::Z25_ddN0_imm4, "set @%rw3,%3", 0}, |
| 90 | {0x2510,0x25ff, 1,1, 11,&z8002_device::Z25_ddN0_imm4, "set @%rw2,%3", 0}, |
91 | 91 | {0x2600,0x260f, 1,2, 10,&z8002_device::Z26_0000_ssss_0000_dddd_0000_0000, "bitb %rb5,%rw3", 0}, |
92 | | {0x2610,0x26ff, 1,1, 8,&z8002_device::Z26_ddN0_imm4, "bitb @%rw3,%3", 0}, |
| 92 | {0x2610,0x26ff, 1,1, 8,&z8002_device::Z26_ddN0_imm4, "bitb @%rw2,%3", 0}, |
93 | 93 | {0x2700,0x270f, 1,2, 10,&z8002_device::Z27_0000_ssss_0000_dddd_0000_0000, "bit %rw5,%rw3", 0}, |
94 | 94 | {0x2710,0x27ff, 1,1, 8,&z8002_device::Z27_ddN0_imm4, "bit @%rw2,%3", 0}, |
95 | 95 | {0x2810,0x28ff, 1,1, 11,&z8002_device::Z28_ddN0_imm4m1, "incb @%rw2,%+3", 0}, |