trunk/src/devices/cpu/tms32031/32031ops.cpp
| r250221 | r250222 | |
|---|
| 1 | | // license:BSD-3-Clause |
| 2 | | // copyright-holders:Aaron Giles |
| 3 | | /*************************************************************************** |
| 4 | | |
| 5 | | 32031ops.cpp |
| 6 | | |
| 7 | | TMS32031/2 emulator |
| 8 | | |
| 9 | | ***************************************************************************/ |
| 10 | | |
| 11 | | |
| 12 | | //************************************************************************** |
| 13 | | // COMPILE-TIME OPTIONS |
| 14 | | //************************************************************************** |
| 15 | | |
| 16 | | #define USE_FP 0 |
| 17 | | |
| 18 | | |
| 19 | | |
| 20 | | //************************************************************************** |
| 21 | | // MACROS |
| 22 | | //************************************************************************** |
| 23 | | |
| 24 | | #define IREG(rnum) (m_r[rnum].i32[0]) |
| 25 | | #define FREGEXP(rnum) (m_r[rnum].exponent()) |
| 26 | | #define FREGMAN(rnum) (m_r[rnum].mantissa()) |
| 27 | | |
| 28 | | #define FP2LONG(rnum) ((FREGEXP(rnum) << 24) | ((UINT32)FREGMAN(rnum) >> 8)) |
| 29 | | #define LONG2FP(rnum,v) do { m_r[rnum].set_mantissa((v) << 8); m_r[rnum].set_exponent((INT32)(v) >> 24); } while (0) |
| 30 | | #define SHORT2FP(rnum,v) do { \ |
| 31 | | if ((UINT16)(v) == 0x8000) { m_r[rnum].set_mantissa(0); m_r[rnum].set_exponent(-128); } \ |
| 32 | | else { m_r[rnum].set_mantissa((v) << 20); m_r[rnum].set_exponent((INT16)(v) >> 12); } \ |
| 33 | | } while (0) |
| 34 | | |
| 35 | | #define DIRECT(op) (((IREG(TMR_DP) & 0xff) << 16) | ((UINT16)op)) |
| 36 | | #define INDIRECT_D(op,o) ((this->*s_indirect_d[((o) >> 3) & 31])(op,o)) |
| 37 | | #define INDIRECT_1(op,o) ((this->*s_indirect_1[((o) >> 3) & 31])(op,o)) |
| 38 | | #define INDIRECT_1_DEF(op,o) ((this->*s_indirect_1_def[((o) >> 3) & 31])(op,o,defptr)) |
| 39 | | |
| 40 | | #define SIGN(val) ((val) & 0x80000000) |
| 41 | | |
| 42 | | #define OVERFLOW_SUB(a,b,r) ((INT32)(((a) ^ (b)) & ((a) ^ (r))) < 0) |
| 43 | | #define OVERFLOW_ADD(a,b,r) ((INT32)(((a) ^ (r)) & ((b) ^ (r))) < 0) |
| 44 | | |
| 45 | | #define CLR_FLAGS(f) do { IREG(TMR_ST) &= ~(f); } while (0) |
| 46 | | #define CLR_NVUF() CLR_FLAGS(NFLAG | VFLAG | UFFLAG) |
| 47 | | #define CLR_NZVUF() CLR_FLAGS(NFLAG | ZFLAG | VFLAG | UFFLAG) |
| 48 | | #define CLR_NZCVUF() CLR_FLAGS(NFLAG | ZFLAG | VFLAG | CFLAG | UFFLAG) |
| 49 | | |
| 50 | | #define OR_C(flag) do { IREG(TMR_ST) |= flag & CFLAG; } while (0) |
| 51 | | #define OR_NZ(val) do { IREG(TMR_ST) |= (((val) >> 28) & NFLAG) | (((val) == 0) << 2); } while (0) |
| 52 | | #define OR_NZF(reg) do { IREG(TMR_ST) |= ((reg.mantissa() >> 28) & NFLAG) | ((reg.exponent() == -128) << 2); } while (0) |
| 53 | | #define OR_NUF(reg) do { int temp = (reg.exponent() == -128) << 4; IREG(TMR_ST) |= ((reg.mantissa() >> 28) & NFLAG) | (temp) | (temp << 2); } while (0) |
| 54 | | #define OR_V_SUB(a,b,r) do { UINT32 temp = ((((a) ^ (b)) & ((a) ^ (r))) >> 30) & VFLAG; IREG(TMR_ST) |= temp | (temp << 4); } while (0) |
| 55 | | #define OR_V_ADD(a,b,r) do { UINT32 temp = ((((a) ^ (r)) & ((b) ^ (r))) >> 30) & VFLAG; IREG(TMR_ST) |= temp | (temp << 4); } while (0) |
| 56 | | #define OR_C_SUB(a,b,r) do { IREG(TMR_ST) |= ((UINT32)(b) > (UINT32)(a)); } while (0) |
| 57 | | #define OR_C_ADD(a,b,r) do { IREG(TMR_ST) |= ((UINT32)(a) > (UINT32)(r)); } while (0) |
| 58 | | #define OR_C_SBB(a,b,c) do { INT64 temp = (INT64)(a) - (UINT32)(b) - (UINT32)(c); IREG(TMR_ST) |= (temp < 0); } while (0) |
| 59 | | #define OR_C_ADC(a,b,c) do { UINT64 temp = (UINT64)(a) + (UINT32)(b) + (UINT32)(c); IREG(TMR_ST) |= (temp > 0xffffffff); } while (0) |
| 60 | | |
| 61 | | #define OVM() (IREG(TMR_ST) & OVMFLAG) |
| 62 | | |
| 63 | | #define DECLARE_DEF UINT32 defval; UINT32 *defptr = &defval |
| 64 | | #define UPDATE_DEF() *defptr = defval |
| 65 | | |
| 66 | | |
| 67 | | |
| 68 | | //************************************************************************** |
| 69 | | // IMPLEMENTATION |
| 70 | | //************************************************************************** |
| 71 | | |
| 72 | | void tms3203x_device::illegal(UINT32 op) |
| 73 | | { |
| 74 | | if ((machine().debug_flags & DEBUG_FLAG_ENABLED) != 0) |
| 75 | | { |
| 76 | | logerror("Illegal op @ %06X: %08X (tbl=%03X)\n", m_pc - 1, op, op >> 21); |
| 77 | | debugger_break(machine()); |
| 78 | | } |
| 79 | | } |
| 80 | | |
| 81 | | |
| 82 | | void tms3203x_device::unimplemented(UINT32 op) |
| 83 | | { |
| 84 | | fatalerror("Unimplemented op @ %06X: %08X (tbl=%03X)\n", m_pc - 1, op, op >> 21); |
| 85 | | } |
| 86 | | |
| 87 | | |
| 88 | | inline void tms3203x_device::execute_one() |
| 89 | | { |
| 90 | | UINT32 op = ROPCODE(m_pc); |
| 91 | | m_icount -= 2; // 2 clocks per cycle |
| 92 | | m_pc++; |
| 93 | | #if (TMS_3203X_LOG_OPCODE_USAGE) |
| 94 | | m_hits[op >> 21]++; |
| 95 | | #endif |
| 96 | | (this->*s_tms32031ops[op >> 21])(op); |
| 97 | | } |
| 98 | | |
| 99 | | |
| 100 | | void tms3203x_device::update_special(int dreg) |
| 101 | | { |
| 102 | | if (dreg == TMR_BK) |
| 103 | | { |
| 104 | | UINT32 temp = IREG(TMR_BK); |
| 105 | | m_bkmask = temp; |
| 106 | | while (temp >>= 1) |
| 107 | | m_bkmask |= temp; |
| 108 | | } |
| 109 | | else if (dreg == TMR_IOF) |
| 110 | | { |
| 111 | | if (IREG(TMR_IOF) & 0x002) |
| 112 | | m_xf0_cb((offs_t)0, (IREG(TMR_IOF) >> 2) & 1); |
| 113 | | if (IREG(TMR_IOF) & 0x020) |
| 114 | | m_xf1_cb((offs_t)0, (IREG(TMR_IOF) >> 6) & 1); |
| 115 | | } |
| 116 | | else if (dreg == TMR_ST || dreg == TMR_IF || dreg == TMR_IE) |
| 117 | | check_irqs(); |
| 118 | | } |
| 119 | | |
| 120 | | |
| 121 | | |
| 122 | | //************************************************************************** |
| 123 | | // CONDITION CODES |
| 124 | | //************************************************************************** |
| 125 | | |
| 126 | | const UINT32 C_LO = 1 << 1; |
| 127 | | const UINT32 C_LS = 1 << 2; |
| 128 | | const UINT32 C_HI = 1 << 3; |
| 129 | | const UINT32 C_HS = 1 << 4; |
| 130 | | const UINT32 C_EQ = 1 << 5; |
| 131 | | const UINT32 C_NE = 1 << 6; |
| 132 | | const UINT32 C_LT = 1 << 7; |
| 133 | | const UINT32 C_LE = 1 << 8; |
| 134 | | const UINT32 C_GT = 1 << 9; |
| 135 | | const UINT32 C_GE = 1 << 10; |
| 136 | | const UINT32 C_NV = 1 << 12; |
| 137 | | const UINT32 C_V = 1 << 13; |
| 138 | | const UINT32 C_NUF = 1 << 14; |
| 139 | | const UINT32 C_UF = 1 << 15; |
| 140 | | const UINT32 C_NLV = 1 << 16; |
| 141 | | const UINT32 C_LV = 1 << 17; |
| 142 | | const UINT32 C_NLUF = 1 << 18; |
| 143 | | const UINT32 C_LUF = 1 << 19; |
| 144 | | const UINT32 C_ZUF = 1 << 20; |
| 145 | | |
| 146 | | const UINT32 condition_table[0x80] = |
| 147 | | { |
| 148 | | /* ------- */ 1 | C_HI | C_HS | C_NE | C_GT | C_GE | C_NV | C_NUF | C_NLV | C_NLUF, |
| 149 | | /* ------C */ 1 | C_LO | C_LS | C_NE | C_GT | C_GE | C_NV | C_NUF | C_NLV | C_NLUF, |
| 150 | | /* -----V- */ 1 | C_HI | C_HS | C_NE | C_GT | C_GE | C_V | C_NUF | C_NLV | C_NLUF, |
| 151 | | /* -----VC */ 1 | C_LO | C_LS | C_NE | C_GT | C_GE | C_V | C_NUF | C_NLV | C_NLUF, |
| 152 | | /* ----Z-- */ 1 | C_LS | C_HS | C_EQ | C_LE | C_GE | C_NV | C_NUF | C_NLV | C_NLUF | C_ZUF, |
| 153 | | /* ----Z-C */ 1 | C_LO | C_LS | C_EQ | C_LE | C_GE | C_NV | C_NUF | C_NLV | C_NLUF | C_ZUF, |
| 154 | | /* ----ZV- */ 1 | C_LS | C_HS | C_EQ | C_LE | C_GE | C_V | C_NUF | C_NLV | C_NLUF | C_ZUF, |
| 155 | | /* ----ZVC */ 1 | C_LO | C_LS | C_EQ | C_LE | C_GE | C_V | C_NUF | C_NLV | C_NLUF | C_ZUF, |
| 156 | | /* ---N--- */ 1 | C_HI | C_HS | C_NE | C_LT | C_LE | C_NV | C_NUF | C_NLV | C_NLUF, |
| 157 | | /* ---N--C */ 1 | C_LO | C_LS | C_NE | C_LT | C_LE | C_NV | C_NUF | C_NLV | C_NLUF, |
| 158 | | /* ---N-V- */ 1 | C_HI | C_HS | C_NE | C_LT | C_LE | C_V | C_NUF | C_NLV | C_NLUF, |
| 159 | | /* ---N-VC */ 1 | C_LO | C_LS | C_NE | C_LT | C_LE | C_V | C_NUF | C_NLV | C_NLUF, |
| 160 | | /* ---NZ-- */ 1 | C_LS | C_HS | C_EQ | C_LT | C_LE | C_NV | C_NUF | C_NLV | C_NLUF | C_ZUF, |
| 161 | | /* ---NZ-C */ 1 | C_LO | C_LS | C_EQ | C_LT | C_LE | C_NV | C_NUF | C_NLV | C_NLUF | C_ZUF, |
| 162 | | /* ---NZV- */ 1 | C_LS | C_HS | C_EQ | C_LT | C_LE | C_V | C_NUF | C_NLV | C_NLUF | C_ZUF, |
| 163 | | /* ---NZVC */ 1 | C_LO | C_LS | C_EQ | C_LT | C_LE | C_V | C_NUF | C_NLV | C_NLUF | C_ZUF, |
| 164 | | /* --U---- */ 1 | C_HI | C_HS | C_NE | C_GT | C_GE | C_NV | C_UF | C_NLV | C_NLUF | C_ZUF, |
| 165 | | /* --U---C */ 1 | C_LO | C_LS | C_NE | C_GT | C_GE | C_NV | C_UF | C_NLV | C_NLUF | C_ZUF, |
| 166 | | /* --U--V- */ 1 | C_HI | C_HS | C_NE | C_GT | C_GE | C_V | C_UF | C_NLV | C_NLUF | C_ZUF, |
| 167 | | /* --U--VC */ 1 | C_LO | C_LS | C_NE | C_GT | C_GE | C_V | C_UF | C_NLV | C_NLUF | C_ZUF, |
| 168 | | /* --U-Z-- */ 1 | C_LS | C_HS | C_EQ | C_LE | C_GE | C_NV | C_UF | C_NLV | C_NLUF | C_ZUF, |
| 169 | | /* --U-Z-C */ 1 | C_LO | C_LS | C_EQ | C_LE | C_GE | C_NV | C_UF | C_NLV | C_NLUF | C_ZUF, |
| 170 | | /* --U-ZV- */ 1 | C_LS | C_HS | C_EQ | C_LE | C_GE | C_V | C_UF | C_NLV | C_NLUF | C_ZUF, |
| 171 | | /* --U-ZVC */ 1 | C_LO | C_LS | C_EQ | C_LE | C_GE | C_V | C_UF | C_NLV | C_NLUF | C_ZUF, |
| 172 | | /* --UN--- */ 1 | C_HI | C_HS | C_NE | C_LT | C_LE | C_NV | C_UF | C_NLV | C_NLUF | C_ZUF, |
| 173 | | /* --UN--C */ 1 | C_LO | C_LS | C_NE | C_LT | C_LE | C_NV | C_UF | C_NLV | C_NLUF | C_ZUF, |
| 174 | | /* --UN-V- */ 1 | C_HI | C_HS | C_NE | C_LT | C_LE | C_V | C_UF | C_NLV | C_NLUF | C_ZUF, |
| 175 | | /* --UN-VC */ 1 | C_LO | C_LS | C_NE | C_LT | C_LE | C_V | C_UF | C_NLV | C_NLUF | C_ZUF, |
| 176 | | /* --UNZ-- */ 1 | C_LS | C_HS | C_EQ | C_LT | C_LE | C_NV | C_UF | C_NLV | C_NLUF | C_ZUF, |
| 177 | | /* --UNZ-C */ 1 | C_LO | C_LS | C_EQ | C_LT | C_LE | C_NV | C_UF | C_NLV | C_NLUF | C_ZUF, |
| 178 | | /* --UNZV- */ 1 | C_LS | C_HS | C_EQ | C_LT | C_LE | C_V | C_UF | C_NLV | C_NLUF | C_ZUF, |
| 179 | | /* --UNZVC */ 1 | C_LO | C_LS | C_EQ | C_LT | C_LE | C_V | C_UF | C_NLV | C_NLUF | C_ZUF, |
| 180 | | /* -v----- */ 1 | C_HI | C_HS | C_NE | C_GT | C_GE | C_NV | C_NUF | C_LV | C_NLUF, |
| 181 | | /* -v----C */ 1 | C_LO | C_LS | C_NE | C_GT | C_GE | C_NV | C_NUF | C_LV | C_NLUF, |
| 182 | | /* -v---V- */ 1 | C_HI | C_HS | C_NE | C_GT | C_GE | C_V | C_NUF | C_LV | C_NLUF, |
| 183 | | /* -v---VC */ 1 | C_LO | C_LS | C_NE | C_GT | C_GE | C_V | C_NUF | C_LV | C_NLUF, |
| 184 | | /* -v--Z-- */ 1 | C_LS | C_HS | C_EQ | C_LE | C_GE | C_NV | C_NUF | C_LV | C_NLUF | C_ZUF, |
| 185 | | /* -v--Z-C */ 1 | C_LO | C_LS | C_EQ | C_LE | C_GE | C_NV | C_NUF | C_LV | C_NLUF | C_ZUF, |
| 186 | | /* -v--ZV- */ 1 | C_LS | C_HS | C_EQ | C_LE | C_GE | C_V | C_NUF | C_LV | C_NLUF | C_ZUF, |
| 187 | | /* -v--ZVC */ 1 | C_LO | C_LS | C_EQ | C_LE | C_GE | C_V | C_NUF | C_LV | C_NLUF | C_ZUF, |
| 188 | | /* -v-N--- */ 1 | C_HI | C_HS | C_NE | C_LT | C_LE | C_NV | C_NUF | C_LV | C_NLUF, |
| 189 | | /* -v-N--C */ 1 | C_LO | C_LS | C_NE | C_LT | C_LE | C_NV | C_NUF | C_LV | C_NLUF, |
| 190 | | /* -v-N-V- */ 1 | C_HI | C_HS | C_NE | C_LT | C_LE | C_V | C_NUF | C_LV | C_NLUF, |
| 191 | | /* -v-N-VC */ 1 | C_LO | C_LS | C_NE | C_LT | C_LE | C_V | C_NUF | C_LV | C_NLUF, |
| 192 | | /* -v-NZ-- */ 1 | C_LS | C_HS | C_EQ | C_LT | C_LE | C_NV | C_NUF | C_LV | C_NLUF | C_ZUF, |
| 193 | | /* -v-NZ-C */ 1 | C_LO | C_LS | C_EQ | C_LT | C_LE | C_NV | C_NUF | C_LV | C_NLUF | C_ZUF, |
| 194 | | /* -v-NZV- */ 1 | C_LS | C_HS | C_EQ | C_LT | C_LE | C_V | C_NUF | C_LV | C_NLUF | C_ZUF, |
| 195 | | /* -v-NZVC */ 1 | C_LO | C_LS | C_EQ | C_LT | C_LE | C_V | C_NUF | C_LV | C_NLUF | C_ZUF, |
| 196 | | /* -vU---- */ 1 | C_HI | C_HS | C_NE | C_GT | C_GE | C_NV | C_UF | C_LV | C_NLUF | C_ZUF, |
| 197 | | /* -vU---C */ 1 | C_LO | C_LS | C_NE | C_GT | C_GE | C_NV | C_UF | C_LV | C_NLUF | C_ZUF, |
| 198 | | /* -vU--V- */ 1 | C_HI | C_HS | C_NE | C_GT | C_GE | C_V | C_UF | C_LV | C_NLUF | C_ZUF, |
| 199 | | /* -vU--VC */ 1 | C_LO | C_LS | C_NE | C_GT | C_GE | C_V | C_UF | C_LV | C_NLUF | C_ZUF, |
| 200 | | /* -vU-Z-- */ 1 | C_LS | C_HS | C_EQ | C_LE | C_GE | C_NV | C_UF | C_LV | C_NLUF | C_ZUF, |
| 201 | | /* -vU-Z-C */ 1 | C_LO | C_LS | C_EQ | C_LE | C_GE | C_NV | C_UF | C_LV | C_NLUF | C_ZUF, |
| 202 | | /* -vU-ZV- */ 1 | C_LS | C_HS | C_EQ | C_LE | C_GE | C_V | C_UF | C_LV | C_NLUF | C_ZUF, |
| 203 | | /* -vU-ZVC */ 1 | C_LO | C_LS | C_EQ | C_LE | C_GE | C_V | C_UF | C_LV | C_NLUF | C_ZUF, |
| 204 | | /* -vUN--- */ 1 | C_HI | C_HS | C_NE | C_LT | C_LE | C_NV | C_UF | C_LV | C_NLUF | C_ZUF, |
| 205 | | /* -vUN--C */ 1 | C_LO | C_LS | C_NE | C_LT | C_LE | C_NV | C_UF | C_LV | C_NLUF | C_ZUF, |
| 206 | | /* -vUN-V- */ 1 | C_HI | C_HS | C_NE | C_LT | C_LE | C_V | C_UF | C_LV | C_NLUF | C_ZUF, |
| 207 | | /* -vUN-VC */ 1 | C_LO | C_LS | C_NE | C_LT | C_LE | C_V | C_UF | C_LV | C_NLUF | C_ZUF, |
| 208 | | /* -vUNZ-- */ 1 | C_LS | C_HS | C_EQ | C_LT | C_LE | C_NV | C_UF | C_LV | C_NLUF | C_ZUF, |
| 209 | | /* -vUNZ-C */ 1 | C_LO | C_LS | C_EQ | C_LT | C_LE | C_NV | C_UF | C_LV | C_NLUF | C_ZUF, |
| 210 | | /* -vUNZV- */ 1 | C_LS | C_HS | C_EQ | C_LT | C_LE | C_V | C_UF | C_LV | C_NLUF | C_ZUF, |
| 211 | | /* -vUNZVC */ 1 | C_LO | C_LS | C_EQ | C_LT | C_LE | C_V | C_UF | C_LV | C_NLUF | C_ZUF, |
| 212 | | /* u------ */ 1 | C_HI | C_HS | C_NE | C_GT | C_GE | C_NV | C_NUF | C_NLV | C_LUF, |
| 213 | | /* u-----C */ 1 | C_LO | C_LS | C_NE | C_GT | C_GE | C_NV | C_NUF | C_NLV | C_LUF, |
| 214 | | /* u----V- */ 1 | C_HI | C_HS | C_NE | C_GT | C_GE | C_V | C_NUF | C_NLV | C_LUF, |
| 215 | | /* u----VC */ 1 | C_LO | C_LS | C_NE | C_GT | C_GE | C_V | C_NUF | C_NLV | C_LUF, |
| 216 | | /* u---Z-- */ 1 | C_LS | C_HS | C_EQ | C_LE | C_GE | C_NV | C_NUF | C_NLV | C_LUF | C_ZUF, |
| 217 | | /* u---Z-C */ 1 | C_LO | C_LS | C_EQ | C_LE | C_GE | C_NV | C_NUF | C_NLV | C_LUF | C_ZUF, |
| 218 | | /* u---ZV- */ 1 | C_LS | C_HS | C_EQ | C_LE | C_GE | C_V | C_NUF | C_NLV | C_LUF | C_ZUF, |
| 219 | | /* u---ZVC */ 1 | C_LO | C_LS | C_EQ | C_LE | C_GE | C_V | C_NUF | C_NLV | C_LUF | C_ZUF, |
| 220 | | /* u--N--- */ 1 | C_HI | C_HS | C_NE | C_LT | C_LE | C_NV | C_NUF | C_NLV | C_LUF, |
| 221 | | /* u--N--C */ 1 | C_LO | C_LS | C_NE | C_LT | C_LE | C_NV | C_NUF | C_NLV | C_LUF, |
| 222 | | /* u--N-V- */ 1 | C_HI | C_HS | C_NE | C_LT | C_LE | C_V | C_NUF | C_NLV | C_LUF, |
| 223 | | /* u--N-VC */ 1 | C_LO | C_LS | C_NE | C_LT | C_LE | C_V | C_NUF | C_NLV | C_LUF, |
| 224 | | /* u--NZ-- */ 1 | C_LS | C_HS | C_EQ | C_LT | C_LE | C_NV | C_NUF | C_NLV | C_LUF | C_ZUF, |
| 225 | | /* u--NZ-C */ 1 | C_LO | C_LS | C_EQ | C_LT | C_LE | C_NV | C_NUF | C_NLV | C_LUF | C_ZUF, |
| 226 | | /* u--NZV- */ 1 | C_LS | C_HS | C_EQ | C_LT | C_LE | C_V | C_NUF | C_NLV | C_LUF | C_ZUF, |
| 227 | | /* u--NZVC */ 1 | C_LO | C_LS | C_EQ | C_LT | C_LE | C_V | C_NUF | C_NLV | C_LUF | C_ZUF, |
| 228 | | /* u-U---- */ 1 | C_HI | C_HS | C_NE | C_GT | C_GE | C_NV | C_UF | C_NLV | C_LUF | C_ZUF, |
| 229 | | /* u-U---C */ 1 | C_LO | C_LS | C_NE | C_GT | C_GE | C_NV | C_UF | C_NLV | C_LUF | C_ZUF, |
| 230 | | /* u-U--V- */ 1 | C_HI | C_HS | C_NE | C_GT | C_GE | C_V | C_UF | C_NLV | C_LUF | C_ZUF, |
| 231 | | /* u-U--VC */ 1 | C_LO | C_LS | C_NE | C_GT | C_GE | C_V | C_UF | C_NLV | C_LUF | C_ZUF, |
| 232 | | /* u-U-Z-- */ 1 | C_LS | C_HS | C_EQ | C_LE | C_GE | C_NV | C_UF | C_NLV | C_LUF | C_ZUF, |
| 233 | | /* u-U-Z-C */ 1 | C_LO | C_LS | C_EQ | C_LE | C_GE | C_NV | C_UF | C_NLV | C_LUF | C_ZUF, |
| 234 | | /* u-U-ZV- */ 1 | C_LS | C_HS | C_EQ | C_LE | C_GE | C_V | C_UF | C_NLV | C_LUF | C_ZUF, |
| 235 | | /* u-U-ZVC */ 1 | C_LO | C_LS | C_EQ | C_LE | C_GE | C_V | C_UF | C_NLV | C_LUF | C_ZUF, |
| 236 | | /* u-UN--- */ 1 | C_HI | C_HS | C_NE | C_LT | C_LE | C_NV | C_UF | C_NLV | C_LUF | C_ZUF, |
| 237 | | /* u-UN--C */ 1 | C_LO | C_LS | C_NE | C_LT | C_LE | C_NV | C_UF | C_NLV | C_LUF | C_ZUF, |
| 238 | | /* u-UN-V- */ 1 | C_HI | C_HS | C_NE | C_LT | C_LE | C_V | C_UF | C_NLV | C_LUF | C_ZUF, |
| 239 | | /* u-UN-VC */ 1 | C_LO | C_LS | C_NE | C_LT | C_LE | C_V | C_UF | C_NLV | C_LUF | C_ZUF, |
| 240 | | /* u-UNZ-- */ 1 | C_LS | C_HS | C_EQ | C_LT | C_LE | C_NV | C_UF | C_NLV | C_LUF | C_ZUF, |
| 241 | | /* u-UNZ-C */ 1 | C_LO | C_LS | C_EQ | C_LT | C_LE | C_NV | C_UF | C_NLV | C_LUF | C_ZUF, |
| 242 | | /* u-UNZV- */ 1 | C_LS | C_HS | C_EQ | C_LT | C_LE | C_V | C_UF | C_NLV | C_LUF | C_ZUF, |
| 243 | | /* u-UNZVC */ 1 | C_LO | C_LS | C_EQ | C_LT | C_LE | C_V | C_UF | C_NLV | C_LUF | C_ZUF, |
| 244 | | /* uv----- */ 1 | C_HI | C_HS | C_NE | C_GT | C_GE | C_NV | C_NUF | C_LV | C_LUF, |
| 245 | | /* uv----C */ 1 | C_LO | C_LS | C_NE | C_GT | C_GE | C_NV | C_NUF | C_LV | C_LUF, |
| 246 | | /* uv---V- */ 1 | C_HI | C_HS | C_NE | C_GT | C_GE | C_V | C_NUF | C_LV | C_LUF, |
| 247 | | /* uv---VC */ 1 | C_LO | C_LS | C_NE | C_GT | C_GE | C_V | C_NUF | C_LV | C_LUF, |
| 248 | | /* uv--Z-- */ 1 | C_LS | C_HS | C_EQ | C_LE | C_GE | C_NV | C_NUF | C_LV | C_LUF | C_ZUF, |
| 249 | | /* uv--Z-C */ 1 | C_LO | C_LS | C_EQ | C_LE | C_GE | C_NV | C_NUF | C_LV | C_LUF | C_ZUF, |
| 250 | | /* uv--ZV- */ 1 | C_LS | C_HS | C_EQ | C_LE | C_GE | C_V | C_NUF | C_LV | C_LUF | C_ZUF, |
| 251 | | /* uv--ZVC */ 1 | C_LO | C_LS | C_EQ | C_LE | C_GE | C_V | C_NUF | C_LV | C_LUF | C_ZUF, |
| 252 | | /* uv-N--- */ 1 | C_HI | C_HS | C_NE | C_LT | C_LE | C_NV | C_NUF | C_LV | C_LUF, |
| 253 | | /* uv-N--C */ 1 | C_LO | C_LS | C_NE | C_LT | C_LE | C_NV | C_NUF | C_LV | C_LUF, |
| 254 | | /* uv-N-V- */ 1 | C_HI | C_HS | C_NE | C_LT | C_LE | C_V | C_NUF | C_LV | C_LUF, |
| 255 | | /* uv-N-VC */ 1 | C_LO | C_LS | C_NE | C_LT | C_LE | C_V | C_NUF | C_LV | C_LUF, |
| 256 | | /* uv-NZ-- */ 1 | C_LS | C_HS | C_EQ | C_LT | C_LE | C_NV | C_NUF | C_LV | C_LUF | C_ZUF, |
| 257 | | /* uv-NZ-C */ 1 | C_LO | C_LS | C_EQ | C_LT | C_LE | C_NV | C_NUF | C_LV | C_LUF | C_ZUF, |
| 258 | | /* uv-NZV- */ 1 | C_LS | C_HS | C_EQ | C_LT | C_LE | C_V | C_NUF | C_LV | C_LUF | C_ZUF, |
| 259 | | /* uv-NZVC */ 1 | C_LO | C_LS | C_EQ | C_LT | C_LE | C_V | C_NUF | C_LV | C_LUF | C_ZUF, |
| 260 | | /* uvU---- */ 1 | C_HI | C_HS | C_NE | C_GT | C_GE | C_NV | C_UF | C_LV | C_LUF | C_ZUF, |
| 261 | | /* uvU---C */ 1 | C_LO | C_LS | C_NE | C_GT | C_GE | C_NV | C_UF | C_LV | C_LUF | C_ZUF, |
| 262 | | /* uvU--V- */ 1 | C_HI | C_HS | C_NE | C_GT | C_GE | C_V | C_UF | C_LV | C_LUF | C_ZUF, |
| 263 | | /* uvU--VC */ 1 | C_LO | C_LS | C_NE | C_GT | C_GE | C_V | C_UF | C_LV | C_LUF | C_ZUF, |
| 264 | | /* uvU-Z-- */ 1 | C_LS | C_HS | C_EQ | C_LE | C_GE | C_NV | C_UF | C_LV | C_LUF | C_ZUF, |
| 265 | | /* uvU-Z-C */ 1 | C_LO | C_LS | C_EQ | C_LE | C_GE | C_NV | C_UF | C_LV | C_LUF | C_ZUF, |
| 266 | | /* uvU-ZV- */ 1 | C_LS | C_HS | C_EQ | C_LE | C_GE | C_V | C_UF | C_LV | C_LUF | C_ZUF, |
| 267 | | /* uvU-ZVC */ 1 | C_LO | C_LS | C_EQ | C_LE | C_GE | C_V | C_UF | C_LV | C_LUF | C_ZUF, |
| 268 | | /* uvUN--- */ 1 | C_HI | C_HS | C_NE | C_LT | C_LE | C_NV | C_UF | C_LV | C_LUF | C_ZUF, |
| 269 | | /* uvUN--C */ 1 | C_LO | C_LS | C_NE | C_LT | C_LE | C_NV | C_UF | C_LV | C_LUF | C_ZUF, |
| 270 | | /* uvUN-V- */ 1 | C_HI | C_HS | C_NE | C_LT | C_LE | C_V | C_UF | C_LV | C_LUF | C_ZUF, |
| 271 | | /* uvUN-VC */ 1 | C_LO | C_LS | C_NE | C_LT | C_LE | C_V | C_UF | C_LV | C_LUF | C_ZUF, |
| 272 | | /* uvUNZ-- */ 1 | C_LS | C_HS | C_EQ | C_LT | C_LE | C_NV | C_UF | C_LV | C_LUF | C_ZUF, |
| 273 | | /* uvUNZ-C */ 1 | C_LO | C_LS | C_EQ | C_LT | C_LE | C_NV | C_UF | C_LV | C_LUF | C_ZUF, |
| 274 | | /* uvUNZV- */ 1 | C_LS | C_HS | C_EQ | C_LT | C_LE | C_V | C_UF | C_LV | C_LUF | C_ZUF, |
| 275 | | /* uvUNZVC */ 1 | C_LO | C_LS | C_EQ | C_LT | C_LE | C_V | C_UF | C_LV | C_LUF | C_ZUF, |
| 276 | | }; |
| 277 | | |
| 278 | | #define CONDITION_LO() (IREG(TMR_ST) & CFLAG) |
| 279 | | #define CONDITION_LS() (IREG(TMR_ST) & (CFLAG | ZFLAG)) |
| 280 | | #define CONDITION_HI() (!(IREG(TMR_ST) & (CFLAG | ZFLAG))) |
| 281 | | #define CONDITION_HS() (!(IREG(TMR_ST) & CFLAG)) |
| 282 | | #define CONDITION_EQ() (IREG(TMR_ST) & ZFLAG) |
| 283 | | #define CONDITION_NE() (!(IREG(TMR_ST) & ZFLAG)) |
| 284 | | #define CONDITION_LT() (IREG(TMR_ST) & NFLAG) |
| 285 | | #define CONDITION_LE() (IREG(TMR_ST) & (NFLAG | ZFLAG)) |
| 286 | | #define CONDITION_GT() (!(IREG(TMR_ST) & (NFLAG | ZFLAG))) |
| 287 | | #define CONDITION_GE() (!(IREG(TMR_ST) & NFLAG)) |
| 288 | | #define CONDITION_NV() (!(IREG(TMR_ST) & VFLAG)) |
| 289 | | #define CONDITION_V() (IREG(TMR_ST) & VFLAG) |
| 290 | | #define CONDITION_NUF() (!(IREG(TMR_ST) & UFFLAG)) |
| 291 | | #define CONDITION_UF() (IREG(TMR_ST) & UFFLAG) |
| 292 | | #define CONDITION_NLV() (!(IREG(TMR_ST) & LVFLAG)) |
| 293 | | #define CONDITION_LV() (IREG(TMR_ST) & LVFLAG) |
| 294 | | #define CONDITION_NLUF() (!(IREG(TMR_ST) & LUFFLAG)) |
| 295 | | #define CONDITION_LUF() (IREG(TMR_ST) & LUFFLAG) |
| 296 | | #define CONDITION_ZUF() (IREG(TMR_ST) & (UFFLAG | ZFLAG)) |
| 297 | | |
| 298 | | inline bool tms3203x_device::condition(int which) |
| 299 | | { |
| 300 | | return (condition_table[IREG(TMR_ST) & (LUFFLAG | LVFLAG | UFFLAG | NFLAG | ZFLAG | VFLAG | CFLAG)] >> (which & 31)) & 1; |
| 301 | | } |
| 302 | | |
| 303 | | |
| 304 | | |
| 305 | | //************************************************************************** |
| 306 | | // FLOATING POINT HELPERS |
| 307 | | //************************************************************************** |
| 308 | | |
| 309 | | #if USE_FP |
| 310 | | void tms3203x_device::double_to_dsp_with_flags(double val, tmsreg &result) |
| 311 | | { |
| 312 | | int_double id; |
| 313 | | id.d = val; |
| 314 | | |
| 315 | | CLR_NZVUF(); |
| 316 | | |
| 317 | | int mantissa = ((id.i[BYTE_XOR_BE(0)] & 0x000fffff) << 11) | ((id.i[BYTE_XOR_BE(1)] & 0xffe00000) >> 21); |
| 318 | | int exponent = ((id.i[BYTE_XOR_BE(0)] & 0x7ff00000) >> 20) - 1023; |
| 319 | | if (exponent <= -128) |
| 320 | | { |
| 321 | | result.set_mantissa(0); |
| 322 | | result.set_exponent(-128); |
| 323 | | IREG(TMR_ST) |= UFFLAG | LUFFLAG | ZFLAG; |
| 324 | | } |
| 325 | | else if (exponent > 127) |
| 326 | | { |
| 327 | | if ((INT32)id.i[BYTE_XOR_BE(0)] >= 0) |
| 328 | | result.set_mantissa(0x7fffffff); |
| 329 | | else |
| 330 | | { |
| 331 | | result.set_mantissa(0x80000001); |
| 332 | | IREG(TMR_ST) |= NFLAG; |
| 333 | | } |
| 334 | | result.set_exponent(127); |
| 335 | | IREG(TMR_ST) |= VFLAG | LVFLAG; |
| 336 | | } |
| 337 | | else if (val == 0) |
| 338 | | { |
| 339 | | result.set_mantissa(0); |
| 340 | | result.set_exponent(-128); |
| 341 | | IREG(TMR_ST) |= ZFLAG; |
| 342 | | } |
| 343 | | else if ((INT32)id.i[BYTE_XOR_BE(0)] >= 0) |
| 344 | | { |
| 345 | | result.set_mantissa(mantissa); |
| 346 | | result.set_exponent(exponent); |
| 347 | | } |
| 348 | | else if (mantissa != 0) |
| 349 | | { |
| 350 | | result.set_mantissa(0x80000000 | -mantissa); |
| 351 | | result.set_exponent(exponent); |
| 352 | | IREG(TMR_ST) |= NFLAG; |
| 353 | | } |
| 354 | | else |
| 355 | | { |
| 356 | | result.set_mantissa(0x80000000); |
| 357 | | result.set_exponent(exponent - 1); |
| 358 | | IREG(TMR_ST) |= NFLAG; |
| 359 | | } |
| 360 | | } |
| 361 | | #endif |
| 362 | | |
| 363 | | // integer to floating point conversion |
| 364 | | #if USE_FP |
| 365 | | void tms3203x_device::int2float(tmsreg &srcdst) |
| 366 | | { |
| 367 | | double val = srcdst.mantissa(); |
| 368 | | double_to_dsp_with_flags(val, srcdst); |
| 369 | | } |
| 370 | | #else |
| 371 | | void tms3203x_device::int2float(tmsreg &srcdst) |
| 372 | | { |
| 373 | | UINT32 man = srcdst.mantissa(); |
| 374 | | int exp, cnt; |
| 375 | | |
| 376 | | // never overflows or underflows |
| 377 | | CLR_NZVUF(); |
| 378 | | |
| 379 | | // 0 always has exponent of -128 |
| 380 | | if (man == 0) |
| 381 | | { |
| 382 | | man = 0x80000000; |
| 383 | | exp = -128; |
| 384 | | } |
| 385 | | |
| 386 | | // check for -1 here because count_leading_ones will infinite loop |
| 387 | | else if (man == (UINT32)-1) |
| 388 | | { |
| 389 | | man = 0; |
| 390 | | exp = -1; |
| 391 | | } |
| 392 | | |
| 393 | | // positive values; count leading zeros and shift |
| 394 | | else if ((INT32)man > 0) |
| 395 | | { |
| 396 | | cnt = count_leading_zeros(man); |
| 397 | | man <<= cnt; |
| 398 | | exp = 31 - cnt; |
| 399 | | } |
| 400 | | |
| 401 | | // negative values; count leading ones and shift |
| 402 | | else |
| 403 | | { |
| 404 | | cnt = count_leading_ones(man); |
| 405 | | man <<= cnt; |
| 406 | | exp = 31 - cnt; |
| 407 | | } |
| 408 | | |
| 409 | | // set the final results and compute NZ |
| 410 | | srcdst.set_mantissa(man ^ 0x80000000); |
| 411 | | srcdst.set_exponent(exp); |
| 412 | | OR_NZF(srcdst); |
| 413 | | } |
| 414 | | #endif |
| 415 | | |
| 416 | | |
| 417 | | // floating point to integer conversion |
| 418 | | #if USE_FP |
| 419 | | void tms3203x_device::float2int(tmsreg &srcdst, int setflags) |
| 420 | | { |
| 421 | | INT32 val; |
| 422 | | |
| 423 | | if (setflags) CLR_NZVUF(); |
| 424 | | if (srcdst.exponent() > 30) |
| 425 | | { |
| 426 | | if ((INT32)srcdst.mantissa() >= 0) |
| 427 | | val = 0x7fffffff; |
| 428 | | else |
| 429 | | val = 0x80000000; |
| 430 | | if (setflags) IREG(TMR_ST) |= VFLAG | LVFLAG; |
| 431 | | } |
| 432 | | else |
| 433 | | val = floor(srcdst.as_double()); |
| 434 | | srcdst.set_mantissa(val); |
| 435 | | if (setflags) OR_NZ(val); |
| 436 | | } |
| 437 | | #else |
| 438 | | void tms3203x_device::float2int(tmsreg &srcdst, bool setflags) |
| 439 | | { |
| 440 | | INT32 man = srcdst.mantissa(); |
| 441 | | int shift = 31 - srcdst.exponent(); |
| 442 | | |
| 443 | | // never underflows |
| 444 | | if (setflags) CLR_NZVUF(); |
| 445 | | |
| 446 | | // if we've got too much to handle, overflow |
| 447 | | if (shift <= 0) |
| 448 | | { |
| 449 | | srcdst.set_mantissa((man >= 0) ? 0x7fffffff : 0x80000000); |
| 450 | | if (setflags) IREG(TMR_ST) |= VFLAG | LVFLAG; |
| 451 | | } |
| 452 | | |
| 453 | | // if we're too small, go to 0 or -1 |
| 454 | | else if (shift > 31) |
| 455 | | srcdst.set_mantissa(man >> 31); |
| 456 | | |
| 457 | | // we're in the middle; shift it |
| 458 | | else |
| 459 | | srcdst.set_mantissa((man >> shift) ^ (1 << (31 - shift))); |
| 460 | | |
| 461 | | // set the NZ flags |
| 462 | | if (setflags) OR_NZ(srcdst.mantissa()); |
| 463 | | } |
| 464 | | #endif |
| 465 | | |
| 466 | | |
| 467 | | // compute the negative of a floating point value |
| 468 | | #if USE_FP |
| 469 | | void tms3203x_device::negf(tmsreg &dst, tmsreg tmsreg &src) |
| 470 | | { |
| 471 | | double val = -src.as_double(); |
| 472 | | double_to_dsp_with_flags(val, dst); |
| 473 | | } |
| 474 | | #else |
| 475 | | void tms3203x_device::negf(tmsreg &dst, tmsreg &src) |
| 476 | | { |
| 477 | | INT32 man = src.mantissa(); |
| 478 | | |
| 479 | | CLR_NZVUF(); |
| 480 | | |
| 481 | | if (src.exponent() == -128) |
| 482 | | { |
| 483 | | dst.set_mantissa(0); |
| 484 | | dst.set_exponent(-128); |
| 485 | | } |
| 486 | | else if ((man & 0x7fffffff) != 0) |
| 487 | | { |
| 488 | | dst.set_mantissa(-man); |
| 489 | | dst.set_exponent(src.exponent()); |
| 490 | | } |
| 491 | | else |
| 492 | | { |
| 493 | | dst.set_mantissa(man ^ 0x80000000); |
| 494 | | if (man == 0) |
| 495 | | dst.set_exponent(src.exponent() - 1); |
| 496 | | else |
| 497 | | dst.set_exponent(src.exponent() + 1); |
| 498 | | } |
| 499 | | OR_NZF(dst); |
| 500 | | } |
| 501 | | #endif |
| 502 | | |
| 503 | | |
| 504 | | |
| 505 | | // add two floating point values |
| 506 | | #if USE_FP |
| 507 | | void tms3203x_device::addf(tmsreg &dst, tmsreg &src1, tmsreg &src2) |
| 508 | | { |
| 509 | | double val = src1.as_double() + src2.as_double(); |
| 510 | | double_to_dsp_with_flags(val, dst); |
| 511 | | } |
| 512 | | #else |
| 513 | | void tms3203x_device::addf(tmsreg &dst, tmsreg &src1, tmsreg &src2) |
| 514 | | { |
| 515 | | INT64 man; |
| 516 | | INT64 m1, m2; |
| 517 | | int exp, cnt; |
| 518 | | |
| 519 | | // reset over/underflow conditions |
| 520 | | CLR_NZVUF(); |
| 521 | | |
| 522 | | // first check for 0 operands |
| 523 | | if (src1.exponent() == -128) |
| 524 | | { |
| 525 | | dst = src2; |
| 526 | | OR_NZF(dst); |
| 527 | | return; |
| 528 | | } |
| 529 | | if (src2.exponent() == -128) |
| 530 | | { |
| 531 | | dst = src1; |
| 532 | | OR_NZF(dst); |
| 533 | | return; |
| 534 | | } |
| 535 | | |
| 536 | | // extract mantissas from 1.0.31 values to 1.1.31 values |
| 537 | | m1 = (INT64)src1.mantissa() ^ 0x80000000; |
| 538 | | m2 = (INT64)src2.mantissa() ^ 0x80000000; |
| 539 | | |
| 540 | | // normalize based on the exponent |
| 541 | | if (src1.exponent() > src2.exponent()) |
| 542 | | { |
| 543 | | exp = src1.exponent(); |
| 544 | | cnt = exp - src2.exponent(); |
| 545 | | if (cnt >= 32) |
| 546 | | { |
| 547 | | dst = src1; |
| 548 | | OR_NZF(dst); |
| 549 | | return; |
| 550 | | } |
| 551 | | m2 >>= cnt; |
| 552 | | } |
| 553 | | else |
| 554 | | { |
| 555 | | exp = src2.exponent(); |
| 556 | | cnt = exp - src1.exponent(); |
| 557 | | if (cnt >= 32) |
| 558 | | { |
| 559 | | dst = src2; |
| 560 | | OR_NZF(dst); |
| 561 | | return; |
| 562 | | } |
| 563 | | m1 >>= cnt; |
| 564 | | } |
| 565 | | |
| 566 | | // add |
| 567 | | man = m1 + m2; |
| 568 | | |
| 569 | | // if the mantissa is zero, set the exponent appropriately |
| 570 | | if (man == 0 || exp == -128) |
| 571 | | { |
| 572 | | exp = -128; |
| 573 | | man = 0x80000000; |
| 574 | | } |
| 575 | | |
| 576 | | // if the mantissa is >= 2.0 or < -2.0, normalize |
| 577 | | else if (man >= ((INT64)2 << 31) || man < ((INT64)-2 << 31)) |
| 578 | | { |
| 579 | | man >>= 1; |
| 580 | | exp++; |
| 581 | | } |
| 582 | | |
| 583 | | // if the mantissa is < 1.0 and > -1.0, normalize |
| 584 | | else if (man < ((INT64)1 << 31) && man >= ((INT64)-1 << 31)) |
| 585 | | { |
| 586 | | if (man > 0) |
| 587 | | { |
| 588 | | cnt = count_leading_zeros((UINT32)man); |
| 589 | | man <<= cnt; |
| 590 | | exp -= cnt; |
| 591 | | } |
| 592 | | else |
| 593 | | { |
| 594 | | cnt = count_leading_ones((UINT32)man); |
| 595 | | man <<= cnt; |
| 596 | | exp -= cnt; |
| 597 | | } |
| 598 | | } |
| 599 | | |
| 600 | | // check for underflow |
| 601 | | if (exp <= -128) |
| 602 | | { |
| 603 | | man = 0x80000000; |
| 604 | | exp = -128; |
| 605 | | IREG(TMR_ST) |= UFFLAG | LUFFLAG; |
| 606 | | } |
| 607 | | |
| 608 | | // check for overflow |
| 609 | | else if (exp > 127) |
| 610 | | { |
| 611 | | man = (man < 0) ? 0x00000000 : 0xffffffff; |
| 612 | | exp = 127; |
| 613 | | IREG(TMR_ST) |= VFLAG | LVFLAG; |
| 614 | | } |
| 615 | | |
| 616 | | // store the result back, removing the implicit one and putting |
| 617 | | // back the sign bit |
| 618 | | dst.set_mantissa((UINT32)man ^ 0x80000000); |
| 619 | | dst.set_exponent(exp); |
| 620 | | OR_NZF(dst); |
| 621 | | } |
| 622 | | #endif |
| 623 | | |
| 624 | | |
| 625 | | // subtract two floating point values |
| 626 | | #if USE_FP |
| 627 | | void tms3203x_device::subf(tmsreg &dst, tmsreg &src1, tmsreg &src2) |
| 628 | | { |
| 629 | | double val = src1.as_double() - src2.as_double(); |
| 630 | | double_to_dsp_with_flags(val, dst); |
| 631 | | } |
| 632 | | #else |
| 633 | | void tms3203x_device::subf(tmsreg &dst, tmsreg &src1, tmsreg &src2) |
| 634 | | { |
| 635 | | INT64 man; |
| 636 | | INT64 m1, m2; |
| 637 | | int exp, cnt; |
| 638 | | |
| 639 | | // reset over/underflow conditions |
| 640 | | CLR_NZVUF(); |
| 641 | | |
| 642 | | // first check for 0 operands |
| 643 | | if (src2.exponent() == -128) |
| 644 | | { |
| 645 | | dst = src1; |
| 646 | | OR_NZF(dst); |
| 647 | | return; |
| 648 | | } |
| 649 | | |
| 650 | | // extract mantissas from 1.0.31 values to 1.1.31 values |
| 651 | | m1 = (INT64)src1.mantissa() ^ 0x80000000; |
| 652 | | m2 = (INT64)src2.mantissa() ^ 0x80000000; |
| 653 | | |
| 654 | | // normalize based on the exponent |
| 655 | | if (src1.exponent() > src2.exponent()) |
| 656 | | { |
| 657 | | exp = src1.exponent(); |
| 658 | | cnt = exp - src2.exponent(); |
| 659 | | if (cnt >= 32) |
| 660 | | { |
| 661 | | dst = src1; |
| 662 | | OR_NZF(dst); |
| 663 | | return; |
| 664 | | } |
| 665 | | m2 >>= cnt; |
| 666 | | } |
| 667 | | else |
| 668 | | { |
| 669 | | exp = src2.exponent(); |
| 670 | | cnt = exp - src1.exponent(); |
| 671 | | if (cnt >= 32) |
| 672 | | { |
| 673 | | negf(dst, src2); |
| 674 | | return; |
| 675 | | } |
| 676 | | m1 >>= cnt; |
| 677 | | } |
| 678 | | |
| 679 | | // subtract |
| 680 | | man = m1 - m2; |
| 681 | | |
| 682 | | // if the mantissa is zero, set the exponent appropriately |
| 683 | | if (man == 0 || exp == -128) |
| 684 | | { |
| 685 | | exp = -128; |
| 686 | | man = 0x80000000; |
| 687 | | } |
| 688 | | |
| 689 | | // if the mantissa is >= 2.0 or < -2.0, normalize |
| 690 | | else if (man >= ((INT64)2 << 31) || man < ((INT64)-2 << 31)) |
| 691 | | { |
| 692 | | man >>= 1; |
| 693 | | exp++; |
| 694 | | } |
| 695 | | |
| 696 | | // if the mantissa is < 1.0 and > -1.0, normalize |
| 697 | | else if (man < ((INT64)1 << 31) && man >= ((INT64)-1 << 31)) |
| 698 | | { |
| 699 | | if (man > 0) |
| 700 | | { |
| 701 | | cnt = count_leading_zeros((UINT32)man); |
| 702 | | man <<= cnt; |
| 703 | | exp -= cnt; |
| 704 | | } |
| 705 | | else |
| 706 | | { |
| 707 | | cnt = count_leading_ones((UINT32)man); |
| 708 | | man <<= cnt; |
| 709 | | exp -= cnt; |
| 710 | | } |
| 711 | | } |
| 712 | | |
| 713 | | // check for underflow |
| 714 | | if (exp <= -128) |
| 715 | | { |
| 716 | | // make sure a 0 result doesn't set underflow |
| 717 | | if (man != 0 || exp < -128) |
| 718 | | IREG(TMR_ST) |= UFFLAG | LUFFLAG; |
| 719 | | man = 0x80000000; |
| 720 | | exp = -128; |
| 721 | | } |
| 722 | | |
| 723 | | // check for overflow |
| 724 | | else if (exp > 127) |
| 725 | | { |
| 726 | | man = (man < 0) ? 0x00000000 : 0xffffffff; |
| 727 | | exp = 127; |
| 728 | | IREG(TMR_ST) |= VFLAG | LVFLAG; |
| 729 | | } |
| 730 | | |
| 731 | | // store the result back, removing the implicit one and putting |
| 732 | | // back the sign bit |
| 733 | | dst.set_mantissa((UINT32)man ^ 0x80000000); |
| 734 | | dst.set_exponent(exp); |
| 735 | | OR_NZF(dst); |
| 736 | | } |
| 737 | | #endif |
| 738 | | |
| 739 | | |
| 740 | | // multiply two floating point values |
| 741 | | #if USE_FP |
| 742 | | void tms3203x_device::mpyf(tmsreg &dst, tmsreg &src1, tmsreg &src2) |
| 743 | | { |
| 744 | | double val = (double)src1.as_float() * (double)src2.as_float(); |
| 745 | | double_to_dsp_with_flags(val, dst); |
| 746 | | } |
| 747 | | #else |
| 748 | | void tms3203x_device::mpyf(tmsreg &dst, tmsreg &src1, tmsreg &src2) |
| 749 | | { |
| 750 | | // reset over/underflow conditions |
| 751 | | CLR_NZVUF(); |
| 752 | | |
| 753 | | // first check for 0 multipliers and return 0 in any case |
| 754 | | if (src1.exponent() == -128 || src2.exponent() == -128) |
| 755 | | { |
| 756 | | dst.set_mantissa(0); |
| 757 | | dst.set_exponent(-128); |
| 758 | | OR_NZF(dst); |
| 759 | | return; |
| 760 | | } |
| 761 | | |
| 762 | | // convert the mantissas from 1.0.31 numbers to 1.1.23 numbers |
| 763 | | INT32 m1 = (src1.mantissa() >> 8) ^ 0x800000; |
| 764 | | INT32 m2 = (src2.mantissa() >> 8) ^ 0x800000; |
| 765 | | |
| 766 | | // multiply the mantissas and add the exponents |
| 767 | | INT64 man = (INT64)m1 * (INT64)m2; |
| 768 | | int exp = src1.exponent() + src2.exponent(); |
| 769 | | |
| 770 | | // chop off the low bits, going from 1.2.46 down to 1.2.31 |
| 771 | | man >>= 46 - 31; |
| 772 | | |
| 773 | | // if the mantissa is zero, set the exponent appropriately |
| 774 | | if (man == 0) |
| 775 | | { |
| 776 | | exp = -128; |
| 777 | | man = 0x80000000; |
| 778 | | } |
| 779 | | |
| 780 | | // if the mantissa is >= 2.0 or <= -2.0, normalize |
| 781 | | else if (man >= ((INT64)2 << 31)) |
| 782 | | { |
| 783 | | man >>= 1; |
| 784 | | exp++; |
| 785 | | if (man >= ((INT64)2 << 31)) |
| 786 | | { |
| 787 | | man >>= 1; |
| 788 | | exp++; |
| 789 | | } |
| 790 | | } |
| 791 | | |
| 792 | | // if the mantissa is >= 2.0 or <= -2.0, normalize |
| 793 | | else if (man < ((INT64)-2 << 31)) |
| 794 | | { |
| 795 | | man >>= 1; |
| 796 | | exp++; |
| 797 | | } |
| 798 | | |
| 799 | | // check for underflow |
| 800 | | if (exp <= -128) |
| 801 | | { |
| 802 | | man = 0x80000000; |
| 803 | | exp = -128; |
| 804 | | IREG(TMR_ST) |= UFFLAG | LUFFLAG; |
| 805 | | } |
| 806 | | |
| 807 | | // check for overflow |
| 808 | | else if (exp > 127) |
| 809 | | { |
| 810 | | man = (man < 0) ? 0x00000000 : 0xffffffff; |
| 811 | | exp = 127; |
| 812 | | IREG(TMR_ST) |= VFLAG | LVFLAG; |
| 813 | | } |
| 814 | | |
| 815 | | // store the result back, removing the implicit one and putting |
| 816 | | // back the sign bit |
| 817 | | dst.set_mantissa((UINT32)man ^ 0x80000000); |
| 818 | | dst.set_exponent(exp); |
| 819 | | OR_NZF(dst); |
| 820 | | } |
| 821 | | #endif |
| 822 | | |
| 823 | | |
| 824 | | // normalize a floating point value |
| 825 | | #if USE_FP |
| 826 | | void tms3203x_device::norm(tmsreg &dst, tmsreg &src) |
| 827 | | { |
| 828 | | fatalerror("norm not implemented\n"); |
| 829 | | } |
| 830 | | #else |
| 831 | | void tms3203x_device::norm(tmsreg &dst, tmsreg &src) |
| 832 | | { |
| 833 | | INT32 man = src.mantissa(); |
| 834 | | int exp = src.exponent(); |
| 835 | | |
| 836 | | CLR_NZVUF(); |
| 837 | | |
| 838 | | if (exp == -128 || man == 0) |
| 839 | | { |
| 840 | | dst.set_mantissa(0); |
| 841 | | dst.set_exponent(-128); |
| 842 | | if (man != 0) |
| 843 | | IREG(TMR_ST) |= UFFLAG | LUFFLAG; |
| 844 | | } |
| 845 | | else |
| 846 | | { |
| 847 | | int cnt; |
| 848 | | if (man > 0) |
| 849 | | { |
| 850 | | cnt = count_leading_zeros((UINT32)man); |
| 851 | | man <<= cnt; |
| 852 | | exp -= cnt; |
| 853 | | } |
| 854 | | else |
| 855 | | { |
| 856 | | cnt = count_leading_ones((UINT32)man); |
| 857 | | man <<= cnt; |
| 858 | | exp -= cnt; |
| 859 | | } |
| 860 | | |
| 861 | | // check for underflow |
| 862 | | if (exp <= -128) |
| 863 | | { |
| 864 | | man = 0x00000000; |
| 865 | | exp = -128; |
| 866 | | IREG(TMR_ST) |= UFFLAG | LUFFLAG; |
| 867 | | } |
| 868 | | } |
| 869 | | |
| 870 | | dst.set_mantissa(man); |
| 871 | | dst.set_exponent(exp); |
| 872 | | OR_NZF(dst); |
| 873 | | } |
| 874 | | #endif |
| 875 | | |
| 876 | | |
| 877 | | |
| 878 | | |
| 879 | | //************************************************************************** |
| 880 | | // INDIRECT MEMORY REFS |
| 881 | | //************************************************************************** |
| 882 | | |
| 883 | | // immediate displacement variants |
| 884 | | |
| 885 | | UINT32 tms3203x_device::mod00_d(UINT32 op, UINT8 ar) |
| 886 | | { |
| 887 | | int reg = TMR_AR0 + (ar & 7); |
| 888 | | return IREG(reg) + (UINT8)op; |
| 889 | | } |
| 890 | | |
| 891 | | UINT32 tms3203x_device::mod01_d(UINT32 op, UINT8 ar) |
| 892 | | { |
| 893 | | int reg = TMR_AR0 + (ar & 7); |
| 894 | | return IREG(reg) - (UINT8)op; |
| 895 | | } |
| 896 | | |
| 897 | | UINT32 tms3203x_device::mod02_d(UINT32 op, UINT8 ar) |
| 898 | | { |
| 899 | | int reg = TMR_AR0 + (ar & 7); |
| 900 | | IREG(reg) += (UINT8)op; |
| 901 | | return IREG(reg); |
| 902 | | } |
| 903 | | |
| 904 | | UINT32 tms3203x_device::mod03_d(UINT32 op, UINT8 ar) |
| 905 | | { |
| 906 | | int reg = TMR_AR0 + (ar & 7); |
| 907 | | IREG(reg) -= (UINT8)op; |
| 908 | | return IREG(reg); |
| 909 | | } |
| 910 | | |
| 911 | | UINT32 tms3203x_device::mod04_d(UINT32 op, UINT8 ar) |
| 912 | | { |
| 913 | | int reg = TMR_AR0 + (ar & 7); |
| 914 | | UINT32 result = IREG(reg); |
| 915 | | IREG(reg) += (UINT8)op; |
| 916 | | return result; |
| 917 | | } |
| 918 | | |
| 919 | | UINT32 tms3203x_device::mod05_d(UINT32 op, UINT8 ar) |
| 920 | | { |
| 921 | | int reg = TMR_AR0 + (ar & 7); |
| 922 | | UINT32 result = IREG(reg); |
| 923 | | IREG(reg) -= (UINT8)op; |
| 924 | | return result; |
| 925 | | } |
| 926 | | |
| 927 | | UINT32 tms3203x_device::mod06_d(UINT32 op, UINT8 ar) |
| 928 | | { |
| 929 | | int reg = TMR_AR0 + (ar & 7); |
| 930 | | UINT32 result = IREG(reg); |
| 931 | | INT32 temp = (result & m_bkmask) + (UINT8)op; |
| 932 | | if (temp >= IREG(TMR_BK)) |
| 933 | | temp -= IREG(TMR_BK); |
| 934 | | IREG(reg) = (IREG(reg) & ~m_bkmask) | (temp & m_bkmask); |
| 935 | | return result; |
| 936 | | } |
| 937 | | |
| 938 | | UINT32 tms3203x_device::mod07_d(UINT32 op, UINT8 ar) |
| 939 | | { |
| 940 | | int reg = TMR_AR0 + (ar & 7); |
| 941 | | UINT32 result = IREG(reg); |
| 942 | | INT32 temp = (result & m_bkmask) - (UINT8)op; |
| 943 | | if (temp < 0) |
| 944 | | temp += IREG(TMR_BK); |
| 945 | | IREG(reg) = (IREG(reg) & ~m_bkmask) | (temp & m_bkmask); |
| 946 | | return result; |
| 947 | | } |
| 948 | | |
| 949 | | |
| 950 | | // immediate displacement variants (implied 1) |
| 951 | | |
| 952 | | UINT32 tms3203x_device::mod00_1(UINT32 op, UINT8 ar) |
| 953 | | { |
| 954 | | int reg = TMR_AR0 + (ar & 7); |
| 955 | | return IREG(reg) + 1; |
| 956 | | } |
| 957 | | |
| 958 | | UINT32 tms3203x_device::mod01_1(UINT32 op, UINT8 ar) |
| 959 | | { |
| 960 | | int reg = TMR_AR0 + (ar & 7); |
| 961 | | return IREG(reg) - 1; |
| 962 | | } |
| 963 | | |
| 964 | | UINT32 tms3203x_device::mod02_1(UINT32 op, UINT8 ar) |
| 965 | | { |
| 966 | | int reg = TMR_AR0 + (ar & 7); |
| 967 | | return ++IREG(reg); |
| 968 | | } |
| 969 | | |
| 970 | | UINT32 tms3203x_device::mod03_1(UINT32 op, UINT8 ar) |
| 971 | | { |
| 972 | | int reg = TMR_AR0 + (ar & 7); |
| 973 | | return --IREG(reg); |
| 974 | | } |
| 975 | | |
| 976 | | UINT32 tms3203x_device::mod04_1(UINT32 op, UINT8 ar) |
| 977 | | { |
| 978 | | int reg = TMR_AR0 + (ar & 7); |
| 979 | | return IREG(reg)++; |
| 980 | | } |
| 981 | | |
| 982 | | UINT32 tms3203x_device::mod05_1(UINT32 op, UINT8 ar) |
| 983 | | { |
| 984 | | int reg = TMR_AR0 + (ar & 7); |
| 985 | | return IREG(reg)--; |
| 986 | | } |
| 987 | | |
| 988 | | UINT32 tms3203x_device::mod06_1(UINT32 op, UINT8 ar) |
| 989 | | { |
| 990 | | int reg = TMR_AR0 + (ar & 7); |
| 991 | | UINT32 result = IREG(reg); |
| 992 | | INT32 temp = (result & m_bkmask) + 1; |
| 993 | | if (temp >= IREG(TMR_BK)) |
| 994 | | temp -= IREG(TMR_BK); |
| 995 | | IREG(reg) = (IREG(reg) & ~m_bkmask) | (temp & m_bkmask); |
| 996 | | return result; |
| 997 | | } |
| 998 | | |
| 999 | | UINT32 tms3203x_device::mod07_1(UINT32 op, UINT8 ar) |
| 1000 | | { |
| 1001 | | int reg = TMR_AR0 + (ar & 7); |
| 1002 | | UINT32 result = IREG(reg); |
| 1003 | | INT32 temp = (result & m_bkmask) - 1; |
| 1004 | | if (temp < 0) |
| 1005 | | temp += IREG(TMR_BK); |
| 1006 | | IREG(reg) = (IREG(reg) & ~m_bkmask) | (temp & m_bkmask); |
| 1007 | | return result; |
| 1008 | | } |
| 1009 | | |
| 1010 | | |
| 1011 | | // IR0 displacement variants |
| 1012 | | |
| 1013 | | UINT32 tms3203x_device::mod08(UINT32 op, UINT8 ar) |
| 1014 | | { |
| 1015 | | int reg = TMR_AR0 + (ar & 7); |
| 1016 | | return IREG(reg) + IREG(TMR_IR0); |
| 1017 | | } |
| 1018 | | |
| 1019 | | UINT32 tms3203x_device::mod09(UINT32 op, UINT8 ar) |
| 1020 | | { |
| 1021 | | int reg = TMR_AR0 + (ar & 7); |
| 1022 | | return IREG(reg) - IREG(TMR_IR0); |
| 1023 | | } |
| 1024 | | |
| 1025 | | UINT32 tms3203x_device::mod0a(UINT32 op, UINT8 ar) |
| 1026 | | { |
| 1027 | | int reg = TMR_AR0 + (ar & 7); |
| 1028 | | IREG(reg) += IREG(TMR_IR0); |
| 1029 | | return IREG(reg); |
| 1030 | | } |
| 1031 | | |
| 1032 | | UINT32 tms3203x_device::mod0b(UINT32 op, UINT8 ar) |
| 1033 | | { |
| 1034 | | int reg = TMR_AR0 + (ar & 7); |
| 1035 | | IREG(reg) -= IREG(TMR_IR0); |
| 1036 | | return IREG(reg); |
| 1037 | | } |
| 1038 | | |
| 1039 | | UINT32 tms3203x_device::mod0c(UINT32 op, UINT8 ar) |
| 1040 | | { |
| 1041 | | int reg = TMR_AR0 + (ar & 7); |
| 1042 | | UINT32 result = IREG(reg); |
| 1043 | | IREG(reg) += IREG(TMR_IR0); |
| 1044 | | return result; |
| 1045 | | } |
| 1046 | | |
| 1047 | | UINT32 tms3203x_device::mod0d(UINT32 op, UINT8 ar) |
| 1048 | | { |
| 1049 | | int reg = TMR_AR0 + (ar & 7); |
| 1050 | | UINT32 result = IREG(reg); |
| 1051 | | IREG(reg) -= IREG(TMR_IR0); |
| 1052 | | return result; |
| 1053 | | } |
| 1054 | | |
| 1055 | | UINT32 tms3203x_device::mod0e(UINT32 op, UINT8 ar) |
| 1056 | | { |
| 1057 | | int reg = TMR_AR0 + (ar & 7); |
| 1058 | | UINT32 result = IREG(reg); |
| 1059 | | INT32 temp = (result & m_bkmask) + IREG(TMR_IR0); |
| 1060 | | if (temp >= IREG(TMR_BK)) |
| 1061 | | temp -= IREG(TMR_BK); |
| 1062 | | IREG(reg) = (IREG(reg) & ~m_bkmask) | (temp & m_bkmask); |
| 1063 | | return result; |
| 1064 | | } |
| 1065 | | |
| 1066 | | UINT32 tms3203x_device::mod0f(UINT32 op, UINT8 ar) |
| 1067 | | { |
| 1068 | | int reg = TMR_AR0 + (ar & 7); |
| 1069 | | UINT32 result = IREG(reg); |
| 1070 | | INT32 temp = (result & m_bkmask) - IREG(TMR_IR0); |
| 1071 | | if (temp < 0) |
| 1072 | | temp += IREG(TMR_BK); |
| 1073 | | IREG(reg) = (IREG(reg) & ~m_bkmask) | (temp & m_bkmask); |
| 1074 | | return result; |
| 1075 | | } |
| 1076 | | |
| 1077 | | |
| 1078 | | // IR1 displacement variants |
| 1079 | | |
| 1080 | | UINT32 tms3203x_device::mod10(UINT32 op, UINT8 ar) |
| 1081 | | { |
| 1082 | | int reg = TMR_AR0 + (ar & 7); |
| 1083 | | return IREG(reg) + IREG(TMR_IR1); |
| 1084 | | } |
| 1085 | | |
| 1086 | | UINT32 tms3203x_device::mod11(UINT32 op, UINT8 ar) |
| 1087 | | { |
| 1088 | | int reg = TMR_AR0 + (ar & 7); |
| 1089 | | return IREG(reg) - IREG(TMR_IR1); |
| 1090 | | } |
| 1091 | | |
| 1092 | | UINT32 tms3203x_device::mod12(UINT32 op, UINT8 ar) |
| 1093 | | { |
| 1094 | | int reg = TMR_AR0 + (ar & 7); |
| 1095 | | IREG(reg) += IREG(TMR_IR1); |
| 1096 | | return IREG(reg); |
| 1097 | | } |
| 1098 | | |
| 1099 | | UINT32 tms3203x_device::mod13(UINT32 op, UINT8 ar) |
| 1100 | | { |
| 1101 | | int reg = TMR_AR0 + (ar & 7); |
| 1102 | | IREG(reg) -= IREG(TMR_IR1); |
| 1103 | | return IREG(reg); |
| 1104 | | } |
| 1105 | | |
| 1106 | | UINT32 tms3203x_device::mod14(UINT32 op, UINT8 ar) |
| 1107 | | { |
| 1108 | | int reg = TMR_AR0 + (ar & 7); |
| 1109 | | UINT32 result = IREG(reg); |
| 1110 | | IREG(reg) += IREG(TMR_IR1); |
| 1111 | | return result; |
| 1112 | | } |
| 1113 | | |
| 1114 | | UINT32 tms3203x_device::mod15(UINT32 op, UINT8 ar) |
| 1115 | | { |
| 1116 | | int reg = TMR_AR0 + (ar & 7); |
| 1117 | | UINT32 result = IREG(reg); |
| 1118 | | IREG(reg) -= IREG(TMR_IR1); |
| 1119 | | return result; |
| 1120 | | } |
| 1121 | | |
| 1122 | | UINT32 tms3203x_device::mod16(UINT32 op, UINT8 ar) |
| 1123 | | { |
| 1124 | | int reg = TMR_AR0 + (ar & 7); |
| 1125 | | UINT32 result = IREG(reg); |
| 1126 | | INT32 temp = (result & m_bkmask) + IREG(TMR_IR1); |
| 1127 | | if (temp >= IREG(TMR_BK)) |
| 1128 | | temp -= IREG(TMR_BK); |
| 1129 | | IREG(reg) = (IREG(reg) & ~m_bkmask) | (temp & m_bkmask); |
| 1130 | | return result; |
| 1131 | | } |
| 1132 | | |
| 1133 | | UINT32 tms3203x_device::mod17(UINT32 op, UINT8 ar) |
| 1134 | | { |
| 1135 | | int reg = TMR_AR0 + (ar & 7); |
| 1136 | | UINT32 result = IREG(reg); |
| 1137 | | INT32 temp = (result & m_bkmask) - IREG(TMR_IR1); |
| 1138 | | if (temp < 0) |
| 1139 | | temp += IREG(TMR_BK); |
| 1140 | | IREG(reg) = (IREG(reg) & ~m_bkmask) | (temp & m_bkmask); |
| 1141 | | return result; |
| 1142 | | } |
| 1143 | | |
| 1144 | | |
| 1145 | | // special variants |
| 1146 | | |
| 1147 | | UINT32 tms3203x_device::mod18(UINT32 op, UINT8 ar) |
| 1148 | | { |
| 1149 | | int reg = TMR_AR0 + (ar & 7); |
| 1150 | | return IREG(reg); |
| 1151 | | } |
| 1152 | | |
| 1153 | | UINT32 tms3203x_device::mod19(UINT32 op, UINT8 ar) |
| 1154 | | { |
| 1155 | | unimplemented(op); |
| 1156 | | return 0; |
| 1157 | | } |
| 1158 | | |
| 1159 | | UINT32 tms3203x_device::modillegal(UINT32 op, UINT8 ar) |
| 1160 | | { |
| 1161 | | illegal(op); |
| 1162 | | return 0; |
| 1163 | | } |
| 1164 | | |
| 1165 | | |
| 1166 | | // immediate displacement variants (implied 1) |
| 1167 | | |
| 1168 | | UINT32 tms3203x_device::mod00_1_def(UINT32 op, UINT8 ar, UINT32 *&defptrptr) |
| 1169 | | { |
| 1170 | | int reg = TMR_AR0 + (ar & 7); |
| 1171 | | return IREG(reg) + 1; |
| 1172 | | } |
| 1173 | | |
| 1174 | | UINT32 tms3203x_device::mod01_1_def(UINT32 op, UINT8 ar, UINT32 *&defptrptr) |
| 1175 | | { |
| 1176 | | int reg = TMR_AR0 + (ar & 7); |
| 1177 | | return IREG(reg) - 1; |
| 1178 | | } |
| 1179 | | |
| 1180 | | UINT32 tms3203x_device::mod02_1_def(UINT32 op, UINT8 ar, UINT32 *&defptrptr) |
| 1181 | | { |
| 1182 | | int reg = TMR_AR0 + (ar & 7); |
| 1183 | | UINT32 defval = IREG(reg) + 1; |
| 1184 | | *defptrptr = defval; |
| 1185 | | defptrptr = &IREG(reg); |
| 1186 | | return defval; |
| 1187 | | } |
| 1188 | | |
| 1189 | | UINT32 tms3203x_device::mod03_1_def(UINT32 op, UINT8 ar, UINT32 *&defptrptr) |
| 1190 | | { |
| 1191 | | int reg = TMR_AR0 + (ar & 7); |
| 1192 | | UINT32 defval = IREG(reg) - 1; |
| 1193 | | *defptrptr = defval; |
| 1194 | | defptrptr = &IREG(reg); |
| 1195 | | return defval; |
| 1196 | | } |
| 1197 | | |
| 1198 | | UINT32 tms3203x_device::mod04_1_def(UINT32 op, UINT8 ar, UINT32 *&defptrptr) |
| 1199 | | { |
| 1200 | | int reg = TMR_AR0 + (ar & 7); |
| 1201 | | *defptrptr = IREG(reg) + 1; |
| 1202 | | defptrptr = &IREG(reg); |
| 1203 | | return IREG(reg); |
| 1204 | | } |
| 1205 | | |
| 1206 | | UINT32 tms3203x_device::mod05_1_def(UINT32 op, UINT8 ar, UINT32 *&defptrptr) |
| 1207 | | { |
| 1208 | | int reg = TMR_AR0 + (ar & 7); |
| 1209 | | *defptrptr = IREG(reg) - 1; |
| 1210 | | defptrptr = &IREG(reg); |
| 1211 | | return IREG(reg); |
| 1212 | | } |
| 1213 | | |
| 1214 | | UINT32 tms3203x_device::mod06_1_def(UINT32 op, UINT8 ar, UINT32 *&defptrptr) |
| 1215 | | { |
| 1216 | | int reg = TMR_AR0 + (ar & 7); |
| 1217 | | UINT32 result = IREG(reg); |
| 1218 | | INT32 temp = (result & m_bkmask) + 1; |
| 1219 | | if (temp >= IREG(TMR_BK)) |
| 1220 | | temp -= IREG(TMR_BK); |
| 1221 | | *defptrptr = (IREG(reg) & ~m_bkmask) | (temp & m_bkmask); |
| 1222 | | defptrptr = &IREG(reg); |
| 1223 | | return result; |
| 1224 | | } |
| 1225 | | |
| 1226 | | UINT32 tms3203x_device::mod07_1_def(UINT32 op, UINT8 ar, UINT32 *&defptrptr) |
| 1227 | | { |
| 1228 | | int reg = TMR_AR0 + (ar & 7); |
| 1229 | | UINT32 result = IREG(reg); |
| 1230 | | INT32 temp = (result & m_bkmask) - 1; |
| 1231 | | if (temp < 0) |
| 1232 | | temp += IREG(TMR_BK); |
| 1233 | | *defptrptr = (IREG(reg) & ~m_bkmask) | (temp & m_bkmask); |
| 1234 | | defptrptr = &IREG(reg); |
| 1235 | | return result; |
| 1236 | | } |
| 1237 | | |
| 1238 | | |
| 1239 | | // IR0 displacement variants |
| 1240 | | |
| 1241 | | UINT32 tms3203x_device::mod08_def(UINT32 op, UINT8 ar, UINT32 *&defptrptr) |
| 1242 | | { |
| 1243 | | int reg = TMR_AR0 + (ar & 7); |
| 1244 | | return IREG(reg) + IREG(TMR_IR0); |
| 1245 | | } |
| 1246 | | |
| 1247 | | UINT32 tms3203x_device::mod09_def(UINT32 op, UINT8 ar, UINT32 *&defptrptr) |
| 1248 | | { |
| 1249 | | int reg = TMR_AR0 + (ar & 7); |
| 1250 | | return IREG(reg) - IREG(TMR_IR0); |
| 1251 | | } |
| 1252 | | |
| 1253 | | UINT32 tms3203x_device::mod0a_def(UINT32 op, UINT8 ar, UINT32 *&defptrptr) |
| 1254 | | { |
| 1255 | | int reg = TMR_AR0 + (ar & 7); |
| 1256 | | UINT32 defval = IREG(reg) + IREG(TMR_IR0); |
| 1257 | | *defptrptr = defval; |
| 1258 | | defptrptr = &IREG(reg); |
| 1259 | | return defval; |
| 1260 | | } |
| 1261 | | |
| 1262 | | UINT32 tms3203x_device::mod0b_def(UINT32 op, UINT8 ar, UINT32 *&defptrptr) |
| 1263 | | { |
| 1264 | | int reg = TMR_AR0 + (ar & 7); |
| 1265 | | UINT32 defval = IREG(reg) - IREG(TMR_IR0); |
| 1266 | | *defptrptr = defval; |
| 1267 | | defptrptr = &IREG(reg); |
| 1268 | | return defval; |
| 1269 | | } |
| 1270 | | |
| 1271 | | UINT32 tms3203x_device::mod0c_def(UINT32 op, UINT8 ar, UINT32 *&defptrptr) |
| 1272 | | { |
| 1273 | | int reg = TMR_AR0 + (ar & 7); |
| 1274 | | *defptrptr = IREG(reg) + IREG(TMR_IR0); |
| 1275 | | defptrptr = &IREG(reg); |
| 1276 | | return IREG(reg); |
| 1277 | | } |
| 1278 | | |
| 1279 | | UINT32 tms3203x_device::mod0d_def(UINT32 op, UINT8 ar, UINT32 *&defptrptr) |
| 1280 | | { |
| 1281 | | int reg = TMR_AR0 + (ar & 7); |
| 1282 | | *defptrptr = IREG(reg) - IREG(TMR_IR0); |
| 1283 | | defptrptr = &IREG(reg); |
| 1284 | | return IREG(reg); |
| 1285 | | } |
| 1286 | | |
| 1287 | | UINT32 tms3203x_device::mod0e_def(UINT32 op, UINT8 ar, UINT32 *&defptrptr) |
| 1288 | | { |
| 1289 | | int reg = TMR_AR0 + (ar & 7); |
| 1290 | | UINT32 result = IREG(reg); |
| 1291 | | INT32 temp = (result & m_bkmask) + IREG(TMR_IR0); |
| 1292 | | if (temp >= IREG(TMR_BK)) |
| 1293 | | temp -= IREG(TMR_BK); |
| 1294 | | *defptrptr = (IREG(reg) & ~m_bkmask) | (temp & m_bkmask); |
| 1295 | | defptrptr = &IREG(reg); |
| 1296 | | return result; |
| 1297 | | } |
| 1298 | | |
| 1299 | | UINT32 tms3203x_device::mod0f_def(UINT32 op, UINT8 ar, UINT32 *&defptrptr) |
| 1300 | | { |
| 1301 | | int reg = TMR_AR0 + (ar & 7); |
| 1302 | | UINT32 result = IREG(reg); |
| 1303 | | INT32 temp = (result & m_bkmask) - IREG(TMR_IR0); |
| 1304 | | if (temp < 0) |
| 1305 | | temp += IREG(TMR_BK); |
| 1306 | | *defptrptr = (IREG(reg) & ~m_bkmask) | (temp & m_bkmask); |
| 1307 | | defptrptr = &IREG(reg); |
| 1308 | | return result; |
| 1309 | | } |
| 1310 | | |
| 1311 | | |
| 1312 | | // IR1 displacement variants |
| 1313 | | |
| 1314 | | UINT32 tms3203x_device::mod10_def(UINT32 op, UINT8 ar, UINT32 *&defptrptr) |
| 1315 | | { |
| 1316 | | int reg = TMR_AR0 + (ar & 7); |
| 1317 | | return IREG(reg) + IREG(TMR_IR1); |
| 1318 | | } |
| 1319 | | |
| 1320 | | UINT32 tms3203x_device::mod11_def(UINT32 op, UINT8 ar, UINT32 *&defptrptr) |
| 1321 | | { |
| 1322 | | int reg = TMR_AR0 + (ar & 7); |
| 1323 | | return IREG(reg) - IREG(TMR_IR1); |
| 1324 | | } |
| 1325 | | |
| 1326 | | UINT32 tms3203x_device::mod12_def(UINT32 op, UINT8 ar, UINT32 *&defptrptr) |
| 1327 | | { |
| 1328 | | int reg = TMR_AR0 + (ar & 7); |
| 1329 | | UINT32 defval = IREG(reg) + IREG(TMR_IR1); |
| 1330 | | *defptrptr = defval; |
| 1331 | | defptrptr = &IREG(reg); |
| 1332 | | return defval; |
| 1333 | | } |
| 1334 | | |
| 1335 | | UINT32 tms3203x_device::mod13_def(UINT32 op, UINT8 ar, UINT32 *&defptrptr) |
| 1336 | | { |
| 1337 | | int reg = TMR_AR0 + (ar & 7); |
| 1338 | | UINT32 defval = IREG(reg) - IREG(TMR_IR1); |
| 1339 | | *defptrptr = defval; |
| 1340 | | defptrptr = &IREG(reg); |
| 1341 | | return defval; |
| 1342 | | } |
| 1343 | | |
| 1344 | | UINT32 tms3203x_device::mod14_def(UINT32 op, UINT8 ar, UINT32 *&defptrptr) |
| 1345 | | { |
| 1346 | | int reg = TMR_AR0 + (ar & 7); |
| 1347 | | *defptrptr = IREG(reg) + IREG(TMR_IR1); |
| 1348 | | defptrptr = &IREG(reg); |
| 1349 | | return IREG(reg); |
| 1350 | | } |
| 1351 | | |
| 1352 | | UINT32 tms3203x_device::mod15_def(UINT32 op, UINT8 ar, UINT32 *&defptrptr) |
| 1353 | | { |
| 1354 | | int reg = TMR_AR0 + (ar & 7); |
| 1355 | | *defptrptr = IREG(reg) - IREG(TMR_IR1); |
| 1356 | | defptrptr = &IREG(reg); |
| 1357 | | return IREG(reg); |
| 1358 | | } |
| 1359 | | |
| 1360 | | UINT32 tms3203x_device::mod16_def(UINT32 op, UINT8 ar, UINT32 *&defptrptr) |
| 1361 | | { |
| 1362 | | int reg = TMR_AR0 + (ar & 7); |
| 1363 | | UINT32 result = IREG(reg); |
| 1364 | | INT32 temp = (result & m_bkmask) + IREG(TMR_IR1); |
| 1365 | | if (temp >= IREG(TMR_BK)) |
| 1366 | | temp -= IREG(TMR_BK); |
| 1367 | | *defptrptr = (IREG(reg) & ~m_bkmask) | (temp & m_bkmask); |
| 1368 | | defptrptr = &IREG(reg); |
| 1369 | | return result; |
| 1370 | | } |
| 1371 | | |
| 1372 | | UINT32 tms3203x_device::mod17_def(UINT32 op, UINT8 ar, UINT32 *&defptrptr) |
| 1373 | | { |
| 1374 | | int reg = TMR_AR0 + (ar & 7); |
| 1375 | | UINT32 result = IREG(reg); |
| 1376 | | INT32 temp = (result & m_bkmask) - IREG(TMR_IR1); |
| 1377 | | if (temp < 0) |
| 1378 | | temp += IREG(TMR_BK); |
| 1379 | | *defptrptr = (IREG(reg) & ~m_bkmask) | (temp & m_bkmask); |
| 1380 | | defptrptr = &IREG(reg); |
| 1381 | | return result; |
| 1382 | | } |
| 1383 | | |
| 1384 | | UINT32 tms3203x_device::mod18_def(UINT32 op, UINT8 ar, UINT32 *&defptrptr) |
| 1385 | | { |
| 1386 | | int reg = TMR_AR0 + (ar & 7); |
| 1387 | | return IREG(reg); |
| 1388 | | } |
| 1389 | | |
| 1390 | | UINT32 tms3203x_device::mod19_def(UINT32 op, UINT8 ar, UINT32 *&defptrptr) |
| 1391 | | { |
| 1392 | | unimplemented(op); |
| 1393 | | return 0; |
| 1394 | | } |
| 1395 | | |
| 1396 | | UINT32 tms3203x_device::modillegal_def(UINT32 op, UINT8 ar, UINT32 *&defptrptr) |
| 1397 | | { |
| 1398 | | illegal(op); |
| 1399 | | return 0; |
| 1400 | | } |
| 1401 | | |
| 1402 | | |
| 1403 | | /*-----------------------------------------------------*/ |
| 1404 | | |
| 1405 | | #define ABSF(dreg, sreg) \ |
| 1406 | | { \ |
| 1407 | | INT32 man = FREGMAN(sreg); \ |
| 1408 | | CLR_NZVUF(); \ |
| 1409 | | m_r[dreg] = m_r[sreg]; \ |
| 1410 | | if (man < 0) \ |
| 1411 | | { \ |
| 1412 | | m_r[dreg].set_mantissa(~man); \ |
| 1413 | | if (man == (INT32)0x80000000 && FREGEXP(sreg) == 127) \ |
| 1414 | | IREG(TMR_ST) |= VFLAG | LVFLAG; \ |
| 1415 | | } \ |
| 1416 | | OR_NZF(m_r[dreg]); \ |
| 1417 | | } |
| 1418 | | |
| 1419 | | void tms3203x_device::absf_reg(UINT32 op) |
| 1420 | | { |
| 1421 | | int dreg = (op >> 16) & 7; |
| 1422 | | int sreg = op & 7; |
| 1423 | | ABSF(dreg, sreg); |
| 1424 | | } |
| 1425 | | |
| 1426 | | void tms3203x_device::absf_dir(UINT32 op) |
| 1427 | | { |
| 1428 | | UINT32 res = RMEM(DIRECT(op)); |
| 1429 | | int dreg = (op >> 16) & 7; |
| 1430 | | LONG2FP(TMR_TEMP1, res); |
| 1431 | | ABSF(dreg, TMR_TEMP1); |
| 1432 | | } |
| 1433 | | |
| 1434 | | void tms3203x_device::absf_ind(UINT32 op) |
| 1435 | | { |
| 1436 | | UINT32 res = RMEM(INDIRECT_D(op, op >> 8)); |
| 1437 | | int dreg = (op >> 16) & 7; |
| 1438 | | LONG2FP(TMR_TEMP1, res); |
| 1439 | | ABSF(dreg, TMR_TEMP1); |
| 1440 | | } |
| 1441 | | |
| 1442 | | void tms3203x_device::absf_imm(UINT32 op) |
| 1443 | | { |
| 1444 | | int dreg = (op >> 16) & 7; |
| 1445 | | SHORT2FP(TMR_TEMP1, op); |
| 1446 | | ABSF(dreg, TMR_TEMP1); |
| 1447 | | } |
| 1448 | | |
| 1449 | | /*-----------------------------------------------------*/ |
| 1450 | | |
| 1451 | | #define ABSI(dreg, src) \ |
| 1452 | | { \ |
| 1453 | | UINT32 _res = ((INT32)src < 0) ? -src : src; \ |
| 1454 | | if (!OVM() || _res != 0x80000000) \ |
| 1455 | | IREG(dreg) = _res; \ |
| 1456 | | else \ |
| 1457 | | IREG(dreg) = 0x7fffffff; \ |
| 1458 | | if (dreg < 8) \ |
| 1459 | | { \ |
| 1460 | | CLR_NZVUF(); \ |
| 1461 | | OR_NZ(_res); \ |
| 1462 | | if (_res == 0x80000000) \ |
| 1463 | | IREG(TMR_ST) |= VFLAG | LVFLAG; \ |
| 1464 | | } \ |
| 1465 | | else if (dreg >= TMR_BK) \ |
| 1466 | | update_special(dreg); \ |
| 1467 | | } |
| 1468 | | |
| 1469 | | void tms3203x_device::absi_reg(UINT32 op) |
| 1470 | | { |
| 1471 | | UINT32 src = IREG(op & 31); |
| 1472 | | int dreg = (op >> 16) & 31; |
| 1473 | | ABSI(dreg, src); |
| 1474 | | } |
| 1475 | | |
| 1476 | | void tms3203x_device::absi_dir(UINT32 op) |
| 1477 | | { |
| 1478 | | UINT32 src = RMEM(DIRECT(op)); |
| 1479 | | int dreg = (op >> 16) & 31; |
| 1480 | | ABSI(dreg, src); |
| 1481 | | } |
| 1482 | | |
| 1483 | | void tms3203x_device::absi_ind(UINT32 op) |
| 1484 | | { |
| 1485 | | UINT32 src = RMEM(INDIRECT_D(op, op >> 8)); |
| 1486 | | int dreg = (op >> 16) & 31; |
| 1487 | | ABSI(dreg, src); |
| 1488 | | } |
| 1489 | | |
| 1490 | | void tms3203x_device::absi_imm(UINT32 op) |
| 1491 | | { |
| 1492 | | UINT32 src = (INT16)op; |
| 1493 | | int dreg = (op >> 16) & 31; |
| 1494 | | ABSI(dreg, src); |
| 1495 | | } |
| 1496 | | |
| 1497 | | /*-----------------------------------------------------*/ |
| 1498 | | |
| 1499 | | #define ADDC(dreg, src1, src2) \ |
| 1500 | | { \ |
| 1501 | | UINT32 _res = src1 + src2 + (IREG(TMR_ST) & CFLAG); \ |
| 1502 | | if (!OVM() || !OVERFLOW_ADD(src1,src2,_res)) \ |
| 1503 | | IREG(dreg) = _res; \ |
| 1504 | | else \ |
| 1505 | | IREG(dreg) = ((INT32)src1 < 0) ? 0x80000000 : 0x7fffffff; \ |
| 1506 | | if (dreg < 8) \ |
| 1507 | | { \ |
| 1508 | | UINT32 tempc = IREG(TMR_ST) & CFLAG; \ |
| 1509 | | CLR_NZCVUF(); \ |
| 1510 | | OR_C_ADC(src1,src2,tempc); \ |
| 1511 | | OR_V_ADD(src1,src2,_res); \ |
| 1512 | | OR_NZ(_res); \ |
| 1513 | | } \ |
| 1514 | | else if (dreg >= TMR_BK) \ |
| 1515 | | update_special(dreg); \ |
| 1516 | | } |
| 1517 | | |
| 1518 | | void tms3203x_device::addc_reg(UINT32 op) |
| 1519 | | { |
| 1520 | | UINT32 src = IREG(op & 31); |
| 1521 | | int dreg = (op >> 16) & 31; |
| 1522 | | UINT32 dst = IREG(dreg); |
| 1523 | | ADDC(dreg, dst, src); |
| 1524 | | } |
| 1525 | | |
| 1526 | | void tms3203x_device::addc_dir(UINT32 op) |
| 1527 | | { |
| 1528 | | UINT32 src = RMEM(DIRECT(op)); |
| 1529 | | int dreg = (op >> 16) & 31; |
| 1530 | | UINT32 dst = IREG(dreg); |
| 1531 | | ADDC(dreg, dst, src); |
| 1532 | | } |
| 1533 | | |
| 1534 | | void tms3203x_device::addc_ind(UINT32 op) |
| 1535 | | { |
| 1536 | | UINT32 src = RMEM(INDIRECT_D(op, op >> 8)); |
| 1537 | | int dreg = (op >> 16) & 31; |
| 1538 | | UINT32 dst = IREG(dreg); |
| 1539 | | ADDC(dreg, dst, src); |
| 1540 | | } |
| 1541 | | |
| 1542 | | void tms3203x_device::addc_imm(UINT32 op) |
| 1543 | | { |
| 1544 | | UINT32 src = (INT16)op; |
| 1545 | | int dreg = (op >> 16) & 31; |
| 1546 | | UINT32 dst = IREG(dreg); |
| 1547 | | ADDC(dreg, dst, src); |
| 1548 | | } |
| 1549 | | |
| 1550 | | /*-----------------------------------------------------*/ |
| 1551 | | |
| 1552 | | void tms3203x_device::addf_reg(UINT32 op) |
| 1553 | | { |
| 1554 | | int dreg = (op >> 16) & 7; |
| 1555 | | addf(m_r[dreg], m_r[dreg], m_r[op & 7]); |
| 1556 | | } |
| 1557 | | |
| 1558 | | void tms3203x_device::addf_dir(UINT32 op) |
| 1559 | | { |
| 1560 | | UINT32 res = RMEM(DIRECT(op)); |
| 1561 | | int dreg = (op >> 16) & 7; |
| 1562 | | LONG2FP(TMR_TEMP1, res); |
| 1563 | | addf(m_r[dreg], m_r[dreg], m_r[TMR_TEMP1]); |
| 1564 | | } |
| 1565 | | |
| 1566 | | void tms3203x_device::addf_ind(UINT32 op) |
| 1567 | | { |
| 1568 | | UINT32 res = RMEM(INDIRECT_D(op, op >> 8)); |
| 1569 | | int dreg = (op >> 16) & 7; |
| 1570 | | LONG2FP(TMR_TEMP1, res); |
| 1571 | | addf(m_r[dreg], m_r[dreg], m_r[TMR_TEMP1]); |
| 1572 | | } |
| 1573 | | |
| 1574 | | void tms3203x_device::addf_imm(UINT32 op) |
| 1575 | | { |
| 1576 | | int dreg = (op >> 16) & 7; |
| 1577 | | SHORT2FP(TMR_TEMP1, op); |
| 1578 | | addf(m_r[dreg], m_r[dreg], m_r[TMR_TEMP1]); |
| 1579 | | } |
| 1580 | | |
| 1581 | | /*-----------------------------------------------------*/ |
| 1582 | | |
| 1583 | | #define ADDI(dreg, src1, src2) \ |
| 1584 | | { \ |
| 1585 | | UINT32 _res = src1 + src2; \ |
| 1586 | | if (!OVM() || !OVERFLOW_ADD(src1,src2,_res)) \ |
| 1587 | | IREG(dreg) = _res; \ |
| 1588 | | else \ |
| 1589 | | IREG(dreg) = ((INT32)src1 < 0) ? 0x80000000 : 0x7fffffff; \ |
| 1590 | | if (dreg < 8) \ |
| 1591 | | { \ |
| 1592 | | CLR_NZCVUF(); \ |
| 1593 | | OR_C_ADD(src1,src2,_res); \ |
| 1594 | | OR_V_ADD(src1,src2,_res); \ |
| 1595 | | OR_NZ(_res); \ |
| 1596 | | } \ |
| 1597 | | else if (dreg >= TMR_BK) \ |
| 1598 | | update_special(dreg); \ |
| 1599 | | } |
| 1600 | | |
| 1601 | | void tms3203x_device::addi_reg(UINT32 op) |
| 1602 | | { |
| 1603 | | UINT32 src = IREG(op & 31); |
| 1604 | | int dreg = (op >> 16) & 31; |
| 1605 | | UINT32 dst = IREG(dreg); |
| 1606 | | ADDI(dreg, dst, src); |
| 1607 | | } |
| 1608 | | |
| 1609 | | void tms3203x_device::addi_dir(UINT32 op) |
| 1610 | | { |
| 1611 | | UINT32 src = RMEM(DIRECT(op)); |
| 1612 | | int dreg = (op >> 16) & 31; |
| 1613 | | UINT32 dst = IREG(dreg); |
| 1614 | | ADDI(dreg, dst, src); |
| 1615 | | } |
| 1616 | | |
| 1617 | | void tms3203x_device::addi_ind(UINT32 op) |
| 1618 | | { |
| 1619 | | UINT32 src = RMEM(INDIRECT_D(op, op >> 8)); |
| 1620 | | int dreg = (op >> 16) & 31; |
| 1621 | | UINT32 dst = IREG(dreg); |
| 1622 | | ADDI(dreg, dst, src); |
| 1623 | | } |
| 1624 | | |
| 1625 | | void tms3203x_device::addi_imm(UINT32 op) |
| 1626 | | { |
| 1627 | | UINT32 src = (INT16)op; |
| 1628 | | int dreg = (op >> 16) & 31; |
| 1629 | | UINT32 dst = IREG(dreg); |
| 1630 | | ADDI(dreg, dst, src); |
| 1631 | | } |
| 1632 | | |
| 1633 | | /*-----------------------------------------------------*/ |
| 1634 | | |
| 1635 | | #define AND(dreg, src1, src2) \ |
| 1636 | | { \ |
| 1637 | | UINT32 _res = (src1) & (src2); \ |
| 1638 | | IREG(dreg) = _res; \ |
| 1639 | | if (dreg < 8) \ |
| 1640 | | { \ |
| 1641 | | CLR_NZVUF(); \ |
| 1642 | | OR_NZ(_res); \ |
| 1643 | | } \ |
| 1644 | | else if (dreg >= TMR_BK) \ |
| 1645 | | update_special(dreg); \ |
| 1646 | | } |
| 1647 | | |
| 1648 | | void tms3203x_device::and_reg(UINT32 op) |
| 1649 | | { |
| 1650 | | UINT32 src = IREG(op & 31); |
| 1651 | | int dreg = (op >> 16) & 31; |
| 1652 | | UINT32 dst = IREG(dreg); |
| 1653 | | AND(dreg, dst, src); |
| 1654 | | } |
| 1655 | | |
| 1656 | | void tms3203x_device::and_dir(UINT32 op) |
| 1657 | | { |
| 1658 | | UINT32 src = RMEM(DIRECT(op)); |
| 1659 | | int dreg = (op >> 16) & 31; |
| 1660 | | UINT32 dst = IREG(dreg); |
| 1661 | | AND(dreg, dst, src); |
| 1662 | | } |
| 1663 | | |
| 1664 | | void tms3203x_device::and_ind(UINT32 op) |
| 1665 | | { |
| 1666 | | UINT32 src = RMEM(INDIRECT_D(op, op >> 8)); |
| 1667 | | int dreg = (op >> 16) & 31; |
| 1668 | | UINT32 dst = IREG(dreg); |
| 1669 | | AND(dreg, dst, src); |
| 1670 | | } |
| 1671 | | |
| 1672 | | void tms3203x_device::and_imm(UINT32 op) |
| 1673 | | { |
| 1674 | | UINT32 src = (UINT16)op; |
| 1675 | | int dreg = (op >> 16) & 31; |
| 1676 | | UINT32 dst = IREG(dreg); |
| 1677 | | AND(dreg, dst, src); |
| 1678 | | } |
| 1679 | | |
| 1680 | | /*-----------------------------------------------------*/ |
| 1681 | | |
| 1682 | | #define ANDN(dreg, src1, src2) \ |
| 1683 | | { \ |
| 1684 | | UINT32 _res = (src1) & ~(src2); \ |
| 1685 | | IREG(dreg) = _res; \ |
| 1686 | | if (dreg < 8) \ |
| 1687 | | { \ |
| 1688 | | CLR_NZVUF(); \ |
| 1689 | | OR_NZ(_res); \ |
| 1690 | | } \ |
| 1691 | | else if (dreg >= TMR_BK) \ |
| 1692 | | update_special(dreg); \ |
| 1693 | | } |
| 1694 | | |
| 1695 | | void tms3203x_device::andn_reg(UINT32 op) |
| 1696 | | { |
| 1697 | | UINT32 src = IREG(op & 31); |
| 1698 | | int dreg = (op >> 16) & 31; |
| 1699 | | UINT32 dst = IREG(dreg); |
| 1700 | | ANDN(dreg, dst, src); |
| 1701 | | } |
| 1702 | | |
| 1703 | | void tms3203x_device::andn_dir(UINT32 op) |
| 1704 | | { |
| 1705 | | UINT32 src = RMEM(DIRECT(op)); |
| 1706 | | int dreg = (op >> 16) & 31; |
| 1707 | | UINT32 dst = IREG(dreg); |
| 1708 | | ANDN(dreg, dst, src); |
| 1709 | | } |
| 1710 | | |
| 1711 | | void tms3203x_device::andn_ind(UINT32 op) |
| 1712 | | { |
| 1713 | | UINT32 src = RMEM(INDIRECT_D(op, op >> 8)); |
| 1714 | | int dreg = (op >> 16) & 31; |
| 1715 | | UINT32 dst = IREG(dreg); |
| 1716 | | ANDN(dreg, dst, src); |
| 1717 | | } |
| 1718 | | |
| 1719 | | void tms3203x_device::andn_imm(UINT32 op) |
| 1720 | | { |
| 1721 | | UINT32 src = (UINT16)op; |
| 1722 | | int dreg = (op >> 16) & 31; |
| 1723 | | UINT32 dst = IREG(dreg); |
| 1724 | | ANDN(dreg, dst, src); |
| 1725 | | } |
| 1726 | | |
| 1727 | | /*-----------------------------------------------------*/ |
| 1728 | | |
| 1729 | | #define ASH(dreg, src, count) \ |
| 1730 | | { \ |
| 1731 | | UINT32 _res; \ |
| 1732 | | INT32 _count = (INT16)(count << 9) >> 9; /* 7 LSBs */ \ |
| 1733 | | if (_count < 0) \ |
| 1734 | | { \ |
| 1735 | | if (_count >= -31) \ |
| 1736 | | _res = (INT32)src >> -_count; \ |
| 1737 | | else \ |
| 1738 | | _res = (INT32)src >> 31; \ |
| 1739 | | } \ |
| 1740 | | else \ |
| 1741 | | { \ |
| 1742 | | if (_count <= 31) \ |
| 1743 | | _res = (INT32)src << _count; \ |
| 1744 | | else \ |
| 1745 | | _res = 0; \ |
| 1746 | | } \ |
| 1747 | | IREG(dreg) = _res; \ |
| 1748 | | if (dreg < 8) \ |
| 1749 | | { \ |
| 1750 | | CLR_NZCVUF(); \ |
| 1751 | | OR_NZ(_res); \ |
| 1752 | | if (_count < 0) \ |
| 1753 | | { \ |
| 1754 | | if (_count >= -32) \ |
| 1755 | | OR_C(((INT32)src >> (-_count - 1)) & 1); \ |
| 1756 | | else \ |
| 1757 | | OR_C(((INT32)src >> 31) & 1); \ |
| 1758 | | } \ |
| 1759 | | else if (_count > 0) \ |
| 1760 | | { \ |
| 1761 | | if (_count <= 32) \ |
| 1762 | | OR_C(((UINT32)src << (_count - 1)) >> 31); \ |
| 1763 | | } \ |
| 1764 | | } \ |
| 1765 | | else if (dreg >= TMR_BK) \ |
| 1766 | | update_special(dreg); \ |
| 1767 | | } |
| 1768 | | |
| 1769 | | void tms3203x_device::ash_reg(UINT32 op) |
| 1770 | | { |
| 1771 | | int dreg = (op >> 16) & 31; |
| 1772 | | int count = IREG(op & 31); |
| 1773 | | UINT32 src = IREG(dreg); |
| 1774 | | ASH(dreg, src, count); |
| 1775 | | } |
| 1776 | | |
| 1777 | | void tms3203x_device::ash_dir(UINT32 op) |
| 1778 | | { |
| 1779 | | int dreg = (op >> 16) & 31; |
| 1780 | | int count = RMEM(DIRECT(op)); |
| 1781 | | UINT32 src = IREG(dreg); |
| 1782 | | ASH(dreg, src, count); |
| 1783 | | } |
| 1784 | | |
| 1785 | | void tms3203x_device::ash_ind(UINT32 op) |
| 1786 | | { |
| 1787 | | int dreg = (op >> 16) & 31; |
| 1788 | | int count = RMEM(INDIRECT_D(op, op >> 8)); |
| 1789 | | UINT32 src = IREG(dreg); |
| 1790 | | ASH(dreg, src, count); |
| 1791 | | } |
| 1792 | | |
| 1793 | | void tms3203x_device::ash_imm(UINT32 op) |
| 1794 | | { |
| 1795 | | int dreg = (op >> 16) & 31; |
| 1796 | | int count = op; |
| 1797 | | UINT32 src = IREG(dreg); |
| 1798 | | ASH(dreg, src, count); |
| 1799 | | } |
| 1800 | | |
| 1801 | | /*-----------------------------------------------------*/ |
| 1802 | | |
| 1803 | | void tms3203x_device::cmpf_reg(UINT32 op) |
| 1804 | | { |
| 1805 | | int dreg = (op >> 16) & 7; |
| 1806 | | subf(m_r[TMR_TEMP2], m_r[dreg], m_r[op & 7]); |
| 1807 | | } |
| 1808 | | |
| 1809 | | void tms3203x_device::cmpf_dir(UINT32 op) |
| 1810 | | { |
| 1811 | | UINT32 res = RMEM(DIRECT(op)); |
| 1812 | | int dreg = (op >> 16) & 7; |
| 1813 | | LONG2FP(TMR_TEMP1, res); |
| 1814 | | subf(m_r[TMR_TEMP2], m_r[dreg], m_r[TMR_TEMP1]); |
| 1815 | | } |
| 1816 | | |
| 1817 | | void tms3203x_device::cmpf_ind(UINT32 op) |
| 1818 | | { |
| 1819 | | UINT32 res = RMEM(INDIRECT_D(op, op >> 8)); |
| 1820 | | int dreg = (op >> 16) & 7; |
| 1821 | | LONG2FP(TMR_TEMP1, res); |
| 1822 | | subf(m_r[TMR_TEMP2], m_r[dreg], m_r[TMR_TEMP1]); |
| 1823 | | } |
| 1824 | | |
| 1825 | | void tms3203x_device::cmpf_imm(UINT32 op) |
| 1826 | | { |
| 1827 | | int dreg = (op >> 16) & 7; |
| 1828 | | SHORT2FP(TMR_TEMP1, op); |
| 1829 | | subf(m_r[TMR_TEMP2], m_r[dreg], m_r[TMR_TEMP1]); |
| 1830 | | } |
| 1831 | | |
| 1832 | | /*-----------------------------------------------------*/ |
| 1833 | | |
| 1834 | | #define CMPI(src1, src2) \ |
| 1835 | | { \ |
| 1836 | | UINT32 _res = src1 - src2; \ |
| 1837 | | CLR_NZCVUF(); \ |
| 1838 | | OR_C_SUB(src1,src2,_res); \ |
| 1839 | | OR_V_SUB(src1,src2,_res); \ |
| 1840 | | OR_NZ(_res); \ |
| 1841 | | } |
| 1842 | | |
| 1843 | | void tms3203x_device::cmpi_reg(UINT32 op) |
| 1844 | | { |
| 1845 | | UINT32 src = IREG(op & 31); |
| 1846 | | UINT32 dst = IREG((op >> 16) & 31); |
| 1847 | | CMPI(dst, src); |
| 1848 | | } |
| 1849 | | |
| 1850 | | void tms3203x_device::cmpi_dir(UINT32 op) |
| 1851 | | { |
| 1852 | | UINT32 src = RMEM(DIRECT(op)); |
| 1853 | | UINT32 dst = IREG((op >> 16) & 31); |
| 1854 | | CMPI(dst, src); |
| 1855 | | } |
| 1856 | | |
| 1857 | | void tms3203x_device::cmpi_ind(UINT32 op) |
| 1858 | | { |
| 1859 | | UINT32 src = RMEM(INDIRECT_D(op, op >> 8)); |
| 1860 | | UINT32 dst = IREG((op >> 16) & 31); |
| 1861 | | CMPI(dst, src); |
| 1862 | | } |
| 1863 | | |
| 1864 | | void tms3203x_device::cmpi_imm(UINT32 op) |
| 1865 | | { |
| 1866 | | UINT32 src = (INT16)op; |
| 1867 | | UINT32 dst = IREG((op >> 16) & 31); |
| 1868 | | CMPI(dst, src); |
| 1869 | | } |
| 1870 | | |
| 1871 | | /*-----------------------------------------------------*/ |
| 1872 | | |
| 1873 | | void tms3203x_device::fix_reg(UINT32 op) |
| 1874 | | { |
| 1875 | | int dreg = (op >> 16) & 31; |
| 1876 | | m_r[TMR_TEMP1] = m_r[op & 7]; |
| 1877 | | float2int(m_r[TMR_TEMP1], dreg < 8); |
| 1878 | | m_r[dreg].set_mantissa(m_r[TMR_TEMP1].mantissa()); |
| 1879 | | } |
| 1880 | | |
| 1881 | | void tms3203x_device::fix_dir(UINT32 op) |
| 1882 | | { |
| 1883 | | UINT32 res = RMEM(DIRECT(op)); |
| 1884 | | int dreg = (op >> 16) & 31; |
| 1885 | | LONG2FP(TMR_TEMP1, res); |
| 1886 | | float2int(m_r[TMR_TEMP1], dreg < 8); |
| 1887 | | m_r[dreg].set_mantissa(m_r[TMR_TEMP1].mantissa()); |
| 1888 | | } |
| 1889 | | |
| 1890 | | void tms3203x_device::fix_ind(UINT32 op) |
| 1891 | | { |
| 1892 | | UINT32 res = RMEM(INDIRECT_D(op, op >> 8)); |
| 1893 | | int dreg = (op >> 16) & 31; |
| 1894 | | LONG2FP(TMR_TEMP1, res); |
| 1895 | | float2int(m_r[TMR_TEMP1], dreg < 8); |
| 1896 | | m_r[dreg].set_mantissa(m_r[TMR_TEMP1].mantissa()); |
| 1897 | | } |
| 1898 | | |
| 1899 | | void tms3203x_device::fix_imm(UINT32 op) |
| 1900 | | { |
| 1901 | | int dreg = (op >> 16) & 31; |
| 1902 | | SHORT2FP(TMR_TEMP1, op); |
| 1903 | | float2int(m_r[TMR_TEMP1], dreg < 8); |
| 1904 | | m_r[dreg].set_mantissa(m_r[TMR_TEMP1].mantissa()); |
| 1905 | | } |
| 1906 | | |
| 1907 | | /*-----------------------------------------------------*/ |
| 1908 | | |
| 1909 | | #define FLOAT(dreg, src) \ |
| 1910 | | { \ |
| 1911 | | IREG(dreg) = src; \ |
| 1912 | | int2float(m_r[dreg]); \ |
| 1913 | | } |
| 1914 | | |
| 1915 | | void tms3203x_device::float_reg(UINT32 op) |
| 1916 | | { |
| 1917 | | UINT32 src = IREG(op & 31); |
| 1918 | | int dreg = (op >> 16) & 7; |
| 1919 | | FLOAT(dreg, src); |
| 1920 | | } |
| 1921 | | |
| 1922 | | void tms3203x_device::float_dir(UINT32 op) |
| 1923 | | { |
| 1924 | | UINT32 src = RMEM(DIRECT(op)); |
| 1925 | | int dreg = (op >> 16) & 7; |
| 1926 | | FLOAT(dreg, src); |
| 1927 | | } |
| 1928 | | |
| 1929 | | void tms3203x_device::float_ind(UINT32 op) |
| 1930 | | { |
| 1931 | | UINT32 src = RMEM(INDIRECT_D(op, op >> 8)); |
| 1932 | | int dreg = (op >> 16) & 7; |
| 1933 | | FLOAT(dreg, src); |
| 1934 | | } |
| 1935 | | |
| 1936 | | void tms3203x_device::float_imm(UINT32 op) |
| 1937 | | { |
| 1938 | | UINT32 src = (INT16)op; |
| 1939 | | int dreg = (op >> 16) & 7; |
| 1940 | | FLOAT(dreg, src); |
| 1941 | | } |
| 1942 | | |
| 1943 | | /*-----------------------------------------------------*/ |
| 1944 | | |
| 1945 | | void tms3203x_device::idle(UINT32 op) |
| 1946 | | { |
| 1947 | | m_is_idling = true; |
| 1948 | | IREG(TMR_ST) |= GIEFLAG; |
| 1949 | | check_irqs(); |
| 1950 | | if (m_is_idling) |
| 1951 | | m_icount = 0; |
| 1952 | | } |
| 1953 | | |
| 1954 | | /*-----------------------------------------------------*/ |
| 1955 | | |
| 1956 | | void tms3203x_device::lde_reg(UINT32 op) |
| 1957 | | { |
| 1958 | | int dreg = (op >> 16) & 7; |
| 1959 | | m_r[dreg].set_exponent(m_r[op & 7].exponent()); |
| 1960 | | if (m_r[dreg].exponent() == -128) |
| 1961 | | m_r[dreg].set_mantissa(0); |
| 1962 | | } |
| 1963 | | |
| 1964 | | void tms3203x_device::lde_dir(UINT32 op) |
| 1965 | | { |
| 1966 | | UINT32 res = RMEM(DIRECT(op)); |
| 1967 | | int dreg = (op >> 16) & 7; |
| 1968 | | LONG2FP(TMR_TEMP1, res); |
| 1969 | | m_r[dreg].set_exponent(m_r[TMR_TEMP1].exponent()); |
| 1970 | | if (m_r[dreg].exponent() == -128) |
| 1971 | | m_r[dreg].set_mantissa(0); |
| 1972 | | } |
| 1973 | | |
| 1974 | | void tms3203x_device::lde_ind(UINT32 op) |
| 1975 | | { |
| 1976 | | UINT32 res = RMEM(INDIRECT_D(op, op >> 8)); |
| 1977 | | int dreg = (op >> 16) & 7; |
| 1978 | | LONG2FP(TMR_TEMP1, res); |
| 1979 | | m_r[dreg].set_exponent(m_r[TMR_TEMP1].exponent()); |
| 1980 | | if (m_r[dreg].exponent() == -128) |
| 1981 | | m_r[dreg].set_mantissa(0); |
| 1982 | | } |
| 1983 | | |
| 1984 | | void tms3203x_device::lde_imm(UINT32 op) |
| 1985 | | { |
| 1986 | | int dreg = (op >> 16) & 7; |
| 1987 | | SHORT2FP(TMR_TEMP1, op); |
| 1988 | | m_r[dreg].set_exponent(m_r[TMR_TEMP1].exponent()); |
| 1989 | | if (m_r[dreg].exponent() == -128) |
| 1990 | | m_r[dreg].set_mantissa(0); |
| 1991 | | } |
| 1992 | | |
| 1993 | | /*-----------------------------------------------------*/ |
| 1994 | | |
| 1995 | | void tms3203x_device::ldf_reg(UINT32 op) |
| 1996 | | { |
| 1997 | | int dreg = (op >> 16) & 7; |
| 1998 | | m_r[dreg] = m_r[op & 7]; |
| 1999 | | CLR_NZVUF(); |
| 2000 | | OR_NZF(m_r[dreg]); |
| 2001 | | } |
| 2002 | | |
| 2003 | | void tms3203x_device::ldf_dir(UINT32 op) |
| 2004 | | { |
| 2005 | | UINT32 res = RMEM(DIRECT(op)); |
| 2006 | | int dreg = (op >> 16) & 7; |
| 2007 | | LONG2FP(dreg, res); |
| 2008 | | CLR_NZVUF(); |
| 2009 | | OR_NZF(m_r[dreg]); |
| 2010 | | } |
| 2011 | | |
| 2012 | | void tms3203x_device::ldf_ind(UINT32 op) |
| 2013 | | { |
| 2014 | | UINT32 res = RMEM(INDIRECT_D(op, op >> 8)); |
| 2015 | | int dreg = (op >> 16) & 7; |
| 2016 | | LONG2FP(dreg, res); |
| 2017 | | CLR_NZVUF(); |
| 2018 | | OR_NZF(m_r[dreg]); |
| 2019 | | } |
| 2020 | | |
| 2021 | | void tms3203x_device::ldf_imm(UINT32 op) |
| 2022 | | { |
| 2023 | | int dreg = (op >> 16) & 7; |
| 2024 | | SHORT2FP(dreg, op); |
| 2025 | | CLR_NZVUF(); |
| 2026 | | OR_NZF(m_r[dreg]); |
| 2027 | | } |
| 2028 | | |
| 2029 | | /*-----------------------------------------------------*/ |
| 2030 | | |
| 2031 | | void tms3203x_device::ldfi_dir(UINT32 op) { unimplemented(op); } |
| 2032 | | void tms3203x_device::ldfi_ind(UINT32 op) { unimplemented(op); } |
| 2033 | | |
| 2034 | | /*-----------------------------------------------------*/ |
| 2035 | | |
| 2036 | | #define LDI(dreg, src) \ |
| 2037 | | { \ |
| 2038 | | IREG(dreg) = src; \ |
| 2039 | | if (dreg < 8) \ |
| 2040 | | { \ |
| 2041 | | CLR_NZVUF(); \ |
| 2042 | | OR_NZ(src); \ |
| 2043 | | } \ |
| 2044 | | else if (dreg >= TMR_BK) \ |
| 2045 | | update_special(dreg); \ |
| 2046 | | } |
| 2047 | | |
| 2048 | | void tms3203x_device::ldi_reg(UINT32 op) |
| 2049 | | { |
| 2050 | | UINT32 src = IREG(op & 31); |
| 2051 | | int dreg = (op >> 16) & 31; |
| 2052 | | LDI(dreg, src); |
| 2053 | | } |
| 2054 | | |
| 2055 | | void tms3203x_device::ldi_dir(UINT32 op) |
| 2056 | | { |
| 2057 | | UINT32 src = RMEM(DIRECT(op)); |
| 2058 | | int dreg = (op >> 16) & 31; |
| 2059 | | LDI(dreg, src); |
| 2060 | | } |
| 2061 | | |
| 2062 | | void tms3203x_device::ldi_ind(UINT32 op) |
| 2063 | | { |
| 2064 | | UINT32 src = RMEM(INDIRECT_D(op, op >> 8)); |
| 2065 | | int dreg = (op >> 16) & 31; |
| 2066 | | LDI(dreg, src); |
| 2067 | | } |
| 2068 | | |
| 2069 | | void tms3203x_device::ldi_imm(UINT32 op) |
| 2070 | | { |
| 2071 | | UINT32 src = (INT16)op; |
| 2072 | | int dreg = (op >> 16) & 31; |
| 2073 | | LDI(dreg, src); |
| 2074 | | } |
| 2075 | | |
| 2076 | | /*-----------------------------------------------------*/ |
| 2077 | | |
| 2078 | | void tms3203x_device::ldii_dir(UINT32 op) { unimplemented(op); } |
| 2079 | | void tms3203x_device::ldii_ind(UINT32 op) { unimplemented(op); } |
| 2080 | | |
| 2081 | | /*-----------------------------------------------------*/ |
| 2082 | | |
| 2083 | | void tms3203x_device::ldm_reg(UINT32 op) |
| 2084 | | { |
| 2085 | | int dreg = (op >> 16) & 7; |
| 2086 | | m_r[dreg].set_mantissa(m_r[op & 7].mantissa()); |
| 2087 | | } |
| 2088 | | |
| 2089 | | void tms3203x_device::ldm_dir(UINT32 op) |
| 2090 | | { |
| 2091 | | UINT32 res = RMEM(DIRECT(op)); |
| 2092 | | int dreg = (op >> 16) & 7; |
| 2093 | | m_r[dreg].set_mantissa(res); |
| 2094 | | } |
| 2095 | | |
| 2096 | | void tms3203x_device::ldm_ind(UINT32 op) |
| 2097 | | { |
| 2098 | | UINT32 res = RMEM(INDIRECT_D(op, op >> 8)); |
| 2099 | | int dreg = (op >> 16) & 7; |
| 2100 | | m_r[dreg].set_mantissa(res); |
| 2101 | | } |
| 2102 | | |
| 2103 | | void tms3203x_device::ldm_imm(UINT32 op) |
| 2104 | | { |
| 2105 | | int dreg = (op >> 16) & 7; |
| 2106 | | SHORT2FP(TMR_TEMP1, op); |
| 2107 | | m_r[dreg].set_mantissa(m_r[TMR_TEMP1].mantissa()); |
| 2108 | | } |
| 2109 | | |
| 2110 | | /*-----------------------------------------------------*/ |
| 2111 | | |
| 2112 | | #define LSH(dreg, src, count) \ |
| 2113 | | { \ |
| 2114 | | UINT32 _res; \ |
| 2115 | | INT32 _count = (INT16)(count << 9) >> 9; /* 7 LSBs */ \ |
| 2116 | | if (_count < 0) \ |
| 2117 | | { \ |
| 2118 | | if (_count >= -31) \ |
| 2119 | | _res = (UINT32)src >> -_count; \ |
| 2120 | | else \ |
| 2121 | | _res = 0; \ |
| 2122 | | } \ |
| 2123 | | else \ |
| 2124 | | { \ |
| 2125 | | if (_count <= 31) \ |
| 2126 | | _res = (UINT32)src << _count; \ |
| 2127 | | else \ |
| 2128 | | _res = 0; \ |
| 2129 | | } \ |
| 2130 | | IREG(dreg) = _res; \ |
| 2131 | | if (dreg < 8) \ |
| 2132 | | { \ |
| 2133 | | CLR_NZCVUF(); \ |
| 2134 | | OR_NZ(_res); \ |
| 2135 | | if (_count < 0) \ |
| 2136 | | { \ |
| 2137 | | if (_count >= -32) \ |
| 2138 | | OR_C(((UINT32)src >> (-_count - 1)) & 1); \ |
| 2139 | | } \ |
| 2140 | | else if (_count > 0) \ |
| 2141 | | { \ |
| 2142 | | if (_count <= 32) \ |
| 2143 | | OR_C(((UINT32)src << (_count - 1)) >> 31); \ |
| 2144 | | } \ |
| 2145 | | } \ |
| 2146 | | else if (dreg >= TMR_BK) \ |
| 2147 | | update_special(dreg); \ |
| 2148 | | } |
| 2149 | | |
| 2150 | | void tms3203x_device::lsh_reg(UINT32 op) |
| 2151 | | { |
| 2152 | | int dreg = (op >> 16) & 31; |
| 2153 | | int count = IREG(op & 31); |
| 2154 | | UINT32 src = IREG(dreg); |
| 2155 | | LSH(dreg, src, count); |
| 2156 | | } |
| 2157 | | |
| 2158 | | void tms3203x_device::lsh_dir(UINT32 op) |
| 2159 | | { |
| 2160 | | int dreg = (op >> 16) & 31; |
| 2161 | | int count = RMEM(DIRECT(op)); |
| 2162 | | UINT32 src = IREG(dreg); |
| 2163 | | LSH(dreg, src, count); |
| 2164 | | } |
| 2165 | | |
| 2166 | | void tms3203x_device::lsh_ind(UINT32 op) |
| 2167 | | { |
| 2168 | | int dreg = (op >> 16) & 31; |
| 2169 | | int count = RMEM(INDIRECT_D(op, op >> 8)); |
| 2170 | | UINT32 src = IREG(dreg); |
| 2171 | | LSH(dreg, src, count); |
| 2172 | | } |
| 2173 | | |
| 2174 | | void tms3203x_device::lsh_imm(UINT32 op) |
| 2175 | | { |
| 2176 | | int dreg = (op >> 16) & 31; |
| 2177 | | int count = op; |
| 2178 | | UINT32 src = IREG(dreg); |
| 2179 | | LSH(dreg, src, count); |
| 2180 | | } |
| 2181 | | |
| 2182 | | /*-----------------------------------------------------*/ |
| 2183 | | |
| 2184 | | void tms3203x_device::mpyf_reg(UINT32 op) |
| 2185 | | { |
| 2186 | | int dreg = (op >> 16) & 31; |
| 2187 | | mpyf(m_r[dreg], m_r[dreg], m_r[op & 31]); |
| 2188 | | } |
| 2189 | | |
| 2190 | | void tms3203x_device::mpyf_dir(UINT32 op) |
| 2191 | | { |
| 2192 | | UINT32 res = RMEM(DIRECT(op)); |
| 2193 | | int dreg = (op >> 16) & 31; |
| 2194 | | LONG2FP(TMR_TEMP1, res); |
| 2195 | | mpyf(m_r[dreg], m_r[dreg], m_r[TMR_TEMP1]); |
| 2196 | | } |
| 2197 | | |
| 2198 | | void tms3203x_device::mpyf_ind(UINT32 op) |
| 2199 | | { |
| 2200 | | UINT32 res = RMEM(INDIRECT_D(op, op >> 8)); |
| 2201 | | int dreg = (op >> 16) & 31; |
| 2202 | | LONG2FP(TMR_TEMP1, res); |
| 2203 | | mpyf(m_r[dreg], m_r[dreg], m_r[TMR_TEMP1]); |
| 2204 | | } |
| 2205 | | |
| 2206 | | void tms3203x_device::mpyf_imm(UINT32 op) |
| 2207 | | { |
| 2208 | | int dreg = (op >> 16) & 31; |
| 2209 | | SHORT2FP(TMR_TEMP1, op); |
| 2210 | | mpyf(m_r[dreg], m_r[dreg], m_r[TMR_TEMP1]); |
| 2211 | | } |
| 2212 | | |
| 2213 | | /*-----------------------------------------------------*/ |
| 2214 | | |
| 2215 | | #define MPYI(dreg, src1, src2) \ |
| 2216 | | { \ |
| 2217 | | INT64 _res = (INT64)((INT32)(src1 << 8) >> 8) * (INT64)((INT32)(src2 << 8) >> 8);\ |
| 2218 | | if (!OVM() || (_res >= -(INT64)0x80000000 && _res <= (INT64)0x7fffffff)) \ |
| 2219 | | IREG(dreg) = _res; \ |
| 2220 | | else \ |
| 2221 | | IREG(dreg) = (_res < 0) ? 0x80000000 : 0x7fffffff; \ |
| 2222 | | if (dreg < 8) \ |
| 2223 | | { \ |
| 2224 | | CLR_NZVUF(); \ |
| 2225 | | OR_NZ((UINT32)_res); \ |
| 2226 | | if (_res < -(INT64)0x80000000 || _res > (INT64)0x7fffffff) \ |
| 2227 | | IREG(TMR_ST) |= VFLAG | LVFLAG; \ |
| 2228 | | } \ |
| 2229 | | else if (dreg >= TMR_BK) \ |
| 2230 | | update_special(dreg); \ |
| 2231 | | } |
| 2232 | | |
| 2233 | | void tms3203x_device::mpyi_reg(UINT32 op) |
| 2234 | | { |
| 2235 | | UINT32 src = IREG(op & 31); |
| 2236 | | int dreg = (op >> 16) & 31; |
| 2237 | | UINT32 dst = IREG(dreg); |
| 2238 | | MPYI(dreg, dst, src); |
| 2239 | | } |
| 2240 | | |
| 2241 | | void tms3203x_device::mpyi_dir(UINT32 op) |
| 2242 | | { |
| 2243 | | UINT32 src = RMEM(DIRECT(op)); |
| 2244 | | int dreg = (op >> 16) & 31; |
| 2245 | | UINT32 dst = IREG(dreg); |
| 2246 | | MPYI(dreg, dst, src); |
| 2247 | | } |
| 2248 | | |
| 2249 | | void tms3203x_device::mpyi_ind(UINT32 op) |
| 2250 | | { |
| 2251 | | UINT32 src = RMEM(INDIRECT_D(op, op >> 8)); |
| 2252 | | int dreg = (op >> 16) & 31; |
| 2253 | | UINT32 dst = IREG(dreg); |
| 2254 | | MPYI(dreg, dst, src); |
| 2255 | | } |
| 2256 | | |
| 2257 | | void tms3203x_device::mpyi_imm(UINT32 op) |
| 2258 | | { |
| 2259 | | UINT32 src = (INT16)op; |
| 2260 | | int dreg = (op >> 16) & 31; |
| 2261 | | UINT32 dst = IREG(dreg); |
| 2262 | | MPYI(dreg, dst, src); |
| 2263 | | } |
| 2264 | | |
| 2265 | | /*-----------------------------------------------------*/ |
| 2266 | | |
| 2267 | | #define NEGB(dreg, src) \ |
| 2268 | | { \ |
| 2269 | | UINT32 _res = 0 - src - (IREG(TMR_ST) & CFLAG); \ |
| 2270 | | if (!OVM() || !OVERFLOW_SUB(0,src,_res)) \ |
| 2271 | | IREG(dreg) = _res; \ |
| 2272 | | else \ |
| 2273 | | IREG(dreg) = ((INT32)src < 0) ? 0x80000000 : 0x7fffffff; \ |
| 2274 | | if (dreg < 8) \ |
| 2275 | | { \ |
| 2276 | | UINT32 tempc = IREG(TMR_ST) & CFLAG; \ |
| 2277 | | CLR_NZCVUF(); \ |
| 2278 | | OR_C_SBB(0,src,tempc); \ |
| 2279 | | OR_V_SUB(0,src,_res); \ |
| 2280 | | OR_NZ(_res); \ |
| 2281 | | } \ |
| 2282 | | else if (dreg >= TMR_BK) \ |
| 2283 | | update_special(dreg); \ |
| 2284 | | } |
| 2285 | | |
| 2286 | | void tms3203x_device::negb_reg(UINT32 op) |
| 2287 | | { |
| 2288 | | UINT32 src = IREG(op & 31); |
| 2289 | | int dreg = (op >> 16) & 31; |
| 2290 | | NEGB(dreg, src); |
| 2291 | | } |
| 2292 | | |
| 2293 | | void tms3203x_device::negb_dir(UINT32 op) |
| 2294 | | { |
| 2295 | | UINT32 src = RMEM(DIRECT(op)); |
| 2296 | | int dreg = (op >> 16) & 31; |
| 2297 | | NEGB(dreg, src); |
| 2298 | | } |
| 2299 | | |
| 2300 | | void tms3203x_device::negb_ind(UINT32 op) |
| 2301 | | { |
| 2302 | | UINT32 src = RMEM(INDIRECT_D(op, op >> 8)); |
| 2303 | | int dreg = (op >> 16) & 31; |
| 2304 | | NEGB(dreg, src); |
| 2305 | | } |
| 2306 | | |
| 2307 | | void tms3203x_device::negb_imm(UINT32 op) |
| 2308 | | { |
| 2309 | | UINT32 src = (INT16)op; |
| 2310 | | int dreg = (op >> 16) & 31; |
| 2311 | | NEGB(dreg, src); |
| 2312 | | } |
| 2313 | | |
| 2314 | | /*-----------------------------------------------------*/ |
| 2315 | | |
| 2316 | | void tms3203x_device::negf_reg(UINT32 op) |
| 2317 | | { |
| 2318 | | int dreg = (op >> 16) & 7; |
| 2319 | | negf(m_r[dreg], m_r[op & 7]); |
| 2320 | | } |
| 2321 | | |
| 2322 | | void tms3203x_device::negf_dir(UINT32 op) |
| 2323 | | { |
| 2324 | | UINT32 res = RMEM(DIRECT(op)); |
| 2325 | | int dreg = (op >> 16) & 7; |
| 2326 | | LONG2FP(TMR_TEMP1, res); |
| 2327 | | negf(m_r[dreg], m_r[TMR_TEMP1]); |
| 2328 | | } |
| 2329 | | |
| 2330 | | void tms3203x_device::negf_ind(UINT32 op) |
| 2331 | | { |
| 2332 | | UINT32 res = RMEM(INDIRECT_D(op, op >> 8)); |
| 2333 | | int dreg = (op >> 16) & 7; |
| 2334 | | LONG2FP(TMR_TEMP1, res); |
| 2335 | | negf(m_r[dreg], m_r[TMR_TEMP1]); |
| 2336 | | } |
| 2337 | | |
| 2338 | | void tms3203x_device::negf_imm(UINT32 op) |
| 2339 | | { |
| 2340 | | int dreg = (op >> 16) & 7; |
| 2341 | | SHORT2FP(TMR_TEMP1, op); |
| 2342 | | negf(m_r[dreg], m_r[TMR_TEMP1]); |
| 2343 | | } |
| 2344 | | |
| 2345 | | /*-----------------------------------------------------*/ |
| 2346 | | |
| 2347 | | #define NEGI(dreg, src) \ |
| 2348 | | { \ |
| 2349 | | UINT32 _res = 0 - src; \ |
| 2350 | | if (!OVM() || !OVERFLOW_SUB(0,src,_res)) \ |
| 2351 | | IREG(dreg) = _res; \ |
| 2352 | | else \ |
| 2353 | | IREG(dreg) = ((INT32)src < 0) ? 0x80000000 : 0x7fffffff; \ |
| 2354 | | if (dreg < 8) \ |
| 2355 | | { \ |
| 2356 | | CLR_NZCVUF(); \ |
| 2357 | | OR_C_SUB(0,src,_res); \ |
| 2358 | | OR_V_SUB(0,src,_res); \ |
| 2359 | | OR_NZ(_res); \ |
| 2360 | | } \ |
| 2361 | | else if (dreg >= TMR_BK) \ |
| 2362 | | update_special(dreg); \ |
| 2363 | | } |
| 2364 | | |
| 2365 | | void tms3203x_device::negi_reg(UINT32 op) |
| 2366 | | { |
| 2367 | | UINT32 src = IREG(op & 31); |
| 2368 | | int dreg = (op >> 16) & 31; |
| 2369 | | NEGI(dreg, src); |
| 2370 | | } |
| 2371 | | |
| 2372 | | void tms3203x_device::negi_dir(UINT32 op) |
| 2373 | | { |
| 2374 | | UINT32 src = RMEM(DIRECT(op)); |
| 2375 | | int dreg = (op >> 16) & 31; |
| 2376 | | NEGI(dreg, src); |
| 2377 | | } |
| 2378 | | |
| 2379 | | void tms3203x_device::negi_ind(UINT32 op) |
| 2380 | | { |
| 2381 | | UINT32 src = RMEM(INDIRECT_D(op, op >> 8)); |
| 2382 | | int dreg = (op >> 16) & 31; |
| 2383 | | NEGI(dreg, src); |
| 2384 | | } |
| 2385 | | |
| 2386 | | void tms3203x_device::negi_imm(UINT32 op) |
| 2387 | | { |
| 2388 | | UINT32 src = (INT16)op; |
| 2389 | | int dreg = (op >> 16) & 31; |
| 2390 | | NEGI(dreg, src); |
| 2391 | | } |
| 2392 | | |
| 2393 | | /*-----------------------------------------------------*/ |
| 2394 | | |
| 2395 | | void tms3203x_device::nop_reg(UINT32 op) |
| 2396 | | { |
| 2397 | | } |
| 2398 | | |
| 2399 | | void tms3203x_device::nop_ind(UINT32 op) |
| 2400 | | { |
| 2401 | | RMEM(INDIRECT_D(op, op >> 8)); |
| 2402 | | } |
| 2403 | | |
| 2404 | | /*-----------------------------------------------------*/ |
| 2405 | | |
| 2406 | | void tms3203x_device::norm_reg(UINT32 op) |
| 2407 | | { |
| 2408 | | int dreg = (op >> 16) & 7; |
| 2409 | | norm(m_r[dreg], m_r[op & 7]); |
| 2410 | | } |
| 2411 | | |
| 2412 | | void tms3203x_device::norm_dir(UINT32 op) |
| 2413 | | { |
| 2414 | | UINT32 res = RMEM(DIRECT(op)); |
| 2415 | | int dreg = (op >> 16) & 7; |
| 2416 | | LONG2FP(TMR_TEMP1, res); |
| 2417 | | norm(m_r[dreg], m_r[TMR_TEMP1]); |
| 2418 | | } |
| 2419 | | |
| 2420 | | void tms3203x_device::norm_ind(UINT32 op) |
| 2421 | | { |
| 2422 | | UINT32 res = RMEM(INDIRECT_D(op, op >> 8)); |
| 2423 | | int dreg = (op >> 16) & 7; |
| 2424 | | LONG2FP(TMR_TEMP1, res); |
| 2425 | | norm(m_r[dreg], m_r[TMR_TEMP1]); |
| 2426 | | } |
| 2427 | | |
| 2428 | | void tms3203x_device::norm_imm(UINT32 op) |
| 2429 | | { |
| 2430 | | int dreg = (op >> 16) & 7; |
| 2431 | | SHORT2FP(TMR_TEMP1, op); |
| 2432 | | norm(m_r[dreg], m_r[TMR_TEMP1]); |
| 2433 | | } |
| 2434 | | |
| 2435 | | /*-----------------------------------------------------*/ |
| 2436 | | |
| 2437 | | #define NOT(dreg, src) \ |
| 2438 | | { \ |
| 2439 | | UINT32 _res = ~(src); \ |
| 2440 | | IREG(dreg) = _res; \ |
| 2441 | | if (dreg < 8) \ |
| 2442 | | { \ |
| 2443 | | CLR_NZVUF(); \ |
| 2444 | | OR_NZ(_res); \ |
| 2445 | | } \ |
| 2446 | | else if (dreg >= TMR_BK) \ |
| 2447 | | update_special(dreg); \ |
| 2448 | | } |
| 2449 | | |
| 2450 | | void tms3203x_device::not_reg(UINT32 op) |
| 2451 | | { |
| 2452 | | UINT32 src = IREG(op & 31); |
| 2453 | | int dreg = (op >> 16) & 31; |
| 2454 | | NOT(dreg, src); |
| 2455 | | } |
| 2456 | | |
| 2457 | | void tms3203x_device::not_dir(UINT32 op) |
| 2458 | | { |
| 2459 | | UINT32 src = RMEM(DIRECT(op)); |
| 2460 | | int dreg = (op >> 16) & 31; |
| 2461 | | NOT(dreg, src); |
| 2462 | | } |
| 2463 | | |
| 2464 | | void tms3203x_device::not_ind(UINT32 op) |
| 2465 | | { |
| 2466 | | UINT32 src = RMEM(INDIRECT_D(op, op >> 8)); |
| 2467 | | int dreg = (op >> 16) & 31; |
| 2468 | | NOT(dreg, src); |
| 2469 | | } |
| 2470 | | |
| 2471 | | void tms3203x_device::not_imm(UINT32 op) |
| 2472 | | { |
| 2473 | | UINT32 src = (UINT16)op; |
| 2474 | | int dreg = (op >> 16) & 31; |
| 2475 | | NOT(dreg, src); |
| 2476 | | } |
| 2477 | | |
| 2478 | | /*-----------------------------------------------------*/ |
| 2479 | | |
| 2480 | | void tms3203x_device::pop(UINT32 op) |
| 2481 | | { |
| 2482 | | int dreg = (op >> 16) & 31; |
| 2483 | | UINT32 val = RMEM(IREG(TMR_SP)--); |
| 2484 | | IREG(dreg) = val; |
| 2485 | | if (dreg < 8) |
| 2486 | | { |
| 2487 | | CLR_NZVUF(); |
| 2488 | | OR_NZ(val); |
| 2489 | | } |
| 2490 | | else if (dreg >= TMR_BK) |
| 2491 | | update_special(dreg); |
| 2492 | | } |
| 2493 | | |
| 2494 | | void tms3203x_device::popf(UINT32 op) |
| 2495 | | { |
| 2496 | | int dreg = (op >> 16) & 7; |
| 2497 | | UINT32 val = RMEM(IREG(TMR_SP)--); |
| 2498 | | LONG2FP(dreg, val); |
| 2499 | | CLR_NZVUF(); |
| 2500 | | OR_NZF(m_r[dreg]); |
| 2501 | | } |
| 2502 | | |
| 2503 | | void tms3203x_device::push(UINT32 op) |
| 2504 | | { |
| 2505 | | WMEM(++IREG(TMR_SP), IREG((op >> 16) & 31)); |
| 2506 | | } |
| 2507 | | |
| 2508 | | void tms3203x_device::pushf(UINT32 op) |
| 2509 | | { |
| 2510 | | int dreg = (op >> 16) & 7; |
| 2511 | | WMEM(++IREG(TMR_SP), FP2LONG(dreg)); |
| 2512 | | } |
| 2513 | | |
| 2514 | | /*-----------------------------------------------------*/ |
| 2515 | | |
| 2516 | | #define OR(dreg, src1, src2) \ |
| 2517 | | { \ |
| 2518 | | UINT32 _res = (src1) | (src2); \ |
| 2519 | | IREG(dreg) = _res; \ |
| 2520 | | if (dreg < 8) \ |
| 2521 | | { \ |
| 2522 | | CLR_NZVUF(); \ |
| 2523 | | OR_NZ(_res); \ |
| 2524 | | } \ |
| 2525 | | else if (dreg >= TMR_BK) \ |
| 2526 | | update_special(dreg); \ |
| 2527 | | } |
| 2528 | | |
| 2529 | | void tms3203x_device::or_reg(UINT32 op) |
| 2530 | | { |
| 2531 | | UINT32 src = IREG(op & 31); |
| 2532 | | int dreg = (op >> 16) & 31; |
| 2533 | | UINT32 dst = IREG(dreg); |
| 2534 | | OR(dreg, dst, src); |
| 2535 | | } |
| 2536 | | |
| 2537 | | void tms3203x_device::or_dir(UINT32 op) |
| 2538 | | { |
| 2539 | | UINT32 src = RMEM(DIRECT(op)); |
| 2540 | | int dreg = (op >> 16) & 31; |
| 2541 | | UINT32 dst = IREG(dreg); |
| 2542 | | OR(dreg, dst, src); |
| 2543 | | } |
| 2544 | | |
| 2545 | | void tms3203x_device::or_ind(UINT32 op) |
| 2546 | | { |
| 2547 | | UINT32 src = RMEM(INDIRECT_D(op, op >> 8)); |
| 2548 | | int dreg = (op >> 16) & 31; |
| 2549 | | UINT32 dst = IREG(dreg); |
| 2550 | | OR(dreg, dst, src); |
| 2551 | | } |
| 2552 | | |
| 2553 | | void tms3203x_device::or_imm(UINT32 op) |
| 2554 | | { |
| 2555 | | UINT32 src = (UINT16)op; |
| 2556 | | int dreg = (op >> 16) & 31; |
| 2557 | | UINT32 dst = IREG(dreg); |
| 2558 | | OR(dreg, dst, src); |
| 2559 | | } |
| 2560 | | |
| 2561 | | /*-----------------------------------------------------*/ |
| 2562 | | |
| 2563 | | void tms3203x_device::maxspeed(UINT32 op) { unimplemented(op); } |
| 2564 | | |
| 2565 | | /*-----------------------------------------------------*/ |
| 2566 | | |
| 2567 | | #define RND(dreg) \ |
| 2568 | | { \ |
| 2569 | | INT32 man = FREGMAN(dreg); \ |
| 2570 | | CLR_NVUF(); \ |
| 2571 | | if (man < 0x7fffff80) \ |
| 2572 | | { \ |
| 2573 | | m_r[dreg].set_mantissa(((UINT32)man + 0x80) & 0xffffff00); \ |
| 2574 | | OR_NUF(m_r[dreg]); \ |
| 2575 | | } \ |
| 2576 | | else if (FREGEXP(dreg) < 127) \ |
| 2577 | | { \ |
| 2578 | | m_r[dreg].set_mantissa(((UINT32)man + 0x80) & 0x7fffff00); \ |
| 2579 | | m_r[dreg].set_exponent(FREGEXP(dreg) + 1); \ |
| 2580 | | OR_NUF(m_r[dreg]); \ |
| 2581 | | } \ |
| 2582 | | else \ |
| 2583 | | { \ |
| 2584 | | m_r[dreg].set_mantissa(0x7fffff00); \ |
| 2585 | | IREG(TMR_ST) |= VFLAG | LVFLAG; \ |
| 2586 | | } \ |
| 2587 | | } |
| 2588 | | |
| 2589 | | void tms3203x_device::rnd_reg(UINT32 op) |
| 2590 | | { |
| 2591 | | int sreg = op & 7; |
| 2592 | | int dreg = (op >> 16) & 7; |
| 2593 | | m_r[dreg] = m_r[sreg]; |
| 2594 | | RND(dreg); |
| 2595 | | } |
| 2596 | | |
| 2597 | | void tms3203x_device::rnd_dir(UINT32 op) |
| 2598 | | { |
| 2599 | | UINT32 res = RMEM(DIRECT(op)); |
| 2600 | | int dreg = (op >> 16) & 7; |
| 2601 | | LONG2FP(dreg, res); |
| 2602 | | RND(dreg); |
| 2603 | | } |
| 2604 | | |
| 2605 | | void tms3203x_device::rnd_ind(UINT32 op) |
| 2606 | | { |
| 2607 | | UINT32 res = RMEM(INDIRECT_D(op, op >> 8)); |
| 2608 | | int dreg = (op >> 16) & 7; |
| 2609 | | LONG2FP(dreg, res); |
| 2610 | | RND(dreg); |
| 2611 | | } |
| 2612 | | |
| 2613 | | void tms3203x_device::rnd_imm(UINT32 op) |
| 2614 | | { |
| 2615 | | int dreg = (op >> 16) & 7; |
| 2616 | | SHORT2FP(dreg, op); |
| 2617 | | RND(dreg); |
| 2618 | | } |
| 2619 | | |
| 2620 | | /*-----------------------------------------------------*/ |
| 2621 | | |
| 2622 | | void tms3203x_device::rol(UINT32 op) |
| 2623 | | { |
| 2624 | | int dreg = (op >> 16) & 31; |
| 2625 | | UINT32 res = IREG(dreg); |
| 2626 | | int newcflag = res >> 31; |
| 2627 | | res = (res << 1) | newcflag; |
| 2628 | | IREG(dreg) = res; |
| 2629 | | if (dreg < 8) |
| 2630 | | { |
| 2631 | | CLR_NZCVUF(); |
| 2632 | | OR_NZ(res); |
| 2633 | | OR_C(newcflag); |
| 2634 | | } |
| 2635 | | else if (dreg >= TMR_BK) |
| 2636 | | update_special(dreg); |
| 2637 | | } |
| 2638 | | |
| 2639 | | void tms3203x_device::rolc(UINT32 op) |
| 2640 | | { |
| 2641 | | int dreg = (op >> 16) & 31; |
| 2642 | | UINT32 res = IREG(dreg); |
| 2643 | | int newcflag = res >> 31; |
| 2644 | | res = (res << 1) | (IREG(TMR_ST) & CFLAG); |
| 2645 | | IREG(dreg) = res; |
| 2646 | | if (dreg < 8) |
| 2647 | | { |
| 2648 | | CLR_NZCVUF(); |
| 2649 | | OR_NZ(res); |
| 2650 | | OR_C(newcflag); |
| 2651 | | } |
| 2652 | | else if (dreg >= TMR_BK) |
| 2653 | | update_special(dreg); |
| 2654 | | } |
| 2655 | | |
| 2656 | | void tms3203x_device::ror(UINT32 op) |
| 2657 | | { |
| 2658 | | int dreg = (op >> 16) & 31; |
| 2659 | | UINT32 res = IREG(dreg); |
| 2660 | | int newcflag = res & 1; |
| 2661 | | res = (res >> 1) | (newcflag << 31); |
| 2662 | | IREG(dreg) = res; |
| 2663 | | if (dreg < 8) |
| 2664 | | { |
| 2665 | | CLR_NZCVUF(); |
| 2666 | | OR_NZ(res); |
| 2667 | | OR_C(newcflag); |
| 2668 | | } |
| 2669 | | else if (dreg >= TMR_BK) |
| 2670 | | update_special(dreg); |
| 2671 | | } |
| 2672 | | |
| 2673 | | void tms3203x_device::rorc(UINT32 op) |
| 2674 | | { |
| 2675 | | int dreg = (op >> 16) & 31; |
| 2676 | | UINT32 res = IREG(dreg); |
| 2677 | | int newcflag = res & 1; |
| 2678 | | res = (res >> 1) | ((IREG(TMR_ST) & CFLAG) << 31); |
| 2679 | | IREG(dreg) = res; |
| 2680 | | if (dreg < 8) |
| 2681 | | { |
| 2682 | | CLR_NZCVUF(); |
| 2683 | | OR_NZ(res); |
| 2684 | | OR_C(newcflag); |
| 2685 | | } |
| 2686 | | else if (dreg >= TMR_BK) |
| 2687 | | update_special(dreg); |
| 2688 | | } |
| 2689 | | |
| 2690 | | /*-----------------------------------------------------*/ |
| 2691 | | |
| 2692 | | void tms3203x_device::rtps_reg(UINT32 op) |
| 2693 | | { |
| 2694 | | IREG(TMR_RC) = IREG(op & 31); |
| 2695 | | IREG(TMR_RS) = m_pc; |
| 2696 | | IREG(TMR_RE) = m_pc; |
| 2697 | | IREG(TMR_ST) |= RMFLAG; |
| 2698 | | m_icount -= 3*2; |
| 2699 | | m_delayed = true; |
| 2700 | | } |
| 2701 | | |
| 2702 | | void tms3203x_device::rtps_dir(UINT32 op) |
| 2703 | | { |
| 2704 | | IREG(TMR_RC) = RMEM(DIRECT(op)); |
| 2705 | | IREG(TMR_RS) = m_pc; |
| 2706 | | IREG(TMR_RE) = m_pc; |
| 2707 | | IREG(TMR_ST) |= RMFLAG; |
| 2708 | | m_icount -= 3*2; |
| 2709 | | m_delayed = true; |
| 2710 | | } |
| 2711 | | |
| 2712 | | void tms3203x_device::rtps_ind(UINT32 op) |
| 2713 | | { |
| 2714 | | IREG(TMR_RC) = RMEM(INDIRECT_D(op, op >> 8)); |
| 2715 | | IREG(TMR_RS) = m_pc; |
| 2716 | | IREG(TMR_RE) = m_pc; |
| 2717 | | IREG(TMR_ST) |= RMFLAG; |
| 2718 | | m_icount -= 3*2; |
| 2719 | | m_delayed = true; |
| 2720 | | } |
| 2721 | | |
| 2722 | | void tms3203x_device::rtps_imm(UINT32 op) |
| 2723 | | { |
| 2724 | | IREG(TMR_RC) = (UINT16)op; |
| 2725 | | IREG(TMR_RS) = m_pc; |
| 2726 | | IREG(TMR_RE) = m_pc; |
| 2727 | | IREG(TMR_ST) |= RMFLAG; |
| 2728 | | m_icount -= 3*2; |
| 2729 | | m_delayed = true; |
| 2730 | | } |
| 2731 | | |
| 2732 | | /*-----------------------------------------------------*/ |
| 2733 | | |
| 2734 | | void tms3203x_device::stf_dir(UINT32 op) |
| 2735 | | { |
| 2736 | | WMEM(DIRECT(op), FP2LONG((op >> 16) & 7)); |
| 2737 | | } |
| 2738 | | |
| 2739 | | void tms3203x_device::stf_ind(UINT32 op) |
| 2740 | | { |
| 2741 | | WMEM(INDIRECT_D(op, op >> 8), FP2LONG((op >> 16) & 7)); |
| 2742 | | } |
| 2743 | | |
| 2744 | | /*-----------------------------------------------------*/ |
| 2745 | | |
| 2746 | | void tms3203x_device::stfi_dir(UINT32 op) { unimplemented(op); } |
| 2747 | | void tms3203x_device::stfi_ind(UINT32 op) { unimplemented(op); } |
| 2748 | | |
| 2749 | | /*-----------------------------------------------------*/ |
| 2750 | | |
| 2751 | | void tms3203x_device::sti_dir(UINT32 op) |
| 2752 | | { |
| 2753 | | WMEM(DIRECT(op), IREG((op >> 16) & 31)); |
| 2754 | | } |
| 2755 | | |
| 2756 | | void tms3203x_device::sti_ind(UINT32 op) |
| 2757 | | { |
| 2758 | | WMEM(INDIRECT_D(op, op >> 8), IREG((op >> 16) & 31)); |
| 2759 | | } |
| 2760 | | |
| 2761 | | /*-----------------------------------------------------*/ |
| 2762 | | |
| 2763 | | void tms3203x_device::stii_dir(UINT32 op) { unimplemented(op); } |
| 2764 | | void tms3203x_device::stii_ind(UINT32 op) { unimplemented(op); } |
| 2765 | | |
| 2766 | | /*-----------------------------------------------------*/ |
| 2767 | | |
| 2768 | | void tms3203x_device::sigi(UINT32 op) { unimplemented(op); } |
| 2769 | | |
| 2770 | | /*-----------------------------------------------------*/ |
| 2771 | | |
| 2772 | | #define SUBB(dreg, src1, src2) \ |
| 2773 | | { \ |
| 2774 | | UINT32 _res = src1 - src2 - (IREG(TMR_ST) & CFLAG); \ |
| 2775 | | if (!OVM() || !OVERFLOW_SUB(src1,src2,_res)) \ |
| 2776 | | IREG(dreg) = _res; \ |
| 2777 | | else \ |
| 2778 | | IREG(dreg) = ((INT32)src1 < 0) ? 0x80000000 : 0x7fffffff; \ |
| 2779 | | if (dreg < 8) \ |
| 2780 | | { \ |
| 2781 | | UINT32 tempc = IREG(TMR_ST) & CFLAG; \ |
| 2782 | | CLR_NZCVUF(); \ |
| 2783 | | OR_C_SBB(src1,src2,tempc); \ |
| 2784 | | OR_V_SUB(src1,src2,_res); \ |
| 2785 | | OR_NZ(_res); \ |
| 2786 | | } \ |
| 2787 | | else if (dreg >= TMR_BK) \ |
| 2788 | | update_special(dreg); \ |
| 2789 | | } |
| 2790 | | |
| 2791 | | void tms3203x_device::subb_reg(UINT32 op) |
| 2792 | | { |
| 2793 | | UINT32 src = IREG(op & 31); |
| 2794 | | int dreg = (op >> 16) & 31; |
| 2795 | | UINT32 dst = IREG(dreg); |
| 2796 | | SUBB(dreg, dst, src); |
| 2797 | | } |
| 2798 | | |
| 2799 | | void tms3203x_device::subb_dir(UINT32 op) |
| 2800 | | { |
| 2801 | | UINT32 src = RMEM(DIRECT(op)); |
| 2802 | | int dreg = (op >> 16) & 31; |
| 2803 | | UINT32 dst = IREG(dreg); |
| 2804 | | SUBB(dreg, dst, src); |
| 2805 | | } |
| 2806 | | |
| 2807 | | void tms3203x_device::subb_ind(UINT32 op) |
| 2808 | | { |
| 2809 | | UINT32 src = RMEM(INDIRECT_D(op, op >> 8)); |
| 2810 | | int dreg = (op >> 16) & 31; |
| 2811 | | UINT32 dst = IREG(dreg); |
| 2812 | | SUBB(dreg, dst, src); |
| 2813 | | } |
| 2814 | | |
| 2815 | | void tms3203x_device::subb_imm(UINT32 op) |
| 2816 | | { |
| 2817 | | UINT32 src = (INT16)op; |
| 2818 | | int dreg = (op >> 16) & 31; |
| 2819 | | UINT32 dst = IREG(dreg); |
| 2820 | | SUBB(dreg, dst, src); |
| 2821 | | } |
| 2822 | | |
| 2823 | | /*-----------------------------------------------------*/ |
| 2824 | | |
| 2825 | | #define SUBC(dreg, src) \ |
| 2826 | | { \ |
| 2827 | | UINT32 dst = IREG(dreg); \ |
| 2828 | | if (dst >= src) \ |
| 2829 | | IREG(dreg) = ((dst - src) << 1) | 1; \ |
| 2830 | | else \ |
| 2831 | | IREG(dreg) = dst << 1; \ |
| 2832 | | if (dreg >= TMR_BK) \ |
| 2833 | | update_special(dreg); \ |
| 2834 | | } |
| 2835 | | |
| 2836 | | void tms3203x_device::subc_reg(UINT32 op) |
| 2837 | | { |
| 2838 | | UINT32 src = IREG(op & 31); |
| 2839 | | int dreg = (op >> 16) & 31; |
| 2840 | | SUBC(dreg, src); |
| 2841 | | } |
| 2842 | | |
| 2843 | | void tms3203x_device::subc_dir(UINT32 op) |
| 2844 | | { |
| 2845 | | UINT32 src = RMEM(DIRECT(op)); |
| 2846 | | int dreg = (op >> 16) & 31; |
| 2847 | | SUBC(dreg, src); |
| 2848 | | } |
| 2849 | | |
| 2850 | | void tms3203x_device::subc_ind(UINT32 op) |
| 2851 | | { |
| 2852 | | UINT32 src = RMEM(INDIRECT_D(op, op >> 8)); |
| 2853 | | int dreg = (op >> 16) & 31; |
| 2854 | | SUBC(dreg, src); |
| 2855 | | } |
| 2856 | | |
| 2857 | | void tms3203x_device::subc_imm(UINT32 op) |
| 2858 | | { |
| 2859 | | UINT32 src = (INT16)op; |
| 2860 | | int dreg = (op >> 16) & 31; |
| 2861 | | SUBC(dreg, src); |
| 2862 | | } |
| 2863 | | |
| 2864 | | /*-----------------------------------------------------*/ |
| 2865 | | |
| 2866 | | void tms3203x_device::subf_reg(UINT32 op) |
| 2867 | | { |
| 2868 | | int dreg = (op >> 16) & 7; |
| 2869 | | subf(m_r[dreg], m_r[dreg], m_r[op & 7]); |
| 2870 | | } |
| 2871 | | |
| 2872 | | void tms3203x_device::subf_dir(UINT32 op) |
| 2873 | | { |
| 2874 | | UINT32 res = RMEM(DIRECT(op)); |
| 2875 | | int dreg = (op >> 16) & 7; |
| 2876 | | LONG2FP(TMR_TEMP1, res); |
| 2877 | | subf(m_r[dreg], m_r[dreg], m_r[TMR_TEMP1]); |
| 2878 | | } |
| 2879 | | |
| 2880 | | void tms3203x_device::subf_ind(UINT32 op) |
| 2881 | | { |
| 2882 | | UINT32 res = RMEM(INDIRECT_D(op, op >> 8)); |
| 2883 | | int dreg = (op >> 16) & 7; |
| 2884 | | LONG2FP(TMR_TEMP1, res); |
| 2885 | | subf(m_r[dreg], m_r[dreg], m_r[TMR_TEMP1]); |
| 2886 | | } |
| 2887 | | |
| 2888 | | void tms3203x_device::subf_imm(UINT32 op) |
| 2889 | | { |
| 2890 | | int dreg = (op >> 16) & 7; |
| 2891 | | SHORT2FP(TMR_TEMP1, op); |
| 2892 | | subf(m_r[dreg], m_r[dreg], m_r[TMR_TEMP1]); |
| 2893 | | } |
| 2894 | | |
| 2895 | | /*-----------------------------------------------------*/ |
| 2896 | | |
| 2897 | | #define SUBI(dreg, src1, src2) \ |
| 2898 | | { \ |
| 2899 | | UINT32 _res = src1 - src2; \ |
| 2900 | | if (!OVM() || !OVERFLOW_SUB(src1,src2,_res)) \ |
| 2901 | | IREG(dreg) = _res; \ |
| 2902 | | else \ |
| 2903 | | IREG(dreg) = ((INT32)src1 < 0) ? 0x80000000 : 0x7fffffff; \ |
| 2904 | | if (dreg < 8) \ |
| 2905 | | { \ |
| 2906 | | CLR_NZCVUF(); \ |
| 2907 | | OR_C_SUB(src1,src2,_res); \ |
| 2908 | | OR_V_SUB(src1,src2,_res); \ |
| 2909 | | OR_NZ(_res); \ |
| 2910 | | } \ |
| 2911 | | else if (dreg >= TMR_BK) \ |
| 2912 | | update_special(dreg); \ |
| 2913 | | } |
| 2914 | | |
| 2915 | | void tms3203x_device::subi_reg(UINT32 op) |
| 2916 | | { |
| 2917 | | UINT32 src = IREG(op & 31); |
| 2918 | | int dreg = (op >> 16) & 31; |
| 2919 | | UINT32 dst = IREG(dreg); |
| 2920 | | SUBI(dreg, dst, src); |
| 2921 | | } |
| 2922 | | |
| 2923 | | void tms3203x_device::subi_dir(UINT32 op) |
| 2924 | | { |
| 2925 | | UINT32 src = RMEM(DIRECT(op)); |
| 2926 | | int dreg = (op >> 16) & 31; |
| 2927 | | UINT32 dst = IREG(dreg); |
| 2928 | | SUBI(dreg, dst, src); |
| 2929 | | } |
| 2930 | | |
| 2931 | | void tms3203x_device::subi_ind(UINT32 op) |
| 2932 | | { |
| 2933 | | UINT32 src = RMEM(INDIRECT_D(op, op >> 8)); |
| 2934 | | int dreg = (op >> 16) & 31; |
| 2935 | | UINT32 dst = IREG(dreg); |
| 2936 | | SUBI(dreg, dst, src); |
| 2937 | | } |
| 2938 | | |
| 2939 | | void tms3203x_device::subi_imm(UINT32 op) |
| 2940 | | { |
| 2941 | | UINT32 src = (INT16)op; |
| 2942 | | int dreg = (op >> 16) & 31; |
| 2943 | | UINT32 dst = IREG(dreg); |
| 2944 | | SUBI(dreg, dst, src); |
| 2945 | | } |
| 2946 | | |
| 2947 | | /*-----------------------------------------------------*/ |
| 2948 | | |
| 2949 | | void tms3203x_device::subrb_reg(UINT32 op) |
| 2950 | | { |
| 2951 | | UINT32 src = IREG(op & 31); |
| 2952 | | int dreg = (op >> 16) & 31; |
| 2953 | | UINT32 dst = IREG(dreg); |
| 2954 | | SUBB(dreg, src, dst); |
| 2955 | | } |
| 2956 | | |
| 2957 | | void tms3203x_device::subrb_dir(UINT32 op) |
| 2958 | | { |
| 2959 | | UINT32 src = RMEM(DIRECT(op)); |
| 2960 | | int dreg = (op >> 16) & 31; |
| 2961 | | UINT32 dst = IREG(dreg); |
| 2962 | | SUBB(dreg, src, dst); |
| 2963 | | } |
| 2964 | | |
| 2965 | | void tms3203x_device::subrb_ind(UINT32 op) |
| 2966 | | { |
| 2967 | | UINT32 src = RMEM(INDIRECT_D(op, op >> 8)); |
| 2968 | | int dreg = (op >> 16) & 31; |
| 2969 | | UINT32 dst = IREG(dreg); |
| 2970 | | SUBB(dreg, src, dst); |
| 2971 | | } |
| 2972 | | |
| 2973 | | void tms3203x_device::subrb_imm(UINT32 op) |
| 2974 | | { |
| 2975 | | UINT32 src = (INT16)op; |
| 2976 | | int dreg = (op >> 16) & 31; |
| 2977 | | UINT32 dst = IREG(dreg); |
| 2978 | | SUBB(dreg, src, dst); |
| 2979 | | } |
| 2980 | | |
| 2981 | | /*-----------------------------------------------------*/ |
| 2982 | | |
| 2983 | | void tms3203x_device::subrf_reg(UINT32 op) |
| 2984 | | { |
| 2985 | | int dreg = (op >> 16) & 7; |
| 2986 | | subf(m_r[dreg], m_r[op & 7], m_r[dreg]); |
| 2987 | | } |
| 2988 | | |
| 2989 | | void tms3203x_device::subrf_dir(UINT32 op) |
| 2990 | | { |
| 2991 | | UINT32 res = RMEM(DIRECT(op)); |
| 2992 | | int dreg = (op >> 16) & 7; |
| 2993 | | LONG2FP(TMR_TEMP1, res); |
| 2994 | | subf(m_r[dreg], m_r[TMR_TEMP1], m_r[dreg]); |
| 2995 | | } |
| 2996 | | |
| 2997 | | void tms3203x_device::subrf_ind(UINT32 op) |
| 2998 | | { |
| 2999 | | UINT32 res = RMEM(INDIRECT_D(op, op >> 8)); |
| 3000 | | int dreg = (op >> 16) & 7; |
| 3001 | | LONG2FP(TMR_TEMP1, res); |
| 3002 | | subf(m_r[dreg], m_r[TMR_TEMP1], m_r[dreg]); |
| 3003 | | } |
| 3004 | | |
| 3005 | | void tms3203x_device::subrf_imm(UINT32 op) |
| 3006 | | { |
| 3007 | | int dreg = (op >> 16) & 7; |
| 3008 | | SHORT2FP(TMR_TEMP1, op); |
| 3009 | | subf(m_r[dreg], m_r[TMR_TEMP1], m_r[dreg]); |
| 3010 | | } |
| 3011 | | |
| 3012 | | /*-----------------------------------------------------*/ |
| 3013 | | |
| 3014 | | void tms3203x_device::subri_reg(UINT32 op) |
| 3015 | | { |
| 3016 | | UINT32 src = IREG(op & 31); |
| 3017 | | int dreg = (op >> 16) & 31; |
| 3018 | | UINT32 dst = IREG(dreg); |
| 3019 | | SUBI(dreg, src, dst); |
| 3020 | | } |
| 3021 | | |
| 3022 | | void tms3203x_device::subri_dir(UINT32 op) |
| 3023 | | { |
| 3024 | | UINT32 src = RMEM(DIRECT(op)); |
| 3025 | | int dreg = (op >> 16) & 31; |
| 3026 | | UINT32 dst = IREG(dreg); |
| 3027 | | SUBI(dreg, src, dst); |
| 3028 | | } |
| 3029 | | |
| 3030 | | void tms3203x_device::subri_ind(UINT32 op) |
| 3031 | | { |
| 3032 | | UINT32 src = RMEM(INDIRECT_D(op, op >> 8)); |
| 3033 | | int dreg = (op >> 16) & 31; |
| 3034 | | UINT32 dst = IREG(dreg); |
| 3035 | | SUBI(dreg, src, dst); |
| 3036 | | } |
| 3037 | | |
| 3038 | | void tms3203x_device::subri_imm(UINT32 op) |
| 3039 | | { |
| 3040 | | UINT32 src = (INT16)op; |
| 3041 | | int dreg = (op >> 16) & 31; |
| 3042 | | UINT32 dst = IREG(dreg); |
| 3043 | | SUBI(dreg, src, dst); |
| 3044 | | } |
| 3045 | | |
| 3046 | | /*-----------------------------------------------------*/ |
| 3047 | | |
| 3048 | | #define TSTB(src1, src2) \ |
| 3049 | | { \ |
| 3050 | | UINT32 _res = (src1) & (src2); \ |
| 3051 | | CLR_NZVUF(); \ |
| 3052 | | OR_NZ(_res); \ |
| 3053 | | } |
| 3054 | | |
| 3055 | | void tms3203x_device::tstb_reg(UINT32 op) |
| 3056 | | { |
| 3057 | | UINT32 src = IREG(op & 31); |
| 3058 | | UINT32 dst = IREG((op >> 16) & 31); |
| 3059 | | TSTB(dst, src); |
| 3060 | | } |
| 3061 | | |
| 3062 | | void tms3203x_device::tstb_dir(UINT32 op) |
| 3063 | | { |
| 3064 | | UINT32 src = RMEM(DIRECT(op)); |
| 3065 | | UINT32 dst = IREG((op >> 16) & 31); |
| 3066 | | TSTB(dst, src); |
| 3067 | | } |
| 3068 | | |
| 3069 | | void tms3203x_device::tstb_ind(UINT32 op) |
| 3070 | | { |
| 3071 | | UINT32 src = RMEM(INDIRECT_D(op, op >> 8)); |
| 3072 | | UINT32 dst = IREG((op >> 16) & 31); |
| 3073 | | TSTB(dst, src); |
| 3074 | | } |
| 3075 | | |
| 3076 | | void tms3203x_device::tstb_imm(UINT32 op) |
| 3077 | | { |
| 3078 | | UINT32 src = (UINT16)op; |
| 3079 | | UINT32 dst = IREG((op >> 16) & 31); |
| 3080 | | TSTB(dst, src); |
| 3081 | | } |
| 3082 | | |
| 3083 | | /*-----------------------------------------------------*/ |
| 3084 | | |
| 3085 | | #define XOR(dreg, src1, src2) \ |
| 3086 | | { \ |
| 3087 | | UINT32 _res = (src1) ^ (src2); \ |
| 3088 | | IREG(dreg) = _res; \ |
| 3089 | | if (dreg < 8) \ |
| 3090 | | { \ |
| 3091 | | CLR_NZVUF(); \ |
| 3092 | | OR_NZ(_res); \ |
| 3093 | | } \ |
| 3094 | | else if (dreg >= TMR_BK) \ |
| 3095 | | update_special(dreg); \ |
| 3096 | | } |
| 3097 | | |
| 3098 | | void tms3203x_device::xor_reg(UINT32 op) |
| 3099 | | { |
| 3100 | | UINT32 src = IREG(op & 31); |
| 3101 | | int dreg = (op >> 16) & 31; |
| 3102 | | UINT32 dst = IREG(dreg); |
| 3103 | | XOR(dreg, dst, src); |
| 3104 | | } |
| 3105 | | |
| 3106 | | void tms3203x_device::xor_dir(UINT32 op) |
| 3107 | | { |
| 3108 | | UINT32 src = RMEM(DIRECT(op)); |
| 3109 | | int dreg = (op >> 16) & 31; |
| 3110 | | UINT32 dst = IREG(dreg); |
| 3111 | | XOR(dreg, dst, src); |
| 3112 | | } |
| 3113 | | |
| 3114 | | void tms3203x_device::xor_ind(UINT32 op) |
| 3115 | | { |
| 3116 | | UINT32 src = RMEM(INDIRECT_D(op, op >> 8)); |
| 3117 | | int dreg = (op >> 16) & 31; |
| 3118 | | UINT32 dst = IREG(dreg); |
| 3119 | | XOR(dreg, dst, src); |
| 3120 | | } |
| 3121 | | |
| 3122 | | void tms3203x_device::xor_imm(UINT32 op) |
| 3123 | | { |
| 3124 | | UINT32 src = (UINT16)op; |
| 3125 | | int dreg = (op >> 16) & 31; |
| 3126 | | UINT32 dst = IREG(dreg); |
| 3127 | | XOR(dreg, dst, src); |
| 3128 | | } |
| 3129 | | |
| 3130 | | /*-----------------------------------------------------*/ |
| 3131 | | |
| 3132 | | void tms3203x_device::iack_dir(UINT32 op) |
| 3133 | | { |
| 3134 | | offs_t addr = DIRECT(op); |
| 3135 | | m_iack_cb(addr, ASSERT_LINE); |
| 3136 | | RMEM(addr); |
| 3137 | | m_iack_cb(addr, CLEAR_LINE); |
| 3138 | | } |
| 3139 | | |
| 3140 | | void tms3203x_device::iack_ind(UINT32 op) |
| 3141 | | { |
| 3142 | | offs_t addr = INDIRECT_D(op, op >> 8); |
| 3143 | | m_iack_cb(addr, ASSERT_LINE); |
| 3144 | | RMEM(addr); |
| 3145 | | m_iack_cb(addr, CLEAR_LINE); |
| 3146 | | } |
| 3147 | | |
| 3148 | | /*-----------------------------------------------------*/ |
| 3149 | | |
| 3150 | | void tms3203x_device::addc3_regreg(UINT32 op) |
| 3151 | | { |
| 3152 | | UINT32 src1 = IREG((op >> 8) & 31); |
| 3153 | | UINT32 src2 = IREG(op & 31); |
| 3154 | | int dreg = (op >> 16) & 31; |
| 3155 | | ADDC(dreg, src1, src2); |
| 3156 | | } |
| 3157 | | |
| 3158 | | void tms3203x_device::addc3_indreg(UINT32 op) |
| 3159 | | { |
| 3160 | | UINT32 src1 = RMEM(INDIRECT_1(op, op >> 8)); |
| 3161 | | UINT32 src2 = IREG(op & 31); |
| 3162 | | int dreg = (op >> 16) & 31; |
| 3163 | | ADDC(dreg, src1, src2); |
| 3164 | | } |
| 3165 | | |
| 3166 | | void tms3203x_device::addc3_regind(UINT32 op) |
| 3167 | | { |
| 3168 | | UINT32 src2 = RMEM(INDIRECT_1(op, op)); |
| 3169 | | UINT32 src1 = IREG((op >> 8) & 31); |
| 3170 | | int dreg = (op >> 16) & 31; |
| 3171 | | ADDC(dreg, src1, src2); |
| 3172 | | } |
| 3173 | | |
| 3174 | | void tms3203x_device::addc3_indind(UINT32 op) |
| 3175 | | { |
| 3176 | | DECLARE_DEF; |
| 3177 | | UINT32 src1 = RMEM(INDIRECT_1_DEF(op, op >> 8)); |
| 3178 | | UINT32 src2 = RMEM(INDIRECT_1(op, op)); |
| 3179 | | int dreg = (op >> 16) & 31; |
| 3180 | | UPDATE_DEF(); |
| 3181 | | ADDC(dreg, src1, src2); |
| 3182 | | } |
| 3183 | | |
| 3184 | | /*-----------------------------------------------------*/ |
| 3185 | | |
| 3186 | | void tms3203x_device::addf3_regreg(UINT32 op) |
| 3187 | | { |
| 3188 | | int sreg1 = (op >> 8) & 7; |
| 3189 | | int sreg2 = op & 7; |
| 3190 | | int dreg = (op >> 16) & 7; |
| 3191 | | addf(m_r[dreg], m_r[sreg1], m_r[sreg2]); |
| 3192 | | } |
| 3193 | | |
| 3194 | | void tms3203x_device::addf3_indreg(UINT32 op) |
| 3195 | | { |
| 3196 | | UINT32 src1 = RMEM(INDIRECT_1(op, op >> 8)); |
| 3197 | | int sreg2 = op & 7; |
| 3198 | | int dreg = (op >> 16) & 7; |
| 3199 | | LONG2FP(TMR_TEMP1, src1); |
| 3200 | | addf(m_r[dreg], m_r[TMR_TEMP1], m_r[sreg2]); |
| 3201 | | } |
| 3202 | | |
| 3203 | | void tms3203x_device::addf3_regind(UINT32 op) |
| 3204 | | { |
| 3205 | | UINT32 src2 = RMEM(INDIRECT_1(op, op)); |
| 3206 | | int sreg1 = (op >> 8) & 7; |
| 3207 | | int dreg = (op >> 16) & 7; |
| 3208 | | LONG2FP(TMR_TEMP2, src2); |
| 3209 | | addf(m_r[dreg], m_r[sreg1], m_r[TMR_TEMP2]); |
| 3210 | | } |
| 3211 | | |
| 3212 | | void tms3203x_device::addf3_indind(UINT32 op) |
| 3213 | | { |
| 3214 | | DECLARE_DEF; |
| 3215 | | UINT32 src1 = RMEM(INDIRECT_1_DEF(op, op >> 8)); |
| 3216 | | UINT32 src2 = RMEM(INDIRECT_1(op, op)); |
| 3217 | | int dreg = (op >> 16) & 7; |
| 3218 | | UPDATE_DEF(); |
| 3219 | | LONG2FP(TMR_TEMP1, src1); |
| 3220 | | LONG2FP(TMR_TEMP2, src2); |
| 3221 | | addf(m_r[dreg], m_r[TMR_TEMP1], m_r[TMR_TEMP2]); |
| 3222 | | } |
| 3223 | | |
| 3224 | | /*-----------------------------------------------------*/ |
| 3225 | | |
| 3226 | | void tms3203x_device::addi3_regreg(UINT32 op) |
| 3227 | | { |
| 3228 | | UINT32 src1 = IREG((op >> 8) & 31); |
| 3229 | | UINT32 src2 = IREG(op & 31); |
| 3230 | | int dreg = (op >> 16) & 31; |
| 3231 | | ADDI(dreg, src1, src2); |
| 3232 | | } |
| 3233 | | |
| 3234 | | void tms3203x_device::addi3_indreg(UINT32 op) |
| 3235 | | { |
| 3236 | | UINT32 src1 = RMEM(INDIRECT_1(op, op >> 8)); |
| 3237 | | UINT32 src2 = IREG(op & 31); |
| 3238 | | int dreg = (op >> 16) & 31; |
| 3239 | | ADDI(dreg, src1, src2); |
| 3240 | | } |
| 3241 | | |
| 3242 | | void tms3203x_device::addi3_regind(UINT32 op) |
| 3243 | | { |
| 3244 | | // Radikal Bikers confirms via ADDI3 AR3,*AR3++(1),R2 / SUB $0001,R2 sequence |
| 3245 | | UINT32 src2 = RMEM(INDIRECT_1(op, op)); |
| 3246 | | UINT32 src1 = IREG((op >> 8) & 31); |
| 3247 | | int dreg = (op >> 16) & 31; |
| 3248 | | ADDI(dreg, src1, src2); |
| 3249 | | } |
| 3250 | | |
| 3251 | | void tms3203x_device::addi3_indind(UINT32 op) |
| 3252 | | { |
| 3253 | | DECLARE_DEF; |
| 3254 | | UINT32 src1 = RMEM(INDIRECT_1_DEF(op, op >> 8)); |
| 3255 | | UINT32 src2 = RMEM(INDIRECT_1(op, op)); |
| 3256 | | int dreg = (op >> 16) & 31; |
| 3257 | | UPDATE_DEF(); |
| 3258 | | ADDI(dreg, src1, src2); |
| 3259 | | } |
| 3260 | | |
| 3261 | | /*-----------------------------------------------------*/ |
| 3262 | | |
| 3263 | | void tms3203x_device::and3_regreg(UINT32 op) |
| 3264 | | { |
| 3265 | | UINT32 src1 = IREG((op >> 8) & 31); |
| 3266 | | UINT32 src2 = IREG(op & 31); |
| 3267 | | int dreg = (op >> 16) & 31; |
| 3268 | | AND(dreg, src1, src2); |
| 3269 | | } |
| 3270 | | |
| 3271 | | void tms3203x_device::and3_indreg(UINT32 op) |
| 3272 | | { |
| 3273 | | UINT32 src1 = RMEM(INDIRECT_1(op, op >> 8)); |
| 3274 | | UINT32 src2 = IREG(op & 31); |
| 3275 | | int dreg = (op >> 16) & 31; |
| 3276 | | AND(dreg, src1, src2); |
| 3277 | | } |
| 3278 | | |
| 3279 | | void tms3203x_device::and3_regind(UINT32 op) |
| 3280 | | { |
| 3281 | | UINT32 src2 = RMEM(INDIRECT_1(op, op)); |
| 3282 | | UINT32 src1 = IREG((op >> 8) & 31); |
| 3283 | | int dreg = (op >> 16) & 31; |
| 3284 | | AND(dreg, src1, src2); |
| 3285 | | } |
| 3286 | | |
| 3287 | | void tms3203x_device::and3_indind(UINT32 op) |
| 3288 | | { |
| 3289 | | DECLARE_DEF; |
| 3290 | | UINT32 src1 = RMEM(INDIRECT_1_DEF(op, op >> 8)); |
| 3291 | | UINT32 src2 = RMEM(INDIRECT_1(op, op)); |
| 3292 | | int dreg = (op >> 16) & 31; |
| 3293 | | UPDATE_DEF(); |
| 3294 | | AND(dreg, src1, src2); |
| 3295 | | } |
| 3296 | | |
| 3297 | | /*-----------------------------------------------------*/ |
| 3298 | | |
| 3299 | | void tms3203x_device::andn3_regreg(UINT32 op) |
| 3300 | | { |
| 3301 | | UINT32 src1 = IREG((op >> 8) & 31); |
| 3302 | | UINT32 src2 = IREG(op & 31); |
| 3303 | | int dreg = (op >> 16) & 31; |
| 3304 | | ANDN(dreg, src1, src2); |
| 3305 | | } |
| 3306 | | |
| 3307 | | void tms3203x_device::andn3_indreg(UINT32 op) |
| 3308 | | { |
| 3309 | | UINT32 src1 = RMEM(INDIRECT_1(op, op >> 8)); |
| 3310 | | UINT32 src2 = IREG(op & 31); |
| 3311 | | int dreg = (op >> 16) & 31; |
| 3312 | | ANDN(dreg, src1, src2); |
| 3313 | | } |
| 3314 | | |
| 3315 | | void tms3203x_device::andn3_regind(UINT32 op) |
| 3316 | | { |
| 3317 | | UINT32 src2 = RMEM(INDIRECT_1(op, op)); |
| 3318 | | UINT32 src1 = IREG((op >> 8) & 31); |
| 3319 | | int dreg = (op >> 16) & 31; |
| 3320 | | ANDN(dreg, src1, src2); |
| 3321 | | } |
| 3322 | | |
| 3323 | | void tms3203x_device::andn3_indind(UINT32 op) |
| 3324 | | { |
| 3325 | | DECLARE_DEF; |
| 3326 | | UINT32 src1 = RMEM(INDIRECT_1_DEF(op, op >> 8)); |
| 3327 | | UINT32 src2 = RMEM(INDIRECT_1(op, op)); |
| 3328 | | int dreg = (op >> 16) & 31; |
| 3329 | | UPDATE_DEF(); |
| 3330 | | ANDN(dreg, src1, src2); |
| 3331 | | } |
| 3332 | | |
| 3333 | | /*-----------------------------------------------------*/ |
| 3334 | | |
| 3335 | | void tms3203x_device::ash3_regreg(UINT32 op) |
| 3336 | | { |
| 3337 | | UINT32 src1 = IREG((op >> 8) & 31); |
| 3338 | | UINT32 src2 = IREG(op & 31); |
| 3339 | | int dreg = (op >> 16) & 31; |
| 3340 | | ASH(dreg, src1, src2); |
| 3341 | | } |
| 3342 | | |
| 3343 | | void tms3203x_device::ash3_indreg(UINT32 op) |
| 3344 | | { |
| 3345 | | UINT32 src1 = RMEM(INDIRECT_1(op, op >> 8)); |
| 3346 | | UINT32 src2 = IREG(op & 31); |
| 3347 | | int dreg = (op >> 16) & 31; |
| 3348 | | ASH(dreg, src1, src2); |
| 3349 | | } |
| 3350 | | |
| 3351 | | void tms3203x_device::ash3_regind(UINT32 op) |
| 3352 | | { |
| 3353 | | UINT32 src2 = RMEM(INDIRECT_1(op, op)); |
| 3354 | | UINT32 src1 = IREG((op >> 8) & 31); |
| 3355 | | int dreg = (op >> 16) & 31; |
| 3356 | | ASH(dreg, src1, src2); |
| 3357 | | } |
| 3358 | | |
| 3359 | | void tms3203x_device::ash3_indind(UINT32 op) |
| 3360 | | { |
| 3361 | | DECLARE_DEF; |
| 3362 | | UINT32 src1 = RMEM(INDIRECT_1_DEF(op, op >> 8)); |
| 3363 | | UINT32 src2 = RMEM(INDIRECT_1(op, op)); |
| 3364 | | int dreg = (op >> 16) & 31; |
| 3365 | | UPDATE_DEF(); |
| 3366 | | ASH(dreg, src1, src2); |
| 3367 | | } |
| 3368 | | |
| 3369 | | /*-----------------------------------------------------*/ |
| 3370 | | |
| 3371 | | void tms3203x_device::cmpf3_regreg(UINT32 op) |
| 3372 | | { |
| 3373 | | int sreg1 = (op >> 8) & 7; |
| 3374 | | int sreg2 = op & 7; |
| 3375 | | subf(m_r[TMR_TEMP1], m_r[sreg1], m_r[sreg2]); |
| 3376 | | } |
| 3377 | | |
| 3378 | | void tms3203x_device::cmpf3_indreg(UINT32 op) |
| 3379 | | { |
| 3380 | | UINT32 src1 = RMEM(INDIRECT_1(op, op >> 8)); |
| 3381 | | int sreg2 = op & 7; |
| 3382 | | LONG2FP(TMR_TEMP1, src1); |
| 3383 | | subf(m_r[TMR_TEMP1], m_r[TMR_TEMP1], m_r[sreg2]); |
| 3384 | | } |
| 3385 | | |
| 3386 | | void tms3203x_device::cmpf3_regind(UINT32 op) |
| 3387 | | { |
| 3388 | | UINT32 src2 = RMEM(INDIRECT_1(op, op)); |
| 3389 | | int sreg1 = (op >> 8) & 7; |
| 3390 | | LONG2FP(TMR_TEMP2, src2); |
| 3391 | | subf(m_r[TMR_TEMP1], m_r[sreg1], m_r[TMR_TEMP2]); |
| 3392 | | } |
| 3393 | | |
| 3394 | | void tms3203x_device::cmpf3_indind(UINT32 op) |
| 3395 | | { |
| 3396 | | DECLARE_DEF; |
| 3397 | | UINT32 src1 = RMEM(INDIRECT_1_DEF(op, op >> 8)); |
| 3398 | | UINT32 src2 = RMEM(INDIRECT_1(op, op)); |
| 3399 | | UPDATE_DEF(); |
| 3400 | | LONG2FP(TMR_TEMP1, src1); |
| 3401 | | LONG2FP(TMR_TEMP2, src2); |
| 3402 | | subf(m_r[TMR_TEMP1], m_r[TMR_TEMP1], m_r[TMR_TEMP2]); |
| 3403 | | } |
| 3404 | | |
| 3405 | | /*-----------------------------------------------------*/ |
| 3406 | | |
| 3407 | | void tms3203x_device::cmpi3_regreg(UINT32 op) |
| 3408 | | { |
| 3409 | | UINT32 src1 = IREG((op >> 8) & 31); |
| 3410 | | UINT32 src2 = IREG(op & 31); |
| 3411 | | CMPI(src1, src2); |
| 3412 | | } |
| 3413 | | |
| 3414 | | void tms3203x_device::cmpi3_indreg(UINT32 op) |
| 3415 | | { |
| 3416 | | UINT32 src1 = RMEM(INDIRECT_1(op, op >> 8)); |
| 3417 | | UINT32 src2 = IREG(op & 31); |
| 3418 | | CMPI(src1, src2); |
| 3419 | | } |
| 3420 | | |
| 3421 | | void tms3203x_device::cmpi3_regind(UINT32 op) |
| 3422 | | { |
| 3423 | | UINT32 src2 = RMEM(INDIRECT_1(op, op)); |
| 3424 | | UINT32 src1 = IREG((op >> 8) & 31); |
| 3425 | | CMPI(src1, src2); |
| 3426 | | } |
| 3427 | | |
| 3428 | | void tms3203x_device::cmpi3_indind(UINT32 op) |
| 3429 | | { |
| 3430 | | DECLARE_DEF; |
| 3431 | | UINT32 src1 = RMEM(INDIRECT_1_DEF(op, op >> 8)); |
| 3432 | | UINT32 src2 = RMEM(INDIRECT_1(op, op)); |
| 3433 | | UPDATE_DEF(); |
| 3434 | | CMPI(src1, src2); |
| 3435 | | } |
| 3436 | | |
| 3437 | | /*-----------------------------------------------------*/ |
| 3438 | | |
| 3439 | | void tms3203x_device::lsh3_regreg(UINT32 op) |
| 3440 | | { |
| 3441 | | UINT32 src1 = IREG((op >> 8) & 31); |
| 3442 | | UINT32 src2 = IREG(op & 31); |
| 3443 | | int dreg = (op >> 16) & 31; |
| 3444 | | LSH(dreg, src1, src2); |
| 3445 | | } |
| 3446 | | |
| 3447 | | void tms3203x_device::lsh3_indreg(UINT32 op) |
| 3448 | | { |
| 3449 | | UINT32 src1 = RMEM(INDIRECT_1(op, op >> 8)); |
| 3450 | | UINT32 src2 = IREG(op & 31); |
| 3451 | | int dreg = (op >> 16) & 31; |
| 3452 | | LSH(dreg, src1, src2); |
| 3453 | | } |
| 3454 | | |
| 3455 | | void tms3203x_device::lsh3_regind(UINT32 op) |
| 3456 | | { |
| 3457 | | UINT32 src2 = RMEM(INDIRECT_1(op, op)); |
| 3458 | | UINT32 src1 = IREG((op >> 8) & 31); |
| 3459 | | int dreg = (op >> 16) & 31; |
| 3460 | | LSH(dreg, src1, src2); |
| 3461 | | } |
| 3462 | | |
| 3463 | | void tms3203x_device::lsh3_indind(UINT32 op) |
| 3464 | | { |
| 3465 | | DECLARE_DEF; |
| 3466 | | UINT32 src1 = RMEM(INDIRECT_1_DEF(op, op >> 8)); |
| 3467 | | UINT32 src2 = RMEM(INDIRECT_1(op, op)); |
| 3468 | | int dreg = (op >> 16) & 31; |
| 3469 | | UPDATE_DEF(); |
| 3470 | | LSH(dreg, src1, src2); |
| 3471 | | } |
| 3472 | | |
| 3473 | | /*-----------------------------------------------------*/ |
| 3474 | | |
| 3475 | | void tms3203x_device::mpyf3_regreg(UINT32 op) |
| 3476 | | { |
| 3477 | | int sreg1 = (op >> 8) & 7; |
| 3478 | | int sreg2 = op & 7; |
| 3479 | | int dreg = (op >> 16) & 7; |
| 3480 | | mpyf(m_r[dreg], m_r[sreg1], m_r[sreg2]); |
| 3481 | | } |
| 3482 | | |
| 3483 | | void tms3203x_device::mpyf3_indreg(UINT32 op) |
| 3484 | | { |
| 3485 | | UINT32 src1 = RMEM(INDIRECT_1(op, op >> 8)); |
| 3486 | | int sreg2 = op & 7; |
| 3487 | | int dreg = (op >> 16) & 7; |
| 3488 | | LONG2FP(TMR_TEMP1, src1); |
| 3489 | | mpyf(m_r[dreg], m_r[TMR_TEMP1], m_r[sreg2]); |
| 3490 | | } |
| 3491 | | |
| 3492 | | void tms3203x_device::mpyf3_regind(UINT32 op) |
| 3493 | | { |
| 3494 | | UINT32 src2 = RMEM(INDIRECT_1(op, op)); |
| 3495 | | int sreg1 = (op >> 8) & 7; |
| 3496 | | int dreg = (op >> 16) & 7; |
| 3497 | | LONG2FP(TMR_TEMP2, src2); |
| 3498 | | mpyf(m_r[dreg], m_r[sreg1], m_r[TMR_TEMP2]); |
| 3499 | | } |
| 3500 | | |
| 3501 | | void tms3203x_device::mpyf3_indind(UINT32 op) |
| 3502 | | { |
| 3503 | | DECLARE_DEF; |
| 3504 | | UINT32 src1 = RMEM(INDIRECT_1_DEF(op, op >> 8)); |
| 3505 | | UINT32 src2 = RMEM(INDIRECT_1(op, op)); |
| 3506 | | int dreg = (op >> 16) & 7; |
| 3507 | | UPDATE_DEF(); |
| 3508 | | LONG2FP(TMR_TEMP1, src1); |
| 3509 | | LONG2FP(TMR_TEMP2, src2); |
| 3510 | | mpyf(m_r[dreg], m_r[TMR_TEMP1], m_r[TMR_TEMP2]); |
| 3511 | | } |
| 3512 | | |
| 3513 | | /*-----------------------------------------------------*/ |
| 3514 | | |
| 3515 | | void tms3203x_device::mpyi3_regreg(UINT32 op) |
| 3516 | | { |
| 3517 | | UINT32 src1 = IREG((op >> 8) & 31); |
| 3518 | | UINT32 src2 = IREG(op & 31); |
| 3519 | | int dreg = (op >> 16) & 31; |
| 3520 | | MPYI(dreg, src1, src2); |
| 3521 | | } |
| 3522 | | |
| 3523 | | void tms3203x_device::mpyi3_indreg(UINT32 op) |
| 3524 | | { |
| 3525 | | UINT32 src1 = RMEM(INDIRECT_1(op, op >> 8)); |
| 3526 | | UINT32 src2 = IREG(op & 31); |
| 3527 | | int dreg = (op >> 16) & 31; |
| 3528 | | MPYI(dreg, src1, src2); |
| 3529 | | } |
| 3530 | | |
| 3531 | | void tms3203x_device::mpyi3_regind(UINT32 op) |
| 3532 | | { |
| 3533 | | UINT32 src2 = RMEM(INDIRECT_1(op, op)); |
| 3534 | | UINT32 src1 = IREG((op >> 8) & 31); |
| 3535 | | int dreg = (op >> 16) & 31; |
| 3536 | | MPYI(dreg, src1, src2); |
| 3537 | | } |
| 3538 | | |
| 3539 | | void tms3203x_device::mpyi3_indind(UINT32 op) |
| 3540 | | { |
| 3541 | | DECLARE_DEF; |
| 3542 | | UINT32 src1 = RMEM(INDIRECT_1_DEF(op, op >> 8)); |
| 3543 | | UINT32 src2 = RMEM(INDIRECT_1(op, op)); |
| 3544 | | int dreg = (op >> 16) & 31; |
| 3545 | | UPDATE_DEF(); |
| 3546 | | MPYI(dreg, src1, src2); |
| 3547 | | } |
| 3548 | | |
| 3549 | | /*-----------------------------------------------------*/ |
| 3550 | | |
| 3551 | | void tms3203x_device::or3_regreg(UINT32 op) |
| 3552 | | { |
| 3553 | | UINT32 src1 = IREG((op >> 8) & 31); |
| 3554 | | UINT32 src2 = IREG(op & 31); |
| 3555 | | int dreg = (op >> 16) & 31; |
| 3556 | | OR(dreg, src1, src2); |
| 3557 | | } |
| 3558 | | |
| 3559 | | void tms3203x_device::or3_indreg(UINT32 op) |
| 3560 | | { |
| 3561 | | UINT32 src1 = RMEM(INDIRECT_1(op, op >> 8)); |
| 3562 | | UINT32 src2 = IREG(op & 31); |
| 3563 | | int dreg = (op >> 16) & 31; |
| 3564 | | OR(dreg, src1, src2); |
| 3565 | | } |
| 3566 | | |
| 3567 | | void tms3203x_device::or3_regind(UINT32 op) |
| 3568 | | { |
| 3569 | | UINT32 src2 = RMEM(INDIRECT_1(op, op)); |
| 3570 | | UINT32 src1 = IREG((op >> 8) & 31); |
| 3571 | | int dreg = (op >> 16) & 31; |
| 3572 | | OR(dreg, src1, src2); |
| 3573 | | } |
| 3574 | | |
| 3575 | | void tms3203x_device::or3_indind(UINT32 op) |
| 3576 | | { |
| 3577 | | DECLARE_DEF; |
| 3578 | | UINT32 src1 = RMEM(INDIRECT_1_DEF(op, op >> 8)); |
| 3579 | | UINT32 src2 = RMEM(INDIRECT_1(op, op)); |
| 3580 | | int dreg = (op >> 16) & 31; |
| 3581 | | UPDATE_DEF(); |
| 3582 | | OR(dreg, src1, src2); |
| 3583 | | } |
| 3584 | | |
| 3585 | | /*-----------------------------------------------------*/ |
| 3586 | | |
| 3587 | | void tms3203x_device::subb3_regreg(UINT32 op) |
| 3588 | | { |
| 3589 | | UINT32 src1 = IREG((op >> 8) & 31); |
| 3590 | | UINT32 src2 = IREG(op & 31); |
| 3591 | | int dreg = (op >> 16) & 31; |
| 3592 | | SUBB(dreg, src1, src2); |
| 3593 | | } |
| 3594 | | |
| 3595 | | void tms3203x_device::subb3_indreg(UINT32 op) |
| 3596 | | { |
| 3597 | | UINT32 src1 = RMEM(INDIRECT_1(op, op >> 8)); |
| 3598 | | UINT32 src2 = IREG(op & 31); |
| 3599 | | int dreg = (op >> 16) & 31; |
| 3600 | | SUBB(dreg, src1, src2); |
| 3601 | | } |
| 3602 | | |
| 3603 | | void tms3203x_device::subb3_regind(UINT32 op) |
| 3604 | | { |
| 3605 | | UINT32 src2 = RMEM(INDIRECT_1(op, op)); |
| 3606 | | UINT32 src1 = IREG((op >> 8) & 31); |
| 3607 | | int dreg = (op >> 16) & 31; |
| 3608 | | SUBB(dreg, src1, src2); |
| 3609 | | } |
| 3610 | | |
| 3611 | | void tms3203x_device::subb3_indind(UINT32 op) |
| 3612 | | { |
| 3613 | | DECLARE_DEF; |
| 3614 | | UINT32 src1 = RMEM(INDIRECT_1_DEF(op, op >> 8)); |
| 3615 | | UINT32 src2 = RMEM(INDIRECT_1(op, op)); |
| 3616 | | int dreg = (op >> 16) & 31; |
| 3617 | | UPDATE_DEF(); |
| 3618 | | SUBB(dreg, src1, src2); |
| 3619 | | } |
| 3620 | | |
| 3621 | | /*-----------------------------------------------------*/ |
| 3622 | | |
| 3623 | | void tms3203x_device::subf3_regreg(UINT32 op) |
| 3624 | | { |
| 3625 | | int sreg1 = (op >> 8) & 7; |
| 3626 | | int sreg2 = op & 7; |
| 3627 | | int dreg = (op >> 16) & 7; |
| 3628 | | subf(m_r[dreg], m_r[sreg1], m_r[sreg2]); |
| 3629 | | } |
| 3630 | | |
| 3631 | | void tms3203x_device::subf3_indreg(UINT32 op) |
| 3632 | | { |
| 3633 | | UINT32 src1 = RMEM(INDIRECT_1(op, op >> 8)); |
| 3634 | | int sreg2 = op & 7; |
| 3635 | | int dreg = (op >> 16) & 7; |
| 3636 | | LONG2FP(TMR_TEMP1, src1); |
| 3637 | | subf(m_r[dreg], m_r[TMR_TEMP1], m_r[sreg2]); |
| 3638 | | } |
| 3639 | | |
| 3640 | | void tms3203x_device::subf3_regind(UINT32 op) |
| 3641 | | { |
| 3642 | | UINT32 src2 = RMEM(INDIRECT_1(op, op)); |
| 3643 | | int sreg1 = (op >> 8) & 7; |
| 3644 | | int dreg = (op >> 16) & 7; |
| 3645 | | LONG2FP(TMR_TEMP2, src2); |
| 3646 | | subf(m_r[dreg], m_r[sreg1], m_r[TMR_TEMP2]); |
| 3647 | | } |
| 3648 | | |
| 3649 | | void tms3203x_device::subf3_indind(UINT32 op) |
| 3650 | | { |
| 3651 | | DECLARE_DEF; |
| 3652 | | UINT32 src1 = RMEM(INDIRECT_1_DEF(op, op >> 8)); |
| 3653 | | UINT32 src2 = RMEM(INDIRECT_1(op, op)); |
| 3654 | | int dreg = (op >> 16) & 7; |
| 3655 | | UPDATE_DEF(); |
| 3656 | | LONG2FP(TMR_TEMP1, src1); |
| 3657 | | LONG2FP(TMR_TEMP2, src2); |
| 3658 | | subf(m_r[dreg], m_r[TMR_TEMP1], m_r[TMR_TEMP2]); |
| 3659 | | } |
| 3660 | | |
| 3661 | | /*-----------------------------------------------------*/ |
| 3662 | | |
| 3663 | | void tms3203x_device::subi3_regreg(UINT32 op) |
| 3664 | | { |
| 3665 | | UINT32 src1 = IREG((op >> 8) & 31); |
| 3666 | | UINT32 src2 = IREG(op & 31); |
| 3667 | | int dreg = (op >> 16) & 31; |
| 3668 | | SUBI(dreg, src1, src2); |
| 3669 | | } |
| 3670 | | |
| 3671 | | void tms3203x_device::subi3_indreg(UINT32 op) |
| 3672 | | { |
| 3673 | | UINT32 src1 = RMEM(INDIRECT_1(op, op >> 8)); |
| 3674 | | UINT32 src2 = IREG(op & 31); |
| 3675 | | int dreg = (op >> 16) & 31; |
| 3676 | | SUBI(dreg, src1, src2); |
| 3677 | | } |
| 3678 | | |
| 3679 | | void tms3203x_device::subi3_regind(UINT32 op) |
| 3680 | | { |
| 3681 | | UINT32 src2 = RMEM(INDIRECT_1(op, op)); |
| 3682 | | UINT32 src1 = IREG((op >> 8) & 31); |
| 3683 | | int dreg = (op >> 16) & 31; |
| 3684 | | SUBI(dreg, src1, src2); |
| 3685 | | } |
| 3686 | | |
| 3687 | | void tms3203x_device::subi3_indind(UINT32 op) |
| 3688 | | { |
| 3689 | | DECLARE_DEF; |
| 3690 | | UINT32 src1 = RMEM(INDIRECT_1_DEF(op, op >> 8)); |
| 3691 | | UINT32 src2 = RMEM(INDIRECT_1(op, op)); |
| 3692 | | int dreg = (op >> 16) & 31; |
| 3693 | | UPDATE_DEF(); |
| 3694 | | SUBI(dreg, src1, src2); |
| 3695 | | } |
| 3696 | | |
| 3697 | | /*-----------------------------------------------------*/ |
| 3698 | | |
| 3699 | | void tms3203x_device::tstb3_regreg(UINT32 op) |
| 3700 | | { |
| 3701 | | UINT32 src1 = IREG((op >> 8) & 31); |
| 3702 | | UINT32 src2 = IREG(op & 31); |
| 3703 | | TSTB(src1, src2); |
| 3704 | | } |
| 3705 | | |
| 3706 | | void tms3203x_device::tstb3_indreg(UINT32 op) |
| 3707 | | { |
| 3708 | | UINT32 src1 = RMEM(INDIRECT_1(op, op >> 8)); |
| 3709 | | UINT32 src2 = IREG(op & 31); |
| 3710 | | TSTB(src1, src2); |
| 3711 | | } |
| 3712 | | |
| 3713 | | void tms3203x_device::tstb3_regind(UINT32 op) |
| 3714 | | { |
| 3715 | | UINT32 src2 = RMEM(INDIRECT_1(op, op)); |
| 3716 | | UINT32 src1 = IREG((op >> 8) & 31); |
| 3717 | | TSTB(src1, src2); |
| 3718 | | } |
| 3719 | | |
| 3720 | | void tms3203x_device::tstb3_indind(UINT32 op) |
| 3721 | | { |
| 3722 | | DECLARE_DEF; |
| 3723 | | UINT32 src1 = RMEM(INDIRECT_1_DEF(op, op >> 8)); |
| 3724 | | UINT32 src2 = RMEM(INDIRECT_1(op, op)); |
| 3725 | | UPDATE_DEF(); |
| 3726 | | TSTB(src1, src2); |
| 3727 | | } |
| 3728 | | |
| 3729 | | /*-----------------------------------------------------*/ |
| 3730 | | |
| 3731 | | void tms3203x_device::xor3_regreg(UINT32 op) |
| 3732 | | { |
| 3733 | | UINT32 src1 = IREG((op >> 8) & 31); |
| 3734 | | UINT32 src2 = IREG(op & 31); |
| 3735 | | int dreg = (op >> 16) & 31; |
| 3736 | | XOR(dreg, src1, src2); |
| 3737 | | } |
| 3738 | | |
| 3739 | | void tms3203x_device::xor3_indreg(UINT32 op) |
| 3740 | | { |
| 3741 | | UINT32 src1 = RMEM(INDIRECT_1(op, op >> 8)); |
| 3742 | | UINT32 src2 = IREG(op & 31); |
| 3743 | | int dreg = (op >> 16) & 31; |
| 3744 | | XOR(dreg, src1, src2); |
| 3745 | | } |
| 3746 | | |
| 3747 | | void tms3203x_device::xor3_regind(UINT32 op) |
| 3748 | | { |
| 3749 | | UINT32 src2 = RMEM(INDIRECT_1(op, op)); |
| 3750 | | UINT32 src1 = IREG((op >> 8) & 31); |
| 3751 | | int dreg = (op >> 16) & 31; |
| 3752 | | XOR(dreg, src1, src2); |
| 3753 | | } |
| 3754 | | |
| 3755 | | void tms3203x_device::xor3_indind(UINT32 op) |
| 3756 | | { |
| 3757 | | DECLARE_DEF; |
| 3758 | | UINT32 src1 = RMEM(INDIRECT_1_DEF(op, op >> 8)); |
| 3759 | | UINT32 src2 = RMEM(INDIRECT_1(op, op)); |
| 3760 | | int dreg = (op >> 16) & 31; |
| 3761 | | UPDATE_DEF(); |
| 3762 | | XOR(dreg, src1, src2); |
| 3763 | | } |
| 3764 | | |
| 3765 | | /*-----------------------------------------------------*/ |
| 3766 | | |
| 3767 | | void tms3203x_device::ldfu_reg(UINT32 op) |
| 3768 | | { |
| 3769 | | m_r[(op >> 16) & 7] = m_r[op & 7]; |
| 3770 | | } |
| 3771 | | |
| 3772 | | void tms3203x_device::ldfu_dir(UINT32 op) |
| 3773 | | { |
| 3774 | | UINT32 res = RMEM(DIRECT(op)); |
| 3775 | | int dreg = (op >> 16) & 7; |
| 3776 | | LONG2FP(dreg, res); |
| 3777 | | } |
| 3778 | | |
| 3779 | | void tms3203x_device::ldfu_ind(UINT32 op) |
| 3780 | | { |
| 3781 | | UINT32 res = RMEM(INDIRECT_D(op, op >> 8)); |
| 3782 | | int dreg = (op >> 16) & 7; |
| 3783 | | LONG2FP(dreg, res); |
| 3784 | | } |
| 3785 | | |
| 3786 | | void tms3203x_device::ldfu_imm(UINT32 op) |
| 3787 | | { |
| 3788 | | int dreg = (op >> 16) & 7; |
| 3789 | | SHORT2FP(dreg, op); |
| 3790 | | } |
| 3791 | | |
| 3792 | | /*-----------------------------------------------------*/ |
| 3793 | | |
| 3794 | | void tms3203x_device::ldflo_reg(UINT32 op) |
| 3795 | | { |
| 3796 | | if (CONDITION_LO()) |
| 3797 | | m_r[(op >> 16) & 7] = m_r[op & 7]; |
| 3798 | | } |
| 3799 | | |
| 3800 | | void tms3203x_device::ldflo_dir(UINT32 op) |
| 3801 | | { |
| 3802 | | if (CONDITION_LO()) |
| 3803 | | { |
| 3804 | | UINT32 res = RMEM(DIRECT(op)); |
| 3805 | | int dreg = (op >> 16) & 7; |
| 3806 | | LONG2FP(dreg, res); |
| 3807 | | } |
| 3808 | | } |
| 3809 | | |
| 3810 | | void tms3203x_device::ldflo_ind(UINT32 op) |
| 3811 | | { |
| 3812 | | if (CONDITION_LO()) |
| 3813 | | { |
| 3814 | | UINT32 res = RMEM(INDIRECT_D(op, op >> 8)); |
| 3815 | | int dreg = (op >> 16) & 7; |
| 3816 | | LONG2FP(dreg, res); |
| 3817 | | } |
| 3818 | | else |
| 3819 | | INDIRECT_D(op, op >> 8); |
| 3820 | | } |
| 3821 | | |
| 3822 | | void tms3203x_device::ldflo_imm(UINT32 op) |
| 3823 | | { |
| 3824 | | if (CONDITION_LO()) |
| 3825 | | { |
| 3826 | | int dreg = (op >> 16) & 7; |
| 3827 | | SHORT2FP(dreg, op); |
| 3828 | | } |
| 3829 | | } |
| 3830 | | |
| 3831 | | /*-----------------------------------------------------*/ |
| 3832 | | |
| 3833 | | void tms3203x_device::ldfls_reg(UINT32 op) |
| 3834 | | { |
| 3835 | | if (CONDITION_LS()) |
| 3836 | | m_r[(op >> 16) & 7] = m_r[op & 7]; |
| 3837 | | } |
| 3838 | | |
| 3839 | | void tms3203x_device::ldfls_dir(UINT32 op) |
| 3840 | | { |
| 3841 | | if (CONDITION_LS()) |
| 3842 | | { |
| 3843 | | UINT32 res = RMEM(DIRECT(op)); |
| 3844 | | int dreg = (op >> 16) & 7; |
| 3845 | | LONG2FP(dreg, res); |
| 3846 | | } |
| 3847 | | } |
| 3848 | | |
| 3849 | | void tms3203x_device::ldfls_ind(UINT32 op) |
| 3850 | | { |
| 3851 | | if (CONDITION_LS()) |
| 3852 | | { |
| 3853 | | UINT32 res = RMEM(INDIRECT_D(op, op >> 8)); |
| 3854 | | int dreg = (op >> 16) & 7; |
| 3855 | | LONG2FP(dreg, res); |
| 3856 | | } |
| 3857 | | else |
| 3858 | | INDIRECT_D(op, op >> 8); |
| 3859 | | } |
| 3860 | | |
| 3861 | | void tms3203x_device::ldfls_imm(UINT32 op) |
| 3862 | | { |
| 3863 | | if (CONDITION_LS()) |
| 3864 | | { |
| 3865 | | int dreg = (op >> 16) & 7; |
| 3866 | | SHORT2FP(dreg, op); |
| 3867 | | } |
| 3868 | | } |
| 3869 | | |
| 3870 | | /*-----------------------------------------------------*/ |
| 3871 | | |
| 3872 | | void tms3203x_device::ldfhi_reg(UINT32 op) |
| 3873 | | { |
| 3874 | | if (CONDITION_HI()) |
| 3875 | | m_r[(op >> 16) & 7] = m_r[op & 7]; |
| 3876 | | } |
| 3877 | | |
| 3878 | | void tms3203x_device::ldfhi_dir(UINT32 op) |
| 3879 | | { |
| 3880 | | if (CONDITION_HI()) |
| 3881 | | { |
| 3882 | | UINT32 res = RMEM(DIRECT(op)); |
| 3883 | | int dreg = (op >> 16) & 7; |
| 3884 | | LONG2FP(dreg, res); |
| 3885 | | } |
| 3886 | | } |
| 3887 | | |
| 3888 | | void tms3203x_device::ldfhi_ind(UINT32 op) |
| 3889 | | { |
| 3890 | | if (CONDITION_HI()) |
| 3891 | | { |
| 3892 | | UINT32 res = RMEM(INDIRECT_D(op, op >> 8)); |
| 3893 | | int dreg = (op >> 16) & 7; |
| 3894 | | LONG2FP(dreg, res); |
| 3895 | | } |
| 3896 | | else |
| 3897 | | INDIRECT_D(op, op >> 8); |
| 3898 | | } |
| 3899 | | |
| 3900 | | void tms3203x_device::ldfhi_imm(UINT32 op) |
| 3901 | | { |
| 3902 | | if (CONDITION_HI()) |
| 3903 | | { |
| 3904 | | int dreg = (op >> 16) & 7; |
| 3905 | | SHORT2FP(dreg, op); |
| 3906 | | } |
| 3907 | | } |
| 3908 | | |
| 3909 | | /*-----------------------------------------------------*/ |
| 3910 | | |
| 3911 | | void tms3203x_device::ldfhs_reg(UINT32 op) |
| 3912 | | { |
| 3913 | | if (CONDITION_HS()) |
| 3914 | | m_r[(op >> 16) & 7] = m_r[op & 7]; |
| 3915 | | } |
| 3916 | | |
| 3917 | | void tms3203x_device::ldfhs_dir(UINT32 op) |
| 3918 | | { |
| 3919 | | if (CONDITION_HS()) |
| 3920 | | { |
| 3921 | | UINT32 res = RMEM(DIRECT(op)); |
| 3922 | | int dreg = (op >> 16) & 7; |
| 3923 | | LONG2FP(dreg, res); |
| 3924 | | } |
| 3925 | | } |
| 3926 | | |
| 3927 | | void tms3203x_device::ldfhs_ind(UINT32 op) |
| 3928 | | { |
| 3929 | | if (CONDITION_HS()) |
| 3930 | | { |
| 3931 | | UINT32 res = RMEM(INDIRECT_D(op, op >> 8)); |
| 3932 | | int dreg = (op >> 16) & 7; |
| 3933 | | LONG2FP(dreg, res); |
| 3934 | | } |
| 3935 | | else |
| 3936 | | INDIRECT_D(op, op >> 8); |
| 3937 | | } |
| 3938 | | |
| 3939 | | void tms3203x_device::ldfhs_imm(UINT32 op) |
| 3940 | | { |
| 3941 | | if (CONDITION_HS()) |
| 3942 | | { |
| 3943 | | int dreg = (op >> 16) & 7; |
| 3944 | | SHORT2FP(dreg, op); |
| 3945 | | } |
| 3946 | | } |
| 3947 | | |
| 3948 | | /*-----------------------------------------------------*/ |
| 3949 | | |
| 3950 | | void tms3203x_device::ldfeq_reg(UINT32 op) |
| 3951 | | { |
| 3952 | | if (CONDITION_EQ()) |
| 3953 | | m_r[(op >> 16) & 7] = m_r[op & 7]; |
| 3954 | | } |
| 3955 | | |
| 3956 | | void tms3203x_device::ldfeq_dir(UINT32 op) |
| 3957 | | { |
| 3958 | | if (CONDITION_EQ()) |
| 3959 | | { |
| 3960 | | UINT32 res = RMEM(DIRECT(op)); |
| 3961 | | int dreg = (op >> 16) & 7; |
| 3962 | | LONG2FP(dreg, res); |
| 3963 | | } |
| 3964 | | } |
| 3965 | | |
| 3966 | | void tms3203x_device::ldfeq_ind(UINT32 op) |
| 3967 | | { |
| 3968 | | if (CONDITION_EQ()) |
| 3969 | | { |
| 3970 | | UINT32 res = RMEM(INDIRECT_D(op, op >> 8)); |
| 3971 | | int dreg = (op >> 16) & 7; |
| 3972 | | LONG2FP(dreg, res); |
| 3973 | | } |
| 3974 | | else |
| 3975 | | INDIRECT_D(op, op >> 8); |
| 3976 | | } |
| 3977 | | |
| 3978 | | void tms3203x_device::ldfeq_imm(UINT32 op) |
| 3979 | | { |
| 3980 | | if (CONDITION_EQ()) |
| 3981 | | { |
| 3982 | | int dreg = (op >> 16) & 7; |
| 3983 | | SHORT2FP(dreg, op); |
| 3984 | | } |
| 3985 | | } |
| 3986 | | |
| 3987 | | /*-----------------------------------------------------*/ |
| 3988 | | |
| 3989 | | void tms3203x_device::ldfne_reg(UINT32 op) |
| 3990 | | { |
| 3991 | | if (CONDITION_NE()) |
| 3992 | | m_r[(op >> 16) & 7] = m_r[op & 7]; |
| 3993 | | } |
| 3994 | | |
| 3995 | | void tms3203x_device::ldfne_dir(UINT32 op) |
| 3996 | | { |
| 3997 | | if (CONDITION_NE()) |
| 3998 | | { |
| 3999 | | UINT32 res = RMEM(DIRECT(op)); |
| 4000 | | int dreg = (op >> 16) & 7; |
| 4001 | | LONG2FP(dreg, res); |
| 4002 | | } |
| 4003 | | } |
| 4004 | | |
| 4005 | | void tms3203x_device::ldfne_ind(UINT32 op) |
| 4006 | | { |
| 4007 | | if (CONDITION_NE()) |
| 4008 | | { |
| 4009 | | UINT32 res = RMEM(INDIRECT_D(op, op >> 8)); |
| 4010 | | int dreg = (op >> 16) & 7; |
| 4011 | | LONG2FP(dreg, res); |
| 4012 | | } |
| 4013 | | else |
| 4014 | | INDIRECT_D(op, op >> 8); |
| 4015 | | } |
| 4016 | | |
| 4017 | | void tms3203x_device::ldfne_imm(UINT32 op) |
| 4018 | | { |
| 4019 | | if (CONDITION_NE()) |
| 4020 | | { |
| 4021 | | int dreg = (op >> 16) & 7; |
| 4022 | | SHORT2FP(dreg, op); |
| 4023 | | } |
| 4024 | | } |
| 4025 | | |
| 4026 | | /*-----------------------------------------------------*/ |
| 4027 | | |
| 4028 | | void tms3203x_device::ldflt_reg(UINT32 op) |
| 4029 | | { |
| 4030 | | if (CONDITION_LT()) |
| 4031 | | m_r[(op >> 16) & 7] = m_r[op & 7]; |
| 4032 | | } |
| 4033 | | |
| 4034 | | void tms3203x_device::ldflt_dir(UINT32 op) |
| 4035 | | { |
| 4036 | | if (CONDITION_LT()) |
| 4037 | | { |
| 4038 | | UINT32 res = RMEM(DIRECT(op)); |
| 4039 | | int dreg = (op >> 16) & 7; |
| 4040 | | LONG2FP(dreg, res); |
| 4041 | | } |
| 4042 | | } |
| 4043 | | |
| 4044 | | void tms3203x_device::ldflt_ind(UINT32 op) |
| 4045 | | { |
| 4046 | | if (CONDITION_LT()) |
| 4047 | | { |
| 4048 | | UINT32 res = RMEM(INDIRECT_D(op, op >> 8)); |
| 4049 | | int dreg = (op >> 16) & 7; |
| 4050 | | LONG2FP(dreg, res); |
| 4051 | | } |
| 4052 | | else |
| 4053 | | INDIRECT_D(op, op >> 8); |
| 4054 | | } |
| 4055 | | |
| 4056 | | void tms3203x_device::ldflt_imm(UINT32 op) |
| 4057 | | { |
| 4058 | | if (CONDITION_LT()) |
| 4059 | | { |
| 4060 | | int dreg = (op >> 16) & 7; |
| 4061 | | SHORT2FP(dreg, op); |
| 4062 | | } |
| 4063 | | } |
| 4064 | | |
| 4065 | | /*-----------------------------------------------------*/ |
| 4066 | | |
| 4067 | | void tms3203x_device::ldfle_reg(UINT32 op) |
| 4068 | | { |
| 4069 | | if (CONDITION_LE()) |
| 4070 | | m_r[(op >> 16) & 7] = m_r[op & 7]; |
| 4071 | | } |
| 4072 | | |
| 4073 | | void tms3203x_device::ldfle_dir(UINT32 op) |
| 4074 | | { |
| 4075 | | if (CONDITION_LE()) |
| 4076 | | { |
| 4077 | | UINT32 res = RMEM(DIRECT(op)); |
| 4078 | | int dreg = (op >> 16) & 7; |
| 4079 | | LONG2FP(dreg, res); |
| 4080 | | } |
| 4081 | | } |
| 4082 | | |
| 4083 | | void tms3203x_device::ldfle_ind(UINT32 op) |
| 4084 | | { |
| 4085 | | if (CONDITION_LE()) |
| 4086 | | { |
| 4087 | | UINT32 res = RMEM(INDIRECT_D(op, op >> 8)); |
| 4088 | | int dreg = (op >> 16) & 7; |
| 4089 | | LONG2FP(dreg, res); |
| 4090 | | } |
| 4091 | | else |
| 4092 | | INDIRECT_D(op, op >> 8); |
| 4093 | | } |
| 4094 | | |
| 4095 | | void tms3203x_device::ldfle_imm(UINT32 op) |
| 4096 | | { |
| 4097 | | if (CONDITION_LE()) |
| 4098 | | { |
| 4099 | | int dreg = (op >> 16) & 7; |
| 4100 | | SHORT2FP(dreg, op); |
| 4101 | | } |
| 4102 | | } |
| 4103 | | |
| 4104 | | /*-----------------------------------------------------*/ |
| 4105 | | |
| 4106 | | void tms3203x_device::ldfgt_reg(UINT32 op) |
| 4107 | | { |
| 4108 | | if (CONDITION_GT()) |
| 4109 | | m_r[(op >> 16) & 7] = m_r[op & 7]; |
| 4110 | | } |
| 4111 | | |
| 4112 | | void tms3203x_device::ldfgt_dir(UINT32 op) |
| 4113 | | { |
| 4114 | | if (CONDITION_GT()) |
| 4115 | | { |
| 4116 | | UINT32 res = RMEM(DIRECT(op)); |
| 4117 | | int dreg = (op >> 16) & 7; |
| 4118 | | LONG2FP(dreg, res); |
| 4119 | | } |
| 4120 | | } |
| 4121 | | |
| 4122 | | void tms3203x_device::ldfgt_ind(UINT32 op) |
| 4123 | | { |
| 4124 | | if (CONDITION_GT()) |
| 4125 | | { |
| 4126 | | UINT32 res = RMEM(INDIRECT_D(op, op >> 8)); |
| 4127 | | int dreg = (op >> 16) & 7; |
| 4128 | | LONG2FP(dreg, res); |
| 4129 | | } |
| 4130 | | else |
| 4131 | | INDIRECT_D(op, op >> 8); |
| 4132 | | } |
| 4133 | | |
| 4134 | | void tms3203x_device::ldfgt_imm(UINT32 op) |
| 4135 | | { |
| 4136 | | if (CONDITION_GT()) |
| 4137 | | { |
| 4138 | | int dreg = (op >> 16) & 7; |
| 4139 | | SHORT2FP(dreg, op); |
| 4140 | | } |
| 4141 | | } |
| 4142 | | |
| 4143 | | /*-----------------------------------------------------*/ |
| 4144 | | |
| 4145 | | void tms3203x_device::ldfge_reg(UINT32 op) |
| 4146 | | { |
| 4147 | | if (CONDITION_GE()) |
| 4148 | | m_r[(op >> 16) & 7] = m_r[op & 7]; |
| 4149 | | } |
| 4150 | | |
| 4151 | | void tms3203x_device::ldfge_dir(UINT32 op) |
| 4152 | | { |
| 4153 | | if (CONDITION_GE()) |
| 4154 | | { |
| 4155 | | UINT32 res = RMEM(DIRECT(op)); |
| 4156 | | int dreg = (op >> 16) & 7; |
| 4157 | | LONG2FP(dreg, res); |
| 4158 | | } |
| 4159 | | } |
| 4160 | | |
| 4161 | | void tms3203x_device::ldfge_ind(UINT32 op) |
| 4162 | | { |
| 4163 | | if (CONDITION_GE()) |
| 4164 | | { |
| 4165 | | UINT32 res = RMEM(INDIRECT_D(op, op >> 8)); |
| 4166 | | int dreg = (op >> 16) & 7; |
| 4167 | | LONG2FP(dreg, res); |
| 4168 | | } |
| 4169 | | else |
| 4170 | | INDIRECT_D(op, op >> 8); |
| 4171 | | } |
| 4172 | | |
| 4173 | | void tms3203x_device::ldfge_imm(UINT32 op) |
| 4174 | | { |
| 4175 | | if (CONDITION_GE()) |
| 4176 | | { |
| 4177 | | int dreg = (op >> 16) & 7; |
| 4178 | | SHORT2FP(dreg, op); |
| 4179 | | } |
| 4180 | | } |
| 4181 | | |
| 4182 | | /*-----------------------------------------------------*/ |
| 4183 | | |
| 4184 | | void tms3203x_device::ldfnv_reg(UINT32 op) |
| 4185 | | { |
| 4186 | | if (CONDITION_NV()) |
| 4187 | | m_r[(op >> 16) & 7] = m_r[op & 7]; |
| 4188 | | } |
| 4189 | | |
| 4190 | | void tms3203x_device::ldfnv_dir(UINT32 op) |
| 4191 | | { |
| 4192 | | if (CONDITION_NV()) |
| 4193 | | { |
| 4194 | | UINT32 res = RMEM(DIRECT(op)); |
| 4195 | | int dreg = (op >> 16) & 7; |
| 4196 | | LONG2FP(dreg, res); |
| 4197 | | } |
| 4198 | | } |
| 4199 | | |
| 4200 | | void tms3203x_device::ldfnv_ind(UINT32 op) |
| 4201 | | { |
| 4202 | | if (CONDITION_NV()) |
| 4203 | | { |
| 4204 | | UINT32 res = RMEM(INDIRECT_D(op, op >> 8)); |
| 4205 | | int dreg = (op >> 16) & 7; |
| 4206 | | LONG2FP(dreg, res); |
| 4207 | | } |
| 4208 | | else |
| 4209 | | INDIRECT_D(op, op >> 8); |
| 4210 | | } |
| 4211 | | |
| 4212 | | void tms3203x_device::ldfnv_imm(UINT32 op) |
| 4213 | | { |
| 4214 | | if (CONDITION_NV()) |
| 4215 | | { |
| 4216 | | int dreg = (op >> 16) & 7; |
| 4217 | | SHORT2FP(dreg, op); |
| 4218 | | } |
| 4219 | | } |
| 4220 | | |
| 4221 | | /*-----------------------------------------------------*/ |
| 4222 | | |
| 4223 | | void tms3203x_device::ldfv_reg(UINT32 op) |
| 4224 | | { |
| 4225 | | if (CONDITION_V()) |
| 4226 | | m_r[(op >> 16) & 7] = m_r[op & 7]; |
| 4227 | | } |
| 4228 | | |
| 4229 | | void tms3203x_device::ldfv_dir(UINT32 op) |
| 4230 | | { |
| 4231 | | if (CONDITION_V()) |
| 4232 | | { |
| 4233 | | UINT32 res = RMEM(DIRECT(op)); |
| 4234 | | int dreg = (op >> 16) & 7; |
| 4235 | | LONG2FP(dreg, res); |
| 4236 | | } |
| 4237 | | } |
| 4238 | | |
| 4239 | | void tms3203x_device::ldfv_ind(UINT32 op) |
| 4240 | | { |
| 4241 | | if (CONDITION_V()) |
| 4242 | | { |
| 4243 | | UINT32 res = RMEM(INDIRECT_D(op, op >> 8)); |
| 4244 | | int dreg = (op >> 16) & 7; |
| 4245 | | LONG2FP(dreg, res); |
| 4246 | | } |
| 4247 | | else |
| 4248 | | INDIRECT_D(op, op >> 8); |
| 4249 | | } |
| 4250 | | |
| 4251 | | void tms3203x_device::ldfv_imm(UINT32 op) |
| 4252 | | { |
| 4253 | | if (CONDITION_V()) |
| 4254 | | { |
| 4255 | | int dreg = (op >> 16) & 7; |
| 4256 | | SHORT2FP(dreg, op); |
| 4257 | | } |
| 4258 | | } |
| 4259 | | |
| 4260 | | /*-----------------------------------------------------*/ |
| 4261 | | |
| 4262 | | void tms3203x_device::ldfnuf_reg(UINT32 op) |
| 4263 | | { |
| 4264 | | if (CONDITION_NUF()) |
| 4265 | | m_r[(op >> 16) & 7] = m_r[op & 7]; |
| 4266 | | } |
| 4267 | | |
| 4268 | | void tms3203x_device::ldfnuf_dir(UINT32 op) |
| 4269 | | { |
| 4270 | | if (CONDITION_NUF()) |
| 4271 | | { |
| 4272 | | UINT32 res = RMEM(DIRECT(op)); |
| 4273 | | int dreg = (op >> 16) & 7; |
| 4274 | | LONG2FP(dreg, res); |
| 4275 | | } |
| 4276 | | } |
| 4277 | | |
| 4278 | | void tms3203x_device::ldfnuf_ind(UINT32 op) |
| 4279 | | { |
| 4280 | | if (CONDITION_NUF()) |
| 4281 | | { |
| 4282 | | UINT32 res = RMEM(INDIRECT_D(op, op >> 8)); |
| 4283 | | int dreg = (op >> 16) & 7; |
| 4284 | | LONG2FP(dreg, res); |
| 4285 | | } |
| 4286 | | else |
| 4287 | | INDIRECT_D(op, op >> 8); |
| 4288 | | } |
| 4289 | | |
| 4290 | | void tms3203x_device::ldfnuf_imm(UINT32 op) |
| 4291 | | { |
| 4292 | | if (CONDITION_NUF()) |
| 4293 | | { |
| 4294 | | int dreg = (op >> 16) & 7; |
| 4295 | | SHORT2FP(dreg, op); |
| 4296 | | } |
| 4297 | | } |
| 4298 | | |
| 4299 | | /*-----------------------------------------------------*/ |
| 4300 | | |
| 4301 | | void tms3203x_device::ldfuf_reg(UINT32 op) |
| 4302 | | { |
| 4303 | | if (CONDITION_UF()) |
| 4304 | | m_r[(op >> 16) & 7] = m_r[op & 7]; |
| 4305 | | } |
| 4306 | | |
| 4307 | | void tms3203x_device::ldfuf_dir(UINT32 op) |
| 4308 | | { |
| 4309 | | if (CONDITION_UF()) |
| 4310 | | { |
| 4311 | | UINT32 res = RMEM(DIRECT(op)); |
| 4312 | | int dreg = (op >> 16) & 7; |
| 4313 | | LONG2FP(dreg, res); |
| 4314 | | } |
| 4315 | | } |
| 4316 | | |
| 4317 | | void tms3203x_device::ldfuf_ind(UINT32 op) |
| 4318 | | { |
| 4319 | | if (CONDITION_UF()) |
| 4320 | | { |
| 4321 | | UINT32 res = RMEM(INDIRECT_D(op, op >> 8)); |
| 4322 | | int dreg = (op >> 16) & 7; |
| 4323 | | LONG2FP(dreg, res); |
| 4324 | | } |
| 4325 | | else |
| 4326 | | INDIRECT_D(op, op >> 8); |
| 4327 | | } |
| 4328 | | |
| 4329 | | void tms3203x_device::ldfuf_imm(UINT32 op) |
| 4330 | | { |
| 4331 | | if (CONDITION_UF()) |
| 4332 | | { |
| 4333 | | int dreg = (op >> 16) & 7; |
| 4334 | | SHORT2FP(dreg, op); |
| 4335 | | } |
| 4336 | | } |
| 4337 | | |
| 4338 | | /*-----------------------------------------------------*/ |
| 4339 | | |
| 4340 | | void tms3203x_device::ldfnlv_reg(UINT32 op) |
| 4341 | | { |
| 4342 | | if (CONDITION_NLV()) |
| 4343 | | m_r[(op >> 16) & 7] = m_r[op & 7]; |
| 4344 | | } |
| 4345 | | |
| 4346 | | void tms3203x_device::ldfnlv_dir(UINT32 op) |
| 4347 | | { |
| 4348 | | if (CONDITION_NLV()) |
| 4349 | | { |
| 4350 | | UINT32 res = RMEM(DIRECT(op)); |
| 4351 | | int dreg = (op >> 16) & 7; |
| 4352 | | LONG2FP(dreg, res); |
| 4353 | | } |
| 4354 | | } |
| 4355 | | |
| 4356 | | void tms3203x_device::ldfnlv_ind(UINT32 op) |
| 4357 | | { |
| 4358 | | if (CONDITION_NLV()) |
| 4359 | | { |
| 4360 | | UINT32 res = RMEM(INDIRECT_D(op, op >> 8)); |
| 4361 | | int dreg = (op >> 16) & 7; |
| 4362 | | LONG2FP(dreg, res); |
| 4363 | | } |
| 4364 | | else |
| 4365 | | INDIRECT_D(op, op >> 8); |
| 4366 | | } |
| 4367 | | |
| 4368 | | void tms3203x_device::ldfnlv_imm(UINT32 op) |
| 4369 | | { |
| 4370 | | if (CONDITION_NLV()) |
| 4371 | | { |
| 4372 | | int dreg = (op >> 16) & 7; |
| 4373 | | SHORT2FP(dreg, op); |
| 4374 | | } |
| 4375 | | } |
| 4376 | | |
| 4377 | | /*-----------------------------------------------------*/ |
| 4378 | | |
| 4379 | | void tms3203x_device::ldflv_reg(UINT32 op) |
| 4380 | | { |
| 4381 | | if (CONDITION_LV()) |
| 4382 | | m_r[(op >> 16) & 7] = m_r[op & 7]; |
| 4383 | | } |
| 4384 | | |
| 4385 | | void tms3203x_device::ldflv_dir(UINT32 op) |
| 4386 | | { |
| 4387 | | if (CONDITION_LV()) |
| 4388 | | { |
| 4389 | | UINT32 res = RMEM(DIRECT(op)); |
| 4390 | | int dreg = (op >> 16) & 7; |
| 4391 | | LONG2FP(dreg, res); |
| 4392 | | } |
| 4393 | | } |
| 4394 | | |
| 4395 | | void tms3203x_device::ldflv_ind(UINT32 op) |
| 4396 | | { |
| 4397 | | if (CONDITION_LV()) |
| 4398 | | { |
| 4399 | | UINT32 res = RMEM(INDIRECT_D(op, op >> 8)); |
| 4400 | | int dreg = (op >> 16) & 7; |
| 4401 | | LONG2FP(dreg, res); |
| 4402 | | } |
| 4403 | | else |
| 4404 | | INDIRECT_D(op, op >> 8); |
| 4405 | | } |
| 4406 | | |
| 4407 | | void tms3203x_device::ldflv_imm(UINT32 op) |
| 4408 | | { |
| 4409 | | if (CONDITION_LV()) |
| 4410 | | { |
| 4411 | | int dreg = (op >> 16) & 7; |
| 4412 | | SHORT2FP(dreg, op); |
| 4413 | | } |
| 4414 | | } |
| 4415 | | |
| 4416 | | /*-----------------------------------------------------*/ |
| 4417 | | |
| 4418 | | void tms3203x_device::ldfnluf_reg(UINT32 op) |
| 4419 | | { |
| 4420 | | if (CONDITION_NLUF()) |
| 4421 | | m_r[(op >> 16) & 7] = m_r[op & 7]; |
| 4422 | | } |
| 4423 | | |
| 4424 | | void tms3203x_device::ldfnluf_dir(UINT32 op) |
| 4425 | | { |
| 4426 | | if (CONDITION_NLUF()) |
| 4427 | | { |
| 4428 | | UINT32 res = RMEM(DIRECT(op)); |
| 4429 | | int dreg = (op >> 16) & 7; |
| 4430 | | LONG2FP(dreg, res); |
| 4431 | | } |
| 4432 | | } |
| 4433 | | |
| 4434 | | void tms3203x_device::ldfnluf_ind(UINT32 op) |
| 4435 | | { |
| 4436 | | if (CONDITION_NLUF()) |
| 4437 | | { |
| 4438 | | UINT32 res = RMEM(INDIRECT_D(op, op >> 8)); |
| 4439 | | int dreg = (op >> 16) & 7; |
| 4440 | | LONG2FP(dreg, res); |
| 4441 | | } |
| 4442 | | else |
| 4443 | | INDIRECT_D(op, op >> 8); |
| 4444 | | } |
| 4445 | | |
| 4446 | | void tms3203x_device::ldfnluf_imm(UINT32 op) |
| 4447 | | { |
| 4448 | | if (CONDITION_NLUF()) |
| 4449 | | { |
| 4450 | | int dreg = (op >> 16) & 7; |
| 4451 | | SHORT2FP(dreg, op); |
| 4452 | | } |
| 4453 | | } |
| 4454 | | |
| 4455 | | /*-----------------------------------------------------*/ |
| 4456 | | |
| 4457 | | void tms3203x_device::ldfluf_reg(UINT32 op) |
| 4458 | | { |
| 4459 | | if (CONDITION_LUF()) |
| 4460 | | m_r[(op >> 16) & 7] = m_r[op & 7]; |
| 4461 | | } |
| 4462 | | |
| 4463 | | void tms3203x_device::ldfluf_dir(UINT32 op) |
| 4464 | | { |
| 4465 | | if (CONDITION_LUF()) |
| 4466 | | { |
| 4467 | | UINT32 res = RMEM(DIRECT(op)); |
| 4468 | | int dreg = (op >> 16) & 7; |
| 4469 | | LONG2FP(dreg, res); |
| 4470 | | } |
| 4471 | | } |
| 4472 | | |
| 4473 | | void tms3203x_device::ldfluf_ind(UINT32 op) |
| 4474 | | { |
| 4475 | | if (CONDITION_LUF()) |
| 4476 | | { |
| 4477 | | UINT32 res = RMEM(INDIRECT_D(op, op >> 8)); |
| 4478 | | int dreg = (op >> 16) & 7; |
| 4479 | | LONG2FP(dreg, res); |
| 4480 | | } |
| 4481 | | else |
| 4482 | | INDIRECT_D(op, op >> 8); |
| 4483 | | } |
| 4484 | | |
| 4485 | | void tms3203x_device::ldfluf_imm(UINT32 op) |
| 4486 | | { |
| 4487 | | if (CONDITION_LUF()) |
| 4488 | | { |
| 4489 | | int dreg = (op >> 16) & 7; |
| 4490 | | SHORT2FP(dreg, op); |
| 4491 | | } |
| 4492 | | } |
| 4493 | | |
| 4494 | | /*-----------------------------------------------------*/ |
| 4495 | | |
| 4496 | | void tms3203x_device::ldfzuf_reg(UINT32 op) |
| 4497 | | { |
| 4498 | | if (CONDITION_ZUF()) |
| 4499 | | m_r[(op >> 16) & 7] = m_r[op & 7]; |
| 4500 | | } |
| 4501 | | |
| 4502 | | void tms3203x_device::ldfzuf_dir(UINT32 op) |
| 4503 | | { |
| 4504 | | if (CONDITION_ZUF()) |
| 4505 | | { |
| 4506 | | UINT32 res = RMEM(DIRECT(op)); |
| 4507 | | int dreg = (op >> 16) & 7; |
| 4508 | | LONG2FP(dreg, res); |
| 4509 | | } |
| 4510 | | } |
| 4511 | | |
| 4512 | | void tms3203x_device::ldfzuf_ind(UINT32 op) |
| 4513 | | { |
| 4514 | | if (CONDITION_ZUF()) |
| 4515 | | { |
| 4516 | | UINT32 res = RMEM(INDIRECT_D(op, op >> 8)); |
| 4517 | | int dreg = (op >> 16) & 7; |
| 4518 | | LONG2FP(dreg, res); |
| 4519 | | } |
| 4520 | | else |
| 4521 | | INDIRECT_D(op, op >> 8); |
| 4522 | | } |
| 4523 | | |
| 4524 | | void tms3203x_device::ldfzuf_imm(UINT32 op) |
| 4525 | | { |
| 4526 | | if (CONDITION_ZUF()) |
| 4527 | | { |
| 4528 | | int dreg = (op >> 16) & 7; |
| 4529 | | SHORT2FP(dreg, op); |
| 4530 | | } |
| 4531 | | } |
| 4532 | | |
| 4533 | | /*-----------------------------------------------------*/ |
| 4534 | | |
| 4535 | | void tms3203x_device::ldiu_reg(UINT32 op) |
| 4536 | | { |
| 4537 | | int dreg = (op >> 16) & 31; |
| 4538 | | IREG(dreg) = IREG(op & 31); |
| 4539 | | if (dreg >= TMR_BK) |
| 4540 | | update_special(dreg); |
| 4541 | | } |
| 4542 | | |
| 4543 | | void tms3203x_device::ldiu_dir(UINT32 op) |
| 4544 | | { |
| 4545 | | int dreg = (op >> 16) & 31; |
| 4546 | | IREG(dreg) = RMEM(DIRECT(op)); |
| 4547 | | if (dreg >= TMR_BK) |
| 4548 | | update_special(dreg); |
| 4549 | | } |
| 4550 | | |
| 4551 | | void tms3203x_device::ldiu_ind(UINT32 op) |
| 4552 | | { |
| 4553 | | int dreg = (op >> 16) & 31; |
| 4554 | | IREG(dreg) = RMEM(INDIRECT_D(op, op >> 8)); |
| 4555 | | if (dreg >= TMR_BK) |
| 4556 | | update_special(dreg); |
| 4557 | | } |
| 4558 | | |
| 4559 | | void tms3203x_device::ldiu_imm(UINT32 op) |
| 4560 | | { |
| 4561 | | int dreg = (op >> 16) & 31; |
| 4562 | | IREG(dreg) = (INT16)op; |
| 4563 | | if (dreg >= TMR_BK) |
| 4564 | | update_special(dreg); |
| 4565 | | } |
| 4566 | | |
| 4567 | | /*-----------------------------------------------------*/ |
| 4568 | | |
| 4569 | | void tms3203x_device::ldilo_reg(UINT32 op) |
| 4570 | | { |
| 4571 | | if (CONDITION_LO()) |
| 4572 | | { |
| 4573 | | int dreg = (op >> 16) & 31; |
| 4574 | | IREG(dreg) = IREG(op & 31); |
| 4575 | | if (dreg >= TMR_BK) |
| 4576 | | update_special(dreg); |
| 4577 | | } |
| 4578 | | } |
| 4579 | | |
| 4580 | | void tms3203x_device::ldilo_dir(UINT32 op) |
| 4581 | | { |
| 4582 | | UINT32 val = RMEM(DIRECT(op)); |
| 4583 | | if (CONDITION_LO()) |
| 4584 | | { |
| 4585 | | int dreg = (op >> 16) & 31; |
| 4586 | | IREG(dreg) = val; |
| 4587 | | if (dreg >= TMR_BK) |
| 4588 | | update_special(dreg); |
| 4589 | | } |
| 4590 | | } |
| 4591 | | |
| 4592 | | void tms3203x_device::ldilo_ind(UINT32 op) |
| 4593 | | { |
| 4594 | | UINT32 val = RMEM(INDIRECT_D(op, op >> 8)); |
| 4595 | | if (CONDITION_LO()) |
| 4596 | | { |
| 4597 | | int dreg = (op >> 16) & 31; |
| 4598 | | IREG(dreg) = val; |
| 4599 | | if (dreg >= TMR_BK) |
| 4600 | | update_special(dreg); |
| 4601 | | } |
| 4602 | | } |
| 4603 | | |
| 4604 | | void tms3203x_device::ldilo_imm(UINT32 op) |
| 4605 | | { |
| 4606 | | if (CONDITION_LO()) |
| 4607 | | { |
| 4608 | | int dreg = (op >> 16) & 31; |
| 4609 | | IREG(dreg) = (INT16)op; |
| 4610 | | if (dreg >= TMR_BK) |
| 4611 | | update_special(dreg); |
| 4612 | | } |
| 4613 | | } |
| 4614 | | |
| 4615 | | /*-----------------------------------------------------*/ |
| 4616 | | |
| 4617 | | void tms3203x_device::ldils_reg(UINT32 op) |
| 4618 | | { |
| 4619 | | if (CONDITION_LS()) |
| 4620 | | { |
| 4621 | | int dreg = (op >> 16) & 31; |
| 4622 | | IREG(dreg) = IREG(op & 31); |
| 4623 | | if (dreg >= TMR_BK) |
| 4624 | | update_special(dreg); |
| 4625 | | } |
| 4626 | | } |
| 4627 | | |
| 4628 | | void tms3203x_device::ldils_dir(UINT32 op) |
| 4629 | | { |
| 4630 | | UINT32 val = RMEM(DIRECT(op)); |
| 4631 | | if (CONDITION_LS()) |
| 4632 | | { |
| 4633 | | int dreg = (op >> 16) & 31; |
| 4634 | | IREG(dreg) = val; |
| 4635 | | if (dreg >= TMR_BK) |
| 4636 | | update_special(dreg); |
| 4637 | | } |
| 4638 | | } |
| 4639 | | |
| 4640 | | void tms3203x_device::ldils_ind(UINT32 op) |
| 4641 | | { |
| 4642 | | UINT32 val = RMEM(INDIRECT_D(op, op >> 8)); |
| 4643 | | if (CONDITION_LS()) |
| 4644 | | { |
| 4645 | | int dreg = (op >> 16) & 31; |
| 4646 | | IREG(dreg) = val; |
| 4647 | | if (dreg >= TMR_BK) |
| 4648 | | update_special(dreg); |
| 4649 | | } |
| 4650 | | } |
| 4651 | | |
| 4652 | | void tms3203x_device::ldils_imm(UINT32 op) |
| 4653 | | { |
| 4654 | | if (CONDITION_LS()) |
| 4655 | | { |
| 4656 | | int dreg = (op >> 16) & 31; |
| 4657 | | IREG(dreg) = (INT16)op; |
| 4658 | | if (dreg >= TMR_BK) |
| 4659 | | update_special(dreg); |
| 4660 | | } |
| 4661 | | } |
| 4662 | | |
| 4663 | | /*-----------------------------------------------------*/ |
| 4664 | | |
| 4665 | | void tms3203x_device::ldihi_reg(UINT32 op) |
| 4666 | | { |
| 4667 | | if (CONDITION_HI()) |
| 4668 | | { |
| 4669 | | int dreg = (op >> 16) & 31; |
| 4670 | | IREG(dreg) = IREG(op & 31); |
| 4671 | | if (dreg >= TMR_BK) |
| 4672 | | update_special(dreg); |
| 4673 | | } |
| 4674 | | } |
| 4675 | | |
| 4676 | | void tms3203x_device::ldihi_dir(UINT32 op) |
| 4677 | | { |
| 4678 | | UINT32 val = RMEM(DIRECT(op)); |
| 4679 | | if (CONDITION_HI()) |
| 4680 | | { |
| 4681 | | int dreg = (op >> 16) & 31; |
| 4682 | | IREG(dreg) = val; |
| 4683 | | if (dreg >= TMR_BK) |
| 4684 | | update_special(dreg); |
| 4685 | | } |
| 4686 | | } |
| 4687 | | |
| 4688 | | void tms3203x_device::ldihi_ind(UINT32 op) |
| 4689 | | { |
| 4690 | | UINT32 val = RMEM(INDIRECT_D(op, op >> 8)); |
| 4691 | | if (CONDITION_HI()) |
| 4692 | | { |
| 4693 | | int dreg = (op >> 16) & 31; |
| 4694 | | IREG(dreg) = val; |
| 4695 | | if (dreg >= TMR_BK) |
| 4696 | | update_special(dreg); |
| 4697 | | } |
| 4698 | | } |
| 4699 | | |
| 4700 | | void tms3203x_device::ldihi_imm(UINT32 op) |
| 4701 | | { |
| 4702 | | if (CONDITION_HI()) |
| 4703 | | { |
| 4704 | | int dreg = (op >> 16) & 31; |
| 4705 | | IREG(dreg) = (INT16)op; |
| 4706 | | if (dreg >= TMR_BK) |
| 4707 | | update_special(dreg); |
| 4708 | | } |
| 4709 | | } |
| 4710 | | |
| 4711 | | /*-----------------------------------------------------*/ |
| 4712 | | |
| 4713 | | void tms3203x_device::ldihs_reg(UINT32 op) |
| 4714 | | { |
| 4715 | | if (CONDITION_HS()) |
| 4716 | | { |
| 4717 | | int dreg = (op >> 16) & 31; |
| 4718 | | IREG(dreg) = IREG(op & 31); |
| 4719 | | if (dreg >= TMR_BK) |
| 4720 | | update_special(dreg); |
| 4721 | | } |
| 4722 | | } |
| 4723 | | |
| 4724 | | void tms3203x_device::ldihs_dir(UINT32 op) |
| 4725 | | { |
| 4726 | | UINT32 val = RMEM(DIRECT(op)); |
| 4727 | | if (CONDITION_HS()) |
| 4728 | | { |
| 4729 | | int dreg = (op >> 16) & 31; |
| 4730 | | IREG(dreg) = val; |
| 4731 | | if (dreg >= TMR_BK) |
| 4732 | | update_special(dreg); |
| 4733 | | } |
| 4734 | | } |
| 4735 | | |
| 4736 | | void tms3203x_device::ldihs_ind(UINT32 op) |
| 4737 | | { |
| 4738 | | UINT32 val = RMEM(INDIRECT_D(op, op >> 8)); |
| 4739 | | if (CONDITION_HS()) |
| 4740 | | { |
| 4741 | | int dreg = (op >> 16) & 31; |
| 4742 | | IREG(dreg) = val; |
| 4743 | | if (dreg >= TMR_BK) |
| 4744 | | update_special(dreg); |
| 4745 | | } |
| 4746 | | } |
| 4747 | | |
| 4748 | | void tms3203x_device::ldihs_imm(UINT32 op) |
| 4749 | | { |
| 4750 | | if (CONDITION_HS()) |
| 4751 | | { |
| 4752 | | int dreg = (op >> 16) & 31; |
| 4753 | | IREG(dreg) = (INT16)op; |
| 4754 | | if (dreg >= TMR_BK) |
| 4755 | | update_special(dreg); |
| 4756 | | } |
| 4757 | | } |
| 4758 | | |
| 4759 | | /*-----------------------------------------------------*/ |
| 4760 | | |
| 4761 | | void tms3203x_device::ldieq_reg(UINT32 op) |
| 4762 | | { |
| 4763 | | if (CONDITION_EQ()) |
| 4764 | | { |
| 4765 | | int dreg = (op >> 16) & 31; |
| 4766 | | IREG(dreg) = IREG(op & 31); |
| 4767 | | if (dreg >= TMR_BK) |
| 4768 | | update_special(dreg); |
| 4769 | | } |
| 4770 | | } |
| 4771 | | |
| 4772 | | void tms3203x_device::ldieq_dir(UINT32 op) |
| 4773 | | { |
| 4774 | | UINT32 val = RMEM(DIRECT(op)); |
| 4775 | | if (CONDITION_EQ()) |
| 4776 | | { |
| 4777 | | int dreg = (op >> 16) & 31; |
| 4778 | | IREG(dreg) = val; |
| 4779 | | if (dreg >= TMR_BK) |
| 4780 | | update_special(dreg); |
| 4781 | | } |
| 4782 | | } |
| 4783 | | |
| 4784 | | void tms3203x_device::ldieq_ind(UINT32 op) |
| 4785 | | { |
| 4786 | | UINT32 val = RMEM(INDIRECT_D(op, op >> 8)); |
| 4787 | | if (CONDITION_EQ()) |
| 4788 | | { |
| 4789 | | int dreg = (op >> 16) & 31; |
| 4790 | | IREG(dreg) = val; |
| 4791 | | if (dreg >= TMR_BK) |
| 4792 | | update_special(dreg); |
| 4793 | | } |
| 4794 | | } |
| 4795 | | |
| 4796 | | void tms3203x_device::ldieq_imm(UINT32 op) |
| 4797 | | { |
| 4798 | | if (CONDITION_EQ()) |
| 4799 | | { |
| 4800 | | int dreg = (op >> 16) & 31; |
| 4801 | | IREG(dreg) = (INT16)op; |
| 4802 | | if (dreg >= TMR_BK) |
| 4803 | | update_special(dreg); |
| 4804 | | } |
| 4805 | | } |
| 4806 | | |
| 4807 | | /*-----------------------------------------------------*/ |
| 4808 | | |
| 4809 | | void tms3203x_device::ldine_reg(UINT32 op) |
| 4810 | | { |
| 4811 | | if (CONDITION_NE()) |
| 4812 | | { |
| 4813 | | int dreg = (op >> 16) & 31; |
| 4814 | | IREG(dreg) = IREG(op & 31); |
| 4815 | | if (dreg >= TMR_BK) |
| 4816 | | update_special(dreg); |
| 4817 | | } |
| 4818 | | } |
| 4819 | | |
| 4820 | | void tms3203x_device::ldine_dir(UINT32 op) |
| 4821 | | { |
| 4822 | | UINT32 val = RMEM(DIRECT(op)); |
| 4823 | | if (CONDITION_NE()) |
| 4824 | | { |
| 4825 | | int dreg = (op >> 16) & 31; |
| 4826 | | IREG(dreg) = val; |
| 4827 | | if (dreg >= TMR_BK) |
| 4828 | | update_special(dreg); |
| 4829 | | } |
| 4830 | | } |
| 4831 | | |
| 4832 | | void tms3203x_device::ldine_ind(UINT32 op) |
| 4833 | | { |
| 4834 | | UINT32 val = RMEM(INDIRECT_D(op, op >> 8)); |
| 4835 | | if (CONDITION_NE()) |
| 4836 | | { |
| 4837 | | int dreg = (op >> 16) & 31; |
| 4838 | | IREG(dreg) = val; |
| 4839 | | if (dreg >= TMR_BK) |
| 4840 | | update_special(dreg); |
| 4841 | | } |
| 4842 | | } |
| 4843 | | |
| 4844 | | void tms3203x_device::ldine_imm(UINT32 op) |
| 4845 | | { |
| 4846 | | if (CONDITION_NE()) |
| 4847 | | { |
| 4848 | | int dreg = (op >> 16) & 31; |
| 4849 | | IREG(dreg) = (INT16)op; |
| 4850 | | if (dreg >= TMR_BK) |
| 4851 | | update_special(dreg); |
| 4852 | | } |
| 4853 | | } |
| 4854 | | |
| 4855 | | /*-----------------------------------------------------*/ |
| 4856 | | |
| 4857 | | void tms3203x_device::ldilt_reg(UINT32 op) |
| 4858 | | { |
| 4859 | | if (CONDITION_LT()) |
| 4860 | | { |
| 4861 | | int dreg = (op >> 16) & 31; |
| 4862 | | IREG(dreg) = IREG(op & 31); |
| 4863 | | if (dreg >= TMR_BK) |
| 4864 | | update_special(dreg); |
| 4865 | | } |
| 4866 | | } |
| 4867 | | |
| 4868 | | void tms3203x_device::ldilt_dir(UINT32 op) |
| 4869 | | { |
| 4870 | | UINT32 val = RMEM(DIRECT(op)); |
| 4871 | | if (CONDITION_LT()) |
| 4872 | | { |
| 4873 | | int dreg = (op >> 16) & 31; |
| 4874 | | IREG(dreg) = val; |
| 4875 | | if (dreg >= TMR_BK) |
| 4876 | | update_special(dreg); |
| 4877 | | } |
| 4878 | | } |
| 4879 | | |
| 4880 | | void tms3203x_device::ldilt_ind(UINT32 op) |
| 4881 | | { |
| 4882 | | UINT32 val = RMEM(INDIRECT_D(op, op >> 8)); |
| 4883 | | if (CONDITION_LT()) |
| 4884 | | { |
| 4885 | | int dreg = (op >> 16) & 31; |
| 4886 | | IREG(dreg) = val; |
| 4887 | | if (dreg >= TMR_BK) |
| 4888 | | update_special(dreg); |
| 4889 | | } |
| 4890 | | } |
| 4891 | | |
| 4892 | | void tms3203x_device::ldilt_imm(UINT32 op) |
| 4893 | | { |
| 4894 | | if (CONDITION_LT()) |
| 4895 | | { |
| 4896 | | int dreg = (op >> 16) & 31; |
| 4897 | | IREG(dreg) = (INT16)op; |
| 4898 | | if (dreg >= TMR_BK) |
| 4899 | | update_special(dreg); |
| 4900 | | } |
| 4901 | | } |
| 4902 | | |
| 4903 | | /*-----------------------------------------------------*/ |
| 4904 | | |
| 4905 | | void tms3203x_device::ldile_reg(UINT32 op) |
| 4906 | | { |
| 4907 | | if (CONDITION_LE()) |
| 4908 | | { |
| 4909 | | int dreg = (op >> 16) & 31; |
| 4910 | | IREG(dreg) = IREG(op & 31); |
| 4911 | | if (dreg >= TMR_BK) |
| 4912 | | update_special(dreg); |
| 4913 | | } |
| 4914 | | } |
| 4915 | | |
| 4916 | | void tms3203x_device::ldile_dir(UINT32 op) |
| 4917 | | { |
| 4918 | | UINT32 val = RMEM(DIRECT(op)); |
| 4919 | | if (CONDITION_LE()) |
| 4920 | | { |
| 4921 | | int dreg = (op >> 16) & 31; |
| 4922 | | IREG(dreg) = val; |
| 4923 | | if (dreg >= TMR_BK) |
| 4924 | | update_special(dreg); |
| 4925 | | } |
| 4926 | | } |
| 4927 | | |
| 4928 | | void tms3203x_device::ldile_ind(UINT32 op) |
| 4929 | | { |
| 4930 | | UINT32 val = RMEM(INDIRECT_D(op, op >> 8)); |
| 4931 | | if (CONDITION_LE()) |
| 4932 | | { |
| 4933 | | int dreg = (op >> 16) & 31; |
| 4934 | | IREG(dreg) = val; |
| 4935 | | if (dreg >= TMR_BK) |
| 4936 | | update_special(dreg); |
| 4937 | | } |
| 4938 | | } |
| 4939 | | |
| 4940 | | void tms3203x_device::ldile_imm(UINT32 op) |
| 4941 | | { |
| 4942 | | if (CONDITION_LE()) |
| 4943 | | { |
| 4944 | | int dreg = (op >> 16) & 31; |
| 4945 | | IREG(dreg) = (INT16)op; |
| 4946 | | if (dreg >= TMR_BK) |
| 4947 | | update_special(dreg); |
| 4948 | | } |
| 4949 | | } |
| 4950 | | |
| 4951 | | /*-----------------------------------------------------*/ |
| 4952 | | |
| 4953 | | void tms3203x_device::ldigt_reg(UINT32 op) |
| 4954 | | { |
| 4955 | | if (CONDITION_GT()) |
| 4956 | | { |
| 4957 | | int dreg = (op >> 16) & 31; |
| 4958 | | IREG(dreg) = IREG(op & 31); |
| 4959 | | if (dreg >= TMR_BK) |
| 4960 | | update_special(dreg); |
| 4961 | | } |
| 4962 | | } |
| 4963 | | |
| 4964 | | void tms3203x_device::ldigt_dir(UINT32 op) |
| 4965 | | { |
| 4966 | | UINT32 val = RMEM(DIRECT(op)); |
| 4967 | | if (CONDITION_GT()) |
| 4968 | | { |
| 4969 | | int dreg = (op >> 16) & 31; |
| 4970 | | IREG(dreg) = val; |
| 4971 | | if (dreg >= TMR_BK) |
| 4972 | | update_special(dreg); |
| 4973 | | } |
| 4974 | | } |
| 4975 | | |
| 4976 | | void tms3203x_device::ldigt_ind(UINT32 op) |
| 4977 | | { |
| 4978 | | UINT32 val = RMEM(INDIRECT_D(op, op >> 8)); |
| 4979 | | if (CONDITION_GT()) |
| 4980 | | { |
| 4981 | | int dreg = (op >> 16) & 31; |
| 4982 | | IREG(dreg) = val; |
| 4983 | | if (dreg >= TMR_BK) |
| 4984 | | update_special(dreg); |
| 4985 | | } |
| 4986 | | } |
| 4987 | | |
| 4988 | | void tms3203x_device::ldigt_imm(UINT32 op) |
| 4989 | | { |
| 4990 | | if (CONDITION_GT()) |
| 4991 | | { |
| 4992 | | int dreg = (op >> 16) & 31; |
| 4993 | | IREG(dreg) = (INT16)op; |
| 4994 | | if (dreg >= TMR_BK) |
| 4995 | | update_special(dreg); |
| 4996 | | } |
| 4997 | | } |
| 4998 | | |
| 4999 | | /*-----------------------------------------------------*/ |
| 5000 | | |
| 5001 | | void tms3203x_device::ldige_reg(UINT32 op) |
| 5002 | | { |
| 5003 | | if (CONDITION_GE()) |
| 5004 | | { |
| 5005 | | int dreg = (op >> 16) & 31; |
| 5006 | | IREG(dreg) = IREG(op & 31); |
| 5007 | | if (dreg >= TMR_BK) |
| 5008 | | update_special(dreg); |
| 5009 | | } |
| 5010 | | } |
| 5011 | | |
| 5012 | | void tms3203x_device::ldige_dir(UINT32 op) |
| 5013 | | { |
| 5014 | | UINT32 val = RMEM(DIRECT(op)); |
| 5015 | | if (CONDITION_GE()) |
| 5016 | | { |
| 5017 | | int dreg = (op >> 16) & 31; |
| 5018 | | IREG(dreg) = val; |
| 5019 | | if (dreg >= TMR_BK) |
| 5020 | | update_special(dreg); |
| 5021 | | } |
| 5022 | | } |
| 5023 | | |
| 5024 | | void tms3203x_device::ldige_ind(UINT32 op) |
| 5025 | | { |
| 5026 | | UINT32 val = RMEM(INDIRECT_D(op, op >> 8)); |
| 5027 | | if (CONDITION_GE()) |
| 5028 | | { |
| 5029 | | int dreg = (op >> 16) & 31; |
| 5030 | | IREG(dreg) = val; |
| 5031 | | if (dreg >= TMR_BK) |
| 5032 | | update_special(dreg); |
| 5033 | | } |
| 5034 | | } |
| 5035 | | |
| 5036 | | void tms3203x_device::ldige_imm(UINT32 op) |
| 5037 | | { |
| 5038 | | if (CONDITION_GE()) |
| 5039 | | { |
| 5040 | | int dreg = (op >> 16) & 31; |
| 5041 | | IREG(dreg) = (INT16)op; |
| 5042 | | if (dreg >= TMR_BK) |
| 5043 | | update_special(dreg); |
| 5044 | | } |
| 5045 | | } |
| 5046 | | |
| 5047 | | /*-----------------------------------------------------*/ |
| 5048 | | |
| 5049 | | void tms3203x_device::ldinv_reg(UINT32 op) |
| 5050 | | { |
| 5051 | | if (CONDITION_NV()) |
| 5052 | | { |
| 5053 | | int dreg = (op >> 16) & 31; |
| 5054 | | IREG(dreg) = IREG(op & 31); |
| 5055 | | if (dreg >= TMR_BK) |
| 5056 | | update_special(dreg); |
| 5057 | | } |
| 5058 | | } |
| 5059 | | |
| 5060 | | void tms3203x_device::ldinv_dir(UINT32 op) |
| 5061 | | { |
| 5062 | | UINT32 val = RMEM(DIRECT(op)); |
| 5063 | | if (CONDITION_NV()) |
| 5064 | | { |
| 5065 | | int dreg = (op >> 16) & 31; |
| 5066 | | IREG(dreg) = val; |
| 5067 | | if (dreg >= TMR_BK) |
| 5068 | | update_special(dreg); |
| 5069 | | } |
| 5070 | | } |
| 5071 | | |
| 5072 | | void tms3203x_device::ldinv_ind(UINT32 op) |
| 5073 | | { |
| 5074 | | UINT32 val = RMEM(INDIRECT_D(op, op >> 8)); |
| 5075 | | if (CONDITION_NV()) |
| 5076 | | { |
| 5077 | | int dreg = (op >> 16) & 31; |
| 5078 | | IREG(dreg) = val; |
| 5079 | | if (dreg >= TMR_BK) |
| 5080 | | update_special(dreg); |
| 5081 | | } |
| 5082 | | } |
| 5083 | | |
| 5084 | | void tms3203x_device::ldinv_imm(UINT32 op) |
| 5085 | | { |
| 5086 | | if (CONDITION_NV()) |
| 5087 | | { |
| 5088 | | int dreg = (op >> 16) & 31; |
| 5089 | | IREG(dreg) = (INT16)op; |
| 5090 | | if (dreg >= TMR_BK) |
| 5091 | | update_special(dreg); |
| 5092 | | } |
| 5093 | | } |
| 5094 | | |
| 5095 | | /*-----------------------------------------------------*/ |
| 5096 | | |
| 5097 | | void tms3203x_device::ldiuf_reg(UINT32 op) |
| 5098 | | { |
| 5099 | | if (CONDITION_UF()) |
| 5100 | | { |
| 5101 | | int dreg = (op >> 16) & 31; |
| 5102 | | IREG(dreg) = IREG(op & 31); |
| 5103 | | if (dreg >= TMR_BK) |
| 5104 | | update_special(dreg); |
| 5105 | | } |
| 5106 | | } |
| 5107 | | |
| 5108 | | void tms3203x_device::ldiuf_dir(UINT32 op) |
| 5109 | | { |
| 5110 | | UINT32 val = RMEM(DIRECT(op)); |
| 5111 | | if (CONDITION_UF()) |
| 5112 | | { |
| 5113 | | int dreg = (op >> 16) & 31; |
| 5114 | | IREG(dreg) = val; |
| 5115 | | if (dreg >= TMR_BK) |
| 5116 | | update_special(dreg); |
| 5117 | | } |
| 5118 | | } |
| 5119 | | |
| 5120 | | void tms3203x_device::ldiuf_ind(UINT32 op) |
| 5121 | | { |
| 5122 | | UINT32 val = RMEM(INDIRECT_D(op, op >> 8)); |
| 5123 | | if (CONDITION_UF()) |
| 5124 | | { |
| 5125 | | int dreg = (op >> 16) & 31; |
| 5126 | | IREG(dreg) = val; |
| 5127 | | if (dreg >= TMR_BK) |
| 5128 | | update_special(dreg); |
| 5129 | | } |
| 5130 | | } |
| 5131 | | |
| 5132 | | void tms3203x_device::ldiuf_imm(UINT32 op) |
| 5133 | | { |
| 5134 | | if (CONDITION_UF()) |
| 5135 | | { |
| 5136 | | int dreg = (op >> 16) & 31; |
| 5137 | | IREG(dreg) = (INT16)op; |
| 5138 | | if (dreg >= TMR_BK) |
| 5139 | | update_special(dreg); |
| 5140 | | } |
| 5141 | | } |
| 5142 | | |
| 5143 | | /*-----------------------------------------------------*/ |
| 5144 | | |
| 5145 | | void tms3203x_device::ldinuf_reg(UINT32 op) |
| 5146 | | { |
| 5147 | | if (CONDITION_NUF()) |
| 5148 | | { |
| 5149 | | int dreg = (op >> 16) & 31; |
| 5150 | | IREG(dreg) = IREG(op & 31); |
| 5151 | | if (dreg >= TMR_BK) |
| 5152 | | update_special(dreg); |
| 5153 | | } |
| 5154 | | } |
| 5155 | | |
| 5156 | | void tms3203x_device::ldinuf_dir(UINT32 op) |
| 5157 | | { |
| 5158 | | UINT32 val = RMEM(DIRECT(op)); |
| 5159 | | if (CONDITION_NUF()) |
| 5160 | | { |
| 5161 | | int dreg = (op >> 16) & 31; |
| 5162 | | IREG(dreg) = val; |
| 5163 | | if (dreg >= TMR_BK) |
| 5164 | | update_special(dreg); |
| 5165 | | } |
| 5166 | | } |
| 5167 | | |
| 5168 | | void tms3203x_device::ldinuf_ind(UINT32 op) |
| 5169 | | { |
| 5170 | | UINT32 val = RMEM(INDIRECT_D(op, op >> 8)); |
| 5171 | | if (CONDITION_NUF()) |
| 5172 | | { |
| 5173 | | int dreg = (op >> 16) & 31; |
| 5174 | | IREG(dreg) = val; |
| 5175 | | if (dreg >= TMR_BK) |
| 5176 | | update_special(dreg); |
| 5177 | | } |
| 5178 | | } |
| 5179 | | |
| 5180 | | void tms3203x_device::ldinuf_imm(UINT32 op) |
| 5181 | | { |
| 5182 | | if (CONDITION_NUF()) |
| 5183 | | { |
| 5184 | | int dreg = (op >> 16) & 31; |
| 5185 | | IREG(dreg) = (INT16)op; |
| 5186 | | if (dreg >= TMR_BK) |
| 5187 | | update_special(dreg); |
| 5188 | | } |
| 5189 | | } |
| 5190 | | |
| 5191 | | /*-----------------------------------------------------*/ |
| 5192 | | |
| 5193 | | void tms3203x_device::ldiv_reg(UINT32 op) |
| 5194 | | { |
| 5195 | | if (CONDITION_V()) |
| 5196 | | { |
| 5197 | | int dreg = (op >> 16) & 31; |
| 5198 | | IREG(dreg) = IREG(op & 31); |
| 5199 | | if (dreg >= TMR_BK) |
| 5200 | | update_special(dreg); |
| 5201 | | } |
| 5202 | | } |
| 5203 | | |
| 5204 | | void tms3203x_device::ldiv_dir(UINT32 op) |
| 5205 | | { |
| 5206 | | UINT32 val = RMEM(DIRECT(op)); |
| 5207 | | if (CONDITION_V()) |
| 5208 | | { |
| 5209 | | int dreg = (op >> 16) & 31; |
| 5210 | | IREG(dreg) = val; |
| 5211 | | if (dreg >= TMR_BK) |
| 5212 | | update_special(dreg); |
| 5213 | | } |
| 5214 | | } |
| 5215 | | |
| 5216 | | void tms3203x_device::ldiv_ind(UINT32 op) |
| 5217 | | { |
| 5218 | | UINT32 val = RMEM(INDIRECT_D(op, op >> 8)); |
| 5219 | | if (CONDITION_V()) |
| 5220 | | { |
| 5221 | | int dreg = (op >> 16) & 31; |
| 5222 | | IREG(dreg) = val; |
| 5223 | | if (dreg >= TMR_BK) |
| 5224 | | update_special(dreg); |
| 5225 | | } |
| 5226 | | } |
| 5227 | | |
| 5228 | | void tms3203x_device::ldiv_imm(UINT32 op) |
| 5229 | | { |
| 5230 | | if (CONDITION_V()) |
| 5231 | | { |
| 5232 | | int dreg = (op >> 16) & 31; |
| 5233 | | IREG(dreg) = (INT16)op; |
| 5234 | | if (dreg >= TMR_BK) |
| 5235 | | update_special(dreg); |
| 5236 | | } |
| 5237 | | } |
| 5238 | | |
| 5239 | | /*-----------------------------------------------------*/ |
| 5240 | | |
| 5241 | | void tms3203x_device::ldinlv_reg(UINT32 op) |
| 5242 | | { |
| 5243 | | if (CONDITION_NLV()) |
| 5244 | | { |
| 5245 | | int dreg = (op >> 16) & 31; |
| 5246 | | IREG(dreg) = IREG(op & 31); |
| 5247 | | if (dreg >= TMR_BK) |
| 5248 | | update_special(dreg); |
| 5249 | | } |
| 5250 | | } |
| 5251 | | |
| 5252 | | void tms3203x_device::ldinlv_dir(UINT32 op) |
| 5253 | | { |
| 5254 | | UINT32 val = RMEM(DIRECT(op)); |
| 5255 | | if (CONDITION_NLV()) |
| 5256 | | { |
| 5257 | | int dreg = (op >> 16) & 31; |
| 5258 | | IREG(dreg) = val; |
| 5259 | | if (dreg >= TMR_BK) |
| 5260 | | update_special(dreg); |
| 5261 | | } |
| 5262 | | } |
| 5263 | | |
| 5264 | | void tms3203x_device::ldinlv_ind(UINT32 op) |
| 5265 | | { |
| 5266 | | UINT32 val = RMEM(INDIRECT_D(op, op >> 8)); |
| 5267 | | if (CONDITION_NLV()) |
| 5268 | | { |
| 5269 | | int dreg = (op >> 16) & 31; |
| 5270 | | IREG(dreg) = val; |
| 5271 | | if (dreg >= TMR_BK) |
| 5272 | | update_special(dreg); |
| 5273 | | } |
| 5274 | | } |
| 5275 | | |
| 5276 | | void tms3203x_device::ldinlv_imm(UINT32 op) |
| 5277 | | { |
| 5278 | | if (CONDITION_NLV()) |
| 5279 | | { |
| 5280 | | int dreg = (op >> 16) & 31; |
| 5281 | | IREG(dreg) = (INT16)op; |
| 5282 | | if (dreg >= TMR_BK) |
| 5283 | | update_special(dreg); |
| 5284 | | } |
| 5285 | | } |
| 5286 | | |
| 5287 | | /*-----------------------------------------------------*/ |
| 5288 | | |
| 5289 | | void tms3203x_device::ldilv_reg(UINT32 op) |
| 5290 | | { |
| 5291 | | if (CONDITION_LV()) |
| 5292 | | { |
| 5293 | | int dreg = (op >> 16) & 31; |
| 5294 | | IREG(dreg) = IREG(op & 31); |
| 5295 | | if (dreg >= TMR_BK) |
| 5296 | | update_special(dreg); |
| 5297 | | } |
| 5298 | | } |
| 5299 | | |
| 5300 | | void tms3203x_device::ldilv_dir(UINT32 op) |
| 5301 | | { |
| 5302 | | UINT32 val = RMEM(DIRECT(op)); |
| 5303 | | if (CONDITION_LV()) |
| 5304 | | { |
| 5305 | | int dreg = (op >> 16) & 31; |
| 5306 | | IREG(dreg) = val; |
| 5307 | | if (dreg >= TMR_BK) |
| 5308 | | update_special(dreg); |
| 5309 | | } |
| 5310 | | } |
| 5311 | | |
| 5312 | | void tms3203x_device::ldilv_ind(UINT32 op) |
| 5313 | | { |
| 5314 | | UINT32 val = RMEM(INDIRECT_D(op, op >> 8)); |
| 5315 | | if (CONDITION_LV()) |
| 5316 | | { |
| 5317 | | int dreg = (op >> 16) & 31; |
| 5318 | | IREG(dreg) = val; |
| 5319 | | if (dreg >= TMR_BK) |
| 5320 | | update_special(dreg); |
| 5321 | | } |
| 5322 | | } |
| 5323 | | |
| 5324 | | void tms3203x_device::ldilv_imm(UINT32 op) |
| 5325 | | { |
| 5326 | | if (CONDITION_LV()) |
| 5327 | | { |
| 5328 | | int dreg = (op >> 16) & 31; |
| 5329 | | IREG(dreg) = (INT16)op; |
| 5330 | | if (dreg >= TMR_BK) |
| 5331 | | update_special(dreg); |
| 5332 | | } |
| 5333 | | } |
| 5334 | | |
| 5335 | | /*-----------------------------------------------------*/ |
| 5336 | | |
| 5337 | | void tms3203x_device::ldinluf_reg(UINT32 op) |
| 5338 | | { |
| 5339 | | if (CONDITION_NLUF()) |
| 5340 | | { |
| 5341 | | int dreg = (op >> 16) & 31; |
| 5342 | | IREG(dreg) = IREG(op & 31); |
| 5343 | | if (dreg >= TMR_BK) |
| 5344 | | update_special(dreg); |
| 5345 | | } |
| 5346 | | } |
| 5347 | | |
| 5348 | | void tms3203x_device::ldinluf_dir(UINT32 op) |
| 5349 | | { |
| 5350 | | UINT32 val = RMEM(DIRECT(op)); |
| 5351 | | if (CONDITION_NLUF()) |
| 5352 | | { |
| 5353 | | int dreg = (op >> 16) & 31; |
| 5354 | | IREG(dreg) = val; |
| 5355 | | if (dreg >= TMR_BK) |
| 5356 | | update_special(dreg); |
| 5357 | | } |
| 5358 | | } |
| 5359 | | |
| 5360 | | void tms3203x_device::ldinluf_ind(UINT32 op) |
| 5361 | | { |
| 5362 | | UINT32 val = RMEM(INDIRECT_D(op, op >> 8)); |
| 5363 | | if (CONDITION_NLUF()) |
| 5364 | | { |
| 5365 | | int dreg = (op >> 16) & 31; |
| 5366 | | IREG(dreg) = val; |
| 5367 | | if (dreg >= TMR_BK) |
| 5368 | | update_special(dreg); |
| 5369 | | } |
| 5370 | | } |
| 5371 | | |
| 5372 | | void tms3203x_device::ldinluf_imm(UINT32 op) |
| 5373 | | { |
| 5374 | | if (CONDITION_NLUF()) |
| 5375 | | { |
| 5376 | | int dreg = (op >> 16) & 31; |
| 5377 | | IREG(dreg) = (INT16)op; |
| 5378 | | if (dreg >= TMR_BK) |
| 5379 | | update_special(dreg); |
| 5380 | | } |
| 5381 | | } |
| 5382 | | |
| 5383 | | /*-----------------------------------------------------*/ |
| 5384 | | |
| 5385 | | void tms3203x_device::ldiluf_reg(UINT32 op) |
| 5386 | | { |
| 5387 | | if (CONDITION_LUF()) |
| 5388 | | { |
| 5389 | | int dreg = (op >> 16) & 31; |
| 5390 | | IREG(dreg) = IREG(op & 31); |
| 5391 | | if (dreg >= TMR_BK) |
| 5392 | | update_special(dreg); |
| 5393 | | } |
| 5394 | | } |
| 5395 | | |
| 5396 | | void tms3203x_device::ldiluf_dir(UINT32 op) |
| 5397 | | { |
| 5398 | | UINT32 val = RMEM(DIRECT(op)); |
| 5399 | | if (CONDITION_LUF()) |
| 5400 | | { |
| 5401 | | int dreg = (op >> 16) & 31; |
| 5402 | | IREG(dreg) = val; |
| 5403 | | if (dreg >= TMR_BK) |
| 5404 | | update_special(dreg); |
| 5405 | | } |
| 5406 | | } |
| 5407 | | |
| 5408 | | void tms3203x_device::ldiluf_ind(UINT32 op) |
| 5409 | | { |
| 5410 | | UINT32 val = RMEM(INDIRECT_D(op, op >> 8)); |
| 5411 | | if (CONDITION_LUF()) |
| 5412 | | { |
| 5413 | | int dreg = (op >> 16) & 31; |
| 5414 | | IREG(dreg) = val; |
| 5415 | | if (dreg >= TMR_BK) |
| 5416 | | update_special(dreg); |
| 5417 | | } |
| 5418 | | } |
| 5419 | | |
| 5420 | | void tms3203x_device::ldiluf_imm(UINT32 op) |
| 5421 | | { |
| 5422 | | if (CONDITION_LUF()) |
| 5423 | | { |
| 5424 | | int dreg = (op >> 16) & 31; |
| 5425 | | IREG(dreg) = (INT16)op; |
| 5426 | | if (dreg >= TMR_BK) |
| 5427 | | update_special(dreg); |
| 5428 | | } |
| 5429 | | } |
| 5430 | | |
| 5431 | | /*-----------------------------------------------------*/ |
| 5432 | | |
| 5433 | | void tms3203x_device::ldizuf_reg(UINT32 op) |
| 5434 | | { |
| 5435 | | if (CONDITION_ZUF()) |
| 5436 | | { |
| 5437 | | int dreg = (op >> 16) & 31; |
| 5438 | | IREG(dreg) = IREG(op & 31); |
| 5439 | | if (dreg >= TMR_BK) |
| 5440 | | update_special(dreg); |
| 5441 | | } |
| 5442 | | } |
| 5443 | | |
| 5444 | | void tms3203x_device::ldizuf_dir(UINT32 op) |
| 5445 | | { |
| 5446 | | UINT32 val = RMEM(DIRECT(op)); |
| 5447 | | if (CONDITION_ZUF()) |
| 5448 | | { |
| 5449 | | int dreg = (op >> 16) & 31; |
| 5450 | | IREG(dreg) = val; |
| 5451 | | if (dreg >= TMR_BK) |
| 5452 | | update_special(dreg); |
| 5453 | | } |
| 5454 | | } |
| 5455 | | |
| 5456 | | void tms3203x_device::ldizuf_ind(UINT32 op) |
| 5457 | | { |
| 5458 | | UINT32 val = RMEM(INDIRECT_D(op, op >> 8)); |
| 5459 | | if (CONDITION_ZUF()) |
| 5460 | | { |
| 5461 | | int dreg = (op >> 16) & 31; |
| 5462 | | IREG(dreg) = val; |
| 5463 | | if (dreg >= TMR_BK) |
| 5464 | | update_special(dreg); |
| 5465 | | } |
| 5466 | | } |
| 5467 | | |
| 5468 | | void tms3203x_device::ldizuf_imm(UINT32 op) |
| 5469 | | { |
| 5470 | | if (CONDITION_ZUF()) |
| 5471 | | { |
| 5472 | | int dreg = (op >> 16) & 31; |
| 5473 | | IREG(dreg) = (INT16)op; |
| 5474 | | if (dreg >= TMR_BK) |
| 5475 | | update_special(dreg); |
| 5476 | | } |
| 5477 | | } |
| 5478 | | |
| 5479 | | /*-----------------------------------------------------*/ |
| 5480 | | |
| 5481 | | inline void tms3203x_device::execute_delayed(UINT32 newpc) |
| 5482 | | { |
| 5483 | | m_delayed = true; |
| 5484 | | |
| 5485 | | if ((machine().debug_flags & DEBUG_FLAG_ENABLED) == 0) |
| 5486 | | { |
| 5487 | | execute_one(); |
| 5488 | | execute_one(); |
| 5489 | | execute_one(); |
| 5490 | | } |
| 5491 | | else |
| 5492 | | { |
| 5493 | | debugger_instruction_hook(this, m_pc); |
| 5494 | | execute_one(); |
| 5495 | | debugger_instruction_hook(this, m_pc); |
| 5496 | | execute_one(); |
| 5497 | | debugger_instruction_hook(this, m_pc); |
| 5498 | | execute_one(); |
| 5499 | | } |
| 5500 | | |
| 5501 | | if (newpc != ~0) |
| 5502 | | m_pc = newpc; |
| 5503 | | |
| 5504 | | m_delayed = false; |
| 5505 | | if (m_irq_pending) |
| 5506 | | { |
| 5507 | | m_irq_pending = false; |
| 5508 | | check_irqs(); |
| 5509 | | } |
| 5510 | | } |
| 5511 | | |
| 5512 | | /*-----------------------------------------------------*/ |
| 5513 | | |
| 5514 | | void tms3203x_device::br_imm(UINT32 op) |
| 5515 | | { |
| 5516 | | m_pc = op & 0xffffff; |
| 5517 | | m_icount -= 3*2; |
| 5518 | | } |
| 5519 | | |
| 5520 | | void tms3203x_device::brd_imm(UINT32 op) |
| 5521 | | { |
| 5522 | | execute_delayed(op & 0xffffff); |
| 5523 | | } |
| 5524 | | |
| 5525 | | /*-----------------------------------------------------*/ |
| 5526 | | |
| 5527 | | void tms3203x_device::call_imm(UINT32 op) |
| 5528 | | { |
| 5529 | | WMEM(++IREG(TMR_SP), m_pc); |
| 5530 | | m_pc = op & 0xffffff; |
| 5531 | | m_icount -= 3*2; |
| 5532 | | } |
| 5533 | | |
| 5534 | | /*-----------------------------------------------------*/ |
| 5535 | | |
| 5536 | | void tms3203x_device::rptb_imm(UINT32 op) |
| 5537 | | { |
| 5538 | | IREG(TMR_RS) = m_pc; |
| 5539 | | IREG(TMR_RE) = op & 0xffffff; |
| 5540 | | IREG(TMR_ST) |= RMFLAG; |
| 5541 | | m_icount -= 3*2; |
| 5542 | | } |
| 5543 | | |
| 5544 | | /*-----------------------------------------------------*/ |
| 5545 | | |
| 5546 | | void tms3203x_device::swi(UINT32 op) { unimplemented(op); } |
| 5547 | | |
| 5548 | | /*-----------------------------------------------------*/ |
| 5549 | | |
| 5550 | | void tms3203x_device::brc_reg(UINT32 op) |
| 5551 | | { |
| 5552 | | if (condition(op >> 16)) |
| 5553 | | { |
| 5554 | | m_pc = IREG(op & 31); |
| 5555 | | m_icount -= 3*2; |
| 5556 | | } |
| 5557 | | } |
| 5558 | | |
| 5559 | | void tms3203x_device::brcd_reg(UINT32 op) |
| 5560 | | { |
| 5561 | | if (condition(op >> 16)) |
| 5562 | | execute_delayed(IREG(op & 31)); |
| 5563 | | else |
| 5564 | | execute_delayed(~0); |
| 5565 | | } |
| 5566 | | |
| 5567 | | void tms3203x_device::brc_imm(UINT32 op) |
| 5568 | | { |
| 5569 | | if (condition(op >> 16)) |
| 5570 | | { |
| 5571 | | m_pc += (INT16)op; |
| 5572 | | m_icount -= 3*2; |
| 5573 | | } |
| 5574 | | } |
| 5575 | | |
| 5576 | | void tms3203x_device::brcd_imm(UINT32 op) |
| 5577 | | { |
| 5578 | | if (condition(op >> 16)) |
| 5579 | | execute_delayed(m_pc + 2 + (INT16)op); |
| 5580 | | else |
| 5581 | | execute_delayed(~0); |
| 5582 | | } |
| 5583 | | |
| 5584 | | /*-----------------------------------------------------*/ |
| 5585 | | |
| 5586 | | void tms3203x_device::dbc_reg(UINT32 op) |
| 5587 | | { |
| 5588 | | int reg = TMR_AR0 + ((op >> 22) & 7); |
| 5589 | | int res = (IREG(reg) - 1) & 0xffffff; |
| 5590 | | IREG(reg) = res | (IREG(reg) & 0xff000000); |
| 5591 | | if (condition(op >> 16) && !(res & 0x800000)) |
| 5592 | | { |
| 5593 | | m_pc = IREG(op & 31); |
| 5594 | | m_icount -= 3*2; |
| 5595 | | } |
| 5596 | | } |
| 5597 | | |
| 5598 | | void tms3203x_device::dbcd_reg(UINT32 op) |
| 5599 | | { |
| 5600 | | int reg = TMR_AR0 + ((op >> 22) & 7); |
| 5601 | | int res = (IREG(reg) - 1) & 0xffffff; |
| 5602 | | IREG(reg) = res | (IREG(reg) & 0xff000000); |
| 5603 | | if (condition(op >> 16) && !(res & 0x800000)) |
| 5604 | | execute_delayed(IREG(op & 31)); |
| 5605 | | else |
| 5606 | | execute_delayed(~0); |
| 5607 | | } |
| 5608 | | |
| 5609 | | void tms3203x_device::dbc_imm(UINT32 op) |
| 5610 | | { |
| 5611 | | int reg = TMR_AR0 + ((op >> 22) & 7); |
| 5612 | | int res = (IREG(reg) - 1) & 0xffffff; |
| 5613 | | IREG(reg) = res | (IREG(reg) & 0xff000000); |
| 5614 | | if (condition(op >> 16) && !(res & 0x800000)) |
| 5615 | | { |
| 5616 | | m_pc += (INT16)op; |
| 5617 | | m_icount -= 3*2; |
| 5618 | | } |
| 5619 | | } |
| 5620 | | |
| 5621 | | void tms3203x_device::dbcd_imm(UINT32 op) |
| 5622 | | { |
| 5623 | | int reg = TMR_AR0 + ((op >> 22) & 7); |
| 5624 | | int res = (IREG(reg) - 1) & 0xffffff; |
| 5625 | | IREG(reg) = res | (IREG(reg) & 0xff000000); |
| 5626 | | if (condition(op >> 16) && !(res & 0x800000)) |
| 5627 | | execute_delayed(m_pc + 2 + (INT16)op); |
| 5628 | | else |
| 5629 | | execute_delayed(~0); |
| 5630 | | } |
| 5631 | | |
| 5632 | | /*-----------------------------------------------------*/ |
| 5633 | | |
| 5634 | | void tms3203x_device::callc_reg(UINT32 op) |
| 5635 | | { |
| 5636 | | if (condition(op >> 16)) |
| 5637 | | { |
| 5638 | | WMEM(++IREG(TMR_SP), m_pc); |
| 5639 | | m_pc = IREG(op & 31); |
| 5640 | | m_icount -= 3*2; |
| 5641 | | } |
| 5642 | | } |
| 5643 | | |
| 5644 | | void tms3203x_device::callc_imm(UINT32 op) |
| 5645 | | { |
| 5646 | | if (condition(op >> 16)) |
| 5647 | | { |
| 5648 | | WMEM(++IREG(TMR_SP), m_pc); |
| 5649 | | m_pc += (INT16)op; |
| 5650 | | m_icount -= 3*2; |
| 5651 | | } |
| 5652 | | } |
| 5653 | | |
| 5654 | | /*-----------------------------------------------------*/ |
| 5655 | | |
| 5656 | | void tms3203x_device::trap(int trapnum) |
| 5657 | | { |
| 5658 | | WMEM(++IREG(TMR_SP), m_pc); |
| 5659 | | IREG(TMR_ST) &= ~GIEFLAG; |
| 5660 | | if (m_chip_type == CHIP_TYPE_TMS32032) |
| 5661 | | m_pc = RMEM(((IREG(TMR_IF) >> 16) << 8) + trapnum); |
| 5662 | | else |
| 5663 | | m_pc = RMEM(trapnum); |
| 5664 | | m_icount -= 4*2; |
| 5665 | | } |
| 5666 | | |
| 5667 | | void tms3203x_device::trapc(UINT32 op) |
| 5668 | | { |
| 5669 | | if (condition(op >> 16)) |
| 5670 | | trap(op & 0x3f); |
| 5671 | | } |
| 5672 | | |
| 5673 | | /*-----------------------------------------------------*/ |
| 5674 | | |
| 5675 | | void tms3203x_device::retic_reg(UINT32 op) |
| 5676 | | { |
| 5677 | | if (condition(op >> 16)) |
| 5678 | | { |
| 5679 | | m_pc = RMEM(IREG(TMR_SP)--); |
| 5680 | | IREG(TMR_ST) |= GIEFLAG; |
| 5681 | | m_icount -= 3*2; |
| 5682 | | check_irqs(); |
| 5683 | | } |
| 5684 | | } |
| 5685 | | |
| 5686 | | void tms3203x_device::retsc_reg(UINT32 op) |
| 5687 | | { |
| 5688 | | if (condition(op >> 16)) |
| 5689 | | { |
| 5690 | | m_pc = RMEM(IREG(TMR_SP)--); |
| 5691 | | m_icount -= 3*2; |
| 5692 | | } |
| 5693 | | } |
| 5694 | | |
| 5695 | | /*-----------------------------------------------------*/ |
| 5696 | | |
| 5697 | | void tms3203x_device::mpyaddf_0(UINT32 op) |
| 5698 | | { |
| 5699 | | // src3 * src4, src1 + src2 |
| 5700 | | DECLARE_DEF; |
| 5701 | | UINT32 src3 = RMEM(INDIRECT_1_DEF(op, op >> 8)); |
| 5702 | | UINT32 src4 = RMEM(INDIRECT_1(op, op)); |
| 5703 | | LONG2FP(TMR_TEMP1, src3); |
| 5704 | | LONG2FP(TMR_TEMP2, src4); |
| 5705 | | mpyf(m_r[TMR_TEMP3], m_r[TMR_TEMP1], m_r[TMR_TEMP2]); |
| 5706 | | addf(m_r[((op >> 22) & 1) | 2], m_r[(op >> 19) & 7], m_r[(op >> 16) & 7]); |
| 5707 | | m_r[(op >> 23) & 1] = m_r[TMR_TEMP3]; |
| 5708 | | UPDATE_DEF(); |
| 5709 | | } |
| 5710 | | |
| 5711 | | void tms3203x_device::mpyaddf_1(UINT32 op) |
| 5712 | | { |
| 5713 | | // src3 * src1, src4 + src2 |
| 5714 | | DECLARE_DEF; |
| 5715 | | UINT32 src3 = RMEM(INDIRECT_1_DEF(op, op >> 8)); |
| 5716 | | UINT32 src4 = RMEM(INDIRECT_1(op, op)); |
| 5717 | | LONG2FP(TMR_TEMP1, src3); |
| 5718 | | LONG2FP(TMR_TEMP2, src4); |
| 5719 | | mpyf(m_r[TMR_TEMP3], m_r[TMR_TEMP1], m_r[(op >> 19) & 7]); |
| 5720 | | addf(m_r[((op >> 22) & 1) | 2], m_r[TMR_TEMP2], m_r[(op >> 16) & 7]); |
| 5721 | | m_r[(op >> 23) & 1] = m_r[TMR_TEMP3]; |
| 5722 | | UPDATE_DEF(); |
| 5723 | | } |
| 5724 | | |
| 5725 | | void tms3203x_device::mpyaddf_2(UINT32 op) |
| 5726 | | { |
| 5727 | | // src1 * src2, src3 + src4 |
| 5728 | | DECLARE_DEF; |
| 5729 | | UINT32 src3 = RMEM(INDIRECT_1_DEF(op, op >> 8)); |
| 5730 | | UINT32 src4 = RMEM(INDIRECT_1(op, op)); |
| 5731 | | LONG2FP(TMR_TEMP1, src3); |
| 5732 | | LONG2FP(TMR_TEMP2, src4); |
| 5733 | | mpyf(m_r[TMR_TEMP3], m_r[(op >> 19) & 7], m_r[(op >> 16) & 7]); |
| 5734 | | addf(m_r[((op >> 22) & 1) | 2], m_r[TMR_TEMP1], m_r[TMR_TEMP2]); |
| 5735 | | m_r[(op >> 23) & 1] = m_r[TMR_TEMP3]; |
| 5736 | | UPDATE_DEF(); |
| 5737 | | } |
| 5738 | | |
| 5739 | | void tms3203x_device::mpyaddf_3(UINT32 op) |
| 5740 | | { |
| 5741 | | // src3 * src1, src2 + src4 |
| 5742 | | DECLARE_DEF; |
| 5743 | | UINT32 src3 = RMEM(INDIRECT_1_DEF(op, op >> 8)); |
| 5744 | | UINT32 src4 = RMEM(INDIRECT_1(op, op)); |
| 5745 | | LONG2FP(TMR_TEMP1, src3); |
| 5746 | | LONG2FP(TMR_TEMP2, src4); |
| 5747 | | mpyf(m_r[TMR_TEMP3], m_r[TMR_TEMP1], m_r[(op >> 19) & 7]); |
| 5748 | | addf(m_r[((op >> 22) & 1) | 2], m_r[(op >> 16) & 7], m_r[TMR_TEMP2]); |
| 5749 | | m_r[(op >> 23) & 1] = m_r[TMR_TEMP3]; |
| 5750 | | UPDATE_DEF(); |
| 5751 | | } |
| 5752 | | |
| 5753 | | /*-----------------------------------------------------*/ |
| 5754 | | |
| 5755 | | void tms3203x_device::mpysubf_0(UINT32 op) |
| 5756 | | { |
| 5757 | | // src3 * src4, src1 - src2 |
| 5758 | | DECLARE_DEF; |
| 5759 | | UINT32 src3 = RMEM(INDIRECT_1_DEF(op, op >> 8)); |
| 5760 | | UINT32 src4 = RMEM(INDIRECT_1(op, op)); |
| 5761 | | LONG2FP(TMR_TEMP1, src3); |
| 5762 | | LONG2FP(TMR_TEMP2, src4); |
| 5763 | | mpyf(m_r[TMR_TEMP3], m_r[TMR_TEMP1], m_r[TMR_TEMP2]); |
| 5764 | | subf(m_r[((op >> 22) & 1) | 2], m_r[(op >> 19) & 7], m_r[(op >> 16) & 7]); |
| 5765 | | m_r[(op >> 23) & 1] = m_r[TMR_TEMP3]; |
| 5766 | | UPDATE_DEF(); |
| 5767 | | } |
| 5768 | | |
| 5769 | | void tms3203x_device::mpysubf_1(UINT32 op) |
| 5770 | | { |
| 5771 | | // src3 * src1, src4 - src2 |
| 5772 | | DECLARE_DEF; |
| 5773 | | UINT32 src3 = RMEM(INDIRECT_1_DEF(op, op >> 8)); |
| 5774 | | UINT32 src4 = RMEM(INDIRECT_1(op, op)); |
| 5775 | | LONG2FP(TMR_TEMP1, src3); |
| 5776 | | LONG2FP(TMR_TEMP2, src4); |
| 5777 | | mpyf(m_r[TMR_TEMP3], m_r[TMR_TEMP1], m_r[(op >> 19) & 7]); |
| 5778 | | subf(m_r[((op >> 22) & 1) | 2], m_r[TMR_TEMP2], m_r[(op >> 16) & 7]); |
| 5779 | | m_r[(op >> 23) & 1] = m_r[TMR_TEMP3]; |
| 5780 | | UPDATE_DEF(); |
| 5781 | | } |
| 5782 | | |
| 5783 | | void tms3203x_device::mpysubf_2(UINT32 op) |
| 5784 | | { |
| 5785 | | // src1 * src2, src3 - src4 |
| 5786 | | DECLARE_DEF; |
| 5787 | | UINT32 src3 = RMEM(INDIRECT_1_DEF(op, op >> 8)); |
| 5788 | | UINT32 src4 = RMEM(INDIRECT_1(op, op)); |
| 5789 | | LONG2FP(TMR_TEMP1, src3); |
| 5790 | | LONG2FP(TMR_TEMP2, src4); |
| 5791 | | mpyf(m_r[TMR_TEMP3], m_r[(op >> 19) & 7], m_r[(op >> 16) & 7]); |
| 5792 | | subf(m_r[((op >> 22) & 1) | 2], m_r[TMR_TEMP1], m_r[TMR_TEMP2]); |
| 5793 | | m_r[(op >> 23) & 1] = m_r[TMR_TEMP3]; |
| 5794 | | UPDATE_DEF(); |
| 5795 | | } |
| 5796 | | |
| 5797 | | void tms3203x_device::mpysubf_3(UINT32 op) |
| 5798 | | { |
| 5799 | | // src3 * src1, src2 - src4 |
| 5800 | | DECLARE_DEF; |
| 5801 | | UINT32 src3 = RMEM(INDIRECT_1_DEF(op, op >> 8)); |
| 5802 | | UINT32 src4 = RMEM(INDIRECT_1(op, op)); |
| 5803 | | LONG2FP(TMR_TEMP1, src3); |
| 5804 | | LONG2FP(TMR_TEMP2, src4); |
| 5805 | | mpyf(m_r[TMR_TEMP3], m_r[TMR_TEMP1], m_r[(op >> 19) & 7]); |
| 5806 | | subf(m_r[((op >> 22) & 1) | 2], m_r[(op >> 16) & 7], m_r[TMR_TEMP2]); |
| 5807 | | m_r[(op >> 23) & 1] = m_r[TMR_TEMP3]; |
| 5808 | | UPDATE_DEF(); |
| 5809 | | } |
| 5810 | | |
| 5811 | | /*-----------------------------------------------------*/ |
| 5812 | | |
| 5813 | | void tms3203x_device::mpyaddi_0(UINT32 op) |
| 5814 | | { |
| 5815 | | // src3 * src4, src1 + src2 |
| 5816 | | DECLARE_DEF; |
| 5817 | | UINT32 src1 = IREG((op >> 19) & 7); |
| 5818 | | UINT32 src2 = IREG((op >> 16) & 7); |
| 5819 | | UINT32 src3 = RMEM(INDIRECT_1_DEF(op, op >> 8)); |
| 5820 | | UINT32 src4 = RMEM(INDIRECT_1(op, op)); |
| 5821 | | INT64 mres = (INT64)((INT32)(src3 << 8) >> 8) * (INT64)((INT32)(src4 << 8) >> 8); |
| 5822 | | UINT32 ares = src1 + src2; |
| 5823 | | |
| 5824 | | CLR_NZVUF(); |
| 5825 | | if (OVM()) |
| 5826 | | { |
| 5827 | | if (mres < -(INT64)0x80000000 || mres > (INT64)0x7fffffff) |
| 5828 | | mres = (mres < 0) ? 0x80000000 : 0x7fffffff; |
| 5829 | | if (OVERFLOW_ADD(src1,src2,ares)) |
| 5830 | | ares = ((INT32)src1 < 0) ? 0x80000000 : 0x7fffffff; |
| 5831 | | } |
| 5832 | | IREG((op >> 23) & 1) = mres; |
| 5833 | | IREG(((op >> 22) & 1) | 2) = ares; |
| 5834 | | UPDATE_DEF(); |
| 5835 | | } |
| 5836 | | |
| 5837 | | void tms3203x_device::mpyaddi_1(UINT32 op) |
| 5838 | | { |
| 5839 | | // src3 * src1, src4 + src2 |
| 5840 | | DECLARE_DEF; |
| 5841 | | UINT32 src1 = IREG((op >> 19) & 7); |
| 5842 | | UINT32 src2 = IREG((op >> 16) & 7); |
| 5843 | | UINT32 src3 = RMEM(INDIRECT_1_DEF(op, op >> 8)); |
| 5844 | | UINT32 src4 = RMEM(INDIRECT_1(op, op)); |
| 5845 | | INT64 mres = (INT64)((INT32)(src3 << 8) >> 8) * (INT64)((INT32)(src1 << 8) >> 8); |
| 5846 | | UINT32 ares = src4 + src2; |
| 5847 | | |
| 5848 | | CLR_NZVUF(); |
| 5849 | | if (OVM()) |
| 5850 | | { |
| 5851 | | if (mres < -(INT64)0x80000000 || mres > (INT64)0x7fffffff) |
| 5852 | | mres = (mres < 0) ? 0x80000000 : 0x7fffffff; |
| 5853 | | if (OVERFLOW_ADD(src4,src2,ares)) |
| 5854 | | ares = ((INT32)src4 < 0) ? 0x80000000 : 0x7fffffff; |
| 5855 | | } |
| 5856 | | IREG((op >> 23) & 1) = mres; |
| 5857 | | IREG(((op >> 22) & 1) | 2) = ares; |
| 5858 | | UPDATE_DEF(); |
| 5859 | | } |
| 5860 | | |
| 5861 | | void tms3203x_device::mpyaddi_2(UINT32 op) |
| 5862 | | { |
| 5863 | | // src1 * src2, src3 + src4 |
| 5864 | | DECLARE_DEF; |
| 5865 | | UINT32 src1 = IREG((op >> 19) & 7); |
| 5866 | | UINT32 src2 = IREG((op >> 16) & 7); |
| 5867 | | UINT32 src3 = RMEM(INDIRECT_1_DEF(op, op >> 8)); |
| 5868 | | UINT32 src4 = RMEM(INDIRECT_1(op, op)); |
| 5869 | | INT64 mres = (INT64)((INT32)(src1 << 8) >> 8) * (INT64)((INT32)(src2 << 8) >> 8); |
| 5870 | | UINT32 ares = src3 + src4; |
| 5871 | | |
| 5872 | | CLR_NZVUF(); |
| 5873 | | if (OVM()) |
| 5874 | | { |
| 5875 | | if (mres < -(INT64)0x80000000 || mres > (INT64)0x7fffffff) |
| 5876 | | mres = (mres < 0) ? 0x80000000 : 0x7fffffff; |
| 5877 | | if (OVERFLOW_ADD(src3,src4,ares)) |
| 5878 | | ares = ((INT32)src3 < 0) ? 0x80000000 : 0x7fffffff; |
| 5879 | | } |
| 5880 | | IREG((op >> 23) & 1) = mres; |
| 5881 | | IREG(((op >> 22) & 1) | 2) = ares; |
| 5882 | | UPDATE_DEF(); |
| 5883 | | } |
| 5884 | | |
| 5885 | | void tms3203x_device::mpyaddi_3(UINT32 op) |
| 5886 | | { |
| 5887 | | // src3 * src1, src2 + src4 |
| 5888 | | DECLARE_DEF; |
| 5889 | | UINT32 src1 = IREG((op >> 19) & 7); |
| 5890 | | UINT32 src2 = IREG((op >> 16) & 7); |
| 5891 | | UINT32 src3 = RMEM(INDIRECT_1_DEF(op, op >> 8)); |
| 5892 | | UINT32 src4 = RMEM(INDIRECT_1(op, op)); |
| 5893 | | INT64 mres = (INT64)((INT32)(src3 << 8) >> 8) * (INT64)((INT32)(src1 << 8) >> 8); |
| 5894 | | UINT32 ares = src2 + src4; |
| 5895 | | |
| 5896 | | CLR_NZVUF(); |
| 5897 | | if (OVM()) |
| 5898 | | { |
| 5899 | | if (mres < -(INT64)0x80000000 || mres > (INT64)0x7fffffff) |
| 5900 | | mres = (mres < 0) ? 0x80000000 : 0x7fffffff; |
| 5901 | | if (OVERFLOW_ADD(src2,src4,ares)) |
| 5902 | | ares = ((INT32)src2 < 0) ? 0x80000000 : 0x7fffffff; |
| 5903 | | } |
| 5904 | | IREG((op >> 23) & 1) = mres; |
| 5905 | | IREG(((op >> 22) & 1) | 2) = ares; |
| 5906 | | UPDATE_DEF(); |
| 5907 | | } |
| 5908 | | |
| 5909 | | /*-----------------------------------------------------*/ |
| 5910 | | |
| 5911 | | void tms3203x_device::mpysubi_0(UINT32 op) |
| 5912 | | { |
| 5913 | | // src3 * src4, src1 - src2 |
| 5914 | | DECLARE_DEF; |
| 5915 | | UINT32 src1 = IREG((op >> 19) & 7); |
| 5916 | | UINT32 src2 = IREG((op >> 16) & 7); |
| 5917 | | UINT32 src3 = RMEM(INDIRECT_1_DEF(op, op >> 8)); |
| 5918 | | UINT32 src4 = RMEM(INDIRECT_1(op, op)); |
| 5919 | | INT64 mres = (INT64)((INT32)(src3 << 8) >> 8) * (INT64)((INT32)(src4 << 8) >> 8); |
| 5920 | | UINT32 ares = src1 - src2; |
| 5921 | | |
| 5922 | | CLR_NZVUF(); |
| 5923 | | if (OVM()) |
| 5924 | | { |
| 5925 | | if (mres < -(INT64)0x80000000 || mres > (INT64)0x7fffffff) |
| 5926 | | mres = (mres < 0) ? 0x80000000 : 0x7fffffff; |
| 5927 | | if (OVERFLOW_SUB(src1,src2,ares)) |
| 5928 | | ares = ((INT32)src1 < 0) ? 0x80000000 : 0x7fffffff; |
| 5929 | | } |
| 5930 | | IREG((op >> 23) & 1) = mres; |
| 5931 | | IREG(((op >> 22) & 1) | 2) = ares; |
| 5932 | | UPDATE_DEF(); |
| 5933 | | } |
| 5934 | | |
| 5935 | | void tms3203x_device::mpysubi_1(UINT32 op) |
| 5936 | | { |
| 5937 | | // src3 * src1, src4 - src2 |
| 5938 | | DECLARE_DEF; |
| 5939 | | UINT32 src1 = IREG((op >> 19) & 7); |
| 5940 | | UINT32 src2 = IREG((op >> 16) & 7); |
| 5941 | | UINT32 src3 = RMEM(INDIRECT_1_DEF(op, op >> 8)); |
| 5942 | | UINT32 src4 = RMEM(INDIRECT_1(op, op)); |
| 5943 | | INT64 mres = (INT64)((INT32)(src3 << 8) >> 8) * (INT64)((INT32)(src1 << 8) >> 8); |
| 5944 | | UINT32 ares = src4 - src2; |
| 5945 | | |
| 5946 | | CLR_NZVUF(); |
| 5947 | | if (OVM()) |
| 5948 | | { |
| 5949 | | if (mres < -(INT64)0x80000000 || mres > (INT64)0x7fffffff) |
| 5950 | | mres = (mres < 0) ? 0x80000000 : 0x7fffffff; |
| 5951 | | if (OVERFLOW_SUB(src4,src2,ares)) |
| 5952 | | ares = ((INT32)src4 < 0) ? 0x80000000 : 0x7fffffff; |
| 5953 | | } |
| 5954 | | IREG((op >> 23) & 1) = mres; |
| 5955 | | IREG(((op >> 22) & 1) | 2) = ares; |
| 5956 | | UPDATE_DEF(); |
| 5957 | | } |
| 5958 | | |
| 5959 | | void tms3203x_device::mpysubi_2(UINT32 op) |
| 5960 | | { |
| 5961 | | // src1 * src2, src3 - src4 |
| 5962 | | DECLARE_DEF; |
| 5963 | | UINT32 src1 = IREG((op >> 19) & 7); |
| 5964 | | UINT32 src2 = IREG((op >> 16) & 7); |
| 5965 | | UINT32 src3 = RMEM(INDIRECT_1_DEF(op, op >> 8)); |
| 5966 | | UINT32 src4 = RMEM(INDIRECT_1(op, op)); |
| 5967 | | INT64 mres = (INT64)((INT32)(src1 << 8) >> 8) * (INT64)((INT32)(src2 << 8) >> 8); |
| 5968 | | UINT32 ares = src3 - src4; |
| 5969 | | |
| 5970 | | CLR_NZVUF(); |
| 5971 | | if (OVM()) |
| 5972 | | { |
| 5973 | | if (mres < -(INT64)0x80000000 || mres > (INT64)0x7fffffff) |
| 5974 | | mres = (mres < 0) ? 0x80000000 : 0x7fffffff; |
| 5975 | | if (OVERFLOW_SUB(src3,src4,ares)) |
| 5976 | | ares = ((INT32)src3 < 0) ? 0x80000000 : 0x7fffffff; |
| 5977 | | } |
| 5978 | | IREG((op >> 23) & 1) = mres; |
| 5979 | | IREG(((op >> 22) & 1) | 2) = ares; |
| 5980 | | UPDATE_DEF(); |
| 5981 | | } |
| 5982 | | |
| 5983 | | void tms3203x_device::mpysubi_3(UINT32 op) |
| 5984 | | { |
| 5985 | | // src3 * src1, src2 - src4 |
| 5986 | | DECLARE_DEF; |
| 5987 | | UINT32 src1 = IREG((op >> 19) & 7); |
| 5988 | | UINT32 src2 = IREG((op >> 16) & 7); |
| 5989 | | UINT32 src3 = RMEM(INDIRECT_1_DEF(op, op >> 8)); |
| 5990 | | UINT32 src4 = RMEM(INDIRECT_1(op, op)); |
| 5991 | | INT64 mres = (INT64)((INT32)(src3 << 8) >> 8) * (INT64)((INT32)(src1 << 8) >> 8); |
| 5992 | | UINT32 ares = src2 - src4; |
| 5993 | | |
| 5994 | | CLR_NZVUF(); |
| 5995 | | if (OVM()) |
| 5996 | | { |
| 5997 | | if (mres < -(INT64)0x80000000 || mres > (INT64)0x7fffffff) |
| 5998 | | mres = (mres < 0) ? 0x80000000 : 0x7fffffff; |
| 5999 | | if (OVERFLOW_SUB(src2,src4,ares)) |
| 6000 | | ares = ((INT32)src2 < 0) ? 0x80000000 : 0x7fffffff; |
| 6001 | | } |
| 6002 | | IREG((op >> 23) & 1) = mres; |
| 6003 | | IREG(((op >> 22) & 1) | 2) = ares; |
| 6004 | | UPDATE_DEF(); |
| 6005 | | } |
| 6006 | | |
| 6007 | | /*-----------------------------------------------------*/ |
| 6008 | | |
| 6009 | | void tms3203x_device::stfstf(UINT32 op) |
| 6010 | | { |
| 6011 | | DECLARE_DEF; |
| 6012 | | WMEM(INDIRECT_1_DEF(op, op >> 8), FP2LONG((op >> 16) & 7)); |
| 6013 | | WMEM(INDIRECT_1(op, op), FP2LONG((op >> 22) & 7)); |
| 6014 | | UPDATE_DEF(); |
| 6015 | | } |
| 6016 | | |
| 6017 | | void tms3203x_device::stisti(UINT32 op) |
| 6018 | | { |
| 6019 | | DECLARE_DEF; |
| 6020 | | WMEM(INDIRECT_1_DEF(op, op >> 8), IREG((op >> 16) & 7)); |
| 6021 | | WMEM(INDIRECT_1(op, op), IREG((op >> 22) & 7)); |
| 6022 | | UPDATE_DEF(); |
| 6023 | | } |
| 6024 | | |
| 6025 | | /*-----------------------------------------------------*/ |
| 6026 | | |
| 6027 | | void tms3203x_device::ldfldf(UINT32 op) |
| 6028 | | { |
| 6029 | | DECLARE_DEF; |
| 6030 | | UINT32 res; |
| 6031 | | int dreg; |
| 6032 | | |
| 6033 | | res = RMEM(INDIRECT_1_DEF(op, op >> 8)); |
| 6034 | | dreg = (op >> 19) & 7; |
| 6035 | | LONG2FP(dreg, res); |
| 6036 | | res = RMEM(INDIRECT_1(op, op)); |
| 6037 | | dreg = (op >> 22) & 7; |
| 6038 | | LONG2FP(dreg, res); |
| 6039 | | UPDATE_DEF(); |
| 6040 | | } |
| 6041 | | |
| 6042 | | void tms3203x_device::ldildi(UINT32 op) |
| 6043 | | { |
| 6044 | | DECLARE_DEF; |
| 6045 | | IREG((op >> 19) & 7) = RMEM(INDIRECT_1_DEF(op, op >> 8)); |
| 6046 | | IREG((op >> 22) & 7) = RMEM(INDIRECT_1(op, op)); |
| 6047 | | UPDATE_DEF(); |
| 6048 | | } |
| 6049 | | |
| 6050 | | /*-----------------------------------------------------*/ |
| 6051 | | |
| 6052 | | // src2 = ind(op) |
| 6053 | | // dst2 = ind(op >> 8) |
| 6054 | | // sreg3 = ((op >> 16) & 7) |
| 6055 | | // sreg1 = ((op >> 19) & 7) |
| 6056 | | // dreg1 = ((op >> 22) & 7) |
| 6057 | | |
| 6058 | | void tms3203x_device::absfstf(UINT32 op) |
| 6059 | | { |
| 6060 | | DECLARE_DEF; |
| 6061 | | UINT32 src3 = FP2LONG((op >> 16) & 7); |
| 6062 | | UINT32 src2 = RMEM(INDIRECT_1_DEF(op, op)); |
| 6063 | | { |
| 6064 | | int dreg = (op >> 22) & 7; |
| 6065 | | LONG2FP(TMR_TEMP1, src2); |
| 6066 | | ABSF(dreg, TMR_TEMP1); |
| 6067 | | } |
| 6068 | | WMEM(INDIRECT_1(op, op >> 8), src3); |
| 6069 | | UPDATE_DEF(); |
| 6070 | | } |
| 6071 | | |
| 6072 | | void tms3203x_device::absisti(UINT32 op) |
| 6073 | | { |
| 6074 | | DECLARE_DEF; |
| 6075 | | UINT32 src3 = IREG((op >> 16) & 7); |
| 6076 | | UINT32 src2 = RMEM(INDIRECT_1_DEF(op, op)); |
| 6077 | | { |
| 6078 | | int dreg = (op >> 22) & 7; |
| 6079 | | ABSI(dreg, src2); |
| 6080 | | } |
| 6081 | | WMEM(INDIRECT_1(op, op >> 8), src3); |
| 6082 | | UPDATE_DEF(); |
| 6083 | | } |
| 6084 | | |
| 6085 | | void tms3203x_device::addf3stf(UINT32 op) |
| 6086 | | { |
| 6087 | | DECLARE_DEF; |
| 6088 | | UINT32 src3 = FP2LONG((op >> 16) & 7); |
| 6089 | | UINT32 src2 = RMEM(INDIRECT_1_DEF(op, op)); |
| 6090 | | { |
| 6091 | | LONG2FP(TMR_TEMP1, src2); |
| 6092 | | addf(m_r[(op >> 22) & 7], m_r[(op >> 19) & 7], m_r[TMR_TEMP1]); |
| 6093 | | } |
| 6094 | | WMEM(INDIRECT_1(op, op >> 8), src3); |
| 6095 | | UPDATE_DEF(); |
| 6096 | | } |
| 6097 | | |
| 6098 | | void tms3203x_device::addi3sti(UINT32 op) |
| 6099 | | { |
| 6100 | | DECLARE_DEF; |
| 6101 | | UINT32 src3 = IREG((op >> 16) & 7); |
| 6102 | | UINT32 src2 = RMEM(INDIRECT_1_DEF(op, op)); |
| 6103 | | { |
| 6104 | | int dreg = (op >> 22) & 7; |
| 6105 | | UINT32 src1 = IREG((op >> 19) & 7); |
| 6106 | | ADDI(dreg, src1, src2); |
| 6107 | | } |
| 6108 | | WMEM(INDIRECT_1(op, op >> 8), src3); |
| 6109 | | UPDATE_DEF(); |
| 6110 | | } |
| 6111 | | |
| 6112 | | void tms3203x_device::and3sti(UINT32 op) |
| 6113 | | { |
| 6114 | | DECLARE_DEF; |
| 6115 | | UINT32 src3 = IREG((op >> 16) & 7); |
| 6116 | | UINT32 src2 = RMEM(INDIRECT_1_DEF(op, op)); |
| 6117 | | { |
| 6118 | | int dreg = (op >> 22) & 7; |
| 6119 | | UINT32 src1 = IREG((op >> 19) & 7); |
| 6120 | | AND(dreg, src1, src2); |
| 6121 | | } |
| 6122 | | WMEM(INDIRECT_1(op, op >> 8), src3); |
| 6123 | | UPDATE_DEF(); |
| 6124 | | } |
| 6125 | | |
| 6126 | | void tms3203x_device::ash3sti(UINT32 op) |
| 6127 | | { |
| 6128 | | DECLARE_DEF; |
| 6129 | | UINT32 src3 = IREG((op >> 16) & 7); |
| 6130 | | UINT32 src2 = RMEM(INDIRECT_1_DEF(op, op)); |
| 6131 | | { |
| 6132 | | int dreg = (op >> 22) & 7; |
| 6133 | | UINT32 count = IREG((op >> 19) & 7); |
| 6134 | | ASH(dreg, src2, count); |
| 6135 | | } |
| 6136 | | WMEM(INDIRECT_1(op, op >> 8), src3); |
| 6137 | | UPDATE_DEF(); |
| 6138 | | } |
| 6139 | | |
| 6140 | | void tms3203x_device::fixsti(UINT32 op) |
| 6141 | | { |
| 6142 | | DECLARE_DEF; |
| 6143 | | UINT32 src3 = IREG((op >> 16) & 7); |
| 6144 | | UINT32 src2 = RMEM(INDIRECT_1_DEF(op, op)); |
| 6145 | | { |
| 6146 | | int dreg = (op >> 22) & 7; |
| 6147 | | LONG2FP(dreg, src2); |
| 6148 | | float2int(m_r[dreg], 1); |
| 6149 | | } |
| 6150 | | WMEM(INDIRECT_1(op, op >> 8), src3); |
| 6151 | | UPDATE_DEF(); |
| 6152 | | } |
| 6153 | | |
| 6154 | | void tms3203x_device::floatstf(UINT32 op) |
| 6155 | | { |
| 6156 | | DECLARE_DEF; |
| 6157 | | UINT32 src3 = FP2LONG((op >> 16) & 7); |
| 6158 | | UINT32 src2 = RMEM(INDIRECT_1_DEF(op, op)); |
| 6159 | | { |
| 6160 | | int dreg = (op >> 22) & 7; |
| 6161 | | IREG(dreg) = src2; |
| 6162 | | int2float(m_r[dreg]); |
| 6163 | | } |
| 6164 | | WMEM(INDIRECT_1(op, op >> 8), src3); |
| 6165 | | UPDATE_DEF(); |
| 6166 | | } |
| 6167 | | |
| 6168 | | void tms3203x_device::ldfstf(UINT32 op) |
| 6169 | | { |
| 6170 | | DECLARE_DEF; |
| 6171 | | UINT32 src3 = FP2LONG((op >> 16) & 7); |
| 6172 | | UINT32 src2 = RMEM(INDIRECT_1_DEF(op, op)); |
| 6173 | | { |
| 6174 | | int dreg = (op >> 22) & 7; |
| 6175 | | LONG2FP(dreg, src2); |
| 6176 | | } |
| 6177 | | WMEM(INDIRECT_1(op, op >> 8), src3); |
| 6178 | | UPDATE_DEF(); |
| 6179 | | } |
| 6180 | | |
| 6181 | | void tms3203x_device::ldisti(UINT32 op) |
| 6182 | | { |
| 6183 | | DECLARE_DEF; |
| 6184 | | UINT32 src3 = IREG((op >> 16) & 7); |
| 6185 | | UINT32 src2 = RMEM(INDIRECT_1_DEF(op, op)); |
| 6186 | | IREG((op >> 22) & 7) = src2; |
| 6187 | | WMEM(INDIRECT_1(op, op >> 8), src3); |
| 6188 | | UPDATE_DEF(); |
| 6189 | | } |
| 6190 | | |
| 6191 | | void tms3203x_device::lsh3sti(UINT32 op) |
| 6192 | | { |
| 6193 | | DECLARE_DEF; |
| 6194 | | UINT32 src3 = IREG((op >> 16) & 7); |
| 6195 | | UINT32 src2 = RMEM(INDIRECT_1_DEF(op, op)); |
| 6196 | | { |
| 6197 | | int dreg = (op >> 22) & 7; |
| 6198 | | UINT32 count = IREG((op >> 19) & 7); |
| 6199 | | LSH(dreg, src2, count); |
| 6200 | | } |
| 6201 | | WMEM(INDIRECT_1(op, op >> 8), src3); |
| 6202 | | UPDATE_DEF(); |
| 6203 | | } |
| 6204 | | |
| 6205 | | void tms3203x_device::mpyf3stf(UINT32 op) |
| 6206 | | { |
| 6207 | | DECLARE_DEF; |
| 6208 | | UINT32 src3 = FP2LONG((op >> 16) & 7); |
| 6209 | | UINT32 src2 = RMEM(INDIRECT_1_DEF(op, op)); |
| 6210 | | { |
| 6211 | | LONG2FP(TMR_TEMP1, src2); |
| 6212 | | mpyf(m_r[(op >> 22) & 7], m_r[(op >> 19) & 7], m_r[TMR_TEMP1]); |
| 6213 | | } |
| 6214 | | WMEM(INDIRECT_1(op, op >> 8), src3); |
| 6215 | | UPDATE_DEF(); |
| 6216 | | } |
| 6217 | | |
| 6218 | | void tms3203x_device::mpyi3sti(UINT32 op) |
| 6219 | | { |
| 6220 | | DECLARE_DEF; |
| 6221 | | UINT32 src3 = IREG((op >> 16) & 7); |
| 6222 | | UINT32 src2 = RMEM(INDIRECT_1_DEF(op, op)); |
| 6223 | | { |
| 6224 | | int dreg = (op >> 22) & 7; |
| 6225 | | UINT32 src1 = IREG((op >> 19) & 7); |
| 6226 | | MPYI(dreg, src1, src2); |
| 6227 | | } |
| 6228 | | WMEM(INDIRECT_1(op, op >> 8), src3); |
| 6229 | | UPDATE_DEF(); |
| 6230 | | } |
| 6231 | | |
| 6232 | | void tms3203x_device::negfstf(UINT32 op) |
| 6233 | | { |
| 6234 | | DECLARE_DEF; |
| 6235 | | UINT32 src3 = FP2LONG((op >> 16) & 7); |
| 6236 | | UINT32 src2 = RMEM(INDIRECT_1_DEF(op, op)); |
| 6237 | | { |
| 6238 | | LONG2FP(TMR_TEMP1, src2); |
| 6239 | | negf(m_r[(op >> 22) & 7], m_r[TMR_TEMP1]); |
| 6240 | | } |
| 6241 | | WMEM(INDIRECT_1(op, op >> 8), src3); |
| 6242 | | UPDATE_DEF(); |
| 6243 | | } |
| 6244 | | |
| 6245 | | void tms3203x_device::negisti(UINT32 op) |
| 6246 | | { |
| 6247 | | DECLARE_DEF; |
| 6248 | | UINT32 src3 = IREG((op >> 16) & 7); |
| 6249 | | UINT32 src2 = RMEM(INDIRECT_1_DEF(op, op)); |
| 6250 | | { |
| 6251 | | int dreg = (op >> 22) & 7; |
| 6252 | | NEGI(dreg, src2); |
| 6253 | | } |
| 6254 | | WMEM(INDIRECT_1(op, op >> 8), src3); |
| 6255 | | UPDATE_DEF(); |
| 6256 | | } |
| 6257 | | |
| 6258 | | void tms3203x_device::notsti(UINT32 op) |
| 6259 | | { |
| 6260 | | DECLARE_DEF; |
| 6261 | | UINT32 src3 = IREG((op >> 16) & 7); |
| 6262 | | UINT32 src2 = RMEM(INDIRECT_1_DEF(op, op)); |
| 6263 | | { |
| 6264 | | int dreg = (op >> 22) & 7; |
| 6265 | | NOT(dreg, src2); |
| 6266 | | } |
| 6267 | | WMEM(INDIRECT_1(op, op >> 8), src3); |
| 6268 | | UPDATE_DEF(); |
| 6269 | | } |
| 6270 | | |
| 6271 | | void tms3203x_device::or3sti(UINT32 op) |
| 6272 | | { |
| 6273 | | DECLARE_DEF; |
| 6274 | | UINT32 src3 = IREG((op >> 16) & 7); |
| 6275 | | UINT32 src2 = RMEM(INDIRECT_1_DEF(op, op)); |
| 6276 | | { |
| 6277 | | int dreg = (op >> 22) & 7; |
| 6278 | | UINT32 src1 = IREG((op >> 19) & 7); |
| 6279 | | OR(dreg, src1, src2); |
| 6280 | | } |
| 6281 | | WMEM(INDIRECT_1(op, op >> 8), src3); |
| 6282 | | UPDATE_DEF(); |
| 6283 | | } |
| 6284 | | |
| 6285 | | void tms3203x_device::subf3stf(UINT32 op) |
| 6286 | | { |
| 6287 | | DECLARE_DEF; |
| 6288 | | UINT32 src3 = FP2LONG((op >> 16) & 7); |
| 6289 | | UINT32 src2 = RMEM(INDIRECT_1_DEF(op, op)); |
| 6290 | | { |
| 6291 | | LONG2FP(TMR_TEMP1, src2); |
| 6292 | | subf(m_r[(op >> 22) & 7], m_r[TMR_TEMP1], m_r[(op >> 19) & 7]); |
| 6293 | | } |
| 6294 | | WMEM(INDIRECT_1(op, op >> 8), src3); |
| 6295 | | UPDATE_DEF(); |
| 6296 | | } |
| 6297 | | |
| 6298 | | void tms3203x_device::subi3sti(UINT32 op) |
| 6299 | | { |
| 6300 | | DECLARE_DEF; |
| 6301 | | UINT32 src3 = IREG((op >> 16) & 7); |
| 6302 | | UINT32 src2 = RMEM(INDIRECT_1_DEF(op, op)); |
| 6303 | | { |
| 6304 | | int dreg = (op >> 22) & 7; |
| 6305 | | UINT32 src1 = IREG((op >> 19) & 7); |
| 6306 | | SUBI(dreg, src2, src1); |
| 6307 | | } |
| 6308 | | WMEM(INDIRECT_1(op, op >> 8), src3); |
| 6309 | | UPDATE_DEF(); |
| 6310 | | } |
| 6311 | | |
| 6312 | | void tms3203x_device::xor3sti(UINT32 op) |
| 6313 | | { |
| 6314 | | DECLARE_DEF; |
| 6315 | | UINT32 src3 = IREG((op >> 16) & 7); |
| 6316 | | UINT32 src2 = RMEM(INDIRECT_1_DEF(op, op)); |
| 6317 | | { |
| 6318 | | int dreg = (op >> 22) & 7; |
| 6319 | | UINT32 src1 = IREG((op >> 19) & 7); |
| 6320 | | XOR(dreg, src1, src2); |
| 6321 | | } |
| 6322 | | WMEM(INDIRECT_1(op, op >> 8), src3); |
| 6323 | | UPDATE_DEF(); |
| 6324 | | } |
| 6325 | | |
| 6326 | | |
| 6327 | | //************************************************************************** |
| 6328 | | // FUNCTION TABLE |
| 6329 | | //************************************************************************** |
| 6330 | | |
| 6331 | | UINT32 (tms3203x_device::*const tms3203x_device::s_indirect_d[0x20])(UINT32, UINT8) = |
| 6332 | | { |
| 6333 | | &tms3203x_device::mod00_d, &tms3203x_device::mod01_d, &tms3203x_device::mod02_d, &tms3203x_device::mod03_d, |
| 6334 | | &tms3203x_device::mod04_d, &tms3203x_device::mod05_d, &tms3203x_device::mod06_d, &tms3203x_device::mod07_d, |
| 6335 | | &tms3203x_device::mod08, &tms3203x_device::mod09, &tms3203x_device::mod0a, &tms3203x_device::mod0b, |
| 6336 | | &tms3203x_device::mod0c, &tms3203x_device::mod0d, &tms3203x_device::mod0e, &tms3203x_device::mod0f, |
| 6337 | | &tms3203x_device::mod10, &tms3203x_device::mod11, &tms3203x_device::mod12, &tms3203x_device::mod13, |
| 6338 | | &tms3203x_device::mod14, &tms3203x_device::mod15, &tms3203x_device::mod16, &tms3203x_device::mod17, |
| 6339 | | &tms3203x_device::mod18, &tms3203x_device::mod19, &tms3203x_device::modillegal, &tms3203x_device::modillegal, |
| 6340 | | &tms3203x_device::modillegal, &tms3203x_device::modillegal, &tms3203x_device::modillegal, &tms3203x_device::modillegal |
| 6341 | | }; |
| 6342 | | |
| 6343 | | |
| 6344 | | UINT32 (tms3203x_device::*const tms3203x_device::s_indirect_1[0x20])(UINT32, UINT8) = |
| 6345 | | { |
| 6346 | | &tms3203x_device::mod00_1, &tms3203x_device::mod01_1, &tms3203x_device::mod02_1, &tms3203x_device::mod03_1, |
| 6347 | | &tms3203x_device::mod04_1, &tms3203x_device::mod05_1, &tms3203x_device::mod06_1, &tms3203x_device::mod07_1, |
| 6348 | | &tms3203x_device::mod08, &tms3203x_device::mod09, &tms3203x_device::mod0a, &tms3203x_device::mod0b, |
| 6349 | | &tms3203x_device::mod0c, &tms3203x_device::mod0d, &tms3203x_device::mod0e, &tms3203x_device::mod0f, |
| 6350 | | &tms3203x_device::mod10, &tms3203x_device::mod11, &tms3203x_device::mod12, &tms3203x_device::mod13, |
| 6351 | | &tms3203x_device::mod14, &tms3203x_device::mod15, &tms3203x_device::mod16, &tms3203x_device::mod17, |
| 6352 | | &tms3203x_device::mod18, &tms3203x_device::mod19, &tms3203x_device::modillegal, &tms3203x_device::modillegal, |
| 6353 | | &tms3203x_device::modillegal, &tms3203x_device::modillegal, &tms3203x_device::modillegal, &tms3203x_device::modillegal |
| 6354 | | }; |
| 6355 | | |
| 6356 | | |
| 6357 | | UINT32 (tms3203x_device::*const tms3203x_device::s_indirect_1_def[0x20])(UINT32, UINT8, UINT32 *&) = |
| 6358 | | { |
| 6359 | | &tms3203x_device::mod00_1_def, &tms3203x_device::mod01_1_def, &tms3203x_device::mod02_1_def, &tms3203x_device::mod03_1_def, |
| 6360 | | &tms3203x_device::mod04_1_def, &tms3203x_device::mod05_1_def, &tms3203x_device::mod06_1_def, &tms3203x_device::mod07_1_def, |
| 6361 | | &tms3203x_device::mod08_def, &tms3203x_device::mod09_def, &tms3203x_device::mod0a_def, &tms3203x_device::mod0b_def, |
| 6362 | | &tms3203x_device::mod0c_def, &tms3203x_device::mod0d_def, &tms3203x_device::mod0e_def, &tms3203x_device::mod0f_def, |
| 6363 | | &tms3203x_device::mod10_def, &tms3203x_device::mod11_def, &tms3203x_device::mod12_def, &tms3203x_device::mod13_def, |
| 6364 | | &tms3203x_device::mod14_def, &tms3203x_device::mod15_def, &tms3203x_device::mod16_def, &tms3203x_device::mod17_def, |
| 6365 | | &tms3203x_device::mod18_def, &tms3203x_device::mod19_def, &tms3203x_device::modillegal_def,&tms3203x_device::modillegal_def, |
| 6366 | | &tms3203x_device::modillegal_def,&tms3203x_device::modillegal_def,&tms3203x_device::modillegal_def,&tms3203x_device::modillegal_def |
| 6367 | | }; |
| 6368 | | |
| 6369 | | void (tms3203x_device::*const tms3203x_device::s_tms32031ops[])(UINT32 op) = |
| 6370 | | { |
| 6371 | | &tms3203x_device::absf_reg, &tms3203x_device::absf_dir, &tms3203x_device::absf_ind, &tms3203x_device::absf_imm, // 0x00 |
| 6372 | | &tms3203x_device::absi_reg, &tms3203x_device::absi_dir, &tms3203x_device::absi_ind, &tms3203x_device::absi_imm, |
| 6373 | | &tms3203x_device::addc_reg, &tms3203x_device::addc_dir, &tms3203x_device::addc_ind, &tms3203x_device::addc_imm, |
| 6374 | | &tms3203x_device::addf_reg, &tms3203x_device::addf_dir, &tms3203x_device::addf_ind, &tms3203x_device::addf_imm, |
| 6375 | | &tms3203x_device::addi_reg, &tms3203x_device::addi_dir, &tms3203x_device::addi_ind, &tms3203x_device::addi_imm, |
| 6376 | | &tms3203x_device::and_reg, &tms3203x_device::and_dir, &tms3203x_device::and_ind, &tms3203x_device::and_imm, |
| 6377 | | &tms3203x_device::andn_reg, &tms3203x_device::andn_dir, &tms3203x_device::andn_ind, &tms3203x_device::andn_imm, |
| 6378 | | &tms3203x_device::ash_reg, &tms3203x_device::ash_dir, &tms3203x_device::ash_ind, &tms3203x_device::ash_imm, |
| 6379 | | &tms3203x_device::cmpf_reg, &tms3203x_device::cmpf_dir, &tms3203x_device::cmpf_ind, &tms3203x_device::cmpf_imm, // 0x08 |
| 6380 | | &tms3203x_device::cmpi_reg, &tms3203x_device::cmpi_dir, &tms3203x_device::cmpi_ind, &tms3203x_device::cmpi_imm, |
| 6381 | | &tms3203x_device::fix_reg, &tms3203x_device::fix_dir, &tms3203x_device::fix_ind, &tms3203x_device::fix_imm, |
| 6382 | | &tms3203x_device::float_reg, &tms3203x_device::float_dir, &tms3203x_device::float_ind, &tms3203x_device::float_imm, |
| 6383 | | &tms3203x_device::idle, &tms3203x_device::idle, &tms3203x_device::idle, &tms3203x_device::idle, |
| 6384 | | &tms3203x_device::lde_reg, &tms3203x_device::lde_dir, &tms3203x_device::lde_ind, &tms3203x_device::lde_imm, |
| 6385 | | &tms3203x_device::ldf_reg, &tms3203x_device::ldf_dir, &tms3203x_device::ldf_ind, &tms3203x_device::ldf_imm, |
| 6386 | | &tms3203x_device::illegal, &tms3203x_device::ldfi_dir, &tms3203x_device::ldfi_ind, &tms3203x_device::illegal, |
| 6387 | | &tms3203x_device::ldi_reg, &tms3203x_device::ldi_dir, &tms3203x_device::ldi_ind, &tms3203x_device::ldi_imm, // 0x10 |
| 6388 | | &tms3203x_device::illegal, &tms3203x_device::ldii_dir, &tms3203x_device::ldii_ind, &tms3203x_device::illegal, |
| 6389 | | &tms3203x_device::ldm_reg, &tms3203x_device::ldm_dir, &tms3203x_device::ldm_ind, &tms3203x_device::ldm_imm, |
| 6390 | | &tms3203x_device::lsh_reg, &tms3203x_device::lsh_dir, &tms3203x_device::lsh_ind, &tms3203x_device::lsh_imm, |
| 6391 | | &tms3203x_device::mpyf_reg, &tms3203x_device::mpyf_dir, &tms3203x_device::mpyf_ind, &tms3203x_device::mpyf_imm, |
| 6392 | | &tms3203x_device::mpyi_reg, &tms3203x_device::mpyi_dir, &tms3203x_device::mpyi_ind, &tms3203x_device::mpyi_imm, |
| 6393 | | &tms3203x_device::negb_reg, &tms3203x_device::negb_dir, &tms3203x_device::negb_ind, &tms3203x_device::negb_imm, |
| 6394 | | &tms3203x_device::negf_reg, &tms3203x_device::negf_dir, &tms3203x_device::negf_ind, &tms3203x_device::negf_imm, |
| 6395 | | &tms3203x_device::negi_reg, &tms3203x_device::negi_dir, &tms3203x_device::negi_ind, &tms3203x_device::negi_imm, // 0x18 |
| 6396 | | &tms3203x_device::nop_reg, &tms3203x_device::illegal, &tms3203x_device::nop_ind, &tms3203x_device::illegal, |
| 6397 | | &tms3203x_device::norm_reg, &tms3203x_device::norm_dir, &tms3203x_device::norm_ind, &tms3203x_device::norm_imm, |
| 6398 | | &tms3203x_device::not_reg, &tms3203x_device::not_dir, &tms3203x_device::not_ind, &tms3203x_device::not_imm, |
| 6399 | | &tms3203x_device::illegal, &tms3203x_device::pop, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6400 | | &tms3203x_device::illegal, &tms3203x_device::popf, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6401 | | &tms3203x_device::illegal, &tms3203x_device::push, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6402 | | &tms3203x_device::illegal, &tms3203x_device::pushf, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6403 | | &tms3203x_device::or_reg, &tms3203x_device::or_dir, &tms3203x_device::or_ind, &tms3203x_device::or_imm, // 0x20 |
| 6404 | | &tms3203x_device::maxspeed, &tms3203x_device::maxspeed, &tms3203x_device::maxspeed, &tms3203x_device::maxspeed, |
| 6405 | | &tms3203x_device::rnd_reg, &tms3203x_device::rnd_dir, &tms3203x_device::rnd_ind, &tms3203x_device::rnd_imm, |
| 6406 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::rol, |
| 6407 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::rolc, |
| 6408 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::ror, |
| 6409 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::rorc, |
| 6410 | | &tms3203x_device::rtps_reg, &tms3203x_device::rtps_dir, &tms3203x_device::rtps_ind, &tms3203x_device::rtps_imm, |
| 6411 | | &tms3203x_device::illegal, &tms3203x_device::stf_dir, &tms3203x_device::stf_ind, &tms3203x_device::illegal, // 0x28 |
| 6412 | | &tms3203x_device::illegal, &tms3203x_device::stfi_dir, &tms3203x_device::stfi_ind, &tms3203x_device::illegal, |
| 6413 | | &tms3203x_device::illegal, &tms3203x_device::sti_dir, &tms3203x_device::sti_ind, &tms3203x_device::illegal, |
| 6414 | | &tms3203x_device::illegal, &tms3203x_device::stii_dir, &tms3203x_device::stii_ind, &tms3203x_device::illegal, |
| 6415 | | &tms3203x_device::sigi, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6416 | | &tms3203x_device::subb_reg, &tms3203x_device::subb_dir, &tms3203x_device::subb_ind, &tms3203x_device::subb_imm, |
| 6417 | | &tms3203x_device::subc_reg, &tms3203x_device::subc_dir, &tms3203x_device::subc_ind, &tms3203x_device::subc_imm, |
| 6418 | | &tms3203x_device::subf_reg, &tms3203x_device::subf_dir, &tms3203x_device::subf_ind, &tms3203x_device::subf_imm, |
| 6419 | | &tms3203x_device::subi_reg, &tms3203x_device::subi_dir, &tms3203x_device::subi_ind, &tms3203x_device::subi_imm, // 0x30 |
| 6420 | | &tms3203x_device::subrb_reg, &tms3203x_device::subrb_dir, &tms3203x_device::subrb_ind, &tms3203x_device::subrb_imm, |
| 6421 | | &tms3203x_device::subrf_reg, &tms3203x_device::subrf_dir, &tms3203x_device::subrf_ind, &tms3203x_device::subrf_imm, |
| 6422 | | &tms3203x_device::subri_reg, &tms3203x_device::subri_dir, &tms3203x_device::subri_ind, &tms3203x_device::subri_imm, |
| 6423 | | &tms3203x_device::tstb_reg, &tms3203x_device::tstb_dir, &tms3203x_device::tstb_ind, &tms3203x_device::tstb_imm, |
| 6424 | | &tms3203x_device::xor_reg, &tms3203x_device::xor_dir, &tms3203x_device::xor_ind, &tms3203x_device::xor_imm, |
| 6425 | | &tms3203x_device::illegal, &tms3203x_device::iack_dir, &tms3203x_device::iack_ind, &tms3203x_device::illegal, |
| 6426 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6427 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, // 0x38 |
| 6428 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6429 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6430 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6431 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6432 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6433 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6434 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6435 | | |
| 6436 | | &tms3203x_device::addc3_regreg, &tms3203x_device::addc3_indreg, &tms3203x_device::addc3_regind, &tms3203x_device::addc3_indind, // 0x40 |
| 6437 | | &tms3203x_device::addf3_regreg, &tms3203x_device::addf3_indreg, &tms3203x_device::addf3_regind, &tms3203x_device::addf3_indind, |
| 6438 | | &tms3203x_device::addi3_regreg, &tms3203x_device::addi3_indreg, &tms3203x_device::addi3_regind, &tms3203x_device::addi3_indind, |
| 6439 | | &tms3203x_device::and3_regreg, &tms3203x_device::and3_indreg, &tms3203x_device::and3_regind, &tms3203x_device::and3_indind, |
| 6440 | | &tms3203x_device::andn3_regreg, &tms3203x_device::andn3_indreg, &tms3203x_device::andn3_regind, &tms3203x_device::andn3_indind, |
| 6441 | | &tms3203x_device::ash3_regreg, &tms3203x_device::ash3_indreg, &tms3203x_device::ash3_regind, &tms3203x_device::ash3_indind, |
| 6442 | | &tms3203x_device::cmpf3_regreg, &tms3203x_device::cmpf3_indreg, &tms3203x_device::cmpf3_regind, &tms3203x_device::cmpf3_indind, |
| 6443 | | &tms3203x_device::cmpi3_regreg, &tms3203x_device::cmpi3_indreg, &tms3203x_device::cmpi3_regind, &tms3203x_device::cmpi3_indind, |
| 6444 | | &tms3203x_device::lsh3_regreg, &tms3203x_device::lsh3_indreg, &tms3203x_device::lsh3_regind, &tms3203x_device::lsh3_indind, // 0x48 |
| 6445 | | &tms3203x_device::mpyf3_regreg, &tms3203x_device::mpyf3_indreg, &tms3203x_device::mpyf3_regind, &tms3203x_device::mpyf3_indind, |
| 6446 | | &tms3203x_device::mpyi3_regreg, &tms3203x_device::mpyi3_indreg, &tms3203x_device::mpyi3_regind, &tms3203x_device::mpyi3_indind, |
| 6447 | | &tms3203x_device::or3_regreg, &tms3203x_device::or3_indreg, &tms3203x_device::or3_regind, &tms3203x_device::or3_indind, |
| 6448 | | &tms3203x_device::subb3_regreg, &tms3203x_device::subb3_indreg, &tms3203x_device::subb3_regind, &tms3203x_device::subb3_indind, |
| 6449 | | &tms3203x_device::subf3_regreg, &tms3203x_device::subf3_indreg, &tms3203x_device::subf3_regind, &tms3203x_device::subf3_indind, |
| 6450 | | &tms3203x_device::subi3_regreg, &tms3203x_device::subi3_indreg, &tms3203x_device::subi3_regind, &tms3203x_device::subi3_indind, |
| 6451 | | &tms3203x_device::tstb3_regreg, &tms3203x_device::tstb3_indreg, &tms3203x_device::tstb3_regind, &tms3203x_device::tstb3_indind, |
| 6452 | | &tms3203x_device::xor3_regreg, &tms3203x_device::xor3_indreg, &tms3203x_device::xor3_regind, &tms3203x_device::xor3_indind, // 0x50 |
| 6453 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6454 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6455 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6456 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6457 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6458 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6459 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6460 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, // 0x58 |
| 6461 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6462 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6463 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6464 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6465 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6466 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6467 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6468 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, // 0x60 |
| 6469 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6470 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6471 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6472 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6473 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6474 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6475 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6476 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, // 0x68 |
| 6477 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6478 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6479 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6480 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6481 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6482 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6483 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6484 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, // 0x70 |
| 6485 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6486 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6487 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6488 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6489 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6490 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6491 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6492 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, // 0x78 |
| 6493 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6494 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6495 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6496 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6497 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6498 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6499 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6500 | | |
| 6501 | | &tms3203x_device::ldfu_reg, &tms3203x_device::ldfu_dir, &tms3203x_device::ldfu_ind, &tms3203x_device::ldfu_imm, // 0x80 |
| 6502 | | &tms3203x_device::ldflo_reg, &tms3203x_device::ldflo_dir, &tms3203x_device::ldflo_ind, &tms3203x_device::ldflo_imm, |
| 6503 | | &tms3203x_device::ldfls_reg, &tms3203x_device::ldfls_dir, &tms3203x_device::ldfls_ind, &tms3203x_device::ldfls_imm, |
| 6504 | | &tms3203x_device::ldfhi_reg, &tms3203x_device::ldfhi_dir, &tms3203x_device::ldfhi_ind, &tms3203x_device::ldfhi_imm, |
| 6505 | | &tms3203x_device::ldfhs_reg, &tms3203x_device::ldfhs_dir, &tms3203x_device::ldfhs_ind, &tms3203x_device::ldfhs_imm, |
| 6506 | | &tms3203x_device::ldfeq_reg, &tms3203x_device::ldfeq_dir, &tms3203x_device::ldfeq_ind, &tms3203x_device::ldfeq_imm, |
| 6507 | | &tms3203x_device::ldfne_reg, &tms3203x_device::ldfne_dir, &tms3203x_device::ldfne_ind, &tms3203x_device::ldfne_imm, |
| 6508 | | &tms3203x_device::ldflt_reg, &tms3203x_device::ldflt_dir, &tms3203x_device::ldflt_ind, &tms3203x_device::ldflt_imm, |
| 6509 | | &tms3203x_device::ldfle_reg, &tms3203x_device::ldfle_dir, &tms3203x_device::ldfle_ind, &tms3203x_device::ldfle_imm, // 0x88 |
| 6510 | | &tms3203x_device::ldfgt_reg, &tms3203x_device::ldfgt_dir, &tms3203x_device::ldfgt_ind, &tms3203x_device::ldfgt_imm, |
| 6511 | | &tms3203x_device::ldfge_reg, &tms3203x_device::ldfge_dir, &tms3203x_device::ldfge_ind, &tms3203x_device::ldfge_imm, |
| 6512 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6513 | | &tms3203x_device::ldfnv_reg, &tms3203x_device::ldfnv_dir, &tms3203x_device::ldfnv_ind, &tms3203x_device::ldfnv_imm, |
| 6514 | | &tms3203x_device::ldfv_reg, &tms3203x_device::ldfv_dir, &tms3203x_device::ldfv_ind, &tms3203x_device::ldfv_imm, |
| 6515 | | &tms3203x_device::ldfnuf_reg, &tms3203x_device::ldfnuf_dir, &tms3203x_device::ldfnuf_ind, &tms3203x_device::ldfnuf_imm, |
| 6516 | | &tms3203x_device::ldfuf_reg, &tms3203x_device::ldfuf_dir, &tms3203x_device::ldfuf_ind, &tms3203x_device::ldfuf_imm, |
| 6517 | | &tms3203x_device::ldfnlv_reg, &tms3203x_device::ldfnlv_dir, &tms3203x_device::ldfnlv_ind, &tms3203x_device::ldfnlv_imm, // 0x90 |
| 6518 | | &tms3203x_device::ldflv_reg, &tms3203x_device::ldflv_dir, &tms3203x_device::ldflv_ind, &tms3203x_device::ldflv_imm, |
| 6519 | | &tms3203x_device::ldfnluf_reg, &tms3203x_device::ldfnluf_dir, &tms3203x_device::ldfnluf_ind, &tms3203x_device::ldfnluf_imm, |
| 6520 | | &tms3203x_device::ldfluf_reg, &tms3203x_device::ldfluf_dir, &tms3203x_device::ldfluf_ind, &tms3203x_device::ldfluf_imm, |
| 6521 | | &tms3203x_device::ldfzuf_reg, &tms3203x_device::ldfzuf_dir, &tms3203x_device::ldfzuf_ind, &tms3203x_device::ldfzuf_imm, |
| 6522 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6523 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6524 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6525 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, // 0x98 |
| 6526 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6527 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6528 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6529 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6530 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6531 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6532 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6533 | | &tms3203x_device::ldiu_reg, &tms3203x_device::ldiu_dir, &tms3203x_device::ldiu_ind, &tms3203x_device::ldiu_imm, // 0xa0 |
| 6534 | | &tms3203x_device::ldilo_reg, &tms3203x_device::ldilo_dir, &tms3203x_device::ldilo_ind, &tms3203x_device::ldilo_imm, |
| 6535 | | &tms3203x_device::ldils_reg, &tms3203x_device::ldils_dir, &tms3203x_device::ldils_ind, &tms3203x_device::ldils_imm, |
| 6536 | | &tms3203x_device::ldihi_reg, &tms3203x_device::ldihi_dir, &tms3203x_device::ldihi_ind, &tms3203x_device::ldihi_imm, |
| 6537 | | &tms3203x_device::ldihs_reg, &tms3203x_device::ldihs_dir, &tms3203x_device::ldihs_ind, &tms3203x_device::ldihs_imm, |
| 6538 | | &tms3203x_device::ldieq_reg, &tms3203x_device::ldieq_dir, &tms3203x_device::ldieq_ind, &tms3203x_device::ldieq_imm, |
| 6539 | | &tms3203x_device::ldine_reg, &tms3203x_device::ldine_dir, &tms3203x_device::ldine_ind, &tms3203x_device::ldine_imm, |
| 6540 | | &tms3203x_device::ldilt_reg, &tms3203x_device::ldilt_dir, &tms3203x_device::ldilt_ind, &tms3203x_device::ldilt_imm, |
| 6541 | | &tms3203x_device::ldile_reg, &tms3203x_device::ldile_dir, &tms3203x_device::ldile_ind, &tms3203x_device::ldile_imm, // 0xa8 |
| 6542 | | &tms3203x_device::ldigt_reg, &tms3203x_device::ldigt_dir, &tms3203x_device::ldigt_ind, &tms3203x_device::ldigt_imm, |
| 6543 | | &tms3203x_device::ldige_reg, &tms3203x_device::ldige_dir, &tms3203x_device::ldige_ind, &tms3203x_device::ldige_imm, |
| 6544 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6545 | | &tms3203x_device::ldinv_reg, &tms3203x_device::ldinv_dir, &tms3203x_device::ldinv_ind, &tms3203x_device::ldinv_imm, |
| 6546 | | &tms3203x_device::ldiv_reg, &tms3203x_device::ldiv_dir, &tms3203x_device::ldiv_ind, &tms3203x_device::ldiv_imm, |
| 6547 | | &tms3203x_device::ldinuf_reg, &tms3203x_device::ldinuf_dir, &tms3203x_device::ldinuf_ind, &tms3203x_device::ldinuf_imm, |
| 6548 | | &tms3203x_device::ldiuf_reg, &tms3203x_device::ldiuf_dir, &tms3203x_device::ldiuf_ind, &tms3203x_device::ldiuf_imm, |
| 6549 | | &tms3203x_device::ldinlv_reg, &tms3203x_device::ldinlv_dir, &tms3203x_device::ldinlv_ind, &tms3203x_device::ldinlv_imm, // 0xb0 |
| 6550 | | &tms3203x_device::ldilv_reg, &tms3203x_device::ldilv_dir, &tms3203x_device::ldilv_ind, &tms3203x_device::ldilv_imm, |
| 6551 | | &tms3203x_device::ldinluf_reg, &tms3203x_device::ldinluf_dir, &tms3203x_device::ldinluf_ind, &tms3203x_device::ldinluf_imm, |
| 6552 | | &tms3203x_device::ldiluf_reg, &tms3203x_device::ldiluf_dir, &tms3203x_device::ldiluf_ind, &tms3203x_device::ldiluf_imm, |
| 6553 | | &tms3203x_device::ldizuf_reg, &tms3203x_device::ldizuf_dir, &tms3203x_device::ldizuf_ind, &tms3203x_device::ldizuf_imm, |
| 6554 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6555 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6556 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6557 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, // 0xb8 |
| 6558 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6559 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6560 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6561 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6562 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6563 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6564 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6565 | | |
| 6566 | | &tms3203x_device::br_imm, &tms3203x_device::br_imm, &tms3203x_device::br_imm, &tms3203x_device::br_imm, // 0xc0 |
| 6567 | | &tms3203x_device::br_imm, &tms3203x_device::br_imm, &tms3203x_device::br_imm, &tms3203x_device::br_imm, |
| 6568 | | &tms3203x_device::brd_imm, &tms3203x_device::brd_imm, &tms3203x_device::brd_imm, &tms3203x_device::brd_imm, |
| 6569 | | &tms3203x_device::brd_imm, &tms3203x_device::brd_imm, &tms3203x_device::brd_imm, &tms3203x_device::brd_imm, |
| 6570 | | &tms3203x_device::call_imm, &tms3203x_device::call_imm, &tms3203x_device::call_imm, &tms3203x_device::call_imm, |
| 6571 | | &tms3203x_device::call_imm, &tms3203x_device::call_imm, &tms3203x_device::call_imm, &tms3203x_device::call_imm, |
| 6572 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6573 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6574 | | &tms3203x_device::rptb_imm, &tms3203x_device::rptb_imm, &tms3203x_device::rptb_imm, &tms3203x_device::rptb_imm, // 0xc8 |
| 6575 | | &tms3203x_device::rptb_imm, &tms3203x_device::rptb_imm, &tms3203x_device::rptb_imm, &tms3203x_device::rptb_imm, |
| 6576 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6577 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6578 | | &tms3203x_device::swi, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6579 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6580 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6581 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6582 | | &tms3203x_device::brc_reg, &tms3203x_device::brcd_reg, &tms3203x_device::illegal, &tms3203x_device::illegal, // 0xd0 |
| 6583 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6584 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6585 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6586 | | &tms3203x_device::brc_imm, &tms3203x_device::brcd_imm, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6587 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6588 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6589 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6590 | | &tms3203x_device::dbc_reg, &tms3203x_device::dbcd_reg, &tms3203x_device::dbc_reg, &tms3203x_device::dbcd_reg, // 0xd8 |
| 6591 | | &tms3203x_device::dbc_reg, &tms3203x_device::dbcd_reg, &tms3203x_device::dbc_reg, &tms3203x_device::dbcd_reg, |
| 6592 | | &tms3203x_device::dbc_reg, &tms3203x_device::dbcd_reg, &tms3203x_device::dbc_reg, &tms3203x_device::dbcd_reg, |
| 6593 | | &tms3203x_device::dbc_reg, &tms3203x_device::dbcd_reg, &tms3203x_device::dbc_reg, &tms3203x_device::dbcd_reg, |
| 6594 | | &tms3203x_device::dbc_imm, &tms3203x_device::dbcd_imm, &tms3203x_device::dbc_imm, &tms3203x_device::dbcd_imm, |
| 6595 | | &tms3203x_device::dbc_imm, &tms3203x_device::dbcd_imm, &tms3203x_device::dbc_imm, &tms3203x_device::dbcd_imm, |
| 6596 | | &tms3203x_device::dbc_imm, &tms3203x_device::dbcd_imm, &tms3203x_device::dbc_imm, &tms3203x_device::dbcd_imm, |
| 6597 | | &tms3203x_device::dbc_imm, &tms3203x_device::dbcd_imm, &tms3203x_device::dbc_imm, &tms3203x_device::dbcd_imm, |
| 6598 | | &tms3203x_device::callc_reg, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, // 0xe0 |
| 6599 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6600 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6601 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6602 | | &tms3203x_device::callc_imm, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6603 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6604 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6605 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6606 | | &tms3203x_device::trapc, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, // 0xe8 |
| 6607 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6608 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6609 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6610 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6611 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6612 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6613 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6614 | | &tms3203x_device::retic_reg, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, // 0xf0 |
| 6615 | | &tms3203x_device::retsc_reg, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6616 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6617 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6618 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6619 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6620 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6621 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6622 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, // 0xf8 |
| 6623 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6624 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6625 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6626 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6627 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6628 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6629 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6630 | | |
| 6631 | | &tms3203x_device::mpyaddf_0, &tms3203x_device::mpyaddf_0, &tms3203x_device::mpyaddf_0, &tms3203x_device::mpyaddf_0, // 0x100 |
| 6632 | | &tms3203x_device::mpyaddf_0, &tms3203x_device::mpyaddf_0, &tms3203x_device::mpyaddf_0, &tms3203x_device::mpyaddf_0, |
| 6633 | | &tms3203x_device::mpyaddf_1, &tms3203x_device::mpyaddf_1, &tms3203x_device::mpyaddf_1, &tms3203x_device::mpyaddf_1, |
| 6634 | | &tms3203x_device::mpyaddf_1, &tms3203x_device::mpyaddf_1, &tms3203x_device::mpyaddf_1, &tms3203x_device::mpyaddf_1, |
| 6635 | | &tms3203x_device::mpyaddf_2, &tms3203x_device::mpyaddf_2, &tms3203x_device::mpyaddf_2, &tms3203x_device::mpyaddf_2, |
| 6636 | | &tms3203x_device::mpyaddf_2, &tms3203x_device::mpyaddf_2, &tms3203x_device::mpyaddf_2, &tms3203x_device::mpyaddf_2, |
| 6637 | | &tms3203x_device::mpyaddf_3, &tms3203x_device::mpyaddf_3, &tms3203x_device::mpyaddf_3, &tms3203x_device::mpyaddf_3, |
| 6638 | | &tms3203x_device::mpyaddf_3, &tms3203x_device::mpyaddf_3, &tms3203x_device::mpyaddf_3, &tms3203x_device::mpyaddf_3, |
| 6639 | | &tms3203x_device::mpysubf_0, &tms3203x_device::mpysubf_0, &tms3203x_device::mpysubf_0, &tms3203x_device::mpysubf_0, // 0x108 |
| 6640 | | &tms3203x_device::mpysubf_0, &tms3203x_device::mpysubf_0, &tms3203x_device::mpysubf_0, &tms3203x_device::mpysubf_0, |
| 6641 | | &tms3203x_device::mpysubf_1, &tms3203x_device::mpysubf_1, &tms3203x_device::mpysubf_1, &tms3203x_device::mpysubf_1, |
| 6642 | | &tms3203x_device::mpysubf_1, &tms3203x_device::mpysubf_1, &tms3203x_device::mpysubf_1, &tms3203x_device::mpysubf_1, |
| 6643 | | &tms3203x_device::mpysubf_2, &tms3203x_device::mpysubf_2, &tms3203x_device::mpysubf_2, &tms3203x_device::mpysubf_2, |
| 6644 | | &tms3203x_device::mpysubf_2, &tms3203x_device::mpysubf_2, &tms3203x_device::mpysubf_2, &tms3203x_device::mpysubf_2, |
| 6645 | | &tms3203x_device::mpysubf_3, &tms3203x_device::mpysubf_3, &tms3203x_device::mpysubf_3, &tms3203x_device::mpysubf_3, |
| 6646 | | &tms3203x_device::mpysubf_3, &tms3203x_device::mpysubf_3, &tms3203x_device::mpysubf_3, &tms3203x_device::mpysubf_3, |
| 6647 | | &tms3203x_device::mpyaddi_0, &tms3203x_device::mpyaddi_0, &tms3203x_device::mpyaddi_0, &tms3203x_device::mpyaddi_0, // 0x110 |
| 6648 | | &tms3203x_device::mpyaddi_0, &tms3203x_device::mpyaddi_0, &tms3203x_device::mpyaddi_0, &tms3203x_device::mpyaddi_0, |
| 6649 | | &tms3203x_device::mpyaddi_1, &tms3203x_device::mpyaddi_1, &tms3203x_device::mpyaddi_1, &tms3203x_device::mpyaddi_1, |
| 6650 | | &tms3203x_device::mpyaddi_1, &tms3203x_device::mpyaddi_1, &tms3203x_device::mpyaddi_1, &tms3203x_device::mpyaddi_1, |
| 6651 | | &tms3203x_device::mpyaddi_2, &tms3203x_device::mpyaddi_2, &tms3203x_device::mpyaddi_2, &tms3203x_device::mpyaddi_2, |
| 6652 | | &tms3203x_device::mpyaddi_2, &tms3203x_device::mpyaddi_2, &tms3203x_device::mpyaddi_2, &tms3203x_device::mpyaddi_2, |
| 6653 | | &tms3203x_device::mpyaddi_3, &tms3203x_device::mpyaddi_3, &tms3203x_device::mpyaddi_3, &tms3203x_device::mpyaddi_3, |
| 6654 | | &tms3203x_device::mpyaddi_3, &tms3203x_device::mpyaddi_3, &tms3203x_device::mpyaddi_3, &tms3203x_device::mpyaddi_3, |
| 6655 | | &tms3203x_device::mpysubi_0, &tms3203x_device::mpysubi_0, &tms3203x_device::mpysubi_0, &tms3203x_device::mpysubi_0, // 0x118 |
| 6656 | | &tms3203x_device::mpysubi_0, &tms3203x_device::mpysubi_0, &tms3203x_device::mpysubi_0, &tms3203x_device::mpysubi_0, |
| 6657 | | &tms3203x_device::mpysubi_1, &tms3203x_device::mpysubi_1, &tms3203x_device::mpysubi_1, &tms3203x_device::mpysubi_1, |
| 6658 | | &tms3203x_device::mpysubi_1, &tms3203x_device::mpysubi_1, &tms3203x_device::mpysubi_1, &tms3203x_device::mpysubi_1, |
| 6659 | | &tms3203x_device::mpysubi_2, &tms3203x_device::mpysubi_2, &tms3203x_device::mpysubi_2, &tms3203x_device::mpysubi_2, |
| 6660 | | &tms3203x_device::mpysubi_2, &tms3203x_device::mpysubi_2, &tms3203x_device::mpysubi_2, &tms3203x_device::mpysubi_2, |
| 6661 | | &tms3203x_device::mpysubi_3, &tms3203x_device::mpysubi_3, &tms3203x_device::mpysubi_3, &tms3203x_device::mpysubi_3, |
| 6662 | | &tms3203x_device::mpysubi_3, &tms3203x_device::mpysubi_3, &tms3203x_device::mpysubi_3, &tms3203x_device::mpysubi_3, |
| 6663 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, // 0x120 |
| 6664 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6665 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6666 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6667 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6668 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6669 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6670 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6671 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, // 0x128 |
| 6672 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6673 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6674 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6675 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6676 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6677 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6678 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6679 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, // 0x130 |
| 6680 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6681 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6682 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6683 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6684 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6685 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6686 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6687 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, // 0x138 |
| 6688 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6689 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6690 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6691 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6692 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6693 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6694 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6695 | | |
| 6696 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, // 0x140 |
| 6697 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6698 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6699 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6700 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6701 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6702 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6703 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6704 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, // 0x148 |
| 6705 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6706 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6707 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6708 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6709 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6710 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6711 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6712 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, // 0x150 |
| 6713 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6714 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6715 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6716 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6717 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6718 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6719 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6720 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, // 0x158 |
| 6721 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6722 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6723 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6724 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6725 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6726 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6727 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6728 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, // 0x160 |
| 6729 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6730 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6731 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6732 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6733 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6734 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6735 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6736 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, // 0x168 |
| 6737 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6738 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6739 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6740 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6741 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6742 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6743 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6744 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, // 0x170 |
| 6745 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6746 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6747 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6748 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6749 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6750 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6751 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6752 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, // 0x178 |
| 6753 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6754 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6755 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6756 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6757 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6758 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6759 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6760 | | |
| 6761 | | &tms3203x_device::stfstf, &tms3203x_device::stfstf, &tms3203x_device::stfstf, &tms3203x_device::stfstf, // 0x180 |
| 6762 | | &tms3203x_device::stfstf, &tms3203x_device::stfstf, &tms3203x_device::stfstf, &tms3203x_device::stfstf, |
| 6763 | | &tms3203x_device::stfstf, &tms3203x_device::stfstf, &tms3203x_device::stfstf, &tms3203x_device::stfstf, |
| 6764 | | &tms3203x_device::stfstf, &tms3203x_device::stfstf, &tms3203x_device::stfstf, &tms3203x_device::stfstf, |
| 6765 | | &tms3203x_device::stisti, &tms3203x_device::stisti, &tms3203x_device::stisti, &tms3203x_device::stisti, |
| 6766 | | &tms3203x_device::stisti, &tms3203x_device::stisti, &tms3203x_device::stisti, &tms3203x_device::stisti, |
| 6767 | | &tms3203x_device::stisti, &tms3203x_device::stisti, &tms3203x_device::stisti, &tms3203x_device::stisti, |
| 6768 | | &tms3203x_device::stisti, &tms3203x_device::stisti, &tms3203x_device::stisti, &tms3203x_device::stisti, |
| 6769 | | &tms3203x_device::ldfldf, &tms3203x_device::ldfldf, &tms3203x_device::ldfldf, &tms3203x_device::ldfldf, // 0x188 |
| 6770 | | &tms3203x_device::ldfldf, &tms3203x_device::ldfldf, &tms3203x_device::ldfldf, &tms3203x_device::ldfldf, |
| 6771 | | &tms3203x_device::ldfldf, &tms3203x_device::ldfldf, &tms3203x_device::ldfldf, &tms3203x_device::ldfldf, |
| 6772 | | &tms3203x_device::ldfldf, &tms3203x_device::ldfldf, &tms3203x_device::ldfldf, &tms3203x_device::ldfldf, |
| 6773 | | &tms3203x_device::ldildi, &tms3203x_device::ldildi, &tms3203x_device::ldildi, &tms3203x_device::ldildi, |
| 6774 | | &tms3203x_device::ldildi, &tms3203x_device::ldildi, &tms3203x_device::ldildi, &tms3203x_device::ldildi, |
| 6775 | | &tms3203x_device::ldildi, &tms3203x_device::ldildi, &tms3203x_device::ldildi, &tms3203x_device::ldildi, |
| 6776 | | &tms3203x_device::ldildi, &tms3203x_device::ldildi, &tms3203x_device::ldildi, &tms3203x_device::ldildi, |
| 6777 | | &tms3203x_device::absfstf, &tms3203x_device::absfstf, &tms3203x_device::absfstf, &tms3203x_device::absfstf, // 0x190 |
| 6778 | | &tms3203x_device::absfstf, &tms3203x_device::absfstf, &tms3203x_device::absfstf, &tms3203x_device::absfstf, |
| 6779 | | &tms3203x_device::absfstf, &tms3203x_device::absfstf, &tms3203x_device::absfstf, &tms3203x_device::absfstf, |
| 6780 | | &tms3203x_device::absfstf, &tms3203x_device::absfstf, &tms3203x_device::absfstf, &tms3203x_device::absfstf, |
| 6781 | | &tms3203x_device::absisti, &tms3203x_device::absisti, &tms3203x_device::absisti, &tms3203x_device::absisti, |
| 6782 | | &tms3203x_device::absisti, &tms3203x_device::absisti, &tms3203x_device::absisti, &tms3203x_device::absisti, |
| 6783 | | &tms3203x_device::absisti, &tms3203x_device::absisti, &tms3203x_device::absisti, &tms3203x_device::absisti, |
| 6784 | | &tms3203x_device::absisti, &tms3203x_device::absisti, &tms3203x_device::absisti, &tms3203x_device::absisti, |
| 6785 | | &tms3203x_device::addf3stf, &tms3203x_device::addf3stf, &tms3203x_device::addf3stf, &tms3203x_device::addf3stf, // 0x198 |
| 6786 | | &tms3203x_device::addf3stf, &tms3203x_device::addf3stf, &tms3203x_device::addf3stf, &tms3203x_device::addf3stf, |
| 6787 | | &tms3203x_device::addf3stf, &tms3203x_device::addf3stf, &tms3203x_device::addf3stf, &tms3203x_device::addf3stf, |
| 6788 | | &tms3203x_device::addf3stf, &tms3203x_device::addf3stf, &tms3203x_device::addf3stf, &tms3203x_device::addf3stf, |
| 6789 | | &tms3203x_device::addi3sti, &tms3203x_device::addi3sti, &tms3203x_device::addi3sti, &tms3203x_device::addi3sti, |
| 6790 | | &tms3203x_device::addi3sti, &tms3203x_device::addi3sti, &tms3203x_device::addi3sti, &tms3203x_device::addi3sti, |
| 6791 | | &tms3203x_device::addi3sti, &tms3203x_device::addi3sti, &tms3203x_device::addi3sti, &tms3203x_device::addi3sti, |
| 6792 | | &tms3203x_device::addi3sti, &tms3203x_device::addi3sti, &tms3203x_device::addi3sti, &tms3203x_device::addi3sti, |
| 6793 | | &tms3203x_device::and3sti, &tms3203x_device::and3sti, &tms3203x_device::and3sti, &tms3203x_device::and3sti, // 0x1a0 |
| 6794 | | &tms3203x_device::and3sti, &tms3203x_device::and3sti, &tms3203x_device::and3sti, &tms3203x_device::and3sti, |
| 6795 | | &tms3203x_device::and3sti, &tms3203x_device::and3sti, &tms3203x_device::and3sti, &tms3203x_device::and3sti, |
| 6796 | | &tms3203x_device::and3sti, &tms3203x_device::and3sti, &tms3203x_device::and3sti, &tms3203x_device::and3sti, |
| 6797 | | &tms3203x_device::ash3sti, &tms3203x_device::ash3sti, &tms3203x_device::ash3sti, &tms3203x_device::ash3sti, |
| 6798 | | &tms3203x_device::ash3sti, &tms3203x_device::ash3sti, &tms3203x_device::ash3sti, &tms3203x_device::ash3sti, |
| 6799 | | &tms3203x_device::ash3sti, &tms3203x_device::ash3sti, &tms3203x_device::ash3sti, &tms3203x_device::ash3sti, |
| 6800 | | &tms3203x_device::ash3sti, &tms3203x_device::ash3sti, &tms3203x_device::ash3sti, &tms3203x_device::ash3sti, |
| 6801 | | &tms3203x_device::fixsti, &tms3203x_device::fixsti, &tms3203x_device::fixsti, &tms3203x_device::fixsti, // 0x1a8 |
| 6802 | | &tms3203x_device::fixsti, &tms3203x_device::fixsti, &tms3203x_device::fixsti, &tms3203x_device::fixsti, |
| 6803 | | &tms3203x_device::fixsti, &tms3203x_device::fixsti, &tms3203x_device::fixsti, &tms3203x_device::fixsti, |
| 6804 | | &tms3203x_device::fixsti, &tms3203x_device::fixsti, &tms3203x_device::fixsti, &tms3203x_device::fixsti, |
| 6805 | | &tms3203x_device::floatstf, &tms3203x_device::floatstf, &tms3203x_device::floatstf, &tms3203x_device::floatstf, |
| 6806 | | &tms3203x_device::floatstf, &tms3203x_device::floatstf, &tms3203x_device::floatstf, &tms3203x_device::floatstf, |
| 6807 | | &tms3203x_device::floatstf, &tms3203x_device::floatstf, &tms3203x_device::floatstf, &tms3203x_device::floatstf, |
| 6808 | | &tms3203x_device::floatstf, &tms3203x_device::floatstf, &tms3203x_device::floatstf, &tms3203x_device::floatstf, |
| 6809 | | &tms3203x_device::ldfstf, &tms3203x_device::ldfstf, &tms3203x_device::ldfstf, &tms3203x_device::ldfstf, // 0x1b0 |
| 6810 | | &tms3203x_device::ldfstf, &tms3203x_device::ldfstf, &tms3203x_device::ldfstf, &tms3203x_device::ldfstf, |
| 6811 | | &tms3203x_device::ldfstf, &tms3203x_device::ldfstf, &tms3203x_device::ldfstf, &tms3203x_device::ldfstf, |
| 6812 | | &tms3203x_device::ldfstf, &tms3203x_device::ldfstf, &tms3203x_device::ldfstf, &tms3203x_device::ldfstf, |
| 6813 | | &tms3203x_device::ldisti, &tms3203x_device::ldisti, &tms3203x_device::ldisti, &tms3203x_device::ldisti, |
| 6814 | | &tms3203x_device::ldisti, &tms3203x_device::ldisti, &tms3203x_device::ldisti, &tms3203x_device::ldisti, |
| 6815 | | &tms3203x_device::ldisti, &tms3203x_device::ldisti, &tms3203x_device::ldisti, &tms3203x_device::ldisti, |
| 6816 | | &tms3203x_device::ldisti, &tms3203x_device::ldisti, &tms3203x_device::ldisti, &tms3203x_device::ldisti, |
| 6817 | | &tms3203x_device::lsh3sti, &tms3203x_device::lsh3sti, &tms3203x_device::lsh3sti, &tms3203x_device::lsh3sti, // 0x1b8 |
| 6818 | | &tms3203x_device::lsh3sti, &tms3203x_device::lsh3sti, &tms3203x_device::lsh3sti, &tms3203x_device::lsh3sti, |
| 6819 | | &tms3203x_device::lsh3sti, &tms3203x_device::lsh3sti, &tms3203x_device::lsh3sti, &tms3203x_device::lsh3sti, |
| 6820 | | &tms3203x_device::lsh3sti, &tms3203x_device::lsh3sti, &tms3203x_device::lsh3sti, &tms3203x_device::lsh3sti, |
| 6821 | | &tms3203x_device::mpyf3stf, &tms3203x_device::mpyf3stf, &tms3203x_device::mpyf3stf, &tms3203x_device::mpyf3stf, |
| 6822 | | &tms3203x_device::mpyf3stf, &tms3203x_device::mpyf3stf, &tms3203x_device::mpyf3stf, &tms3203x_device::mpyf3stf, |
| 6823 | | &tms3203x_device::mpyf3stf, &tms3203x_device::mpyf3stf, &tms3203x_device::mpyf3stf, &tms3203x_device::mpyf3stf, |
| 6824 | | &tms3203x_device::mpyf3stf, &tms3203x_device::mpyf3stf, &tms3203x_device::mpyf3stf, &tms3203x_device::mpyf3stf, |
| 6825 | | |
| 6826 | | &tms3203x_device::mpyi3sti, &tms3203x_device::mpyi3sti, &tms3203x_device::mpyi3sti, &tms3203x_device::mpyi3sti, // 0x1c0 |
| 6827 | | &tms3203x_device::mpyi3sti, &tms3203x_device::mpyi3sti, &tms3203x_device::mpyi3sti, &tms3203x_device::mpyi3sti, |
| 6828 | | &tms3203x_device::mpyi3sti, &tms3203x_device::mpyi3sti, &tms3203x_device::mpyi3sti, &tms3203x_device::mpyi3sti, |
| 6829 | | &tms3203x_device::mpyi3sti, &tms3203x_device::mpyi3sti, &tms3203x_device::mpyi3sti, &tms3203x_device::mpyi3sti, |
| 6830 | | &tms3203x_device::negfstf, &tms3203x_device::negfstf, &tms3203x_device::negfstf, &tms3203x_device::negfstf, |
| 6831 | | &tms3203x_device::negfstf, &tms3203x_device::negfstf, &tms3203x_device::negfstf, &tms3203x_device::negfstf, |
| 6832 | | &tms3203x_device::negfstf, &tms3203x_device::negfstf, &tms3203x_device::negfstf, &tms3203x_device::negfstf, |
| 6833 | | &tms3203x_device::negfstf, &tms3203x_device::negfstf, &tms3203x_device::negfstf, &tms3203x_device::negfstf, |
| 6834 | | &tms3203x_device::negisti, &tms3203x_device::negisti, &tms3203x_device::negisti, &tms3203x_device::negisti, // 0x1c8 |
| 6835 | | &tms3203x_device::negisti, &tms3203x_device::negisti, &tms3203x_device::negisti, &tms3203x_device::negisti, |
| 6836 | | &tms3203x_device::negisti, &tms3203x_device::negisti, &tms3203x_device::negisti, &tms3203x_device::negisti, |
| 6837 | | &tms3203x_device::negisti, &tms3203x_device::negisti, &tms3203x_device::negisti, &tms3203x_device::negisti, |
| 6838 | | &tms3203x_device::notsti, &tms3203x_device::notsti, &tms3203x_device::notsti, &tms3203x_device::notsti, |
| 6839 | | &tms3203x_device::notsti, &tms3203x_device::notsti, &tms3203x_device::notsti, &tms3203x_device::notsti, |
| 6840 | | &tms3203x_device::notsti, &tms3203x_device::notsti, &tms3203x_device::notsti, &tms3203x_device::notsti, |
| 6841 | | &tms3203x_device::notsti, &tms3203x_device::notsti, &tms3203x_device::notsti, &tms3203x_device::notsti, |
| 6842 | | &tms3203x_device::or3sti, &tms3203x_device::or3sti, &tms3203x_device::or3sti, &tms3203x_device::or3sti, // 0x1d0 |
| 6843 | | &tms3203x_device::or3sti, &tms3203x_device::or3sti, &tms3203x_device::or3sti, &tms3203x_device::or3sti, |
| 6844 | | &tms3203x_device::or3sti, &tms3203x_device::or3sti, &tms3203x_device::or3sti, &tms3203x_device::or3sti, |
| 6845 | | &tms3203x_device::or3sti, &tms3203x_device::or3sti, &tms3203x_device::or3sti, &tms3203x_device::or3sti, |
| 6846 | | &tms3203x_device::subf3stf, &tms3203x_device::subf3stf, &tms3203x_device::subf3stf, &tms3203x_device::subf3stf, |
| 6847 | | &tms3203x_device::subf3stf, &tms3203x_device::subf3stf, &tms3203x_device::subf3stf, &tms3203x_device::subf3stf, |
| 6848 | | &tms3203x_device::subf3stf, &tms3203x_device::subf3stf, &tms3203x_device::subf3stf, &tms3203x_device::subf3stf, |
| 6849 | | &tms3203x_device::subf3stf, &tms3203x_device::subf3stf, &tms3203x_device::subf3stf, &tms3203x_device::subf3stf, |
| 6850 | | &tms3203x_device::subi3sti, &tms3203x_device::subi3sti, &tms3203x_device::subi3sti, &tms3203x_device::subi3sti, // 0x1d8 |
| 6851 | | &tms3203x_device::subi3sti, &tms3203x_device::subi3sti, &tms3203x_device::subi3sti, &tms3203x_device::subi3sti, |
| 6852 | | &tms3203x_device::subi3sti, &tms3203x_device::subi3sti, &tms3203x_device::subi3sti, &tms3203x_device::subi3sti, |
| 6853 | | &tms3203x_device::subi3sti, &tms3203x_device::subi3sti, &tms3203x_device::subi3sti, &tms3203x_device::subi3sti, |
| 6854 | | &tms3203x_device::xor3sti, &tms3203x_device::xor3sti, &tms3203x_device::xor3sti, &tms3203x_device::xor3sti, |
| 6855 | | &tms3203x_device::xor3sti, &tms3203x_device::xor3sti, &tms3203x_device::xor3sti, &tms3203x_device::xor3sti, |
| 6856 | | &tms3203x_device::xor3sti, &tms3203x_device::xor3sti, &tms3203x_device::xor3sti, &tms3203x_device::xor3sti, |
| 6857 | | &tms3203x_device::xor3sti, &tms3203x_device::xor3sti, &tms3203x_device::xor3sti, &tms3203x_device::xor3sti, |
| 6858 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, // 0x1e0 |
| 6859 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6860 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6861 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6862 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6863 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6864 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6865 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6866 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, // 0x1e8 |
| 6867 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6868 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6869 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6870 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6871 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6872 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6873 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6874 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, // 0x1f0 |
| 6875 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6876 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6877 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6878 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6879 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6880 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6881 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6882 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, // 0x1f8 |
| 6883 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6884 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6885 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6886 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6887 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6888 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6889 | | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal |
| 6890 | | }; |
trunk/src/devices/cpu/tms32031/32031ops.inc
| r0 | r250222 | |
|---|
| 1 | // license:BSD-3-Clause |
| 2 | // copyright-holders:Aaron Giles |
| 3 | /*************************************************************************** |
| 4 | |
| 5 | 32031ops.cpp |
| 6 | |
| 7 | TMS32031/2 emulator |
| 8 | |
| 9 | ***************************************************************************/ |
| 10 | |
| 11 | |
| 12 | //************************************************************************** |
| 13 | // COMPILE-TIME OPTIONS |
| 14 | //************************************************************************** |
| 15 | |
| 16 | #define USE_FP 0 |
| 17 | |
| 18 | |
| 19 | |
| 20 | //************************************************************************** |
| 21 | // MACROS |
| 22 | //************************************************************************** |
| 23 | |
| 24 | #define IREG(rnum) (m_r[rnum].i32[0]) |
| 25 | #define FREGEXP(rnum) (m_r[rnum].exponent()) |
| 26 | #define FREGMAN(rnum) (m_r[rnum].mantissa()) |
| 27 | |
| 28 | #define FP2LONG(rnum) ((FREGEXP(rnum) << 24) | ((UINT32)FREGMAN(rnum) >> 8)) |
| 29 | #define LONG2FP(rnum,v) do { m_r[rnum].set_mantissa((v) << 8); m_r[rnum].set_exponent((INT32)(v) >> 24); } while (0) |
| 30 | #define SHORT2FP(rnum,v) do { \ |
| 31 | if ((UINT16)(v) == 0x8000) { m_r[rnum].set_mantissa(0); m_r[rnum].set_exponent(-128); } \ |
| 32 | else { m_r[rnum].set_mantissa((v) << 20); m_r[rnum].set_exponent((INT16)(v) >> 12); } \ |
| 33 | } while (0) |
| 34 | |
| 35 | #define DIRECT(op) (((IREG(TMR_DP) & 0xff) << 16) | ((UINT16)op)) |
| 36 | #define INDIRECT_D(op,o) ((this->*s_indirect_d[((o) >> 3) & 31])(op,o)) |
| 37 | #define INDIRECT_1(op,o) ((this->*s_indirect_1[((o) >> 3) & 31])(op,o)) |
| 38 | #define INDIRECT_1_DEF(op,o) ((this->*s_indirect_1_def[((o) >> 3) & 31])(op,o,defptr)) |
| 39 | |
| 40 | #define SIGN(val) ((val) & 0x80000000) |
| 41 | |
| 42 | #define OVERFLOW_SUB(a,b,r) ((INT32)(((a) ^ (b)) & ((a) ^ (r))) < 0) |
| 43 | #define OVERFLOW_ADD(a,b,r) ((INT32)(((a) ^ (r)) & ((b) ^ (r))) < 0) |
| 44 | |
| 45 | #define CLR_FLAGS(f) do { IREG(TMR_ST) &= ~(f); } while (0) |
| 46 | #define CLR_NVUF() CLR_FLAGS(NFLAG | VFLAG | UFFLAG) |
| 47 | #define CLR_NZVUF() CLR_FLAGS(NFLAG | ZFLAG | VFLAG | UFFLAG) |
| 48 | #define CLR_NZCVUF() CLR_FLAGS(NFLAG | ZFLAG | VFLAG | CFLAG | UFFLAG) |
| 49 | |
| 50 | #define OR_C(flag) do { IREG(TMR_ST) |= flag & CFLAG; } while (0) |
| 51 | #define OR_NZ(val) do { IREG(TMR_ST) |= (((val) >> 28) & NFLAG) | (((val) == 0) << 2); } while (0) |
| 52 | #define OR_NZF(reg) do { IREG(TMR_ST) |= ((reg.mantissa() >> 28) & NFLAG) | ((reg.exponent() == -128) << 2); } while (0) |
| 53 | #define OR_NUF(reg) do { int temp = (reg.exponent() == -128) << 4; IREG(TMR_ST) |= ((reg.mantissa() >> 28) & NFLAG) | (temp) | (temp << 2); } while (0) |
| 54 | #define OR_V_SUB(a,b,r) do { UINT32 temp = ((((a) ^ (b)) & ((a) ^ (r))) >> 30) & VFLAG; IREG(TMR_ST) |= temp | (temp << 4); } while (0) |
| 55 | #define OR_V_ADD(a,b,r) do { UINT32 temp = ((((a) ^ (r)) & ((b) ^ (r))) >> 30) & VFLAG; IREG(TMR_ST) |= temp | (temp << 4); } while (0) |
| 56 | #define OR_C_SUB(a,b,r) do { IREG(TMR_ST) |= ((UINT32)(b) > (UINT32)(a)); } while (0) |
| 57 | #define OR_C_ADD(a,b,r) do { IREG(TMR_ST) |= ((UINT32)(a) > (UINT32)(r)); } while (0) |
| 58 | #define OR_C_SBB(a,b,c) do { INT64 temp = (INT64)(a) - (UINT32)(b) - (UINT32)(c); IREG(TMR_ST) |= (temp < 0); } while (0) |
| 59 | #define OR_C_ADC(a,b,c) do { UINT64 temp = (UINT64)(a) + (UINT32)(b) + (UINT32)(c); IREG(TMR_ST) |= (temp > 0xffffffff); } while (0) |
| 60 | |
| 61 | #define OVM() (IREG(TMR_ST) & OVMFLAG) |
| 62 | |
| 63 | #define DECLARE_DEF UINT32 defval; UINT32 *defptr = &defval |
| 64 | #define UPDATE_DEF() *defptr = defval |
| 65 | |
| 66 | |
| 67 | |
| 68 | //************************************************************************** |
| 69 | // IMPLEMENTATION |
| 70 | //************************************************************************** |
| 71 | |
| 72 | void tms3203x_device::illegal(UINT32 op) |
| 73 | { |
| 74 | if ((machine().debug_flags & DEBUG_FLAG_ENABLED) != 0) |
| 75 | { |
| 76 | logerror("Illegal op @ %06X: %08X (tbl=%03X)\n", m_pc - 1, op, op >> 21); |
| 77 | debugger_break(machine()); |
| 78 | } |
| 79 | } |
| 80 | |
| 81 | |
| 82 | void tms3203x_device::unimplemented(UINT32 op) |
| 83 | { |
| 84 | fatalerror("Unimplemented op @ %06X: %08X (tbl=%03X)\n", m_pc - 1, op, op >> 21); |
| 85 | } |
| 86 | |
| 87 | |
| 88 | inline void tms3203x_device::execute_one() |
| 89 | { |
| 90 | UINT32 op = ROPCODE(m_pc); |
| 91 | m_icount -= 2; // 2 clocks per cycle |
| 92 | m_pc++; |
| 93 | #if (TMS_3203X_LOG_OPCODE_USAGE) |
| 94 | m_hits[op >> 21]++; |
| 95 | #endif |
| 96 | (this->*s_tms32031ops[op >> 21])(op); |
| 97 | } |
| 98 | |
| 99 | |
| 100 | void tms3203x_device::update_special(int dreg) |
| 101 | { |
| 102 | if (dreg == TMR_BK) |
| 103 | { |
| 104 | UINT32 temp = IREG(TMR_BK); |
| 105 | m_bkmask = temp; |
| 106 | while (temp >>= 1) |
| 107 | m_bkmask |= temp; |
| 108 | } |
| 109 | else if (dreg == TMR_IOF) |
| 110 | { |
| 111 | if (IREG(TMR_IOF) & 0x002) |
| 112 | m_xf0_cb((offs_t)0, (IREG(TMR_IOF) >> 2) & 1); |
| 113 | if (IREG(TMR_IOF) & 0x020) |
| 114 | m_xf1_cb((offs_t)0, (IREG(TMR_IOF) >> 6) & 1); |
| 115 | } |
| 116 | else if (dreg == TMR_ST || dreg == TMR_IF || dreg == TMR_IE) |
| 117 | check_irqs(); |
| 118 | } |
| 119 | |
| 120 | |
| 121 | |
| 122 | //************************************************************************** |
| 123 | // CONDITION CODES |
| 124 | //************************************************************************** |
| 125 | |
| 126 | const UINT32 C_LO = 1 << 1; |
| 127 | const UINT32 C_LS = 1 << 2; |
| 128 | const UINT32 C_HI = 1 << 3; |
| 129 | const UINT32 C_HS = 1 << 4; |
| 130 | const UINT32 C_EQ = 1 << 5; |
| 131 | const UINT32 C_NE = 1 << 6; |
| 132 | const UINT32 C_LT = 1 << 7; |
| 133 | const UINT32 C_LE = 1 << 8; |
| 134 | const UINT32 C_GT = 1 << 9; |
| 135 | const UINT32 C_GE = 1 << 10; |
| 136 | const UINT32 C_NV = 1 << 12; |
| 137 | const UINT32 C_V = 1 << 13; |
| 138 | const UINT32 C_NUF = 1 << 14; |
| 139 | const UINT32 C_UF = 1 << 15; |
| 140 | const UINT32 C_NLV = 1 << 16; |
| 141 | const UINT32 C_LV = 1 << 17; |
| 142 | const UINT32 C_NLUF = 1 << 18; |
| 143 | const UINT32 C_LUF = 1 << 19; |
| 144 | const UINT32 C_ZUF = 1 << 20; |
| 145 | |
| 146 | const UINT32 condition_table[0x80] = |
| 147 | { |
| 148 | /* ------- */ 1 | C_HI | C_HS | C_NE | C_GT | C_GE | C_NV | C_NUF | C_NLV | C_NLUF, |
| 149 | /* ------C */ 1 | C_LO | C_LS | C_NE | C_GT | C_GE | C_NV | C_NUF | C_NLV | C_NLUF, |
| 150 | /* -----V- */ 1 | C_HI | C_HS | C_NE | C_GT | C_GE | C_V | C_NUF | C_NLV | C_NLUF, |
| 151 | /* -----VC */ 1 | C_LO | C_LS | C_NE | C_GT | C_GE | C_V | C_NUF | C_NLV | C_NLUF, |
| 152 | /* ----Z-- */ 1 | C_LS | C_HS | C_EQ | C_LE | C_GE | C_NV | C_NUF | C_NLV | C_NLUF | C_ZUF, |
| 153 | /* ----Z-C */ 1 | C_LO | C_LS | C_EQ | C_LE | C_GE | C_NV | C_NUF | C_NLV | C_NLUF | C_ZUF, |
| 154 | /* ----ZV- */ 1 | C_LS | C_HS | C_EQ | C_LE | C_GE | C_V | C_NUF | C_NLV | C_NLUF | C_ZUF, |
| 155 | /* ----ZVC */ 1 | C_LO | C_LS | C_EQ | C_LE | C_GE | C_V | C_NUF | C_NLV | C_NLUF | C_ZUF, |
| 156 | /* ---N--- */ 1 | C_HI | C_HS | C_NE | C_LT | C_LE | C_NV | C_NUF | C_NLV | C_NLUF, |
| 157 | /* ---N--C */ 1 | C_LO | C_LS | C_NE | C_LT | C_LE | C_NV | C_NUF | C_NLV | C_NLUF, |
| 158 | /* ---N-V- */ 1 | C_HI | C_HS | C_NE | C_LT | C_LE | C_V | C_NUF | C_NLV | C_NLUF, |
| 159 | /* ---N-VC */ 1 | C_LO | C_LS | C_NE | C_LT | C_LE | C_V | C_NUF | C_NLV | C_NLUF, |
| 160 | /* ---NZ-- */ 1 | C_LS | C_HS | C_EQ | C_LT | C_LE | C_NV | C_NUF | C_NLV | C_NLUF | C_ZUF, |
| 161 | /* ---NZ-C */ 1 | C_LO | C_LS | C_EQ | C_LT | C_LE | C_NV | C_NUF | C_NLV | C_NLUF | C_ZUF, |
| 162 | /* ---NZV- */ 1 | C_LS | C_HS | C_EQ | C_LT | C_LE | C_V | C_NUF | C_NLV | C_NLUF | C_ZUF, |
| 163 | /* ---NZVC */ 1 | C_LO | C_LS | C_EQ | C_LT | C_LE | C_V | C_NUF | C_NLV | C_NLUF | C_ZUF, |
| 164 | /* --U---- */ 1 | C_HI | C_HS | C_NE | C_GT | C_GE | C_NV | C_UF | C_NLV | C_NLUF | C_ZUF, |
| 165 | /* --U---C */ 1 | C_LO | C_LS | C_NE | C_GT | C_GE | C_NV | C_UF | C_NLV | C_NLUF | C_ZUF, |
| 166 | /* --U--V- */ 1 | C_HI | C_HS | C_NE | C_GT | C_GE | C_V | C_UF | C_NLV | C_NLUF | C_ZUF, |
| 167 | /* --U--VC */ 1 | C_LO | C_LS | C_NE | C_GT | C_GE | C_V | C_UF | C_NLV | C_NLUF | C_ZUF, |
| 168 | /* --U-Z-- */ 1 | C_LS | C_HS | C_EQ | C_LE | C_GE | C_NV | C_UF | C_NLV | C_NLUF | C_ZUF, |
| 169 | /* --U-Z-C */ 1 | C_LO | C_LS | C_EQ | C_LE | C_GE | C_NV | C_UF | C_NLV | C_NLUF | C_ZUF, |
| 170 | /* --U-ZV- */ 1 | C_LS | C_HS | C_EQ | C_LE | C_GE | C_V | C_UF | C_NLV | C_NLUF | C_ZUF, |
| 171 | /* --U-ZVC */ 1 | C_LO | C_LS | C_EQ | C_LE | C_GE | C_V | C_UF | C_NLV | C_NLUF | C_ZUF, |
| 172 | /* --UN--- */ 1 | C_HI | C_HS | C_NE | C_LT | C_LE | C_NV | C_UF | C_NLV | C_NLUF | C_ZUF, |
| 173 | /* --UN--C */ 1 | C_LO | C_LS | C_NE | C_LT | C_LE | C_NV | C_UF | C_NLV | C_NLUF | C_ZUF, |
| 174 | /* --UN-V- */ 1 | C_HI | C_HS | C_NE | C_LT | C_LE | C_V | C_UF | C_NLV | C_NLUF | C_ZUF, |
| 175 | /* --UN-VC */ 1 | C_LO | C_LS | C_NE | C_LT | C_LE | C_V | C_UF | C_NLV | C_NLUF | C_ZUF, |
| 176 | /* --UNZ-- */ 1 | C_LS | C_HS | C_EQ | C_LT | C_LE | C_NV | C_UF | C_NLV | C_NLUF | C_ZUF, |
| 177 | /* --UNZ-C */ 1 | C_LO | C_LS | C_EQ | C_LT | C_LE | C_NV | C_UF | C_NLV | C_NLUF | C_ZUF, |
| 178 | /* --UNZV- */ 1 | C_LS | C_HS | C_EQ | C_LT | C_LE | C_V | C_UF | C_NLV | C_NLUF | C_ZUF, |
| 179 | /* --UNZVC */ 1 | C_LO | C_LS | C_EQ | C_LT | C_LE | C_V | C_UF | C_NLV | C_NLUF | C_ZUF, |
| 180 | /* -v----- */ 1 | C_HI | C_HS | C_NE | C_GT | C_GE | C_NV | C_NUF | C_LV | C_NLUF, |
| 181 | /* -v----C */ 1 | C_LO | C_LS | C_NE | C_GT | C_GE | C_NV | C_NUF | C_LV | C_NLUF, |
| 182 | /* -v---V- */ 1 | C_HI | C_HS | C_NE | C_GT | C_GE | C_V | C_NUF | C_LV | C_NLUF, |
| 183 | /* -v---VC */ 1 | C_LO | C_LS | C_NE | C_GT | C_GE | C_V | C_NUF | C_LV | C_NLUF, |
| 184 | /* -v--Z-- */ 1 | C_LS | C_HS | C_EQ | C_LE | C_GE | C_NV | C_NUF | C_LV | C_NLUF | C_ZUF, |
| 185 | /* -v--Z-C */ 1 | C_LO | C_LS | C_EQ | C_LE | C_GE | C_NV | C_NUF | C_LV | C_NLUF | C_ZUF, |
| 186 | /* -v--ZV- */ 1 | C_LS | C_HS | C_EQ | C_LE | C_GE | C_V | C_NUF | C_LV | C_NLUF | C_ZUF, |
| 187 | /* -v--ZVC */ 1 | C_LO | C_LS | C_EQ | C_LE | C_GE | C_V | C_NUF | C_LV | C_NLUF | C_ZUF, |
| 188 | /* -v-N--- */ 1 | C_HI | C_HS | C_NE | C_LT | C_LE | C_NV | C_NUF | C_LV | C_NLUF, |
| 189 | /* -v-N--C */ 1 | C_LO | C_LS | C_NE | C_LT | C_LE | C_NV | C_NUF | C_LV | C_NLUF, |
| 190 | /* -v-N-V- */ 1 | C_HI | C_HS | C_NE | C_LT | C_LE | C_V | C_NUF | C_LV | C_NLUF, |
| 191 | /* -v-N-VC */ 1 | C_LO | C_LS | C_NE | C_LT | C_LE | C_V | C_NUF | C_LV | C_NLUF, |
| 192 | /* -v-NZ-- */ 1 | C_LS | C_HS | C_EQ | C_LT | C_LE | C_NV | C_NUF | C_LV | C_NLUF | C_ZUF, |
| 193 | /* -v-NZ-C */ 1 | C_LO | C_LS | C_EQ | C_LT | C_LE | C_NV | C_NUF | C_LV | C_NLUF | C_ZUF, |
| 194 | /* -v-NZV- */ 1 | C_LS | C_HS | C_EQ | C_LT | C_LE | C_V | C_NUF | C_LV | C_NLUF | C_ZUF, |
| 195 | /* -v-NZVC */ 1 | C_LO | C_LS | C_EQ | C_LT | C_LE | C_V | C_NUF | C_LV | C_NLUF | C_ZUF, |
| 196 | /* -vU---- */ 1 | C_HI | C_HS | C_NE | C_GT | C_GE | C_NV | C_UF | C_LV | C_NLUF | C_ZUF, |
| 197 | /* -vU---C */ 1 | C_LO | C_LS | C_NE | C_GT | C_GE | C_NV | C_UF | C_LV | C_NLUF | C_ZUF, |
| 198 | /* -vU--V- */ 1 | C_HI | C_HS | C_NE | C_GT | C_GE | C_V | C_UF | C_LV | C_NLUF | C_ZUF, |
| 199 | /* -vU--VC */ 1 | C_LO | C_LS | C_NE | C_GT | C_GE | C_V | C_UF | C_LV | C_NLUF | C_ZUF, |
| 200 | /* -vU-Z-- */ 1 | C_LS | C_HS | C_EQ | C_LE | C_GE | C_NV | C_UF | C_LV | C_NLUF | C_ZUF, |
| 201 | /* -vU-Z-C */ 1 | C_LO | C_LS | C_EQ | C_LE | C_GE | C_NV | C_UF | C_LV | C_NLUF | C_ZUF, |
| 202 | /* -vU-ZV- */ 1 | C_LS | C_HS | C_EQ | C_LE | C_GE | C_V | C_UF | C_LV | C_NLUF | C_ZUF, |
| 203 | /* -vU-ZVC */ 1 | C_LO | C_LS | C_EQ | C_LE | C_GE | C_V | C_UF | C_LV | C_NLUF | C_ZUF, |
| 204 | /* -vUN--- */ 1 | C_HI | C_HS | C_NE | C_LT | C_LE | C_NV | C_UF | C_LV | C_NLUF | C_ZUF, |
| 205 | /* -vUN--C */ 1 | C_LO | C_LS | C_NE | C_LT | C_LE | C_NV | C_UF | C_LV | C_NLUF | C_ZUF, |
| 206 | /* -vUN-V- */ 1 | C_HI | C_HS | C_NE | C_LT | C_LE | C_V | C_UF | C_LV | C_NLUF | C_ZUF, |
| 207 | /* -vUN-VC */ 1 | C_LO | C_LS | C_NE | C_LT | C_LE | C_V | C_UF | C_LV | C_NLUF | C_ZUF, |
| 208 | /* -vUNZ-- */ 1 | C_LS | C_HS | C_EQ | C_LT | C_LE | C_NV | C_UF | C_LV | C_NLUF | C_ZUF, |
| 209 | /* -vUNZ-C */ 1 | C_LO | C_LS | C_EQ | C_LT | C_LE | C_NV | C_UF | C_LV | C_NLUF | C_ZUF, |
| 210 | /* -vUNZV- */ 1 | C_LS | C_HS | C_EQ | C_LT | C_LE | C_V | C_UF | C_LV | C_NLUF | C_ZUF, |
| 211 | /* -vUNZVC */ 1 | C_LO | C_LS | C_EQ | C_LT | C_LE | C_V | C_UF | C_LV | C_NLUF | C_ZUF, |
| 212 | /* u------ */ 1 | C_HI | C_HS | C_NE | C_GT | C_GE | C_NV | C_NUF | C_NLV | C_LUF, |
| 213 | /* u-----C */ 1 | C_LO | C_LS | C_NE | C_GT | C_GE | C_NV | C_NUF | C_NLV | C_LUF, |
| 214 | /* u----V- */ 1 | C_HI | C_HS | C_NE | C_GT | C_GE | C_V | C_NUF | C_NLV | C_LUF, |
| 215 | /* u----VC */ 1 | C_LO | C_LS | C_NE | C_GT | C_GE | C_V | C_NUF | C_NLV | C_LUF, |
| 216 | /* u---Z-- */ 1 | C_LS | C_HS | C_EQ | C_LE | C_GE | C_NV | C_NUF | C_NLV | C_LUF | C_ZUF, |
| 217 | /* u---Z-C */ 1 | C_LO | C_LS | C_EQ | C_LE | C_GE | C_NV | C_NUF | C_NLV | C_LUF | C_ZUF, |
| 218 | /* u---ZV- */ 1 | C_LS | C_HS | C_EQ | C_LE | C_GE | C_V | C_NUF | C_NLV | C_LUF | C_ZUF, |
| 219 | /* u---ZVC */ 1 | C_LO | C_LS | C_EQ | C_LE | C_GE | C_V | C_NUF | C_NLV | C_LUF | C_ZUF, |
| 220 | /* u--N--- */ 1 | C_HI | C_HS | C_NE | C_LT | C_LE | C_NV | C_NUF | C_NLV | C_LUF, |
| 221 | /* u--N--C */ 1 | C_LO | C_LS | C_NE | C_LT | C_LE | C_NV | C_NUF | C_NLV | C_LUF, |
| 222 | /* u--N-V- */ 1 | C_HI | C_HS | C_NE | C_LT | C_LE | C_V | C_NUF | C_NLV | C_LUF, |
| 223 | /* u--N-VC */ 1 | C_LO | C_LS | C_NE | C_LT | C_LE | C_V | C_NUF | C_NLV | C_LUF, |
| 224 | /* u--NZ-- */ 1 | C_LS | C_HS | C_EQ | C_LT | C_LE | C_NV | C_NUF | C_NLV | C_LUF | C_ZUF, |
| 225 | /* u--NZ-C */ 1 | C_LO | C_LS | C_EQ | C_LT | C_LE | C_NV | C_NUF | C_NLV | C_LUF | C_ZUF, |
| 226 | /* u--NZV- */ 1 | C_LS | C_HS | C_EQ | C_LT | C_LE | C_V | C_NUF | C_NLV | C_LUF | C_ZUF, |
| 227 | /* u--NZVC */ 1 | C_LO | C_LS | C_EQ | C_LT | C_LE | C_V | C_NUF | C_NLV | C_LUF | C_ZUF, |
| 228 | /* u-U---- */ 1 | C_HI | C_HS | C_NE | C_GT | C_GE | C_NV | C_UF | C_NLV | C_LUF | C_ZUF, |
| 229 | /* u-U---C */ 1 | C_LO | C_LS | C_NE | C_GT | C_GE | C_NV | C_UF | C_NLV | C_LUF | C_ZUF, |
| 230 | /* u-U--V- */ 1 | C_HI | C_HS | C_NE | C_GT | C_GE | C_V | C_UF | C_NLV | C_LUF | C_ZUF, |
| 231 | /* u-U--VC */ 1 | C_LO | C_LS | C_NE | C_GT | C_GE | C_V | C_UF | C_NLV | C_LUF | C_ZUF, |
| 232 | /* u-U-Z-- */ 1 | C_LS | C_HS | C_EQ | C_LE | C_GE | C_NV | C_UF | C_NLV | C_LUF | C_ZUF, |
| 233 | /* u-U-Z-C */ 1 | C_LO | C_LS | C_EQ | C_LE | C_GE | C_NV | C_UF | C_NLV | C_LUF | C_ZUF, |
| 234 | /* u-U-ZV- */ 1 | C_LS | C_HS | C_EQ | C_LE | C_GE | C_V | C_UF | C_NLV | C_LUF | C_ZUF, |
| 235 | /* u-U-ZVC */ 1 | C_LO | C_LS | C_EQ | C_LE | C_GE | C_V | C_UF | C_NLV | C_LUF | C_ZUF, |
| 236 | /* u-UN--- */ 1 | C_HI | C_HS | C_NE | C_LT | C_LE | C_NV | C_UF | C_NLV | C_LUF | C_ZUF, |
| 237 | /* u-UN--C */ 1 | C_LO | C_LS | C_NE | C_LT | C_LE | C_NV | C_UF | C_NLV | C_LUF | C_ZUF, |
| 238 | /* u-UN-V- */ 1 | C_HI | C_HS | C_NE | C_LT | C_LE | C_V | C_UF | C_NLV | C_LUF | C_ZUF, |
| 239 | /* u-UN-VC */ 1 | C_LO | C_LS | C_NE | C_LT | C_LE | C_V | C_UF | C_NLV | C_LUF | C_ZUF, |
| 240 | /* u-UNZ-- */ 1 | C_LS | C_HS | C_EQ | C_LT | C_LE | C_NV | C_UF | C_NLV | C_LUF | C_ZUF, |
| 241 | /* u-UNZ-C */ 1 | C_LO | C_LS | C_EQ | C_LT | C_LE | C_NV | C_UF | C_NLV | C_LUF | C_ZUF, |
| 242 | /* u-UNZV- */ 1 | C_LS | C_HS | C_EQ | C_LT | C_LE | C_V | C_UF | C_NLV | C_LUF | C_ZUF, |
| 243 | /* u-UNZVC */ 1 | C_LO | C_LS | C_EQ | C_LT | C_LE | C_V | C_UF | C_NLV | C_LUF | C_ZUF, |
| 244 | /* uv----- */ 1 | C_HI | C_HS | C_NE | C_GT | C_GE | C_NV | C_NUF | C_LV | C_LUF, |
| 245 | /* uv----C */ 1 | C_LO | C_LS | C_NE | C_GT | C_GE | C_NV | C_NUF | C_LV | C_LUF, |
| 246 | /* uv---V- */ 1 | C_HI | C_HS | C_NE | C_GT | C_GE | C_V | C_NUF | C_LV | C_LUF, |
| 247 | /* uv---VC */ 1 | C_LO | C_LS | C_NE | C_GT | C_GE | C_V | C_NUF | C_LV | C_LUF, |
| 248 | /* uv--Z-- */ 1 | C_LS | C_HS | C_EQ | C_LE | C_GE | C_NV | C_NUF | C_LV | C_LUF | C_ZUF, |
| 249 | /* uv--Z-C */ 1 | C_LO | C_LS | C_EQ | C_LE | C_GE | C_NV | C_NUF | C_LV | C_LUF | C_ZUF, |
| 250 | /* uv--ZV- */ 1 | C_LS | C_HS | C_EQ | C_LE | C_GE | C_V | C_NUF | C_LV | C_LUF | C_ZUF, |
| 251 | /* uv--ZVC */ 1 | C_LO | C_LS | C_EQ | C_LE | C_GE | C_V | C_NUF | C_LV | C_LUF | C_ZUF, |
| 252 | /* uv-N--- */ 1 | C_HI | C_HS | C_NE | C_LT | C_LE | C_NV | C_NUF | C_LV | C_LUF, |
| 253 | /* uv-N--C */ 1 | C_LO | C_LS | C_NE | C_LT | C_LE | C_NV | C_NUF | C_LV | C_LUF, |
| 254 | /* uv-N-V- */ 1 | C_HI | C_HS | C_NE | C_LT | C_LE | C_V | C_NUF | C_LV | C_LUF, |
| 255 | /* uv-N-VC */ 1 | C_LO | C_LS | C_NE | C_LT | C_LE | C_V | C_NUF | C_LV | C_LUF, |
| 256 | /* uv-NZ-- */ 1 | C_LS | C_HS | C_EQ | C_LT | C_LE | C_NV | C_NUF | C_LV | C_LUF | C_ZUF, |
| 257 | /* uv-NZ-C */ 1 | C_LO | C_LS | C_EQ | C_LT | C_LE | C_NV | C_NUF | C_LV | C_LUF | C_ZUF, |
| 258 | /* uv-NZV- */ 1 | C_LS | C_HS | C_EQ | C_LT | C_LE | C_V | C_NUF | C_LV | C_LUF | C_ZUF, |
| 259 | /* uv-NZVC */ 1 | C_LO | C_LS | C_EQ | C_LT | C_LE | C_V | C_NUF | C_LV | C_LUF | C_ZUF, |
| 260 | /* uvU---- */ 1 | C_HI | C_HS | C_NE | C_GT | C_GE | C_NV | C_UF | C_LV | C_LUF | C_ZUF, |
| 261 | /* uvU---C */ 1 | C_LO | C_LS | C_NE | C_GT | C_GE | C_NV | C_UF | C_LV | C_LUF | C_ZUF, |
| 262 | /* uvU--V- */ 1 | C_HI | C_HS | C_NE | C_GT | C_GE | C_V | C_UF | C_LV | C_LUF | C_ZUF, |
| 263 | /* uvU--VC */ 1 | C_LO | C_LS | C_NE | C_GT | C_GE | C_V | C_UF | C_LV | C_LUF | C_ZUF, |
| 264 | /* uvU-Z-- */ 1 | C_LS | C_HS | C_EQ | C_LE | C_GE | C_NV | C_UF | C_LV | C_LUF | C_ZUF, |
| 265 | /* uvU-Z-C */ 1 | C_LO | C_LS | C_EQ | C_LE | C_GE | C_NV | C_UF | C_LV | C_LUF | C_ZUF, |
| 266 | /* uvU-ZV- */ 1 | C_LS | C_HS | C_EQ | C_LE | C_GE | C_V | C_UF | C_LV | C_LUF | C_ZUF, |
| 267 | /* uvU-ZVC */ 1 | C_LO | C_LS | C_EQ | C_LE | C_GE | C_V | C_UF | C_LV | C_LUF | C_ZUF, |
| 268 | /* uvUN--- */ 1 | C_HI | C_HS | C_NE | C_LT | C_LE | C_NV | C_UF | C_LV | C_LUF | C_ZUF, |
| 269 | /* uvUN--C */ 1 | C_LO | C_LS | C_NE | C_LT | C_LE | C_NV | C_UF | C_LV | C_LUF | C_ZUF, |
| 270 | /* uvUN-V- */ 1 | C_HI | C_HS | C_NE | C_LT | C_LE | C_V | C_UF | C_LV | C_LUF | C_ZUF, |
| 271 | /* uvUN-VC */ 1 | C_LO | C_LS | C_NE | C_LT | C_LE | C_V | C_UF | C_LV | C_LUF | C_ZUF, |
| 272 | /* uvUNZ-- */ 1 | C_LS | C_HS | C_EQ | C_LT | C_LE | C_NV | C_UF | C_LV | C_LUF | C_ZUF, |
| 273 | /* uvUNZ-C */ 1 | C_LO | C_LS | C_EQ | C_LT | C_LE | C_NV | C_UF | C_LV | C_LUF | C_ZUF, |
| 274 | /* uvUNZV- */ 1 | C_LS | C_HS | C_EQ | C_LT | C_LE | C_V | C_UF | C_LV | C_LUF | C_ZUF, |
| 275 | /* uvUNZVC */ 1 | C_LO | C_LS | C_EQ | C_LT | C_LE | C_V | C_UF | C_LV | C_LUF | C_ZUF, |
| 276 | }; |
| 277 | |
| 278 | #define CONDITION_LO() (IREG(TMR_ST) & CFLAG) |
| 279 | #define CONDITION_LS() (IREG(TMR_ST) & (CFLAG | ZFLAG)) |
| 280 | #define CONDITION_HI() (!(IREG(TMR_ST) & (CFLAG | ZFLAG))) |
| 281 | #define CONDITION_HS() (!(IREG(TMR_ST) & CFLAG)) |
| 282 | #define CONDITION_EQ() (IREG(TMR_ST) & ZFLAG) |
| 283 | #define CONDITION_NE() (!(IREG(TMR_ST) & ZFLAG)) |
| 284 | #define CONDITION_LT() (IREG(TMR_ST) & NFLAG) |
| 285 | #define CONDITION_LE() (IREG(TMR_ST) & (NFLAG | ZFLAG)) |
| 286 | #define CONDITION_GT() (!(IREG(TMR_ST) & (NFLAG | ZFLAG))) |
| 287 | #define CONDITION_GE() (!(IREG(TMR_ST) & NFLAG)) |
| 288 | #define CONDITION_NV() (!(IREG(TMR_ST) & VFLAG)) |
| 289 | #define CONDITION_V() (IREG(TMR_ST) & VFLAG) |
| 290 | #define CONDITION_NUF() (!(IREG(TMR_ST) & UFFLAG)) |
| 291 | #define CONDITION_UF() (IREG(TMR_ST) & UFFLAG) |
| 292 | #define CONDITION_NLV() (!(IREG(TMR_ST) & LVFLAG)) |
| 293 | #define CONDITION_LV() (IREG(TMR_ST) & LVFLAG) |
| 294 | #define CONDITION_NLUF() (!(IREG(TMR_ST) & LUFFLAG)) |
| 295 | #define CONDITION_LUF() (IREG(TMR_ST) & LUFFLAG) |
| 296 | #define CONDITION_ZUF() (IREG(TMR_ST) & (UFFLAG | ZFLAG)) |
| 297 | |
| 298 | inline bool tms3203x_device::condition(int which) |
| 299 | { |
| 300 | return (condition_table[IREG(TMR_ST) & (LUFFLAG | LVFLAG | UFFLAG | NFLAG | ZFLAG | VFLAG | CFLAG)] >> (which & 31)) & 1; |
| 301 | } |
| 302 | |
| 303 | |
| 304 | |
| 305 | //************************************************************************** |
| 306 | // FLOATING POINT HELPERS |
| 307 | //************************************************************************** |
| 308 | |
| 309 | #if USE_FP |
| 310 | void tms3203x_device::double_to_dsp_with_flags(double val, tmsreg &result) |
| 311 | { |
| 312 | int_double id; |
| 313 | id.d = val; |
| 314 | |
| 315 | CLR_NZVUF(); |
| 316 | |
| 317 | int mantissa = ((id.i[BYTE_XOR_BE(0)] & 0x000fffff) << 11) | ((id.i[BYTE_XOR_BE(1)] & 0xffe00000) >> 21); |
| 318 | int exponent = ((id.i[BYTE_XOR_BE(0)] & 0x7ff00000) >> 20) - 1023; |
| 319 | if (exponent <= -128) |
| 320 | { |
| 321 | result.set_mantissa(0); |
| 322 | result.set_exponent(-128); |
| 323 | IREG(TMR_ST) |= UFFLAG | LUFFLAG | ZFLAG; |
| 324 | } |
| 325 | else if (exponent > 127) |
| 326 | { |
| 327 | if ((INT32)id.i[BYTE_XOR_BE(0)] >= 0) |
| 328 | result.set_mantissa(0x7fffffff); |
| 329 | else |
| 330 | { |
| 331 | result.set_mantissa(0x80000001); |
| 332 | IREG(TMR_ST) |= NFLAG; |
| 333 | } |
| 334 | result.set_exponent(127); |
| 335 | IREG(TMR_ST) |= VFLAG | LVFLAG; |
| 336 | } |
| 337 | else if (val == 0) |
| 338 | { |
| 339 | result.set_mantissa(0); |
| 340 | result.set_exponent(-128); |
| 341 | IREG(TMR_ST) |= ZFLAG; |
| 342 | } |
| 343 | else if ((INT32)id.i[BYTE_XOR_BE(0)] >= 0) |
| 344 | { |
| 345 | result.set_mantissa(mantissa); |
| 346 | result.set_exponent(exponent); |
| 347 | } |
| 348 | else if (mantissa != 0) |
| 349 | { |
| 350 | result.set_mantissa(0x80000000 | -mantissa); |
| 351 | result.set_exponent(exponent); |
| 352 | IREG(TMR_ST) |= NFLAG; |
| 353 | } |
| 354 | else |
| 355 | { |
| 356 | result.set_mantissa(0x80000000); |
| 357 | result.set_exponent(exponent - 1); |
| 358 | IREG(TMR_ST) |= NFLAG; |
| 359 | } |
| 360 | } |
| 361 | #endif |
| 362 | |
| 363 | // integer to floating point conversion |
| 364 | #if USE_FP |
| 365 | void tms3203x_device::int2float(tmsreg &srcdst) |
| 366 | { |
| 367 | double val = srcdst.mantissa(); |
| 368 | double_to_dsp_with_flags(val, srcdst); |
| 369 | } |
| 370 | #else |
| 371 | void tms3203x_device::int2float(tmsreg &srcdst) |
| 372 | { |
| 373 | UINT32 man = srcdst.mantissa(); |
| 374 | int exp, cnt; |
| 375 | |
| 376 | // never overflows or underflows |
| 377 | CLR_NZVUF(); |
| 378 | |
| 379 | // 0 always has exponent of -128 |
| 380 | if (man == 0) |
| 381 | { |
| 382 | man = 0x80000000; |
| 383 | exp = -128; |
| 384 | } |
| 385 | |
| 386 | // check for -1 here because count_leading_ones will infinite loop |
| 387 | else if (man == (UINT32)-1) |
| 388 | { |
| 389 | man = 0; |
| 390 | exp = -1; |
| 391 | } |
| 392 | |
| 393 | // positive values; count leading zeros and shift |
| 394 | else if ((INT32)man > 0) |
| 395 | { |
| 396 | cnt = count_leading_zeros(man); |
| 397 | man <<= cnt; |
| 398 | exp = 31 - cnt; |
| 399 | } |
| 400 | |
| 401 | // negative values; count leading ones and shift |
| 402 | else |
| 403 | { |
| 404 | cnt = count_leading_ones(man); |
| 405 | man <<= cnt; |
| 406 | exp = 31 - cnt; |
| 407 | } |
| 408 | |
| 409 | // set the final results and compute NZ |
| 410 | srcdst.set_mantissa(man ^ 0x80000000); |
| 411 | srcdst.set_exponent(exp); |
| 412 | OR_NZF(srcdst); |
| 413 | } |
| 414 | #endif |
| 415 | |
| 416 | |
| 417 | // floating point to integer conversion |
| 418 | #if USE_FP |
| 419 | void tms3203x_device::float2int(tmsreg &srcdst, int setflags) |
| 420 | { |
| 421 | INT32 val; |
| 422 | |
| 423 | if (setflags) CLR_NZVUF(); |
| 424 | if (srcdst.exponent() > 30) |
| 425 | { |
| 426 | if ((INT32)srcdst.mantissa() >= 0) |
| 427 | val = 0x7fffffff; |
| 428 | else |
| 429 | val = 0x80000000; |
| 430 | if (setflags) IREG(TMR_ST) |= VFLAG | LVFLAG; |
| 431 | } |
| 432 | else |
| 433 | val = floor(srcdst.as_double()); |
| 434 | srcdst.set_mantissa(val); |
| 435 | if (setflags) OR_NZ(val); |
| 436 | } |
| 437 | #else |
| 438 | void tms3203x_device::float2int(tmsreg &srcdst, bool setflags) |
| 439 | { |
| 440 | INT32 man = srcdst.mantissa(); |
| 441 | int shift = 31 - srcdst.exponent(); |
| 442 | |
| 443 | // never underflows |
| 444 | if (setflags) CLR_NZVUF(); |
| 445 | |
| 446 | // if we've got too much to handle, overflow |
| 447 | if (shift <= 0) |
| 448 | { |
| 449 | srcdst.set_mantissa((man >= 0) ? 0x7fffffff : 0x80000000); |
| 450 | if (setflags) IREG(TMR_ST) |= VFLAG | LVFLAG; |
| 451 | } |
| 452 | |
| 453 | // if we're too small, go to 0 or -1 |
| 454 | else if (shift > 31) |
| 455 | srcdst.set_mantissa(man >> 31); |
| 456 | |
| 457 | // we're in the middle; shift it |
| 458 | else |
| 459 | srcdst.set_mantissa((man >> shift) ^ (1 << (31 - shift))); |
| 460 | |
| 461 | // set the NZ flags |
| 462 | if (setflags) OR_NZ(srcdst.mantissa()); |
| 463 | } |
| 464 | #endif |
| 465 | |
| 466 | |
| 467 | // compute the negative of a floating point value |
| 468 | #if USE_FP |
| 469 | void tms3203x_device::negf(tmsreg &dst, tmsreg tmsreg &src) |
| 470 | { |
| 471 | double val = -src.as_double(); |
| 472 | double_to_dsp_with_flags(val, dst); |
| 473 | } |
| 474 | #else |
| 475 | void tms3203x_device::negf(tmsreg &dst, tmsreg &src) |
| 476 | { |
| 477 | INT32 man = src.mantissa(); |
| 478 | |
| 479 | CLR_NZVUF(); |
| 480 | |
| 481 | if (src.exponent() == -128) |
| 482 | { |
| 483 | dst.set_mantissa(0); |
| 484 | dst.set_exponent(-128); |
| 485 | } |
| 486 | else if ((man & 0x7fffffff) != 0) |
| 487 | { |
| 488 | dst.set_mantissa(-man); |
| 489 | dst.set_exponent(src.exponent()); |
| 490 | } |
| 491 | else |
| 492 | { |
| 493 | dst.set_mantissa(man ^ 0x80000000); |
| 494 | if (man == 0) |
| 495 | dst.set_exponent(src.exponent() - 1); |
| 496 | else |
| 497 | dst.set_exponent(src.exponent() + 1); |
| 498 | } |
| 499 | OR_NZF(dst); |
| 500 | } |
| 501 | #endif |
| 502 | |
| 503 | |
| 504 | |
| 505 | // add two floating point values |
| 506 | #if USE_FP |
| 507 | void tms3203x_device::addf(tmsreg &dst, tmsreg &src1, tmsreg &src2) |
| 508 | { |
| 509 | double val = src1.as_double() + src2.as_double(); |
| 510 | double_to_dsp_with_flags(val, dst); |
| 511 | } |
| 512 | #else |
| 513 | void tms3203x_device::addf(tmsreg &dst, tmsreg &src1, tmsreg &src2) |
| 514 | { |
| 515 | INT64 man; |
| 516 | INT64 m1, m2; |
| 517 | int exp, cnt; |
| 518 | |
| 519 | // reset over/underflow conditions |
| 520 | CLR_NZVUF(); |
| 521 | |
| 522 | // first check for 0 operands |
| 523 | if (src1.exponent() == -128) |
| 524 | { |
| 525 | dst = src2; |
| 526 | OR_NZF(dst); |
| 527 | return; |
| 528 | } |
| 529 | if (src2.exponent() == -128) |
| 530 | { |
| 531 | dst = src1; |
| 532 | OR_NZF(dst); |
| 533 | return; |
| 534 | } |
| 535 | |
| 536 | // extract mantissas from 1.0.31 values to 1.1.31 values |
| 537 | m1 = (INT64)src1.mantissa() ^ 0x80000000; |
| 538 | m2 = (INT64)src2.mantissa() ^ 0x80000000; |
| 539 | |
| 540 | // normalize based on the exponent |
| 541 | if (src1.exponent() > src2.exponent()) |
| 542 | { |
| 543 | exp = src1.exponent(); |
| 544 | cnt = exp - src2.exponent(); |
| 545 | if (cnt >= 32) |
| 546 | { |
| 547 | dst = src1; |
| 548 | OR_NZF(dst); |
| 549 | return; |
| 550 | } |
| 551 | m2 >>= cnt; |
| 552 | } |
| 553 | else |
| 554 | { |
| 555 | exp = src2.exponent(); |
| 556 | cnt = exp - src1.exponent(); |
| 557 | if (cnt >= 32) |
| 558 | { |
| 559 | dst = src2; |
| 560 | OR_NZF(dst); |
| 561 | return; |
| 562 | } |
| 563 | m1 >>= cnt; |
| 564 | } |
| 565 | |
| 566 | // add |
| 567 | man = m1 + m2; |
| 568 | |
| 569 | // if the mantissa is zero, set the exponent appropriately |
| 570 | if (man == 0 || exp == -128) |
| 571 | { |
| 572 | exp = -128; |
| 573 | man = 0x80000000; |
| 574 | } |
| 575 | |
| 576 | // if the mantissa is >= 2.0 or < -2.0, normalize |
| 577 | else if (man >= ((INT64)2 << 31) || man < ((INT64)-2 << 31)) |
| 578 | { |
| 579 | man >>= 1; |
| 580 | exp++; |
| 581 | } |
| 582 | |
| 583 | // if the mantissa is < 1.0 and > -1.0, normalize |
| 584 | else if (man < ((INT64)1 << 31) && man >= ((INT64)-1 << 31)) |
| 585 | { |
| 586 | if (man > 0) |
| 587 | { |
| 588 | cnt = count_leading_zeros((UINT32)man); |
| 589 | man <<= cnt; |
| 590 | exp -= cnt; |
| 591 | } |
| 592 | else |
| 593 | { |
| 594 | cnt = count_leading_ones((UINT32)man); |
| 595 | man <<= cnt; |
| 596 | exp -= cnt; |
| 597 | } |
| 598 | } |
| 599 | |
| 600 | // check for underflow |
| 601 | if (exp <= -128) |
| 602 | { |
| 603 | man = 0x80000000; |
| 604 | exp = -128; |
| 605 | IREG(TMR_ST) |= UFFLAG | LUFFLAG; |
| 606 | } |
| 607 | |
| 608 | // check for overflow |
| 609 | else if (exp > 127) |
| 610 | { |
| 611 | man = (man < 0) ? 0x00000000 : 0xffffffff; |
| 612 | exp = 127; |
| 613 | IREG(TMR_ST) |= VFLAG | LVFLAG; |
| 614 | } |
| 615 | |
| 616 | // store the result back, removing the implicit one and putting |
| 617 | // back the sign bit |
| 618 | dst.set_mantissa((UINT32)man ^ 0x80000000); |
| 619 | dst.set_exponent(exp); |
| 620 | OR_NZF(dst); |
| 621 | } |
| 622 | #endif |
| 623 | |
| 624 | |
| 625 | // subtract two floating point values |
| 626 | #if USE_FP |
| 627 | void tms3203x_device::subf(tmsreg &dst, tmsreg &src1, tmsreg &src2) |
| 628 | { |
| 629 | double val = src1.as_double() - src2.as_double(); |
| 630 | double_to_dsp_with_flags(val, dst); |
| 631 | } |
| 632 | #else |
| 633 | void tms3203x_device::subf(tmsreg &dst, tmsreg &src1, tmsreg &src2) |
| 634 | { |
| 635 | INT64 man; |
| 636 | INT64 m1, m2; |
| 637 | int exp, cnt; |
| 638 | |
| 639 | // reset over/underflow conditions |
| 640 | CLR_NZVUF(); |
| 641 | |
| 642 | // first check for 0 operands |
| 643 | if (src2.exponent() == -128) |
| 644 | { |
| 645 | dst = src1; |
| 646 | OR_NZF(dst); |
| 647 | return; |
| 648 | } |
| 649 | |
| 650 | // extract mantissas from 1.0.31 values to 1.1.31 values |
| 651 | m1 = (INT64)src1.mantissa() ^ 0x80000000; |
| 652 | m2 = (INT64)src2.mantissa() ^ 0x80000000; |
| 653 | |
| 654 | // normalize based on the exponent |
| 655 | if (src1.exponent() > src2.exponent()) |
| 656 | { |
| 657 | exp = src1.exponent(); |
| 658 | cnt = exp - src2.exponent(); |
| 659 | if (cnt >= 32) |
| 660 | { |
| 661 | dst = src1; |
| 662 | OR_NZF(dst); |
| 663 | return; |
| 664 | } |
| 665 | m2 >>= cnt; |
| 666 | } |
| 667 | else |
| 668 | { |
| 669 | exp = src2.exponent(); |
| 670 | cnt = exp - src1.exponent(); |
| 671 | if (cnt >= 32) |
| 672 | { |
| 673 | negf(dst, src2); |
| 674 | return; |
| 675 | } |
| 676 | m1 >>= cnt; |
| 677 | } |
| 678 | |
| 679 | // subtract |
| 680 | man = m1 - m2; |
| 681 | |
| 682 | // if the mantissa is zero, set the exponent appropriately |
| 683 | if (man == 0 || exp == -128) |
| 684 | { |
| 685 | exp = -128; |
| 686 | man = 0x80000000; |
| 687 | } |
| 688 | |
| 689 | // if the mantissa is >= 2.0 or < -2.0, normalize |
| 690 | else if (man >= ((INT64)2 << 31) || man < ((INT64)-2 << 31)) |
| 691 | { |
| 692 | man >>= 1; |
| 693 | exp++; |
| 694 | } |
| 695 | |
| 696 | // if the mantissa is < 1.0 and > -1.0, normalize |
| 697 | else if (man < ((INT64)1 << 31) && man >= ((INT64)-1 << 31)) |
| 698 | { |
| 699 | if (man > 0) |
| 700 | { |
| 701 | cnt = count_leading_zeros((UINT32)man); |
| 702 | man <<= cnt; |
| 703 | exp -= cnt; |
| 704 | } |
| 705 | else |
| 706 | { |
| 707 | cnt = count_leading_ones((UINT32)man); |
| 708 | man <<= cnt; |
| 709 | exp -= cnt; |
| 710 | } |
| 711 | } |
| 712 | |
| 713 | // check for underflow |
| 714 | if (exp <= -128) |
| 715 | { |
| 716 | // make sure a 0 result doesn't set underflow |
| 717 | if (man != 0 || exp < -128) |
| 718 | IREG(TMR_ST) |= UFFLAG | LUFFLAG; |
| 719 | man = 0x80000000; |
| 720 | exp = -128; |
| 721 | } |
| 722 | |
| 723 | // check for overflow |
| 724 | else if (exp > 127) |
| 725 | { |
| 726 | man = (man < 0) ? 0x00000000 : 0xffffffff; |
| 727 | exp = 127; |
| 728 | IREG(TMR_ST) |= VFLAG | LVFLAG; |
| 729 | } |
| 730 | |
| 731 | // store the result back, removing the implicit one and putting |
| 732 | // back the sign bit |
| 733 | dst.set_mantissa((UINT32)man ^ 0x80000000); |
| 734 | dst.set_exponent(exp); |
| 735 | OR_NZF(dst); |
| 736 | } |
| 737 | #endif |
| 738 | |
| 739 | |
| 740 | // multiply two floating point values |
| 741 | #if USE_FP |
| 742 | void tms3203x_device::mpyf(tmsreg &dst, tmsreg &src1, tmsreg &src2) |
| 743 | { |
| 744 | double val = (double)src1.as_float() * (double)src2.as_float(); |
| 745 | double_to_dsp_with_flags(val, dst); |
| 746 | } |
| 747 | #else |
| 748 | void tms3203x_device::mpyf(tmsreg &dst, tmsreg &src1, tmsreg &src2) |
| 749 | { |
| 750 | // reset over/underflow conditions |
| 751 | CLR_NZVUF(); |
| 752 | |
| 753 | // first check for 0 multipliers and return 0 in any case |
| 754 | if (src1.exponent() == -128 || src2.exponent() == -128) |
| 755 | { |
| 756 | dst.set_mantissa(0); |
| 757 | dst.set_exponent(-128); |
| 758 | OR_NZF(dst); |
| 759 | return; |
| 760 | } |
| 761 | |
| 762 | // convert the mantissas from 1.0.31 numbers to 1.1.23 numbers |
| 763 | INT32 m1 = (src1.mantissa() >> 8) ^ 0x800000; |
| 764 | INT32 m2 = (src2.mantissa() >> 8) ^ 0x800000; |
| 765 | |
| 766 | // multiply the mantissas and add the exponents |
| 767 | INT64 man = (INT64)m1 * (INT64)m2; |
| 768 | int exp = src1.exponent() + src2.exponent(); |
| 769 | |
| 770 | // chop off the low bits, going from 1.2.46 down to 1.2.31 |
| 771 | man >>= 46 - 31; |
| 772 | |
| 773 | // if the mantissa is zero, set the exponent appropriately |
| 774 | if (man == 0) |
| 775 | { |
| 776 | exp = -128; |
| 777 | man = 0x80000000; |
| 778 | } |
| 779 | |
| 780 | // if the mantissa is >= 2.0 or <= -2.0, normalize |
| 781 | else if (man >= ((INT64)2 << 31)) |
| 782 | { |
| 783 | man >>= 1; |
| 784 | exp++; |
| 785 | if (man >= ((INT64)2 << 31)) |
| 786 | { |
| 787 | man >>= 1; |
| 788 | exp++; |
| 789 | } |
| 790 | } |
| 791 | |
| 792 | // if the mantissa is >= 2.0 or <= -2.0, normalize |
| 793 | else if (man < ((INT64)-2 << 31)) |
| 794 | { |
| 795 | man >>= 1; |
| 796 | exp++; |
| 797 | } |
| 798 | |
| 799 | // check for underflow |
| 800 | if (exp <= -128) |
| 801 | { |
| 802 | man = 0x80000000; |
| 803 | exp = -128; |
| 804 | IREG(TMR_ST) |= UFFLAG | LUFFLAG; |
| 805 | } |
| 806 | |
| 807 | // check for overflow |
| 808 | else if (exp > 127) |
| 809 | { |
| 810 | man = (man < 0) ? 0x00000000 : 0xffffffff; |
| 811 | exp = 127; |
| 812 | IREG(TMR_ST) |= VFLAG | LVFLAG; |
| 813 | } |
| 814 | |
| 815 | // store the result back, removing the implicit one and putting |
| 816 | // back the sign bit |
| 817 | dst.set_mantissa((UINT32)man ^ 0x80000000); |
| 818 | dst.set_exponent(exp); |
| 819 | OR_NZF(dst); |
| 820 | } |
| 821 | #endif |
| 822 | |
| 823 | |
| 824 | // normalize a floating point value |
| 825 | #if USE_FP |
| 826 | void tms3203x_device::norm(tmsreg &dst, tmsreg &src) |
| 827 | { |
| 828 | fatalerror("norm not implemented\n"); |
| 829 | } |
| 830 | #else |
| 831 | void tms3203x_device::norm(tmsreg &dst, tmsreg &src) |
| 832 | { |
| 833 | INT32 man = src.mantissa(); |
| 834 | int exp = src.exponent(); |
| 835 | |
| 836 | CLR_NZVUF(); |
| 837 | |
| 838 | if (exp == -128 || man == 0) |
| 839 | { |
| 840 | dst.set_mantissa(0); |
| 841 | dst.set_exponent(-128); |
| 842 | if (man != 0) |
| 843 | IREG(TMR_ST) |= UFFLAG | LUFFLAG; |
| 844 | } |
| 845 | else |
| 846 | { |
| 847 | int cnt; |
| 848 | if (man > 0) |
| 849 | { |
| 850 | cnt = count_leading_zeros((UINT32)man); |
| 851 | man <<= cnt; |
| 852 | exp -= cnt; |
| 853 | } |
| 854 | else |
| 855 | { |
| 856 | cnt = count_leading_ones((UINT32)man); |
| 857 | man <<= cnt; |
| 858 | exp -= cnt; |
| 859 | } |
| 860 | |
| 861 | // check for underflow |
| 862 | if (exp <= -128) |
| 863 | { |
| 864 | man = 0x00000000; |
| 865 | exp = -128; |
| 866 | IREG(TMR_ST) |= UFFLAG | LUFFLAG; |
| 867 | } |
| 868 | } |
| 869 | |
| 870 | dst.set_mantissa(man); |
| 871 | dst.set_exponent(exp); |
| 872 | OR_NZF(dst); |
| 873 | } |
| 874 | #endif |
| 875 | |
| 876 | |
| 877 | |
| 878 | |
| 879 | //************************************************************************** |
| 880 | // INDIRECT MEMORY REFS |
| 881 | //************************************************************************** |
| 882 | |
| 883 | // immediate displacement variants |
| 884 | |
| 885 | UINT32 tms3203x_device::mod00_d(UINT32 op, UINT8 ar) |
| 886 | { |
| 887 | int reg = TMR_AR0 + (ar & 7); |
| 888 | return IREG(reg) + (UINT8)op; |
| 889 | } |
| 890 | |
| 891 | UINT32 tms3203x_device::mod01_d(UINT32 op, UINT8 ar) |
| 892 | { |
| 893 | int reg = TMR_AR0 + (ar & 7); |
| 894 | return IREG(reg) - (UINT8)op; |
| 895 | } |
| 896 | |
| 897 | UINT32 tms3203x_device::mod02_d(UINT32 op, UINT8 ar) |
| 898 | { |
| 899 | int reg = TMR_AR0 + (ar & 7); |
| 900 | IREG(reg) += (UINT8)op; |
| 901 | return IREG(reg); |
| 902 | } |
| 903 | |
| 904 | UINT32 tms3203x_device::mod03_d(UINT32 op, UINT8 ar) |
| 905 | { |
| 906 | int reg = TMR_AR0 + (ar & 7); |
| 907 | IREG(reg) -= (UINT8)op; |
| 908 | return IREG(reg); |
| 909 | } |
| 910 | |
| 911 | UINT32 tms3203x_device::mod04_d(UINT32 op, UINT8 ar) |
| 912 | { |
| 913 | int reg = TMR_AR0 + (ar & 7); |
| 914 | UINT32 result = IREG(reg); |
| 915 | IREG(reg) += (UINT8)op; |
| 916 | return result; |
| 917 | } |
| 918 | |
| 919 | UINT32 tms3203x_device::mod05_d(UINT32 op, UINT8 ar) |
| 920 | { |
| 921 | int reg = TMR_AR0 + (ar & 7); |
| 922 | UINT32 result = IREG(reg); |
| 923 | IREG(reg) -= (UINT8)op; |
| 924 | return result; |
| 925 | } |
| 926 | |
| 927 | UINT32 tms3203x_device::mod06_d(UINT32 op, UINT8 ar) |
| 928 | { |
| 929 | int reg = TMR_AR0 + (ar & 7); |
| 930 | UINT32 result = IREG(reg); |
| 931 | INT32 temp = (result & m_bkmask) + (UINT8)op; |
| 932 | if (temp >= IREG(TMR_BK)) |
| 933 | temp -= IREG(TMR_BK); |
| 934 | IREG(reg) = (IREG(reg) & ~m_bkmask) | (temp & m_bkmask); |
| 935 | return result; |
| 936 | } |
| 937 | |
| 938 | UINT32 tms3203x_device::mod07_d(UINT32 op, UINT8 ar) |
| 939 | { |
| 940 | int reg = TMR_AR0 + (ar & 7); |
| 941 | UINT32 result = IREG(reg); |
| 942 | INT32 temp = (result & m_bkmask) - (UINT8)op; |
| 943 | if (temp < 0) |
| 944 | temp += IREG(TMR_BK); |
| 945 | IREG(reg) = (IREG(reg) & ~m_bkmask) | (temp & m_bkmask); |
| 946 | return result; |
| 947 | } |
| 948 | |
| 949 | |
| 950 | // immediate displacement variants (implied 1) |
| 951 | |
| 952 | UINT32 tms3203x_device::mod00_1(UINT32 op, UINT8 ar) |
| 953 | { |
| 954 | int reg = TMR_AR0 + (ar & 7); |
| 955 | return IREG(reg) + 1; |
| 956 | } |
| 957 | |
| 958 | UINT32 tms3203x_device::mod01_1(UINT32 op, UINT8 ar) |
| 959 | { |
| 960 | int reg = TMR_AR0 + (ar & 7); |
| 961 | return IREG(reg) - 1; |
| 962 | } |
| 963 | |
| 964 | UINT32 tms3203x_device::mod02_1(UINT32 op, UINT8 ar) |
| 965 | { |
| 966 | int reg = TMR_AR0 + (ar & 7); |
| 967 | return ++IREG(reg); |
| 968 | } |
| 969 | |
| 970 | UINT32 tms3203x_device::mod03_1(UINT32 op, UINT8 ar) |
| 971 | { |
| 972 | int reg = TMR_AR0 + (ar & 7); |
| 973 | return --IREG(reg); |
| 974 | } |
| 975 | |
| 976 | UINT32 tms3203x_device::mod04_1(UINT32 op, UINT8 ar) |
| 977 | { |
| 978 | int reg = TMR_AR0 + (ar & 7); |
| 979 | return IREG(reg)++; |
| 980 | } |
| 981 | |
| 982 | UINT32 tms3203x_device::mod05_1(UINT32 op, UINT8 ar) |
| 983 | { |
| 984 | int reg = TMR_AR0 + (ar & 7); |
| 985 | return IREG(reg)--; |
| 986 | } |
| 987 | |
| 988 | UINT32 tms3203x_device::mod06_1(UINT32 op, UINT8 ar) |
| 989 | { |
| 990 | int reg = TMR_AR0 + (ar & 7); |
| 991 | UINT32 result = IREG(reg); |
| 992 | INT32 temp = (result & m_bkmask) + 1; |
| 993 | if (temp >= IREG(TMR_BK)) |
| 994 | temp -= IREG(TMR_BK); |
| 995 | IREG(reg) = (IREG(reg) & ~m_bkmask) | (temp & m_bkmask); |
| 996 | return result; |
| 997 | } |
| 998 | |
| 999 | UINT32 tms3203x_device::mod07_1(UINT32 op, UINT8 ar) |
| 1000 | { |
| 1001 | int reg = TMR_AR0 + (ar & 7); |
| 1002 | UINT32 result = IREG(reg); |
| 1003 | INT32 temp = (result & m_bkmask) - 1; |
| 1004 | if (temp < 0) |
| 1005 | temp += IREG(TMR_BK); |
| 1006 | IREG(reg) = (IREG(reg) & ~m_bkmask) | (temp & m_bkmask); |
| 1007 | return result; |
| 1008 | } |
| 1009 | |
| 1010 | |
| 1011 | // IR0 displacement variants |
| 1012 | |
| 1013 | UINT32 tms3203x_device::mod08(UINT32 op, UINT8 ar) |
| 1014 | { |
| 1015 | int reg = TMR_AR0 + (ar & 7); |
| 1016 | return IREG(reg) + IREG(TMR_IR0); |
| 1017 | } |
| 1018 | |
| 1019 | UINT32 tms3203x_device::mod09(UINT32 op, UINT8 ar) |
| 1020 | { |
| 1021 | int reg = TMR_AR0 + (ar & 7); |
| 1022 | return IREG(reg) - IREG(TMR_IR0); |
| 1023 | } |
| 1024 | |
| 1025 | UINT32 tms3203x_device::mod0a(UINT32 op, UINT8 ar) |
| 1026 | { |
| 1027 | int reg = TMR_AR0 + (ar & 7); |
| 1028 | IREG(reg) += IREG(TMR_IR0); |
| 1029 | return IREG(reg); |
| 1030 | } |
| 1031 | |
| 1032 | UINT32 tms3203x_device::mod0b(UINT32 op, UINT8 ar) |
| 1033 | { |
| 1034 | int reg = TMR_AR0 + (ar & 7); |
| 1035 | IREG(reg) -= IREG(TMR_IR0); |
| 1036 | return IREG(reg); |
| 1037 | } |
| 1038 | |
| 1039 | UINT32 tms3203x_device::mod0c(UINT32 op, UINT8 ar) |
| 1040 | { |
| 1041 | int reg = TMR_AR0 + (ar & 7); |
| 1042 | UINT32 result = IREG(reg); |
| 1043 | IREG(reg) += IREG(TMR_IR0); |
| 1044 | return result; |
| 1045 | } |
| 1046 | |
| 1047 | UINT32 tms3203x_device::mod0d(UINT32 op, UINT8 ar) |
| 1048 | { |
| 1049 | int reg = TMR_AR0 + (ar & 7); |
| 1050 | UINT32 result = IREG(reg); |
| 1051 | IREG(reg) -= IREG(TMR_IR0); |
| 1052 | return result; |
| 1053 | } |
| 1054 | |
| 1055 | UINT32 tms3203x_device::mod0e(UINT32 op, UINT8 ar) |
| 1056 | { |
| 1057 | int reg = TMR_AR0 + (ar & 7); |
| 1058 | UINT32 result = IREG(reg); |
| 1059 | INT32 temp = (result & m_bkmask) + IREG(TMR_IR0); |
| 1060 | if (temp >= IREG(TMR_BK)) |
| 1061 | temp -= IREG(TMR_BK); |
| 1062 | IREG(reg) = (IREG(reg) & ~m_bkmask) | (temp & m_bkmask); |
| 1063 | return result; |
| 1064 | } |
| 1065 | |
| 1066 | UINT32 tms3203x_device::mod0f(UINT32 op, UINT8 ar) |
| 1067 | { |
| 1068 | int reg = TMR_AR0 + (ar & 7); |
| 1069 | UINT32 result = IREG(reg); |
| 1070 | INT32 temp = (result & m_bkmask) - IREG(TMR_IR0); |
| 1071 | if (temp < 0) |
| 1072 | temp += IREG(TMR_BK); |
| 1073 | IREG(reg) = (IREG(reg) & ~m_bkmask) | (temp & m_bkmask); |
| 1074 | return result; |
| 1075 | } |
| 1076 | |
| 1077 | |
| 1078 | // IR1 displacement variants |
| 1079 | |
| 1080 | UINT32 tms3203x_device::mod10(UINT32 op, UINT8 ar) |
| 1081 | { |
| 1082 | int reg = TMR_AR0 + (ar & 7); |
| 1083 | return IREG(reg) + IREG(TMR_IR1); |
| 1084 | } |
| 1085 | |
| 1086 | UINT32 tms3203x_device::mod11(UINT32 op, UINT8 ar) |
| 1087 | { |
| 1088 | int reg = TMR_AR0 + (ar & 7); |
| 1089 | return IREG(reg) - IREG(TMR_IR1); |
| 1090 | } |
| 1091 | |
| 1092 | UINT32 tms3203x_device::mod12(UINT32 op, UINT8 ar) |
| 1093 | { |
| 1094 | int reg = TMR_AR0 + (ar & 7); |
| 1095 | IREG(reg) += IREG(TMR_IR1); |
| 1096 | return IREG(reg); |
| 1097 | } |
| 1098 | |
| 1099 | UINT32 tms3203x_device::mod13(UINT32 op, UINT8 ar) |
| 1100 | { |
| 1101 | int reg = TMR_AR0 + (ar & 7); |
| 1102 | IREG(reg) -= IREG(TMR_IR1); |
| 1103 | return IREG(reg); |
| 1104 | } |
| 1105 | |
| 1106 | UINT32 tms3203x_device::mod14(UINT32 op, UINT8 ar) |
| 1107 | { |
| 1108 | int reg = TMR_AR0 + (ar & 7); |
| 1109 | UINT32 result = IREG(reg); |
| 1110 | IREG(reg) += IREG(TMR_IR1); |
| 1111 | return result; |
| 1112 | } |
| 1113 | |
| 1114 | UINT32 tms3203x_device::mod15(UINT32 op, UINT8 ar) |
| 1115 | { |
| 1116 | int reg = TMR_AR0 + (ar & 7); |
| 1117 | UINT32 result = IREG(reg); |
| 1118 | IREG(reg) -= IREG(TMR_IR1); |
| 1119 | return result; |
| 1120 | } |
| 1121 | |
| 1122 | UINT32 tms3203x_device::mod16(UINT32 op, UINT8 ar) |
| 1123 | { |
| 1124 | int reg = TMR_AR0 + (ar & 7); |
| 1125 | UINT32 result = IREG(reg); |
| 1126 | INT32 temp = (result & m_bkmask) + IREG(TMR_IR1); |
| 1127 | if (temp >= IREG(TMR_BK)) |
| 1128 | temp -= IREG(TMR_BK); |
| 1129 | IREG(reg) = (IREG(reg) & ~m_bkmask) | (temp & m_bkmask); |
| 1130 | return result; |
| 1131 | } |
| 1132 | |
| 1133 | UINT32 tms3203x_device::mod17(UINT32 op, UINT8 ar) |
| 1134 | { |
| 1135 | int reg = TMR_AR0 + (ar & 7); |
| 1136 | UINT32 result = IREG(reg); |
| 1137 | INT32 temp = (result & m_bkmask) - IREG(TMR_IR1); |
| 1138 | if (temp < 0) |
| 1139 | temp += IREG(TMR_BK); |
| 1140 | IREG(reg) = (IREG(reg) & ~m_bkmask) | (temp & m_bkmask); |
| 1141 | return result; |
| 1142 | } |
| 1143 | |
| 1144 | |
| 1145 | // special variants |
| 1146 | |
| 1147 | UINT32 tms3203x_device::mod18(UINT32 op, UINT8 ar) |
| 1148 | { |
| 1149 | int reg = TMR_AR0 + (ar & 7); |
| 1150 | return IREG(reg); |
| 1151 | } |
| 1152 | |
| 1153 | UINT32 tms3203x_device::mod19(UINT32 op, UINT8 ar) |
| 1154 | { |
| 1155 | unimplemented(op); |
| 1156 | return 0; |
| 1157 | } |
| 1158 | |
| 1159 | UINT32 tms3203x_device::modillegal(UINT32 op, UINT8 ar) |
| 1160 | { |
| 1161 | illegal(op); |
| 1162 | return 0; |
| 1163 | } |
| 1164 | |
| 1165 | |
| 1166 | // immediate displacement variants (implied 1) |
| 1167 | |
| 1168 | UINT32 tms3203x_device::mod00_1_def(UINT32 op, UINT8 ar, UINT32 *&defptrptr) |
| 1169 | { |
| 1170 | int reg = TMR_AR0 + (ar & 7); |
| 1171 | return IREG(reg) + 1; |
| 1172 | } |
| 1173 | |
| 1174 | UINT32 tms3203x_device::mod01_1_def(UINT32 op, UINT8 ar, UINT32 *&defptrptr) |
| 1175 | { |
| 1176 | int reg = TMR_AR0 + (ar & 7); |
| 1177 | return IREG(reg) - 1; |
| 1178 | } |
| 1179 | |
| 1180 | UINT32 tms3203x_device::mod02_1_def(UINT32 op, UINT8 ar, UINT32 *&defptrptr) |
| 1181 | { |
| 1182 | int reg = TMR_AR0 + (ar & 7); |
| 1183 | UINT32 defval = IREG(reg) + 1; |
| 1184 | *defptrptr = defval; |
| 1185 | defptrptr = &IREG(reg); |
| 1186 | return defval; |
| 1187 | } |
| 1188 | |
| 1189 | UINT32 tms3203x_device::mod03_1_def(UINT32 op, UINT8 ar, UINT32 *&defptrptr) |
| 1190 | { |
| 1191 | int reg = TMR_AR0 + (ar & 7); |
| 1192 | UINT32 defval = IREG(reg) - 1; |
| 1193 | *defptrptr = defval; |
| 1194 | defptrptr = &IREG(reg); |
| 1195 | return defval; |
| 1196 | } |
| 1197 | |
| 1198 | UINT32 tms3203x_device::mod04_1_def(UINT32 op, UINT8 ar, UINT32 *&defptrptr) |
| 1199 | { |
| 1200 | int reg = TMR_AR0 + (ar & 7); |
| 1201 | *defptrptr = IREG(reg) + 1; |
| 1202 | defptrptr = &IREG(reg); |
| 1203 | return IREG(reg); |
| 1204 | } |
| 1205 | |
| 1206 | UINT32 tms3203x_device::mod05_1_def(UINT32 op, UINT8 ar, UINT32 *&defptrptr) |
| 1207 | { |
| 1208 | int reg = TMR_AR0 + (ar & 7); |
| 1209 | *defptrptr = IREG(reg) - 1; |
| 1210 | defptrptr = &IREG(reg); |
| 1211 | return IREG(reg); |
| 1212 | } |
| 1213 | |
| 1214 | UINT32 tms3203x_device::mod06_1_def(UINT32 op, UINT8 ar, UINT32 *&defptrptr) |
| 1215 | { |
| 1216 | int reg = TMR_AR0 + (ar & 7); |
| 1217 | UINT32 result = IREG(reg); |
| 1218 | INT32 temp = (result & m_bkmask) + 1; |
| 1219 | if (temp >= IREG(TMR_BK)) |
| 1220 | temp -= IREG(TMR_BK); |
| 1221 | *defptrptr = (IREG(reg) & ~m_bkmask) | (temp & m_bkmask); |
| 1222 | defptrptr = &IREG(reg); |
| 1223 | return result; |
| 1224 | } |
| 1225 | |
| 1226 | UINT32 tms3203x_device::mod07_1_def(UINT32 op, UINT8 ar, UINT32 *&defptrptr) |
| 1227 | { |
| 1228 | int reg = TMR_AR0 + (ar & 7); |
| 1229 | UINT32 result = IREG(reg); |
| 1230 | INT32 temp = (result & m_bkmask) - 1; |
| 1231 | if (temp < 0) |
| 1232 | temp += IREG(TMR_BK); |
| 1233 | *defptrptr = (IREG(reg) & ~m_bkmask) | (temp & m_bkmask); |
| 1234 | defptrptr = &IREG(reg); |
| 1235 | return result; |
| 1236 | } |
| 1237 | |
| 1238 | |
| 1239 | // IR0 displacement variants |
| 1240 | |
| 1241 | UINT32 tms3203x_device::mod08_def(UINT32 op, UINT8 ar, UINT32 *&defptrptr) |
| 1242 | { |
| 1243 | int reg = TMR_AR0 + (ar & 7); |
| 1244 | return IREG(reg) + IREG(TMR_IR0); |
| 1245 | } |
| 1246 | |
| 1247 | UINT32 tms3203x_device::mod09_def(UINT32 op, UINT8 ar, UINT32 *&defptrptr) |
| 1248 | { |
| 1249 | int reg = TMR_AR0 + (ar & 7); |
| 1250 | return IREG(reg) - IREG(TMR_IR0); |
| 1251 | } |
| 1252 | |
| 1253 | UINT32 tms3203x_device::mod0a_def(UINT32 op, UINT8 ar, UINT32 *&defptrptr) |
| 1254 | { |
| 1255 | int reg = TMR_AR0 + (ar & 7); |
| 1256 | UINT32 defval = IREG(reg) + IREG(TMR_IR0); |
| 1257 | *defptrptr = defval; |
| 1258 | defptrptr = &IREG(reg); |
| 1259 | return defval; |
| 1260 | } |
| 1261 | |
| 1262 | UINT32 tms3203x_device::mod0b_def(UINT32 op, UINT8 ar, UINT32 *&defptrptr) |
| 1263 | { |
| 1264 | int reg = TMR_AR0 + (ar & 7); |
| 1265 | UINT32 defval = IREG(reg) - IREG(TMR_IR0); |
| 1266 | *defptrptr = defval; |
| 1267 | defptrptr = &IREG(reg); |
| 1268 | return defval; |
| 1269 | } |
| 1270 | |
| 1271 | UINT32 tms3203x_device::mod0c_def(UINT32 op, UINT8 ar, UINT32 *&defptrptr) |
| 1272 | { |
| 1273 | int reg = TMR_AR0 + (ar & 7); |
| 1274 | *defptrptr = IREG(reg) + IREG(TMR_IR0); |
| 1275 | defptrptr = &IREG(reg); |
| 1276 | return IREG(reg); |
| 1277 | } |
| 1278 | |
| 1279 | UINT32 tms3203x_device::mod0d_def(UINT32 op, UINT8 ar, UINT32 *&defptrptr) |
| 1280 | { |
| 1281 | int reg = TMR_AR0 + (ar & 7); |
| 1282 | *defptrptr = IREG(reg) - IREG(TMR_IR0); |
| 1283 | defptrptr = &IREG(reg); |
| 1284 | return IREG(reg); |
| 1285 | } |
| 1286 | |
| 1287 | UINT32 tms3203x_device::mod0e_def(UINT32 op, UINT8 ar, UINT32 *&defptrptr) |
| 1288 | { |
| 1289 | int reg = TMR_AR0 + (ar & 7); |
| 1290 | UINT32 result = IREG(reg); |
| 1291 | INT32 temp = (result & m_bkmask) + IREG(TMR_IR0); |
| 1292 | if (temp >= IREG(TMR_BK)) |
| 1293 | temp -= IREG(TMR_BK); |
| 1294 | *defptrptr = (IREG(reg) & ~m_bkmask) | (temp & m_bkmask); |
| 1295 | defptrptr = &IREG(reg); |
| 1296 | return result; |
| 1297 | } |
| 1298 | |
| 1299 | UINT32 tms3203x_device::mod0f_def(UINT32 op, UINT8 ar, UINT32 *&defptrptr) |
| 1300 | { |
| 1301 | int reg = TMR_AR0 + (ar & 7); |
| 1302 | UINT32 result = IREG(reg); |
| 1303 | INT32 temp = (result & m_bkmask) - IREG(TMR_IR0); |
| 1304 | if (temp < 0) |
| 1305 | temp += IREG(TMR_BK); |
| 1306 | *defptrptr = (IREG(reg) & ~m_bkmask) | (temp & m_bkmask); |
| 1307 | defptrptr = &IREG(reg); |
| 1308 | return result; |
| 1309 | } |
| 1310 | |
| 1311 | |
| 1312 | // IR1 displacement variants |
| 1313 | |
| 1314 | UINT32 tms3203x_device::mod10_def(UINT32 op, UINT8 ar, UINT32 *&defptrptr) |
| 1315 | { |
| 1316 | int reg = TMR_AR0 + (ar & 7); |
| 1317 | return IREG(reg) + IREG(TMR_IR1); |
| 1318 | } |
| 1319 | |
| 1320 | UINT32 tms3203x_device::mod11_def(UINT32 op, UINT8 ar, UINT32 *&defptrptr) |
| 1321 | { |
| 1322 | int reg = TMR_AR0 + (ar & 7); |
| 1323 | return IREG(reg) - IREG(TMR_IR1); |
| 1324 | } |
| 1325 | |
| 1326 | UINT32 tms3203x_device::mod12_def(UINT32 op, UINT8 ar, UINT32 *&defptrptr) |
| 1327 | { |
| 1328 | int reg = TMR_AR0 + (ar & 7); |
| 1329 | UINT32 defval = IREG(reg) + IREG(TMR_IR1); |
| 1330 | *defptrptr = defval; |
| 1331 | defptrptr = &IREG(reg); |
| 1332 | return defval; |
| 1333 | } |
| 1334 | |
| 1335 | UINT32 tms3203x_device::mod13_def(UINT32 op, UINT8 ar, UINT32 *&defptrptr) |
| 1336 | { |
| 1337 | int reg = TMR_AR0 + (ar & 7); |
| 1338 | UINT32 defval = IREG(reg) - IREG(TMR_IR1); |
| 1339 | *defptrptr = defval; |
| 1340 | defptrptr = &IREG(reg); |
| 1341 | return defval; |
| 1342 | } |
| 1343 | |
| 1344 | UINT32 tms3203x_device::mod14_def(UINT32 op, UINT8 ar, UINT32 *&defptrptr) |
| 1345 | { |
| 1346 | int reg = TMR_AR0 + (ar & 7); |
| 1347 | *defptrptr = IREG(reg) + IREG(TMR_IR1); |
| 1348 | defptrptr = &IREG(reg); |
| 1349 | return IREG(reg); |
| 1350 | } |
| 1351 | |
| 1352 | UINT32 tms3203x_device::mod15_def(UINT32 op, UINT8 ar, UINT32 *&defptrptr) |
| 1353 | { |
| 1354 | int reg = TMR_AR0 + (ar & 7); |
| 1355 | *defptrptr = IREG(reg) - IREG(TMR_IR1); |
| 1356 | defptrptr = &IREG(reg); |
| 1357 | return IREG(reg); |
| 1358 | } |
| 1359 | |
| 1360 | UINT32 tms3203x_device::mod16_def(UINT32 op, UINT8 ar, UINT32 *&defptrptr) |
| 1361 | { |
| 1362 | int reg = TMR_AR0 + (ar & 7); |
| 1363 | UINT32 result = IREG(reg); |
| 1364 | INT32 temp = (result & m_bkmask) + IREG(TMR_IR1); |
| 1365 | if (temp >= IREG(TMR_BK)) |
| 1366 | temp -= IREG(TMR_BK); |
| 1367 | *defptrptr = (IREG(reg) & ~m_bkmask) | (temp & m_bkmask); |
| 1368 | defptrptr = &IREG(reg); |
| 1369 | return result; |
| 1370 | } |
| 1371 | |
| 1372 | UINT32 tms3203x_device::mod17_def(UINT32 op, UINT8 ar, UINT32 *&defptrptr) |
| 1373 | { |
| 1374 | int reg = TMR_AR0 + (ar & 7); |
| 1375 | UINT32 result = IREG(reg); |
| 1376 | INT32 temp = (result & m_bkmask) - IREG(TMR_IR1); |
| 1377 | if (temp < 0) |
| 1378 | temp += IREG(TMR_BK); |
| 1379 | *defptrptr = (IREG(reg) & ~m_bkmask) | (temp & m_bkmask); |
| 1380 | defptrptr = &IREG(reg); |
| 1381 | return result; |
| 1382 | } |
| 1383 | |
| 1384 | UINT32 tms3203x_device::mod18_def(UINT32 op, UINT8 ar, UINT32 *&defptrptr) |
| 1385 | { |
| 1386 | int reg = TMR_AR0 + (ar & 7); |
| 1387 | return IREG(reg); |
| 1388 | } |
| 1389 | |
| 1390 | UINT32 tms3203x_device::mod19_def(UINT32 op, UINT8 ar, UINT32 *&defptrptr) |
| 1391 | { |
| 1392 | unimplemented(op); |
| 1393 | return 0; |
| 1394 | } |
| 1395 | |
| 1396 | UINT32 tms3203x_device::modillegal_def(UINT32 op, UINT8 ar, UINT32 *&defptrptr) |
| 1397 | { |
| 1398 | illegal(op); |
| 1399 | return 0; |
| 1400 | } |
| 1401 | |
| 1402 | |
| 1403 | /*-----------------------------------------------------*/ |
| 1404 | |
| 1405 | #define ABSF(dreg, sreg) \ |
| 1406 | { \ |
| 1407 | INT32 man = FREGMAN(sreg); \ |
| 1408 | CLR_NZVUF(); \ |
| 1409 | m_r[dreg] = m_r[sreg]; \ |
| 1410 | if (man < 0) \ |
| 1411 | { \ |
| 1412 | m_r[dreg].set_mantissa(~man); \ |
| 1413 | if (man == (INT32)0x80000000 && FREGEXP(sreg) == 127) \ |
| 1414 | IREG(TMR_ST) |= VFLAG | LVFLAG; \ |
| 1415 | } \ |
| 1416 | OR_NZF(m_r[dreg]); \ |
| 1417 | } |
| 1418 | |
| 1419 | void tms3203x_device::absf_reg(UINT32 op) |
| 1420 | { |
| 1421 | int dreg = (op >> 16) & 7; |
| 1422 | int sreg = op & 7; |
| 1423 | ABSF(dreg, sreg); |
| 1424 | } |
| 1425 | |
| 1426 | void tms3203x_device::absf_dir(UINT32 op) |
| 1427 | { |
| 1428 | UINT32 res = RMEM(DIRECT(op)); |
| 1429 | int dreg = (op >> 16) & 7; |
| 1430 | LONG2FP(TMR_TEMP1, res); |
| 1431 | ABSF(dreg, TMR_TEMP1); |
| 1432 | } |
| 1433 | |
| 1434 | void tms3203x_device::absf_ind(UINT32 op) |
| 1435 | { |
| 1436 | UINT32 res = RMEM(INDIRECT_D(op, op >> 8)); |
| 1437 | int dreg = (op >> 16) & 7; |
| 1438 | LONG2FP(TMR_TEMP1, res); |
| 1439 | ABSF(dreg, TMR_TEMP1); |
| 1440 | } |
| 1441 | |
| 1442 | void tms3203x_device::absf_imm(UINT32 op) |
| 1443 | { |
| 1444 | int dreg = (op >> 16) & 7; |
| 1445 | SHORT2FP(TMR_TEMP1, op); |
| 1446 | ABSF(dreg, TMR_TEMP1); |
| 1447 | } |
| 1448 | |
| 1449 | /*-----------------------------------------------------*/ |
| 1450 | |
| 1451 | #define ABSI(dreg, src) \ |
| 1452 | { \ |
| 1453 | UINT32 _res = ((INT32)src < 0) ? -src : src; \ |
| 1454 | if (!OVM() || _res != 0x80000000) \ |
| 1455 | IREG(dreg) = _res; \ |
| 1456 | else \ |
| 1457 | IREG(dreg) = 0x7fffffff; \ |
| 1458 | if (dreg < 8) \ |
| 1459 | { \ |
| 1460 | CLR_NZVUF(); \ |
| 1461 | OR_NZ(_res); \ |
| 1462 | if (_res == 0x80000000) \ |
| 1463 | IREG(TMR_ST) |= VFLAG | LVFLAG; \ |
| 1464 | } \ |
| 1465 | else if (dreg >= TMR_BK) \ |
| 1466 | update_special(dreg); \ |
| 1467 | } |
| 1468 | |
| 1469 | void tms3203x_device::absi_reg(UINT32 op) |
| 1470 | { |
| 1471 | UINT32 src = IREG(op & 31); |
| 1472 | int dreg = (op >> 16) & 31; |
| 1473 | ABSI(dreg, src); |
| 1474 | } |
| 1475 | |
| 1476 | void tms3203x_device::absi_dir(UINT32 op) |
| 1477 | { |
| 1478 | UINT32 src = RMEM(DIRECT(op)); |
| 1479 | int dreg = (op >> 16) & 31; |
| 1480 | ABSI(dreg, src); |
| 1481 | } |
| 1482 | |
| 1483 | void tms3203x_device::absi_ind(UINT32 op) |
| 1484 | { |
| 1485 | UINT32 src = RMEM(INDIRECT_D(op, op >> 8)); |
| 1486 | int dreg = (op >> 16) & 31; |
| 1487 | ABSI(dreg, src); |
| 1488 | } |
| 1489 | |
| 1490 | void tms3203x_device::absi_imm(UINT32 op) |
| 1491 | { |
| 1492 | UINT32 src = (INT16)op; |
| 1493 | int dreg = (op >> 16) & 31; |
| 1494 | ABSI(dreg, src); |
| 1495 | } |
| 1496 | |
| 1497 | /*-----------------------------------------------------*/ |
| 1498 | |
| 1499 | #define ADDC(dreg, src1, src2) \ |
| 1500 | { \ |
| 1501 | UINT32 _res = src1 + src2 + (IREG(TMR_ST) & CFLAG); \ |
| 1502 | if (!OVM() || !OVERFLOW_ADD(src1,src2,_res)) \ |
| 1503 | IREG(dreg) = _res; \ |
| 1504 | else \ |
| 1505 | IREG(dreg) = ((INT32)src1 < 0) ? 0x80000000 : 0x7fffffff; \ |
| 1506 | if (dreg < 8) \ |
| 1507 | { \ |
| 1508 | UINT32 tempc = IREG(TMR_ST) & CFLAG; \ |
| 1509 | CLR_NZCVUF(); \ |
| 1510 | OR_C_ADC(src1,src2,tempc); \ |
| 1511 | OR_V_ADD(src1,src2,_res); \ |
| 1512 | OR_NZ(_res); \ |
| 1513 | } \ |
| 1514 | else if (dreg >= TMR_BK) \ |
| 1515 | update_special(dreg); \ |
| 1516 | } |
| 1517 | |
| 1518 | void tms3203x_device::addc_reg(UINT32 op) |
| 1519 | { |
| 1520 | UINT32 src = IREG(op & 31); |
| 1521 | int dreg = (op >> 16) & 31; |
| 1522 | UINT32 dst = IREG(dreg); |
| 1523 | ADDC(dreg, dst, src); |
| 1524 | } |
| 1525 | |
| 1526 | void tms3203x_device::addc_dir(UINT32 op) |
| 1527 | { |
| 1528 | UINT32 src = RMEM(DIRECT(op)); |
| 1529 | int dreg = (op >> 16) & 31; |
| 1530 | UINT32 dst = IREG(dreg); |
| 1531 | ADDC(dreg, dst, src); |
| 1532 | } |
| 1533 | |
| 1534 | void tms3203x_device::addc_ind(UINT32 op) |
| 1535 | { |
| 1536 | UINT32 src = RMEM(INDIRECT_D(op, op >> 8)); |
| 1537 | int dreg = (op >> 16) & 31; |
| 1538 | UINT32 dst = IREG(dreg); |
| 1539 | ADDC(dreg, dst, src); |
| 1540 | } |
| 1541 | |
| 1542 | void tms3203x_device::addc_imm(UINT32 op) |
| 1543 | { |
| 1544 | UINT32 src = (INT16)op; |
| 1545 | int dreg = (op >> 16) & 31; |
| 1546 | UINT32 dst = IREG(dreg); |
| 1547 | ADDC(dreg, dst, src); |
| 1548 | } |
| 1549 | |
| 1550 | /*-----------------------------------------------------*/ |
| 1551 | |
| 1552 | void tms3203x_device::addf_reg(UINT32 op) |
| 1553 | { |
| 1554 | int dreg = (op >> 16) & 7; |
| 1555 | addf(m_r[dreg], m_r[dreg], m_r[op & 7]); |
| 1556 | } |
| 1557 | |
| 1558 | void tms3203x_device::addf_dir(UINT32 op) |
| 1559 | { |
| 1560 | UINT32 res = RMEM(DIRECT(op)); |
| 1561 | int dreg = (op >> 16) & 7; |
| 1562 | LONG2FP(TMR_TEMP1, res); |
| 1563 | addf(m_r[dreg], m_r[dreg], m_r[TMR_TEMP1]); |
| 1564 | } |
| 1565 | |
| 1566 | void tms3203x_device::addf_ind(UINT32 op) |
| 1567 | { |
| 1568 | UINT32 res = RMEM(INDIRECT_D(op, op >> 8)); |
| 1569 | int dreg = (op >> 16) & 7; |
| 1570 | LONG2FP(TMR_TEMP1, res); |
| 1571 | addf(m_r[dreg], m_r[dreg], m_r[TMR_TEMP1]); |
| 1572 | } |
| 1573 | |
| 1574 | void tms3203x_device::addf_imm(UINT32 op) |
| 1575 | { |
| 1576 | int dreg = (op >> 16) & 7; |
| 1577 | SHORT2FP(TMR_TEMP1, op); |
| 1578 | addf(m_r[dreg], m_r[dreg], m_r[TMR_TEMP1]); |
| 1579 | } |
| 1580 | |
| 1581 | /*-----------------------------------------------------*/ |
| 1582 | |
| 1583 | #define ADDI(dreg, src1, src2) \ |
| 1584 | { \ |
| 1585 | UINT32 _res = src1 + src2; \ |
| 1586 | if (!OVM() || !OVERFLOW_ADD(src1,src2,_res)) \ |
| 1587 | IREG(dreg) = _res; \ |
| 1588 | else \ |
| 1589 | IREG(dreg) = ((INT32)src1 < 0) ? 0x80000000 : 0x7fffffff; \ |
| 1590 | if (dreg < 8) \ |
| 1591 | { \ |
| 1592 | CLR_NZCVUF(); \ |
| 1593 | OR_C_ADD(src1,src2,_res); \ |
| 1594 | OR_V_ADD(src1,src2,_res); \ |
| 1595 | OR_NZ(_res); \ |
| 1596 | } \ |
| 1597 | else if (dreg >= TMR_BK) \ |
| 1598 | update_special(dreg); \ |
| 1599 | } |
| 1600 | |
| 1601 | void tms3203x_device::addi_reg(UINT32 op) |
| 1602 | { |
| 1603 | UINT32 src = IREG(op & 31); |
| 1604 | int dreg = (op >> 16) & 31; |
| 1605 | UINT32 dst = IREG(dreg); |
| 1606 | ADDI(dreg, dst, src); |
| 1607 | } |
| 1608 | |
| 1609 | void tms3203x_device::addi_dir(UINT32 op) |
| 1610 | { |
| 1611 | UINT32 src = RMEM(DIRECT(op)); |
| 1612 | int dreg = (op >> 16) & 31; |
| 1613 | UINT32 dst = IREG(dreg); |
| 1614 | ADDI(dreg, dst, src); |
| 1615 | } |
| 1616 | |
| 1617 | void tms3203x_device::addi_ind(UINT32 op) |
| 1618 | { |
| 1619 | UINT32 src = RMEM(INDIRECT_D(op, op >> 8)); |
| 1620 | int dreg = (op >> 16) & 31; |
| 1621 | UINT32 dst = IREG(dreg); |
| 1622 | ADDI(dreg, dst, src); |
| 1623 | } |
| 1624 | |
| 1625 | void tms3203x_device::addi_imm(UINT32 op) |
| 1626 | { |
| 1627 | UINT32 src = (INT16)op; |
| 1628 | int dreg = (op >> 16) & 31; |
| 1629 | UINT32 dst = IREG(dreg); |
| 1630 | ADDI(dreg, dst, src); |
| 1631 | } |
| 1632 | |
| 1633 | /*-----------------------------------------------------*/ |
| 1634 | |
| 1635 | #define AND(dreg, src1, src2) \ |
| 1636 | { \ |
| 1637 | UINT32 _res = (src1) & (src2); \ |
| 1638 | IREG(dreg) = _res; \ |
| 1639 | if (dreg < 8) \ |
| 1640 | { \ |
| 1641 | CLR_NZVUF(); \ |
| 1642 | OR_NZ(_res); \ |
| 1643 | } \ |
| 1644 | else if (dreg >= TMR_BK) \ |
| 1645 | update_special(dreg); \ |
| 1646 | } |
| 1647 | |
| 1648 | void tms3203x_device::and_reg(UINT32 op) |
| 1649 | { |
| 1650 | UINT32 src = IREG(op & 31); |
| 1651 | int dreg = (op >> 16) & 31; |
| 1652 | UINT32 dst = IREG(dreg); |
| 1653 | AND(dreg, dst, src); |
| 1654 | } |
| 1655 | |
| 1656 | void tms3203x_device::and_dir(UINT32 op) |
| 1657 | { |
| 1658 | UINT32 src = RMEM(DIRECT(op)); |
| 1659 | int dreg = (op >> 16) & 31; |
| 1660 | UINT32 dst = IREG(dreg); |
| 1661 | AND(dreg, dst, src); |
| 1662 | } |
| 1663 | |
| 1664 | void tms3203x_device::and_ind(UINT32 op) |
| 1665 | { |
| 1666 | UINT32 src = RMEM(INDIRECT_D(op, op >> 8)); |
| 1667 | int dreg = (op >> 16) & 31; |
| 1668 | UINT32 dst = IREG(dreg); |
| 1669 | AND(dreg, dst, src); |
| 1670 | } |
| 1671 | |
| 1672 | void tms3203x_device::and_imm(UINT32 op) |
| 1673 | { |
| 1674 | UINT32 src = (UINT16)op; |
| 1675 | int dreg = (op >> 16) & 31; |
| 1676 | UINT32 dst = IREG(dreg); |
| 1677 | AND(dreg, dst, src); |
| 1678 | } |
| 1679 | |
| 1680 | /*-----------------------------------------------------*/ |
| 1681 | |
| 1682 | #define ANDN(dreg, src1, src2) \ |
| 1683 | { \ |
| 1684 | UINT32 _res = (src1) & ~(src2); \ |
| 1685 | IREG(dreg) = _res; \ |
| 1686 | if (dreg < 8) \ |
| 1687 | { \ |
| 1688 | CLR_NZVUF(); \ |
| 1689 | OR_NZ(_res); \ |
| 1690 | } \ |
| 1691 | else if (dreg >= TMR_BK) \ |
| 1692 | update_special(dreg); \ |
| 1693 | } |
| 1694 | |
| 1695 | void tms3203x_device::andn_reg(UINT32 op) |
| 1696 | { |
| 1697 | UINT32 src = IREG(op & 31); |
| 1698 | int dreg = (op >> 16) & 31; |
| 1699 | UINT32 dst = IREG(dreg); |
| 1700 | ANDN(dreg, dst, src); |
| 1701 | } |
| 1702 | |
| 1703 | void tms3203x_device::andn_dir(UINT32 op) |
| 1704 | { |
| 1705 | UINT32 src = RMEM(DIRECT(op)); |
| 1706 | int dreg = (op >> 16) & 31; |
| 1707 | UINT32 dst = IREG(dreg); |
| 1708 | ANDN(dreg, dst, src); |
| 1709 | } |
| 1710 | |
| 1711 | void tms3203x_device::andn_ind(UINT32 op) |
| 1712 | { |
| 1713 | UINT32 src = RMEM(INDIRECT_D(op, op >> 8)); |
| 1714 | int dreg = (op >> 16) & 31; |
| 1715 | UINT32 dst = IREG(dreg); |
| 1716 | ANDN(dreg, dst, src); |
| 1717 | } |
| 1718 | |
| 1719 | void tms3203x_device::andn_imm(UINT32 op) |
| 1720 | { |
| 1721 | UINT32 src = (UINT16)op; |
| 1722 | int dreg = (op >> 16) & 31; |
| 1723 | UINT32 dst = IREG(dreg); |
| 1724 | ANDN(dreg, dst, src); |
| 1725 | } |
| 1726 | |
| 1727 | /*-----------------------------------------------------*/ |
| 1728 | |
| 1729 | #define ASH(dreg, src, count) \ |
| 1730 | { \ |
| 1731 | UINT32 _res; \ |
| 1732 | INT32 _count = (INT16)(count << 9) >> 9; /* 7 LSBs */ \ |
| 1733 | if (_count < 0) \ |
| 1734 | { \ |
| 1735 | if (_count >= -31) \ |
| 1736 | _res = (INT32)src >> -_count; \ |
| 1737 | else \ |
| 1738 | _res = (INT32)src >> 31; \ |
| 1739 | } \ |
| 1740 | else \ |
| 1741 | { \ |
| 1742 | if (_count <= 31) \ |
| 1743 | _res = (INT32)src << _count; \ |
| 1744 | else \ |
| 1745 | _res = 0; \ |
| 1746 | } \ |
| 1747 | IREG(dreg) = _res; \ |
| 1748 | if (dreg < 8) \ |
| 1749 | { \ |
| 1750 | CLR_NZCVUF(); \ |
| 1751 | OR_NZ(_res); \ |
| 1752 | if (_count < 0) \ |
| 1753 | { \ |
| 1754 | if (_count >= -32) \ |
| 1755 | OR_C(((INT32)src >> (-_count - 1)) & 1); \ |
| 1756 | else \ |
| 1757 | OR_C(((INT32)src >> 31) & 1); \ |
| 1758 | } \ |
| 1759 | else if (_count > 0) \ |
| 1760 | { \ |
| 1761 | if (_count <= 32) \ |
| 1762 | OR_C(((UINT32)src << (_count - 1)) >> 31); \ |
| 1763 | } \ |
| 1764 | } \ |
| 1765 | else if (dreg >= TMR_BK) \ |
| 1766 | update_special(dreg); \ |
| 1767 | } |
| 1768 | |
| 1769 | void tms3203x_device::ash_reg(UINT32 op) |
| 1770 | { |
| 1771 | int dreg = (op >> 16) & 31; |
| 1772 | int count = IREG(op & 31); |
| 1773 | UINT32 src = IREG(dreg); |
| 1774 | ASH(dreg, src, count); |
| 1775 | } |
| 1776 | |
| 1777 | void tms3203x_device::ash_dir(UINT32 op) |
| 1778 | { |
| 1779 | int dreg = (op >> 16) & 31; |
| 1780 | int count = RMEM(DIRECT(op)); |
| 1781 | UINT32 src = IREG(dreg); |
| 1782 | ASH(dreg, src, count); |
| 1783 | } |
| 1784 | |
| 1785 | void tms3203x_device::ash_ind(UINT32 op) |
| 1786 | { |
| 1787 | int dreg = (op >> 16) & 31; |
| 1788 | int count = RMEM(INDIRECT_D(op, op >> 8)); |
| 1789 | UINT32 src = IREG(dreg); |
| 1790 | ASH(dreg, src, count); |
| 1791 | } |
| 1792 | |
| 1793 | void tms3203x_device::ash_imm(UINT32 op) |
| 1794 | { |
| 1795 | int dreg = (op >> 16) & 31; |
| 1796 | int count = op; |
| 1797 | UINT32 src = IREG(dreg); |
| 1798 | ASH(dreg, src, count); |
| 1799 | } |
| 1800 | |
| 1801 | /*-----------------------------------------------------*/ |
| 1802 | |
| 1803 | void tms3203x_device::cmpf_reg(UINT32 op) |
| 1804 | { |
| 1805 | int dreg = (op >> 16) & 7; |
| 1806 | subf(m_r[TMR_TEMP2], m_r[dreg], m_r[op & 7]); |
| 1807 | } |
| 1808 | |
| 1809 | void tms3203x_device::cmpf_dir(UINT32 op) |
| 1810 | { |
| 1811 | UINT32 res = RMEM(DIRECT(op)); |
| 1812 | int dreg = (op >> 16) & 7; |
| 1813 | LONG2FP(TMR_TEMP1, res); |
| 1814 | subf(m_r[TMR_TEMP2], m_r[dreg], m_r[TMR_TEMP1]); |
| 1815 | } |
| 1816 | |
| 1817 | void tms3203x_device::cmpf_ind(UINT32 op) |
| 1818 | { |
| 1819 | UINT32 res = RMEM(INDIRECT_D(op, op >> 8)); |
| 1820 | int dreg = (op >> 16) & 7; |
| 1821 | LONG2FP(TMR_TEMP1, res); |
| 1822 | subf(m_r[TMR_TEMP2], m_r[dreg], m_r[TMR_TEMP1]); |
| 1823 | } |
| 1824 | |
| 1825 | void tms3203x_device::cmpf_imm(UINT32 op) |
| 1826 | { |
| 1827 | int dreg = (op >> 16) & 7; |
| 1828 | SHORT2FP(TMR_TEMP1, op); |
| 1829 | subf(m_r[TMR_TEMP2], m_r[dreg], m_r[TMR_TEMP1]); |
| 1830 | } |
| 1831 | |
| 1832 | /*-----------------------------------------------------*/ |
| 1833 | |
| 1834 | #define CMPI(src1, src2) \ |
| 1835 | { \ |
| 1836 | UINT32 _res = src1 - src2; \ |
| 1837 | CLR_NZCVUF(); \ |
| 1838 | OR_C_SUB(src1,src2,_res); \ |
| 1839 | OR_V_SUB(src1,src2,_res); \ |
| 1840 | OR_NZ(_res); \ |
| 1841 | } |
| 1842 | |
| 1843 | void tms3203x_device::cmpi_reg(UINT32 op) |
| 1844 | { |
| 1845 | UINT32 src = IREG(op & 31); |
| 1846 | UINT32 dst = IREG((op >> 16) & 31); |
| 1847 | CMPI(dst, src); |
| 1848 | } |
| 1849 | |
| 1850 | void tms3203x_device::cmpi_dir(UINT32 op) |
| 1851 | { |
| 1852 | UINT32 src = RMEM(DIRECT(op)); |
| 1853 | UINT32 dst = IREG((op >> 16) & 31); |
| 1854 | CMPI(dst, src); |
| 1855 | } |
| 1856 | |
| 1857 | void tms3203x_device::cmpi_ind(UINT32 op) |
| 1858 | { |
| 1859 | UINT32 src = RMEM(INDIRECT_D(op, op >> 8)); |
| 1860 | UINT32 dst = IREG((op >> 16) & 31); |
| 1861 | CMPI(dst, src); |
| 1862 | } |
| 1863 | |
| 1864 | void tms3203x_device::cmpi_imm(UINT32 op) |
| 1865 | { |
| 1866 | UINT32 src = (INT16)op; |
| 1867 | UINT32 dst = IREG((op >> 16) & 31); |
| 1868 | CMPI(dst, src); |
| 1869 | } |
| 1870 | |
| 1871 | /*-----------------------------------------------------*/ |
| 1872 | |
| 1873 | void tms3203x_device::fix_reg(UINT32 op) |
| 1874 | { |
| 1875 | int dreg = (op >> 16) & 31; |
| 1876 | m_r[TMR_TEMP1] = m_r[op & 7]; |
| 1877 | float2int(m_r[TMR_TEMP1], dreg < 8); |
| 1878 | m_r[dreg].set_mantissa(m_r[TMR_TEMP1].mantissa()); |
| 1879 | } |
| 1880 | |
| 1881 | void tms3203x_device::fix_dir(UINT32 op) |
| 1882 | { |
| 1883 | UINT32 res = RMEM(DIRECT(op)); |
| 1884 | int dreg = (op >> 16) & 31; |
| 1885 | LONG2FP(TMR_TEMP1, res); |
| 1886 | float2int(m_r[TMR_TEMP1], dreg < 8); |
| 1887 | m_r[dreg].set_mantissa(m_r[TMR_TEMP1].mantissa()); |
| 1888 | } |
| 1889 | |
| 1890 | void tms3203x_device::fix_ind(UINT32 op) |
| 1891 | { |
| 1892 | UINT32 res = RMEM(INDIRECT_D(op, op >> 8)); |
| 1893 | int dreg = (op >> 16) & 31; |
| 1894 | LONG2FP(TMR_TEMP1, res); |
| 1895 | float2int(m_r[TMR_TEMP1], dreg < 8); |
| 1896 | m_r[dreg].set_mantissa(m_r[TMR_TEMP1].mantissa()); |
| 1897 | } |
| 1898 | |
| 1899 | void tms3203x_device::fix_imm(UINT32 op) |
| 1900 | { |
| 1901 | int dreg = (op >> 16) & 31; |
| 1902 | SHORT2FP(TMR_TEMP1, op); |
| 1903 | float2int(m_r[TMR_TEMP1], dreg < 8); |
| 1904 | m_r[dreg].set_mantissa(m_r[TMR_TEMP1].mantissa()); |
| 1905 | } |
| 1906 | |
| 1907 | /*-----------------------------------------------------*/ |
| 1908 | |
| 1909 | #define FLOAT(dreg, src) \ |
| 1910 | { \ |
| 1911 | IREG(dreg) = src; \ |
| 1912 | int2float(m_r[dreg]); \ |
| 1913 | } |
| 1914 | |
| 1915 | void tms3203x_device::float_reg(UINT32 op) |
| 1916 | { |
| 1917 | UINT32 src = IREG(op & 31); |
| 1918 | int dreg = (op >> 16) & 7; |
| 1919 | FLOAT(dreg, src); |
| 1920 | } |
| 1921 | |
| 1922 | void tms3203x_device::float_dir(UINT32 op) |
| 1923 | { |
| 1924 | UINT32 src = RMEM(DIRECT(op)); |
| 1925 | int dreg = (op >> 16) & 7; |
| 1926 | FLOAT(dreg, src); |
| 1927 | } |
| 1928 | |
| 1929 | void tms3203x_device::float_ind(UINT32 op) |
| 1930 | { |
| 1931 | UINT32 src = RMEM(INDIRECT_D(op, op >> 8)); |
| 1932 | int dreg = (op >> 16) & 7; |
| 1933 | FLOAT(dreg, src); |
| 1934 | } |
| 1935 | |
| 1936 | void tms3203x_device::float_imm(UINT32 op) |
| 1937 | { |
| 1938 | UINT32 src = (INT16)op; |
| 1939 | int dreg = (op >> 16) & 7; |
| 1940 | FLOAT(dreg, src); |
| 1941 | } |
| 1942 | |
| 1943 | /*-----------------------------------------------------*/ |
| 1944 | |
| 1945 | void tms3203x_device::idle(UINT32 op) |
| 1946 | { |
| 1947 | m_is_idling = true; |
| 1948 | IREG(TMR_ST) |= GIEFLAG; |
| 1949 | check_irqs(); |
| 1950 | if (m_is_idling) |
| 1951 | m_icount = 0; |
| 1952 | } |
| 1953 | |
| 1954 | /*-----------------------------------------------------*/ |
| 1955 | |
| 1956 | void tms3203x_device::lde_reg(UINT32 op) |
| 1957 | { |
| 1958 | int dreg = (op >> 16) & 7; |
| 1959 | m_r[dreg].set_exponent(m_r[op & 7].exponent()); |
| 1960 | if (m_r[dreg].exponent() == -128) |
| 1961 | m_r[dreg].set_mantissa(0); |
| 1962 | } |
| 1963 | |
| 1964 | void tms3203x_device::lde_dir(UINT32 op) |
| 1965 | { |
| 1966 | UINT32 res = RMEM(DIRECT(op)); |
| 1967 | int dreg = (op >> 16) & 7; |
| 1968 | LONG2FP(TMR_TEMP1, res); |
| 1969 | m_r[dreg].set_exponent(m_r[TMR_TEMP1].exponent()); |
| 1970 | if (m_r[dreg].exponent() == -128) |
| 1971 | m_r[dreg].set_mantissa(0); |
| 1972 | } |
| 1973 | |
| 1974 | void tms3203x_device::lde_ind(UINT32 op) |
| 1975 | { |
| 1976 | UINT32 res = RMEM(INDIRECT_D(op, op >> 8)); |
| 1977 | int dreg = (op >> 16) & 7; |
| 1978 | LONG2FP(TMR_TEMP1, res); |
| 1979 | m_r[dreg].set_exponent(m_r[TMR_TEMP1].exponent()); |
| 1980 | if (m_r[dreg].exponent() == -128) |
| 1981 | m_r[dreg].set_mantissa(0); |
| 1982 | } |
| 1983 | |
| 1984 | void tms3203x_device::lde_imm(UINT32 op) |
| 1985 | { |
| 1986 | int dreg = (op >> 16) & 7; |
| 1987 | SHORT2FP(TMR_TEMP1, op); |
| 1988 | m_r[dreg].set_exponent(m_r[TMR_TEMP1].exponent()); |
| 1989 | if (m_r[dreg].exponent() == -128) |
| 1990 | m_r[dreg].set_mantissa(0); |
| 1991 | } |
| 1992 | |
| 1993 | /*-----------------------------------------------------*/ |
| 1994 | |
| 1995 | void tms3203x_device::ldf_reg(UINT32 op) |
| 1996 | { |
| 1997 | int dreg = (op >> 16) & 7; |
| 1998 | m_r[dreg] = m_r[op & 7]; |
| 1999 | CLR_NZVUF(); |
| 2000 | OR_NZF(m_r[dreg]); |
| 2001 | } |
| 2002 | |
| 2003 | void tms3203x_device::ldf_dir(UINT32 op) |
| 2004 | { |
| 2005 | UINT32 res = RMEM(DIRECT(op)); |
| 2006 | int dreg = (op >> 16) & 7; |
| 2007 | LONG2FP(dreg, res); |
| 2008 | CLR_NZVUF(); |
| 2009 | OR_NZF(m_r[dreg]); |
| 2010 | } |
| 2011 | |
| 2012 | void tms3203x_device::ldf_ind(UINT32 op) |
| 2013 | { |
| 2014 | UINT32 res = RMEM(INDIRECT_D(op, op >> 8)); |
| 2015 | int dreg = (op >> 16) & 7; |
| 2016 | LONG2FP(dreg, res); |
| 2017 | CLR_NZVUF(); |
| 2018 | OR_NZF(m_r[dreg]); |
| 2019 | } |
| 2020 | |
| 2021 | void tms3203x_device::ldf_imm(UINT32 op) |
| 2022 | { |
| 2023 | int dreg = (op >> 16) & 7; |
| 2024 | SHORT2FP(dreg, op); |
| 2025 | CLR_NZVUF(); |
| 2026 | OR_NZF(m_r[dreg]); |
| 2027 | } |
| 2028 | |
| 2029 | /*-----------------------------------------------------*/ |
| 2030 | |
| 2031 | void tms3203x_device::ldfi_dir(UINT32 op) { unimplemented(op); } |
| 2032 | void tms3203x_device::ldfi_ind(UINT32 op) { unimplemented(op); } |
| 2033 | |
| 2034 | /*-----------------------------------------------------*/ |
| 2035 | |
| 2036 | #define LDI(dreg, src) \ |
| 2037 | { \ |
| 2038 | IREG(dreg) = src; \ |
| 2039 | if (dreg < 8) \ |
| 2040 | { \ |
| 2041 | CLR_NZVUF(); \ |
| 2042 | OR_NZ(src); \ |
| 2043 | } \ |
| 2044 | else if (dreg >= TMR_BK) \ |
| 2045 | update_special(dreg); \ |
| 2046 | } |
| 2047 | |
| 2048 | void tms3203x_device::ldi_reg(UINT32 op) |
| 2049 | { |
| 2050 | UINT32 src = IREG(op & 31); |
| 2051 | int dreg = (op >> 16) & 31; |
| 2052 | LDI(dreg, src); |
| 2053 | } |
| 2054 | |
| 2055 | void tms3203x_device::ldi_dir(UINT32 op) |
| 2056 | { |
| 2057 | UINT32 src = RMEM(DIRECT(op)); |
| 2058 | int dreg = (op >> 16) & 31; |
| 2059 | LDI(dreg, src); |
| 2060 | } |
| 2061 | |
| 2062 | void tms3203x_device::ldi_ind(UINT32 op) |
| 2063 | { |
| 2064 | UINT32 src = RMEM(INDIRECT_D(op, op >> 8)); |
| 2065 | int dreg = (op >> 16) & 31; |
| 2066 | LDI(dreg, src); |
| 2067 | } |
| 2068 | |
| 2069 | void tms3203x_device::ldi_imm(UINT32 op) |
| 2070 | { |
| 2071 | UINT32 src = (INT16)op; |
| 2072 | int dreg = (op >> 16) & 31; |
| 2073 | LDI(dreg, src); |
| 2074 | } |
| 2075 | |
| 2076 | /*-----------------------------------------------------*/ |
| 2077 | |
| 2078 | void tms3203x_device::ldii_dir(UINT32 op) { unimplemented(op); } |
| 2079 | void tms3203x_device::ldii_ind(UINT32 op) { unimplemented(op); } |
| 2080 | |
| 2081 | /*-----------------------------------------------------*/ |
| 2082 | |
| 2083 | void tms3203x_device::ldm_reg(UINT32 op) |
| 2084 | { |
| 2085 | int dreg = (op >> 16) & 7; |
| 2086 | m_r[dreg].set_mantissa(m_r[op & 7].mantissa()); |
| 2087 | } |
| 2088 | |
| 2089 | void tms3203x_device::ldm_dir(UINT32 op) |
| 2090 | { |
| 2091 | UINT32 res = RMEM(DIRECT(op)); |
| 2092 | int dreg = (op >> 16) & 7; |
| 2093 | m_r[dreg].set_mantissa(res); |
| 2094 | } |
| 2095 | |
| 2096 | void tms3203x_device::ldm_ind(UINT32 op) |
| 2097 | { |
| 2098 | UINT32 res = RMEM(INDIRECT_D(op, op >> 8)); |
| 2099 | int dreg = (op >> 16) & 7; |
| 2100 | m_r[dreg].set_mantissa(res); |
| 2101 | } |
| 2102 | |
| 2103 | void tms3203x_device::ldm_imm(UINT32 op) |
| 2104 | { |
| 2105 | int dreg = (op >> 16) & 7; |
| 2106 | SHORT2FP(TMR_TEMP1, op); |
| 2107 | m_r[dreg].set_mantissa(m_r[TMR_TEMP1].mantissa()); |
| 2108 | } |
| 2109 | |
| 2110 | /*-----------------------------------------------------*/ |
| 2111 | |
| 2112 | #define LSH(dreg, src, count) \ |
| 2113 | { \ |
| 2114 | UINT32 _res; \ |
| 2115 | INT32 _count = (INT16)(count << 9) >> 9; /* 7 LSBs */ \ |
| 2116 | if (_count < 0) \ |
| 2117 | { \ |
| 2118 | if (_count >= -31) \ |
| 2119 | _res = (UINT32)src >> -_count; \ |
| 2120 | else \ |
| 2121 | _res = 0; \ |
| 2122 | } \ |
| 2123 | else \ |
| 2124 | { \ |
| 2125 | if (_count <= 31) \ |
| 2126 | _res = (UINT32)src << _count; \ |
| 2127 | else \ |
| 2128 | _res = 0; \ |
| 2129 | } \ |
| 2130 | IREG(dreg) = _res; \ |
| 2131 | if (dreg < 8) \ |
| 2132 | { \ |
| 2133 | CLR_NZCVUF(); \ |
| 2134 | OR_NZ(_res); \ |
| 2135 | if (_count < 0) \ |
| 2136 | { \ |
| 2137 | if (_count >= -32) \ |
| 2138 | OR_C(((UINT32)src >> (-_count - 1)) & 1); \ |
| 2139 | } \ |
| 2140 | else if (_count > 0) \ |
| 2141 | { \ |
| 2142 | if (_count <= 32) \ |
| 2143 | OR_C(((UINT32)src << (_count - 1)) >> 31); \ |
| 2144 | } \ |
| 2145 | } \ |
| 2146 | else if (dreg >= TMR_BK) \ |
| 2147 | update_special(dreg); \ |
| 2148 | } |
| 2149 | |
| 2150 | void tms3203x_device::lsh_reg(UINT32 op) |
| 2151 | { |
| 2152 | int dreg = (op >> 16) & 31; |
| 2153 | int count = IREG(op & 31); |
| 2154 | UINT32 src = IREG(dreg); |
| 2155 | LSH(dreg, src, count); |
| 2156 | } |
| 2157 | |
| 2158 | void tms3203x_device::lsh_dir(UINT32 op) |
| 2159 | { |
| 2160 | int dreg = (op >> 16) & 31; |
| 2161 | int count = RMEM(DIRECT(op)); |
| 2162 | UINT32 src = IREG(dreg); |
| 2163 | LSH(dreg, src, count); |
| 2164 | } |
| 2165 | |
| 2166 | void tms3203x_device::lsh_ind(UINT32 op) |
| 2167 | { |
| 2168 | int dreg = (op >> 16) & 31; |
| 2169 | int count = RMEM(INDIRECT_D(op, op >> 8)); |
| 2170 | UINT32 src = IREG(dreg); |
| 2171 | LSH(dreg, src, count); |
| 2172 | } |
| 2173 | |
| 2174 | void tms3203x_device::lsh_imm(UINT32 op) |
| 2175 | { |
| 2176 | int dreg = (op >> 16) & 31; |
| 2177 | int count = op; |
| 2178 | UINT32 src = IREG(dreg); |
| 2179 | LSH(dreg, src, count); |
| 2180 | } |
| 2181 | |
| 2182 | /*-----------------------------------------------------*/ |
| 2183 | |
| 2184 | void tms3203x_device::mpyf_reg(UINT32 op) |
| 2185 | { |
| 2186 | int dreg = (op >> 16) & 31; |
| 2187 | mpyf(m_r[dreg], m_r[dreg], m_r[op & 31]); |
| 2188 | } |
| 2189 | |
| 2190 | void tms3203x_device::mpyf_dir(UINT32 op) |
| 2191 | { |
| 2192 | UINT32 res = RMEM(DIRECT(op)); |
| 2193 | int dreg = (op >> 16) & 31; |
| 2194 | LONG2FP(TMR_TEMP1, res); |
| 2195 | mpyf(m_r[dreg], m_r[dreg], m_r[TMR_TEMP1]); |
| 2196 | } |
| 2197 | |
| 2198 | void tms3203x_device::mpyf_ind(UINT32 op) |
| 2199 | { |
| 2200 | UINT32 res = RMEM(INDIRECT_D(op, op >> 8)); |
| 2201 | int dreg = (op >> 16) & 31; |
| 2202 | LONG2FP(TMR_TEMP1, res); |
| 2203 | mpyf(m_r[dreg], m_r[dreg], m_r[TMR_TEMP1]); |
| 2204 | } |
| 2205 | |
| 2206 | void tms3203x_device::mpyf_imm(UINT32 op) |
| 2207 | { |
| 2208 | int dreg = (op >> 16) & 31; |
| 2209 | SHORT2FP(TMR_TEMP1, op); |
| 2210 | mpyf(m_r[dreg], m_r[dreg], m_r[TMR_TEMP1]); |
| 2211 | } |
| 2212 | |
| 2213 | /*-----------------------------------------------------*/ |
| 2214 | |
| 2215 | #define MPYI(dreg, src1, src2) \ |
| 2216 | { \ |
| 2217 | INT64 _res = (INT64)((INT32)(src1 << 8) >> 8) * (INT64)((INT32)(src2 << 8) >> 8);\ |
| 2218 | if (!OVM() || (_res >= -(INT64)0x80000000 && _res <= (INT64)0x7fffffff)) \ |
| 2219 | IREG(dreg) = _res; \ |
| 2220 | else \ |
| 2221 | IREG(dreg) = (_res < 0) ? 0x80000000 : 0x7fffffff; \ |
| 2222 | if (dreg < 8) \ |
| 2223 | { \ |
| 2224 | CLR_NZVUF(); \ |
| 2225 | OR_NZ((UINT32)_res); \ |
| 2226 | if (_res < -(INT64)0x80000000 || _res > (INT64)0x7fffffff) \ |
| 2227 | IREG(TMR_ST) |= VFLAG | LVFLAG; \ |
| 2228 | } \ |
| 2229 | else if (dreg >= TMR_BK) \ |
| 2230 | update_special(dreg); \ |
| 2231 | } |
| 2232 | |
| 2233 | void tms3203x_device::mpyi_reg(UINT32 op) |
| 2234 | { |
| 2235 | UINT32 src = IREG(op & 31); |
| 2236 | int dreg = (op >> 16) & 31; |
| 2237 | UINT32 dst = IREG(dreg); |
| 2238 | MPYI(dreg, dst, src); |
| 2239 | } |
| 2240 | |
| 2241 | void tms3203x_device::mpyi_dir(UINT32 op) |
| 2242 | { |
| 2243 | UINT32 src = RMEM(DIRECT(op)); |
| 2244 | int dreg = (op >> 16) & 31; |
| 2245 | UINT32 dst = IREG(dreg); |
| 2246 | MPYI(dreg, dst, src); |
| 2247 | } |
| 2248 | |
| 2249 | void tms3203x_device::mpyi_ind(UINT32 op) |
| 2250 | { |
| 2251 | UINT32 src = RMEM(INDIRECT_D(op, op >> 8)); |
| 2252 | int dreg = (op >> 16) & 31; |
| 2253 | UINT32 dst = IREG(dreg); |
| 2254 | MPYI(dreg, dst, src); |
| 2255 | } |
| 2256 | |
| 2257 | void tms3203x_device::mpyi_imm(UINT32 op) |
| 2258 | { |
| 2259 | UINT32 src = (INT16)op; |
| 2260 | int dreg = (op >> 16) & 31; |
| 2261 | UINT32 dst = IREG(dreg); |
| 2262 | MPYI(dreg, dst, src); |
| 2263 | } |
| 2264 | |
| 2265 | /*-----------------------------------------------------*/ |
| 2266 | |
| 2267 | #define NEGB(dreg, src) \ |
| 2268 | { \ |
| 2269 | UINT32 _res = 0 - src - (IREG(TMR_ST) & CFLAG); \ |
| 2270 | if (!OVM() || !OVERFLOW_SUB(0,src,_res)) \ |
| 2271 | IREG(dreg) = _res; \ |
| 2272 | else \ |
| 2273 | IREG(dreg) = ((INT32)src < 0) ? 0x80000000 : 0x7fffffff; \ |
| 2274 | if (dreg < 8) \ |
| 2275 | { \ |
| 2276 | UINT32 tempc = IREG(TMR_ST) & CFLAG; \ |
| 2277 | CLR_NZCVUF(); \ |
| 2278 | OR_C_SBB(0,src,tempc); \ |
| 2279 | OR_V_SUB(0,src,_res); \ |
| 2280 | OR_NZ(_res); \ |
| 2281 | } \ |
| 2282 | else if (dreg >= TMR_BK) \ |
| 2283 | update_special(dreg); \ |
| 2284 | } |
| 2285 | |
| 2286 | void tms3203x_device::negb_reg(UINT32 op) |
| 2287 | { |
| 2288 | UINT32 src = IREG(op & 31); |
| 2289 | int dreg = (op >> 16) & 31; |
| 2290 | NEGB(dreg, src); |
| 2291 | } |
| 2292 | |
| 2293 | void tms3203x_device::negb_dir(UINT32 op) |
| 2294 | { |
| 2295 | UINT32 src = RMEM(DIRECT(op)); |
| 2296 | int dreg = (op >> 16) & 31; |
| 2297 | NEGB(dreg, src); |
| 2298 | } |
| 2299 | |
| 2300 | void tms3203x_device::negb_ind(UINT32 op) |
| 2301 | { |
| 2302 | UINT32 src = RMEM(INDIRECT_D(op, op >> 8)); |
| 2303 | int dreg = (op >> 16) & 31; |
| 2304 | NEGB(dreg, src); |
| 2305 | } |
| 2306 | |
| 2307 | void tms3203x_device::negb_imm(UINT32 op) |
| 2308 | { |
| 2309 | UINT32 src = (INT16)op; |
| 2310 | int dreg = (op >> 16) & 31; |
| 2311 | NEGB(dreg, src); |
| 2312 | } |
| 2313 | |
| 2314 | /*-----------------------------------------------------*/ |
| 2315 | |
| 2316 | void tms3203x_device::negf_reg(UINT32 op) |
| 2317 | { |
| 2318 | int dreg = (op >> 16) & 7; |
| 2319 | negf(m_r[dreg], m_r[op & 7]); |
| 2320 | } |
| 2321 | |
| 2322 | void tms3203x_device::negf_dir(UINT32 op) |
| 2323 | { |
| 2324 | UINT32 res = RMEM(DIRECT(op)); |
| 2325 | int dreg = (op >> 16) & 7; |
| 2326 | LONG2FP(TMR_TEMP1, res); |
| 2327 | negf(m_r[dreg], m_r[TMR_TEMP1]); |
| 2328 | } |
| 2329 | |
| 2330 | void tms3203x_device::negf_ind(UINT32 op) |
| 2331 | { |
| 2332 | UINT32 res = RMEM(INDIRECT_D(op, op >> 8)); |
| 2333 | int dreg = (op >> 16) & 7; |
| 2334 | LONG2FP(TMR_TEMP1, res); |
| 2335 | negf(m_r[dreg], m_r[TMR_TEMP1]); |
| 2336 | } |
| 2337 | |
| 2338 | void tms3203x_device::negf_imm(UINT32 op) |
| 2339 | { |
| 2340 | int dreg = (op >> 16) & 7; |
| 2341 | SHORT2FP(TMR_TEMP1, op); |
| 2342 | negf(m_r[dreg], m_r[TMR_TEMP1]); |
| 2343 | } |
| 2344 | |
| 2345 | /*-----------------------------------------------------*/ |
| 2346 | |
| 2347 | #define NEGI(dreg, src) \ |
| 2348 | { \ |
| 2349 | UINT32 _res = 0 - src; \ |
| 2350 | if (!OVM() || !OVERFLOW_SUB(0,src,_res)) \ |
| 2351 | IREG(dreg) = _res; \ |
| 2352 | else \ |
| 2353 | IREG(dreg) = ((INT32)src < 0) ? 0x80000000 : 0x7fffffff; \ |
| 2354 | if (dreg < 8) \ |
| 2355 | { \ |
| 2356 | CLR_NZCVUF(); \ |
| 2357 | OR_C_SUB(0,src,_res); \ |
| 2358 | OR_V_SUB(0,src,_res); \ |
| 2359 | OR_NZ(_res); \ |
| 2360 | } \ |
| 2361 | else if (dreg >= TMR_BK) \ |
| 2362 | update_special(dreg); \ |
| 2363 | } |
| 2364 | |
| 2365 | void tms3203x_device::negi_reg(UINT32 op) |
| 2366 | { |
| 2367 | UINT32 src = IREG(op & 31); |
| 2368 | int dreg = (op >> 16) & 31; |
| 2369 | NEGI(dreg, src); |
| 2370 | } |
| 2371 | |
| 2372 | void tms3203x_device::negi_dir(UINT32 op) |
| 2373 | { |
| 2374 | UINT32 src = RMEM(DIRECT(op)); |
| 2375 | int dreg = (op >> 16) & 31; |
| 2376 | NEGI(dreg, src); |
| 2377 | } |
| 2378 | |
| 2379 | void tms3203x_device::negi_ind(UINT32 op) |
| 2380 | { |
| 2381 | UINT32 src = RMEM(INDIRECT_D(op, op >> 8)); |
| 2382 | int dreg = (op >> 16) & 31; |
| 2383 | NEGI(dreg, src); |
| 2384 | } |
| 2385 | |
| 2386 | void tms3203x_device::negi_imm(UINT32 op) |
| 2387 | { |
| 2388 | UINT32 src = (INT16)op; |
| 2389 | int dreg = (op >> 16) & 31; |
| 2390 | NEGI(dreg, src); |
| 2391 | } |
| 2392 | |
| 2393 | /*-----------------------------------------------------*/ |
| 2394 | |
| 2395 | void tms3203x_device::nop_reg(UINT32 op) |
| 2396 | { |
| 2397 | } |
| 2398 | |
| 2399 | void tms3203x_device::nop_ind(UINT32 op) |
| 2400 | { |
| 2401 | RMEM(INDIRECT_D(op, op >> 8)); |
| 2402 | } |
| 2403 | |
| 2404 | /*-----------------------------------------------------*/ |
| 2405 | |
| 2406 | void tms3203x_device::norm_reg(UINT32 op) |
| 2407 | { |
| 2408 | int dreg = (op >> 16) & 7; |
| 2409 | norm(m_r[dreg], m_r[op & 7]); |
| 2410 | } |
| 2411 | |
| 2412 | void tms3203x_device::norm_dir(UINT32 op) |
| 2413 | { |
| 2414 | UINT32 res = RMEM(DIRECT(op)); |
| 2415 | int dreg = (op >> 16) & 7; |
| 2416 | LONG2FP(TMR_TEMP1, res); |
| 2417 | norm(m_r[dreg], m_r[TMR_TEMP1]); |
| 2418 | } |
| 2419 | |
| 2420 | void tms3203x_device::norm_ind(UINT32 op) |
| 2421 | { |
| 2422 | UINT32 res = RMEM(INDIRECT_D(op, op >> 8)); |
| 2423 | int dreg = (op >> 16) & 7; |
| 2424 | LONG2FP(TMR_TEMP1, res); |
| 2425 | norm(m_r[dreg], m_r[TMR_TEMP1]); |
| 2426 | } |
| 2427 | |
| 2428 | void tms3203x_device::norm_imm(UINT32 op) |
| 2429 | { |
| 2430 | int dreg = (op >> 16) & 7; |
| 2431 | SHORT2FP(TMR_TEMP1, op); |
| 2432 | norm(m_r[dreg], m_r[TMR_TEMP1]); |
| 2433 | } |
| 2434 | |
| 2435 | /*-----------------------------------------------------*/ |
| 2436 | |
| 2437 | #define NOT(dreg, src) \ |
| 2438 | { \ |
| 2439 | UINT32 _res = ~(src); \ |
| 2440 | IREG(dreg) = _res; \ |
| 2441 | if (dreg < 8) \ |
| 2442 | { \ |
| 2443 | CLR_NZVUF(); \ |
| 2444 | OR_NZ(_res); \ |
| 2445 | } \ |
| 2446 | else if (dreg >= TMR_BK) \ |
| 2447 | update_special(dreg); \ |
| 2448 | } |
| 2449 | |
| 2450 | void tms3203x_device::not_reg(UINT32 op) |
| 2451 | { |
| 2452 | UINT32 src = IREG(op & 31); |
| 2453 | int dreg = (op >> 16) & 31; |
| 2454 | NOT(dreg, src); |
| 2455 | } |
| 2456 | |
| 2457 | void tms3203x_device::not_dir(UINT32 op) |
| 2458 | { |
| 2459 | UINT32 src = RMEM(DIRECT(op)); |
| 2460 | int dreg = (op >> 16) & 31; |
| 2461 | NOT(dreg, src); |
| 2462 | } |
| 2463 | |
| 2464 | void tms3203x_device::not_ind(UINT32 op) |
| 2465 | { |
| 2466 | UINT32 src = RMEM(INDIRECT_D(op, op >> 8)); |
| 2467 | int dreg = (op >> 16) & 31; |
| 2468 | NOT(dreg, src); |
| 2469 | } |
| 2470 | |
| 2471 | void tms3203x_device::not_imm(UINT32 op) |
| 2472 | { |
| 2473 | UINT32 src = (UINT16)op; |
| 2474 | int dreg = (op >> 16) & 31; |
| 2475 | NOT(dreg, src); |
| 2476 | } |
| 2477 | |
| 2478 | /*-----------------------------------------------------*/ |
| 2479 | |
| 2480 | void tms3203x_device::pop(UINT32 op) |
| 2481 | { |
| 2482 | int dreg = (op >> 16) & 31; |
| 2483 | UINT32 val = RMEM(IREG(TMR_SP)--); |
| 2484 | IREG(dreg) = val; |
| 2485 | if (dreg < 8) |
| 2486 | { |
| 2487 | CLR_NZVUF(); |
| 2488 | OR_NZ(val); |
| 2489 | } |
| 2490 | else if (dreg >= TMR_BK) |
| 2491 | update_special(dreg); |
| 2492 | } |
| 2493 | |
| 2494 | void tms3203x_device::popf(UINT32 op) |
| 2495 | { |
| 2496 | int dreg = (op >> 16) & 7; |
| 2497 | UINT32 val = RMEM(IREG(TMR_SP)--); |
| 2498 | LONG2FP(dreg, val); |
| 2499 | CLR_NZVUF(); |
| 2500 | OR_NZF(m_r[dreg]); |
| 2501 | } |
| 2502 | |
| 2503 | void tms3203x_device::push(UINT32 op) |
| 2504 | { |
| 2505 | WMEM(++IREG(TMR_SP), IREG((op >> 16) & 31)); |
| 2506 | } |
| 2507 | |
| 2508 | void tms3203x_device::pushf(UINT32 op) |
| 2509 | { |
| 2510 | int dreg = (op >> 16) & 7; |
| 2511 | WMEM(++IREG(TMR_SP), FP2LONG(dreg)); |
| 2512 | } |
| 2513 | |
| 2514 | /*-----------------------------------------------------*/ |
| 2515 | |
| 2516 | #define OR(dreg, src1, src2) \ |
| 2517 | { \ |
| 2518 | UINT32 _res = (src1) | (src2); \ |
| 2519 | IREG(dreg) = _res; \ |
| 2520 | if (dreg < 8) \ |
| 2521 | { \ |
| 2522 | CLR_NZVUF(); \ |
| 2523 | OR_NZ(_res); \ |
| 2524 | } \ |
| 2525 | else if (dreg >= TMR_BK) \ |
| 2526 | update_special(dreg); \ |
| 2527 | } |
| 2528 | |
| 2529 | void tms3203x_device::or_reg(UINT32 op) |
| 2530 | { |
| 2531 | UINT32 src = IREG(op & 31); |
| 2532 | int dreg = (op >> 16) & 31; |
| 2533 | UINT32 dst = IREG(dreg); |
| 2534 | OR(dreg, dst, src); |
| 2535 | } |
| 2536 | |
| 2537 | void tms3203x_device::or_dir(UINT32 op) |
| 2538 | { |
| 2539 | UINT32 src = RMEM(DIRECT(op)); |
| 2540 | int dreg = (op >> 16) & 31; |
| 2541 | UINT32 dst = IREG(dreg); |
| 2542 | OR(dreg, dst, src); |
| 2543 | } |
| 2544 | |
| 2545 | void tms3203x_device::or_ind(UINT32 op) |
| 2546 | { |
| 2547 | UINT32 src = RMEM(INDIRECT_D(op, op >> 8)); |
| 2548 | int dreg = (op >> 16) & 31; |
| 2549 | UINT32 dst = IREG(dreg); |
| 2550 | OR(dreg, dst, src); |
| 2551 | } |
| 2552 | |
| 2553 | void tms3203x_device::or_imm(UINT32 op) |
| 2554 | { |
| 2555 | UINT32 src = (UINT16)op; |
| 2556 | int dreg = (op >> 16) & 31; |
| 2557 | UINT32 dst = IREG(dreg); |
| 2558 | OR(dreg, dst, src); |
| 2559 | } |
| 2560 | |
| 2561 | /*-----------------------------------------------------*/ |
| 2562 | |
| 2563 | void tms3203x_device::maxspeed(UINT32 op) { unimplemented(op); } |
| 2564 | |
| 2565 | /*-----------------------------------------------------*/ |
| 2566 | |
| 2567 | #define RND(dreg) \ |
| 2568 | { \ |
| 2569 | INT32 man = FREGMAN(dreg); \ |
| 2570 | CLR_NVUF(); \ |
| 2571 | if (man < 0x7fffff80) \ |
| 2572 | { \ |
| 2573 | m_r[dreg].set_mantissa(((UINT32)man + 0x80) & 0xffffff00); \ |
| 2574 | OR_NUF(m_r[dreg]); \ |
| 2575 | } \ |
| 2576 | else if (FREGEXP(dreg) < 127) \ |
| 2577 | { \ |
| 2578 | m_r[dreg].set_mantissa(((UINT32)man + 0x80) & 0x7fffff00); \ |
| 2579 | m_r[dreg].set_exponent(FREGEXP(dreg) + 1); \ |
| 2580 | OR_NUF(m_r[dreg]); \ |
| 2581 | } \ |
| 2582 | else \ |
| 2583 | { \ |
| 2584 | m_r[dreg].set_mantissa(0x7fffff00); \ |
| 2585 | IREG(TMR_ST) |= VFLAG | LVFLAG; \ |
| 2586 | } \ |
| 2587 | } |
| 2588 | |
| 2589 | void tms3203x_device::rnd_reg(UINT32 op) |
| 2590 | { |
| 2591 | int sreg = op & 7; |
| 2592 | int dreg = (op >> 16) & 7; |
| 2593 | m_r[dreg] = m_r[sreg]; |
| 2594 | RND(dreg); |
| 2595 | } |
| 2596 | |
| 2597 | void tms3203x_device::rnd_dir(UINT32 op) |
| 2598 | { |
| 2599 | UINT32 res = RMEM(DIRECT(op)); |
| 2600 | int dreg = (op >> 16) & 7; |
| 2601 | LONG2FP(dreg, res); |
| 2602 | RND(dreg); |
| 2603 | } |
| 2604 | |
| 2605 | void tms3203x_device::rnd_ind(UINT32 op) |
| 2606 | { |
| 2607 | UINT32 res = RMEM(INDIRECT_D(op, op >> 8)); |
| 2608 | int dreg = (op >> 16) & 7; |
| 2609 | LONG2FP(dreg, res); |
| 2610 | RND(dreg); |
| 2611 | } |
| 2612 | |
| 2613 | void tms3203x_device::rnd_imm(UINT32 op) |
| 2614 | { |
| 2615 | int dreg = (op >> 16) & 7; |
| 2616 | SHORT2FP(dreg, op); |
| 2617 | RND(dreg); |
| 2618 | } |
| 2619 | |
| 2620 | /*-----------------------------------------------------*/ |
| 2621 | |
| 2622 | void tms3203x_device::rol(UINT32 op) |
| 2623 | { |
| 2624 | int dreg = (op >> 16) & 31; |
| 2625 | UINT32 res = IREG(dreg); |
| 2626 | int newcflag = res >> 31; |
| 2627 | res = (res << 1) | newcflag; |
| 2628 | IREG(dreg) = res; |
| 2629 | if (dreg < 8) |
| 2630 | { |
| 2631 | CLR_NZCVUF(); |
| 2632 | OR_NZ(res); |
| 2633 | OR_C(newcflag); |
| 2634 | } |
| 2635 | else if (dreg >= TMR_BK) |
| 2636 | update_special(dreg); |
| 2637 | } |
| 2638 | |
| 2639 | void tms3203x_device::rolc(UINT32 op) |
| 2640 | { |
| 2641 | int dreg = (op >> 16) & 31; |
| 2642 | UINT32 res = IREG(dreg); |
| 2643 | int newcflag = res >> 31; |
| 2644 | res = (res << 1) | (IREG(TMR_ST) & CFLAG); |
| 2645 | IREG(dreg) = res; |
| 2646 | if (dreg < 8) |
| 2647 | { |
| 2648 | CLR_NZCVUF(); |
| 2649 | OR_NZ(res); |
| 2650 | OR_C(newcflag); |
| 2651 | } |
| 2652 | else if (dreg >= TMR_BK) |
| 2653 | update_special(dreg); |
| 2654 | } |
| 2655 | |
| 2656 | void tms3203x_device::ror(UINT32 op) |
| 2657 | { |
| 2658 | int dreg = (op >> 16) & 31; |
| 2659 | UINT32 res = IREG(dreg); |
| 2660 | int newcflag = res & 1; |
| 2661 | res = (res >> 1) | (newcflag << 31); |
| 2662 | IREG(dreg) = res; |
| 2663 | if (dreg < 8) |
| 2664 | { |
| 2665 | CLR_NZCVUF(); |
| 2666 | OR_NZ(res); |
| 2667 | OR_C(newcflag); |
| 2668 | } |
| 2669 | else if (dreg >= TMR_BK) |
| 2670 | update_special(dreg); |
| 2671 | } |
| 2672 | |
| 2673 | void tms3203x_device::rorc(UINT32 op) |
| 2674 | { |
| 2675 | int dreg = (op >> 16) & 31; |
| 2676 | UINT32 res = IREG(dreg); |
| 2677 | int newcflag = res & 1; |
| 2678 | res = (res >> 1) | ((IREG(TMR_ST) & CFLAG) << 31); |
| 2679 | IREG(dreg) = res; |
| 2680 | if (dreg < 8) |
| 2681 | { |
| 2682 | CLR_NZCVUF(); |
| 2683 | OR_NZ(res); |
| 2684 | OR_C(newcflag); |
| 2685 | } |
| 2686 | else if (dreg >= TMR_BK) |
| 2687 | update_special(dreg); |
| 2688 | } |
| 2689 | |
| 2690 | /*-----------------------------------------------------*/ |
| 2691 | |
| 2692 | void tms3203x_device::rtps_reg(UINT32 op) |
| 2693 | { |
| 2694 | IREG(TMR_RC) = IREG(op & 31); |
| 2695 | IREG(TMR_RS) = m_pc; |
| 2696 | IREG(TMR_RE) = m_pc; |
| 2697 | IREG(TMR_ST) |= RMFLAG; |
| 2698 | m_icount -= 3*2; |
| 2699 | m_delayed = true; |
| 2700 | } |
| 2701 | |
| 2702 | void tms3203x_device::rtps_dir(UINT32 op) |
| 2703 | { |
| 2704 | IREG(TMR_RC) = RMEM(DIRECT(op)); |
| 2705 | IREG(TMR_RS) = m_pc; |
| 2706 | IREG(TMR_RE) = m_pc; |
| 2707 | IREG(TMR_ST) |= RMFLAG; |
| 2708 | m_icount -= 3*2; |
| 2709 | m_delayed = true; |
| 2710 | } |
| 2711 | |
| 2712 | void tms3203x_device::rtps_ind(UINT32 op) |
| 2713 | { |
| 2714 | IREG(TMR_RC) = RMEM(INDIRECT_D(op, op >> 8)); |
| 2715 | IREG(TMR_RS) = m_pc; |
| 2716 | IREG(TMR_RE) = m_pc; |
| 2717 | IREG(TMR_ST) |= RMFLAG; |
| 2718 | m_icount -= 3*2; |
| 2719 | m_delayed = true; |
| 2720 | } |
| 2721 | |
| 2722 | void tms3203x_device::rtps_imm(UINT32 op) |
| 2723 | { |
| 2724 | IREG(TMR_RC) = (UINT16)op; |
| 2725 | IREG(TMR_RS) = m_pc; |
| 2726 | IREG(TMR_RE) = m_pc; |
| 2727 | IREG(TMR_ST) |= RMFLAG; |
| 2728 | m_icount -= 3*2; |
| 2729 | m_delayed = true; |
| 2730 | } |
| 2731 | |
| 2732 | /*-----------------------------------------------------*/ |
| 2733 | |
| 2734 | void tms3203x_device::stf_dir(UINT32 op) |
| 2735 | { |
| 2736 | WMEM(DIRECT(op), FP2LONG((op >> 16) & 7)); |
| 2737 | } |
| 2738 | |
| 2739 | void tms3203x_device::stf_ind(UINT32 op) |
| 2740 | { |
| 2741 | WMEM(INDIRECT_D(op, op >> 8), FP2LONG((op >> 16) & 7)); |
| 2742 | } |
| 2743 | |
| 2744 | /*-----------------------------------------------------*/ |
| 2745 | |
| 2746 | void tms3203x_device::stfi_dir(UINT32 op) { unimplemented(op); } |
| 2747 | void tms3203x_device::stfi_ind(UINT32 op) { unimplemented(op); } |
| 2748 | |
| 2749 | /*-----------------------------------------------------*/ |
| 2750 | |
| 2751 | void tms3203x_device::sti_dir(UINT32 op) |
| 2752 | { |
| 2753 | WMEM(DIRECT(op), IREG((op >> 16) & 31)); |
| 2754 | } |
| 2755 | |
| 2756 | void tms3203x_device::sti_ind(UINT32 op) |
| 2757 | { |
| 2758 | WMEM(INDIRECT_D(op, op >> 8), IREG((op >> 16) & 31)); |
| 2759 | } |
| 2760 | |
| 2761 | /*-----------------------------------------------------*/ |
| 2762 | |
| 2763 | void tms3203x_device::stii_dir(UINT32 op) { unimplemented(op); } |
| 2764 | void tms3203x_device::stii_ind(UINT32 op) { unimplemented(op); } |
| 2765 | |
| 2766 | /*-----------------------------------------------------*/ |
| 2767 | |
| 2768 | void tms3203x_device::sigi(UINT32 op) { unimplemented(op); } |
| 2769 | |
| 2770 | /*-----------------------------------------------------*/ |
| 2771 | |
| 2772 | #define SUBB(dreg, src1, src2) \ |
| 2773 | { \ |
| 2774 | UINT32 _res = src1 - src2 - (IREG(TMR_ST) & CFLAG); \ |
| 2775 | if (!OVM() || !OVERFLOW_SUB(src1,src2,_res)) \ |
| 2776 | IREG(dreg) = _res; \ |
| 2777 | else \ |
| 2778 | IREG(dreg) = ((INT32)src1 < 0) ? 0x80000000 : 0x7fffffff; \ |
| 2779 | if (dreg < 8) \ |
| 2780 | { \ |
| 2781 | UINT32 tempc = IREG(TMR_ST) & CFLAG; \ |
| 2782 | CLR_NZCVUF(); \ |
| 2783 | OR_C_SBB(src1,src2,tempc); \ |
| 2784 | OR_V_SUB(src1,src2,_res); \ |
| 2785 | OR_NZ(_res); \ |
| 2786 | } \ |
| 2787 | else if (dreg >= TMR_BK) \ |
| 2788 | update_special(dreg); \ |
| 2789 | } |
| 2790 | |
| 2791 | void tms3203x_device::subb_reg(UINT32 op) |
| 2792 | { |
| 2793 | UINT32 src = IREG(op & 31); |
| 2794 | int dreg = (op >> 16) & 31; |
| 2795 | UINT32 dst = IREG(dreg); |
| 2796 | SUBB(dreg, dst, src); |
| 2797 | } |
| 2798 | |
| 2799 | void tms3203x_device::subb_dir(UINT32 op) |
| 2800 | { |
| 2801 | UINT32 src = RMEM(DIRECT(op)); |
| 2802 | int dreg = (op >> 16) & 31; |
| 2803 | UINT32 dst = IREG(dreg); |
| 2804 | SUBB(dreg, dst, src); |
| 2805 | } |
| 2806 | |
| 2807 | void tms3203x_device::subb_ind(UINT32 op) |
| 2808 | { |
| 2809 | UINT32 src = RMEM(INDIRECT_D(op, op >> 8)); |
| 2810 | int dreg = (op >> 16) & 31; |
| 2811 | UINT32 dst = IREG(dreg); |
| 2812 | SUBB(dreg, dst, src); |
| 2813 | } |
| 2814 | |
| 2815 | void tms3203x_device::subb_imm(UINT32 op) |
| 2816 | { |
| 2817 | UINT32 src = (INT16)op; |
| 2818 | int dreg = (op >> 16) & 31; |
| 2819 | UINT32 dst = IREG(dreg); |
| 2820 | SUBB(dreg, dst, src); |
| 2821 | } |
| 2822 | |
| 2823 | /*-----------------------------------------------------*/ |
| 2824 | |
| 2825 | #define SUBC(dreg, src) \ |
| 2826 | { \ |
| 2827 | UINT32 dst = IREG(dreg); \ |
| 2828 | if (dst >= src) \ |
| 2829 | IREG(dreg) = ((dst - src) << 1) | 1; \ |
| 2830 | else \ |
| 2831 | IREG(dreg) = dst << 1; \ |
| 2832 | if (dreg >= TMR_BK) \ |
| 2833 | update_special(dreg); \ |
| 2834 | } |
| 2835 | |
| 2836 | void tms3203x_device::subc_reg(UINT32 op) |
| 2837 | { |
| 2838 | UINT32 src = IREG(op & 31); |
| 2839 | int dreg = (op >> 16) & 31; |
| 2840 | SUBC(dreg, src); |
| 2841 | } |
| 2842 | |
| 2843 | void tms3203x_device::subc_dir(UINT32 op) |
| 2844 | { |
| 2845 | UINT32 src = RMEM(DIRECT(op)); |
| 2846 | int dreg = (op >> 16) & 31; |
| 2847 | SUBC(dreg, src); |
| 2848 | } |
| 2849 | |
| 2850 | void tms3203x_device::subc_ind(UINT32 op) |
| 2851 | { |
| 2852 | UINT32 src = RMEM(INDIRECT_D(op, op >> 8)); |
| 2853 | int dreg = (op >> 16) & 31; |
| 2854 | SUBC(dreg, src); |
| 2855 | } |
| 2856 | |
| 2857 | void tms3203x_device::subc_imm(UINT32 op) |
| 2858 | { |
| 2859 | UINT32 src = (INT16)op; |
| 2860 | int dreg = (op >> 16) & 31; |
| 2861 | SUBC(dreg, src); |
| 2862 | } |
| 2863 | |
| 2864 | /*-----------------------------------------------------*/ |
| 2865 | |
| 2866 | void tms3203x_device::subf_reg(UINT32 op) |
| 2867 | { |
| 2868 | int dreg = (op >> 16) & 7; |
| 2869 | subf(m_r[dreg], m_r[dreg], m_r[op & 7]); |
| 2870 | } |
| 2871 | |
| 2872 | void tms3203x_device::subf_dir(UINT32 op) |
| 2873 | { |
| 2874 | UINT32 res = RMEM(DIRECT(op)); |
| 2875 | int dreg = (op >> 16) & 7; |
| 2876 | LONG2FP(TMR_TEMP1, res); |
| 2877 | subf(m_r[dreg], m_r[dreg], m_r[TMR_TEMP1]); |
| 2878 | } |
| 2879 | |
| 2880 | void tms3203x_device::subf_ind(UINT32 op) |
| 2881 | { |
| 2882 | UINT32 res = RMEM(INDIRECT_D(op, op >> 8)); |
| 2883 | int dreg = (op >> 16) & 7; |
| 2884 | LONG2FP(TMR_TEMP1, res); |
| 2885 | subf(m_r[dreg], m_r[dreg], m_r[TMR_TEMP1]); |
| 2886 | } |
| 2887 | |
| 2888 | void tms3203x_device::subf_imm(UINT32 op) |
| 2889 | { |
| 2890 | int dreg = (op >> 16) & 7; |
| 2891 | SHORT2FP(TMR_TEMP1, op); |
| 2892 | subf(m_r[dreg], m_r[dreg], m_r[TMR_TEMP1]); |
| 2893 | } |
| 2894 | |
| 2895 | /*-----------------------------------------------------*/ |
| 2896 | |
| 2897 | #define SUBI(dreg, src1, src2) \ |
| 2898 | { \ |
| 2899 | UINT32 _res = src1 - src2; \ |
| 2900 | if (!OVM() || !OVERFLOW_SUB(src1,src2,_res)) \ |
| 2901 | IREG(dreg) = _res; \ |
| 2902 | else \ |
| 2903 | IREG(dreg) = ((INT32)src1 < 0) ? 0x80000000 : 0x7fffffff; \ |
| 2904 | if (dreg < 8) \ |
| 2905 | { \ |
| 2906 | CLR_NZCVUF(); \ |
| 2907 | OR_C_SUB(src1,src2,_res); \ |
| 2908 | OR_V_SUB(src1,src2,_res); \ |
| 2909 | OR_NZ(_res); \ |
| 2910 | } \ |
| 2911 | else if (dreg >= TMR_BK) \ |
| 2912 | update_special(dreg); \ |
| 2913 | } |
| 2914 | |
| 2915 | void tms3203x_device::subi_reg(UINT32 op) |
| 2916 | { |
| 2917 | UINT32 src = IREG(op & 31); |
| 2918 | int dreg = (op >> 16) & 31; |
| 2919 | UINT32 dst = IREG(dreg); |
| 2920 | SUBI(dreg, dst, src); |
| 2921 | } |
| 2922 | |
| 2923 | void tms3203x_device::subi_dir(UINT32 op) |
| 2924 | { |
| 2925 | UINT32 src = RMEM(DIRECT(op)); |
| 2926 | int dreg = (op >> 16) & 31; |
| 2927 | UINT32 dst = IREG(dreg); |
| 2928 | SUBI(dreg, dst, src); |
| 2929 | } |
| 2930 | |
| 2931 | void tms3203x_device::subi_ind(UINT32 op) |
| 2932 | { |
| 2933 | UINT32 src = RMEM(INDIRECT_D(op, op >> 8)); |
| 2934 | int dreg = (op >> 16) & 31; |
| 2935 | UINT32 dst = IREG(dreg); |
| 2936 | SUBI(dreg, dst, src); |
| 2937 | } |
| 2938 | |
| 2939 | void tms3203x_device::subi_imm(UINT32 op) |
| 2940 | { |
| 2941 | UINT32 src = (INT16)op; |
| 2942 | int dreg = (op >> 16) & 31; |
| 2943 | UINT32 dst = IREG(dreg); |
| 2944 | SUBI(dreg, dst, src); |
| 2945 | } |
| 2946 | |
| 2947 | /*-----------------------------------------------------*/ |
| 2948 | |
| 2949 | void tms3203x_device::subrb_reg(UINT32 op) |
| 2950 | { |
| 2951 | UINT32 src = IREG(op & 31); |
| 2952 | int dreg = (op >> 16) & 31; |
| 2953 | UINT32 dst = IREG(dreg); |
| 2954 | SUBB(dreg, src, dst); |
| 2955 | } |
| 2956 | |
| 2957 | void tms3203x_device::subrb_dir(UINT32 op) |
| 2958 | { |
| 2959 | UINT32 src = RMEM(DIRECT(op)); |
| 2960 | int dreg = (op >> 16) & 31; |
| 2961 | UINT32 dst = IREG(dreg); |
| 2962 | SUBB(dreg, src, dst); |
| 2963 | } |
| 2964 | |
| 2965 | void tms3203x_device::subrb_ind(UINT32 op) |
| 2966 | { |
| 2967 | UINT32 src = RMEM(INDIRECT_D(op, op >> 8)); |
| 2968 | int dreg = (op >> 16) & 31; |
| 2969 | UINT32 dst = IREG(dreg); |
| 2970 | SUBB(dreg, src, dst); |
| 2971 | } |
| 2972 | |
| 2973 | void tms3203x_device::subrb_imm(UINT32 op) |
| 2974 | { |
| 2975 | UINT32 src = (INT16)op; |
| 2976 | int dreg = (op >> 16) & 31; |
| 2977 | UINT32 dst = IREG(dreg); |
| 2978 | SUBB(dreg, src, dst); |
| 2979 | } |
| 2980 | |
| 2981 | /*-----------------------------------------------------*/ |
| 2982 | |
| 2983 | void tms3203x_device::subrf_reg(UINT32 op) |
| 2984 | { |
| 2985 | int dreg = (op >> 16) & 7; |
| 2986 | subf(m_r[dreg], m_r[op & 7], m_r[dreg]); |
| 2987 | } |
| 2988 | |
| 2989 | void tms3203x_device::subrf_dir(UINT32 op) |
| 2990 | { |
| 2991 | UINT32 res = RMEM(DIRECT(op)); |
| 2992 | int dreg = (op >> 16) & 7; |
| 2993 | LONG2FP(TMR_TEMP1, res); |
| 2994 | subf(m_r[dreg], m_r[TMR_TEMP1], m_r[dreg]); |
| 2995 | } |
| 2996 | |
| 2997 | void tms3203x_device::subrf_ind(UINT32 op) |
| 2998 | { |
| 2999 | UINT32 res = RMEM(INDIRECT_D(op, op >> 8)); |
| 3000 | int dreg = (op >> 16) & 7; |
| 3001 | LONG2FP(TMR_TEMP1, res); |
| 3002 | subf(m_r[dreg], m_r[TMR_TEMP1], m_r[dreg]); |
| 3003 | } |
| 3004 | |
| 3005 | void tms3203x_device::subrf_imm(UINT32 op) |
| 3006 | { |
| 3007 | int dreg = (op >> 16) & 7; |
| 3008 | SHORT2FP(TMR_TEMP1, op); |
| 3009 | subf(m_r[dreg], m_r[TMR_TEMP1], m_r[dreg]); |
| 3010 | } |
| 3011 | |
| 3012 | /*-----------------------------------------------------*/ |
| 3013 | |
| 3014 | void tms3203x_device::subri_reg(UINT32 op) |
| 3015 | { |
| 3016 | UINT32 src = IREG(op & 31); |
| 3017 | int dreg = (op >> 16) & 31; |
| 3018 | UINT32 dst = IREG(dreg); |
| 3019 | SUBI(dreg, src, dst); |
| 3020 | } |
| 3021 | |
| 3022 | void tms3203x_device::subri_dir(UINT32 op) |
| 3023 | { |
| 3024 | UINT32 src = RMEM(DIRECT(op)); |
| 3025 | int dreg = (op >> 16) & 31; |
| 3026 | UINT32 dst = IREG(dreg); |
| 3027 | SUBI(dreg, src, dst); |
| 3028 | } |
| 3029 | |
| 3030 | void tms3203x_device::subri_ind(UINT32 op) |
| 3031 | { |
| 3032 | UINT32 src = RMEM(INDIRECT_D(op, op >> 8)); |
| 3033 | int dreg = (op >> 16) & 31; |
| 3034 | UINT32 dst = IREG(dreg); |
| 3035 | SUBI(dreg, src, dst); |
| 3036 | } |
| 3037 | |
| 3038 | void tms3203x_device::subri_imm(UINT32 op) |
| 3039 | { |
| 3040 | UINT32 src = (INT16)op; |
| 3041 | int dreg = (op >> 16) & 31; |
| 3042 | UINT32 dst = IREG(dreg); |
| 3043 | SUBI(dreg, src, dst); |
| 3044 | } |
| 3045 | |
| 3046 | /*-----------------------------------------------------*/ |
| 3047 | |
| 3048 | #define TSTB(src1, src2) \ |
| 3049 | { \ |
| 3050 | UINT32 _res = (src1) & (src2); \ |
| 3051 | CLR_NZVUF(); \ |
| 3052 | OR_NZ(_res); \ |
| 3053 | } |
| 3054 | |
| 3055 | void tms3203x_device::tstb_reg(UINT32 op) |
| 3056 | { |
| 3057 | UINT32 src = IREG(op & 31); |
| 3058 | UINT32 dst = IREG((op >> 16) & 31); |
| 3059 | TSTB(dst, src); |
| 3060 | } |
| 3061 | |
| 3062 | void tms3203x_device::tstb_dir(UINT32 op) |
| 3063 | { |
| 3064 | UINT32 src = RMEM(DIRECT(op)); |
| 3065 | UINT32 dst = IREG((op >> 16) & 31); |
| 3066 | TSTB(dst, src); |
| 3067 | } |
| 3068 | |
| 3069 | void tms3203x_device::tstb_ind(UINT32 op) |
| 3070 | { |
| 3071 | UINT32 src = RMEM(INDIRECT_D(op, op >> 8)); |
| 3072 | UINT32 dst = IREG((op >> 16) & 31); |
| 3073 | TSTB(dst, src); |
| 3074 | } |
| 3075 | |
| 3076 | void tms3203x_device::tstb_imm(UINT32 op) |
| 3077 | { |
| 3078 | UINT32 src = (UINT16)op; |
| 3079 | UINT32 dst = IREG((op >> 16) & 31); |
| 3080 | TSTB(dst, src); |
| 3081 | } |
| 3082 | |
| 3083 | /*-----------------------------------------------------*/ |
| 3084 | |
| 3085 | #define XOR(dreg, src1, src2) \ |
| 3086 | { \ |
| 3087 | UINT32 _res = (src1) ^ (src2); \ |
| 3088 | IREG(dreg) = _res; \ |
| 3089 | if (dreg < 8) \ |
| 3090 | { \ |
| 3091 | CLR_NZVUF(); \ |
| 3092 | OR_NZ(_res); \ |
| 3093 | } \ |
| 3094 | else if (dreg >= TMR_BK) \ |
| 3095 | update_special(dreg); \ |
| 3096 | } |
| 3097 | |
| 3098 | void tms3203x_device::xor_reg(UINT32 op) |
| 3099 | { |
| 3100 | UINT32 src = IREG(op & 31); |
| 3101 | int dreg = (op >> 16) & 31; |
| 3102 | UINT32 dst = IREG(dreg); |
| 3103 | XOR(dreg, dst, src); |
| 3104 | } |
| 3105 | |
| 3106 | void tms3203x_device::xor_dir(UINT32 op) |
| 3107 | { |
| 3108 | UINT32 src = RMEM(DIRECT(op)); |
| 3109 | int dreg = (op >> 16) & 31; |
| 3110 | UINT32 dst = IREG(dreg); |
| 3111 | XOR(dreg, dst, src); |
| 3112 | } |
| 3113 | |
| 3114 | void tms3203x_device::xor_ind(UINT32 op) |
| 3115 | { |
| 3116 | UINT32 src = RMEM(INDIRECT_D(op, op >> 8)); |
| 3117 | int dreg = (op >> 16) & 31; |
| 3118 | UINT32 dst = IREG(dreg); |
| 3119 | XOR(dreg, dst, src); |
| 3120 | } |
| 3121 | |
| 3122 | void tms3203x_device::xor_imm(UINT32 op) |
| 3123 | { |
| 3124 | UINT32 src = (UINT16)op; |
| 3125 | int dreg = (op >> 16) & 31; |
| 3126 | UINT32 dst = IREG(dreg); |
| 3127 | XOR(dreg, dst, src); |
| 3128 | } |
| 3129 | |
| 3130 | /*-----------------------------------------------------*/ |
| 3131 | |
| 3132 | void tms3203x_device::iack_dir(UINT32 op) |
| 3133 | { |
| 3134 | offs_t addr = DIRECT(op); |
| 3135 | m_iack_cb(addr, ASSERT_LINE); |
| 3136 | RMEM(addr); |
| 3137 | m_iack_cb(addr, CLEAR_LINE); |
| 3138 | } |
| 3139 | |
| 3140 | void tms3203x_device::iack_ind(UINT32 op) |
| 3141 | { |
| 3142 | offs_t addr = INDIRECT_D(op, op >> 8); |
| 3143 | m_iack_cb(addr, ASSERT_LINE); |
| 3144 | RMEM(addr); |
| 3145 | m_iack_cb(addr, CLEAR_LINE); |
| 3146 | } |
| 3147 | |
| 3148 | /*-----------------------------------------------------*/ |
| 3149 | |
| 3150 | void tms3203x_device::addc3_regreg(UINT32 op) |
| 3151 | { |
| 3152 | UINT32 src1 = IREG((op >> 8) & 31); |
| 3153 | UINT32 src2 = IREG(op & 31); |
| 3154 | int dreg = (op >> 16) & 31; |
| 3155 | ADDC(dreg, src1, src2); |
| 3156 | } |
| 3157 | |
| 3158 | void tms3203x_device::addc3_indreg(UINT32 op) |
| 3159 | { |
| 3160 | UINT32 src1 = RMEM(INDIRECT_1(op, op >> 8)); |
| 3161 | UINT32 src2 = IREG(op & 31); |
| 3162 | int dreg = (op >> 16) & 31; |
| 3163 | ADDC(dreg, src1, src2); |
| 3164 | } |
| 3165 | |
| 3166 | void tms3203x_device::addc3_regind(UINT32 op) |
| 3167 | { |
| 3168 | UINT32 src2 = RMEM(INDIRECT_1(op, op)); |
| 3169 | UINT32 src1 = IREG((op >> 8) & 31); |
| 3170 | int dreg = (op >> 16) & 31; |
| 3171 | ADDC(dreg, src1, src2); |
| 3172 | } |
| 3173 | |
| 3174 | void tms3203x_device::addc3_indind(UINT32 op) |
| 3175 | { |
| 3176 | DECLARE_DEF; |
| 3177 | UINT32 src1 = RMEM(INDIRECT_1_DEF(op, op >> 8)); |
| 3178 | UINT32 src2 = RMEM(INDIRECT_1(op, op)); |
| 3179 | int dreg = (op >> 16) & 31; |
| 3180 | UPDATE_DEF(); |
| 3181 | ADDC(dreg, src1, src2); |
| 3182 | } |
| 3183 | |
| 3184 | /*-----------------------------------------------------*/ |
| 3185 | |
| 3186 | void tms3203x_device::addf3_regreg(UINT32 op) |
| 3187 | { |
| 3188 | int sreg1 = (op >> 8) & 7; |
| 3189 | int sreg2 = op & 7; |
| 3190 | int dreg = (op >> 16) & 7; |
| 3191 | addf(m_r[dreg], m_r[sreg1], m_r[sreg2]); |
| 3192 | } |
| 3193 | |
| 3194 | void tms3203x_device::addf3_indreg(UINT32 op) |
| 3195 | { |
| 3196 | UINT32 src1 = RMEM(INDIRECT_1(op, op >> 8)); |
| 3197 | int sreg2 = op & 7; |
| 3198 | int dreg = (op >> 16) & 7; |
| 3199 | LONG2FP(TMR_TEMP1, src1); |
| 3200 | addf(m_r[dreg], m_r[TMR_TEMP1], m_r[sreg2]); |
| 3201 | } |
| 3202 | |
| 3203 | void tms3203x_device::addf3_regind(UINT32 op) |
| 3204 | { |
| 3205 | UINT32 src2 = RMEM(INDIRECT_1(op, op)); |
| 3206 | int sreg1 = (op >> 8) & 7; |
| 3207 | int dreg = (op >> 16) & 7; |
| 3208 | LONG2FP(TMR_TEMP2, src2); |
| 3209 | addf(m_r[dreg], m_r[sreg1], m_r[TMR_TEMP2]); |
| 3210 | } |
| 3211 | |
| 3212 | void tms3203x_device::addf3_indind(UINT32 op) |
| 3213 | { |
| 3214 | DECLARE_DEF; |
| 3215 | UINT32 src1 = RMEM(INDIRECT_1_DEF(op, op >> 8)); |
| 3216 | UINT32 src2 = RMEM(INDIRECT_1(op, op)); |
| 3217 | int dreg = (op >> 16) & 7; |
| 3218 | UPDATE_DEF(); |
| 3219 | LONG2FP(TMR_TEMP1, src1); |
| 3220 | LONG2FP(TMR_TEMP2, src2); |
| 3221 | addf(m_r[dreg], m_r[TMR_TEMP1], m_r[TMR_TEMP2]); |
| 3222 | } |
| 3223 | |
| 3224 | /*-----------------------------------------------------*/ |
| 3225 | |
| 3226 | void tms3203x_device::addi3_regreg(UINT32 op) |
| 3227 | { |
| 3228 | UINT32 src1 = IREG((op >> 8) & 31); |
| 3229 | UINT32 src2 = IREG(op & 31); |
| 3230 | int dreg = (op >> 16) & 31; |
| 3231 | ADDI(dreg, src1, src2); |
| 3232 | } |
| 3233 | |
| 3234 | void tms3203x_device::addi3_indreg(UINT32 op) |
| 3235 | { |
| 3236 | UINT32 src1 = RMEM(INDIRECT_1(op, op >> 8)); |
| 3237 | UINT32 src2 = IREG(op & 31); |
| 3238 | int dreg = (op >> 16) & 31; |
| 3239 | ADDI(dreg, src1, src2); |
| 3240 | } |
| 3241 | |
| 3242 | void tms3203x_device::addi3_regind(UINT32 op) |
| 3243 | { |
| 3244 | // Radikal Bikers confirms via ADDI3 AR3,*AR3++(1),R2 / SUB $0001,R2 sequence |
| 3245 | UINT32 src2 = RMEM(INDIRECT_1(op, op)); |
| 3246 | UINT32 src1 = IREG((op >> 8) & 31); |
| 3247 | int dreg = (op >> 16) & 31; |
| 3248 | ADDI(dreg, src1, src2); |
| 3249 | } |
| 3250 | |
| 3251 | void tms3203x_device::addi3_indind(UINT32 op) |
| 3252 | { |
| 3253 | DECLARE_DEF; |
| 3254 | UINT32 src1 = RMEM(INDIRECT_1_DEF(op, op >> 8)); |
| 3255 | UINT32 src2 = RMEM(INDIRECT_1(op, op)); |
| 3256 | int dreg = (op >> 16) & 31; |
| 3257 | UPDATE_DEF(); |
| 3258 | ADDI(dreg, src1, src2); |
| 3259 | } |
| 3260 | |
| 3261 | /*-----------------------------------------------------*/ |
| 3262 | |
| 3263 | void tms3203x_device::and3_regreg(UINT32 op) |
| 3264 | { |
| 3265 | UINT32 src1 = IREG((op >> 8) & 31); |
| 3266 | UINT32 src2 = IREG(op & 31); |
| 3267 | int dreg = (op >> 16) & 31; |
| 3268 | AND(dreg, src1, src2); |
| 3269 | } |
| 3270 | |
| 3271 | void tms3203x_device::and3_indreg(UINT32 op) |
| 3272 | { |
| 3273 | UINT32 src1 = RMEM(INDIRECT_1(op, op >> 8)); |
| 3274 | UINT32 src2 = IREG(op & 31); |
| 3275 | int dreg = (op >> 16) & 31; |
| 3276 | AND(dreg, src1, src2); |
| 3277 | } |
| 3278 | |
| 3279 | void tms3203x_device::and3_regind(UINT32 op) |
| 3280 | { |
| 3281 | UINT32 src2 = RMEM(INDIRECT_1(op, op)); |
| 3282 | UINT32 src1 = IREG((op >> 8) & 31); |
| 3283 | int dreg = (op >> 16) & 31; |
| 3284 | AND(dreg, src1, src2); |
| 3285 | } |
| 3286 | |
| 3287 | void tms3203x_device::and3_indind(UINT32 op) |
| 3288 | { |
| 3289 | DECLARE_DEF; |
| 3290 | UINT32 src1 = RMEM(INDIRECT_1_DEF(op, op >> 8)); |
| 3291 | UINT32 src2 = RMEM(INDIRECT_1(op, op)); |
| 3292 | int dreg = (op >> 16) & 31; |
| 3293 | UPDATE_DEF(); |
| 3294 | AND(dreg, src1, src2); |
| 3295 | } |
| 3296 | |
| 3297 | /*-----------------------------------------------------*/ |
| 3298 | |
| 3299 | void tms3203x_device::andn3_regreg(UINT32 op) |
| 3300 | { |
| 3301 | UINT32 src1 = IREG((op >> 8) & 31); |
| 3302 | UINT32 src2 = IREG(op & 31); |
| 3303 | int dreg = (op >> 16) & 31; |
| 3304 | ANDN(dreg, src1, src2); |
| 3305 | } |
| 3306 | |
| 3307 | void tms3203x_device::andn3_indreg(UINT32 op) |
| 3308 | { |
| 3309 | UINT32 src1 = RMEM(INDIRECT_1(op, op >> 8)); |
| 3310 | UINT32 src2 = IREG(op & 31); |
| 3311 | int dreg = (op >> 16) & 31; |
| 3312 | ANDN(dreg, src1, src2); |
| 3313 | } |
| 3314 | |
| 3315 | void tms3203x_device::andn3_regind(UINT32 op) |
| 3316 | { |
| 3317 | UINT32 src2 = RMEM(INDIRECT_1(op, op)); |
| 3318 | UINT32 src1 = IREG((op >> 8) & 31); |
| 3319 | int dreg = (op >> 16) & 31; |
| 3320 | ANDN(dreg, src1, src2); |
| 3321 | } |
| 3322 | |
| 3323 | void tms3203x_device::andn3_indind(UINT32 op) |
| 3324 | { |
| 3325 | DECLARE_DEF; |
| 3326 | UINT32 src1 = RMEM(INDIRECT_1_DEF(op, op >> 8)); |
| 3327 | UINT32 src2 = RMEM(INDIRECT_1(op, op)); |
| 3328 | int dreg = (op >> 16) & 31; |
| 3329 | UPDATE_DEF(); |
| 3330 | ANDN(dreg, src1, src2); |
| 3331 | } |
| 3332 | |
| 3333 | /*-----------------------------------------------------*/ |
| 3334 | |
| 3335 | void tms3203x_device::ash3_regreg(UINT32 op) |
| 3336 | { |
| 3337 | UINT32 src1 = IREG((op >> 8) & 31); |
| 3338 | UINT32 src2 = IREG(op & 31); |
| 3339 | int dreg = (op >> 16) & 31; |
| 3340 | ASH(dreg, src1, src2); |
| 3341 | } |
| 3342 | |
| 3343 | void tms3203x_device::ash3_indreg(UINT32 op) |
| 3344 | { |
| 3345 | UINT32 src1 = RMEM(INDIRECT_1(op, op >> 8)); |
| 3346 | UINT32 src2 = IREG(op & 31); |
| 3347 | int dreg = (op >> 16) & 31; |
| 3348 | ASH(dreg, src1, src2); |
| 3349 | } |
| 3350 | |
| 3351 | void tms3203x_device::ash3_regind(UINT32 op) |
| 3352 | { |
| 3353 | UINT32 src2 = RMEM(INDIRECT_1(op, op)); |
| 3354 | UINT32 src1 = IREG((op >> 8) & 31); |
| 3355 | int dreg = (op >> 16) & 31; |
| 3356 | ASH(dreg, src1, src2); |
| 3357 | } |
| 3358 | |
| 3359 | void tms3203x_device::ash3_indind(UINT32 op) |
| 3360 | { |
| 3361 | DECLARE_DEF; |
| 3362 | UINT32 src1 = RMEM(INDIRECT_1_DEF(op, op >> 8)); |
| 3363 | UINT32 src2 = RMEM(INDIRECT_1(op, op)); |
| 3364 | int dreg = (op >> 16) & 31; |
| 3365 | UPDATE_DEF(); |
| 3366 | ASH(dreg, src1, src2); |
| 3367 | } |
| 3368 | |
| 3369 | /*-----------------------------------------------------*/ |
| 3370 | |
| 3371 | void tms3203x_device::cmpf3_regreg(UINT32 op) |
| 3372 | { |
| 3373 | int sreg1 = (op >> 8) & 7; |
| 3374 | int sreg2 = op & 7; |
| 3375 | subf(m_r[TMR_TEMP1], m_r[sreg1], m_r[sreg2]); |
| 3376 | } |
| 3377 | |
| 3378 | void tms3203x_device::cmpf3_indreg(UINT32 op) |
| 3379 | { |
| 3380 | UINT32 src1 = RMEM(INDIRECT_1(op, op >> 8)); |
| 3381 | int sreg2 = op & 7; |
| 3382 | LONG2FP(TMR_TEMP1, src1); |
| 3383 | subf(m_r[TMR_TEMP1], m_r[TMR_TEMP1], m_r[sreg2]); |
| 3384 | } |
| 3385 | |
| 3386 | void tms3203x_device::cmpf3_regind(UINT32 op) |
| 3387 | { |
| 3388 | UINT32 src2 = RMEM(INDIRECT_1(op, op)); |
| 3389 | int sreg1 = (op >> 8) & 7; |
| 3390 | LONG2FP(TMR_TEMP2, src2); |
| 3391 | subf(m_r[TMR_TEMP1], m_r[sreg1], m_r[TMR_TEMP2]); |
| 3392 | } |
| 3393 | |
| 3394 | void tms3203x_device::cmpf3_indind(UINT32 op) |
| 3395 | { |
| 3396 | DECLARE_DEF; |
| 3397 | UINT32 src1 = RMEM(INDIRECT_1_DEF(op, op >> 8)); |
| 3398 | UINT32 src2 = RMEM(INDIRECT_1(op, op)); |
| 3399 | UPDATE_DEF(); |
| 3400 | LONG2FP(TMR_TEMP1, src1); |
| 3401 | LONG2FP(TMR_TEMP2, src2); |
| 3402 | subf(m_r[TMR_TEMP1], m_r[TMR_TEMP1], m_r[TMR_TEMP2]); |
| 3403 | } |
| 3404 | |
| 3405 | /*-----------------------------------------------------*/ |
| 3406 | |
| 3407 | void tms3203x_device::cmpi3_regreg(UINT32 op) |
| 3408 | { |
| 3409 | UINT32 src1 = IREG((op >> 8) & 31); |
| 3410 | UINT32 src2 = IREG(op & 31); |
| 3411 | CMPI(src1, src2); |
| 3412 | } |
| 3413 | |
| 3414 | void tms3203x_device::cmpi3_indreg(UINT32 op) |
| 3415 | { |
| 3416 | UINT32 src1 = RMEM(INDIRECT_1(op, op >> 8)); |
| 3417 | UINT32 src2 = IREG(op & 31); |
| 3418 | CMPI(src1, src2); |
| 3419 | } |
| 3420 | |
| 3421 | void tms3203x_device::cmpi3_regind(UINT32 op) |
| 3422 | { |
| 3423 | UINT32 src2 = RMEM(INDIRECT_1(op, op)); |
| 3424 | UINT32 src1 = IREG((op >> 8) & 31); |
| 3425 | CMPI(src1, src2); |
| 3426 | } |
| 3427 | |
| 3428 | void tms3203x_device::cmpi3_indind(UINT32 op) |
| 3429 | { |
| 3430 | DECLARE_DEF; |
| 3431 | UINT32 src1 = RMEM(INDIRECT_1_DEF(op, op >> 8)); |
| 3432 | UINT32 src2 = RMEM(INDIRECT_1(op, op)); |
| 3433 | UPDATE_DEF(); |
| 3434 | CMPI(src1, src2); |
| 3435 | } |
| 3436 | |
| 3437 | /*-----------------------------------------------------*/ |
| 3438 | |
| 3439 | void tms3203x_device::lsh3_regreg(UINT32 op) |
| 3440 | { |
| 3441 | UINT32 src1 = IREG((op >> 8) & 31); |
| 3442 | UINT32 src2 = IREG(op & 31); |
| 3443 | int dreg = (op >> 16) & 31; |
| 3444 | LSH(dreg, src1, src2); |
| 3445 | } |
| 3446 | |
| 3447 | void tms3203x_device::lsh3_indreg(UINT32 op) |
| 3448 | { |
| 3449 | UINT32 src1 = RMEM(INDIRECT_1(op, op >> 8)); |
| 3450 | UINT32 src2 = IREG(op & 31); |
| 3451 | int dreg = (op >> 16) & 31; |
| 3452 | LSH(dreg, src1, src2); |
| 3453 | } |
| 3454 | |
| 3455 | void tms3203x_device::lsh3_regind(UINT32 op) |
| 3456 | { |
| 3457 | UINT32 src2 = RMEM(INDIRECT_1(op, op)); |
| 3458 | UINT32 src1 = IREG((op >> 8) & 31); |
| 3459 | int dreg = (op >> 16) & 31; |
| 3460 | LSH(dreg, src1, src2); |
| 3461 | } |
| 3462 | |
| 3463 | void tms3203x_device::lsh3_indind(UINT32 op) |
| 3464 | { |
| 3465 | DECLARE_DEF; |
| 3466 | UINT32 src1 = RMEM(INDIRECT_1_DEF(op, op >> 8)); |
| 3467 | UINT32 src2 = RMEM(INDIRECT_1(op, op)); |
| 3468 | int dreg = (op >> 16) & 31; |
| 3469 | UPDATE_DEF(); |
| 3470 | LSH(dreg, src1, src2); |
| 3471 | } |
| 3472 | |
| 3473 | /*-----------------------------------------------------*/ |
| 3474 | |
| 3475 | void tms3203x_device::mpyf3_regreg(UINT32 op) |
| 3476 | { |
| 3477 | int sreg1 = (op >> 8) & 7; |
| 3478 | int sreg2 = op & 7; |
| 3479 | int dreg = (op >> 16) & 7; |
| 3480 | mpyf(m_r[dreg], m_r[sreg1], m_r[sreg2]); |
| 3481 | } |
| 3482 | |
| 3483 | void tms3203x_device::mpyf3_indreg(UINT32 op) |
| 3484 | { |
| 3485 | UINT32 src1 = RMEM(INDIRECT_1(op, op >> 8)); |
| 3486 | int sreg2 = op & 7; |
| 3487 | int dreg = (op >> 16) & 7; |
| 3488 | LONG2FP(TMR_TEMP1, src1); |
| 3489 | mpyf(m_r[dreg], m_r[TMR_TEMP1], m_r[sreg2]); |
| 3490 | } |
| 3491 | |
| 3492 | void tms3203x_device::mpyf3_regind(UINT32 op) |
| 3493 | { |
| 3494 | UINT32 src2 = RMEM(INDIRECT_1(op, op)); |
| 3495 | int sreg1 = (op >> 8) & 7; |
| 3496 | int dreg = (op >> 16) & 7; |
| 3497 | LONG2FP(TMR_TEMP2, src2); |
| 3498 | mpyf(m_r[dreg], m_r[sreg1], m_r[TMR_TEMP2]); |
| 3499 | } |
| 3500 | |
| 3501 | void tms3203x_device::mpyf3_indind(UINT32 op) |
| 3502 | { |
| 3503 | DECLARE_DEF; |
| 3504 | UINT32 src1 = RMEM(INDIRECT_1_DEF(op, op >> 8)); |
| 3505 | UINT32 src2 = RMEM(INDIRECT_1(op, op)); |
| 3506 | int dreg = (op >> 16) & 7; |
| 3507 | UPDATE_DEF(); |
| 3508 | LONG2FP(TMR_TEMP1, src1); |
| 3509 | LONG2FP(TMR_TEMP2, src2); |
| 3510 | mpyf(m_r[dreg], m_r[TMR_TEMP1], m_r[TMR_TEMP2]); |
| 3511 | } |
| 3512 | |
| 3513 | /*-----------------------------------------------------*/ |
| 3514 | |
| 3515 | void tms3203x_device::mpyi3_regreg(UINT32 op) |
| 3516 | { |
| 3517 | UINT32 src1 = IREG((op >> 8) & 31); |
| 3518 | UINT32 src2 = IREG(op & 31); |
| 3519 | int dreg = (op >> 16) & 31; |
| 3520 | MPYI(dreg, src1, src2); |
| 3521 | } |
| 3522 | |
| 3523 | void tms3203x_device::mpyi3_indreg(UINT32 op) |
| 3524 | { |
| 3525 | UINT32 src1 = RMEM(INDIRECT_1(op, op >> 8)); |
| 3526 | UINT32 src2 = IREG(op & 31); |
| 3527 | int dreg = (op >> 16) & 31; |
| 3528 | MPYI(dreg, src1, src2); |
| 3529 | } |
| 3530 | |
| 3531 | void tms3203x_device::mpyi3_regind(UINT32 op) |
| 3532 | { |
| 3533 | UINT32 src2 = RMEM(INDIRECT_1(op, op)); |
| 3534 | UINT32 src1 = IREG((op >> 8) & 31); |
| 3535 | int dreg = (op >> 16) & 31; |
| 3536 | MPYI(dreg, src1, src2); |
| 3537 | } |
| 3538 | |
| 3539 | void tms3203x_device::mpyi3_indind(UINT32 op) |
| 3540 | { |
| 3541 | DECLARE_DEF; |
| 3542 | UINT32 src1 = RMEM(INDIRECT_1_DEF(op, op >> 8)); |
| 3543 | UINT32 src2 = RMEM(INDIRECT_1(op, op)); |
| 3544 | int dreg = (op >> 16) & 31; |
| 3545 | UPDATE_DEF(); |
| 3546 | MPYI(dreg, src1, src2); |
| 3547 | } |
| 3548 | |
| 3549 | /*-----------------------------------------------------*/ |
| 3550 | |
| 3551 | void tms3203x_device::or3_regreg(UINT32 op) |
| 3552 | { |
| 3553 | UINT32 src1 = IREG((op >> 8) & 31); |
| 3554 | UINT32 src2 = IREG(op & 31); |
| 3555 | int dreg = (op >> 16) & 31; |
| 3556 | OR(dreg, src1, src2); |
| 3557 | } |
| 3558 | |
| 3559 | void tms3203x_device::or3_indreg(UINT32 op) |
| 3560 | { |
| 3561 | UINT32 src1 = RMEM(INDIRECT_1(op, op >> 8)); |
| 3562 | UINT32 src2 = IREG(op & 31); |
| 3563 | int dreg = (op >> 16) & 31; |
| 3564 | OR(dreg, src1, src2); |
| 3565 | } |
| 3566 | |
| 3567 | void tms3203x_device::or3_regind(UINT32 op) |
| 3568 | { |
| 3569 | UINT32 src2 = RMEM(INDIRECT_1(op, op)); |
| 3570 | UINT32 src1 = IREG((op >> 8) & 31); |
| 3571 | int dreg = (op >> 16) & 31; |
| 3572 | OR(dreg, src1, src2); |
| 3573 | } |
| 3574 | |
| 3575 | void tms3203x_device::or3_indind(UINT32 op) |
| 3576 | { |
| 3577 | DECLARE_DEF; |
| 3578 | UINT32 src1 = RMEM(INDIRECT_1_DEF(op, op >> 8)); |
| 3579 | UINT32 src2 = RMEM(INDIRECT_1(op, op)); |
| 3580 | int dreg = (op >> 16) & 31; |
| 3581 | UPDATE_DEF(); |
| 3582 | OR(dreg, src1, src2); |
| 3583 | } |
| 3584 | |
| 3585 | /*-----------------------------------------------------*/ |
| 3586 | |
| 3587 | void tms3203x_device::subb3_regreg(UINT32 op) |
| 3588 | { |
| 3589 | UINT32 src1 = IREG((op >> 8) & 31); |
| 3590 | UINT32 src2 = IREG(op & 31); |
| 3591 | int dreg = (op >> 16) & 31; |
| 3592 | SUBB(dreg, src1, src2); |
| 3593 | } |
| 3594 | |
| 3595 | void tms3203x_device::subb3_indreg(UINT32 op) |
| 3596 | { |
| 3597 | UINT32 src1 = RMEM(INDIRECT_1(op, op >> 8)); |
| 3598 | UINT32 src2 = IREG(op & 31); |
| 3599 | int dreg = (op >> 16) & 31; |
| 3600 | SUBB(dreg, src1, src2); |
| 3601 | } |
| 3602 | |
| 3603 | void tms3203x_device::subb3_regind(UINT32 op) |
| 3604 | { |
| 3605 | UINT32 src2 = RMEM(INDIRECT_1(op, op)); |
| 3606 | UINT32 src1 = IREG((op >> 8) & 31); |
| 3607 | int dreg = (op >> 16) & 31; |
| 3608 | SUBB(dreg, src1, src2); |
| 3609 | } |
| 3610 | |
| 3611 | void tms3203x_device::subb3_indind(UINT32 op) |
| 3612 | { |
| 3613 | DECLARE_DEF; |
| 3614 | UINT32 src1 = RMEM(INDIRECT_1_DEF(op, op >> 8)); |
| 3615 | UINT32 src2 = RMEM(INDIRECT_1(op, op)); |
| 3616 | int dreg = (op >> 16) & 31; |
| 3617 | UPDATE_DEF(); |
| 3618 | SUBB(dreg, src1, src2); |
| 3619 | } |
| 3620 | |
| 3621 | /*-----------------------------------------------------*/ |
| 3622 | |
| 3623 | void tms3203x_device::subf3_regreg(UINT32 op) |
| 3624 | { |
| 3625 | int sreg1 = (op >> 8) & 7; |
| 3626 | int sreg2 = op & 7; |
| 3627 | int dreg = (op >> 16) & 7; |
| 3628 | subf(m_r[dreg], m_r[sreg1], m_r[sreg2]); |
| 3629 | } |
| 3630 | |
| 3631 | void tms3203x_device::subf3_indreg(UINT32 op) |
| 3632 | { |
| 3633 | UINT32 src1 = RMEM(INDIRECT_1(op, op >> 8)); |
| 3634 | int sreg2 = op & 7; |
| 3635 | int dreg = (op >> 16) & 7; |
| 3636 | LONG2FP(TMR_TEMP1, src1); |
| 3637 | subf(m_r[dreg], m_r[TMR_TEMP1], m_r[sreg2]); |
| 3638 | } |
| 3639 | |
| 3640 | void tms3203x_device::subf3_regind(UINT32 op) |
| 3641 | { |
| 3642 | UINT32 src2 = RMEM(INDIRECT_1(op, op)); |
| 3643 | int sreg1 = (op >> 8) & 7; |
| 3644 | int dreg = (op >> 16) & 7; |
| 3645 | LONG2FP(TMR_TEMP2, src2); |
| 3646 | subf(m_r[dreg], m_r[sreg1], m_r[TMR_TEMP2]); |
| 3647 | } |
| 3648 | |
| 3649 | void tms3203x_device::subf3_indind(UINT32 op) |
| 3650 | { |
| 3651 | DECLARE_DEF; |
| 3652 | UINT32 src1 = RMEM(INDIRECT_1_DEF(op, op >> 8)); |
| 3653 | UINT32 src2 = RMEM(INDIRECT_1(op, op)); |
| 3654 | int dreg = (op >> 16) & 7; |
| 3655 | UPDATE_DEF(); |
| 3656 | LONG2FP(TMR_TEMP1, src1); |
| 3657 | LONG2FP(TMR_TEMP2, src2); |
| 3658 | subf(m_r[dreg], m_r[TMR_TEMP1], m_r[TMR_TEMP2]); |
| 3659 | } |
| 3660 | |
| 3661 | /*-----------------------------------------------------*/ |
| 3662 | |
| 3663 | void tms3203x_device::subi3_regreg(UINT32 op) |
| 3664 | { |
| 3665 | UINT32 src1 = IREG((op >> 8) & 31); |
| 3666 | UINT32 src2 = IREG(op & 31); |
| 3667 | int dreg = (op >> 16) & 31; |
| 3668 | SUBI(dreg, src1, src2); |
| 3669 | } |
| 3670 | |
| 3671 | void tms3203x_device::subi3_indreg(UINT32 op) |
| 3672 | { |
| 3673 | UINT32 src1 = RMEM(INDIRECT_1(op, op >> 8)); |
| 3674 | UINT32 src2 = IREG(op & 31); |
| 3675 | int dreg = (op >> 16) & 31; |
| 3676 | SUBI(dreg, src1, src2); |
| 3677 | } |
| 3678 | |
| 3679 | void tms3203x_device::subi3_regind(UINT32 op) |
| 3680 | { |
| 3681 | UINT32 src2 = RMEM(INDIRECT_1(op, op)); |
| 3682 | UINT32 src1 = IREG((op >> 8) & 31); |
| 3683 | int dreg = (op >> 16) & 31; |
| 3684 | SUBI(dreg, src1, src2); |
| 3685 | } |
| 3686 | |
| 3687 | void tms3203x_device::subi3_indind(UINT32 op) |
| 3688 | { |
| 3689 | DECLARE_DEF; |
| 3690 | UINT32 src1 = RMEM(INDIRECT_1_DEF(op, op >> 8)); |
| 3691 | UINT32 src2 = RMEM(INDIRECT_1(op, op)); |
| 3692 | int dreg = (op >> 16) & 31; |
| 3693 | UPDATE_DEF(); |
| 3694 | SUBI(dreg, src1, src2); |
| 3695 | } |
| 3696 | |
| 3697 | /*-----------------------------------------------------*/ |
| 3698 | |
| 3699 | void tms3203x_device::tstb3_regreg(UINT32 op) |
| 3700 | { |
| 3701 | UINT32 src1 = IREG((op >> 8) & 31); |
| 3702 | UINT32 src2 = IREG(op & 31); |
| 3703 | TSTB(src1, src2); |
| 3704 | } |
| 3705 | |
| 3706 | void tms3203x_device::tstb3_indreg(UINT32 op) |
| 3707 | { |
| 3708 | UINT32 src1 = RMEM(INDIRECT_1(op, op >> 8)); |
| 3709 | UINT32 src2 = IREG(op & 31); |
| 3710 | TSTB(src1, src2); |
| 3711 | } |
| 3712 | |
| 3713 | void tms3203x_device::tstb3_regind(UINT32 op) |
| 3714 | { |
| 3715 | UINT32 src2 = RMEM(INDIRECT_1(op, op)); |
| 3716 | UINT32 src1 = IREG((op >> 8) & 31); |
| 3717 | TSTB(src1, src2); |
| 3718 | } |
| 3719 | |
| 3720 | void tms3203x_device::tstb3_indind(UINT32 op) |
| 3721 | { |
| 3722 | DECLARE_DEF; |
| 3723 | UINT32 src1 = RMEM(INDIRECT_1_DEF(op, op >> 8)); |
| 3724 | UINT32 src2 = RMEM(INDIRECT_1(op, op)); |
| 3725 | UPDATE_DEF(); |
| 3726 | TSTB(src1, src2); |
| 3727 | } |
| 3728 | |
| 3729 | /*-----------------------------------------------------*/ |
| 3730 | |
| 3731 | void tms3203x_device::xor3_regreg(UINT32 op) |
| 3732 | { |
| 3733 | UINT32 src1 = IREG((op >> 8) & 31); |
| 3734 | UINT32 src2 = IREG(op & 31); |
| 3735 | int dreg = (op >> 16) & 31; |
| 3736 | XOR(dreg, src1, src2); |
| 3737 | } |
| 3738 | |
| 3739 | void tms3203x_device::xor3_indreg(UINT32 op) |
| 3740 | { |
| 3741 | UINT32 src1 = RMEM(INDIRECT_1(op, op >> 8)); |
| 3742 | UINT32 src2 = IREG(op & 31); |
| 3743 | int dreg = (op >> 16) & 31; |
| 3744 | XOR(dreg, src1, src2); |
| 3745 | } |
| 3746 | |
| 3747 | void tms3203x_device::xor3_regind(UINT32 op) |
| 3748 | { |
| 3749 | UINT32 src2 = RMEM(INDIRECT_1(op, op)); |
| 3750 | UINT32 src1 = IREG((op >> 8) & 31); |
| 3751 | int dreg = (op >> 16) & 31; |
| 3752 | XOR(dreg, src1, src2); |
| 3753 | } |
| 3754 | |
| 3755 | void tms3203x_device::xor3_indind(UINT32 op) |
| 3756 | { |
| 3757 | DECLARE_DEF; |
| 3758 | UINT32 src1 = RMEM(INDIRECT_1_DEF(op, op >> 8)); |
| 3759 | UINT32 src2 = RMEM(INDIRECT_1(op, op)); |
| 3760 | int dreg = (op >> 16) & 31; |
| 3761 | UPDATE_DEF(); |
| 3762 | XOR(dreg, src1, src2); |
| 3763 | } |
| 3764 | |
| 3765 | /*-----------------------------------------------------*/ |
| 3766 | |
| 3767 | void tms3203x_device::ldfu_reg(UINT32 op) |
| 3768 | { |
| 3769 | m_r[(op >> 16) & 7] = m_r[op & 7]; |
| 3770 | } |
| 3771 | |
| 3772 | void tms3203x_device::ldfu_dir(UINT32 op) |
| 3773 | { |
| 3774 | UINT32 res = RMEM(DIRECT(op)); |
| 3775 | int dreg = (op >> 16) & 7; |
| 3776 | LONG2FP(dreg, res); |
| 3777 | } |
| 3778 | |
| 3779 | void tms3203x_device::ldfu_ind(UINT32 op) |
| 3780 | { |
| 3781 | UINT32 res = RMEM(INDIRECT_D(op, op >> 8)); |
| 3782 | int dreg = (op >> 16) & 7; |
| 3783 | LONG2FP(dreg, res); |
| 3784 | } |
| 3785 | |
| 3786 | void tms3203x_device::ldfu_imm(UINT32 op) |
| 3787 | { |
| 3788 | int dreg = (op >> 16) & 7; |
| 3789 | SHORT2FP(dreg, op); |
| 3790 | } |
| 3791 | |
| 3792 | /*-----------------------------------------------------*/ |
| 3793 | |
| 3794 | void tms3203x_device::ldflo_reg(UINT32 op) |
| 3795 | { |
| 3796 | if (CONDITION_LO()) |
| 3797 | m_r[(op >> 16) & 7] = m_r[op & 7]; |
| 3798 | } |
| 3799 | |
| 3800 | void tms3203x_device::ldflo_dir(UINT32 op) |
| 3801 | { |
| 3802 | if (CONDITION_LO()) |
| 3803 | { |
| 3804 | UINT32 res = RMEM(DIRECT(op)); |
| 3805 | int dreg = (op >> 16) & 7; |
| 3806 | LONG2FP(dreg, res); |
| 3807 | } |
| 3808 | } |
| 3809 | |
| 3810 | void tms3203x_device::ldflo_ind(UINT32 op) |
| 3811 | { |
| 3812 | if (CONDITION_LO()) |
| 3813 | { |
| 3814 | UINT32 res = RMEM(INDIRECT_D(op, op >> 8)); |
| 3815 | int dreg = (op >> 16) & 7; |
| 3816 | LONG2FP(dreg, res); |
| 3817 | } |
| 3818 | else |
| 3819 | INDIRECT_D(op, op >> 8); |
| 3820 | } |
| 3821 | |
| 3822 | void tms3203x_device::ldflo_imm(UINT32 op) |
| 3823 | { |
| 3824 | if (CONDITION_LO()) |
| 3825 | { |
| 3826 | int dreg = (op >> 16) & 7; |
| 3827 | SHORT2FP(dreg, op); |
| 3828 | } |
| 3829 | } |
| 3830 | |
| 3831 | /*-----------------------------------------------------*/ |
| 3832 | |
| 3833 | void tms3203x_device::ldfls_reg(UINT32 op) |
| 3834 | { |
| 3835 | if (CONDITION_LS()) |
| 3836 | m_r[(op >> 16) & 7] = m_r[op & 7]; |
| 3837 | } |
| 3838 | |
| 3839 | void tms3203x_device::ldfls_dir(UINT32 op) |
| 3840 | { |
| 3841 | if (CONDITION_LS()) |
| 3842 | { |
| 3843 | UINT32 res = RMEM(DIRECT(op)); |
| 3844 | int dreg = (op >> 16) & 7; |
| 3845 | LONG2FP(dreg, res); |
| 3846 | } |
| 3847 | } |
| 3848 | |
| 3849 | void tms3203x_device::ldfls_ind(UINT32 op) |
| 3850 | { |
| 3851 | if (CONDITION_LS()) |
| 3852 | { |
| 3853 | UINT32 res = RMEM(INDIRECT_D(op, op >> 8)); |
| 3854 | int dreg = (op >> 16) & 7; |
| 3855 | LONG2FP(dreg, res); |
| 3856 | } |
| 3857 | else |
| 3858 | INDIRECT_D(op, op >> 8); |
| 3859 | } |
| 3860 | |
| 3861 | void tms3203x_device::ldfls_imm(UINT32 op) |
| 3862 | { |
| 3863 | if (CONDITION_LS()) |
| 3864 | { |
| 3865 | int dreg = (op >> 16) & 7; |
| 3866 | SHORT2FP(dreg, op); |
| 3867 | } |
| 3868 | } |
| 3869 | |
| 3870 | /*-----------------------------------------------------*/ |
| 3871 | |
| 3872 | void tms3203x_device::ldfhi_reg(UINT32 op) |
| 3873 | { |
| 3874 | if (CONDITION_HI()) |
| 3875 | m_r[(op >> 16) & 7] = m_r[op & 7]; |
| 3876 | } |
| 3877 | |
| 3878 | void tms3203x_device::ldfhi_dir(UINT32 op) |
| 3879 | { |
| 3880 | if (CONDITION_HI()) |
| 3881 | { |
| 3882 | UINT32 res = RMEM(DIRECT(op)); |
| 3883 | int dreg = (op >> 16) & 7; |
| 3884 | LONG2FP(dreg, res); |
| 3885 | } |
| 3886 | } |
| 3887 | |
| 3888 | void tms3203x_device::ldfhi_ind(UINT32 op) |
| 3889 | { |
| 3890 | if (CONDITION_HI()) |
| 3891 | { |
| 3892 | UINT32 res = RMEM(INDIRECT_D(op, op >> 8)); |
| 3893 | int dreg = (op >> 16) & 7; |
| 3894 | LONG2FP(dreg, res); |
| 3895 | } |
| 3896 | else |
| 3897 | INDIRECT_D(op, op >> 8); |
| 3898 | } |
| 3899 | |
| 3900 | void tms3203x_device::ldfhi_imm(UINT32 op) |
| 3901 | { |
| 3902 | if (CONDITION_HI()) |
| 3903 | { |
| 3904 | int dreg = (op >> 16) & 7; |
| 3905 | SHORT2FP(dreg, op); |
| 3906 | } |
| 3907 | } |
| 3908 | |
| 3909 | /*-----------------------------------------------------*/ |
| 3910 | |
| 3911 | void tms3203x_device::ldfhs_reg(UINT32 op) |
| 3912 | { |
| 3913 | if (CONDITION_HS()) |
| 3914 | m_r[(op >> 16) & 7] = m_r[op & 7]; |
| 3915 | } |
| 3916 | |
| 3917 | void tms3203x_device::ldfhs_dir(UINT32 op) |
| 3918 | { |
| 3919 | if (CONDITION_HS()) |
| 3920 | { |
| 3921 | UINT32 res = RMEM(DIRECT(op)); |
| 3922 | int dreg = (op >> 16) & 7; |
| 3923 | LONG2FP(dreg, res); |
| 3924 | } |
| 3925 | } |
| 3926 | |
| 3927 | void tms3203x_device::ldfhs_ind(UINT32 op) |
| 3928 | { |
| 3929 | if (CONDITION_HS()) |
| 3930 | { |
| 3931 | UINT32 res = RMEM(INDIRECT_D(op, op >> 8)); |
| 3932 | int dreg = (op >> 16) & 7; |
| 3933 | LONG2FP(dreg, res); |
| 3934 | } |
| 3935 | else |
| 3936 | INDIRECT_D(op, op >> 8); |
| 3937 | } |
| 3938 | |
| 3939 | void tms3203x_device::ldfhs_imm(UINT32 op) |
| 3940 | { |
| 3941 | if (CONDITION_HS()) |
| 3942 | { |
| 3943 | int dreg = (op >> 16) & 7; |
| 3944 | SHORT2FP(dreg, op); |
| 3945 | } |
| 3946 | } |
| 3947 | |
| 3948 | /*-----------------------------------------------------*/ |
| 3949 | |
| 3950 | void tms3203x_device::ldfeq_reg(UINT32 op) |
| 3951 | { |
| 3952 | if (CONDITION_EQ()) |
| 3953 | m_r[(op >> 16) & 7] = m_r[op & 7]; |
| 3954 | } |
| 3955 | |
| 3956 | void tms3203x_device::ldfeq_dir(UINT32 op) |
| 3957 | { |
| 3958 | if (CONDITION_EQ()) |
| 3959 | { |
| 3960 | UINT32 res = RMEM(DIRECT(op)); |
| 3961 | int dreg = (op >> 16) & 7; |
| 3962 | LONG2FP(dreg, res); |
| 3963 | } |
| 3964 | } |
| 3965 | |
| 3966 | void tms3203x_device::ldfeq_ind(UINT32 op) |
| 3967 | { |
| 3968 | if (CONDITION_EQ()) |
| 3969 | { |
| 3970 | UINT32 res = RMEM(INDIRECT_D(op, op >> 8)); |
| 3971 | int dreg = (op >> 16) & 7; |
| 3972 | LONG2FP(dreg, res); |
| 3973 | } |
| 3974 | else |
| 3975 | INDIRECT_D(op, op >> 8); |
| 3976 | } |
| 3977 | |
| 3978 | void tms3203x_device::ldfeq_imm(UINT32 op) |
| 3979 | { |
| 3980 | if (CONDITION_EQ()) |
| 3981 | { |
| 3982 | int dreg = (op >> 16) & 7; |
| 3983 | SHORT2FP(dreg, op); |
| 3984 | } |
| 3985 | } |
| 3986 | |
| 3987 | /*-----------------------------------------------------*/ |
| 3988 | |
| 3989 | void tms3203x_device::ldfne_reg(UINT32 op) |
| 3990 | { |
| 3991 | if (CONDITION_NE()) |
| 3992 | m_r[(op >> 16) & 7] = m_r[op & 7]; |
| 3993 | } |
| 3994 | |
| 3995 | void tms3203x_device::ldfne_dir(UINT32 op) |
| 3996 | { |
| 3997 | if (CONDITION_NE()) |
| 3998 | { |
| 3999 | UINT32 res = RMEM(DIRECT(op)); |
| 4000 | int dreg = (op >> 16) & 7; |
| 4001 | LONG2FP(dreg, res); |
| 4002 | } |
| 4003 | } |
| 4004 | |
| 4005 | void tms3203x_device::ldfne_ind(UINT32 op) |
| 4006 | { |
| 4007 | if (CONDITION_NE()) |
| 4008 | { |
| 4009 | UINT32 res = RMEM(INDIRECT_D(op, op >> 8)); |
| 4010 | int dreg = (op >> 16) & 7; |
| 4011 | LONG2FP(dreg, res); |
| 4012 | } |
| 4013 | else |
| 4014 | INDIRECT_D(op, op >> 8); |
| 4015 | } |
| 4016 | |
| 4017 | void tms3203x_device::ldfne_imm(UINT32 op) |
| 4018 | { |
| 4019 | if (CONDITION_NE()) |
| 4020 | { |
| 4021 | int dreg = (op >> 16) & 7; |
| 4022 | SHORT2FP(dreg, op); |
| 4023 | } |
| 4024 | } |
| 4025 | |
| 4026 | /*-----------------------------------------------------*/ |
| 4027 | |
| 4028 | void tms3203x_device::ldflt_reg(UINT32 op) |
| 4029 | { |
| 4030 | if (CONDITION_LT()) |
| 4031 | m_r[(op >> 16) & 7] = m_r[op & 7]; |
| 4032 | } |
| 4033 | |
| 4034 | void tms3203x_device::ldflt_dir(UINT32 op) |
| 4035 | { |
| 4036 | if (CONDITION_LT()) |
| 4037 | { |
| 4038 | UINT32 res = RMEM(DIRECT(op)); |
| 4039 | int dreg = (op >> 16) & 7; |
| 4040 | LONG2FP(dreg, res); |
| 4041 | } |
| 4042 | } |
| 4043 | |
| 4044 | void tms3203x_device::ldflt_ind(UINT32 op) |
| 4045 | { |
| 4046 | if (CONDITION_LT()) |
| 4047 | { |
| 4048 | UINT32 res = RMEM(INDIRECT_D(op, op >> 8)); |
| 4049 | int dreg = (op >> 16) & 7; |
| 4050 | LONG2FP(dreg, res); |
| 4051 | } |
| 4052 | else |
| 4053 | INDIRECT_D(op, op >> 8); |
| 4054 | } |
| 4055 | |
| 4056 | void tms3203x_device::ldflt_imm(UINT32 op) |
| 4057 | { |
| 4058 | if (CONDITION_LT()) |
| 4059 | { |
| 4060 | int dreg = (op >> 16) & 7; |
| 4061 | SHORT2FP(dreg, op); |
| 4062 | } |
| 4063 | } |
| 4064 | |
| 4065 | /*-----------------------------------------------------*/ |
| 4066 | |
| 4067 | void tms3203x_device::ldfle_reg(UINT32 op) |
| 4068 | { |
| 4069 | if (CONDITION_LE()) |
| 4070 | m_r[(op >> 16) & 7] = m_r[op & 7]; |
| 4071 | } |
| 4072 | |
| 4073 | void tms3203x_device::ldfle_dir(UINT32 op) |
| 4074 | { |
| 4075 | if (CONDITION_LE()) |
| 4076 | { |
| 4077 | UINT32 res = RMEM(DIRECT(op)); |
| 4078 | int dreg = (op >> 16) & 7; |
| 4079 | LONG2FP(dreg, res); |
| 4080 | } |
| 4081 | } |
| 4082 | |
| 4083 | void tms3203x_device::ldfle_ind(UINT32 op) |
| 4084 | { |
| 4085 | if (CONDITION_LE()) |
| 4086 | { |
| 4087 | UINT32 res = RMEM(INDIRECT_D(op, op >> 8)); |
| 4088 | int dreg = (op >> 16) & 7; |
| 4089 | LONG2FP(dreg, res); |
| 4090 | } |
| 4091 | else |
| 4092 | INDIRECT_D(op, op >> 8); |
| 4093 | } |
| 4094 | |
| 4095 | void tms3203x_device::ldfle_imm(UINT32 op) |
| 4096 | { |
| 4097 | if (CONDITION_LE()) |
| 4098 | { |
| 4099 | int dreg = (op >> 16) & 7; |
| 4100 | SHORT2FP(dreg, op); |
| 4101 | } |
| 4102 | } |
| 4103 | |
| 4104 | /*-----------------------------------------------------*/ |
| 4105 | |
| 4106 | void tms3203x_device::ldfgt_reg(UINT32 op) |
| 4107 | { |
| 4108 | if (CONDITION_GT()) |
| 4109 | m_r[(op >> 16) & 7] = m_r[op & 7]; |
| 4110 | } |
| 4111 | |
| 4112 | void tms3203x_device::ldfgt_dir(UINT32 op) |
| 4113 | { |
| 4114 | if (CONDITION_GT()) |
| 4115 | { |
| 4116 | UINT32 res = RMEM(DIRECT(op)); |
| 4117 | int dreg = (op >> 16) & 7; |
| 4118 | LONG2FP(dreg, res); |
| 4119 | } |
| 4120 | } |
| 4121 | |
| 4122 | void tms3203x_device::ldfgt_ind(UINT32 op) |
| 4123 | { |
| 4124 | if (CONDITION_GT()) |
| 4125 | { |
| 4126 | UINT32 res = RMEM(INDIRECT_D(op, op >> 8)); |
| 4127 | int dreg = (op >> 16) & 7; |
| 4128 | LONG2FP(dreg, res); |
| 4129 | } |
| 4130 | else |
| 4131 | INDIRECT_D(op, op >> 8); |
| 4132 | } |
| 4133 | |
| 4134 | void tms3203x_device::ldfgt_imm(UINT32 op) |
| 4135 | { |
| 4136 | if (CONDITION_GT()) |
| 4137 | { |
| 4138 | int dreg = (op >> 16) & 7; |
| 4139 | SHORT2FP(dreg, op); |
| 4140 | } |
| 4141 | } |
| 4142 | |
| 4143 | /*-----------------------------------------------------*/ |
| 4144 | |
| 4145 | void tms3203x_device::ldfge_reg(UINT32 op) |
| 4146 | { |
| 4147 | if (CONDITION_GE()) |
| 4148 | m_r[(op >> 16) & 7] = m_r[op & 7]; |
| 4149 | } |
| 4150 | |
| 4151 | void tms3203x_device::ldfge_dir(UINT32 op) |
| 4152 | { |
| 4153 | if (CONDITION_GE()) |
| 4154 | { |
| 4155 | UINT32 res = RMEM(DIRECT(op)); |
| 4156 | int dreg = (op >> 16) & 7; |
| 4157 | LONG2FP(dreg, res); |
| 4158 | } |
| 4159 | } |
| 4160 | |
| 4161 | void tms3203x_device::ldfge_ind(UINT32 op) |
| 4162 | { |
| 4163 | if (CONDITION_GE()) |
| 4164 | { |
| 4165 | UINT32 res = RMEM(INDIRECT_D(op, op >> 8)); |
| 4166 | int dreg = (op >> 16) & 7; |
| 4167 | LONG2FP(dreg, res); |
| 4168 | } |
| 4169 | else |
| 4170 | INDIRECT_D(op, op >> 8); |
| 4171 | } |
| 4172 | |
| 4173 | void tms3203x_device::ldfge_imm(UINT32 op) |
| 4174 | { |
| 4175 | if (CONDITION_GE()) |
| 4176 | { |
| 4177 | int dreg = (op >> 16) & 7; |
| 4178 | SHORT2FP(dreg, op); |
| 4179 | } |
| 4180 | } |
| 4181 | |
| 4182 | /*-----------------------------------------------------*/ |
| 4183 | |
| 4184 | void tms3203x_device::ldfnv_reg(UINT32 op) |
| 4185 | { |
| 4186 | if (CONDITION_NV()) |
| 4187 | m_r[(op >> 16) & 7] = m_r[op & 7]; |
| 4188 | } |
| 4189 | |
| 4190 | void tms3203x_device::ldfnv_dir(UINT32 op) |
| 4191 | { |
| 4192 | if (CONDITION_NV()) |
| 4193 | { |
| 4194 | UINT32 res = RMEM(DIRECT(op)); |
| 4195 | int dreg = (op >> 16) & 7; |
| 4196 | LONG2FP(dreg, res); |
| 4197 | } |
| 4198 | } |
| 4199 | |
| 4200 | void tms3203x_device::ldfnv_ind(UINT32 op) |
| 4201 | { |
| 4202 | if (CONDITION_NV()) |
| 4203 | { |
| 4204 | UINT32 res = RMEM(INDIRECT_D(op, op >> 8)); |
| 4205 | int dreg = (op >> 16) & 7; |
| 4206 | LONG2FP(dreg, res); |
| 4207 | } |
| 4208 | else |
| 4209 | INDIRECT_D(op, op >> 8); |
| 4210 | } |
| 4211 | |
| 4212 | void tms3203x_device::ldfnv_imm(UINT32 op) |
| 4213 | { |
| 4214 | if (CONDITION_NV()) |
| 4215 | { |
| 4216 | int dreg = (op >> 16) & 7; |
| 4217 | SHORT2FP(dreg, op); |
| 4218 | } |
| 4219 | } |
| 4220 | |
| 4221 | /*-----------------------------------------------------*/ |
| 4222 | |
| 4223 | void tms3203x_device::ldfv_reg(UINT32 op) |
| 4224 | { |
| 4225 | if (CONDITION_V()) |
| 4226 | m_r[(op >> 16) & 7] = m_r[op & 7]; |
| 4227 | } |
| 4228 | |
| 4229 | void tms3203x_device::ldfv_dir(UINT32 op) |
| 4230 | { |
| 4231 | if (CONDITION_V()) |
| 4232 | { |
| 4233 | UINT32 res = RMEM(DIRECT(op)); |
| 4234 | int dreg = (op >> 16) & 7; |
| 4235 | LONG2FP(dreg, res); |
| 4236 | } |
| 4237 | } |
| 4238 | |
| 4239 | void tms3203x_device::ldfv_ind(UINT32 op) |
| 4240 | { |
| 4241 | if (CONDITION_V()) |
| 4242 | { |
| 4243 | UINT32 res = RMEM(INDIRECT_D(op, op >> 8)); |
| 4244 | int dreg = (op >> 16) & 7; |
| 4245 | LONG2FP(dreg, res); |
| 4246 | } |
| 4247 | else |
| 4248 | INDIRECT_D(op, op >> 8); |
| 4249 | } |
| 4250 | |
| 4251 | void tms3203x_device::ldfv_imm(UINT32 op) |
| 4252 | { |
| 4253 | if (CONDITION_V()) |
| 4254 | { |
| 4255 | int dreg = (op >> 16) & 7; |
| 4256 | SHORT2FP(dreg, op); |
| 4257 | } |
| 4258 | } |
| 4259 | |
| 4260 | /*-----------------------------------------------------*/ |
| 4261 | |
| 4262 | void tms3203x_device::ldfnuf_reg(UINT32 op) |
| 4263 | { |
| 4264 | if (CONDITION_NUF()) |
| 4265 | m_r[(op >> 16) & 7] = m_r[op & 7]; |
| 4266 | } |
| 4267 | |
| 4268 | void tms3203x_device::ldfnuf_dir(UINT32 op) |
| 4269 | { |
| 4270 | if (CONDITION_NUF()) |
| 4271 | { |
| 4272 | UINT32 res = RMEM(DIRECT(op)); |
| 4273 | int dreg = (op >> 16) & 7; |
| 4274 | LONG2FP(dreg, res); |
| 4275 | } |
| 4276 | } |
| 4277 | |
| 4278 | void tms3203x_device::ldfnuf_ind(UINT32 op) |
| 4279 | { |
| 4280 | if (CONDITION_NUF()) |
| 4281 | { |
| 4282 | UINT32 res = RMEM(INDIRECT_D(op, op >> 8)); |
| 4283 | int dreg = (op >> 16) & 7; |
| 4284 | LONG2FP(dreg, res); |
| 4285 | } |
| 4286 | else |
| 4287 | INDIRECT_D(op, op >> 8); |
| 4288 | } |
| 4289 | |
| 4290 | void tms3203x_device::ldfnuf_imm(UINT32 op) |
| 4291 | { |
| 4292 | if (CONDITION_NUF()) |
| 4293 | { |
| 4294 | int dreg = (op >> 16) & 7; |
| 4295 | SHORT2FP(dreg, op); |
| 4296 | } |
| 4297 | } |
| 4298 | |
| 4299 | /*-----------------------------------------------------*/ |
| 4300 | |
| 4301 | void tms3203x_device::ldfuf_reg(UINT32 op) |
| 4302 | { |
| 4303 | if (CONDITION_UF()) |
| 4304 | m_r[(op >> 16) & 7] = m_r[op & 7]; |
| 4305 | } |
| 4306 | |
| 4307 | void tms3203x_device::ldfuf_dir(UINT32 op) |
| 4308 | { |
| 4309 | if (CONDITION_UF()) |
| 4310 | { |
| 4311 | UINT32 res = RMEM(DIRECT(op)); |
| 4312 | int dreg = (op >> 16) & 7; |
| 4313 | LONG2FP(dreg, res); |
| 4314 | } |
| 4315 | } |
| 4316 | |
| 4317 | void tms3203x_device::ldfuf_ind(UINT32 op) |
| 4318 | { |
| 4319 | if (CONDITION_UF()) |
| 4320 | { |
| 4321 | UINT32 res = RMEM(INDIRECT_D(op, op >> 8)); |
| 4322 | int dreg = (op >> 16) & 7; |
| 4323 | LONG2FP(dreg, res); |
| 4324 | } |
| 4325 | else |
| 4326 | INDIRECT_D(op, op >> 8); |
| 4327 | } |
| 4328 | |
| 4329 | void tms3203x_device::ldfuf_imm(UINT32 op) |
| 4330 | { |
| 4331 | if (CONDITION_UF()) |
| 4332 | { |
| 4333 | int dreg = (op >> 16) & 7; |
| 4334 | SHORT2FP(dreg, op); |
| 4335 | } |
| 4336 | } |
| 4337 | |
| 4338 | /*-----------------------------------------------------*/ |
| 4339 | |
| 4340 | void tms3203x_device::ldfnlv_reg(UINT32 op) |
| 4341 | { |
| 4342 | if (CONDITION_NLV()) |
| 4343 | m_r[(op >> 16) & 7] = m_r[op & 7]; |
| 4344 | } |
| 4345 | |
| 4346 | void tms3203x_device::ldfnlv_dir(UINT32 op) |
| 4347 | { |
| 4348 | if (CONDITION_NLV()) |
| 4349 | { |
| 4350 | UINT32 res = RMEM(DIRECT(op)); |
| 4351 | int dreg = (op >> 16) & 7; |
| 4352 | LONG2FP(dreg, res); |
| 4353 | } |
| 4354 | } |
| 4355 | |
| 4356 | void tms3203x_device::ldfnlv_ind(UINT32 op) |
| 4357 | { |
| 4358 | if (CONDITION_NLV()) |
| 4359 | { |
| 4360 | UINT32 res = RMEM(INDIRECT_D(op, op >> 8)); |
| 4361 | int dreg = (op >> 16) & 7; |
| 4362 | LONG2FP(dreg, res); |
| 4363 | } |
| 4364 | else |
| 4365 | INDIRECT_D(op, op >> 8); |
| 4366 | } |
| 4367 | |
| 4368 | void tms3203x_device::ldfnlv_imm(UINT32 op) |
| 4369 | { |
| 4370 | if (CONDITION_NLV()) |
| 4371 | { |
| 4372 | int dreg = (op >> 16) & 7; |
| 4373 | SHORT2FP(dreg, op); |
| 4374 | } |
| 4375 | } |
| 4376 | |
| 4377 | /*-----------------------------------------------------*/ |
| 4378 | |
| 4379 | void tms3203x_device::ldflv_reg(UINT32 op) |
| 4380 | { |
| 4381 | if (CONDITION_LV()) |
| 4382 | m_r[(op >> 16) & 7] = m_r[op & 7]; |
| 4383 | } |
| 4384 | |
| 4385 | void tms3203x_device::ldflv_dir(UINT32 op) |
| 4386 | { |
| 4387 | if (CONDITION_LV()) |
| 4388 | { |
| 4389 | UINT32 res = RMEM(DIRECT(op)); |
| 4390 | int dreg = (op >> 16) & 7; |
| 4391 | LONG2FP(dreg, res); |
| 4392 | } |
| 4393 | } |
| 4394 | |
| 4395 | void tms3203x_device::ldflv_ind(UINT32 op) |
| 4396 | { |
| 4397 | if (CONDITION_LV()) |
| 4398 | { |
| 4399 | UINT32 res = RMEM(INDIRECT_D(op, op >> 8)); |
| 4400 | int dreg = (op >> 16) & 7; |
| 4401 | LONG2FP(dreg, res); |
| 4402 | } |
| 4403 | else |
| 4404 | INDIRECT_D(op, op >> 8); |
| 4405 | } |
| 4406 | |
| 4407 | void tms3203x_device::ldflv_imm(UINT32 op) |
| 4408 | { |
| 4409 | if (CONDITION_LV()) |
| 4410 | { |
| 4411 | int dreg = (op >> 16) & 7; |
| 4412 | SHORT2FP(dreg, op); |
| 4413 | } |
| 4414 | } |
| 4415 | |
| 4416 | /*-----------------------------------------------------*/ |
| 4417 | |
| 4418 | void tms3203x_device::ldfnluf_reg(UINT32 op) |
| 4419 | { |
| 4420 | if (CONDITION_NLUF()) |
| 4421 | m_r[(op >> 16) & 7] = m_r[op & 7]; |
| 4422 | } |
| 4423 | |
| 4424 | void tms3203x_device::ldfnluf_dir(UINT32 op) |
| 4425 | { |
| 4426 | if (CONDITION_NLUF()) |
| 4427 | { |
| 4428 | UINT32 res = RMEM(DIRECT(op)); |
| 4429 | int dreg = (op >> 16) & 7; |
| 4430 | LONG2FP(dreg, res); |
| 4431 | } |
| 4432 | } |
| 4433 | |
| 4434 | void tms3203x_device::ldfnluf_ind(UINT32 op) |
| 4435 | { |
| 4436 | if (CONDITION_NLUF()) |
| 4437 | { |
| 4438 | UINT32 res = RMEM(INDIRECT_D(op, op >> 8)); |
| 4439 | int dreg = (op >> 16) & 7; |
| 4440 | LONG2FP(dreg, res); |
| 4441 | } |
| 4442 | else |
| 4443 | INDIRECT_D(op, op >> 8); |
| 4444 | } |
| 4445 | |
| 4446 | void tms3203x_device::ldfnluf_imm(UINT32 op) |
| 4447 | { |
| 4448 | if (CONDITION_NLUF()) |
| 4449 | { |
| 4450 | int dreg = (op >> 16) & 7; |
| 4451 | SHORT2FP(dreg, op); |
| 4452 | } |
| 4453 | } |
| 4454 | |
| 4455 | /*-----------------------------------------------------*/ |
| 4456 | |
| 4457 | void tms3203x_device::ldfluf_reg(UINT32 op) |
| 4458 | { |
| 4459 | if (CONDITION_LUF()) |
| 4460 | m_r[(op >> 16) & 7] = m_r[op & 7]; |
| 4461 | } |
| 4462 | |
| 4463 | void tms3203x_device::ldfluf_dir(UINT32 op) |
| 4464 | { |
| 4465 | if (CONDITION_LUF()) |
| 4466 | { |
| 4467 | UINT32 res = RMEM(DIRECT(op)); |
| 4468 | int dreg = (op >> 16) & 7; |
| 4469 | LONG2FP(dreg, res); |
| 4470 | } |
| 4471 | } |
| 4472 | |
| 4473 | void tms3203x_device::ldfluf_ind(UINT32 op) |
| 4474 | { |
| 4475 | if (CONDITION_LUF()) |
| 4476 | { |
| 4477 | UINT32 res = RMEM(INDIRECT_D(op, op >> 8)); |
| 4478 | int dreg = (op >> 16) & 7; |
| 4479 | LONG2FP(dreg, res); |
| 4480 | } |
| 4481 | else |
| 4482 | INDIRECT_D(op, op >> 8); |
| 4483 | } |
| 4484 | |
| 4485 | void tms3203x_device::ldfluf_imm(UINT32 op) |
| 4486 | { |
| 4487 | if (CONDITION_LUF()) |
| 4488 | { |
| 4489 | int dreg = (op >> 16) & 7; |
| 4490 | SHORT2FP(dreg, op); |
| 4491 | } |
| 4492 | } |
| 4493 | |
| 4494 | /*-----------------------------------------------------*/ |
| 4495 | |
| 4496 | void tms3203x_device::ldfzuf_reg(UINT32 op) |
| 4497 | { |
| 4498 | if (CONDITION_ZUF()) |
| 4499 | m_r[(op >> 16) & 7] = m_r[op & 7]; |
| 4500 | } |
| 4501 | |
| 4502 | void tms3203x_device::ldfzuf_dir(UINT32 op) |
| 4503 | { |
| 4504 | if (CONDITION_ZUF()) |
| 4505 | { |
| 4506 | UINT32 res = RMEM(DIRECT(op)); |
| 4507 | int dreg = (op >> 16) & 7; |
| 4508 | LONG2FP(dreg, res); |
| 4509 | } |
| 4510 | } |
| 4511 | |
| 4512 | void tms3203x_device::ldfzuf_ind(UINT32 op) |
| 4513 | { |
| 4514 | if (CONDITION_ZUF()) |
| 4515 | { |
| 4516 | UINT32 res = RMEM(INDIRECT_D(op, op >> 8)); |
| 4517 | int dreg = (op >> 16) & 7; |
| 4518 | LONG2FP(dreg, res); |
| 4519 | } |
| 4520 | else |
| 4521 | INDIRECT_D(op, op >> 8); |
| 4522 | } |
| 4523 | |
| 4524 | void tms3203x_device::ldfzuf_imm(UINT32 op) |
| 4525 | { |
| 4526 | if (CONDITION_ZUF()) |
| 4527 | { |
| 4528 | int dreg = (op >> 16) & 7; |
| 4529 | SHORT2FP(dreg, op); |
| 4530 | } |
| 4531 | } |
| 4532 | |
| 4533 | /*-----------------------------------------------------*/ |
| 4534 | |
| 4535 | void tms3203x_device::ldiu_reg(UINT32 op) |
| 4536 | { |
| 4537 | int dreg = (op >> 16) & 31; |
| 4538 | IREG(dreg) = IREG(op & 31); |
| 4539 | if (dreg >= TMR_BK) |
| 4540 | update_special(dreg); |
| 4541 | } |
| 4542 | |
| 4543 | void tms3203x_device::ldiu_dir(UINT32 op) |
| 4544 | { |
| 4545 | int dreg = (op >> 16) & 31; |
| 4546 | IREG(dreg) = RMEM(DIRECT(op)); |
| 4547 | if (dreg >= TMR_BK) |
| 4548 | update_special(dreg); |
| 4549 | } |
| 4550 | |
| 4551 | void tms3203x_device::ldiu_ind(UINT32 op) |
| 4552 | { |
| 4553 | int dreg = (op >> 16) & 31; |
| 4554 | IREG(dreg) = RMEM(INDIRECT_D(op, op >> 8)); |
| 4555 | if (dreg >= TMR_BK) |
| 4556 | update_special(dreg); |
| 4557 | } |
| 4558 | |
| 4559 | void tms3203x_device::ldiu_imm(UINT32 op) |
| 4560 | { |
| 4561 | int dreg = (op >> 16) & 31; |
| 4562 | IREG(dreg) = (INT16)op; |
| 4563 | if (dreg >= TMR_BK) |
| 4564 | update_special(dreg); |
| 4565 | } |
| 4566 | |
| 4567 | /*-----------------------------------------------------*/ |
| 4568 | |
| 4569 | void tms3203x_device::ldilo_reg(UINT32 op) |
| 4570 | { |
| 4571 | if (CONDITION_LO()) |
| 4572 | { |
| 4573 | int dreg = (op >> 16) & 31; |
| 4574 | IREG(dreg) = IREG(op & 31); |
| 4575 | if (dreg >= TMR_BK) |
| 4576 | update_special(dreg); |
| 4577 | } |
| 4578 | } |
| 4579 | |
| 4580 | void tms3203x_device::ldilo_dir(UINT32 op) |
| 4581 | { |
| 4582 | UINT32 val = RMEM(DIRECT(op)); |
| 4583 | if (CONDITION_LO()) |
| 4584 | { |
| 4585 | int dreg = (op >> 16) & 31; |
| 4586 | IREG(dreg) = val; |
| 4587 | if (dreg >= TMR_BK) |
| 4588 | update_special(dreg); |
| 4589 | } |
| 4590 | } |
| 4591 | |
| 4592 | void tms3203x_device::ldilo_ind(UINT32 op) |
| 4593 | { |
| 4594 | UINT32 val = RMEM(INDIRECT_D(op, op >> 8)); |
| 4595 | if (CONDITION_LO()) |
| 4596 | { |
| 4597 | int dreg = (op >> 16) & 31; |
| 4598 | IREG(dreg) = val; |
| 4599 | if (dreg >= TMR_BK) |
| 4600 | update_special(dreg); |
| 4601 | } |
| 4602 | } |
| 4603 | |
| 4604 | void tms3203x_device::ldilo_imm(UINT32 op) |
| 4605 | { |
| 4606 | if (CONDITION_LO()) |
| 4607 | { |
| 4608 | int dreg = (op >> 16) & 31; |
| 4609 | IREG(dreg) = (INT16)op; |
| 4610 | if (dreg >= TMR_BK) |
| 4611 | update_special(dreg); |
| 4612 | } |
| 4613 | } |
| 4614 | |
| 4615 | /*-----------------------------------------------------*/ |
| 4616 | |
| 4617 | void tms3203x_device::ldils_reg(UINT32 op) |
| 4618 | { |
| 4619 | if (CONDITION_LS()) |
| 4620 | { |
| 4621 | int dreg = (op >> 16) & 31; |
| 4622 | IREG(dreg) = IREG(op & 31); |
| 4623 | if (dreg >= TMR_BK) |
| 4624 | update_special(dreg); |
| 4625 | } |
| 4626 | } |
| 4627 | |
| 4628 | void tms3203x_device::ldils_dir(UINT32 op) |
| 4629 | { |
| 4630 | UINT32 val = RMEM(DIRECT(op)); |
| 4631 | if (CONDITION_LS()) |
| 4632 | { |
| 4633 | int dreg = (op >> 16) & 31; |
| 4634 | IREG(dreg) = val; |
| 4635 | if (dreg >= TMR_BK) |
| 4636 | update_special(dreg); |
| 4637 | } |
| 4638 | } |
| 4639 | |
| 4640 | void tms3203x_device::ldils_ind(UINT32 op) |
| 4641 | { |
| 4642 | UINT32 val = RMEM(INDIRECT_D(op, op >> 8)); |
| 4643 | if (CONDITION_LS()) |
| 4644 | { |
| 4645 | int dreg = (op >> 16) & 31; |
| 4646 | IREG(dreg) = val; |
| 4647 | if (dreg >= TMR_BK) |
| 4648 | update_special(dreg); |
| 4649 | } |
| 4650 | } |
| 4651 | |
| 4652 | void tms3203x_device::ldils_imm(UINT32 op) |
| 4653 | { |
| 4654 | if (CONDITION_LS()) |
| 4655 | { |
| 4656 | int dreg = (op >> 16) & 31; |
| 4657 | IREG(dreg) = (INT16)op; |
| 4658 | if (dreg >= TMR_BK) |
| 4659 | update_special(dreg); |
| 4660 | } |
| 4661 | } |
| 4662 | |
| 4663 | /*-----------------------------------------------------*/ |
| 4664 | |
| 4665 | void tms3203x_device::ldihi_reg(UINT32 op) |
| 4666 | { |
| 4667 | if (CONDITION_HI()) |
| 4668 | { |
| 4669 | int dreg = (op >> 16) & 31; |
| 4670 | IREG(dreg) = IREG(op & 31); |
| 4671 | if (dreg >= TMR_BK) |
| 4672 | update_special(dreg); |
| 4673 | } |
| 4674 | } |
| 4675 | |
| 4676 | void tms3203x_device::ldihi_dir(UINT32 op) |
| 4677 | { |
| 4678 | UINT32 val = RMEM(DIRECT(op)); |
| 4679 | if (CONDITION_HI()) |
| 4680 | { |
| 4681 | int dreg = (op >> 16) & 31; |
| 4682 | IREG(dreg) = val; |
| 4683 | if (dreg >= TMR_BK) |
| 4684 | update_special(dreg); |
| 4685 | } |
| 4686 | } |
| 4687 | |
| 4688 | void tms3203x_device::ldihi_ind(UINT32 op) |
| 4689 | { |
| 4690 | UINT32 val = RMEM(INDIRECT_D(op, op >> 8)); |
| 4691 | if (CONDITION_HI()) |
| 4692 | { |
| 4693 | int dreg = (op >> 16) & 31; |
| 4694 | IREG(dreg) = val; |
| 4695 | if (dreg >= TMR_BK) |
| 4696 | update_special(dreg); |
| 4697 | } |
| 4698 | } |
| 4699 | |
| 4700 | void tms3203x_device::ldihi_imm(UINT32 op) |
| 4701 | { |
| 4702 | if (CONDITION_HI()) |
| 4703 | { |
| 4704 | int dreg = (op >> 16) & 31; |
| 4705 | IREG(dreg) = (INT16)op; |
| 4706 | if (dreg >= TMR_BK) |
| 4707 | update_special(dreg); |
| 4708 | } |
| 4709 | } |
| 4710 | |
| 4711 | /*-----------------------------------------------------*/ |
| 4712 | |
| 4713 | void tms3203x_device::ldihs_reg(UINT32 op) |
| 4714 | { |
| 4715 | if (CONDITION_HS()) |
| 4716 | { |
| 4717 | int dreg = (op >> 16) & 31; |
| 4718 | IREG(dreg) = IREG(op & 31); |
| 4719 | if (dreg >= TMR_BK) |
| 4720 | update_special(dreg); |
| 4721 | } |
| 4722 | } |
| 4723 | |
| 4724 | void tms3203x_device::ldihs_dir(UINT32 op) |
| 4725 | { |
| 4726 | UINT32 val = RMEM(DIRECT(op)); |
| 4727 | if (CONDITION_HS()) |
| 4728 | { |
| 4729 | int dreg = (op >> 16) & 31; |
| 4730 | IREG(dreg) = val; |
| 4731 | if (dreg >= TMR_BK) |
| 4732 | update_special(dreg); |
| 4733 | } |
| 4734 | } |
| 4735 | |
| 4736 | void tms3203x_device::ldihs_ind(UINT32 op) |
| 4737 | { |
| 4738 | UINT32 val = RMEM(INDIRECT_D(op, op >> 8)); |
| 4739 | if (CONDITION_HS()) |
| 4740 | { |
| 4741 | int dreg = (op >> 16) & 31; |
| 4742 | IREG(dreg) = val; |
| 4743 | if (dreg >= TMR_BK) |
| 4744 | update_special(dreg); |
| 4745 | } |
| 4746 | } |
| 4747 | |
| 4748 | void tms3203x_device::ldihs_imm(UINT32 op) |
| 4749 | { |
| 4750 | if (CONDITION_HS()) |
| 4751 | { |
| 4752 | int dreg = (op >> 16) & 31; |
| 4753 | IREG(dreg) = (INT16)op; |
| 4754 | if (dreg >= TMR_BK) |
| 4755 | update_special(dreg); |
| 4756 | } |
| 4757 | } |
| 4758 | |
| 4759 | /*-----------------------------------------------------*/ |
| 4760 | |
| 4761 | void tms3203x_device::ldieq_reg(UINT32 op) |
| 4762 | { |
| 4763 | if (CONDITION_EQ()) |
| 4764 | { |
| 4765 | int dreg = (op >> 16) & 31; |
| 4766 | IREG(dreg) = IREG(op & 31); |
| 4767 | if (dreg >= TMR_BK) |
| 4768 | update_special(dreg); |
| 4769 | } |
| 4770 | } |
| 4771 | |
| 4772 | void tms3203x_device::ldieq_dir(UINT32 op) |
| 4773 | { |
| 4774 | UINT32 val = RMEM(DIRECT(op)); |
| 4775 | if (CONDITION_EQ()) |
| 4776 | { |
| 4777 | int dreg = (op >> 16) & 31; |
| 4778 | IREG(dreg) = val; |
| 4779 | if (dreg >= TMR_BK) |
| 4780 | update_special(dreg); |
| 4781 | } |
| 4782 | } |
| 4783 | |
| 4784 | void tms3203x_device::ldieq_ind(UINT32 op) |
| 4785 | { |
| 4786 | UINT32 val = RMEM(INDIRECT_D(op, op >> 8)); |
| 4787 | if (CONDITION_EQ()) |
| 4788 | { |
| 4789 | int dreg = (op >> 16) & 31; |
| 4790 | IREG(dreg) = val; |
| 4791 | if (dreg >= TMR_BK) |
| 4792 | update_special(dreg); |
| 4793 | } |
| 4794 | } |
| 4795 | |
| 4796 | void tms3203x_device::ldieq_imm(UINT32 op) |
| 4797 | { |
| 4798 | if (CONDITION_EQ()) |
| 4799 | { |
| 4800 | int dreg = (op >> 16) & 31; |
| 4801 | IREG(dreg) = (INT16)op; |
| 4802 | if (dreg >= TMR_BK) |
| 4803 | update_special(dreg); |
| 4804 | } |
| 4805 | } |
| 4806 | |
| 4807 | /*-----------------------------------------------------*/ |
| 4808 | |
| 4809 | void tms3203x_device::ldine_reg(UINT32 op) |
| 4810 | { |
| 4811 | if (CONDITION_NE()) |
| 4812 | { |
| 4813 | int dreg = (op >> 16) & 31; |
| 4814 | IREG(dreg) = IREG(op & 31); |
| 4815 | if (dreg >= TMR_BK) |
| 4816 | update_special(dreg); |
| 4817 | } |
| 4818 | } |
| 4819 | |
| 4820 | void tms3203x_device::ldine_dir(UINT32 op) |
| 4821 | { |
| 4822 | UINT32 val = RMEM(DIRECT(op)); |
| 4823 | if (CONDITION_NE()) |
| 4824 | { |
| 4825 | int dreg = (op >> 16) & 31; |
| 4826 | IREG(dreg) = val; |
| 4827 | if (dreg >= TMR_BK) |
| 4828 | update_special(dreg); |
| 4829 | } |
| 4830 | } |
| 4831 | |
| 4832 | void tms3203x_device::ldine_ind(UINT32 op) |
| 4833 | { |
| 4834 | UINT32 val = RMEM(INDIRECT_D(op, op >> 8)); |
| 4835 | if (CONDITION_NE()) |
| 4836 | { |
| 4837 | int dreg = (op >> 16) & 31; |
| 4838 | IREG(dreg) = val; |
| 4839 | if (dreg >= TMR_BK) |
| 4840 | update_special(dreg); |
| 4841 | } |
| 4842 | } |
| 4843 | |
| 4844 | void tms3203x_device::ldine_imm(UINT32 op) |
| 4845 | { |
| 4846 | if (CONDITION_NE()) |
| 4847 | { |
| 4848 | int dreg = (op >> 16) & 31; |
| 4849 | IREG(dreg) = (INT16)op; |
| 4850 | if (dreg >= TMR_BK) |
| 4851 | update_special(dreg); |
| 4852 | } |
| 4853 | } |
| 4854 | |
| 4855 | /*-----------------------------------------------------*/ |
| 4856 | |
| 4857 | void tms3203x_device::ldilt_reg(UINT32 op) |
| 4858 | { |
| 4859 | if (CONDITION_LT()) |
| 4860 | { |
| 4861 | int dreg = (op >> 16) & 31; |
| 4862 | IREG(dreg) = IREG(op & 31); |
| 4863 | if (dreg >= TMR_BK) |
| 4864 | update_special(dreg); |
| 4865 | } |
| 4866 | } |
| 4867 | |
| 4868 | void tms3203x_device::ldilt_dir(UINT32 op) |
| 4869 | { |
| 4870 | UINT32 val = RMEM(DIRECT(op)); |
| 4871 | if (CONDITION_LT()) |
| 4872 | { |
| 4873 | int dreg = (op >> 16) & 31; |
| 4874 | IREG(dreg) = val; |
| 4875 | if (dreg >= TMR_BK) |
| 4876 | update_special(dreg); |
| 4877 | } |
| 4878 | } |
| 4879 | |
| 4880 | void tms3203x_device::ldilt_ind(UINT32 op) |
| 4881 | { |
| 4882 | UINT32 val = RMEM(INDIRECT_D(op, op >> 8)); |
| 4883 | if (CONDITION_LT()) |
| 4884 | { |
| 4885 | int dreg = (op >> 16) & 31; |
| 4886 | IREG(dreg) = val; |
| 4887 | if (dreg >= TMR_BK) |
| 4888 | update_special(dreg); |
| 4889 | } |
| 4890 | } |
| 4891 | |
| 4892 | void tms3203x_device::ldilt_imm(UINT32 op) |
| 4893 | { |
| 4894 | if (CONDITION_LT()) |
| 4895 | { |
| 4896 | int dreg = (op >> 16) & 31; |
| 4897 | IREG(dreg) = (INT16)op; |
| 4898 | if (dreg >= TMR_BK) |
| 4899 | update_special(dreg); |
| 4900 | } |
| 4901 | } |
| 4902 | |
| 4903 | /*-----------------------------------------------------*/ |
| 4904 | |
| 4905 | void tms3203x_device::ldile_reg(UINT32 op) |
| 4906 | { |
| 4907 | if (CONDITION_LE()) |
| 4908 | { |
| 4909 | int dreg = (op >> 16) & 31; |
| 4910 | IREG(dreg) = IREG(op & 31); |
| 4911 | if (dreg >= TMR_BK) |
| 4912 | update_special(dreg); |
| 4913 | } |
| 4914 | } |
| 4915 | |
| 4916 | void tms3203x_device::ldile_dir(UINT32 op) |
| 4917 | { |
| 4918 | UINT32 val = RMEM(DIRECT(op)); |
| 4919 | if (CONDITION_LE()) |
| 4920 | { |
| 4921 | int dreg = (op >> 16) & 31; |
| 4922 | IREG(dreg) = val; |
| 4923 | if (dreg >= TMR_BK) |
| 4924 | update_special(dreg); |
| 4925 | } |
| 4926 | } |
| 4927 | |
| 4928 | void tms3203x_device::ldile_ind(UINT32 op) |
| 4929 | { |
| 4930 | UINT32 val = RMEM(INDIRECT_D(op, op >> 8)); |
| 4931 | if (CONDITION_LE()) |
| 4932 | { |
| 4933 | int dreg = (op >> 16) & 31; |
| 4934 | IREG(dreg) = val; |
| 4935 | if (dreg >= TMR_BK) |
| 4936 | update_special(dreg); |
| 4937 | } |
| 4938 | } |
| 4939 | |
| 4940 | void tms3203x_device::ldile_imm(UINT32 op) |
| 4941 | { |
| 4942 | if (CONDITION_LE()) |
| 4943 | { |
| 4944 | int dreg = (op >> 16) & 31; |
| 4945 | IREG(dreg) = (INT16)op; |
| 4946 | if (dreg >= TMR_BK) |
| 4947 | update_special(dreg); |
| 4948 | } |
| 4949 | } |
| 4950 | |
| 4951 | /*-----------------------------------------------------*/ |
| 4952 | |
| 4953 | void tms3203x_device::ldigt_reg(UINT32 op) |
| 4954 | { |
| 4955 | if (CONDITION_GT()) |
| 4956 | { |
| 4957 | int dreg = (op >> 16) & 31; |
| 4958 | IREG(dreg) = IREG(op & 31); |
| 4959 | if (dreg >= TMR_BK) |
| 4960 | update_special(dreg); |
| 4961 | } |
| 4962 | } |
| 4963 | |
| 4964 | void tms3203x_device::ldigt_dir(UINT32 op) |
| 4965 | { |
| 4966 | UINT32 val = RMEM(DIRECT(op)); |
| 4967 | if (CONDITION_GT()) |
| 4968 | { |
| 4969 | int dreg = (op >> 16) & 31; |
| 4970 | IREG(dreg) = val; |
| 4971 | if (dreg >= TMR_BK) |
| 4972 | update_special(dreg); |
| 4973 | } |
| 4974 | } |
| 4975 | |
| 4976 | void tms3203x_device::ldigt_ind(UINT32 op) |
| 4977 | { |
| 4978 | UINT32 val = RMEM(INDIRECT_D(op, op >> 8)); |
| 4979 | if (CONDITION_GT()) |
| 4980 | { |
| 4981 | int dreg = (op >> 16) & 31; |
| 4982 | IREG(dreg) = val; |
| 4983 | if (dreg >= TMR_BK) |
| 4984 | update_special(dreg); |
| 4985 | } |
| 4986 | } |
| 4987 | |
| 4988 | void tms3203x_device::ldigt_imm(UINT32 op) |
| 4989 | { |
| 4990 | if (CONDITION_GT()) |
| 4991 | { |
| 4992 | int dreg = (op >> 16) & 31; |
| 4993 | IREG(dreg) = (INT16)op; |
| 4994 | if (dreg >= TMR_BK) |
| 4995 | update_special(dreg); |
| 4996 | } |
| 4997 | } |
| 4998 | |
| 4999 | /*-----------------------------------------------------*/ |
| 5000 | |
| 5001 | void tms3203x_device::ldige_reg(UINT32 op) |
| 5002 | { |
| 5003 | if (CONDITION_GE()) |
| 5004 | { |
| 5005 | int dreg = (op >> 16) & 31; |
| 5006 | IREG(dreg) = IREG(op & 31); |
| 5007 | if (dreg >= TMR_BK) |
| 5008 | update_special(dreg); |
| 5009 | } |
| 5010 | } |
| 5011 | |
| 5012 | void tms3203x_device::ldige_dir(UINT32 op) |
| 5013 | { |
| 5014 | UINT32 val = RMEM(DIRECT(op)); |
| 5015 | if (CONDITION_GE()) |
| 5016 | { |
| 5017 | int dreg = (op >> 16) & 31; |
| 5018 | IREG(dreg) = val; |
| 5019 | if (dreg >= TMR_BK) |
| 5020 | update_special(dreg); |
| 5021 | } |
| 5022 | } |
| 5023 | |
| 5024 | void tms3203x_device::ldige_ind(UINT32 op) |
| 5025 | { |
| 5026 | UINT32 val = RMEM(INDIRECT_D(op, op >> 8)); |
| 5027 | if (CONDITION_GE()) |
| 5028 | { |
| 5029 | int dreg = (op >> 16) & 31; |
| 5030 | IREG(dreg) = val; |
| 5031 | if (dreg >= TMR_BK) |
| 5032 | update_special(dreg); |
| 5033 | } |
| 5034 | } |
| 5035 | |
| 5036 | void tms3203x_device::ldige_imm(UINT32 op) |
| 5037 | { |
| 5038 | if (CONDITION_GE()) |
| 5039 | { |
| 5040 | int dreg = (op >> 16) & 31; |
| 5041 | IREG(dreg) = (INT16)op; |
| 5042 | if (dreg >= TMR_BK) |
| 5043 | update_special(dreg); |
| 5044 | } |
| 5045 | } |
| 5046 | |
| 5047 | /*-----------------------------------------------------*/ |
| 5048 | |
| 5049 | void tms3203x_device::ldinv_reg(UINT32 op) |
| 5050 | { |
| 5051 | if (CONDITION_NV()) |
| 5052 | { |
| 5053 | int dreg = (op >> 16) & 31; |
| 5054 | IREG(dreg) = IREG(op & 31); |
| 5055 | if (dreg >= TMR_BK) |
| 5056 | update_special(dreg); |
| 5057 | } |
| 5058 | } |
| 5059 | |
| 5060 | void tms3203x_device::ldinv_dir(UINT32 op) |
| 5061 | { |
| 5062 | UINT32 val = RMEM(DIRECT(op)); |
| 5063 | if (CONDITION_NV()) |
| 5064 | { |
| 5065 | int dreg = (op >> 16) & 31; |
| 5066 | IREG(dreg) = val; |
| 5067 | if (dreg >= TMR_BK) |
| 5068 | update_special(dreg); |
| 5069 | } |
| 5070 | } |
| 5071 | |
| 5072 | void tms3203x_device::ldinv_ind(UINT32 op) |
| 5073 | { |
| 5074 | UINT32 val = RMEM(INDIRECT_D(op, op >> 8)); |
| 5075 | if (CONDITION_NV()) |
| 5076 | { |
| 5077 | int dreg = (op >> 16) & 31; |
| 5078 | IREG(dreg) = val; |
| 5079 | if (dreg >= TMR_BK) |
| 5080 | update_special(dreg); |
| 5081 | } |
| 5082 | } |
| 5083 | |
| 5084 | void tms3203x_device::ldinv_imm(UINT32 op) |
| 5085 | { |
| 5086 | if (CONDITION_NV()) |
| 5087 | { |
| 5088 | int dreg = (op >> 16) & 31; |
| 5089 | IREG(dreg) = (INT16)op; |
| 5090 | if (dreg >= TMR_BK) |
| 5091 | update_special(dreg); |
| 5092 | } |
| 5093 | } |
| 5094 | |
| 5095 | /*-----------------------------------------------------*/ |
| 5096 | |
| 5097 | void tms3203x_device::ldiuf_reg(UINT32 op) |
| 5098 | { |
| 5099 | if (CONDITION_UF()) |
| 5100 | { |
| 5101 | int dreg = (op >> 16) & 31; |
| 5102 | IREG(dreg) = IREG(op & 31); |
| 5103 | if (dreg >= TMR_BK) |
| 5104 | update_special(dreg); |
| 5105 | } |
| 5106 | } |
| 5107 | |
| 5108 | void tms3203x_device::ldiuf_dir(UINT32 op) |
| 5109 | { |
| 5110 | UINT32 val = RMEM(DIRECT(op)); |
| 5111 | if (CONDITION_UF()) |
| 5112 | { |
| 5113 | int dreg = (op >> 16) & 31; |
| 5114 | IREG(dreg) = val; |
| 5115 | if (dreg >= TMR_BK) |
| 5116 | update_special(dreg); |
| 5117 | } |
| 5118 | } |
| 5119 | |
| 5120 | void tms3203x_device::ldiuf_ind(UINT32 op) |
| 5121 | { |
| 5122 | UINT32 val = RMEM(INDIRECT_D(op, op >> 8)); |
| 5123 | if (CONDITION_UF()) |
| 5124 | { |
| 5125 | int dreg = (op >> 16) & 31; |
| 5126 | IREG(dreg) = val; |
| 5127 | if (dreg >= TMR_BK) |
| 5128 | update_special(dreg); |
| 5129 | } |
| 5130 | } |
| 5131 | |
| 5132 | void tms3203x_device::ldiuf_imm(UINT32 op) |
| 5133 | { |
| 5134 | if (CONDITION_UF()) |
| 5135 | { |
| 5136 | int dreg = (op >> 16) & 31; |
| 5137 | IREG(dreg) = (INT16)op; |
| 5138 | if (dreg >= TMR_BK) |
| 5139 | update_special(dreg); |
| 5140 | } |
| 5141 | } |
| 5142 | |
| 5143 | /*-----------------------------------------------------*/ |
| 5144 | |
| 5145 | void tms3203x_device::ldinuf_reg(UINT32 op) |
| 5146 | { |
| 5147 | if (CONDITION_NUF()) |
| 5148 | { |
| 5149 | int dreg = (op >> 16) & 31; |
| 5150 | IREG(dreg) = IREG(op & 31); |
| 5151 | if (dreg >= TMR_BK) |
| 5152 | update_special(dreg); |
| 5153 | } |
| 5154 | } |
| 5155 | |
| 5156 | void tms3203x_device::ldinuf_dir(UINT32 op) |
| 5157 | { |
| 5158 | UINT32 val = RMEM(DIRECT(op)); |
| 5159 | if (CONDITION_NUF()) |
| 5160 | { |
| 5161 | int dreg = (op >> 16) & 31; |
| 5162 | IREG(dreg) = val; |
| 5163 | if (dreg >= TMR_BK) |
| 5164 | update_special(dreg); |
| 5165 | } |
| 5166 | } |
| 5167 | |
| 5168 | void tms3203x_device::ldinuf_ind(UINT32 op) |
| 5169 | { |
| 5170 | UINT32 val = RMEM(INDIRECT_D(op, op >> 8)); |
| 5171 | if (CONDITION_NUF()) |
| 5172 | { |
| 5173 | int dreg = (op >> 16) & 31; |
| 5174 | IREG(dreg) = val; |
| 5175 | if (dreg >= TMR_BK) |
| 5176 | update_special(dreg); |
| 5177 | } |
| 5178 | } |
| 5179 | |
| 5180 | void tms3203x_device::ldinuf_imm(UINT32 op) |
| 5181 | { |
| 5182 | if (CONDITION_NUF()) |
| 5183 | { |
| 5184 | int dreg = (op >> 16) & 31; |
| 5185 | IREG(dreg) = (INT16)op; |
| 5186 | if (dreg >= TMR_BK) |
| 5187 | update_special(dreg); |
| 5188 | } |
| 5189 | } |
| 5190 | |
| 5191 | /*-----------------------------------------------------*/ |
| 5192 | |
| 5193 | void tms3203x_device::ldiv_reg(UINT32 op) |
| 5194 | { |
| 5195 | if (CONDITION_V()) |
| 5196 | { |
| 5197 | int dreg = (op >> 16) & 31; |
| 5198 | IREG(dreg) = IREG(op & 31); |
| 5199 | if (dreg >= TMR_BK) |
| 5200 | update_special(dreg); |
| 5201 | } |
| 5202 | } |
| 5203 | |
| 5204 | void tms3203x_device::ldiv_dir(UINT32 op) |
| 5205 | { |
| 5206 | UINT32 val = RMEM(DIRECT(op)); |
| 5207 | if (CONDITION_V()) |
| 5208 | { |
| 5209 | int dreg = (op >> 16) & 31; |
| 5210 | IREG(dreg) = val; |
| 5211 | if (dreg >= TMR_BK) |
| 5212 | update_special(dreg); |
| 5213 | } |
| 5214 | } |
| 5215 | |
| 5216 | void tms3203x_device::ldiv_ind(UINT32 op) |
| 5217 | { |
| 5218 | UINT32 val = RMEM(INDIRECT_D(op, op >> 8)); |
| 5219 | if (CONDITION_V()) |
| 5220 | { |
| 5221 | int dreg = (op >> 16) & 31; |
| 5222 | IREG(dreg) = val; |
| 5223 | if (dreg >= TMR_BK) |
| 5224 | update_special(dreg); |
| 5225 | } |
| 5226 | } |
| 5227 | |
| 5228 | void tms3203x_device::ldiv_imm(UINT32 op) |
| 5229 | { |
| 5230 | if (CONDITION_V()) |
| 5231 | { |
| 5232 | int dreg = (op >> 16) & 31; |
| 5233 | IREG(dreg) = (INT16)op; |
| 5234 | if (dreg >= TMR_BK) |
| 5235 | update_special(dreg); |
| 5236 | } |
| 5237 | } |
| 5238 | |
| 5239 | /*-----------------------------------------------------*/ |
| 5240 | |
| 5241 | void tms3203x_device::ldinlv_reg(UINT32 op) |
| 5242 | { |
| 5243 | if (CONDITION_NLV()) |
| 5244 | { |
| 5245 | int dreg = (op >> 16) & 31; |
| 5246 | IREG(dreg) = IREG(op & 31); |
| 5247 | if (dreg >= TMR_BK) |
| 5248 | update_special(dreg); |
| 5249 | } |
| 5250 | } |
| 5251 | |
| 5252 | void tms3203x_device::ldinlv_dir(UINT32 op) |
| 5253 | { |
| 5254 | UINT32 val = RMEM(DIRECT(op)); |
| 5255 | if (CONDITION_NLV()) |
| 5256 | { |
| 5257 | int dreg = (op >> 16) & 31; |
| 5258 | IREG(dreg) = val; |
| 5259 | if (dreg >= TMR_BK) |
| 5260 | update_special(dreg); |
| 5261 | } |
| 5262 | } |
| 5263 | |
| 5264 | void tms3203x_device::ldinlv_ind(UINT32 op) |
| 5265 | { |
| 5266 | UINT32 val = RMEM(INDIRECT_D(op, op >> 8)); |
| 5267 | if (CONDITION_NLV()) |
| 5268 | { |
| 5269 | int dreg = (op >> 16) & 31; |
| 5270 | IREG(dreg) = val; |
| 5271 | if (dreg >= TMR_BK) |
| 5272 | update_special(dreg); |
| 5273 | } |
| 5274 | } |
| 5275 | |
| 5276 | void tms3203x_device::ldinlv_imm(UINT32 op) |
| 5277 | { |
| 5278 | if (CONDITION_NLV()) |
| 5279 | { |
| 5280 | int dreg = (op >> 16) & 31; |
| 5281 | IREG(dreg) = (INT16)op; |
| 5282 | if (dreg >= TMR_BK) |
| 5283 | update_special(dreg); |
| 5284 | } |
| 5285 | } |
| 5286 | |
| 5287 | /*-----------------------------------------------------*/ |
| 5288 | |
| 5289 | void tms3203x_device::ldilv_reg(UINT32 op) |
| 5290 | { |
| 5291 | if (CONDITION_LV()) |
| 5292 | { |
| 5293 | int dreg = (op >> 16) & 31; |
| 5294 | IREG(dreg) = IREG(op & 31); |
| 5295 | if (dreg >= TMR_BK) |
| 5296 | update_special(dreg); |
| 5297 | } |
| 5298 | } |
| 5299 | |
| 5300 | void tms3203x_device::ldilv_dir(UINT32 op) |
| 5301 | { |
| 5302 | UINT32 val = RMEM(DIRECT(op)); |
| 5303 | if (CONDITION_LV()) |
| 5304 | { |
| 5305 | int dreg = (op >> 16) & 31; |
| 5306 | IREG(dreg) = val; |
| 5307 | if (dreg >= TMR_BK) |
| 5308 | update_special(dreg); |
| 5309 | } |
| 5310 | } |
| 5311 | |
| 5312 | void tms3203x_device::ldilv_ind(UINT32 op) |
| 5313 | { |
| 5314 | UINT32 val = RMEM(INDIRECT_D(op, op >> 8)); |
| 5315 | if (CONDITION_LV()) |
| 5316 | { |
| 5317 | int dreg = (op >> 16) & 31; |
| 5318 | IREG(dreg) = val; |
| 5319 | if (dreg >= TMR_BK) |
| 5320 | update_special(dreg); |
| 5321 | } |
| 5322 | } |
| 5323 | |
| 5324 | void tms3203x_device::ldilv_imm(UINT32 op) |
| 5325 | { |
| 5326 | if (CONDITION_LV()) |
| 5327 | { |
| 5328 | int dreg = (op >> 16) & 31; |
| 5329 | IREG(dreg) = (INT16)op; |
| 5330 | if (dreg >= TMR_BK) |
| 5331 | update_special(dreg); |
| 5332 | } |
| 5333 | } |
| 5334 | |
| 5335 | /*-----------------------------------------------------*/ |
| 5336 | |
| 5337 | void tms3203x_device::ldinluf_reg(UINT32 op) |
| 5338 | { |
| 5339 | if (CONDITION_NLUF()) |
| 5340 | { |
| 5341 | int dreg = (op >> 16) & 31; |
| 5342 | IREG(dreg) = IREG(op & 31); |
| 5343 | if (dreg >= TMR_BK) |
| 5344 | update_special(dreg); |
| 5345 | } |
| 5346 | } |
| 5347 | |
| 5348 | void tms3203x_device::ldinluf_dir(UINT32 op) |
| 5349 | { |
| 5350 | UINT32 val = RMEM(DIRECT(op)); |
| 5351 | if (CONDITION_NLUF()) |
| 5352 | { |
| 5353 | int dreg = (op >> 16) & 31; |
| 5354 | IREG(dreg) = val; |
| 5355 | if (dreg >= TMR_BK) |
| 5356 | update_special(dreg); |
| 5357 | } |
| 5358 | } |
| 5359 | |
| 5360 | void tms3203x_device::ldinluf_ind(UINT32 op) |
| 5361 | { |
| 5362 | UINT32 val = RMEM(INDIRECT_D(op, op >> 8)); |
| 5363 | if (CONDITION_NLUF()) |
| 5364 | { |
| 5365 | int dreg = (op >> 16) & 31; |
| 5366 | IREG(dreg) = val; |
| 5367 | if (dreg >= TMR_BK) |
| 5368 | update_special(dreg); |
| 5369 | } |
| 5370 | } |
| 5371 | |
| 5372 | void tms3203x_device::ldinluf_imm(UINT32 op) |
| 5373 | { |
| 5374 | if (CONDITION_NLUF()) |
| 5375 | { |
| 5376 | int dreg = (op >> 16) & 31; |
| 5377 | IREG(dreg) = (INT16)op; |
| 5378 | if (dreg >= TMR_BK) |
| 5379 | update_special(dreg); |
| 5380 | } |
| 5381 | } |
| 5382 | |
| 5383 | /*-----------------------------------------------------*/ |
| 5384 | |
| 5385 | void tms3203x_device::ldiluf_reg(UINT32 op) |
| 5386 | { |
| 5387 | if (CONDITION_LUF()) |
| 5388 | { |
| 5389 | int dreg = (op >> 16) & 31; |
| 5390 | IREG(dreg) = IREG(op & 31); |
| 5391 | if (dreg >= TMR_BK) |
| 5392 | update_special(dreg); |
| 5393 | } |
| 5394 | } |
| 5395 | |
| 5396 | void tms3203x_device::ldiluf_dir(UINT32 op) |
| 5397 | { |
| 5398 | UINT32 val = RMEM(DIRECT(op)); |
| 5399 | if (CONDITION_LUF()) |
| 5400 | { |
| 5401 | int dreg = (op >> 16) & 31; |
| 5402 | IREG(dreg) = val; |
| 5403 | if (dreg >= TMR_BK) |
| 5404 | update_special(dreg); |
| 5405 | } |
| 5406 | } |
| 5407 | |
| 5408 | void tms3203x_device::ldiluf_ind(UINT32 op) |
| 5409 | { |
| 5410 | UINT32 val = RMEM(INDIRECT_D(op, op >> 8)); |
| 5411 | if (CONDITION_LUF()) |
| 5412 | { |
| 5413 | int dreg = (op >> 16) & 31; |
| 5414 | IREG(dreg) = val; |
| 5415 | if (dreg >= TMR_BK) |
| 5416 | update_special(dreg); |
| 5417 | } |
| 5418 | } |
| 5419 | |
| 5420 | void tms3203x_device::ldiluf_imm(UINT32 op) |
| 5421 | { |
| 5422 | if (CONDITION_LUF()) |
| 5423 | { |
| 5424 | int dreg = (op >> 16) & 31; |
| 5425 | IREG(dreg) = (INT16)op; |
| 5426 | if (dreg >= TMR_BK) |
| 5427 | update_special(dreg); |
| 5428 | } |
| 5429 | } |
| 5430 | |
| 5431 | /*-----------------------------------------------------*/ |
| 5432 | |
| 5433 | void tms3203x_device::ldizuf_reg(UINT32 op) |
| 5434 | { |
| 5435 | if (CONDITION_ZUF()) |
| 5436 | { |
| 5437 | int dreg = (op >> 16) & 31; |
| 5438 | IREG(dreg) = IREG(op & 31); |
| 5439 | if (dreg >= TMR_BK) |
| 5440 | update_special(dreg); |
| 5441 | } |
| 5442 | } |
| 5443 | |
| 5444 | void tms3203x_device::ldizuf_dir(UINT32 op) |
| 5445 | { |
| 5446 | UINT32 val = RMEM(DIRECT(op)); |
| 5447 | if (CONDITION_ZUF()) |
| 5448 | { |
| 5449 | int dreg = (op >> 16) & 31; |
| 5450 | IREG(dreg) = val; |
| 5451 | if (dreg >= TMR_BK) |
| 5452 | update_special(dreg); |
| 5453 | } |
| 5454 | } |
| 5455 | |
| 5456 | void tms3203x_device::ldizuf_ind(UINT32 op) |
| 5457 | { |
| 5458 | UINT32 val = RMEM(INDIRECT_D(op, op >> 8)); |
| 5459 | if (CONDITION_ZUF()) |
| 5460 | { |
| 5461 | int dreg = (op >> 16) & 31; |
| 5462 | IREG(dreg) = val; |
| 5463 | if (dreg >= TMR_BK) |
| 5464 | update_special(dreg); |
| 5465 | } |
| 5466 | } |
| 5467 | |
| 5468 | void tms3203x_device::ldizuf_imm(UINT32 op) |
| 5469 | { |
| 5470 | if (CONDITION_ZUF()) |
| 5471 | { |
| 5472 | int dreg = (op >> 16) & 31; |
| 5473 | IREG(dreg) = (INT16)op; |
| 5474 | if (dreg >= TMR_BK) |
| 5475 | update_special(dreg); |
| 5476 | } |
| 5477 | } |
| 5478 | |
| 5479 | /*-----------------------------------------------------*/ |
| 5480 | |
| 5481 | inline void tms3203x_device::execute_delayed(UINT32 newpc) |
| 5482 | { |
| 5483 | m_delayed = true; |
| 5484 | |
| 5485 | if ((machine().debug_flags & DEBUG_FLAG_ENABLED) == 0) |
| 5486 | { |
| 5487 | execute_one(); |
| 5488 | execute_one(); |
| 5489 | execute_one(); |
| 5490 | } |
| 5491 | else |
| 5492 | { |
| 5493 | debugger_instruction_hook(this, m_pc); |
| 5494 | execute_one(); |
| 5495 | debugger_instruction_hook(this, m_pc); |
| 5496 | execute_one(); |
| 5497 | debugger_instruction_hook(this, m_pc); |
| 5498 | execute_one(); |
| 5499 | } |
| 5500 | |
| 5501 | if (newpc != ~0) |
| 5502 | m_pc = newpc; |
| 5503 | |
| 5504 | m_delayed = false; |
| 5505 | if (m_irq_pending) |
| 5506 | { |
| 5507 | m_irq_pending = false; |
| 5508 | check_irqs(); |
| 5509 | } |
| 5510 | } |
| 5511 | |
| 5512 | /*-----------------------------------------------------*/ |
| 5513 | |
| 5514 | void tms3203x_device::br_imm(UINT32 op) |
| 5515 | { |
| 5516 | m_pc = op & 0xffffff; |
| 5517 | m_icount -= 3*2; |
| 5518 | } |
| 5519 | |
| 5520 | void tms3203x_device::brd_imm(UINT32 op) |
| 5521 | { |
| 5522 | execute_delayed(op & 0xffffff); |
| 5523 | } |
| 5524 | |
| 5525 | /*-----------------------------------------------------*/ |
| 5526 | |
| 5527 | void tms3203x_device::call_imm(UINT32 op) |
| 5528 | { |
| 5529 | WMEM(++IREG(TMR_SP), m_pc); |
| 5530 | m_pc = op & 0xffffff; |
| 5531 | m_icount -= 3*2; |
| 5532 | } |
| 5533 | |
| 5534 | /*-----------------------------------------------------*/ |
| 5535 | |
| 5536 | void tms3203x_device::rptb_imm(UINT32 op) |
| 5537 | { |
| 5538 | IREG(TMR_RS) = m_pc; |
| 5539 | IREG(TMR_RE) = op & 0xffffff; |
| 5540 | IREG(TMR_ST) |= RMFLAG; |
| 5541 | m_icount -= 3*2; |
| 5542 | } |
| 5543 | |
| 5544 | /*-----------------------------------------------------*/ |
| 5545 | |
| 5546 | void tms3203x_device::swi(UINT32 op) { unimplemented(op); } |
| 5547 | |
| 5548 | /*-----------------------------------------------------*/ |
| 5549 | |
| 5550 | void tms3203x_device::brc_reg(UINT32 op) |
| 5551 | { |
| 5552 | if (condition(op >> 16)) |
| 5553 | { |
| 5554 | m_pc = IREG(op & 31); |
| 5555 | m_icount -= 3*2; |
| 5556 | } |
| 5557 | } |
| 5558 | |
| 5559 | void tms3203x_device::brcd_reg(UINT32 op) |
| 5560 | { |
| 5561 | if (condition(op >> 16)) |
| 5562 | execute_delayed(IREG(op & 31)); |
| 5563 | else |
| 5564 | execute_delayed(~0); |
| 5565 | } |
| 5566 | |
| 5567 | void tms3203x_device::brc_imm(UINT32 op) |
| 5568 | { |
| 5569 | if (condition(op >> 16)) |
| 5570 | { |
| 5571 | m_pc += (INT16)op; |
| 5572 | m_icount -= 3*2; |
| 5573 | } |
| 5574 | } |
| 5575 | |
| 5576 | void tms3203x_device::brcd_imm(UINT32 op) |
| 5577 | { |
| 5578 | if (condition(op >> 16)) |
| 5579 | execute_delayed(m_pc + 2 + (INT16)op); |
| 5580 | else |
| 5581 | execute_delayed(~0); |
| 5582 | } |
| 5583 | |
| 5584 | /*-----------------------------------------------------*/ |
| 5585 | |
| 5586 | void tms3203x_device::dbc_reg(UINT32 op) |
| 5587 | { |
| 5588 | int reg = TMR_AR0 + ((op >> 22) & 7); |
| 5589 | int res = (IREG(reg) - 1) & 0xffffff; |
| 5590 | IREG(reg) = res | (IREG(reg) & 0xff000000); |
| 5591 | if (condition(op >> 16) && !(res & 0x800000)) |
| 5592 | { |
| 5593 | m_pc = IREG(op & 31); |
| 5594 | m_icount -= 3*2; |
| 5595 | } |
| 5596 | } |
| 5597 | |
| 5598 | void tms3203x_device::dbcd_reg(UINT32 op) |
| 5599 | { |
| 5600 | int reg = TMR_AR0 + ((op >> 22) & 7); |
| 5601 | int res = (IREG(reg) - 1) & 0xffffff; |
| 5602 | IREG(reg) = res | (IREG(reg) & 0xff000000); |
| 5603 | if (condition(op >> 16) && !(res & 0x800000)) |
| 5604 | execute_delayed(IREG(op & 31)); |
| 5605 | else |
| 5606 | execute_delayed(~0); |
| 5607 | } |
| 5608 | |
| 5609 | void tms3203x_device::dbc_imm(UINT32 op) |
| 5610 | { |
| 5611 | int reg = TMR_AR0 + ((op >> 22) & 7); |
| 5612 | int res = (IREG(reg) - 1) & 0xffffff; |
| 5613 | IREG(reg) = res | (IREG(reg) & 0xff000000); |
| 5614 | if (condition(op >> 16) && !(res & 0x800000)) |
| 5615 | { |
| 5616 | m_pc += (INT16)op; |
| 5617 | m_icount -= 3*2; |
| 5618 | } |
| 5619 | } |
| 5620 | |
| 5621 | void tms3203x_device::dbcd_imm(UINT32 op) |
| 5622 | { |
| 5623 | int reg = TMR_AR0 + ((op >> 22) & 7); |
| 5624 | int res = (IREG(reg) - 1) & 0xffffff; |
| 5625 | IREG(reg) = res | (IREG(reg) & 0xff000000); |
| 5626 | if (condition(op >> 16) && !(res & 0x800000)) |
| 5627 | execute_delayed(m_pc + 2 + (INT16)op); |
| 5628 | else |
| 5629 | execute_delayed(~0); |
| 5630 | } |
| 5631 | |
| 5632 | /*-----------------------------------------------------*/ |
| 5633 | |
| 5634 | void tms3203x_device::callc_reg(UINT32 op) |
| 5635 | { |
| 5636 | if (condition(op >> 16)) |
| 5637 | { |
| 5638 | WMEM(++IREG(TMR_SP), m_pc); |
| 5639 | m_pc = IREG(op & 31); |
| 5640 | m_icount -= 3*2; |
| 5641 | } |
| 5642 | } |
| 5643 | |
| 5644 | void tms3203x_device::callc_imm(UINT32 op) |
| 5645 | { |
| 5646 | if (condition(op >> 16)) |
| 5647 | { |
| 5648 | WMEM(++IREG(TMR_SP), m_pc); |
| 5649 | m_pc += (INT16)op; |
| 5650 | m_icount -= 3*2; |
| 5651 | } |
| 5652 | } |
| 5653 | |
| 5654 | /*-----------------------------------------------------*/ |
| 5655 | |
| 5656 | void tms3203x_device::trap(int trapnum) |
| 5657 | { |
| 5658 | WMEM(++IREG(TMR_SP), m_pc); |
| 5659 | IREG(TMR_ST) &= ~GIEFLAG; |
| 5660 | if (m_chip_type == CHIP_TYPE_TMS32032) |
| 5661 | m_pc = RMEM(((IREG(TMR_IF) >> 16) << 8) + trapnum); |
| 5662 | else |
| 5663 | m_pc = RMEM(trapnum); |
| 5664 | m_icount -= 4*2; |
| 5665 | } |
| 5666 | |
| 5667 | void tms3203x_device::trapc(UINT32 op) |
| 5668 | { |
| 5669 | if (condition(op >> 16)) |
| 5670 | trap(op & 0x3f); |
| 5671 | } |
| 5672 | |
| 5673 | /*-----------------------------------------------------*/ |
| 5674 | |
| 5675 | void tms3203x_device::retic_reg(UINT32 op) |
| 5676 | { |
| 5677 | if (condition(op >> 16)) |
| 5678 | { |
| 5679 | m_pc = RMEM(IREG(TMR_SP)--); |
| 5680 | IREG(TMR_ST) |= GIEFLAG; |
| 5681 | m_icount -= 3*2; |
| 5682 | check_irqs(); |
| 5683 | } |
| 5684 | } |
| 5685 | |
| 5686 | void tms3203x_device::retsc_reg(UINT32 op) |
| 5687 | { |
| 5688 | if (condition(op >> 16)) |
| 5689 | { |
| 5690 | m_pc = RMEM(IREG(TMR_SP)--); |
| 5691 | m_icount -= 3*2; |
| 5692 | } |
| 5693 | } |
| 5694 | |
| 5695 | /*-----------------------------------------------------*/ |
| 5696 | |
| 5697 | void tms3203x_device::mpyaddf_0(UINT32 op) |
| 5698 | { |
| 5699 | // src3 * src4, src1 + src2 |
| 5700 | DECLARE_DEF; |
| 5701 | UINT32 src3 = RMEM(INDIRECT_1_DEF(op, op >> 8)); |
| 5702 | UINT32 src4 = RMEM(INDIRECT_1(op, op)); |
| 5703 | LONG2FP(TMR_TEMP1, src3); |
| 5704 | LONG2FP(TMR_TEMP2, src4); |
| 5705 | mpyf(m_r[TMR_TEMP3], m_r[TMR_TEMP1], m_r[TMR_TEMP2]); |
| 5706 | addf(m_r[((op >> 22) & 1) | 2], m_r[(op >> 19) & 7], m_r[(op >> 16) & 7]); |
| 5707 | m_r[(op >> 23) & 1] = m_r[TMR_TEMP3]; |
| 5708 | UPDATE_DEF(); |
| 5709 | } |
| 5710 | |
| 5711 | void tms3203x_device::mpyaddf_1(UINT32 op) |
| 5712 | { |
| 5713 | // src3 * src1, src4 + src2 |
| 5714 | DECLARE_DEF; |
| 5715 | UINT32 src3 = RMEM(INDIRECT_1_DEF(op, op >> 8)); |
| 5716 | UINT32 src4 = RMEM(INDIRECT_1(op, op)); |
| 5717 | LONG2FP(TMR_TEMP1, src3); |
| 5718 | LONG2FP(TMR_TEMP2, src4); |
| 5719 | mpyf(m_r[TMR_TEMP3], m_r[TMR_TEMP1], m_r[(op >> 19) & 7]); |
| 5720 | addf(m_r[((op >> 22) & 1) | 2], m_r[TMR_TEMP2], m_r[(op >> 16) & 7]); |
| 5721 | m_r[(op >> 23) & 1] = m_r[TMR_TEMP3]; |
| 5722 | UPDATE_DEF(); |
| 5723 | } |
| 5724 | |
| 5725 | void tms3203x_device::mpyaddf_2(UINT32 op) |
| 5726 | { |
| 5727 | // src1 * src2, src3 + src4 |
| 5728 | DECLARE_DEF; |
| 5729 | UINT32 src3 = RMEM(INDIRECT_1_DEF(op, op >> 8)); |
| 5730 | UINT32 src4 = RMEM(INDIRECT_1(op, op)); |
| 5731 | LONG2FP(TMR_TEMP1, src3); |
| 5732 | LONG2FP(TMR_TEMP2, src4); |
| 5733 | mpyf(m_r[TMR_TEMP3], m_r[(op >> 19) & 7], m_r[(op >> 16) & 7]); |
| 5734 | addf(m_r[((op >> 22) & 1) | 2], m_r[TMR_TEMP1], m_r[TMR_TEMP2]); |
| 5735 | m_r[(op >> 23) & 1] = m_r[TMR_TEMP3]; |
| 5736 | UPDATE_DEF(); |
| 5737 | } |
| 5738 | |
| 5739 | void tms3203x_device::mpyaddf_3(UINT32 op) |
| 5740 | { |
| 5741 | // src3 * src1, src2 + src4 |
| 5742 | DECLARE_DEF; |
| 5743 | UINT32 src3 = RMEM(INDIRECT_1_DEF(op, op >> 8)); |
| 5744 | UINT32 src4 = RMEM(INDIRECT_1(op, op)); |
| 5745 | LONG2FP(TMR_TEMP1, src3); |
| 5746 | LONG2FP(TMR_TEMP2, src4); |
| 5747 | mpyf(m_r[TMR_TEMP3], m_r[TMR_TEMP1], m_r[(op >> 19) & 7]); |
| 5748 | addf(m_r[((op >> 22) & 1) | 2], m_r[(op >> 16) & 7], m_r[TMR_TEMP2]); |
| 5749 | m_r[(op >> 23) & 1] = m_r[TMR_TEMP3]; |
| 5750 | UPDATE_DEF(); |
| 5751 | } |
| 5752 | |
| 5753 | /*-----------------------------------------------------*/ |
| 5754 | |
| 5755 | void tms3203x_device::mpysubf_0(UINT32 op) |
| 5756 | { |
| 5757 | // src3 * src4, src1 - src2 |
| 5758 | DECLARE_DEF; |
| 5759 | UINT32 src3 = RMEM(INDIRECT_1_DEF(op, op >> 8)); |
| 5760 | UINT32 src4 = RMEM(INDIRECT_1(op, op)); |
| 5761 | LONG2FP(TMR_TEMP1, src3); |
| 5762 | LONG2FP(TMR_TEMP2, src4); |
| 5763 | mpyf(m_r[TMR_TEMP3], m_r[TMR_TEMP1], m_r[TMR_TEMP2]); |
| 5764 | subf(m_r[((op >> 22) & 1) | 2], m_r[(op >> 19) & 7], m_r[(op >> 16) & 7]); |
| 5765 | m_r[(op >> 23) & 1] = m_r[TMR_TEMP3]; |
| 5766 | UPDATE_DEF(); |
| 5767 | } |
| 5768 | |
| 5769 | void tms3203x_device::mpysubf_1(UINT32 op) |
| 5770 | { |
| 5771 | // src3 * src1, src4 - src2 |
| 5772 | DECLARE_DEF; |
| 5773 | UINT32 src3 = RMEM(INDIRECT_1_DEF(op, op >> 8)); |
| 5774 | UINT32 src4 = RMEM(INDIRECT_1(op, op)); |
| 5775 | LONG2FP(TMR_TEMP1, src3); |
| 5776 | LONG2FP(TMR_TEMP2, src4); |
| 5777 | mpyf(m_r[TMR_TEMP3], m_r[TMR_TEMP1], m_r[(op >> 19) & 7]); |
| 5778 | subf(m_r[((op >> 22) & 1) | 2], m_r[TMR_TEMP2], m_r[(op >> 16) & 7]); |
| 5779 | m_r[(op >> 23) & 1] = m_r[TMR_TEMP3]; |
| 5780 | UPDATE_DEF(); |
| 5781 | } |
| 5782 | |
| 5783 | void tms3203x_device::mpysubf_2(UINT32 op) |
| 5784 | { |
| 5785 | // src1 * src2, src3 - src4 |
| 5786 | DECLARE_DEF; |
| 5787 | UINT32 src3 = RMEM(INDIRECT_1_DEF(op, op >> 8)); |
| 5788 | UINT32 src4 = RMEM(INDIRECT_1(op, op)); |
| 5789 | LONG2FP(TMR_TEMP1, src3); |
| 5790 | LONG2FP(TMR_TEMP2, src4); |
| 5791 | mpyf(m_r[TMR_TEMP3], m_r[(op >> 19) & 7], m_r[(op >> 16) & 7]); |
| 5792 | subf(m_r[((op >> 22) & 1) | 2], m_r[TMR_TEMP1], m_r[TMR_TEMP2]); |
| 5793 | m_r[(op >> 23) & 1] = m_r[TMR_TEMP3]; |
| 5794 | UPDATE_DEF(); |
| 5795 | } |
| 5796 | |
| 5797 | void tms3203x_device::mpysubf_3(UINT32 op) |
| 5798 | { |
| 5799 | // src3 * src1, src2 - src4 |
| 5800 | DECLARE_DEF; |
| 5801 | UINT32 src3 = RMEM(INDIRECT_1_DEF(op, op >> 8)); |
| 5802 | UINT32 src4 = RMEM(INDIRECT_1(op, op)); |
| 5803 | LONG2FP(TMR_TEMP1, src3); |
| 5804 | LONG2FP(TMR_TEMP2, src4); |
| 5805 | mpyf(m_r[TMR_TEMP3], m_r[TMR_TEMP1], m_r[(op >> 19) & 7]); |
| 5806 | subf(m_r[((op >> 22) & 1) | 2], m_r[(op >> 16) & 7], m_r[TMR_TEMP2]); |
| 5807 | m_r[(op >> 23) & 1] = m_r[TMR_TEMP3]; |
| 5808 | UPDATE_DEF(); |
| 5809 | } |
| 5810 | |
| 5811 | /*-----------------------------------------------------*/ |
| 5812 | |
| 5813 | void tms3203x_device::mpyaddi_0(UINT32 op) |
| 5814 | { |
| 5815 | // src3 * src4, src1 + src2 |
| 5816 | DECLARE_DEF; |
| 5817 | UINT32 src1 = IREG((op >> 19) & 7); |
| 5818 | UINT32 src2 = IREG((op >> 16) & 7); |
| 5819 | UINT32 src3 = RMEM(INDIRECT_1_DEF(op, op >> 8)); |
| 5820 | UINT32 src4 = RMEM(INDIRECT_1(op, op)); |
| 5821 | INT64 mres = (INT64)((INT32)(src3 << 8) >> 8) * (INT64)((INT32)(src4 << 8) >> 8); |
| 5822 | UINT32 ares = src1 + src2; |
| 5823 | |
| 5824 | CLR_NZVUF(); |
| 5825 | if (OVM()) |
| 5826 | { |
| 5827 | if (mres < -(INT64)0x80000000 || mres > (INT64)0x7fffffff) |
| 5828 | mres = (mres < 0) ? 0x80000000 : 0x7fffffff; |
| 5829 | if (OVERFLOW_ADD(src1,src2,ares)) |
| 5830 | ares = ((INT32)src1 < 0) ? 0x80000000 : 0x7fffffff; |
| 5831 | } |
| 5832 | IREG((op >> 23) & 1) = mres; |
| 5833 | IREG(((op >> 22) & 1) | 2) = ares; |
| 5834 | UPDATE_DEF(); |
| 5835 | } |
| 5836 | |
| 5837 | void tms3203x_device::mpyaddi_1(UINT32 op) |
| 5838 | { |
| 5839 | // src3 * src1, src4 + src2 |
| 5840 | DECLARE_DEF; |
| 5841 | UINT32 src1 = IREG((op >> 19) & 7); |
| 5842 | UINT32 src2 = IREG((op >> 16) & 7); |
| 5843 | UINT32 src3 = RMEM(INDIRECT_1_DEF(op, op >> 8)); |
| 5844 | UINT32 src4 = RMEM(INDIRECT_1(op, op)); |
| 5845 | INT64 mres = (INT64)((INT32)(src3 << 8) >> 8) * (INT64)((INT32)(src1 << 8) >> 8); |
| 5846 | UINT32 ares = src4 + src2; |
| 5847 | |
| 5848 | CLR_NZVUF(); |
| 5849 | if (OVM()) |
| 5850 | { |
| 5851 | if (mres < -(INT64)0x80000000 || mres > (INT64)0x7fffffff) |
| 5852 | mres = (mres < 0) ? 0x80000000 : 0x7fffffff; |
| 5853 | if (OVERFLOW_ADD(src4,src2,ares)) |
| 5854 | ares = ((INT32)src4 < 0) ? 0x80000000 : 0x7fffffff; |
| 5855 | } |
| 5856 | IREG((op >> 23) & 1) = mres; |
| 5857 | IREG(((op >> 22) & 1) | 2) = ares; |
| 5858 | UPDATE_DEF(); |
| 5859 | } |
| 5860 | |
| 5861 | void tms3203x_device::mpyaddi_2(UINT32 op) |
| 5862 | { |
| 5863 | // src1 * src2, src3 + src4 |
| 5864 | DECLARE_DEF; |
| 5865 | UINT32 src1 = IREG((op >> 19) & 7); |
| 5866 | UINT32 src2 = IREG((op >> 16) & 7); |
| 5867 | UINT32 src3 = RMEM(INDIRECT_1_DEF(op, op >> 8)); |
| 5868 | UINT32 src4 = RMEM(INDIRECT_1(op, op)); |
| 5869 | INT64 mres = (INT64)((INT32)(src1 << 8) >> 8) * (INT64)((INT32)(src2 << 8) >> 8); |
| 5870 | UINT32 ares = src3 + src4; |
| 5871 | |
| 5872 | CLR_NZVUF(); |
| 5873 | if (OVM()) |
| 5874 | { |
| 5875 | if (mres < -(INT64)0x80000000 || mres > (INT64)0x7fffffff) |
| 5876 | mres = (mres < 0) ? 0x80000000 : 0x7fffffff; |
| 5877 | if (OVERFLOW_ADD(src3,src4,ares)) |
| 5878 | ares = ((INT32)src3 < 0) ? 0x80000000 : 0x7fffffff; |
| 5879 | } |
| 5880 | IREG((op >> 23) & 1) = mres; |
| 5881 | IREG(((op >> 22) & 1) | 2) = ares; |
| 5882 | UPDATE_DEF(); |
| 5883 | } |
| 5884 | |
| 5885 | void tms3203x_device::mpyaddi_3(UINT32 op) |
| 5886 | { |
| 5887 | // src3 * src1, src2 + src4 |
| 5888 | DECLARE_DEF; |
| 5889 | UINT32 src1 = IREG((op >> 19) & 7); |
| 5890 | UINT32 src2 = IREG((op >> 16) & 7); |
| 5891 | UINT32 src3 = RMEM(INDIRECT_1_DEF(op, op >> 8)); |
| 5892 | UINT32 src4 = RMEM(INDIRECT_1(op, op)); |
| 5893 | INT64 mres = (INT64)((INT32)(src3 << 8) >> 8) * (INT64)((INT32)(src1 << 8) >> 8); |
| 5894 | UINT32 ares = src2 + src4; |
| 5895 | |
| 5896 | CLR_NZVUF(); |
| 5897 | if (OVM()) |
| 5898 | { |
| 5899 | if (mres < -(INT64)0x80000000 || mres > (INT64)0x7fffffff) |
| 5900 | mres = (mres < 0) ? 0x80000000 : 0x7fffffff; |
| 5901 | if (OVERFLOW_ADD(src2,src4,ares)) |
| 5902 | ares = ((INT32)src2 < 0) ? 0x80000000 : 0x7fffffff; |
| 5903 | } |
| 5904 | IREG((op >> 23) & 1) = mres; |
| 5905 | IREG(((op >> 22) & 1) | 2) = ares; |
| 5906 | UPDATE_DEF(); |
| 5907 | } |
| 5908 | |
| 5909 | /*-----------------------------------------------------*/ |
| 5910 | |
| 5911 | void tms3203x_device::mpysubi_0(UINT32 op) |
| 5912 | { |
| 5913 | // src3 * src4, src1 - src2 |
| 5914 | DECLARE_DEF; |
| 5915 | UINT32 src1 = IREG((op >> 19) & 7); |
| 5916 | UINT32 src2 = IREG((op >> 16) & 7); |
| 5917 | UINT32 src3 = RMEM(INDIRECT_1_DEF(op, op >> 8)); |
| 5918 | UINT32 src4 = RMEM(INDIRECT_1(op, op)); |
| 5919 | INT64 mres = (INT64)((INT32)(src3 << 8) >> 8) * (INT64)((INT32)(src4 << 8) >> 8); |
| 5920 | UINT32 ares = src1 - src2; |
| 5921 | |
| 5922 | CLR_NZVUF(); |
| 5923 | if (OVM()) |
| 5924 | { |
| 5925 | if (mres < -(INT64)0x80000000 || mres > (INT64)0x7fffffff) |
| 5926 | mres = (mres < 0) ? 0x80000000 : 0x7fffffff; |
| 5927 | if (OVERFLOW_SUB(src1,src2,ares)) |
| 5928 | ares = ((INT32)src1 < 0) ? 0x80000000 : 0x7fffffff; |
| 5929 | } |
| 5930 | IREG((op >> 23) & 1) = mres; |
| 5931 | IREG(((op >> 22) & 1) | 2) = ares; |
| 5932 | UPDATE_DEF(); |
| 5933 | } |
| 5934 | |
| 5935 | void tms3203x_device::mpysubi_1(UINT32 op) |
| 5936 | { |
| 5937 | // src3 * src1, src4 - src2 |
| 5938 | DECLARE_DEF; |
| 5939 | UINT32 src1 = IREG((op >> 19) & 7); |
| 5940 | UINT32 src2 = IREG((op >> 16) & 7); |
| 5941 | UINT32 src3 = RMEM(INDIRECT_1_DEF(op, op >> 8)); |
| 5942 | UINT32 src4 = RMEM(INDIRECT_1(op, op)); |
| 5943 | INT64 mres = (INT64)((INT32)(src3 << 8) >> 8) * (INT64)((INT32)(src1 << 8) >> 8); |
| 5944 | UINT32 ares = src4 - src2; |
| 5945 | |
| 5946 | CLR_NZVUF(); |
| 5947 | if (OVM()) |
| 5948 | { |
| 5949 | if (mres < -(INT64)0x80000000 || mres > (INT64)0x7fffffff) |
| 5950 | mres = (mres < 0) ? 0x80000000 : 0x7fffffff; |
| 5951 | if (OVERFLOW_SUB(src4,src2,ares)) |
| 5952 | ares = ((INT32)src4 < 0) ? 0x80000000 : 0x7fffffff; |
| 5953 | } |
| 5954 | IREG((op >> 23) & 1) = mres; |
| 5955 | IREG(((op >> 22) & 1) | 2) = ares; |
| 5956 | UPDATE_DEF(); |
| 5957 | } |
| 5958 | |
| 5959 | void tms3203x_device::mpysubi_2(UINT32 op) |
| 5960 | { |
| 5961 | // src1 * src2, src3 - src4 |
| 5962 | DECLARE_DEF; |
| 5963 | UINT32 src1 = IREG((op >> 19) & 7); |
| 5964 | UINT32 src2 = IREG((op >> 16) & 7); |
| 5965 | UINT32 src3 = RMEM(INDIRECT_1_DEF(op, op >> 8)); |
| 5966 | UINT32 src4 = RMEM(INDIRECT_1(op, op)); |
| 5967 | INT64 mres = (INT64)((INT32)(src1 << 8) >> 8) * (INT64)((INT32)(src2 << 8) >> 8); |
| 5968 | UINT32 ares = src3 - src4; |
| 5969 | |
| 5970 | CLR_NZVUF(); |
| 5971 | if (OVM()) |
| 5972 | { |
| 5973 | if (mres < -(INT64)0x80000000 || mres > (INT64)0x7fffffff) |
| 5974 | mres = (mres < 0) ? 0x80000000 : 0x7fffffff; |
| 5975 | if (OVERFLOW_SUB(src3,src4,ares)) |
| 5976 | ares = ((INT32)src3 < 0) ? 0x80000000 : 0x7fffffff; |
| 5977 | } |
| 5978 | IREG((op >> 23) & 1) = mres; |
| 5979 | IREG(((op >> 22) & 1) | 2) = ares; |
| 5980 | UPDATE_DEF(); |
| 5981 | } |
| 5982 | |
| 5983 | void tms3203x_device::mpysubi_3(UINT32 op) |
| 5984 | { |
| 5985 | // src3 * src1, src2 - src4 |
| 5986 | DECLARE_DEF; |
| 5987 | UINT32 src1 = IREG((op >> 19) & 7); |
| 5988 | UINT32 src2 = IREG((op >> 16) & 7); |
| 5989 | UINT32 src3 = RMEM(INDIRECT_1_DEF(op, op >> 8)); |
| 5990 | UINT32 src4 = RMEM(INDIRECT_1(op, op)); |
| 5991 | INT64 mres = (INT64)((INT32)(src3 << 8) >> 8) * (INT64)((INT32)(src1 << 8) >> 8); |
| 5992 | UINT32 ares = src2 - src4; |
| 5993 | |
| 5994 | CLR_NZVUF(); |
| 5995 | if (OVM()) |
| 5996 | { |
| 5997 | if (mres < -(INT64)0x80000000 || mres > (INT64)0x7fffffff) |
| 5998 | mres = (mres < 0) ? 0x80000000 : 0x7fffffff; |
| 5999 | if (OVERFLOW_SUB(src2,src4,ares)) |
| 6000 | ares = ((INT32)src2 < 0) ? 0x80000000 : 0x7fffffff; |
| 6001 | } |
| 6002 | IREG((op >> 23) & 1) = mres; |
| 6003 | IREG(((op >> 22) & 1) | 2) = ares; |
| 6004 | UPDATE_DEF(); |
| 6005 | } |
| 6006 | |
| 6007 | /*-----------------------------------------------------*/ |
| 6008 | |
| 6009 | void tms3203x_device::stfstf(UINT32 op) |
| 6010 | { |
| 6011 | DECLARE_DEF; |
| 6012 | WMEM(INDIRECT_1_DEF(op, op >> 8), FP2LONG((op >> 16) & 7)); |
| 6013 | WMEM(INDIRECT_1(op, op), FP2LONG((op >> 22) & 7)); |
| 6014 | UPDATE_DEF(); |
| 6015 | } |
| 6016 | |
| 6017 | void tms3203x_device::stisti(UINT32 op) |
| 6018 | { |
| 6019 | DECLARE_DEF; |
| 6020 | WMEM(INDIRECT_1_DEF(op, op >> 8), IREG((op >> 16) & 7)); |
| 6021 | WMEM(INDIRECT_1(op, op), IREG((op >> 22) & 7)); |
| 6022 | UPDATE_DEF(); |
| 6023 | } |
| 6024 | |
| 6025 | /*-----------------------------------------------------*/ |
| 6026 | |
| 6027 | void tms3203x_device::ldfldf(UINT32 op) |
| 6028 | { |
| 6029 | DECLARE_DEF; |
| 6030 | UINT32 res; |
| 6031 | int dreg; |
| 6032 | |
| 6033 | res = RMEM(INDIRECT_1_DEF(op, op >> 8)); |
| 6034 | dreg = (op >> 19) & 7; |
| 6035 | LONG2FP(dreg, res); |
| 6036 | res = RMEM(INDIRECT_1(op, op)); |
| 6037 | dreg = (op >> 22) & 7; |
| 6038 | LONG2FP(dreg, res); |
| 6039 | UPDATE_DEF(); |
| 6040 | } |
| 6041 | |
| 6042 | void tms3203x_device::ldildi(UINT32 op) |
| 6043 | { |
| 6044 | DECLARE_DEF; |
| 6045 | IREG((op >> 19) & 7) = RMEM(INDIRECT_1_DEF(op, op >> 8)); |
| 6046 | IREG((op >> 22) & 7) = RMEM(INDIRECT_1(op, op)); |
| 6047 | UPDATE_DEF(); |
| 6048 | } |
| 6049 | |
| 6050 | /*-----------------------------------------------------*/ |
| 6051 | |
| 6052 | // src2 = ind(op) |
| 6053 | // dst2 = ind(op >> 8) |
| 6054 | // sreg3 = ((op >> 16) & 7) |
| 6055 | // sreg1 = ((op >> 19) & 7) |
| 6056 | // dreg1 = ((op >> 22) & 7) |
| 6057 | |
| 6058 | void tms3203x_device::absfstf(UINT32 op) |
| 6059 | { |
| 6060 | DECLARE_DEF; |
| 6061 | UINT32 src3 = FP2LONG((op >> 16) & 7); |
| 6062 | UINT32 src2 = RMEM(INDIRECT_1_DEF(op, op)); |
| 6063 | { |
| 6064 | int dreg = (op >> 22) & 7; |
| 6065 | LONG2FP(TMR_TEMP1, src2); |
| 6066 | ABSF(dreg, TMR_TEMP1); |
| 6067 | } |
| 6068 | WMEM(INDIRECT_1(op, op >> 8), src3); |
| 6069 | UPDATE_DEF(); |
| 6070 | } |
| 6071 | |
| 6072 | void tms3203x_device::absisti(UINT32 op) |
| 6073 | { |
| 6074 | DECLARE_DEF; |
| 6075 | UINT32 src3 = IREG((op >> 16) & 7); |
| 6076 | UINT32 src2 = RMEM(INDIRECT_1_DEF(op, op)); |
| 6077 | { |
| 6078 | int dreg = (op >> 22) & 7; |
| 6079 | ABSI(dreg, src2); |
| 6080 | } |
| 6081 | WMEM(INDIRECT_1(op, op >> 8), src3); |
| 6082 | UPDATE_DEF(); |
| 6083 | } |
| 6084 | |
| 6085 | void tms3203x_device::addf3stf(UINT32 op) |
| 6086 | { |
| 6087 | DECLARE_DEF; |
| 6088 | UINT32 src3 = FP2LONG((op >> 16) & 7); |
| 6089 | UINT32 src2 = RMEM(INDIRECT_1_DEF(op, op)); |
| 6090 | { |
| 6091 | LONG2FP(TMR_TEMP1, src2); |
| 6092 | addf(m_r[(op >> 22) & 7], m_r[(op >> 19) & 7], m_r[TMR_TEMP1]); |
| 6093 | } |
| 6094 | WMEM(INDIRECT_1(op, op >> 8), src3); |
| 6095 | UPDATE_DEF(); |
| 6096 | } |
| 6097 | |
| 6098 | void tms3203x_device::addi3sti(UINT32 op) |
| 6099 | { |
| 6100 | DECLARE_DEF; |
| 6101 | UINT32 src3 = IREG((op >> 16) & 7); |
| 6102 | UINT32 src2 = RMEM(INDIRECT_1_DEF(op, op)); |
| 6103 | { |
| 6104 | int dreg = (op >> 22) & 7; |
| 6105 | UINT32 src1 = IREG((op >> 19) & 7); |
| 6106 | ADDI(dreg, src1, src2); |
| 6107 | } |
| 6108 | WMEM(INDIRECT_1(op, op >> 8), src3); |
| 6109 | UPDATE_DEF(); |
| 6110 | } |
| 6111 | |
| 6112 | void tms3203x_device::and3sti(UINT32 op) |
| 6113 | { |
| 6114 | DECLARE_DEF; |
| 6115 | UINT32 src3 = IREG((op >> 16) & 7); |
| 6116 | UINT32 src2 = RMEM(INDIRECT_1_DEF(op, op)); |
| 6117 | { |
| 6118 | int dreg = (op >> 22) & 7; |
| 6119 | UINT32 src1 = IREG((op >> 19) & 7); |
| 6120 | AND(dreg, src1, src2); |
| 6121 | } |
| 6122 | WMEM(INDIRECT_1(op, op >> 8), src3); |
| 6123 | UPDATE_DEF(); |
| 6124 | } |
| 6125 | |
| 6126 | void tms3203x_device::ash3sti(UINT32 op) |
| 6127 | { |
| 6128 | DECLARE_DEF; |
| 6129 | UINT32 src3 = IREG((op >> 16) & 7); |
| 6130 | UINT32 src2 = RMEM(INDIRECT_1_DEF(op, op)); |
| 6131 | { |
| 6132 | int dreg = (op >> 22) & 7; |
| 6133 | UINT32 count = IREG((op >> 19) & 7); |
| 6134 | ASH(dreg, src2, count); |
| 6135 | } |
| 6136 | WMEM(INDIRECT_1(op, op >> 8), src3); |
| 6137 | UPDATE_DEF(); |
| 6138 | } |
| 6139 | |
| 6140 | void tms3203x_device::fixsti(UINT32 op) |
| 6141 | { |
| 6142 | DECLARE_DEF; |
| 6143 | UINT32 src3 = IREG((op >> 16) & 7); |
| 6144 | UINT32 src2 = RMEM(INDIRECT_1_DEF(op, op)); |
| 6145 | { |
| 6146 | int dreg = (op >> 22) & 7; |
| 6147 | LONG2FP(dreg, src2); |
| 6148 | float2int(m_r[dreg], 1); |
| 6149 | } |
| 6150 | WMEM(INDIRECT_1(op, op >> 8), src3); |
| 6151 | UPDATE_DEF(); |
| 6152 | } |
| 6153 | |
| 6154 | void tms3203x_device::floatstf(UINT32 op) |
| 6155 | { |
| 6156 | DECLARE_DEF; |
| 6157 | UINT32 src3 = FP2LONG((op >> 16) & 7); |
| 6158 | UINT32 src2 = RMEM(INDIRECT_1_DEF(op, op)); |
| 6159 | { |
| 6160 | int dreg = (op >> 22) & 7; |
| 6161 | IREG(dreg) = src2; |
| 6162 | int2float(m_r[dreg]); |
| 6163 | } |
| 6164 | WMEM(INDIRECT_1(op, op >> 8), src3); |
| 6165 | UPDATE_DEF(); |
| 6166 | } |
| 6167 | |
| 6168 | void tms3203x_device::ldfstf(UINT32 op) |
| 6169 | { |
| 6170 | DECLARE_DEF; |
| 6171 | UINT32 src3 = FP2LONG((op >> 16) & 7); |
| 6172 | UINT32 src2 = RMEM(INDIRECT_1_DEF(op, op)); |
| 6173 | { |
| 6174 | int dreg = (op >> 22) & 7; |
| 6175 | LONG2FP(dreg, src2); |
| 6176 | } |
| 6177 | WMEM(INDIRECT_1(op, op >> 8), src3); |
| 6178 | UPDATE_DEF(); |
| 6179 | } |
| 6180 | |
| 6181 | void tms3203x_device::ldisti(UINT32 op) |
| 6182 | { |
| 6183 | DECLARE_DEF; |
| 6184 | UINT32 src3 = IREG((op >> 16) & 7); |
| 6185 | UINT32 src2 = RMEM(INDIRECT_1_DEF(op, op)); |
| 6186 | IREG((op >> 22) & 7) = src2; |
| 6187 | WMEM(INDIRECT_1(op, op >> 8), src3); |
| 6188 | UPDATE_DEF(); |
| 6189 | } |
| 6190 | |
| 6191 | void tms3203x_device::lsh3sti(UINT32 op) |
| 6192 | { |
| 6193 | DECLARE_DEF; |
| 6194 | UINT32 src3 = IREG((op >> 16) & 7); |
| 6195 | UINT32 src2 = RMEM(INDIRECT_1_DEF(op, op)); |
| 6196 | { |
| 6197 | int dreg = (op >> 22) & 7; |
| 6198 | UINT32 count = IREG((op >> 19) & 7); |
| 6199 | LSH(dreg, src2, count); |
| 6200 | } |
| 6201 | WMEM(INDIRECT_1(op, op >> 8), src3); |
| 6202 | UPDATE_DEF(); |
| 6203 | } |
| 6204 | |
| 6205 | void tms3203x_device::mpyf3stf(UINT32 op) |
| 6206 | { |
| 6207 | DECLARE_DEF; |
| 6208 | UINT32 src3 = FP2LONG((op >> 16) & 7); |
| 6209 | UINT32 src2 = RMEM(INDIRECT_1_DEF(op, op)); |
| 6210 | { |
| 6211 | LONG2FP(TMR_TEMP1, src2); |
| 6212 | mpyf(m_r[(op >> 22) & 7], m_r[(op >> 19) & 7], m_r[TMR_TEMP1]); |
| 6213 | } |
| 6214 | WMEM(INDIRECT_1(op, op >> 8), src3); |
| 6215 | UPDATE_DEF(); |
| 6216 | } |
| 6217 | |
| 6218 | void tms3203x_device::mpyi3sti(UINT32 op) |
| 6219 | { |
| 6220 | DECLARE_DEF; |
| 6221 | UINT32 src3 = IREG((op >> 16) & 7); |
| 6222 | UINT32 src2 = RMEM(INDIRECT_1_DEF(op, op)); |
| 6223 | { |
| 6224 | int dreg = (op >> 22) & 7; |
| 6225 | UINT32 src1 = IREG((op >> 19) & 7); |
| 6226 | MPYI(dreg, src1, src2); |
| 6227 | } |
| 6228 | WMEM(INDIRECT_1(op, op >> 8), src3); |
| 6229 | UPDATE_DEF(); |
| 6230 | } |
| 6231 | |
| 6232 | void tms3203x_device::negfstf(UINT32 op) |
| 6233 | { |
| 6234 | DECLARE_DEF; |
| 6235 | UINT32 src3 = FP2LONG((op >> 16) & 7); |
| 6236 | UINT32 src2 = RMEM(INDIRECT_1_DEF(op, op)); |
| 6237 | { |
| 6238 | LONG2FP(TMR_TEMP1, src2); |
| 6239 | negf(m_r[(op >> 22) & 7], m_r[TMR_TEMP1]); |
| 6240 | } |
| 6241 | WMEM(INDIRECT_1(op, op >> 8), src3); |
| 6242 | UPDATE_DEF(); |
| 6243 | } |
| 6244 | |
| 6245 | void tms3203x_device::negisti(UINT32 op) |
| 6246 | { |
| 6247 | DECLARE_DEF; |
| 6248 | UINT32 src3 = IREG((op >> 16) & 7); |
| 6249 | UINT32 src2 = RMEM(INDIRECT_1_DEF(op, op)); |
| 6250 | { |
| 6251 | int dreg = (op >> 22) & 7; |
| 6252 | NEGI(dreg, src2); |
| 6253 | } |
| 6254 | WMEM(INDIRECT_1(op, op >> 8), src3); |
| 6255 | UPDATE_DEF(); |
| 6256 | } |
| 6257 | |
| 6258 | void tms3203x_device::notsti(UINT32 op) |
| 6259 | { |
| 6260 | DECLARE_DEF; |
| 6261 | UINT32 src3 = IREG((op >> 16) & 7); |
| 6262 | UINT32 src2 = RMEM(INDIRECT_1_DEF(op, op)); |
| 6263 | { |
| 6264 | int dreg = (op >> 22) & 7; |
| 6265 | NOT(dreg, src2); |
| 6266 | } |
| 6267 | WMEM(INDIRECT_1(op, op >> 8), src3); |
| 6268 | UPDATE_DEF(); |
| 6269 | } |
| 6270 | |
| 6271 | void tms3203x_device::or3sti(UINT32 op) |
| 6272 | { |
| 6273 | DECLARE_DEF; |
| 6274 | UINT32 src3 = IREG((op >> 16) & 7); |
| 6275 | UINT32 src2 = RMEM(INDIRECT_1_DEF(op, op)); |
| 6276 | { |
| 6277 | int dreg = (op >> 22) & 7; |
| 6278 | UINT32 src1 = IREG((op >> 19) & 7); |
| 6279 | OR(dreg, src1, src2); |
| 6280 | } |
| 6281 | WMEM(INDIRECT_1(op, op >> 8), src3); |
| 6282 | UPDATE_DEF(); |
| 6283 | } |
| 6284 | |
| 6285 | void tms3203x_device::subf3stf(UINT32 op) |
| 6286 | { |
| 6287 | DECLARE_DEF; |
| 6288 | UINT32 src3 = FP2LONG((op >> 16) & 7); |
| 6289 | UINT32 src2 = RMEM(INDIRECT_1_DEF(op, op)); |
| 6290 | { |
| 6291 | LONG2FP(TMR_TEMP1, src2); |
| 6292 | subf(m_r[(op >> 22) & 7], m_r[TMR_TEMP1], m_r[(op >> 19) & 7]); |
| 6293 | } |
| 6294 | WMEM(INDIRECT_1(op, op >> 8), src3); |
| 6295 | UPDATE_DEF(); |
| 6296 | } |
| 6297 | |
| 6298 | void tms3203x_device::subi3sti(UINT32 op) |
| 6299 | { |
| 6300 | DECLARE_DEF; |
| 6301 | UINT32 src3 = IREG((op >> 16) & 7); |
| 6302 | UINT32 src2 = RMEM(INDIRECT_1_DEF(op, op)); |
| 6303 | { |
| 6304 | int dreg = (op >> 22) & 7; |
| 6305 | UINT32 src1 = IREG((op >> 19) & 7); |
| 6306 | SUBI(dreg, src2, src1); |
| 6307 | } |
| 6308 | WMEM(INDIRECT_1(op, op >> 8), src3); |
| 6309 | UPDATE_DEF(); |
| 6310 | } |
| 6311 | |
| 6312 | void tms3203x_device::xor3sti(UINT32 op) |
| 6313 | { |
| 6314 | DECLARE_DEF; |
| 6315 | UINT32 src3 = IREG((op >> 16) & 7); |
| 6316 | UINT32 src2 = RMEM(INDIRECT_1_DEF(op, op)); |
| 6317 | { |
| 6318 | int dreg = (op >> 22) & 7; |
| 6319 | UINT32 src1 = IREG((op >> 19) & 7); |
| 6320 | XOR(dreg, src1, src2); |
| 6321 | } |
| 6322 | WMEM(INDIRECT_1(op, op >> 8), src3); |
| 6323 | UPDATE_DEF(); |
| 6324 | } |
| 6325 | |
| 6326 | |
| 6327 | //************************************************************************** |
| 6328 | // FUNCTION TABLE |
| 6329 | //************************************************************************** |
| 6330 | |
| 6331 | UINT32 (tms3203x_device::*const tms3203x_device::s_indirect_d[0x20])(UINT32, UINT8) = |
| 6332 | { |
| 6333 | &tms3203x_device::mod00_d, &tms3203x_device::mod01_d, &tms3203x_device::mod02_d, &tms3203x_device::mod03_d, |
| 6334 | &tms3203x_device::mod04_d, &tms3203x_device::mod05_d, &tms3203x_device::mod06_d, &tms3203x_device::mod07_d, |
| 6335 | &tms3203x_device::mod08, &tms3203x_device::mod09, &tms3203x_device::mod0a, &tms3203x_device::mod0b, |
| 6336 | &tms3203x_device::mod0c, &tms3203x_device::mod0d, &tms3203x_device::mod0e, &tms3203x_device::mod0f, |
| 6337 | &tms3203x_device::mod10, &tms3203x_device::mod11, &tms3203x_device::mod12, &tms3203x_device::mod13, |
| 6338 | &tms3203x_device::mod14, &tms3203x_device::mod15, &tms3203x_device::mod16, &tms3203x_device::mod17, |
| 6339 | &tms3203x_device::mod18, &tms3203x_device::mod19, &tms3203x_device::modillegal, &tms3203x_device::modillegal, |
| 6340 | &tms3203x_device::modillegal, &tms3203x_device::modillegal, &tms3203x_device::modillegal, &tms3203x_device::modillegal |
| 6341 | }; |
| 6342 | |
| 6343 | |
| 6344 | UINT32 (tms3203x_device::*const tms3203x_device::s_indirect_1[0x20])(UINT32, UINT8) = |
| 6345 | { |
| 6346 | &tms3203x_device::mod00_1, &tms3203x_device::mod01_1, &tms3203x_device::mod02_1, &tms3203x_device::mod03_1, |
| 6347 | &tms3203x_device::mod04_1, &tms3203x_device::mod05_1, &tms3203x_device::mod06_1, &tms3203x_device::mod07_1, |
| 6348 | &tms3203x_device::mod08, &tms3203x_device::mod09, &tms3203x_device::mod0a, &tms3203x_device::mod0b, |
| 6349 | &tms3203x_device::mod0c, &tms3203x_device::mod0d, &tms3203x_device::mod0e, &tms3203x_device::mod0f, |
| 6350 | &tms3203x_device::mod10, &tms3203x_device::mod11, &tms3203x_device::mod12, &tms3203x_device::mod13, |
| 6351 | &tms3203x_device::mod14, &tms3203x_device::mod15, &tms3203x_device::mod16, &tms3203x_device::mod17, |
| 6352 | &tms3203x_device::mod18, &tms3203x_device::mod19, &tms3203x_device::modillegal, &tms3203x_device::modillegal, |
| 6353 | &tms3203x_device::modillegal, &tms3203x_device::modillegal, &tms3203x_device::modillegal, &tms3203x_device::modillegal |
| 6354 | }; |
| 6355 | |
| 6356 | |
| 6357 | UINT32 (tms3203x_device::*const tms3203x_device::s_indirect_1_def[0x20])(UINT32, UINT8, UINT32 *&) = |
| 6358 | { |
| 6359 | &tms3203x_device::mod00_1_def, &tms3203x_device::mod01_1_def, &tms3203x_device::mod02_1_def, &tms3203x_device::mod03_1_def, |
| 6360 | &tms3203x_device::mod04_1_def, &tms3203x_device::mod05_1_def, &tms3203x_device::mod06_1_def, &tms3203x_device::mod07_1_def, |
| 6361 | &tms3203x_device::mod08_def, &tms3203x_device::mod09_def, &tms3203x_device::mod0a_def, &tms3203x_device::mod0b_def, |
| 6362 | &tms3203x_device::mod0c_def, &tms3203x_device::mod0d_def, &tms3203x_device::mod0e_def, &tms3203x_device::mod0f_def, |
| 6363 | &tms3203x_device::mod10_def, &tms3203x_device::mod11_def, &tms3203x_device::mod12_def, &tms3203x_device::mod13_def, |
| 6364 | &tms3203x_device::mod14_def, &tms3203x_device::mod15_def, &tms3203x_device::mod16_def, &tms3203x_device::mod17_def, |
| 6365 | &tms3203x_device::mod18_def, &tms3203x_device::mod19_def, &tms3203x_device::modillegal_def,&tms3203x_device::modillegal_def, |
| 6366 | &tms3203x_device::modillegal_def,&tms3203x_device::modillegal_def,&tms3203x_device::modillegal_def,&tms3203x_device::modillegal_def |
| 6367 | }; |
| 6368 | |
| 6369 | void (tms3203x_device::*const tms3203x_device::s_tms32031ops[])(UINT32 op) = |
| 6370 | { |
| 6371 | &tms3203x_device::absf_reg, &tms3203x_device::absf_dir, &tms3203x_device::absf_ind, &tms3203x_device::absf_imm, // 0x00 |
| 6372 | &tms3203x_device::absi_reg, &tms3203x_device::absi_dir, &tms3203x_device::absi_ind, &tms3203x_device::absi_imm, |
| 6373 | &tms3203x_device::addc_reg, &tms3203x_device::addc_dir, &tms3203x_device::addc_ind, &tms3203x_device::addc_imm, |
| 6374 | &tms3203x_device::addf_reg, &tms3203x_device::addf_dir, &tms3203x_device::addf_ind, &tms3203x_device::addf_imm, |
| 6375 | &tms3203x_device::addi_reg, &tms3203x_device::addi_dir, &tms3203x_device::addi_ind, &tms3203x_device::addi_imm, |
| 6376 | &tms3203x_device::and_reg, &tms3203x_device::and_dir, &tms3203x_device::and_ind, &tms3203x_device::and_imm, |
| 6377 | &tms3203x_device::andn_reg, &tms3203x_device::andn_dir, &tms3203x_device::andn_ind, &tms3203x_device::andn_imm, |
| 6378 | &tms3203x_device::ash_reg, &tms3203x_device::ash_dir, &tms3203x_device::ash_ind, &tms3203x_device::ash_imm, |
| 6379 | &tms3203x_device::cmpf_reg, &tms3203x_device::cmpf_dir, &tms3203x_device::cmpf_ind, &tms3203x_device::cmpf_imm, // 0x08 |
| 6380 | &tms3203x_device::cmpi_reg, &tms3203x_device::cmpi_dir, &tms3203x_device::cmpi_ind, &tms3203x_device::cmpi_imm, |
| 6381 | &tms3203x_device::fix_reg, &tms3203x_device::fix_dir, &tms3203x_device::fix_ind, &tms3203x_device::fix_imm, |
| 6382 | &tms3203x_device::float_reg, &tms3203x_device::float_dir, &tms3203x_device::float_ind, &tms3203x_device::float_imm, |
| 6383 | &tms3203x_device::idle, &tms3203x_device::idle, &tms3203x_device::idle, &tms3203x_device::idle, |
| 6384 | &tms3203x_device::lde_reg, &tms3203x_device::lde_dir, &tms3203x_device::lde_ind, &tms3203x_device::lde_imm, |
| 6385 | &tms3203x_device::ldf_reg, &tms3203x_device::ldf_dir, &tms3203x_device::ldf_ind, &tms3203x_device::ldf_imm, |
| 6386 | &tms3203x_device::illegal, &tms3203x_device::ldfi_dir, &tms3203x_device::ldfi_ind, &tms3203x_device::illegal, |
| 6387 | &tms3203x_device::ldi_reg, &tms3203x_device::ldi_dir, &tms3203x_device::ldi_ind, &tms3203x_device::ldi_imm, // 0x10 |
| 6388 | &tms3203x_device::illegal, &tms3203x_device::ldii_dir, &tms3203x_device::ldii_ind, &tms3203x_device::illegal, |
| 6389 | &tms3203x_device::ldm_reg, &tms3203x_device::ldm_dir, &tms3203x_device::ldm_ind, &tms3203x_device::ldm_imm, |
| 6390 | &tms3203x_device::lsh_reg, &tms3203x_device::lsh_dir, &tms3203x_device::lsh_ind, &tms3203x_device::lsh_imm, |
| 6391 | &tms3203x_device::mpyf_reg, &tms3203x_device::mpyf_dir, &tms3203x_device::mpyf_ind, &tms3203x_device::mpyf_imm, |
| 6392 | &tms3203x_device::mpyi_reg, &tms3203x_device::mpyi_dir, &tms3203x_device::mpyi_ind, &tms3203x_device::mpyi_imm, |
| 6393 | &tms3203x_device::negb_reg, &tms3203x_device::negb_dir, &tms3203x_device::negb_ind, &tms3203x_device::negb_imm, |
| 6394 | &tms3203x_device::negf_reg, &tms3203x_device::negf_dir, &tms3203x_device::negf_ind, &tms3203x_device::negf_imm, |
| 6395 | &tms3203x_device::negi_reg, &tms3203x_device::negi_dir, &tms3203x_device::negi_ind, &tms3203x_device::negi_imm, // 0x18 |
| 6396 | &tms3203x_device::nop_reg, &tms3203x_device::illegal, &tms3203x_device::nop_ind, &tms3203x_device::illegal, |
| 6397 | &tms3203x_device::norm_reg, &tms3203x_device::norm_dir, &tms3203x_device::norm_ind, &tms3203x_device::norm_imm, |
| 6398 | &tms3203x_device::not_reg, &tms3203x_device::not_dir, &tms3203x_device::not_ind, &tms3203x_device::not_imm, |
| 6399 | &tms3203x_device::illegal, &tms3203x_device::pop, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6400 | &tms3203x_device::illegal, &tms3203x_device::popf, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6401 | &tms3203x_device::illegal, &tms3203x_device::push, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6402 | &tms3203x_device::illegal, &tms3203x_device::pushf, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6403 | &tms3203x_device::or_reg, &tms3203x_device::or_dir, &tms3203x_device::or_ind, &tms3203x_device::or_imm, // 0x20 |
| 6404 | &tms3203x_device::maxspeed, &tms3203x_device::maxspeed, &tms3203x_device::maxspeed, &tms3203x_device::maxspeed, |
| 6405 | &tms3203x_device::rnd_reg, &tms3203x_device::rnd_dir, &tms3203x_device::rnd_ind, &tms3203x_device::rnd_imm, |
| 6406 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::rol, |
| 6407 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::rolc, |
| 6408 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::ror, |
| 6409 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::rorc, |
| 6410 | &tms3203x_device::rtps_reg, &tms3203x_device::rtps_dir, &tms3203x_device::rtps_ind, &tms3203x_device::rtps_imm, |
| 6411 | &tms3203x_device::illegal, &tms3203x_device::stf_dir, &tms3203x_device::stf_ind, &tms3203x_device::illegal, // 0x28 |
| 6412 | &tms3203x_device::illegal, &tms3203x_device::stfi_dir, &tms3203x_device::stfi_ind, &tms3203x_device::illegal, |
| 6413 | &tms3203x_device::illegal, &tms3203x_device::sti_dir, &tms3203x_device::sti_ind, &tms3203x_device::illegal, |
| 6414 | &tms3203x_device::illegal, &tms3203x_device::stii_dir, &tms3203x_device::stii_ind, &tms3203x_device::illegal, |
| 6415 | &tms3203x_device::sigi, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6416 | &tms3203x_device::subb_reg, &tms3203x_device::subb_dir, &tms3203x_device::subb_ind, &tms3203x_device::subb_imm, |
| 6417 | &tms3203x_device::subc_reg, &tms3203x_device::subc_dir, &tms3203x_device::subc_ind, &tms3203x_device::subc_imm, |
| 6418 | &tms3203x_device::subf_reg, &tms3203x_device::subf_dir, &tms3203x_device::subf_ind, &tms3203x_device::subf_imm, |
| 6419 | &tms3203x_device::subi_reg, &tms3203x_device::subi_dir, &tms3203x_device::subi_ind, &tms3203x_device::subi_imm, // 0x30 |
| 6420 | &tms3203x_device::subrb_reg, &tms3203x_device::subrb_dir, &tms3203x_device::subrb_ind, &tms3203x_device::subrb_imm, |
| 6421 | &tms3203x_device::subrf_reg, &tms3203x_device::subrf_dir, &tms3203x_device::subrf_ind, &tms3203x_device::subrf_imm, |
| 6422 | &tms3203x_device::subri_reg, &tms3203x_device::subri_dir, &tms3203x_device::subri_ind, &tms3203x_device::subri_imm, |
| 6423 | &tms3203x_device::tstb_reg, &tms3203x_device::tstb_dir, &tms3203x_device::tstb_ind, &tms3203x_device::tstb_imm, |
| 6424 | &tms3203x_device::xor_reg, &tms3203x_device::xor_dir, &tms3203x_device::xor_ind, &tms3203x_device::xor_imm, |
| 6425 | &tms3203x_device::illegal, &tms3203x_device::iack_dir, &tms3203x_device::iack_ind, &tms3203x_device::illegal, |
| 6426 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6427 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, // 0x38 |
| 6428 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6429 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6430 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6431 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6432 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6433 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6434 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6435 | |
| 6436 | &tms3203x_device::addc3_regreg, &tms3203x_device::addc3_indreg, &tms3203x_device::addc3_regind, &tms3203x_device::addc3_indind, // 0x40 |
| 6437 | &tms3203x_device::addf3_regreg, &tms3203x_device::addf3_indreg, &tms3203x_device::addf3_regind, &tms3203x_device::addf3_indind, |
| 6438 | &tms3203x_device::addi3_regreg, &tms3203x_device::addi3_indreg, &tms3203x_device::addi3_regind, &tms3203x_device::addi3_indind, |
| 6439 | &tms3203x_device::and3_regreg, &tms3203x_device::and3_indreg, &tms3203x_device::and3_regind, &tms3203x_device::and3_indind, |
| 6440 | &tms3203x_device::andn3_regreg, &tms3203x_device::andn3_indreg, &tms3203x_device::andn3_regind, &tms3203x_device::andn3_indind, |
| 6441 | &tms3203x_device::ash3_regreg, &tms3203x_device::ash3_indreg, &tms3203x_device::ash3_regind, &tms3203x_device::ash3_indind, |
| 6442 | &tms3203x_device::cmpf3_regreg, &tms3203x_device::cmpf3_indreg, &tms3203x_device::cmpf3_regind, &tms3203x_device::cmpf3_indind, |
| 6443 | &tms3203x_device::cmpi3_regreg, &tms3203x_device::cmpi3_indreg, &tms3203x_device::cmpi3_regind, &tms3203x_device::cmpi3_indind, |
| 6444 | &tms3203x_device::lsh3_regreg, &tms3203x_device::lsh3_indreg, &tms3203x_device::lsh3_regind, &tms3203x_device::lsh3_indind, // 0x48 |
| 6445 | &tms3203x_device::mpyf3_regreg, &tms3203x_device::mpyf3_indreg, &tms3203x_device::mpyf3_regind, &tms3203x_device::mpyf3_indind, |
| 6446 | &tms3203x_device::mpyi3_regreg, &tms3203x_device::mpyi3_indreg, &tms3203x_device::mpyi3_regind, &tms3203x_device::mpyi3_indind, |
| 6447 | &tms3203x_device::or3_regreg, &tms3203x_device::or3_indreg, &tms3203x_device::or3_regind, &tms3203x_device::or3_indind, |
| 6448 | &tms3203x_device::subb3_regreg, &tms3203x_device::subb3_indreg, &tms3203x_device::subb3_regind, &tms3203x_device::subb3_indind, |
| 6449 | &tms3203x_device::subf3_regreg, &tms3203x_device::subf3_indreg, &tms3203x_device::subf3_regind, &tms3203x_device::subf3_indind, |
| 6450 | &tms3203x_device::subi3_regreg, &tms3203x_device::subi3_indreg, &tms3203x_device::subi3_regind, &tms3203x_device::subi3_indind, |
| 6451 | &tms3203x_device::tstb3_regreg, &tms3203x_device::tstb3_indreg, &tms3203x_device::tstb3_regind, &tms3203x_device::tstb3_indind, |
| 6452 | &tms3203x_device::xor3_regreg, &tms3203x_device::xor3_indreg, &tms3203x_device::xor3_regind, &tms3203x_device::xor3_indind, // 0x50 |
| 6453 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6454 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6455 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6456 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6457 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6458 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6459 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6460 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, // 0x58 |
| 6461 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6462 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6463 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6464 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6465 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6466 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6467 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6468 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, // 0x60 |
| 6469 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6470 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6471 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6472 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6473 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6474 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6475 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6476 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, // 0x68 |
| 6477 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6478 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6479 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6480 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6481 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6482 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6483 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6484 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, // 0x70 |
| 6485 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6486 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6487 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6488 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6489 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6490 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6491 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6492 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, // 0x78 |
| 6493 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6494 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6495 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6496 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6497 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6498 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6499 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6500 | |
| 6501 | &tms3203x_device::ldfu_reg, &tms3203x_device::ldfu_dir, &tms3203x_device::ldfu_ind, &tms3203x_device::ldfu_imm, // 0x80 |
| 6502 | &tms3203x_device::ldflo_reg, &tms3203x_device::ldflo_dir, &tms3203x_device::ldflo_ind, &tms3203x_device::ldflo_imm, |
| 6503 | &tms3203x_device::ldfls_reg, &tms3203x_device::ldfls_dir, &tms3203x_device::ldfls_ind, &tms3203x_device::ldfls_imm, |
| 6504 | &tms3203x_device::ldfhi_reg, &tms3203x_device::ldfhi_dir, &tms3203x_device::ldfhi_ind, &tms3203x_device::ldfhi_imm, |
| 6505 | &tms3203x_device::ldfhs_reg, &tms3203x_device::ldfhs_dir, &tms3203x_device::ldfhs_ind, &tms3203x_device::ldfhs_imm, |
| 6506 | &tms3203x_device::ldfeq_reg, &tms3203x_device::ldfeq_dir, &tms3203x_device::ldfeq_ind, &tms3203x_device::ldfeq_imm, |
| 6507 | &tms3203x_device::ldfne_reg, &tms3203x_device::ldfne_dir, &tms3203x_device::ldfne_ind, &tms3203x_device::ldfne_imm, |
| 6508 | &tms3203x_device::ldflt_reg, &tms3203x_device::ldflt_dir, &tms3203x_device::ldflt_ind, &tms3203x_device::ldflt_imm, |
| 6509 | &tms3203x_device::ldfle_reg, &tms3203x_device::ldfle_dir, &tms3203x_device::ldfle_ind, &tms3203x_device::ldfle_imm, // 0x88 |
| 6510 | &tms3203x_device::ldfgt_reg, &tms3203x_device::ldfgt_dir, &tms3203x_device::ldfgt_ind, &tms3203x_device::ldfgt_imm, |
| 6511 | &tms3203x_device::ldfge_reg, &tms3203x_device::ldfge_dir, &tms3203x_device::ldfge_ind, &tms3203x_device::ldfge_imm, |
| 6512 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6513 | &tms3203x_device::ldfnv_reg, &tms3203x_device::ldfnv_dir, &tms3203x_device::ldfnv_ind, &tms3203x_device::ldfnv_imm, |
| 6514 | &tms3203x_device::ldfv_reg, &tms3203x_device::ldfv_dir, &tms3203x_device::ldfv_ind, &tms3203x_device::ldfv_imm, |
| 6515 | &tms3203x_device::ldfnuf_reg, &tms3203x_device::ldfnuf_dir, &tms3203x_device::ldfnuf_ind, &tms3203x_device::ldfnuf_imm, |
| 6516 | &tms3203x_device::ldfuf_reg, &tms3203x_device::ldfuf_dir, &tms3203x_device::ldfuf_ind, &tms3203x_device::ldfuf_imm, |
| 6517 | &tms3203x_device::ldfnlv_reg, &tms3203x_device::ldfnlv_dir, &tms3203x_device::ldfnlv_ind, &tms3203x_device::ldfnlv_imm, // 0x90 |
| 6518 | &tms3203x_device::ldflv_reg, &tms3203x_device::ldflv_dir, &tms3203x_device::ldflv_ind, &tms3203x_device::ldflv_imm, |
| 6519 | &tms3203x_device::ldfnluf_reg, &tms3203x_device::ldfnluf_dir, &tms3203x_device::ldfnluf_ind, &tms3203x_device::ldfnluf_imm, |
| 6520 | &tms3203x_device::ldfluf_reg, &tms3203x_device::ldfluf_dir, &tms3203x_device::ldfluf_ind, &tms3203x_device::ldfluf_imm, |
| 6521 | &tms3203x_device::ldfzuf_reg, &tms3203x_device::ldfzuf_dir, &tms3203x_device::ldfzuf_ind, &tms3203x_device::ldfzuf_imm, |
| 6522 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6523 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6524 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6525 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, // 0x98 |
| 6526 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6527 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6528 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6529 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6530 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6531 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6532 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6533 | &tms3203x_device::ldiu_reg, &tms3203x_device::ldiu_dir, &tms3203x_device::ldiu_ind, &tms3203x_device::ldiu_imm, // 0xa0 |
| 6534 | &tms3203x_device::ldilo_reg, &tms3203x_device::ldilo_dir, &tms3203x_device::ldilo_ind, &tms3203x_device::ldilo_imm, |
| 6535 | &tms3203x_device::ldils_reg, &tms3203x_device::ldils_dir, &tms3203x_device::ldils_ind, &tms3203x_device::ldils_imm, |
| 6536 | &tms3203x_device::ldihi_reg, &tms3203x_device::ldihi_dir, &tms3203x_device::ldihi_ind, &tms3203x_device::ldihi_imm, |
| 6537 | &tms3203x_device::ldihs_reg, &tms3203x_device::ldihs_dir, &tms3203x_device::ldihs_ind, &tms3203x_device::ldihs_imm, |
| 6538 | &tms3203x_device::ldieq_reg, &tms3203x_device::ldieq_dir, &tms3203x_device::ldieq_ind, &tms3203x_device::ldieq_imm, |
| 6539 | &tms3203x_device::ldine_reg, &tms3203x_device::ldine_dir, &tms3203x_device::ldine_ind, &tms3203x_device::ldine_imm, |
| 6540 | &tms3203x_device::ldilt_reg, &tms3203x_device::ldilt_dir, &tms3203x_device::ldilt_ind, &tms3203x_device::ldilt_imm, |
| 6541 | &tms3203x_device::ldile_reg, &tms3203x_device::ldile_dir, &tms3203x_device::ldile_ind, &tms3203x_device::ldile_imm, // 0xa8 |
| 6542 | &tms3203x_device::ldigt_reg, &tms3203x_device::ldigt_dir, &tms3203x_device::ldigt_ind, &tms3203x_device::ldigt_imm, |
| 6543 | &tms3203x_device::ldige_reg, &tms3203x_device::ldige_dir, &tms3203x_device::ldige_ind, &tms3203x_device::ldige_imm, |
| 6544 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6545 | &tms3203x_device::ldinv_reg, &tms3203x_device::ldinv_dir, &tms3203x_device::ldinv_ind, &tms3203x_device::ldinv_imm, |
| 6546 | &tms3203x_device::ldiv_reg, &tms3203x_device::ldiv_dir, &tms3203x_device::ldiv_ind, &tms3203x_device::ldiv_imm, |
| 6547 | &tms3203x_device::ldinuf_reg, &tms3203x_device::ldinuf_dir, &tms3203x_device::ldinuf_ind, &tms3203x_device::ldinuf_imm, |
| 6548 | &tms3203x_device::ldiuf_reg, &tms3203x_device::ldiuf_dir, &tms3203x_device::ldiuf_ind, &tms3203x_device::ldiuf_imm, |
| 6549 | &tms3203x_device::ldinlv_reg, &tms3203x_device::ldinlv_dir, &tms3203x_device::ldinlv_ind, &tms3203x_device::ldinlv_imm, // 0xb0 |
| 6550 | &tms3203x_device::ldilv_reg, &tms3203x_device::ldilv_dir, &tms3203x_device::ldilv_ind, &tms3203x_device::ldilv_imm, |
| 6551 | &tms3203x_device::ldinluf_reg, &tms3203x_device::ldinluf_dir, &tms3203x_device::ldinluf_ind, &tms3203x_device::ldinluf_imm, |
| 6552 | &tms3203x_device::ldiluf_reg, &tms3203x_device::ldiluf_dir, &tms3203x_device::ldiluf_ind, &tms3203x_device::ldiluf_imm, |
| 6553 | &tms3203x_device::ldizuf_reg, &tms3203x_device::ldizuf_dir, &tms3203x_device::ldizuf_ind, &tms3203x_device::ldizuf_imm, |
| 6554 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6555 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6556 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6557 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, // 0xb8 |
| 6558 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6559 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6560 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6561 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6562 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6563 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6564 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6565 | |
| 6566 | &tms3203x_device::br_imm, &tms3203x_device::br_imm, &tms3203x_device::br_imm, &tms3203x_device::br_imm, // 0xc0 |
| 6567 | &tms3203x_device::br_imm, &tms3203x_device::br_imm, &tms3203x_device::br_imm, &tms3203x_device::br_imm, |
| 6568 | &tms3203x_device::brd_imm, &tms3203x_device::brd_imm, &tms3203x_device::brd_imm, &tms3203x_device::brd_imm, |
| 6569 | &tms3203x_device::brd_imm, &tms3203x_device::brd_imm, &tms3203x_device::brd_imm, &tms3203x_device::brd_imm, |
| 6570 | &tms3203x_device::call_imm, &tms3203x_device::call_imm, &tms3203x_device::call_imm, &tms3203x_device::call_imm, |
| 6571 | &tms3203x_device::call_imm, &tms3203x_device::call_imm, &tms3203x_device::call_imm, &tms3203x_device::call_imm, |
| 6572 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6573 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6574 | &tms3203x_device::rptb_imm, &tms3203x_device::rptb_imm, &tms3203x_device::rptb_imm, &tms3203x_device::rptb_imm, // 0xc8 |
| 6575 | &tms3203x_device::rptb_imm, &tms3203x_device::rptb_imm, &tms3203x_device::rptb_imm, &tms3203x_device::rptb_imm, |
| 6576 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6577 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6578 | &tms3203x_device::swi, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6579 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6580 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6581 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6582 | &tms3203x_device::brc_reg, &tms3203x_device::brcd_reg, &tms3203x_device::illegal, &tms3203x_device::illegal, // 0xd0 |
| 6583 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6584 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6585 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6586 | &tms3203x_device::brc_imm, &tms3203x_device::brcd_imm, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6587 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6588 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6589 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6590 | &tms3203x_device::dbc_reg, &tms3203x_device::dbcd_reg, &tms3203x_device::dbc_reg, &tms3203x_device::dbcd_reg, // 0xd8 |
| 6591 | &tms3203x_device::dbc_reg, &tms3203x_device::dbcd_reg, &tms3203x_device::dbc_reg, &tms3203x_device::dbcd_reg, |
| 6592 | &tms3203x_device::dbc_reg, &tms3203x_device::dbcd_reg, &tms3203x_device::dbc_reg, &tms3203x_device::dbcd_reg, |
| 6593 | &tms3203x_device::dbc_reg, &tms3203x_device::dbcd_reg, &tms3203x_device::dbc_reg, &tms3203x_device::dbcd_reg, |
| 6594 | &tms3203x_device::dbc_imm, &tms3203x_device::dbcd_imm, &tms3203x_device::dbc_imm, &tms3203x_device::dbcd_imm, |
| 6595 | &tms3203x_device::dbc_imm, &tms3203x_device::dbcd_imm, &tms3203x_device::dbc_imm, &tms3203x_device::dbcd_imm, |
| 6596 | &tms3203x_device::dbc_imm, &tms3203x_device::dbcd_imm, &tms3203x_device::dbc_imm, &tms3203x_device::dbcd_imm, |
| 6597 | &tms3203x_device::dbc_imm, &tms3203x_device::dbcd_imm, &tms3203x_device::dbc_imm, &tms3203x_device::dbcd_imm, |
| 6598 | &tms3203x_device::callc_reg, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, // 0xe0 |
| 6599 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6600 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6601 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6602 | &tms3203x_device::callc_imm, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6603 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6604 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6605 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6606 | &tms3203x_device::trapc, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, // 0xe8 |
| 6607 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6608 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6609 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6610 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6611 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6612 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6613 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6614 | &tms3203x_device::retic_reg, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, // 0xf0 |
| 6615 | &tms3203x_device::retsc_reg, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6616 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6617 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6618 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6619 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6620 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6621 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6622 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, // 0xf8 |
| 6623 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6624 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6625 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6626 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6627 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6628 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6629 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6630 | |
| 6631 | &tms3203x_device::mpyaddf_0, &tms3203x_device::mpyaddf_0, &tms3203x_device::mpyaddf_0, &tms3203x_device::mpyaddf_0, // 0x100 |
| 6632 | &tms3203x_device::mpyaddf_0, &tms3203x_device::mpyaddf_0, &tms3203x_device::mpyaddf_0, &tms3203x_device::mpyaddf_0, |
| 6633 | &tms3203x_device::mpyaddf_1, &tms3203x_device::mpyaddf_1, &tms3203x_device::mpyaddf_1, &tms3203x_device::mpyaddf_1, |
| 6634 | &tms3203x_device::mpyaddf_1, &tms3203x_device::mpyaddf_1, &tms3203x_device::mpyaddf_1, &tms3203x_device::mpyaddf_1, |
| 6635 | &tms3203x_device::mpyaddf_2, &tms3203x_device::mpyaddf_2, &tms3203x_device::mpyaddf_2, &tms3203x_device::mpyaddf_2, |
| 6636 | &tms3203x_device::mpyaddf_2, &tms3203x_device::mpyaddf_2, &tms3203x_device::mpyaddf_2, &tms3203x_device::mpyaddf_2, |
| 6637 | &tms3203x_device::mpyaddf_3, &tms3203x_device::mpyaddf_3, &tms3203x_device::mpyaddf_3, &tms3203x_device::mpyaddf_3, |
| 6638 | &tms3203x_device::mpyaddf_3, &tms3203x_device::mpyaddf_3, &tms3203x_device::mpyaddf_3, &tms3203x_device::mpyaddf_3, |
| 6639 | &tms3203x_device::mpysubf_0, &tms3203x_device::mpysubf_0, &tms3203x_device::mpysubf_0, &tms3203x_device::mpysubf_0, // 0x108 |
| 6640 | &tms3203x_device::mpysubf_0, &tms3203x_device::mpysubf_0, &tms3203x_device::mpysubf_0, &tms3203x_device::mpysubf_0, |
| 6641 | &tms3203x_device::mpysubf_1, &tms3203x_device::mpysubf_1, &tms3203x_device::mpysubf_1, &tms3203x_device::mpysubf_1, |
| 6642 | &tms3203x_device::mpysubf_1, &tms3203x_device::mpysubf_1, &tms3203x_device::mpysubf_1, &tms3203x_device::mpysubf_1, |
| 6643 | &tms3203x_device::mpysubf_2, &tms3203x_device::mpysubf_2, &tms3203x_device::mpysubf_2, &tms3203x_device::mpysubf_2, |
| 6644 | &tms3203x_device::mpysubf_2, &tms3203x_device::mpysubf_2, &tms3203x_device::mpysubf_2, &tms3203x_device::mpysubf_2, |
| 6645 | &tms3203x_device::mpysubf_3, &tms3203x_device::mpysubf_3, &tms3203x_device::mpysubf_3, &tms3203x_device::mpysubf_3, |
| 6646 | &tms3203x_device::mpysubf_3, &tms3203x_device::mpysubf_3, &tms3203x_device::mpysubf_3, &tms3203x_device::mpysubf_3, |
| 6647 | &tms3203x_device::mpyaddi_0, &tms3203x_device::mpyaddi_0, &tms3203x_device::mpyaddi_0, &tms3203x_device::mpyaddi_0, // 0x110 |
| 6648 | &tms3203x_device::mpyaddi_0, &tms3203x_device::mpyaddi_0, &tms3203x_device::mpyaddi_0, &tms3203x_device::mpyaddi_0, |
| 6649 | &tms3203x_device::mpyaddi_1, &tms3203x_device::mpyaddi_1, &tms3203x_device::mpyaddi_1, &tms3203x_device::mpyaddi_1, |
| 6650 | &tms3203x_device::mpyaddi_1, &tms3203x_device::mpyaddi_1, &tms3203x_device::mpyaddi_1, &tms3203x_device::mpyaddi_1, |
| 6651 | &tms3203x_device::mpyaddi_2, &tms3203x_device::mpyaddi_2, &tms3203x_device::mpyaddi_2, &tms3203x_device::mpyaddi_2, |
| 6652 | &tms3203x_device::mpyaddi_2, &tms3203x_device::mpyaddi_2, &tms3203x_device::mpyaddi_2, &tms3203x_device::mpyaddi_2, |
| 6653 | &tms3203x_device::mpyaddi_3, &tms3203x_device::mpyaddi_3, &tms3203x_device::mpyaddi_3, &tms3203x_device::mpyaddi_3, |
| 6654 | &tms3203x_device::mpyaddi_3, &tms3203x_device::mpyaddi_3, &tms3203x_device::mpyaddi_3, &tms3203x_device::mpyaddi_3, |
| 6655 | &tms3203x_device::mpysubi_0, &tms3203x_device::mpysubi_0, &tms3203x_device::mpysubi_0, &tms3203x_device::mpysubi_0, // 0x118 |
| 6656 | &tms3203x_device::mpysubi_0, &tms3203x_device::mpysubi_0, &tms3203x_device::mpysubi_0, &tms3203x_device::mpysubi_0, |
| 6657 | &tms3203x_device::mpysubi_1, &tms3203x_device::mpysubi_1, &tms3203x_device::mpysubi_1, &tms3203x_device::mpysubi_1, |
| 6658 | &tms3203x_device::mpysubi_1, &tms3203x_device::mpysubi_1, &tms3203x_device::mpysubi_1, &tms3203x_device::mpysubi_1, |
| 6659 | &tms3203x_device::mpysubi_2, &tms3203x_device::mpysubi_2, &tms3203x_device::mpysubi_2, &tms3203x_device::mpysubi_2, |
| 6660 | &tms3203x_device::mpysubi_2, &tms3203x_device::mpysubi_2, &tms3203x_device::mpysubi_2, &tms3203x_device::mpysubi_2, |
| 6661 | &tms3203x_device::mpysubi_3, &tms3203x_device::mpysubi_3, &tms3203x_device::mpysubi_3, &tms3203x_device::mpysubi_3, |
| 6662 | &tms3203x_device::mpysubi_3, &tms3203x_device::mpysubi_3, &tms3203x_device::mpysubi_3, &tms3203x_device::mpysubi_3, |
| 6663 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, // 0x120 |
| 6664 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6665 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6666 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6667 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6668 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6669 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6670 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6671 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, // 0x128 |
| 6672 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6673 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6674 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6675 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6676 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6677 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6678 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6679 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, // 0x130 |
| 6680 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6681 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6682 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6683 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6684 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6685 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6686 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6687 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, // 0x138 |
| 6688 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6689 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6690 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6691 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6692 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6693 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6694 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6695 | |
| 6696 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, // 0x140 |
| 6697 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6698 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6699 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6700 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6701 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6702 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6703 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6704 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, // 0x148 |
| 6705 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6706 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6707 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6708 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6709 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6710 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6711 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6712 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, // 0x150 |
| 6713 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6714 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6715 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6716 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6717 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6718 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6719 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6720 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, // 0x158 |
| 6721 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6722 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6723 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6724 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6725 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6726 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6727 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6728 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, // 0x160 |
| 6729 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6730 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6731 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6732 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6733 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6734 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6735 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6736 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, // 0x168 |
| 6737 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6738 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6739 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6740 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6741 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6742 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6743 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6744 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, // 0x170 |
| 6745 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6746 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6747 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6748 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6749 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6750 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6751 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6752 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, // 0x178 |
| 6753 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6754 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6755 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6756 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6757 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6758 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6759 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6760 | |
| 6761 | &tms3203x_device::stfstf, &tms3203x_device::stfstf, &tms3203x_device::stfstf, &tms3203x_device::stfstf, // 0x180 |
| 6762 | &tms3203x_device::stfstf, &tms3203x_device::stfstf, &tms3203x_device::stfstf, &tms3203x_device::stfstf, |
| 6763 | &tms3203x_device::stfstf, &tms3203x_device::stfstf, &tms3203x_device::stfstf, &tms3203x_device::stfstf, |
| 6764 | &tms3203x_device::stfstf, &tms3203x_device::stfstf, &tms3203x_device::stfstf, &tms3203x_device::stfstf, |
| 6765 | &tms3203x_device::stisti, &tms3203x_device::stisti, &tms3203x_device::stisti, &tms3203x_device::stisti, |
| 6766 | &tms3203x_device::stisti, &tms3203x_device::stisti, &tms3203x_device::stisti, &tms3203x_device::stisti, |
| 6767 | &tms3203x_device::stisti, &tms3203x_device::stisti, &tms3203x_device::stisti, &tms3203x_device::stisti, |
| 6768 | &tms3203x_device::stisti, &tms3203x_device::stisti, &tms3203x_device::stisti, &tms3203x_device::stisti, |
| 6769 | &tms3203x_device::ldfldf, &tms3203x_device::ldfldf, &tms3203x_device::ldfldf, &tms3203x_device::ldfldf, // 0x188 |
| 6770 | &tms3203x_device::ldfldf, &tms3203x_device::ldfldf, &tms3203x_device::ldfldf, &tms3203x_device::ldfldf, |
| 6771 | &tms3203x_device::ldfldf, &tms3203x_device::ldfldf, &tms3203x_device::ldfldf, &tms3203x_device::ldfldf, |
| 6772 | &tms3203x_device::ldfldf, &tms3203x_device::ldfldf, &tms3203x_device::ldfldf, &tms3203x_device::ldfldf, |
| 6773 | &tms3203x_device::ldildi, &tms3203x_device::ldildi, &tms3203x_device::ldildi, &tms3203x_device::ldildi, |
| 6774 | &tms3203x_device::ldildi, &tms3203x_device::ldildi, &tms3203x_device::ldildi, &tms3203x_device::ldildi, |
| 6775 | &tms3203x_device::ldildi, &tms3203x_device::ldildi, &tms3203x_device::ldildi, &tms3203x_device::ldildi, |
| 6776 | &tms3203x_device::ldildi, &tms3203x_device::ldildi, &tms3203x_device::ldildi, &tms3203x_device::ldildi, |
| 6777 | &tms3203x_device::absfstf, &tms3203x_device::absfstf, &tms3203x_device::absfstf, &tms3203x_device::absfstf, // 0x190 |
| 6778 | &tms3203x_device::absfstf, &tms3203x_device::absfstf, &tms3203x_device::absfstf, &tms3203x_device::absfstf, |
| 6779 | &tms3203x_device::absfstf, &tms3203x_device::absfstf, &tms3203x_device::absfstf, &tms3203x_device::absfstf, |
| 6780 | &tms3203x_device::absfstf, &tms3203x_device::absfstf, &tms3203x_device::absfstf, &tms3203x_device::absfstf, |
| 6781 | &tms3203x_device::absisti, &tms3203x_device::absisti, &tms3203x_device::absisti, &tms3203x_device::absisti, |
| 6782 | &tms3203x_device::absisti, &tms3203x_device::absisti, &tms3203x_device::absisti, &tms3203x_device::absisti, |
| 6783 | &tms3203x_device::absisti, &tms3203x_device::absisti, &tms3203x_device::absisti, &tms3203x_device::absisti, |
| 6784 | &tms3203x_device::absisti, &tms3203x_device::absisti, &tms3203x_device::absisti, &tms3203x_device::absisti, |
| 6785 | &tms3203x_device::addf3stf, &tms3203x_device::addf3stf, &tms3203x_device::addf3stf, &tms3203x_device::addf3stf, // 0x198 |
| 6786 | &tms3203x_device::addf3stf, &tms3203x_device::addf3stf, &tms3203x_device::addf3stf, &tms3203x_device::addf3stf, |
| 6787 | &tms3203x_device::addf3stf, &tms3203x_device::addf3stf, &tms3203x_device::addf3stf, &tms3203x_device::addf3stf, |
| 6788 | &tms3203x_device::addf3stf, &tms3203x_device::addf3stf, &tms3203x_device::addf3stf, &tms3203x_device::addf3stf, |
| 6789 | &tms3203x_device::addi3sti, &tms3203x_device::addi3sti, &tms3203x_device::addi3sti, &tms3203x_device::addi3sti, |
| 6790 | &tms3203x_device::addi3sti, &tms3203x_device::addi3sti, &tms3203x_device::addi3sti, &tms3203x_device::addi3sti, |
| 6791 | &tms3203x_device::addi3sti, &tms3203x_device::addi3sti, &tms3203x_device::addi3sti, &tms3203x_device::addi3sti, |
| 6792 | &tms3203x_device::addi3sti, &tms3203x_device::addi3sti, &tms3203x_device::addi3sti, &tms3203x_device::addi3sti, |
| 6793 | &tms3203x_device::and3sti, &tms3203x_device::and3sti, &tms3203x_device::and3sti, &tms3203x_device::and3sti, // 0x1a0 |
| 6794 | &tms3203x_device::and3sti, &tms3203x_device::and3sti, &tms3203x_device::and3sti, &tms3203x_device::and3sti, |
| 6795 | &tms3203x_device::and3sti, &tms3203x_device::and3sti, &tms3203x_device::and3sti, &tms3203x_device::and3sti, |
| 6796 | &tms3203x_device::and3sti, &tms3203x_device::and3sti, &tms3203x_device::and3sti, &tms3203x_device::and3sti, |
| 6797 | &tms3203x_device::ash3sti, &tms3203x_device::ash3sti, &tms3203x_device::ash3sti, &tms3203x_device::ash3sti, |
| 6798 | &tms3203x_device::ash3sti, &tms3203x_device::ash3sti, &tms3203x_device::ash3sti, &tms3203x_device::ash3sti, |
| 6799 | &tms3203x_device::ash3sti, &tms3203x_device::ash3sti, &tms3203x_device::ash3sti, &tms3203x_device::ash3sti, |
| 6800 | &tms3203x_device::ash3sti, &tms3203x_device::ash3sti, &tms3203x_device::ash3sti, &tms3203x_device::ash3sti, |
| 6801 | &tms3203x_device::fixsti, &tms3203x_device::fixsti, &tms3203x_device::fixsti, &tms3203x_device::fixsti, // 0x1a8 |
| 6802 | &tms3203x_device::fixsti, &tms3203x_device::fixsti, &tms3203x_device::fixsti, &tms3203x_device::fixsti, |
| 6803 | &tms3203x_device::fixsti, &tms3203x_device::fixsti, &tms3203x_device::fixsti, &tms3203x_device::fixsti, |
| 6804 | &tms3203x_device::fixsti, &tms3203x_device::fixsti, &tms3203x_device::fixsti, &tms3203x_device::fixsti, |
| 6805 | &tms3203x_device::floatstf, &tms3203x_device::floatstf, &tms3203x_device::floatstf, &tms3203x_device::floatstf, |
| 6806 | &tms3203x_device::floatstf, &tms3203x_device::floatstf, &tms3203x_device::floatstf, &tms3203x_device::floatstf, |
| 6807 | &tms3203x_device::floatstf, &tms3203x_device::floatstf, &tms3203x_device::floatstf, &tms3203x_device::floatstf, |
| 6808 | &tms3203x_device::floatstf, &tms3203x_device::floatstf, &tms3203x_device::floatstf, &tms3203x_device::floatstf, |
| 6809 | &tms3203x_device::ldfstf, &tms3203x_device::ldfstf, &tms3203x_device::ldfstf, &tms3203x_device::ldfstf, // 0x1b0 |
| 6810 | &tms3203x_device::ldfstf, &tms3203x_device::ldfstf, &tms3203x_device::ldfstf, &tms3203x_device::ldfstf, |
| 6811 | &tms3203x_device::ldfstf, &tms3203x_device::ldfstf, &tms3203x_device::ldfstf, &tms3203x_device::ldfstf, |
| 6812 | &tms3203x_device::ldfstf, &tms3203x_device::ldfstf, &tms3203x_device::ldfstf, &tms3203x_device::ldfstf, |
| 6813 | &tms3203x_device::ldisti, &tms3203x_device::ldisti, &tms3203x_device::ldisti, &tms3203x_device::ldisti, |
| 6814 | &tms3203x_device::ldisti, &tms3203x_device::ldisti, &tms3203x_device::ldisti, &tms3203x_device::ldisti, |
| 6815 | &tms3203x_device::ldisti, &tms3203x_device::ldisti, &tms3203x_device::ldisti, &tms3203x_device::ldisti, |
| 6816 | &tms3203x_device::ldisti, &tms3203x_device::ldisti, &tms3203x_device::ldisti, &tms3203x_device::ldisti, |
| 6817 | &tms3203x_device::lsh3sti, &tms3203x_device::lsh3sti, &tms3203x_device::lsh3sti, &tms3203x_device::lsh3sti, // 0x1b8 |
| 6818 | &tms3203x_device::lsh3sti, &tms3203x_device::lsh3sti, &tms3203x_device::lsh3sti, &tms3203x_device::lsh3sti, |
| 6819 | &tms3203x_device::lsh3sti, &tms3203x_device::lsh3sti, &tms3203x_device::lsh3sti, &tms3203x_device::lsh3sti, |
| 6820 | &tms3203x_device::lsh3sti, &tms3203x_device::lsh3sti, &tms3203x_device::lsh3sti, &tms3203x_device::lsh3sti, |
| 6821 | &tms3203x_device::mpyf3stf, &tms3203x_device::mpyf3stf, &tms3203x_device::mpyf3stf, &tms3203x_device::mpyf3stf, |
| 6822 | &tms3203x_device::mpyf3stf, &tms3203x_device::mpyf3stf, &tms3203x_device::mpyf3stf, &tms3203x_device::mpyf3stf, |
| 6823 | &tms3203x_device::mpyf3stf, &tms3203x_device::mpyf3stf, &tms3203x_device::mpyf3stf, &tms3203x_device::mpyf3stf, |
| 6824 | &tms3203x_device::mpyf3stf, &tms3203x_device::mpyf3stf, &tms3203x_device::mpyf3stf, &tms3203x_device::mpyf3stf, |
| 6825 | |
| 6826 | &tms3203x_device::mpyi3sti, &tms3203x_device::mpyi3sti, &tms3203x_device::mpyi3sti, &tms3203x_device::mpyi3sti, // 0x1c0 |
| 6827 | &tms3203x_device::mpyi3sti, &tms3203x_device::mpyi3sti, &tms3203x_device::mpyi3sti, &tms3203x_device::mpyi3sti, |
| 6828 | &tms3203x_device::mpyi3sti, &tms3203x_device::mpyi3sti, &tms3203x_device::mpyi3sti, &tms3203x_device::mpyi3sti, |
| 6829 | &tms3203x_device::mpyi3sti, &tms3203x_device::mpyi3sti, &tms3203x_device::mpyi3sti, &tms3203x_device::mpyi3sti, |
| 6830 | &tms3203x_device::negfstf, &tms3203x_device::negfstf, &tms3203x_device::negfstf, &tms3203x_device::negfstf, |
| 6831 | &tms3203x_device::negfstf, &tms3203x_device::negfstf, &tms3203x_device::negfstf, &tms3203x_device::negfstf, |
| 6832 | &tms3203x_device::negfstf, &tms3203x_device::negfstf, &tms3203x_device::negfstf, &tms3203x_device::negfstf, |
| 6833 | &tms3203x_device::negfstf, &tms3203x_device::negfstf, &tms3203x_device::negfstf, &tms3203x_device::negfstf, |
| 6834 | &tms3203x_device::negisti, &tms3203x_device::negisti, &tms3203x_device::negisti, &tms3203x_device::negisti, // 0x1c8 |
| 6835 | &tms3203x_device::negisti, &tms3203x_device::negisti, &tms3203x_device::negisti, &tms3203x_device::negisti, |
| 6836 | &tms3203x_device::negisti, &tms3203x_device::negisti, &tms3203x_device::negisti, &tms3203x_device::negisti, |
| 6837 | &tms3203x_device::negisti, &tms3203x_device::negisti, &tms3203x_device::negisti, &tms3203x_device::negisti, |
| 6838 | &tms3203x_device::notsti, &tms3203x_device::notsti, &tms3203x_device::notsti, &tms3203x_device::notsti, |
| 6839 | &tms3203x_device::notsti, &tms3203x_device::notsti, &tms3203x_device::notsti, &tms3203x_device::notsti, |
| 6840 | &tms3203x_device::notsti, &tms3203x_device::notsti, &tms3203x_device::notsti, &tms3203x_device::notsti, |
| 6841 | &tms3203x_device::notsti, &tms3203x_device::notsti, &tms3203x_device::notsti, &tms3203x_device::notsti, |
| 6842 | &tms3203x_device::or3sti, &tms3203x_device::or3sti, &tms3203x_device::or3sti, &tms3203x_device::or3sti, // 0x1d0 |
| 6843 | &tms3203x_device::or3sti, &tms3203x_device::or3sti, &tms3203x_device::or3sti, &tms3203x_device::or3sti, |
| 6844 | &tms3203x_device::or3sti, &tms3203x_device::or3sti, &tms3203x_device::or3sti, &tms3203x_device::or3sti, |
| 6845 | &tms3203x_device::or3sti, &tms3203x_device::or3sti, &tms3203x_device::or3sti, &tms3203x_device::or3sti, |
| 6846 | &tms3203x_device::subf3stf, &tms3203x_device::subf3stf, &tms3203x_device::subf3stf, &tms3203x_device::subf3stf, |
| 6847 | &tms3203x_device::subf3stf, &tms3203x_device::subf3stf, &tms3203x_device::subf3stf, &tms3203x_device::subf3stf, |
| 6848 | &tms3203x_device::subf3stf, &tms3203x_device::subf3stf, &tms3203x_device::subf3stf, &tms3203x_device::subf3stf, |
| 6849 | &tms3203x_device::subf3stf, &tms3203x_device::subf3stf, &tms3203x_device::subf3stf, &tms3203x_device::subf3stf, |
| 6850 | &tms3203x_device::subi3sti, &tms3203x_device::subi3sti, &tms3203x_device::subi3sti, &tms3203x_device::subi3sti, // 0x1d8 |
| 6851 | &tms3203x_device::subi3sti, &tms3203x_device::subi3sti, &tms3203x_device::subi3sti, &tms3203x_device::subi3sti, |
| 6852 | &tms3203x_device::subi3sti, &tms3203x_device::subi3sti, &tms3203x_device::subi3sti, &tms3203x_device::subi3sti, |
| 6853 | &tms3203x_device::subi3sti, &tms3203x_device::subi3sti, &tms3203x_device::subi3sti, &tms3203x_device::subi3sti, |
| 6854 | &tms3203x_device::xor3sti, &tms3203x_device::xor3sti, &tms3203x_device::xor3sti, &tms3203x_device::xor3sti, |
| 6855 | &tms3203x_device::xor3sti, &tms3203x_device::xor3sti, &tms3203x_device::xor3sti, &tms3203x_device::xor3sti, |
| 6856 | &tms3203x_device::xor3sti, &tms3203x_device::xor3sti, &tms3203x_device::xor3sti, &tms3203x_device::xor3sti, |
| 6857 | &tms3203x_device::xor3sti, &tms3203x_device::xor3sti, &tms3203x_device::xor3sti, &tms3203x_device::xor3sti, |
| 6858 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, // 0x1e0 |
| 6859 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6860 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6861 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6862 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6863 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6864 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6865 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6866 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, // 0x1e8 |
| 6867 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6868 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6869 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6870 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6871 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6872 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6873 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6874 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, // 0x1f0 |
| 6875 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6876 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6877 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6878 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6879 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6880 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6881 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6882 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, // 0x1f8 |
| 6883 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6884 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6885 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6886 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6887 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6888 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, |
| 6889 | &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal, &tms3203x_device::illegal |
| 6890 | }; |
trunk/src/devices/cpu/tms34010/34010gfx.cpp
| r250221 | r250222 | |
|---|
| 1 | | // license:BSD-3-Clause |
| 2 | | // copyright-holders:Alex Pasadyn,Zsolt Vasvari,Aaron Giles |
| 3 | | /*************************************************************************** |
| 4 | | |
| 5 | | TMS34010: Portable Texas Instruments TMS34010 emulator |
| 6 | | |
| 7 | | Copyright Alex Pasadyn/Zsolt Vasvari |
| 8 | | Parts based on code by Aaron Giles |
| 9 | | |
| 10 | | ***************************************************************************/ |
| 11 | | |
| 12 | | #ifndef RECURSIVE_INCLUDE |
| 13 | | |
| 14 | | |
| 15 | | #define LOG_GFX_OPS 0 |
| 16 | | #define LOGGFX(x) do { if (LOG_GFX_OPS && machine().input().code_pressed(KEYCODE_L)) logerror x; } while (0) |
| 17 | | |
| 18 | | |
| 19 | | /* Graphics Instructions */ |
| 20 | | |
| 21 | | void tms340x0_device::line(UINT16 op) |
| 22 | | { |
| 23 | | if (!P_FLAG()) |
| 24 | | { |
| 25 | | if (WINDOW_CHECKING() != 0 && WINDOW_CHECKING() != 3) |
| 26 | | logerror("LINE XY %08X - Window Checking Mode %d not supported\n", m_pc, WINDOW_CHECKING()); |
| 27 | | |
| 28 | | m_st |= STBIT_P; |
| 29 | | TEMP() = (op & 0x80) ? 1 : 0; /* boundary value depends on the algorithm */ |
| 30 | | LOGGFX(("%08X(%3d):LINE (%d,%d)-(%d,%d)\n", m_pc, m_screen->vpos(), DADDR_X(), DADDR_Y(), DADDR_X() + DYDX_X(), DADDR_Y() + DYDX_Y())); |
| 31 | | } |
| 32 | | |
| 33 | | if (COUNT() > 0) |
| 34 | | { |
| 35 | | INT16 x1,y1; |
| 36 | | |
| 37 | | COUNT()--; |
| 38 | | if (WINDOW_CHECKING() != 3 || |
| 39 | | (DADDR_X() >= WSTART_X() && DADDR_X() <= WEND_X() && |
| 40 | | DADDR_Y() >= WSTART_Y() && DADDR_Y() <= WEND_Y())) |
| 41 | | WPIXEL(DXYTOL(DADDR_XY()),COLOR1()); |
| 42 | | |
| 43 | | if (SADDR() >= TEMP()) |
| 44 | | { |
| 45 | | SADDR() += DYDX_Y()*2 - DYDX_X()*2; |
| 46 | | x1 = INC1_X(); |
| 47 | | y1 = INC1_Y(); |
| 48 | | } |
| 49 | | else |
| 50 | | { |
| 51 | | SADDR() += DYDX_Y()*2; |
| 52 | | x1 = INC2_X(); |
| 53 | | y1 = INC2_Y(); |
| 54 | | } |
| 55 | | DADDR_X() += x1; |
| 56 | | DADDR_Y() += y1; |
| 57 | | |
| 58 | | COUNT_UNKNOWN_CYCLES(2); |
| 59 | | m_pc -= 0x10; /* not done yet, check for interrupts and restart instruction */ |
| 60 | | return; |
| 61 | | } |
| 62 | | m_st &= ~STBIT_P; |
| 63 | | } |
| 64 | | |
| 65 | | |
| 66 | | /* |
| 67 | | cases: |
| 68 | | * window modes (0,1,2,3) |
| 69 | | * boolean/arithmetic ops (16+6) |
| 70 | | * transparency (on/off) |
| 71 | | * plane masking |
| 72 | | * directions (left->right/right->left, top->bottom/bottom->top) |
| 73 | | */ |
| 74 | | |
| 75 | | int tms340x0_device::apply_window(const char *inst_name,int srcbpp, UINT32 *srcaddr, XY *dst, int *dx, int *dy) |
| 76 | | { |
| 77 | | /* apply the window */ |
| 78 | | if (WINDOW_CHECKING() == 0) |
| 79 | | return 0; |
| 80 | | else |
| 81 | | { |
| 82 | | int sx = dst->x; |
| 83 | | int sy = dst->y; |
| 84 | | int ex = sx + *dx - 1; |
| 85 | | int ey = sy + *dy - 1; |
| 86 | | int diff, cycles = 3; |
| 87 | | |
| 88 | | if (WINDOW_CHECKING() == 2) |
| 89 | | logerror("%08x: %s apply_window window mode %d not supported!\n", pc(), inst_name, WINDOW_CHECKING()); |
| 90 | | |
| 91 | | CLR_V(); |
| 92 | | if (WINDOW_CHECKING() == 1) |
| 93 | | SET_V_LOG(1); |
| 94 | | |
| 95 | | /* clip X */ |
| 96 | | diff = WSTART_X() - sx; |
| 97 | | if (diff > 0) |
| 98 | | { |
| 99 | | if (srcaddr) |
| 100 | | *srcaddr += diff * srcbpp; |
| 101 | | sx += diff; |
| 102 | | SET_V_LOG(1); |
| 103 | | } |
| 104 | | diff = ex - WEND_X(); |
| 105 | | if (diff > 0) |
| 106 | | { |
| 107 | | ex -= diff; |
| 108 | | SET_V_LOG(1); |
| 109 | | } |
| 110 | | |
| 111 | | |
| 112 | | /* clip Y */ |
| 113 | | diff = WSTART_Y() - sy; |
| 114 | | if (diff > 0) |
| 115 | | { |
| 116 | | if (srcaddr) |
| 117 | | *srcaddr += diff * m_convsp; |
| 118 | | |
| 119 | | sy += diff; |
| 120 | | SET_V_LOG(1); |
| 121 | | } |
| 122 | | diff = ey - WEND_Y(); |
| 123 | | if (diff > 0) |
| 124 | | { |
| 125 | | ey -= diff; |
| 126 | | SET_V_LOG(1); |
| 127 | | } |
| 128 | | |
| 129 | | /* compute cycles */ |
| 130 | | if (*dx != ex - sx + 1 || *dy != ey - sy + 1) |
| 131 | | { |
| 132 | | if (dst->x != sx || dst->y != sy) |
| 133 | | cycles += 11; |
| 134 | | else |
| 135 | | cycles += 3; |
| 136 | | } |
| 137 | | else if (dst->x != sx || dst->y != sy) |
| 138 | | cycles += 7; |
| 139 | | |
| 140 | | /* update the values */ |
| 141 | | dst->x = sx; |
| 142 | | dst->y = sy; |
| 143 | | *dx = ex - sx + 1; |
| 144 | | *dy = ey - sy + 1; |
| 145 | | return cycles; |
| 146 | | } |
| 147 | | } |
| 148 | | |
| 149 | | |
| 150 | | /******************************************************************* |
| 151 | | |
| 152 | | About the timing of gfx operations: |
| 153 | | |
| 154 | | The 34010 manual lists a fairly intricate and accurate way of |
| 155 | | computing cycle timings for graphics ops. However, there are |
| 156 | | enough typos and misleading statements to make the reliability |
| 157 | | of the timing info questionable. |
| 158 | | |
| 159 | | So, to address this, here is a simplified approximate version |
| 160 | | of the timing. |
| 161 | | |
| 162 | | timing = setup + (srcwords * 2 + dstwords * gfxop) * rows |
| 163 | | |
| 164 | | Each read access takes 2 cycles. Each gfx operation has |
| 165 | | its own timing as specified in the 34010 manual. So, it's 2 |
| 166 | | cycles per read plus gfxop cycles per operation. Pretty |
| 167 | | simple, no? |
| 168 | | |
| 169 | | *******************************************************************/ |
| 170 | | |
| 171 | | int tms340x0_device::compute_fill_cycles(int left_partials, int right_partials, int full_words, int op_timing) |
| 172 | | { |
| 173 | | int dstwords; |
| 174 | | |
| 175 | | if (left_partials) full_words += 1; |
| 176 | | if (right_partials) full_words += 1; |
| 177 | | dstwords = full_words; |
| 178 | | |
| 179 | | return (dstwords * op_timing); |
| 180 | | } |
| 181 | | |
| 182 | | int tms340x0_device::compute_pixblt_cycles(int left_partials, int right_partials, int full_words, int op_timing) |
| 183 | | { |
| 184 | | int srcwords, dstwords; |
| 185 | | |
| 186 | | if (left_partials) full_words += 1; |
| 187 | | if (right_partials) full_words += 1; |
| 188 | | srcwords = full_words; |
| 189 | | dstwords = full_words; |
| 190 | | |
| 191 | | return (dstwords * op_timing + srcwords * 2) + 2; |
| 192 | | } |
| 193 | | |
| 194 | | int tms340x0_device::compute_pixblt_b_cycles(int left_partials, int right_partials, int full_words, int rows, int op_timing, int bpp) |
| 195 | | { |
| 196 | | int srcwords, dstwords; |
| 197 | | |
| 198 | | if (left_partials) full_words += 1; |
| 199 | | if (right_partials) full_words += 1; |
| 200 | | srcwords = full_words * bpp / 16; |
| 201 | | dstwords = full_words; |
| 202 | | |
| 203 | | return (dstwords * op_timing + srcwords * 2) * rows + 2; |
| 204 | | } |
| 205 | | |
| 206 | | |
| 207 | | /* Shift register handling */ |
| 208 | | void tms340x0_device::memory_w(address_space &space, offs_t offset,UINT16 data) |
| 209 | | { |
| 210 | | space.write_word(offset, data); |
| 211 | | } |
| 212 | | |
| 213 | | UINT16 tms340x0_device::memory_r(address_space &space, offs_t offset) |
| 214 | | { |
| 215 | | return space.read_word(offset); |
| 216 | | } |
| 217 | | |
| 218 | | void tms340x0_device::shiftreg_w(address_space &space, offs_t offset,UINT16 data) |
| 219 | | { |
| 220 | | if (!m_from_shiftreg_cb.isnull()) |
| 221 | | m_from_shiftreg_cb(space, (UINT32)(offset << 3) & ~15, &m_shiftreg[0]); |
| 222 | | else |
| 223 | | logerror("From ShiftReg function not set. PC = %08X\n", m_pc); |
| 224 | | } |
| 225 | | |
| 226 | | UINT16 tms340x0_device::shiftreg_r(address_space &space, offs_t offset) |
| 227 | | { |
| 228 | | if (!m_to_shiftreg_cb.isnull()) |
| 229 | | m_to_shiftreg_cb(space, (UINT32)(offset << 3) & ~15, &m_shiftreg[0]); |
| 230 | | else |
| 231 | | logerror("To ShiftReg function not set. PC = %08X\n", m_pc); |
| 232 | | return m_shiftreg[0]; |
| 233 | | } |
| 234 | | |
| 235 | | UINT16 tms340x0_device::dummy_shiftreg_r(address_space &space, offs_t offset) |
| 236 | | { |
| 237 | | return m_shiftreg[0]; |
| 238 | | } |
| 239 | | |
| 240 | | |
| 241 | | |
| 242 | | /* Pixel operations */ |
| 243 | | UINT32 tms340x0_device::pixel_op00(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return srcpix; } |
| 244 | | UINT32 tms340x0_device::pixel_op01(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return srcpix & dstpix; } |
| 245 | | UINT32 tms340x0_device::pixel_op02(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return srcpix & ~dstpix; } |
| 246 | | UINT32 tms340x0_device::pixel_op03(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return 0; } |
| 247 | | UINT32 tms340x0_device::pixel_op04(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return (srcpix | ~dstpix) & mask; } |
| 248 | | UINT32 tms340x0_device::pixel_op05(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return ~(srcpix ^ dstpix) & mask; } |
| 249 | | UINT32 tms340x0_device::pixel_op06(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return ~dstpix & mask; } |
| 250 | | UINT32 tms340x0_device::pixel_op07(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return ~(srcpix | dstpix) & mask; } |
| 251 | | UINT32 tms340x0_device::pixel_op08(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return (srcpix | dstpix) & mask; } |
| 252 | | UINT32 tms340x0_device::pixel_op09(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return dstpix & mask; } |
| 253 | | UINT32 tms340x0_device::pixel_op10(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return (srcpix ^ dstpix) & mask; } |
| 254 | | UINT32 tms340x0_device::pixel_op11(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return (~srcpix & dstpix) & mask; } |
| 255 | | UINT32 tms340x0_device::pixel_op12(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return mask; } |
| 256 | | UINT32 tms340x0_device::pixel_op13(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return (~srcpix & dstpix) & mask; } |
| 257 | | UINT32 tms340x0_device::pixel_op14(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return ~(srcpix & dstpix) & mask; } |
| 258 | | UINT32 tms340x0_device::pixel_op15(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return srcpix ^ mask; } |
| 259 | | UINT32 tms340x0_device::pixel_op16(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return (srcpix + dstpix) & mask; } |
| 260 | | UINT32 tms340x0_device::pixel_op17(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { INT32 tmp = srcpix + (dstpix & mask); return (tmp > mask) ? mask : tmp; } |
| 261 | | UINT32 tms340x0_device::pixel_op18(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return (dstpix - srcpix) & mask; } |
| 262 | | UINT32 tms340x0_device::pixel_op19(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { INT32 tmp = srcpix - (dstpix & mask); return (tmp < 0) ? 0 : tmp; } |
| 263 | | UINT32 tms340x0_device::pixel_op20(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { dstpix &= mask; return (srcpix > dstpix) ? srcpix : dstpix; } |
| 264 | | UINT32 tms340x0_device::pixel_op21(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { dstpix &= mask; return (srcpix < dstpix) ? srcpix : dstpix; } |
| 265 | | |
| 266 | | const tms340x0_device::pixel_op_func tms340x0_device::s_pixel_op_table[32] = |
| 267 | | { |
| 268 | | &tms340x0_device::pixel_op00, &tms340x0_device::pixel_op01, &tms340x0_device::pixel_op02, &tms340x0_device::pixel_op03, &tms340x0_device::pixel_op04, &tms340x0_device::pixel_op05, &tms340x0_device::pixel_op06, &tms340x0_device::pixel_op07, |
| 269 | | &tms340x0_device::pixel_op08, &tms340x0_device::pixel_op09, &tms340x0_device::pixel_op10, &tms340x0_device::pixel_op11, &tms340x0_device::pixel_op12, &tms340x0_device::pixel_op13, &tms340x0_device::pixel_op14, &tms340x0_device::pixel_op15, |
| 270 | | &tms340x0_device::pixel_op16, &tms340x0_device::pixel_op17, &tms340x0_device::pixel_op18, &tms340x0_device::pixel_op19, &tms340x0_device::pixel_op20, &tms340x0_device::pixel_op21, &tms340x0_device::pixel_op00, &tms340x0_device::pixel_op00, |
| 271 | | &tms340x0_device::pixel_op00, &tms340x0_device::pixel_op00, &tms340x0_device::pixel_op00, &tms340x0_device::pixel_op00, &tms340x0_device::pixel_op00, &tms340x0_device::pixel_op00, &tms340x0_device::pixel_op00, &tms340x0_device::pixel_op00 |
| 272 | | }; |
| 273 | | const UINT8 tms340x0_device::s_pixel_op_timing_table[33] = |
| 274 | | { |
| 275 | | 2,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,5,5,6,5,5,2,2,2,2,2,2,2,2,2,2,2 |
| 276 | | }; |
| 277 | | |
| 278 | | |
| 279 | | /* tables */ |
| 280 | | const tms340x0_device::pixblt_op_func tms340x0_device::s_pixblt_op_table[] = |
| 281 | | { |
| 282 | | &tms340x0_device::pixblt_1_op0, &tms340x0_device::pixblt_1_op0_trans, &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, |
| 283 | | &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, |
| 284 | | &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, |
| 285 | | &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, |
| 286 | | &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, |
| 287 | | &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, |
| 288 | | &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, |
| 289 | | &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, |
| 290 | | &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, |
| 291 | | &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, |
| 292 | | &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, |
| 293 | | &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, |
| 294 | | &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, |
| 295 | | &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, |
| 296 | | &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, |
| 297 | | &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, |
| 298 | | |
| 299 | | &tms340x0_device::pixblt_2_op0, &tms340x0_device::pixblt_2_op0_trans, &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, |
| 300 | | &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, |
| 301 | | &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, |
| 302 | | &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, |
| 303 | | &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, |
| 304 | | &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, |
| 305 | | &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, |
| 306 | | &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, |
| 307 | | &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, |
| 308 | | &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, |
| 309 | | &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, |
| 310 | | &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, |
| 311 | | &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, |
| 312 | | &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, |
| 313 | | &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, |
| 314 | | &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, |
| 315 | | |
| 316 | | &tms340x0_device::pixblt_4_op0, &tms340x0_device::pixblt_4_op0_trans, &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, |
| 317 | | &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, |
| 318 | | &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, |
| 319 | | &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, |
| 320 | | &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, |
| 321 | | &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, |
| 322 | | &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, |
| 323 | | &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, |
| 324 | | &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, |
| 325 | | &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, |
| 326 | | &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, |
| 327 | | &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, |
| 328 | | &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, |
| 329 | | &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, |
| 330 | | &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, |
| 331 | | &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, |
| 332 | | |
| 333 | | &tms340x0_device::pixblt_8_op0, &tms340x0_device::pixblt_8_op0_trans, &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, |
| 334 | | &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, |
| 335 | | &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, |
| 336 | | &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, |
| 337 | | &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, |
| 338 | | &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, |
| 339 | | &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, |
| 340 | | &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, |
| 341 | | &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, |
| 342 | | &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, |
| 343 | | &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, |
| 344 | | &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, |
| 345 | | &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, |
| 346 | | &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, |
| 347 | | &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, |
| 348 | | &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, |
| 349 | | |
| 350 | | &tms340x0_device::pixblt_16_op0, &tms340x0_device::pixblt_16_op0_trans, &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, |
| 351 | | &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, |
| 352 | | &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, |
| 353 | | &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, |
| 354 | | &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, |
| 355 | | &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, |
| 356 | | &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, |
| 357 | | &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, |
| 358 | | &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, |
| 359 | | &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, |
| 360 | | &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, |
| 361 | | &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, |
| 362 | | &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, |
| 363 | | &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, |
| 364 | | &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, |
| 365 | | &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans |
| 366 | | }; |
| 367 | | |
| 368 | | const tms340x0_device::pixblt_op_func tms340x0_device::s_pixblt_r_op_table[] = |
| 369 | | { |
| 370 | | &tms340x0_device::pixblt_r_1_op0, &tms340x0_device::pixblt_r_1_op0_trans, &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, |
| 371 | | &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, |
| 372 | | &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, |
| 373 | | &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, |
| 374 | | &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, |
| 375 | | &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, |
| 376 | | &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, |
| 377 | | &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, |
| 378 | | &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, |
| 379 | | &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, |
| 380 | | &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, |
| 381 | | &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, |
| 382 | | &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, |
| 383 | | &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, |
| 384 | | &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, |
| 385 | | &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, |
| 386 | | |
| 387 | | &tms340x0_device::pixblt_r_2_op0, &tms340x0_device::pixblt_r_2_op0_trans, &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, |
| 388 | | &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, |
| 389 | | &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, |
| 390 | | &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, |
| 391 | | &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, |
| 392 | | &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, |
| 393 | | &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, |
| 394 | | &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, |
| 395 | | &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, |
| 396 | | &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, |
| 397 | | &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, |
| 398 | | &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, |
| 399 | | &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, |
| 400 | | &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, |
| 401 | | &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, |
| 402 | | &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, |
| 403 | | |
| 404 | | &tms340x0_device::pixblt_r_4_op0, &tms340x0_device::pixblt_r_4_op0_trans, &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, |
| 405 | | &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, |
| 406 | | &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, |
| 407 | | &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, |
| 408 | | &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, |
| 409 | | &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, |
| 410 | | &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, |
| 411 | | &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, |
| 412 | | &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, |
| 413 | | &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, |
| 414 | | &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, |
| 415 | | &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, |
| 416 | | &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, |
| 417 | | &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, |
| 418 | | &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, |
| 419 | | &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, |
| 420 | | |
| 421 | | &tms340x0_device::pixblt_r_8_op0, &tms340x0_device::pixblt_r_8_op0_trans, &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, |
| 422 | | &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, |
| 423 | | &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, |
| 424 | | &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, |
| 425 | | &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, |
| 426 | | &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, |
| 427 | | &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, |
| 428 | | &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, |
| 429 | | &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, |
| 430 | | &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, |
| 431 | | &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, |
| 432 | | &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, |
| 433 | | &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, |
| 434 | | &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, |
| 435 | | &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, |
| 436 | | &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, |
| 437 | | |
| 438 | | &tms340x0_device::pixblt_r_16_op0,&tms340x0_device::pixblt_r_16_op0_trans, &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, |
| 439 | | &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, |
| 440 | | &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, |
| 441 | | &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, |
| 442 | | &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, |
| 443 | | &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, |
| 444 | | &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, |
| 445 | | &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, |
| 446 | | &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, |
| 447 | | &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, |
| 448 | | &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, |
| 449 | | &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, |
| 450 | | &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, |
| 451 | | &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, |
| 452 | | &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, |
| 453 | | &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans |
| 454 | | }; |
| 455 | | |
| 456 | | const tms340x0_device::pixblt_b_op_func tms340x0_device::s_pixblt_b_op_table[] = |
| 457 | | { |
| 458 | | &tms340x0_device::pixblt_b_1_op0, &tms340x0_device::pixblt_b_1_op0_trans, &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, |
| 459 | | &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, |
| 460 | | &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, |
| 461 | | &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, |
| 462 | | &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, |
| 463 | | &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, |
| 464 | | &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, |
| 465 | | &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, |
| 466 | | &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, |
| 467 | | &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, |
| 468 | | &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, |
| 469 | | &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, |
| 470 | | &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, |
| 471 | | &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, |
| 472 | | &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, |
| 473 | | &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, |
| 474 | | |
| 475 | | &tms340x0_device::pixblt_b_2_op0, &tms340x0_device::pixblt_b_2_op0_trans, &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, |
| 476 | | &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, |
| 477 | | &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, |
| 478 | | &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, |
| 479 | | &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, |
| 480 | | &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, |
| 481 | | &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, |
| 482 | | &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, |
| 483 | | &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, |
| 484 | | &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, |
| 485 | | &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, |
| 486 | | &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, |
| 487 | | &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, |
| 488 | | &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, |
| 489 | | &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, |
| 490 | | &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, |
| 491 | | |
| 492 | | &tms340x0_device::pixblt_b_4_op0, &tms340x0_device::pixblt_b_4_op0_trans, &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, |
| 493 | | &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, |
| 494 | | &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, |
| 495 | | &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, |
| 496 | | &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, |
| 497 | | &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, |
| 498 | | &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, |
| 499 | | &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, |
| 500 | | &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, |
| 501 | | &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, |
| 502 | | &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, |
| 503 | | &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, |
| 504 | | &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, |
| 505 | | &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, |
| 506 | | &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, |
| 507 | | &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, |
| 508 | | |
| 509 | | &tms340x0_device::pixblt_b_8_op0, &tms340x0_device::pixblt_b_8_op0_trans, &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, |
| 510 | | &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, |
| 511 | | &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, |
| 512 | | &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, |
| 513 | | &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, |
| 514 | | &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, |
| 515 | | &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, |
| 516 | | &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, |
| 517 | | &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, |
| 518 | | &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, |
| 519 | | &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, |
| 520 | | &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, |
| 521 | | &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, |
| 522 | | &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, |
| 523 | | &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, |
| 524 | | &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, |
| 525 | | |
| 526 | | &tms340x0_device::pixblt_b_16_op0,&tms340x0_device::pixblt_b_16_op0_trans, &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, |
| 527 | | &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, |
| 528 | | &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, |
| 529 | | &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, |
| 530 | | &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, |
| 531 | | &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, |
| 532 | | &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, |
| 533 | | &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, |
| 534 | | &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, |
| 535 | | &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, |
| 536 | | &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, |
| 537 | | &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, |
| 538 | | &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, |
| 539 | | &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, |
| 540 | | &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, |
| 541 | | &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans |
| 542 | | }; |
| 543 | | |
| 544 | | const tms340x0_device::pixblt_b_op_func tms340x0_device::s_fill_op_table[] = |
| 545 | | { |
| 546 | | &tms340x0_device::fill_1_op0, &tms340x0_device::fill_1_op0_trans, &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, |
| 547 | | &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, |
| 548 | | &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, |
| 549 | | &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, |
| 550 | | &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, |
| 551 | | &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, |
| 552 | | &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, |
| 553 | | &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, |
| 554 | | &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, |
| 555 | | &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, |
| 556 | | &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, |
| 557 | | &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, |
| 558 | | &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, |
| 559 | | &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, |
| 560 | | &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, |
| 561 | | &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, |
| 562 | | |
| 563 | | &tms340x0_device::fill_2_op0, &tms340x0_device::fill_2_op0_trans, &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, |
| 564 | | &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, |
| 565 | | &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, |
| 566 | | &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, |
| 567 | | &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, |
| 568 | | &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, |
| 569 | | &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, |
| 570 | | &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, |
| 571 | | &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, |
| 572 | | &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, |
| 573 | | &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, |
| 574 | | &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, |
| 575 | | &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, |
| 576 | | &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, |
| 577 | | &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, |
| 578 | | &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, |
| 579 | | |
| 580 | | &tms340x0_device::fill_4_op0, &tms340x0_device::fill_4_op0_trans, &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, |
| 581 | | &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, |
| 582 | | &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, |
| 583 | | &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, |
| 584 | | &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, |
| 585 | | &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, |
| 586 | | &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, |
| 587 | | &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, |
| 588 | | &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, |
| 589 | | &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, |
| 590 | | &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, |
| 591 | | &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, |
| 592 | | &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, |
| 593 | | &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, |
| 594 | | &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, |
| 595 | | &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, |
| 596 | | |
| 597 | | &tms340x0_device::fill_8_op0, &tms340x0_device::fill_8_op0_trans, &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, |
| 598 | | &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, |
| 599 | | &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, |
| 600 | | &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, |
| 601 | | &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, |
| 602 | | &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, |
| 603 | | &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, |
| 604 | | &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, |
| 605 | | &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, |
| 606 | | &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, |
| 607 | | &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, |
| 608 | | &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, |
| 609 | | &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, |
| 610 | | &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, |
| 611 | | &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, |
| 612 | | &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, |
| 613 | | |
| 614 | | &tms340x0_device::fill_16_op0, &tms340x0_device::fill_16_op0_trans, &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, |
| 615 | | &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, |
| 616 | | &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, |
| 617 | | &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, |
| 618 | | &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, |
| 619 | | &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, |
| 620 | | &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, |
| 621 | | &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, |
| 622 | | &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, |
| 623 | | &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, |
| 624 | | &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, |
| 625 | | &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, |
| 626 | | &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, |
| 627 | | &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, |
| 628 | | &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, |
| 629 | | &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans |
| 630 | | }; |
| 631 | | |
| 632 | | |
| 633 | | #define RECURSIVE_INCLUDE |
| 634 | | |
| 635 | | /* non-transparent replace ops */ |
| 636 | | #define PIXEL_OP(src, mask, pixel) pixel = pixel |
| 637 | | #define PIXEL_OP_TIMING 2 |
| 638 | | #define PIXEL_OP_REQUIRES_SOURCE 0 |
| 639 | | #define TRANSPARENCY 0 |
| 640 | | |
| 641 | | /* 1bpp cases */ |
| 642 | | #define BITS_PER_PIXEL 1 |
| 643 | | #define FUNCTION_NAME(base) base##_1_op0 |
| 644 | | #include "34010gfx.cpp" |
| 645 | | #undef FUNCTION_NAME |
| 646 | | #undef BITS_PER_PIXEL |
| 647 | | |
| 648 | | /* 2bpp cases */ |
| 649 | | #define BITS_PER_PIXEL 2 |
| 650 | | #define FUNCTION_NAME(base) base##_2_op0 |
| 651 | | #include "34010gfx.cpp" |
| 652 | | #undef FUNCTION_NAME |
| 653 | | #undef BITS_PER_PIXEL |
| 654 | | |
| 655 | | /* 4bpp cases */ |
| 656 | | #define BITS_PER_PIXEL 4 |
| 657 | | #define FUNCTION_NAME(base) base##_4_op0 |
| 658 | | #include "34010gfx.cpp" |
| 659 | | #undef FUNCTION_NAME |
| 660 | | #undef BITS_PER_PIXEL |
| 661 | | |
| 662 | | /* 8bpp cases */ |
| 663 | | #define BITS_PER_PIXEL 8 |
| 664 | | #define FUNCTION_NAME(base) base##_8_op0 |
| 665 | | #include "34010gfx.cpp" |
| 666 | | #undef FUNCTION_NAME |
| 667 | | #undef BITS_PER_PIXEL |
| 668 | | |
| 669 | | /* 16bpp cases */ |
| 670 | | #define BITS_PER_PIXEL 16 |
| 671 | | #define FUNCTION_NAME(base) base##_16_op0 |
| 672 | | #include "34010gfx.cpp" |
| 673 | | #undef FUNCTION_NAME |
| 674 | | #undef BITS_PER_PIXEL |
| 675 | | |
| 676 | | #undef TRANSPARENCY |
| 677 | | #undef PIXEL_OP_REQUIRES_SOURCE |
| 678 | | #undef PIXEL_OP_TIMING |
| 679 | | #undef PIXEL_OP |
| 680 | | |
| 681 | | |
| 682 | | #define PIXEL_OP(src, mask, pixel) pixel = (this->*m_pixel_op)(src, mask, pixel) |
| 683 | | #define PIXEL_OP_TIMING m_pixel_op_timing |
| 684 | | #define PIXEL_OP_REQUIRES_SOURCE 1 |
| 685 | | #define TRANSPARENCY 0 |
| 686 | | |
| 687 | | /* 1bpp cases */ |
| 688 | | #define BITS_PER_PIXEL 1 |
| 689 | | #define FUNCTION_NAME(base) base##_1_opx |
| 690 | | #include "34010gfx.cpp" |
| 691 | | #undef FUNCTION_NAME |
| 692 | | #undef BITS_PER_PIXEL |
| 693 | | |
| 694 | | /* 2bpp cases */ |
| 695 | | #define BITS_PER_PIXEL 2 |
| 696 | | #define FUNCTION_NAME(base) base##_2_opx |
| 697 | | #include "34010gfx.cpp" |
| 698 | | #undef FUNCTION_NAME |
| 699 | | #undef BITS_PER_PIXEL |
| 700 | | |
| 701 | | /* 4bpp cases */ |
| 702 | | #define BITS_PER_PIXEL 4 |
| 703 | | #define FUNCTION_NAME(base) base##_4_opx |
| 704 | | #include "34010gfx.cpp" |
| 705 | | #undef FUNCTION_NAME |
| 706 | | #undef BITS_PER_PIXEL |
| 707 | | |
| 708 | | /* 8bpp cases */ |
| 709 | | #define BITS_PER_PIXEL 8 |
| 710 | | #define FUNCTION_NAME(base) base##_8_opx |
| 711 | | #include "34010gfx.cpp" |
| 712 | | #undef FUNCTION_NAME |
| 713 | | #undef BITS_PER_PIXEL |
| 714 | | |
| 715 | | /* 16bpp cases */ |
| 716 | | #define BITS_PER_PIXEL 16 |
| 717 | | #define FUNCTION_NAME(base) base##_16_opx |
| 718 | | #include "34010gfx.cpp" |
| 719 | | #undef FUNCTION_NAME |
| 720 | | #undef BITS_PER_PIXEL |
| 721 | | |
| 722 | | #undef TRANSPARENCY |
| 723 | | #undef PIXEL_OP_REQUIRES_SOURCE |
| 724 | | #undef PIXEL_OP_TIMING |
| 725 | | #undef PIXEL_OP |
| 726 | | |
| 727 | | |
| 728 | | /* transparent replace ops */ |
| 729 | | #define PIXEL_OP(src, mask, pixel) pixel = pixel |
| 730 | | #define PIXEL_OP_REQUIRES_SOURCE 0 |
| 731 | | #define PIXEL_OP_TIMING 4 |
| 732 | | #define TRANSPARENCY 1 |
| 733 | | |
| 734 | | /* 1bpp cases */ |
| 735 | | #define BITS_PER_PIXEL 1 |
| 736 | | #define FUNCTION_NAME(base) base##_1_op0_trans |
| 737 | | #include "34010gfx.cpp" |
| 738 | | #undef FUNCTION_NAME |
| 739 | | #undef BITS_PER_PIXEL |
| 740 | | |
| 741 | | /* 2bpp cases */ |
| 742 | | #define BITS_PER_PIXEL 2 |
| 743 | | #define FUNCTION_NAME(base) base##_2_op0_trans |
| 744 | | #include "34010gfx.cpp" |
| 745 | | #undef FUNCTION_NAME |
| 746 | | #undef BITS_PER_PIXEL |
| 747 | | |
| 748 | | /* 4bpp cases */ |
| 749 | | #define BITS_PER_PIXEL 4 |
| 750 | | #define FUNCTION_NAME(base) base##_4_op0_trans |
| 751 | | #include "34010gfx.cpp" |
| 752 | | #undef FUNCTION_NAME |
| 753 | | #undef BITS_PER_PIXEL |
| 754 | | |
| 755 | | /* 8bpp cases */ |
| 756 | | #define BITS_PER_PIXEL 8 |
| 757 | | #define FUNCTION_NAME(base) base##_8_op0_trans |
| 758 | | #include "34010gfx.cpp" |
| 759 | | #undef FUNCTION_NAME |
| 760 | | #undef BITS_PER_PIXEL |
| 761 | | |
| 762 | | /* 16bpp cases */ |
| 763 | | #define BITS_PER_PIXEL 16 |
| 764 | | #define FUNCTION_NAME(base) base##_16_op0_trans |
| 765 | | #include "34010gfx.cpp" |
| 766 | | #undef FUNCTION_NAME |
| 767 | | #undef BITS_PER_PIXEL |
| 768 | | |
| 769 | | #undef TRANSPARENCY |
| 770 | | #undef PIXEL_OP_REQUIRES_SOURCE |
| 771 | | #undef PIXEL_OP_TIMING |
| 772 | | #undef PIXEL_OP |
| 773 | | |
| 774 | | |
| 775 | | #define PIXEL_OP(src, mask, pixel) pixel = (this->*m_pixel_op)(src, mask, pixel) |
| 776 | | #define PIXEL_OP_REQUIRES_SOURCE 1 |
| 777 | | #define PIXEL_OP_TIMING (2+m_pixel_op_timing) |
| 778 | | #define TRANSPARENCY 1 |
| 779 | | |
| 780 | | /* 1bpp cases */ |
| 781 | | #define BITS_PER_PIXEL 1 |
| 782 | | #define FUNCTION_NAME(base) base##_1_opx_trans |
| 783 | | #include "34010gfx.cpp" |
| 784 | | #undef FUNCTION_NAME |
| 785 | | #undef BITS_PER_PIXEL |
| 786 | | |
| 787 | | /* 2bpp cases */ |
| 788 | | #define BITS_PER_PIXEL 2 |
| 789 | | #define FUNCTION_NAME(base) base##_2_opx_trans |
| 790 | | #include "34010gfx.cpp" |
| 791 | | #undef FUNCTION_NAME |
| 792 | | #undef BITS_PER_PIXEL |
| 793 | | |
| 794 | | /* 4bpp cases */ |
| 795 | | #define BITS_PER_PIXEL 4 |
| 796 | | #define FUNCTION_NAME(base) base##_4_opx_trans |
| 797 | | #include "34010gfx.cpp" |
| 798 | | #undef FUNCTION_NAME |
| 799 | | #undef BITS_PER_PIXEL |
| 800 | | |
| 801 | | /* 8bpp cases */ |
| 802 | | #define BITS_PER_PIXEL 8 |
| 803 | | #define FUNCTION_NAME(base) base##_8_opx_trans |
| 804 | | #include "34010gfx.cpp" |
| 805 | | #undef FUNCTION_NAME |
| 806 | | #undef BITS_PER_PIXEL |
| 807 | | |
| 808 | | /* 16bpp cases */ |
| 809 | | #define BITS_PER_PIXEL 16 |
| 810 | | #define FUNCTION_NAME(base) base##_16_opx_trans |
| 811 | | #include "34010gfx.cpp" |
| 812 | | #undef FUNCTION_NAME |
| 813 | | #undef BITS_PER_PIXEL |
| 814 | | |
| 815 | | #undef TRANSPARENCY |
| 816 | | #undef PIXEL_OP_REQUIRES_SOURCE |
| 817 | | #undef PIXEL_OP_TIMING |
| 818 | | #undef PIXEL_OP |
| 819 | | |
| 820 | | static const UINT8 pixelsize_lookup[32] = |
| 821 | | { |
| 822 | | 0,0,1,1,2,2,2,2,3,3,3,3,3,3,3,3,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4 |
| 823 | | }; |
| 824 | | |
| 825 | | |
| 826 | | void tms340x0_device::pixblt_b_l(UINT16 op) |
| 827 | | { |
| 828 | | int psize = pixelsize_lookup[IOREG(REG_PSIZE) & 0x1f]; |
| 829 | | int trans = (IOREG(REG_CONTROL) & 0x20) >> 5; |
| 830 | | int rop = (IOREG(REG_CONTROL) >> 10) & 0x1f; |
| 831 | | int ix = trans | (rop << 1) | (psize << 6); |
| 832 | | if (!P_FLAG()) LOGGFX(("%08X(%3d):PIXBLT B,L (%dx%d) depth=%d\n", m_pc, m_screen->vpos(), DYDX_X(), DYDX_Y(), IOREG(REG_PSIZE) ? IOREG(REG_PSIZE) : 32)); |
| 833 | | m_pixel_op = s_pixel_op_table[rop]; |
| 834 | | m_pixel_op_timing = s_pixel_op_timing_table[rop]; |
| 835 | | (this->*s_pixblt_b_op_table[ix])(1); |
| 836 | | } |
| 837 | | |
| 838 | | void tms340x0_device::pixblt_b_xy(UINT16 op) |
| 839 | | { |
| 840 | | int psize = pixelsize_lookup[IOREG(REG_PSIZE) & 0x1f]; |
| 841 | | int trans = (IOREG(REG_CONTROL) & 0x20) >> 5; |
| 842 | | int rop = (IOREG(REG_CONTROL) >> 10) & 0x1f; |
| 843 | | int ix = trans | (rop << 1) | (psize << 6); |
| 844 | | if (!P_FLAG()) LOGGFX(("%08X(%3d):PIXBLT B,XY (%d,%d) (%dx%d) depth=%d\n", m_pc, m_screen->vpos(), DADDR_X(), DADDR_Y(), DYDX_X(), DYDX_Y(), IOREG(REG_PSIZE) ? IOREG(REG_PSIZE) : 32)); |
| 845 | | m_pixel_op = s_pixel_op_table[rop]; |
| 846 | | m_pixel_op_timing = s_pixel_op_timing_table[rop]; |
| 847 | | (this->*s_pixblt_b_op_table[ix])(0); |
| 848 | | } |
| 849 | | |
| 850 | | void tms340x0_device::pixblt_l_l(UINT16 op) |
| 851 | | { |
| 852 | | int psize = pixelsize_lookup[IOREG(REG_PSIZE) & 0x1f]; |
| 853 | | int trans = (IOREG(REG_CONTROL) & 0x20) >> 5; |
| 854 | | int rop = (IOREG(REG_CONTROL) >> 10) & 0x1f; |
| 855 | | int pbh = (IOREG(REG_CONTROL) >> 8) & 1; |
| 856 | | int ix = trans | (rop << 1) | (psize << 6); |
| 857 | | if (!P_FLAG()) LOGGFX(("%08X(%3d):PIXBLT L,L (%dx%d) depth=%d\n", m_pc, m_screen->vpos(), DYDX_X(), DYDX_Y(), IOREG(REG_PSIZE) ? IOREG(REG_PSIZE) : 32)); |
| 858 | | m_pixel_op = s_pixel_op_table[rop]; |
| 859 | | m_pixel_op_timing = s_pixel_op_timing_table[rop]; |
| 860 | | if (!pbh) |
| 861 | | (this->*s_pixblt_op_table[ix])(1, 1); |
| 862 | | else |
| 863 | | (this->*s_pixblt_r_op_table[ix])(1, 1); |
| 864 | | } |
| 865 | | |
| 866 | | void tms340x0_device::pixblt_l_xy(UINT16 op) |
| 867 | | { |
| 868 | | int psize = pixelsize_lookup[IOREG(REG_PSIZE) & 0x1f]; |
| 869 | | int trans = (IOREG(REG_CONTROL) & 0x20) >> 5; |
| 870 | | int rop = (IOREG(REG_CONTROL) >> 10) & 0x1f; |
| 871 | | int pbh = (IOREG(REG_CONTROL) >> 8) & 1; |
| 872 | | int ix = trans | (rop << 1) | (psize << 6); |
| 873 | | if (!P_FLAG()) LOGGFX(("%08X(%3d):PIXBLT L,XY (%d,%d) (%dx%d) depth=%d\n", m_pc, m_screen->vpos(), DADDR_X(), DADDR_Y(), DYDX_X(), DYDX_Y(), IOREG(REG_PSIZE) ? IOREG(REG_PSIZE) : 32)); |
| 874 | | m_pixel_op = s_pixel_op_table[rop]; |
| 875 | | m_pixel_op_timing = s_pixel_op_timing_table[rop]; |
| 876 | | if (!pbh) |
| 877 | | (this->*s_pixblt_op_table[ix])(1, 0); |
| 878 | | else |
| 879 | | (this->*s_pixblt_r_op_table[ix])(1, 0); |
| 880 | | } |
| 881 | | |
| 882 | | void tms340x0_device::pixblt_xy_l(UINT16 op) |
| 883 | | { |
| 884 | | int psize = pixelsize_lookup[IOREG(REG_PSIZE) & 0x1f]; |
| 885 | | int trans = (IOREG(REG_CONTROL) & 0x20) >> 5; |
| 886 | | int rop = (IOREG(REG_CONTROL) >> 10) & 0x1f; |
| 887 | | int pbh = (IOREG(REG_CONTROL) >> 8) & 1; |
| 888 | | int ix = trans | (rop << 1) | (psize << 6); |
| 889 | | if (!P_FLAG()) LOGGFX(("%08X(%3d):PIXBLT XY,L (%dx%d) depth=%d\n", m_pc, m_screen->vpos(), DYDX_X(), DYDX_Y(), IOREG(REG_PSIZE) ? IOREG(REG_PSIZE) : 32)); |
| 890 | | m_pixel_op = s_pixel_op_table[rop]; |
| 891 | | m_pixel_op_timing = s_pixel_op_timing_table[rop]; |
| 892 | | if (!pbh) |
| 893 | | (this->*s_pixblt_op_table[ix])(0, 1); |
| 894 | | else |
| 895 | | (this->*s_pixblt_r_op_table[ix])(0, 1); |
| 896 | | } |
| 897 | | |
| 898 | | void tms340x0_device::pixblt_xy_xy(UINT16 op) |
| 899 | | { |
| 900 | | int psize = pixelsize_lookup[IOREG(REG_PSIZE) & 0x1f]; |
| 901 | | int trans = (IOREG(REG_CONTROL) & 0x20) >> 5; |
| 902 | | int rop = (IOREG(REG_CONTROL) >> 10) & 0x1f; |
| 903 | | int pbh = (IOREG(REG_CONTROL) >> 8) & 1; |
| 904 | | int ix = trans | (rop << 1) | (psize << 6); |
| 905 | | if (!P_FLAG()) LOGGFX(("%08X(%3d):PIXBLT XY,XY (%dx%d) depth=%d\n", m_pc, m_screen->vpos(), DYDX_X(), DYDX_Y(), IOREG(REG_PSIZE) ? IOREG(REG_PSIZE) : 32)); |
| 906 | | m_pixel_op = s_pixel_op_table[rop]; |
| 907 | | m_pixel_op_timing = s_pixel_op_timing_table[rop]; |
| 908 | | if (!pbh) |
| 909 | | (this->*s_pixblt_op_table[ix])(0, 0); |
| 910 | | else |
| 911 | | (this->*s_pixblt_r_op_table[ix])(0, 0); |
| 912 | | } |
| 913 | | |
| 914 | | void tms340x0_device::fill_l(UINT16 op) |
| 915 | | { |
| 916 | | int psize = pixelsize_lookup[IOREG(REG_PSIZE) & 0x1f]; |
| 917 | | int trans = (IOREG(REG_CONTROL) & 0x20) >> 5; |
| 918 | | int rop = (IOREG(REG_CONTROL) >> 10) & 0x1f; |
| 919 | | int ix = trans | (rop << 1) | (psize << 6); |
| 920 | | if (!P_FLAG()) LOGGFX(("%08X(%3d):FILL L (%dx%d) depth=%d\n", m_pc, m_screen->vpos(), DYDX_X(), DYDX_Y(), IOREG(REG_PSIZE) ? IOREG(REG_PSIZE) : 32)); |
| 921 | | m_pixel_op = s_pixel_op_table[rop]; |
| 922 | | m_pixel_op_timing = s_pixel_op_timing_table[rop]; |
| 923 | | (this->*s_fill_op_table[ix])(1); |
| 924 | | } |
| 925 | | |
| 926 | | void tms340x0_device::fill_xy(UINT16 op) |
| 927 | | { |
| 928 | | int psize = pixelsize_lookup[IOREG(REG_PSIZE) & 0x1f]; |
| 929 | | int trans = (IOREG(REG_CONTROL) & 0x20) >> 5; |
| 930 | | int rop = (IOREG(REG_CONTROL) >> 10) & 0x1f; |
| 931 | | int ix = trans | (rop << 1) | (psize << 6); |
| 932 | | if (!P_FLAG()) LOGGFX(("%08X(%3d):FILL XY (%d,%d) (%dx%d) depth=%d\n", m_pc, m_screen->vpos(), DADDR_X(), DADDR_Y(), DYDX_X(), DYDX_Y(), IOREG(REG_PSIZE) ? IOREG(REG_PSIZE) : 32)); |
| 933 | | m_pixel_op = s_pixel_op_table[rop]; |
| 934 | | m_pixel_op_timing = s_pixel_op_timing_table[rop]; |
| 935 | | (this->*s_fill_op_table[ix])(0); |
| 936 | | } |
| 937 | | |
| 938 | | |
| 939 | | #else |
| 940 | | |
| 941 | | |
| 942 | | #undef PIXELS_PER_WORD |
| 943 | | #undef PIXEL_MASK |
| 944 | | |
| 945 | | #define PIXELS_PER_WORD (16 / BITS_PER_PIXEL) |
| 946 | | #define PIXEL_MASK ((1 << BITS_PER_PIXEL) - 1) |
| 947 | | |
| 948 | | void FUNCTION_NAME(tms340x0_device::pixblt)(int src_is_linear, int dst_is_linear) |
| 949 | | { |
| 950 | | /* if this is the first time through, perform the operation */ |
| 951 | | if (!P_FLAG()) |
| 952 | | { |
| 953 | | int dx, dy, x, y, /*words,*/ yreverse; |
| 954 | | word_write_func word_write; |
| 955 | | word_read_func word_read; |
| 956 | | UINT32 readwrites = 0; |
| 957 | | UINT32 saddr, daddr; |
| 958 | | XY dstxy = { 0 }; |
| 959 | | |
| 960 | | /* determine read/write functions */ |
| 961 | | if (IOREG(REG_DPYCTL) & 0x0800) |
| 962 | | { |
| 963 | | word_write = &tms340x0_device::shiftreg_w; |
| 964 | | word_read = &tms340x0_device::shiftreg_r; |
| 965 | | } |
| 966 | | else |
| 967 | | { |
| 968 | | word_write = &tms340x0_device::memory_w; |
| 969 | | word_read = &tms340x0_device::memory_r; |
| 970 | | } |
| 971 | | |
| 972 | | /* compute the starting addresses */ |
| 973 | | saddr = src_is_linear ? SADDR() : SXYTOL(SADDR_XY()); |
| 974 | | |
| 975 | | /* compute the bounds of the operation */ |
| 976 | | dx = (INT16)DYDX_X(); |
| 977 | | dy = (INT16)DYDX_Y(); |
| 978 | | |
| 979 | | /* apply the window for non-linear destinations */ |
| 980 | | m_gfxcycles = 7 + (src_is_linear ? 0 : 2); |
| 981 | | if (!dst_is_linear) |
| 982 | | { |
| 983 | | dstxy = DADDR_XY(); |
| 984 | | m_gfxcycles += 2 + (!src_is_linear) + apply_window("PIXBLT", BITS_PER_PIXEL, &saddr, &dstxy, &dx, &dy); |
| 985 | | daddr = DXYTOL(dstxy); |
| 986 | | } |
| 987 | | else |
| 988 | | daddr = DADDR(); |
| 989 | | daddr &= ~(BITS_PER_PIXEL - 1); |
| 990 | | LOGGFX((" saddr=%08X daddr=%08X sptch=%08X dptch=%08X\n", saddr, daddr, SPTCH(), DPTCH())); |
| 991 | | |
| 992 | | /* bail if we're clipped */ |
| 993 | | if (dx <= 0 || dy <= 0) |
| 994 | | return; |
| 995 | | |
| 996 | | /* window mode 1: just return and interrupt if we are within the window */ |
| 997 | | if (WINDOW_CHECKING() == 1 && !dst_is_linear) |
| 998 | | { |
| 999 | | CLR_V(); |
| 1000 | | DADDR_XY() = dstxy; |
| 1001 | | DYDX_X() = dx; |
| 1002 | | DYDX_Y() = dy; |
| 1003 | | IOREG(REG_INTPEND) |= TMS34010_WV; |
| 1004 | | check_interrupt(); |
| 1005 | | return; |
| 1006 | | } |
| 1007 | | |
| 1008 | | /* handle flipping the addresses */ |
| 1009 | | yreverse = (IOREG(REG_CONTROL) >> 9) & 1; |
| 1010 | | if (!src_is_linear || !dst_is_linear) |
| 1011 | | { |
| 1012 | | if (yreverse) |
| 1013 | | { |
| 1014 | | saddr += (dy - 1) * m_convsp; |
| 1015 | | daddr += (dy - 1) * m_convdp; |
| 1016 | | } |
| 1017 | | } |
| 1018 | | |
| 1019 | | m_st |= STBIT_P; |
| 1020 | | |
| 1021 | | /* loop over rows */ |
| 1022 | | for (y = 0; y < dy; y++) |
| 1023 | | { |
| 1024 | | UINT32 srcwordaddr = saddr >> 4; |
| 1025 | | UINT32 dstwordaddr = daddr >> 4; |
| 1026 | | UINT8 srcbit = saddr & 15; |
| 1027 | | UINT8 dstbit = daddr & 15; |
| 1028 | | UINT32 srcword, dstword = 0; |
| 1029 | | |
| 1030 | | /* fetch the initial source word */ |
| 1031 | | srcword = (this->*word_read)(*m_program, srcwordaddr++ << 1); |
| 1032 | | readwrites++; |
| 1033 | | |
| 1034 | | /* fetch the initial dest word */ |
| 1035 | | if (PIXEL_OP_REQUIRES_SOURCE || TRANSPARENCY || (daddr & 0x0f) != 0) |
| 1036 | | { |
| 1037 | | dstword = (this->*word_read)(*m_program, dstwordaddr << 1); |
| 1038 | | readwrites++; |
| 1039 | | } |
| 1040 | | |
| 1041 | | /* loop over pixels */ |
| 1042 | | for (x = 0; x < dx; x++) |
| 1043 | | { |
| 1044 | | UINT32 dstmask; |
| 1045 | | UINT32 pixel; |
| 1046 | | |
| 1047 | | /* fetch more words if necessary */ |
| 1048 | | if (srcbit + BITS_PER_PIXEL > 16) |
| 1049 | | { |
| 1050 | | srcword |= (this->*word_read)(*m_program, srcwordaddr++ << 1) << 16; |
| 1051 | | readwrites++; |
| 1052 | | } |
| 1053 | | |
| 1054 | | /* extract pixel from source */ |
| 1055 | | pixel = (srcword >> srcbit) & PIXEL_MASK; |
| 1056 | | srcbit += BITS_PER_PIXEL; |
| 1057 | | if (srcbit > 16) |
| 1058 | | { |
| 1059 | | srcbit -= 16; |
| 1060 | | srcword >>= 16; |
| 1061 | | } |
| 1062 | | |
| 1063 | | /* fetch additional destination word if necessary */ |
| 1064 | | if (PIXEL_OP_REQUIRES_SOURCE || TRANSPARENCY) |
| 1065 | | if (dstbit + BITS_PER_PIXEL > 16) |
| 1066 | | { |
| 1067 | | dstword |= (this->*word_read)(*m_program, (dstwordaddr + 1) << 1) << 16; |
| 1068 | | readwrites++; |
| 1069 | | } |
| 1070 | | |
| 1071 | | /* apply pixel operations */ |
| 1072 | | pixel <<= dstbit; |
| 1073 | | dstmask = PIXEL_MASK << dstbit; |
| 1074 | | PIXEL_OP(dstword, dstmask, pixel); |
| 1075 | | if (!TRANSPARENCY || pixel != 0) |
| 1076 | | dstword = (dstword & ~dstmask) | pixel; |
| 1077 | | |
| 1078 | | /* flush destination words */ |
| 1079 | | dstbit += BITS_PER_PIXEL; |
| 1080 | | if (dstbit > 16) |
| 1081 | | { |
| 1082 | | (this->*word_write)(*m_program, dstwordaddr++ << 1, dstword); |
| 1083 | | readwrites++; |
| 1084 | | dstbit -= 16; |
| 1085 | | dstword >>= 16; |
| 1086 | | } |
| 1087 | | } |
| 1088 | | |
| 1089 | | /* flush any remaining words */ |
| 1090 | | if (dstbit > 0) |
| 1091 | | { |
| 1092 | | /* if we're right-partial, read and mask the remaining bits */ |
| 1093 | | if (dstbit != 16) |
| 1094 | | { |
| 1095 | | UINT16 origdst = (this->*word_read)(*m_program, dstwordaddr << 1); |
| 1096 | | UINT16 mask = 0xffff << dstbit; |
| 1097 | | dstword = (dstword & ~mask) | (origdst & mask); |
| 1098 | | readwrites++; |
| 1099 | | } |
| 1100 | | |
| 1101 | | (this->*word_write)(*m_program, dstwordaddr++ << 1, dstword); |
| 1102 | | readwrites++; |
| 1103 | | } |
| 1104 | | |
| 1105 | | |
| 1106 | | |
| 1107 | | #if 0 |
| 1108 | | int left_partials, right_partials, full_words, bitshift, bitshift_alt; |
| 1109 | | UINT16 srcword, srcmask, dstword, dstmask, pixel; |
| 1110 | | UINT32 swordaddr, dwordaddr; |
| 1111 | | |
| 1112 | | /* determine the bit shift to get from source to dest */ |
| 1113 | | bitshift = ((daddr & 15) - (saddr & 15)) & 15; |
| 1114 | | bitshift_alt = (16 - bitshift) & 15; |
| 1115 | | |
| 1116 | | /* how many left and right partial pixels do we have? */ |
| 1117 | | left_partials = (PIXELS_PER_WORD - ((daddr & 15) / BITS_PER_PIXEL)) & (PIXELS_PER_WORD - 1); |
| 1118 | | right_partials = ((daddr + dx * BITS_PER_PIXEL) & 15) / BITS_PER_PIXEL; |
| 1119 | | full_words = dx - left_partials - right_partials; |
| 1120 | | if (full_words < 0) |
| 1121 | | left_partials = dx, right_partials = full_words = 0; |
| 1122 | | else |
| 1123 | | full_words /= PIXELS_PER_WORD; |
| 1124 | | |
| 1125 | | /* compute cycles */ |
| 1126 | | m_gfxcycles += compute_pixblt_cycles(left_partials, right_partials, full_words, PIXEL_OP_TIMING); |
| 1127 | | |
| 1128 | | /* use word addresses each row */ |
| 1129 | | swordaddr = saddr >> 4; |
| 1130 | | dwordaddr = daddr >> 4; |
| 1131 | | |
| 1132 | | /* fetch the initial source word */ |
| 1133 | | srcword = (this->*word_read)(*m_program, swordaddr++ << 1); |
| 1134 | | srcmask = PIXEL_MASK << (saddr & 15); |
| 1135 | | |
| 1136 | | /* handle the left partial word */ |
| 1137 | | if (left_partials != 0) |
| 1138 | | { |
| 1139 | | /* fetch the destination word */ |
| 1140 | | dstword = (this->*word_read)(*m_program, dwordaddr << 1); |
| 1141 | | dstmask = PIXEL_MASK << (daddr & 15); |
| 1142 | | |
| 1143 | | /* loop over partials */ |
| 1144 | | for (x = 0; x < left_partials; x++) |
| 1145 | | { |
| 1146 | | /* fetch another word if necessary */ |
| 1147 | | if (srcmask == 0) |
| 1148 | | { |
| 1149 | | srcword = (this->*word_read)(*m_program, swordaddr++ << 1); |
| 1150 | | srcmask = PIXEL_MASK; |
| 1151 | | } |
| 1152 | | |
| 1153 | | /* process the pixel */ |
| 1154 | | pixel = srcword & srcmask; |
| 1155 | | if (dstmask > srcmask) |
| 1156 | | pixel <<= bitshift; |
| 1157 | | else |
| 1158 | | pixel >>= bitshift_alt; |
| 1159 | | PIXEL_OP(dstword, dstmask, pixel); |
| 1160 | | if (!TRANSPARENCY || pixel != 0) |
| 1161 | | dstword = (dstword & ~dstmask) | pixel; |
| 1162 | | |
| 1163 | | /* update the source */ |
| 1164 | | srcmask <<= BITS_PER_PIXEL; |
| 1165 | | |
| 1166 | | /* update the destination */ |
| 1167 | | dstmask <<= BITS_PER_PIXEL; |
| 1168 | | } |
| 1169 | | |
| 1170 | | /* write the result */ |
| 1171 | | (this->*word_write)(*m_program, dwordaddr++ << 1, dstword); |
| 1172 | | } |
| 1173 | | |
| 1174 | | /* loop over full words */ |
| 1175 | | for (words = 0; words < full_words; words++) |
| 1176 | | { |
| 1177 | | /* fetch the destination word (if necessary) */ |
| 1178 | | if (PIXEL_OP_REQUIRES_SOURCE || TRANSPARENCY) |
| 1179 | | dstword = (this->*word_read)(*m_program, dwordaddr << 1); |
| 1180 | | else |
| 1181 | | dstword = 0; |
| 1182 | | dstmask = PIXEL_MASK; |
| 1183 | | |
| 1184 | | /* loop over partials */ |
| 1185 | | for (x = 0; x < PIXELS_PER_WORD; x++) |
| 1186 | | { |
| 1187 | | /* fetch another word if necessary */ |
| 1188 | | if (srcmask == 0) |
| 1189 | | { |
| 1190 | | srcword = (this->*word_read)(*m_program, swordaddr++ << 1); |
| 1191 | | srcmask = PIXEL_MASK; |
| 1192 | | } |
| 1193 | | |
| 1194 | | /* process the pixel */ |
| 1195 | | pixel = srcword & srcmask; |
| 1196 | | if (dstmask > srcmask) |
| 1197 | | pixel <<= bitshift; |
| 1198 | | else |
| 1199 | | pixel >>= bitshift_alt; |
| 1200 | | PIXEL_OP(dstword, dstmask, pixel); |
| 1201 | | if (!TRANSPARENCY || pixel != 0) |
| 1202 | | dstword = (dstword & ~dstmask) | pixel; |
| 1203 | | |
| 1204 | | /* update the source */ |
| 1205 | | srcmask <<= BITS_PER_PIXEL; |
| 1206 | | |
| 1207 | | /* update the destination */ |
| 1208 | | dstmask <<= BITS_PER_PIXEL; |
| 1209 | | } |
| 1210 | | |
| 1211 | | /* write the result */ |
| 1212 | | (this->*word_write)(*m_program, dwordaddr++ << 1, dstword); |
| 1213 | | } |
| 1214 | | |
| 1215 | | /* handle the right partial word */ |
| 1216 | | if (right_partials != 0) |
| 1217 | | { |
| 1218 | | /* fetch the destination word */ |
| 1219 | | dstword = (this->*word_read)(*m_program, dwordaddr << 1); |
| 1220 | | dstmask = PIXEL_MASK; |
| 1221 | | |
| 1222 | | /* loop over partials */ |
| 1223 | | for (x = 0; x < right_partials; x++) |
| 1224 | | { |
| 1225 | | /* fetch another word if necessary */ |
| 1226 | | if (srcmask == 0) |
| 1227 | | { |
| 1228 | | LOGGFX((" right fetch @ %08x\n", swordaddr)); |
| 1229 | | srcword = (this->*word_read)(*m_program, swordaddr++ << 1); |
| 1230 | | srcmask = PIXEL_MASK; |
| 1231 | | } |
| 1232 | | |
| 1233 | | /* process the pixel */ |
| 1234 | | pixel = srcword & srcmask; |
| 1235 | | if (dstmask > srcmask) |
| 1236 | | pixel <<= bitshift; |
| 1237 | | else |
| 1238 | | pixel >>= bitshift_alt; |
| 1239 | | PIXEL_OP(dstword, dstmask, pixel); |
| 1240 | | if (!TRANSPARENCY || pixel != 0) |
| 1241 | | dstword = (dstword & ~dstmask) | pixel; |
| 1242 | | |
| 1243 | | /* update the source */ |
| 1244 | | srcmask <<= BITS_PER_PIXEL; |
| 1245 | | |
| 1246 | | /* update the destination */ |
| 1247 | | dstmask <<= BITS_PER_PIXEL; |
| 1248 | | } |
| 1249 | | |
| 1250 | | /* write the result */ |
| 1251 | | (this->*word_write)(*m_program, dwordaddr++ << 1, dstword); |
| 1252 | | } |
| 1253 | | #endif |
| 1254 | | |
| 1255 | | /* update for next row */ |
| 1256 | | if (!yreverse) |
| 1257 | | { |
| 1258 | | saddr += SPTCH(); |
| 1259 | | daddr += DPTCH(); |
| 1260 | | } |
| 1261 | | else |
| 1262 | | { |
| 1263 | | saddr -= SPTCH(); |
| 1264 | | daddr -= DPTCH(); |
| 1265 | | } |
| 1266 | | } |
| 1267 | | |
| 1268 | | m_gfxcycles += readwrites * 2 + dx * dy * (PIXEL_OP_TIMING - 2); |
| 1269 | | |
| 1270 | | LOGGFX((" (%d cycles)\n", m_gfxcycles)); |
| 1271 | | } |
| 1272 | | |
| 1273 | | /* eat cycles */ |
| 1274 | | if (m_gfxcycles > m_icount) |
| 1275 | | { |
| 1276 | | m_gfxcycles -= m_icount; |
| 1277 | | m_icount = 0; |
| 1278 | | m_pc -= 0x10; |
| 1279 | | } |
| 1280 | | else |
| 1281 | | { |
| 1282 | | m_icount -= m_gfxcycles; |
| 1283 | | m_st &= ~STBIT_P; |
| 1284 | | if (src_is_linear && dst_is_linear) |
| 1285 | | SADDR() += DYDX_Y() * SPTCH(); |
| 1286 | | else if (src_is_linear) |
| 1287 | | SADDR() += DYDX_Y() * SPTCH(); |
| 1288 | | else |
| 1289 | | SADDR_Y() += DYDX_Y(); |
| 1290 | | if (dst_is_linear) |
| 1291 | | DADDR() += DYDX_Y() * DPTCH(); |
| 1292 | | else |
| 1293 | | DADDR_Y() += DYDX_Y(); |
| 1294 | | } |
| 1295 | | } |
| 1296 | | |
| 1297 | | void FUNCTION_NAME(tms340x0_device::pixblt_r)(int src_is_linear, int dst_is_linear) |
| 1298 | | { |
| 1299 | | /* if this is the first time through, perform the operation */ |
| 1300 | | if (!P_FLAG()) |
| 1301 | | { |
| 1302 | | int dx, dy, x, y, words, yreverse; |
| 1303 | | word_write_func word_write; |
| 1304 | | word_read_func word_read; |
| 1305 | | UINT32 saddr, daddr; |
| 1306 | | XY dstxy = { 0 }; |
| 1307 | | |
| 1308 | | /* determine read/write functions */ |
| 1309 | | if (IOREG(REG_DPYCTL) & 0x0800) |
| 1310 | | { |
| 1311 | | word_write = &tms340x0_device::shiftreg_w; |
| 1312 | | word_read = &tms340x0_device::shiftreg_r; |
| 1313 | | } |
| 1314 | | else |
| 1315 | | { |
| 1316 | | word_write = &tms340x0_device::memory_w; |
| 1317 | | word_read = &tms340x0_device::memory_r; |
| 1318 | | } |
| 1319 | | |
| 1320 | | /* compute the starting addresses */ |
| 1321 | | saddr = src_is_linear ? SADDR() : SXYTOL(SADDR_XY()); |
| 1322 | | if ((saddr & (BITS_PER_PIXEL - 1)) != 0) osd_printf_debug("PIXBLT_R%d with odd saddr\n", BITS_PER_PIXEL); |
| 1323 | | saddr &= ~(BITS_PER_PIXEL - 1); |
| 1324 | | |
| 1325 | | /* compute the bounds of the operation */ |
| 1326 | | dx = (INT16)DYDX_X(); |
| 1327 | | dy = (INT16)DYDX_Y(); |
| 1328 | | |
| 1329 | | /* apply the window for non-linear destinations */ |
| 1330 | | m_gfxcycles = 7 + (src_is_linear ? 0 : 2); |
| 1331 | | if (!dst_is_linear) |
| 1332 | | { |
| 1333 | | dstxy = DADDR_XY(); |
| 1334 | | m_gfxcycles += 2 + (!src_is_linear) + apply_window("PIXBLT R", BITS_PER_PIXEL, &saddr, &dstxy, &dx, &dy); |
| 1335 | | daddr = DXYTOL(dstxy); |
| 1336 | | } |
| 1337 | | else |
| 1338 | | daddr = DADDR(); |
| 1339 | | if ((daddr & (BITS_PER_PIXEL - 1)) != 0) osd_printf_debug("PIXBLT_R%d with odd daddr\n", BITS_PER_PIXEL); |
| 1340 | | daddr &= ~(BITS_PER_PIXEL - 1); |
| 1341 | | LOGGFX((" saddr=%08X daddr=%08X sptch=%08X dptch=%08X\n", saddr, daddr, SPTCH(), DPTCH())); |
| 1342 | | |
| 1343 | | /* bail if we're clipped */ |
| 1344 | | if (dx <= 0 || dy <= 0) |
| 1345 | | return; |
| 1346 | | |
| 1347 | | /* window mode 1: just return and interrupt if we are within the window */ |
| 1348 | | if (WINDOW_CHECKING() == 1 && !dst_is_linear) |
| 1349 | | { |
| 1350 | | CLR_V(); |
| 1351 | | DADDR_XY() = dstxy; |
| 1352 | | DYDX_X() = dx; |
| 1353 | | DYDX_Y() = dy; |
| 1354 | | IOREG(REG_INTPEND) |= TMS34010_WV; |
| 1355 | | check_interrupt(); |
| 1356 | | return; |
| 1357 | | } |
| 1358 | | |
| 1359 | | /* handle flipping the addresses */ |
| 1360 | | yreverse = (IOREG(REG_CONTROL) >> 9) & 1; |
| 1361 | | if (!src_is_linear || !dst_is_linear) |
| 1362 | | { |
| 1363 | | saddr += dx * BITS_PER_PIXEL; |
| 1364 | | daddr += dx * BITS_PER_PIXEL; |
| 1365 | | if (yreverse) |
| 1366 | | { |
| 1367 | | saddr += (dy - 1) * m_convsp; |
| 1368 | | daddr += (dy - 1) * m_convdp; |
| 1369 | | } |
| 1370 | | } |
| 1371 | | |
| 1372 | | m_st |= STBIT_P; |
| 1373 | | |
| 1374 | | /* loop over rows */ |
| 1375 | | for (y = 0; y < dy; y++) |
| 1376 | | { |
| 1377 | | int left_partials, right_partials, full_words, bitshift, bitshift_alt; |
| 1378 | | UINT16 srcword, srcmask, dstword, dstmask, pixel; |
| 1379 | | UINT32 swordaddr, dwordaddr; |
| 1380 | | |
| 1381 | | /* determine the bit shift to get from source to dest */ |
| 1382 | | bitshift = ((daddr & 15) - (saddr & 15)) & 15; |
| 1383 | | bitshift_alt = (16 - bitshift) & 15; |
| 1384 | | |
| 1385 | | /* how many left and right partial pixels do we have? */ |
| 1386 | | left_partials = (PIXELS_PER_WORD - (((daddr - dx * BITS_PER_PIXEL) & 15) / BITS_PER_PIXEL)) & (PIXELS_PER_WORD - 1); |
| 1387 | | right_partials = (daddr & 15) / BITS_PER_PIXEL; |
| 1388 | | full_words = dx - left_partials - right_partials; |
| 1389 | | if (full_words < 0) |
| 1390 | | right_partials = dx, left_partials = full_words = 0; |
| 1391 | | else |
| 1392 | | full_words /= PIXELS_PER_WORD; |
| 1393 | | |
| 1394 | | /* compute cycles */ |
| 1395 | | m_gfxcycles += compute_pixblt_cycles(left_partials, right_partials, full_words, PIXEL_OP_TIMING); |
| 1396 | | |
| 1397 | | /* use word addresses each row */ |
| 1398 | | swordaddr = (saddr + 15) >> 4; |
| 1399 | | dwordaddr = (daddr + 15) >> 4; |
| 1400 | | |
| 1401 | | /* fetch the initial source word */ |
| 1402 | | srcword = (this->*word_read)(*m_program, --swordaddr << 1); |
| 1403 | | srcmask = PIXEL_MASK << ((saddr - BITS_PER_PIXEL) & 15); |
| 1404 | | |
| 1405 | | /* handle the right partial word */ |
| 1406 | | if (right_partials != 0) |
| 1407 | | { |
| 1408 | | /* fetch the destination word */ |
| 1409 | | dstword = (this->*word_read)(*m_program, --dwordaddr << 1); |
| 1410 | | dstmask = PIXEL_MASK << ((daddr - BITS_PER_PIXEL) & 15); |
| 1411 | | |
| 1412 | | /* loop over partials */ |
| 1413 | | for (x = 0; x < right_partials; x++) |
| 1414 | | { |
| 1415 | | /* fetch source pixel if necessary */ |
| 1416 | | if (srcmask == 0) |
| 1417 | | { |
| 1418 | | srcword = (this->*word_read)(*m_program, --swordaddr << 1); |
| 1419 | | srcmask = PIXEL_MASK << (16 - BITS_PER_PIXEL); |
| 1420 | | } |
| 1421 | | |
| 1422 | | /* process the pixel */ |
| 1423 | | pixel = srcword & srcmask; |
| 1424 | | if (dstmask > srcmask) |
| 1425 | | pixel <<= bitshift; |
| 1426 | | else |
| 1427 | | pixel >>= bitshift_alt; |
| 1428 | | PIXEL_OP(dstword, dstmask, pixel); |
| 1429 | | if (!TRANSPARENCY || pixel != 0) |
| 1430 | | dstword = (dstword & ~dstmask) | pixel; |
| 1431 | | |
| 1432 | | #if (BITS_PER_PIXEL<16) |
| 1433 | | /* update the source */ |
| 1434 | | srcmask >>= BITS_PER_PIXEL; |
| 1435 | | |
| 1436 | | /* update the destination */ |
| 1437 | | dstmask >>= BITS_PER_PIXEL; |
| 1438 | | #else |
| 1439 | | srcmask = 0; |
| 1440 | | dstmask = 0; |
| 1441 | | #endif |
| 1442 | | } |
| 1443 | | |
| 1444 | | /* write the result */ |
| 1445 | | (this->*word_write)(*m_program, dwordaddr << 1, dstword); |
| 1446 | | } |
| 1447 | | |
| 1448 | | /* loop over full words */ |
| 1449 | | for (words = 0; words < full_words; words++) |
| 1450 | | { |
| 1451 | | /* fetch the destination word (if necessary) */ |
| 1452 | | dwordaddr--; |
| 1453 | | if (PIXEL_OP_REQUIRES_SOURCE || TRANSPARENCY) |
| 1454 | | dstword = (this->*word_read)(*m_program, dwordaddr << 1); |
| 1455 | | else |
| 1456 | | dstword = 0; |
| 1457 | | dstmask = PIXEL_MASK << (16 - BITS_PER_PIXEL); |
| 1458 | | |
| 1459 | | /* loop over partials */ |
| 1460 | | for (x = 0; x < PIXELS_PER_WORD; x++) |
| 1461 | | { |
| 1462 | | /* fetch source pixel if necessary */ |
| 1463 | | if (srcmask == 0) |
| 1464 | | { |
| 1465 | | srcword = (this->*word_read)(*m_program, --swordaddr << 1); |
| 1466 | | srcmask = PIXEL_MASK << (16 - BITS_PER_PIXEL); |
| 1467 | | } |
| 1468 | | |
| 1469 | | /* process the pixel */ |
| 1470 | | pixel = srcword & srcmask; |
| 1471 | | if (dstmask > srcmask) |
| 1472 | | pixel <<= bitshift; |
| 1473 | | else |
| 1474 | | pixel >>= bitshift_alt; |
| 1475 | | PIXEL_OP(dstword, dstmask, pixel); |
| 1476 | | if (!TRANSPARENCY || pixel != 0) |
| 1477 | | dstword = (dstword & ~dstmask) | pixel; |
| 1478 | | |
| 1479 | | #if (BITS_PER_PIXEL<16) |
| 1480 | | /* update the source */ |
| 1481 | | srcmask >>= BITS_PER_PIXEL; |
| 1482 | | |
| 1483 | | /* update the destination */ |
| 1484 | | dstmask >>= BITS_PER_PIXEL; |
| 1485 | | #else |
| 1486 | | srcmask = 0; |
| 1487 | | dstmask = 0; |
| 1488 | | #endif |
| 1489 | | } |
| 1490 | | |
| 1491 | | /* write the result */ |
| 1492 | | (this->*word_write)(*m_program, dwordaddr << 1, dstword); |
| 1493 | | } |
| 1494 | | |
| 1495 | | /* handle the left partial word */ |
| 1496 | | if (left_partials != 0) |
| 1497 | | { |
| 1498 | | /* fetch the destination word */ |
| 1499 | | dstword = (this->*word_read)(*m_program, --dwordaddr << 1); |
| 1500 | | dstmask = PIXEL_MASK << (16 - BITS_PER_PIXEL); |
| 1501 | | |
| 1502 | | /* loop over partials */ |
| 1503 | | for (x = 0; x < left_partials; x++) |
| 1504 | | { |
| 1505 | | /* fetch the source pixel if necessary */ |
| 1506 | | if (srcmask == 0) |
| 1507 | | { |
| 1508 | | srcword = (this->*word_read)(*m_program, --swordaddr << 1); |
| 1509 | | srcmask = PIXEL_MASK << (16 - BITS_PER_PIXEL); |
| 1510 | | } |
| 1511 | | |
| 1512 | | /* process the pixel */ |
| 1513 | | pixel = srcword & srcmask; |
| 1514 | | if (dstmask > srcmask) |
| 1515 | | pixel <<= bitshift; |
| 1516 | | else |
| 1517 | | pixel >>= bitshift_alt; |
| 1518 | | PIXEL_OP(dstword, dstmask, pixel); |
| 1519 | | if (!TRANSPARENCY || pixel != 0) |
| 1520 | | dstword = (dstword & ~dstmask) | pixel; |
| 1521 | | |
| 1522 | | #if (BITS_PER_PIXEL<16) |
| 1523 | | /* update the source */ |
| 1524 | | srcmask >>= BITS_PER_PIXEL; |
| 1525 | | |
| 1526 | | /* update the destination */ |
| 1527 | | dstmask >>= BITS_PER_PIXEL; |
| 1528 | | #else |
| 1529 | | srcmask = 0; |
| 1530 | | dstmask = 0; |
| 1531 | | #endif |
| 1532 | | } |
| 1533 | | |
| 1534 | | /* write the result */ |
| 1535 | | (this->*word_write)(*m_program, dwordaddr << 1, dstword); |
| 1536 | | } |
| 1537 | | |
| 1538 | | /* update for next row */ |
| 1539 | | if (!yreverse) |
| 1540 | | { |
| 1541 | | saddr += SPTCH(); |
| 1542 | | daddr += DPTCH(); |
| 1543 | | } |
| 1544 | | else |
| 1545 | | { |
| 1546 | | saddr -= SPTCH(); |
| 1547 | | daddr -= DPTCH(); |
| 1548 | | } |
| 1549 | | } |
| 1550 | | LOGGFX((" (%d cycles)\n", m_gfxcycles)); |
| 1551 | | } |
| 1552 | | |
| 1553 | | /* eat cycles */ |
| 1554 | | if (m_gfxcycles > m_icount) |
| 1555 | | { |
| 1556 | | m_gfxcycles -= m_icount; |
| 1557 | | m_icount = 0; |
| 1558 | | m_pc -= 0x10; |
| 1559 | | } |
| 1560 | | else |
| 1561 | | { |
| 1562 | | m_icount -= m_gfxcycles; |
| 1563 | | m_st &= ~STBIT_P; |
| 1564 | | if (src_is_linear && dst_is_linear) |
| 1565 | | SADDR() += DYDX_Y() * SPTCH(); |
| 1566 | | else if (src_is_linear) |
| 1567 | | SADDR() += DYDX_Y() * SPTCH(); |
| 1568 | | else |
| 1569 | | SADDR_Y() += DYDX_Y(); |
| 1570 | | if (dst_is_linear) |
| 1571 | | DADDR() += DYDX_Y() * DPTCH(); |
| 1572 | | else |
| 1573 | | DADDR_Y() += DYDX_Y(); |
| 1574 | | } |
| 1575 | | } |
| 1576 | | |
| 1577 | | void FUNCTION_NAME(tms340x0_device::pixblt_b)(int dst_is_linear) |
| 1578 | | { |
| 1579 | | /* if this is the first time through, perform the operation */ |
| 1580 | | if (!P_FLAG()) |
| 1581 | | { |
| 1582 | | int dx, dy, x, y, words, left_partials, right_partials, full_words; |
| 1583 | | word_write_func word_write; |
| 1584 | | word_read_func word_read; |
| 1585 | | UINT32 saddr, daddr; |
| 1586 | | XY dstxy = { 0 }; |
| 1587 | | |
| 1588 | | /* determine read/write functions */ |
| 1589 | | if (IOREG(REG_DPYCTL) & 0x0800) |
| 1590 | | { |
| 1591 | | word_write = &tms340x0_device::shiftreg_w; |
| 1592 | | word_read = &tms340x0_device::shiftreg_r; |
| 1593 | | } |
| 1594 | | else |
| 1595 | | { |
| 1596 | | word_write = &tms340x0_device::memory_w; |
| 1597 | | word_read = &tms340x0_device::memory_r; |
| 1598 | | } |
| 1599 | | |
| 1600 | | /* compute the starting addresses */ |
| 1601 | | saddr = SADDR(); |
| 1602 | | |
| 1603 | | /* compute the bounds of the operation */ |
| 1604 | | dx = (INT16)DYDX_X(); |
| 1605 | | dy = (INT16)DYDX_Y(); |
| 1606 | | |
| 1607 | | /* apply the window for non-linear destinations */ |
| 1608 | | m_gfxcycles = 4; |
| 1609 | | if (!dst_is_linear) |
| 1610 | | { |
| 1611 | | dstxy = DADDR_XY(); |
| 1612 | | m_gfxcycles += 2 + apply_window("PIXBLT B", 1, &saddr, &dstxy, &dx, &dy); |
| 1613 | | daddr = DXYTOL(dstxy); |
| 1614 | | } |
| 1615 | | else |
| 1616 | | daddr = DADDR(); |
| 1617 | | daddr &= ~(BITS_PER_PIXEL - 1); |
| 1618 | | LOGGFX((" saddr=%08X daddr=%08X sptch=%08X dptch=%08X\n", saddr, daddr, SPTCH(), DPTCH())); |
| 1619 | | |
| 1620 | | /* bail if we're clipped */ |
| 1621 | | if (dx <= 0 || dy <= 0) |
| 1622 | | return; |
| 1623 | | |
| 1624 | | /* window mode 1: just return and interrupt if we are within the window */ |
| 1625 | | if (WINDOW_CHECKING() == 1 && !dst_is_linear) |
| 1626 | | { |
| 1627 | | CLR_V(); |
| 1628 | | DADDR_XY() = dstxy; |
| 1629 | | DYDX_X() = dx; |
| 1630 | | DYDX_Y() = dy; |
| 1631 | | IOREG(REG_INTPEND) |= TMS34010_WV; |
| 1632 | | check_interrupt(); |
| 1633 | | return; |
| 1634 | | } |
| 1635 | | |
| 1636 | | /* how many left and right partial pixels do we have? */ |
| 1637 | | left_partials = (PIXELS_PER_WORD - ((daddr & 15) / BITS_PER_PIXEL)) & (PIXELS_PER_WORD - 1); |
| 1638 | | right_partials = ((daddr + dx * BITS_PER_PIXEL) & 15) / BITS_PER_PIXEL; |
| 1639 | | full_words = dx - left_partials - right_partials; |
| 1640 | | if (full_words < 0) |
| 1641 | | left_partials = dx, right_partials = full_words = 0; |
| 1642 | | else |
| 1643 | | full_words /= PIXELS_PER_WORD; |
| 1644 | | |
| 1645 | | /* compute cycles */ |
| 1646 | | m_gfxcycles += compute_pixblt_b_cycles(left_partials, right_partials, full_words, dy, PIXEL_OP_TIMING, BITS_PER_PIXEL); |
| 1647 | | m_st |= STBIT_P; |
| 1648 | | |
| 1649 | | /* loop over rows */ |
| 1650 | | for (y = 0; y < dy; y++) |
| 1651 | | { |
| 1652 | | UINT16 srcword, srcmask, dstword, dstmask, pixel; |
| 1653 | | UINT32 swordaddr, dwordaddr; |
| 1654 | | |
| 1655 | | /* use byte addresses each row */ |
| 1656 | | swordaddr = saddr >> 4; |
| 1657 | | dwordaddr = daddr >> 4; |
| 1658 | | |
| 1659 | | /* fetch the initial source word */ |
| 1660 | | srcword = (this->*word_read)(*m_program, swordaddr++ << 1); |
| 1661 | | srcmask = 1 << (saddr & 15); |
| 1662 | | |
| 1663 | | /* handle the left partial word */ |
| 1664 | | if (left_partials != 0) |
| 1665 | | { |
| 1666 | | /* fetch the destination word */ |
| 1667 | | dstword = (this->*word_read)(*m_program, dwordaddr << 1); |
| 1668 | | dstmask = PIXEL_MASK << (daddr & 15); |
| 1669 | | |
| 1670 | | /* loop over partials */ |
| 1671 | | for (x = 0; x < left_partials; x++) |
| 1672 | | { |
| 1673 | | /* process the pixel */ |
| 1674 | | pixel = (srcword & srcmask) ? COLOR1() : COLOR0(); |
| 1675 | | pixel &= dstmask; |
| 1676 | | PIXEL_OP(dstword, dstmask, pixel); |
| 1677 | | if (!TRANSPARENCY || pixel != 0) |
| 1678 | | dstword = (dstword & ~dstmask) | pixel; |
| 1679 | | |
| 1680 | | /* update the source */ |
| 1681 | | srcmask <<= 1; |
| 1682 | | if (srcmask == 0) |
| 1683 | | { |
| 1684 | | srcword = (this->*word_read)(*m_program, swordaddr++ << 1); |
| 1685 | | srcmask = 0x0001; |
| 1686 | | } |
| 1687 | | |
| 1688 | | /* update the destination */ |
| 1689 | | dstmask = dstmask << BITS_PER_PIXEL; |
| 1690 | | } |
| 1691 | | |
| 1692 | | /* write the result */ |
| 1693 | | (this->*word_write)(*m_program, dwordaddr++ << 1, dstword); |
| 1694 | | } |
| 1695 | | |
| 1696 | | /* loop over full words */ |
| 1697 | | for (words = 0; words < full_words; words++) |
| 1698 | | { |
| 1699 | | /* fetch the destination word (if necessary) */ |
| 1700 | | if (PIXEL_OP_REQUIRES_SOURCE || TRANSPARENCY) |
| 1701 | | dstword = (this->*word_read)(*m_program, dwordaddr << 1); |
| 1702 | | else |
| 1703 | | dstword = 0; |
| 1704 | | dstmask = PIXEL_MASK; |
| 1705 | | |
| 1706 | | /* loop over partials */ |
| 1707 | | for (x = 0; x < PIXELS_PER_WORD; x++) |
| 1708 | | { |
| 1709 | | /* process the pixel */ |
| 1710 | | pixel = (srcword & srcmask) ? COLOR1() : COLOR0(); |
| 1711 | | pixel &= dstmask; |
| 1712 | | PIXEL_OP(dstword, dstmask, pixel); |
| 1713 | | if (!TRANSPARENCY || pixel != 0) |
| 1714 | | dstword = (dstword & ~dstmask) | pixel; |
| 1715 | | |
| 1716 | | /* update the source */ |
| 1717 | | srcmask <<= 1; |
| 1718 | | if (srcmask == 0) |
| 1719 | | { |
| 1720 | | srcword = (this->*word_read)(*m_program, swordaddr++ << 1); |
| 1721 | | srcmask = 0x0001; |
| 1722 | | } |
| 1723 | | |
| 1724 | | /* update the destination */ |
| 1725 | | dstmask = dstmask << BITS_PER_PIXEL; |
| 1726 | | } |
| 1727 | | |
| 1728 | | /* write the result */ |
| 1729 | | (this->*word_write)(*m_program, dwordaddr++ << 1, dstword); |
| 1730 | | } |
| 1731 | | |
| 1732 | | /* handle the right partial word */ |
| 1733 | | if (right_partials != 0) |
| 1734 | | { |
| 1735 | | /* fetch the destination word */ |
| 1736 | | dstword = (this->*word_read)(*m_program, dwordaddr << 1); |
| 1737 | | dstmask = PIXEL_MASK; |
| 1738 | | |
| 1739 | | /* loop over partials */ |
| 1740 | | for (x = 0; x < right_partials; x++) |
| 1741 | | { |
| 1742 | | /* process the pixel */ |
| 1743 | | pixel = (srcword & srcmask) ? COLOR1() : COLOR0(); |
| 1744 | | pixel &= dstmask; |
| 1745 | | PIXEL_OP(dstword, dstmask, pixel); |
| 1746 | | if (!TRANSPARENCY || pixel != 0) |
| 1747 | | dstword = (dstword & ~dstmask) | pixel; |
| 1748 | | |
| 1749 | | /* update the source */ |
| 1750 | | srcmask <<= 1; |
| 1751 | | if (srcmask == 0) |
| 1752 | | { |
| 1753 | | srcword = (this->*word_read)(*m_program, swordaddr++ << 1); |
| 1754 | | srcmask = 0x0001; |
| 1755 | | } |
| 1756 | | |
| 1757 | | /* update the destination */ |
| 1758 | | dstmask = dstmask << BITS_PER_PIXEL; |
| 1759 | | } |
| 1760 | | |
| 1761 | | /* write the result */ |
| 1762 | | (this->*word_write)(*m_program, dwordaddr++ << 1, dstword); |
| 1763 | | } |
| 1764 | | |
| 1765 | | /* update for next row */ |
| 1766 | | saddr += SPTCH(); |
| 1767 | | daddr += DPTCH(); |
| 1768 | | } |
| 1769 | | LOGGFX((" (%d cycles)\n", m_gfxcycles)); |
| 1770 | | } |
| 1771 | | |
| 1772 | | /* eat cycles */ |
| 1773 | | if (m_gfxcycles > m_icount) |
| 1774 | | { |
| 1775 | | m_gfxcycles -= m_icount; |
| 1776 | | m_icount = 0; |
| 1777 | | m_pc -= 0x10; |
| 1778 | | } |
| 1779 | | else |
| 1780 | | { |
| 1781 | | m_icount -= m_gfxcycles; |
| 1782 | | m_st &= ~STBIT_P; |
| 1783 | | SADDR() += DYDX_Y() * SPTCH(); |
| 1784 | | if (dst_is_linear) |
| 1785 | | DADDR() += DYDX_Y() * DPTCH(); |
| 1786 | | else |
| 1787 | | DADDR_Y() += DYDX_Y(); |
| 1788 | | } |
| 1789 | | } |
| 1790 | | |
| 1791 | | void FUNCTION_NAME(tms340x0_device::fill)(int dst_is_linear) |
| 1792 | | { |
| 1793 | | /* if this is the first time through, perform the operation */ |
| 1794 | | if (!P_FLAG()) |
| 1795 | | { |
| 1796 | | int dx, dy, x, y, words, left_partials, right_partials, full_words; |
| 1797 | | word_write_func word_write; |
| 1798 | | word_read_func word_read; |
| 1799 | | UINT32 daddr; |
| 1800 | | XY dstxy = { 0 }; |
| 1801 | | |
| 1802 | | /* determine read/write functions */ |
| 1803 | | if (IOREG(REG_DPYCTL) & 0x0800) |
| 1804 | | { |
| 1805 | | word_write = &tms340x0_device::shiftreg_w; |
| 1806 | | word_read = &tms340x0_device::dummy_shiftreg_r; |
| 1807 | | } |
| 1808 | | else |
| 1809 | | { |
| 1810 | | word_write = &tms340x0_device::memory_w; |
| 1811 | | word_read = &tms340x0_device::memory_r; |
| 1812 | | } |
| 1813 | | |
| 1814 | | /* compute the bounds of the operation */ |
| 1815 | | dx = (INT16)DYDX_X(); |
| 1816 | | dy = (INT16)DYDX_Y(); |
| 1817 | | |
| 1818 | | /* apply the window for non-linear destinations */ |
| 1819 | | m_gfxcycles = 4; |
| 1820 | | if (!dst_is_linear) |
| 1821 | | { |
| 1822 | | dstxy = DADDR_XY(); |
| 1823 | | m_gfxcycles += 2 + apply_window("FILL", 0, NULL, &dstxy, &dx, &dy); |
| 1824 | | daddr = DXYTOL(dstxy); |
| 1825 | | } |
| 1826 | | else |
| 1827 | | daddr = DADDR(); |
| 1828 | | daddr &= ~(BITS_PER_PIXEL - 1); |
| 1829 | | LOGGFX((" daddr=%08X\n", daddr)); |
| 1830 | | |
| 1831 | | /* bail if we're clipped */ |
| 1832 | | if (dx <= 0 || dy <= 0) |
| 1833 | | return; |
| 1834 | | |
| 1835 | | /* window mode 1: just return and interrupt if we are within the window */ |
| 1836 | | if (WINDOW_CHECKING() == 1 && !dst_is_linear) |
| 1837 | | { |
| 1838 | | CLR_V(); |
| 1839 | | DADDR_XY() = dstxy; |
| 1840 | | DYDX_X() = dx; |
| 1841 | | DYDX_Y() = dy; |
| 1842 | | IOREG(REG_INTPEND) |= TMS34010_WV; |
| 1843 | | check_interrupt(); |
| 1844 | | return; |
| 1845 | | } |
| 1846 | | |
| 1847 | | /* how many left and right partial pixels do we have? */ |
| 1848 | | left_partials = (PIXELS_PER_WORD - ((daddr & 15) / BITS_PER_PIXEL)) & (PIXELS_PER_WORD - 1); |
| 1849 | | right_partials = ((daddr + dx * BITS_PER_PIXEL) & 15) / BITS_PER_PIXEL; |
| 1850 | | full_words = dx - left_partials - right_partials; |
| 1851 | | if (full_words < 0) |
| 1852 | | left_partials = dx, right_partials = full_words = 0; |
| 1853 | | else |
| 1854 | | full_words /= PIXELS_PER_WORD; |
| 1855 | | |
| 1856 | | /* compute cycles */ |
| 1857 | | m_gfxcycles += 2; |
| 1858 | | m_st |= STBIT_P; |
| 1859 | | |
| 1860 | | /* loop over rows */ |
| 1861 | | for (y = 0; y < dy; y++) |
| 1862 | | { |
| 1863 | | UINT16 dstword, dstmask, pixel; |
| 1864 | | UINT32 dwordaddr; |
| 1865 | | |
| 1866 | | /* use byte addresses each row */ |
| 1867 | | dwordaddr = daddr >> 4; |
| 1868 | | |
| 1869 | | /* compute cycles */ |
| 1870 | | m_gfxcycles += compute_fill_cycles(left_partials, right_partials, full_words, PIXEL_OP_TIMING); |
| 1871 | | |
| 1872 | | /* handle the left partial word */ |
| 1873 | | if (left_partials != 0) |
| 1874 | | { |
| 1875 | | /* fetch the destination word */ |
| 1876 | | dstword = (this->*word_read)(*m_program, dwordaddr << 1); |
| 1877 | | dstmask = PIXEL_MASK << (daddr & 15); |
| 1878 | | |
| 1879 | | /* loop over partials */ |
| 1880 | | for (x = 0; x < left_partials; x++) |
| 1881 | | { |
| 1882 | | /* process the pixel */ |
| 1883 | | pixel = COLOR1() & dstmask; |
| 1884 | | PIXEL_OP(dstword, dstmask, pixel); |
| 1885 | | if (!TRANSPARENCY || pixel != 0) |
| 1886 | | dstword = (dstword & ~dstmask) | pixel; |
| 1887 | | |
| 1888 | | /* update the destination */ |
| 1889 | | dstmask = dstmask << BITS_PER_PIXEL; |
| 1890 | | } |
| 1891 | | |
| 1892 | | /* write the result */ |
| 1893 | | (this->*word_write)(*m_program, dwordaddr++ << 1, dstword); |
| 1894 | | } |
| 1895 | | |
| 1896 | | /* loop over full words */ |
| 1897 | | for (words = 0; words < full_words; words++) |
| 1898 | | { |
| 1899 | | /* fetch the destination word (if necessary) */ |
| 1900 | | if (PIXEL_OP_REQUIRES_SOURCE || TRANSPARENCY) |
| 1901 | | dstword = (this->*word_read)(*m_program, dwordaddr << 1); |
| 1902 | | else |
| 1903 | | dstword = 0; |
| 1904 | | dstmask = PIXEL_MASK; |
| 1905 | | |
| 1906 | | /* loop over partials */ |
| 1907 | | for (x = 0; x < PIXELS_PER_WORD; x++) |
| 1908 | | { |
| 1909 | | /* process the pixel */ |
| 1910 | | pixel = COLOR1() & dstmask; |
| 1911 | | PIXEL_OP(dstword, dstmask, pixel); |
| 1912 | | if (!TRANSPARENCY || pixel != 0) |
| 1913 | | dstword = (dstword & ~dstmask) | pixel; |
| 1914 | | |
| 1915 | | /* update the destination */ |
| 1916 | | dstmask = dstmask << BITS_PER_PIXEL; |
| 1917 | | } |
| 1918 | | |
| 1919 | | /* write the result */ |
| 1920 | | (this->*word_write)(*m_program, dwordaddr++ << 1, dstword); |
| 1921 | | } |
| 1922 | | |
| 1923 | | /* handle the right partial word */ |
| 1924 | | if (right_partials != 0) |
| 1925 | | { |
| 1926 | | /* fetch the destination word */ |
| 1927 | | dstword = (this->*word_read)(*m_program, dwordaddr << 1); |
| 1928 | | dstmask = PIXEL_MASK; |
| 1929 | | |
| 1930 | | /* loop over partials */ |
| 1931 | | for (x = 0; x < right_partials; x++) |
| 1932 | | { |
| 1933 | | /* process the pixel */ |
| 1934 | | pixel = COLOR1() & dstmask; |
| 1935 | | PIXEL_OP(dstword, dstmask, pixel); |
| 1936 | | if (!TRANSPARENCY || pixel != 0) |
| 1937 | | dstword = (dstword & ~dstmask) | pixel; |
| 1938 | | |
| 1939 | | /* update the destination */ |
| 1940 | | dstmask = dstmask << BITS_PER_PIXEL; |
| 1941 | | } |
| 1942 | | |
| 1943 | | /* write the result */ |
| 1944 | | (this->*word_write)(*m_program, dwordaddr++ << 1, dstword); |
| 1945 | | } |
| 1946 | | |
| 1947 | | /* update for next row */ |
| 1948 | | daddr += DPTCH(); |
| 1949 | | } |
| 1950 | | |
| 1951 | | LOGGFX((" (%d cycles)\n", m_gfxcycles)); |
| 1952 | | } |
| 1953 | | |
| 1954 | | /* eat cycles */ |
| 1955 | | if (m_gfxcycles > m_icount) |
| 1956 | | { |
| 1957 | | m_gfxcycles -= m_icount; |
| 1958 | | m_icount = 0; |
| 1959 | | m_pc -= 0x10; |
| 1960 | | } |
| 1961 | | else |
| 1962 | | { |
| 1963 | | m_icount -= m_gfxcycles; |
| 1964 | | m_st &= ~STBIT_P; |
| 1965 | | if (dst_is_linear) |
| 1966 | | DADDR() += DYDX_Y() * DPTCH(); |
| 1967 | | else |
| 1968 | | DADDR_Y() += DYDX_Y(); |
| 1969 | | } |
| 1970 | | } |
| 1971 | | |
| 1972 | | #endif |
trunk/src/devices/cpu/tms34010/34010gfx.inc
| r0 | r250222 | |
|---|
| 1 | // license:BSD-3-Clause |
| 2 | // copyright-holders:Alex Pasadyn,Zsolt Vasvari,Aaron Giles |
| 3 | /*************************************************************************** |
| 4 | |
| 5 | TMS34010: Portable Texas Instruments TMS34010 emulator |
| 6 | |
| 7 | Copyright Alex Pasadyn/Zsolt Vasvari |
| 8 | Parts based on code by Aaron Giles |
| 9 | |
| 10 | ***************************************************************************/ |
| 11 | |
| 12 | #ifndef RECURSIVE_INCLUDE |
| 13 | |
| 14 | |
| 15 | #define LOG_GFX_OPS 0 |
| 16 | #define LOGGFX(x) do { if (LOG_GFX_OPS && machine().input().code_pressed(KEYCODE_L)) logerror x; } while (0) |
| 17 | |
| 18 | |
| 19 | /* Graphics Instructions */ |
| 20 | |
| 21 | void tms340x0_device::line(UINT16 op) |
| 22 | { |
| 23 | if (!P_FLAG()) |
| 24 | { |
| 25 | if (WINDOW_CHECKING() != 0 && WINDOW_CHECKING() != 3) |
| 26 | logerror("LINE XY %08X - Window Checking Mode %d not supported\n", m_pc, WINDOW_CHECKING()); |
| 27 | |
| 28 | m_st |= STBIT_P; |
| 29 | TEMP() = (op & 0x80) ? 1 : 0; /* boundary value depends on the algorithm */ |
| 30 | LOGGFX(("%08X(%3d):LINE (%d,%d)-(%d,%d)\n", m_pc, m_screen->vpos(), DADDR_X(), DADDR_Y(), DADDR_X() + DYDX_X(), DADDR_Y() + DYDX_Y())); |
| 31 | } |
| 32 | |
| 33 | if (COUNT() > 0) |
| 34 | { |
| 35 | INT16 x1,y1; |
| 36 | |
| 37 | COUNT()--; |
| 38 | if (WINDOW_CHECKING() != 3 || |
| 39 | (DADDR_X() >= WSTART_X() && DADDR_X() <= WEND_X() && |
| 40 | DADDR_Y() >= WSTART_Y() && DADDR_Y() <= WEND_Y())) |
| 41 | WPIXEL(DXYTOL(DADDR_XY()),COLOR1()); |
| 42 | |
| 43 | if (SADDR() >= TEMP()) |
| 44 | { |
| 45 | SADDR() += DYDX_Y()*2 - DYDX_X()*2; |
| 46 | x1 = INC1_X(); |
| 47 | y1 = INC1_Y(); |
| 48 | } |
| 49 | else |
| 50 | { |
| 51 | SADDR() += DYDX_Y()*2; |
| 52 | x1 = INC2_X(); |
| 53 | y1 = INC2_Y(); |
| 54 | } |
| 55 | DADDR_X() += x1; |
| 56 | DADDR_Y() += y1; |
| 57 | |
| 58 | COUNT_UNKNOWN_CYCLES(2); |
| 59 | m_pc -= 0x10; /* not done yet, check for interrupts and restart instruction */ |
| 60 | return; |
| 61 | } |
| 62 | m_st &= ~STBIT_P; |
| 63 | } |
| 64 | |
| 65 | |
| 66 | /* |
| 67 | cases: |
| 68 | * window modes (0,1,2,3) |
| 69 | * boolean/arithmetic ops (16+6) |
| 70 | * transparency (on/off) |
| 71 | * plane masking |
| 72 | * directions (left->right/right->left, top->bottom/bottom->top) |
| 73 | */ |
| 74 | |
| 75 | int tms340x0_device::apply_window(const char *inst_name,int srcbpp, UINT32 *srcaddr, XY *dst, int *dx, int *dy) |
| 76 | { |
| 77 | /* apply the window */ |
| 78 | if (WINDOW_CHECKING() == 0) |
| 79 | return 0; |
| 80 | else |
| 81 | { |
| 82 | int sx = dst->x; |
| 83 | int sy = dst->y; |
| 84 | int ex = sx + *dx - 1; |
| 85 | int ey = sy + *dy - 1; |
| 86 | int diff, cycles = 3; |
| 87 | |
| 88 | if (WINDOW_CHECKING() == 2) |
| 89 | logerror("%08x: %s apply_window window mode %d not supported!\n", pc(), inst_name, WINDOW_CHECKING()); |
| 90 | |
| 91 | CLR_V(); |
| 92 | if (WINDOW_CHECKING() == 1) |
| 93 | SET_V_LOG(1); |
| 94 | |
| 95 | /* clip X */ |
| 96 | diff = WSTART_X() - sx; |
| 97 | if (diff > 0) |
| 98 | { |
| 99 | if (srcaddr) |
| 100 | *srcaddr += diff * srcbpp; |
| 101 | sx += diff; |
| 102 | SET_V_LOG(1); |
| 103 | } |
| 104 | diff = ex - WEND_X(); |
| 105 | if (diff > 0) |
| 106 | { |
| 107 | ex -= diff; |
| 108 | SET_V_LOG(1); |
| 109 | } |
| 110 | |
| 111 | |
| 112 | /* clip Y */ |
| 113 | diff = WSTART_Y() - sy; |
| 114 | if (diff > 0) |
| 115 | { |
| 116 | if (srcaddr) |
| 117 | *srcaddr += diff * m_convsp; |
| 118 | |
| 119 | sy += diff; |
| 120 | SET_V_LOG(1); |
| 121 | } |
| 122 | diff = ey - WEND_Y(); |
| 123 | if (diff > 0) |
| 124 | { |
| 125 | ey -= diff; |
| 126 | SET_V_LOG(1); |
| 127 | } |
| 128 | |
| 129 | /* compute cycles */ |
| 130 | if (*dx != ex - sx + 1 || *dy != ey - sy + 1) |
| 131 | { |
| 132 | if (dst->x != sx || dst->y != sy) |
| 133 | cycles += 11; |
| 134 | else |
| 135 | cycles += 3; |
| 136 | } |
| 137 | else if (dst->x != sx || dst->y != sy) |
| 138 | cycles += 7; |
| 139 | |
| 140 | /* update the values */ |
| 141 | dst->x = sx; |
| 142 | dst->y = sy; |
| 143 | *dx = ex - sx + 1; |
| 144 | *dy = ey - sy + 1; |
| 145 | return cycles; |
| 146 | } |
| 147 | } |
| 148 | |
| 149 | |
| 150 | /******************************************************************* |
| 151 | |
| 152 | About the timing of gfx operations: |
| 153 | |
| 154 | The 34010 manual lists a fairly intricate and accurate way of |
| 155 | computing cycle timings for graphics ops. However, there are |
| 156 | enough typos and misleading statements to make the reliability |
| 157 | of the timing info questionable. |
| 158 | |
| 159 | So, to address this, here is a simplified approximate version |
| 160 | of the timing. |
| 161 | |
| 162 | timing = setup + (srcwords * 2 + dstwords * gfxop) * rows |
| 163 | |
| 164 | Each read access takes 2 cycles. Each gfx operation has |
| 165 | its own timing as specified in the 34010 manual. So, it's 2 |
| 166 | cycles per read plus gfxop cycles per operation. Pretty |
| 167 | simple, no? |
| 168 | |
| 169 | *******************************************************************/ |
| 170 | |
| 171 | int tms340x0_device::compute_fill_cycles(int left_partials, int right_partials, int full_words, int op_timing) |
| 172 | { |
| 173 | int dstwords; |
| 174 | |
| 175 | if (left_partials) full_words += 1; |
| 176 | if (right_partials) full_words += 1; |
| 177 | dstwords = full_words; |
| 178 | |
| 179 | return (dstwords * op_timing); |
| 180 | } |
| 181 | |
| 182 | int tms340x0_device::compute_pixblt_cycles(int left_partials, int right_partials, int full_words, int op_timing) |
| 183 | { |
| 184 | int srcwords, dstwords; |
| 185 | |
| 186 | if (left_partials) full_words += 1; |
| 187 | if (right_partials) full_words += 1; |
| 188 | srcwords = full_words; |
| 189 | dstwords = full_words; |
| 190 | |
| 191 | return (dstwords * op_timing + srcwords * 2) + 2; |
| 192 | } |
| 193 | |
| 194 | int tms340x0_device::compute_pixblt_b_cycles(int left_partials, int right_partials, int full_words, int rows, int op_timing, int bpp) |
| 195 | { |
| 196 | int srcwords, dstwords; |
| 197 | |
| 198 | if (left_partials) full_words += 1; |
| 199 | if (right_partials) full_words += 1; |
| 200 | srcwords = full_words * bpp / 16; |
| 201 | dstwords = full_words; |
| 202 | |
| 203 | return (dstwords * op_timing + srcwords * 2) * rows + 2; |
| 204 | } |
| 205 | |
| 206 | |
| 207 | /* Shift register handling */ |
| 208 | void tms340x0_device::memory_w(address_space &space, offs_t offset,UINT16 data) |
| 209 | { |
| 210 | space.write_word(offset, data); |
| 211 | } |
| 212 | |
| 213 | UINT16 tms340x0_device::memory_r(address_space &space, offs_t offset) |
| 214 | { |
| 215 | return space.read_word(offset); |
| 216 | } |
| 217 | |
| 218 | void tms340x0_device::shiftreg_w(address_space &space, offs_t offset,UINT16 data) |
| 219 | { |
| 220 | if (!m_from_shiftreg_cb.isnull()) |
| 221 | m_from_shiftreg_cb(space, (UINT32)(offset << 3) & ~15, &m_shiftreg[0]); |
| 222 | else |
| 223 | logerror("From ShiftReg function not set. PC = %08X\n", m_pc); |
| 224 | } |
| 225 | |
| 226 | UINT16 tms340x0_device::shiftreg_r(address_space &space, offs_t offset) |
| 227 | { |
| 228 | if (!m_to_shiftreg_cb.isnull()) |
| 229 | m_to_shiftreg_cb(space, (UINT32)(offset << 3) & ~15, &m_shiftreg[0]); |
| 230 | else |
| 231 | logerror("To ShiftReg function not set. PC = %08X\n", m_pc); |
| 232 | return m_shiftreg[0]; |
| 233 | } |
| 234 | |
| 235 | UINT16 tms340x0_device::dummy_shiftreg_r(address_space &space, offs_t offset) |
| 236 | { |
| 237 | return m_shiftreg[0]; |
| 238 | } |
| 239 | |
| 240 | |
| 241 | |
| 242 | /* Pixel operations */ |
| 243 | UINT32 tms340x0_device::pixel_op00(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return srcpix; } |
| 244 | UINT32 tms340x0_device::pixel_op01(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return srcpix & dstpix; } |
| 245 | UINT32 tms340x0_device::pixel_op02(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return srcpix & ~dstpix; } |
| 246 | UINT32 tms340x0_device::pixel_op03(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return 0; } |
| 247 | UINT32 tms340x0_device::pixel_op04(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return (srcpix | ~dstpix) & mask; } |
| 248 | UINT32 tms340x0_device::pixel_op05(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return ~(srcpix ^ dstpix) & mask; } |
| 249 | UINT32 tms340x0_device::pixel_op06(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return ~dstpix & mask; } |
| 250 | UINT32 tms340x0_device::pixel_op07(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return ~(srcpix | dstpix) & mask; } |
| 251 | UINT32 tms340x0_device::pixel_op08(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return (srcpix | dstpix) & mask; } |
| 252 | UINT32 tms340x0_device::pixel_op09(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return dstpix & mask; } |
| 253 | UINT32 tms340x0_device::pixel_op10(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return (srcpix ^ dstpix) & mask; } |
| 254 | UINT32 tms340x0_device::pixel_op11(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return (~srcpix & dstpix) & mask; } |
| 255 | UINT32 tms340x0_device::pixel_op12(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return mask; } |
| 256 | UINT32 tms340x0_device::pixel_op13(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return (~srcpix & dstpix) & mask; } |
| 257 | UINT32 tms340x0_device::pixel_op14(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return ~(srcpix & dstpix) & mask; } |
| 258 | UINT32 tms340x0_device::pixel_op15(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return srcpix ^ mask; } |
| 259 | UINT32 tms340x0_device::pixel_op16(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return (srcpix + dstpix) & mask; } |
| 260 | UINT32 tms340x0_device::pixel_op17(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { INT32 tmp = srcpix + (dstpix & mask); return (tmp > mask) ? mask : tmp; } |
| 261 | UINT32 tms340x0_device::pixel_op18(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { return (dstpix - srcpix) & mask; } |
| 262 | UINT32 tms340x0_device::pixel_op19(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { INT32 tmp = srcpix - (dstpix & mask); return (tmp < 0) ? 0 : tmp; } |
| 263 | UINT32 tms340x0_device::pixel_op20(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { dstpix &= mask; return (srcpix > dstpix) ? srcpix : dstpix; } |
| 264 | UINT32 tms340x0_device::pixel_op21(UINT32 dstpix, UINT32 mask, UINT32 srcpix) { dstpix &= mask; return (srcpix < dstpix) ? srcpix : dstpix; } |
| 265 | |
| 266 | const tms340x0_device::pixel_op_func tms340x0_device::s_pixel_op_table[32] = |
| 267 | { |
| 268 | &tms340x0_device::pixel_op00, &tms340x0_device::pixel_op01, &tms340x0_device::pixel_op02, &tms340x0_device::pixel_op03, &tms340x0_device::pixel_op04, &tms340x0_device::pixel_op05, &tms340x0_device::pixel_op06, &tms340x0_device::pixel_op07, |
| 269 | &tms340x0_device::pixel_op08, &tms340x0_device::pixel_op09, &tms340x0_device::pixel_op10, &tms340x0_device::pixel_op11, &tms340x0_device::pixel_op12, &tms340x0_device::pixel_op13, &tms340x0_device::pixel_op14, &tms340x0_device::pixel_op15, |
| 270 | &tms340x0_device::pixel_op16, &tms340x0_device::pixel_op17, &tms340x0_device::pixel_op18, &tms340x0_device::pixel_op19, &tms340x0_device::pixel_op20, &tms340x0_device::pixel_op21, &tms340x0_device::pixel_op00, &tms340x0_device::pixel_op00, |
| 271 | &tms340x0_device::pixel_op00, &tms340x0_device::pixel_op00, &tms340x0_device::pixel_op00, &tms340x0_device::pixel_op00, &tms340x0_device::pixel_op00, &tms340x0_device::pixel_op00, &tms340x0_device::pixel_op00, &tms340x0_device::pixel_op00 |
| 272 | }; |
| 273 | const UINT8 tms340x0_device::s_pixel_op_timing_table[33] = |
| 274 | { |
| 275 | 2,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,5,5,6,5,5,2,2,2,2,2,2,2,2,2,2,2 |
| 276 | }; |
| 277 | |
| 278 | |
| 279 | /* tables */ |
| 280 | const tms340x0_device::pixblt_op_func tms340x0_device::s_pixblt_op_table[] = |
| 281 | { |
| 282 | &tms340x0_device::pixblt_1_op0, &tms340x0_device::pixblt_1_op0_trans, &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, |
| 283 | &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, |
| 284 | &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, |
| 285 | &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, |
| 286 | &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, |
| 287 | &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, |
| 288 | &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, |
| 289 | &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, |
| 290 | &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, |
| 291 | &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, |
| 292 | &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, |
| 293 | &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, |
| 294 | &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, |
| 295 | &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, |
| 296 | &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, |
| 297 | &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, &tms340x0_device::pixblt_1_opx, &tms340x0_device::pixblt_1_opx_trans, |
| 298 | |
| 299 | &tms340x0_device::pixblt_2_op0, &tms340x0_device::pixblt_2_op0_trans, &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, |
| 300 | &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, |
| 301 | &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, |
| 302 | &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, |
| 303 | &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, |
| 304 | &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, |
| 305 | &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, |
| 306 | &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, |
| 307 | &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, |
| 308 | &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, |
| 309 | &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, |
| 310 | &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, |
| 311 | &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, |
| 312 | &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, |
| 313 | &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, |
| 314 | &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, &tms340x0_device::pixblt_2_opx, &tms340x0_device::pixblt_2_opx_trans, |
| 315 | |
| 316 | &tms340x0_device::pixblt_4_op0, &tms340x0_device::pixblt_4_op0_trans, &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, |
| 317 | &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, |
| 318 | &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, |
| 319 | &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, |
| 320 | &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, |
| 321 | &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, |
| 322 | &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, |
| 323 | &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, |
| 324 | &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, |
| 325 | &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, |
| 326 | &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, |
| 327 | &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, |
| 328 | &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, |
| 329 | &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, |
| 330 | &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, |
| 331 | &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, &tms340x0_device::pixblt_4_opx, &tms340x0_device::pixblt_4_opx_trans, |
| 332 | |
| 333 | &tms340x0_device::pixblt_8_op0, &tms340x0_device::pixblt_8_op0_trans, &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, |
| 334 | &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, |
| 335 | &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, |
| 336 | &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, |
| 337 | &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, |
| 338 | &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, |
| 339 | &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, |
| 340 | &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, |
| 341 | &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, |
| 342 | &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, |
| 343 | &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, |
| 344 | &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, |
| 345 | &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, |
| 346 | &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, |
| 347 | &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, |
| 348 | &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, &tms340x0_device::pixblt_8_opx, &tms340x0_device::pixblt_8_opx_trans, |
| 349 | |
| 350 | &tms340x0_device::pixblt_16_op0, &tms340x0_device::pixblt_16_op0_trans, &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, |
| 351 | &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, |
| 352 | &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, |
| 353 | &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, |
| 354 | &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, |
| 355 | &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, |
| 356 | &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, |
| 357 | &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, |
| 358 | &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, |
| 359 | &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, |
| 360 | &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, |
| 361 | &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, |
| 362 | &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, |
| 363 | &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, |
| 364 | &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, |
| 365 | &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans, &tms340x0_device::pixblt_16_opx, &tms340x0_device::pixblt_16_opx_trans |
| 366 | }; |
| 367 | |
| 368 | const tms340x0_device::pixblt_op_func tms340x0_device::s_pixblt_r_op_table[] = |
| 369 | { |
| 370 | &tms340x0_device::pixblt_r_1_op0, &tms340x0_device::pixblt_r_1_op0_trans, &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, |
| 371 | &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, |
| 372 | &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, |
| 373 | &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, |
| 374 | &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, |
| 375 | &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, |
| 376 | &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, |
| 377 | &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, |
| 378 | &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, |
| 379 | &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, |
| 380 | &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, |
| 381 | &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, |
| 382 | &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, |
| 383 | &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, |
| 384 | &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, |
| 385 | &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, &tms340x0_device::pixblt_r_1_opx, &tms340x0_device::pixblt_r_1_opx_trans, |
| 386 | |
| 387 | &tms340x0_device::pixblt_r_2_op0, &tms340x0_device::pixblt_r_2_op0_trans, &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, |
| 388 | &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, |
| 389 | &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, |
| 390 | &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, |
| 391 | &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, |
| 392 | &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, |
| 393 | &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, |
| 394 | &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, |
| 395 | &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, |
| 396 | &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, |
| 397 | &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, |
| 398 | &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, |
| 399 | &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, |
| 400 | &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, |
| 401 | &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, |
| 402 | &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, &tms340x0_device::pixblt_r_2_opx, &tms340x0_device::pixblt_r_2_opx_trans, |
| 403 | |
| 404 | &tms340x0_device::pixblt_r_4_op0, &tms340x0_device::pixblt_r_4_op0_trans, &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, |
| 405 | &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, |
| 406 | &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, |
| 407 | &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, |
| 408 | &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, |
| 409 | &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, |
| 410 | &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, |
| 411 | &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, |
| 412 | &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, |
| 413 | &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, |
| 414 | &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, |
| 415 | &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, |
| 416 | &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, |
| 417 | &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, |
| 418 | &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, |
| 419 | &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, &tms340x0_device::pixblt_r_4_opx, &tms340x0_device::pixblt_r_4_opx_trans, |
| 420 | |
| 421 | &tms340x0_device::pixblt_r_8_op0, &tms340x0_device::pixblt_r_8_op0_trans, &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, |
| 422 | &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, |
| 423 | &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, |
| 424 | &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, |
| 425 | &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, |
| 426 | &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, |
| 427 | &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, |
| 428 | &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, |
| 429 | &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, |
| 430 | &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, |
| 431 | &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, |
| 432 | &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, |
| 433 | &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, |
| 434 | &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, |
| 435 | &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, |
| 436 | &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, &tms340x0_device::pixblt_r_8_opx, &tms340x0_device::pixblt_r_8_opx_trans, |
| 437 | |
| 438 | &tms340x0_device::pixblt_r_16_op0,&tms340x0_device::pixblt_r_16_op0_trans, &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, |
| 439 | &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, |
| 440 | &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, |
| 441 | &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, |
| 442 | &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, |
| 443 | &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, |
| 444 | &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, |
| 445 | &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, |
| 446 | &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, |
| 447 | &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, |
| 448 | &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, |
| 449 | &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, |
| 450 | &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, |
| 451 | &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, |
| 452 | &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, |
| 453 | &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans, &tms340x0_device::pixblt_r_16_opx,&tms340x0_device::pixblt_r_16_opx_trans |
| 454 | }; |
| 455 | |
| 456 | const tms340x0_device::pixblt_b_op_func tms340x0_device::s_pixblt_b_op_table[] = |
| 457 | { |
| 458 | &tms340x0_device::pixblt_b_1_op0, &tms340x0_device::pixblt_b_1_op0_trans, &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, |
| 459 | &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, |
| 460 | &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, |
| 461 | &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, |
| 462 | &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, |
| 463 | &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, |
| 464 | &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, |
| 465 | &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, |
| 466 | &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, |
| 467 | &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, |
| 468 | &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, |
| 469 | &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, |
| 470 | &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, |
| 471 | &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, |
| 472 | &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, |
| 473 | &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, &tms340x0_device::pixblt_b_1_opx, &tms340x0_device::pixblt_b_1_opx_trans, |
| 474 | |
| 475 | &tms340x0_device::pixblt_b_2_op0, &tms340x0_device::pixblt_b_2_op0_trans, &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, |
| 476 | &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, |
| 477 | &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, |
| 478 | &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, |
| 479 | &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, |
| 480 | &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, |
| 481 | &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, |
| 482 | &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, |
| 483 | &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, |
| 484 | &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, |
| 485 | &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, |
| 486 | &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, |
| 487 | &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, |
| 488 | &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, |
| 489 | &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, |
| 490 | &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, &tms340x0_device::pixblt_b_2_opx, &tms340x0_device::pixblt_b_2_opx_trans, |
| 491 | |
| 492 | &tms340x0_device::pixblt_b_4_op0, &tms340x0_device::pixblt_b_4_op0_trans, &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, |
| 493 | &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, |
| 494 | &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, |
| 495 | &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, |
| 496 | &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, |
| 497 | &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, |
| 498 | &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, |
| 499 | &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, |
| 500 | &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, |
| 501 | &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, |
| 502 | &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, |
| 503 | &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, |
| 504 | &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, |
| 505 | &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, |
| 506 | &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, |
| 507 | &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, &tms340x0_device::pixblt_b_4_opx, &tms340x0_device::pixblt_b_4_opx_trans, |
| 508 | |
| 509 | &tms340x0_device::pixblt_b_8_op0, &tms340x0_device::pixblt_b_8_op0_trans, &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, |
| 510 | &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, |
| 511 | &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, |
| 512 | &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, |
| 513 | &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, |
| 514 | &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, |
| 515 | &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, |
| 516 | &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, |
| 517 | &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, |
| 518 | &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, |
| 519 | &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, |
| 520 | &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, |
| 521 | &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, |
| 522 | &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, |
| 523 | &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, |
| 524 | &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, &tms340x0_device::pixblt_b_8_opx, &tms340x0_device::pixblt_b_8_opx_trans, |
| 525 | |
| 526 | &tms340x0_device::pixblt_b_16_op0,&tms340x0_device::pixblt_b_16_op0_trans, &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, |
| 527 | &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, |
| 528 | &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, |
| 529 | &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, |
| 530 | &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, |
| 531 | &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, |
| 532 | &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, |
| 533 | &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, |
| 534 | &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, |
| 535 | &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, |
| 536 | &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, |
| 537 | &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, |
| 538 | &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, |
| 539 | &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, |
| 540 | &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, |
| 541 | &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans, &tms340x0_device::pixblt_b_16_opx,&tms340x0_device::pixblt_b_16_opx_trans |
| 542 | }; |
| 543 | |
| 544 | const tms340x0_device::pixblt_b_op_func tms340x0_device::s_fill_op_table[] = |
| 545 | { |
| 546 | &tms340x0_device::fill_1_op0, &tms340x0_device::fill_1_op0_trans, &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, |
| 547 | &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, |
| 548 | &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, |
| 549 | &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, |
| 550 | &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, |
| 551 | &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, |
| 552 | &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, |
| 553 | &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, |
| 554 | &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, |
| 555 | &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, |
| 556 | &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, |
| 557 | &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, |
| 558 | &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, |
| 559 | &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, |
| 560 | &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, |
| 561 | &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, &tms340x0_device::fill_1_opx, &tms340x0_device::fill_1_opx_trans, |
| 562 | |
| 563 | &tms340x0_device::fill_2_op0, &tms340x0_device::fill_2_op0_trans, &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, |
| 564 | &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, |
| 565 | &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, |
| 566 | &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, |
| 567 | &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, |
| 568 | &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, |
| 569 | &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, |
| 570 | &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, |
| 571 | &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, |
| 572 | &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, |
| 573 | &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, |
| 574 | &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, |
| 575 | &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, |
| 576 | &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, |
| 577 | &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, |
| 578 | &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, &tms340x0_device::fill_2_opx, &tms340x0_device::fill_2_opx_trans, |
| 579 | |
| 580 | &tms340x0_device::fill_4_op0, &tms340x0_device::fill_4_op0_trans, &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, |
| 581 | &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, |
| 582 | &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, |
| 583 | &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, |
| 584 | &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, |
| 585 | &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, |
| 586 | &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, |
| 587 | &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, |
| 588 | &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, |
| 589 | &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, |
| 590 | &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, |
| 591 | &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, |
| 592 | &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, |
| 593 | &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, |
| 594 | &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, |
| 595 | &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, &tms340x0_device::fill_4_opx, &tms340x0_device::fill_4_opx_trans, |
| 596 | |
| 597 | &tms340x0_device::fill_8_op0, &tms340x0_device::fill_8_op0_trans, &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, |
| 598 | &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, |
| 599 | &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, |
| 600 | &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, |
| 601 | &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, |
| 602 | &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, |
| 603 | &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, |
| 604 | &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, |
| 605 | &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, |
| 606 | &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, |
| 607 | &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, |
| 608 | &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, |
| 609 | &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, |
| 610 | &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, |
| 611 | &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, |
| 612 | &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, &tms340x0_device::fill_8_opx, &tms340x0_device::fill_8_opx_trans, |
| 613 | |
| 614 | &tms340x0_device::fill_16_op0, &tms340x0_device::fill_16_op0_trans, &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, |
| 615 | &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, |
| 616 | &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, |
| 617 | &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, |
| 618 | &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, |
| 619 | &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, |
| 620 | &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, |
| 621 | &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, |
| 622 | &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, |
| 623 | &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, |
| 624 | &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, |
| 625 | &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, |
| 626 | &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, |
| 627 | &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, |
| 628 | &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, |
| 629 | &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans, &tms340x0_device::fill_16_opx, &tms340x0_device::fill_16_opx_trans |
| 630 | }; |
| 631 | |
| 632 | |
| 633 | #define RECURSIVE_INCLUDE |
| 634 | |
| 635 | /* non-transparent replace ops */ |
| 636 | #define PIXEL_OP(src, mask, pixel) pixel = pixel |
| 637 | #define PIXEL_OP_TIMING 2 |
| 638 | #define PIXEL_OP_REQUIRES_SOURCE 0 |
| 639 | #define TRANSPARENCY 0 |
| 640 | |
| 641 | /* 1bpp cases */ |
| 642 | #define BITS_PER_PIXEL 1 |
| 643 | #define FUNCTION_NAME(base) base##_1_op0 |
| 644 | #include "34010gfx.inc" |
| 645 | #undef FUNCTION_NAME |
| 646 | #undef BITS_PER_PIXEL |
| 647 | |
| 648 | /* 2bpp cases */ |
| 649 | #define BITS_PER_PIXEL 2 |
| 650 | #define FUNCTION_NAME(base) base##_2_op0 |
| 651 | #include "34010gfx.inc" |
| 652 | #undef FUNCTION_NAME |
| 653 | #undef BITS_PER_PIXEL |
| 654 | |
| 655 | /* 4bpp cases */ |
| 656 | #define BITS_PER_PIXEL 4 |
| 657 | #define FUNCTION_NAME(base) base##_4_op0 |
| 658 | #include "34010gfx.inc" |
| 659 | #undef FUNCTION_NAME |
| 660 | #undef BITS_PER_PIXEL |
| 661 | |
| 662 | /* 8bpp cases */ |
| 663 | #define BITS_PER_PIXEL 8 |
| 664 | #define FUNCTION_NAME(base) base##_8_op0 |
| 665 | #include "34010gfx.inc" |
| 666 | #undef FUNCTION_NAME |
| 667 | #undef BITS_PER_PIXEL |
| 668 | |
| 669 | /* 16bpp cases */ |
| 670 | #define BITS_PER_PIXEL 16 |
| 671 | #define FUNCTION_NAME(base) base##_16_op0 |
| 672 | #include "34010gfx.inc" |
| 673 | #undef FUNCTION_NAME |
| 674 | #undef BITS_PER_PIXEL |
| 675 | |
| 676 | #undef TRANSPARENCY |
| 677 | #undef PIXEL_OP_REQUIRES_SOURCE |
| 678 | #undef PIXEL_OP_TIMING |
| 679 | #undef PIXEL_OP |
| 680 | |
| 681 | |
| 682 | #define PIXEL_OP(src, mask, pixel) pixel = (this->*m_pixel_op)(src, mask, pixel) |
| 683 | #define PIXEL_OP_TIMING m_pixel_op_timing |
| 684 | #define PIXEL_OP_REQUIRES_SOURCE 1 |
| 685 | #define TRANSPARENCY 0 |
| 686 | |
| 687 | /* 1bpp cases */ |
| 688 | #define BITS_PER_PIXEL 1 |
| 689 | #define FUNCTION_NAME(base) base##_1_opx |
| 690 | #include "34010gfx.inc" |
| 691 | #undef FUNCTION_NAME |
| 692 | #undef BITS_PER_PIXEL |
| 693 | |
| 694 | /* 2bpp cases */ |
| 695 | #define BITS_PER_PIXEL 2 |
| 696 | #define FUNCTION_NAME(base) base##_2_opx |
| 697 | #include "34010gfx.inc" |
| 698 | #undef FUNCTION_NAME |
| 699 | #undef BITS_PER_PIXEL |
| 700 | |
| 701 | /* 4bpp cases */ |
| 702 | #define BITS_PER_PIXEL 4 |
| 703 | #define FUNCTION_NAME(base) base##_4_opx |
| 704 | #include "34010gfx.inc" |
| 705 | #undef FUNCTION_NAME |
| 706 | #undef BITS_PER_PIXEL |
| 707 | |
| 708 | /* 8bpp cases */ |
| 709 | #define BITS_PER_PIXEL 8 |
| 710 | #define FUNCTION_NAME(base) base##_8_opx |
| 711 | #include "34010gfx.inc" |
| 712 | #undef FUNCTION_NAME |
| 713 | #undef BITS_PER_PIXEL |
| 714 | |
| 715 | /* 16bpp cases */ |
| 716 | #define BITS_PER_PIXEL 16 |
| 717 | #define FUNCTION_NAME(base) base##_16_opx |
| 718 | #include "34010gfx.inc" |
| 719 | #undef FUNCTION_NAME |
| 720 | #undef BITS_PER_PIXEL |
| 721 | |
| 722 | #undef TRANSPARENCY |
| 723 | #undef PIXEL_OP_REQUIRES_SOURCE |
| 724 | #undef PIXEL_OP_TIMING |
| 725 | #undef PIXEL_OP |
| 726 | |
| 727 | |
| 728 | /* transparent replace ops */ |
| 729 | #define PIXEL_OP(src, mask, pixel) pixel = pixel |
| 730 | #define PIXEL_OP_REQUIRES_SOURCE 0 |
| 731 | #define PIXEL_OP_TIMING 4 |
| 732 | #define TRANSPARENCY 1 |
| 733 | |
| 734 | /* 1bpp cases */ |
| 735 | #define BITS_PER_PIXEL 1 |
| 736 | #define FUNCTION_NAME(base) base##_1_op0_trans |
| 737 | #include "34010gfx.inc" |
| 738 | #undef FUNCTION_NAME |
| 739 | #undef BITS_PER_PIXEL |
| 740 | |
| 741 | /* 2bpp cases */ |
| 742 | #define BITS_PER_PIXEL 2 |
| 743 | #define FUNCTION_NAME(base) base##_2_op0_trans |
| 744 | #include "34010gfx.inc" |
| 745 | #undef FUNCTION_NAME |
| 746 | #undef BITS_PER_PIXEL |
| 747 | |
| 748 | /* 4bpp cases */ |
| 749 | #define BITS_PER_PIXEL 4 |
| 750 | #define FUNCTION_NAME(base) base##_4_op0_trans |
| 751 | #include "34010gfx.inc" |
| 752 | #undef FUNCTION_NAME |
| 753 | #undef BITS_PER_PIXEL |
| 754 | |
| 755 | /* 8bpp cases */ |
| 756 | #define BITS_PER_PIXEL 8 |
| 757 | #define FUNCTION_NAME(base) base##_8_op0_trans |
| 758 | #include "34010gfx.inc" |
| 759 | #undef FUNCTION_NAME |
| 760 | #undef BITS_PER_PIXEL |
| 761 | |
| 762 | /* 16bpp cases */ |
| 763 | #define BITS_PER_PIXEL 16 |
| 764 | #define FUNCTION_NAME(base) base##_16_op0_trans |
| 765 | #include "34010gfx.inc" |
| 766 | #undef FUNCTION_NAME |
| 767 | #undef BITS_PER_PIXEL |
| 768 | |
| 769 | #undef TRANSPARENCY |
| 770 | #undef PIXEL_OP_REQUIRES_SOURCE |
| 771 | #undef PIXEL_OP_TIMING |
| 772 | #undef PIXEL_OP |
| 773 | |
| 774 | |
| 775 | #define PIXEL_OP(src, mask, pixel) pixel = (this->*m_pixel_op)(src, mask, pixel) |
| 776 | #define PIXEL_OP_REQUIRES_SOURCE 1 |
| 777 | #define PIXEL_OP_TIMING (2+m_pixel_op_timing) |
| 778 | #define TRANSPARENCY 1 |
| 779 | |
| 780 | /* 1bpp cases */ |
| 781 | #define BITS_PER_PIXEL 1 |
| 782 | #define FUNCTION_NAME(base) base##_1_opx_trans |
| 783 | #include "34010gfx.inc" |
| 784 | #undef FUNCTION_NAME |
| 785 | #undef BITS_PER_PIXEL |
| 786 | |
| 787 | /* 2bpp cases */ |
| 788 | #define BITS_PER_PIXEL 2 |
| 789 | #define FUNCTION_NAME(base) base##_2_opx_trans |
| 790 | #include "34010gfx.inc" |
| 791 | #undef FUNCTION_NAME |
| 792 | #undef BITS_PER_PIXEL |
| 793 | |
| 794 | /* 4bpp cases */ |
| 795 | #define BITS_PER_PIXEL 4 |
| 796 | #define FUNCTION_NAME(base) base##_4_opx_trans |
| 797 | #include "34010gfx.inc" |
| 798 | #undef FUNCTION_NAME |
| 799 | #undef BITS_PER_PIXEL |
| 800 | |
| 801 | /* 8bpp cases */ |
| 802 | #define BITS_PER_PIXEL 8 |
| 803 | #define FUNCTION_NAME(base) base##_8_opx_trans |
| 804 | #include "34010gfx.inc" |
| 805 | #undef FUNCTION_NAME |
| 806 | #undef BITS_PER_PIXEL |
| 807 | |
| 808 | /* 16bpp cases */ |
| 809 | #define BITS_PER_PIXEL 16 |
| 810 | #define FUNCTION_NAME(base) base##_16_opx_trans |
| 811 | #include "34010gfx.inc" |
| 812 | #undef FUNCTION_NAME |
| 813 | #undef BITS_PER_PIXEL |
| 814 | |
| 815 | #undef TRANSPARENCY |
| 816 | #undef PIXEL_OP_REQUIRES_SOURCE |
| 817 | #undef PIXEL_OP_TIMING |
| 818 | #undef PIXEL_OP |
| 819 | |
| 820 | static const UINT8 pixelsize_lookup[32] = |
| 821 | { |
| 822 | 0,0,1,1,2,2,2,2,3,3,3,3,3,3,3,3,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4 |
| 823 | }; |
| 824 | |
| 825 | |
| 826 | void tms340x0_device::pixblt_b_l(UINT16 op) |
| 827 | { |
| 828 | int psize = pixelsize_lookup[IOREG(REG_PSIZE) & 0x1f]; |
| 829 | int trans = (IOREG(REG_CONTROL) & 0x20) >> 5; |
| 830 | int rop = (IOREG(REG_CONTROL) >> 10) & 0x1f; |
| 831 | int ix = trans | (rop << 1) | (psize << 6); |
| 832 | if (!P_FLAG()) LOGGFX(("%08X(%3d):PIXBLT B,L (%dx%d) depth=%d\n", m_pc, m_screen->vpos(), DYDX_X(), DYDX_Y(), IOREG(REG_PSIZE) ? IOREG(REG_PSIZE) : 32)); |
| 833 | m_pixel_op = s_pixel_op_table[rop]; |
| 834 | m_pixel_op_timing = s_pixel_op_timing_table[rop]; |
| 835 | (this->*s_pixblt_b_op_table[ix])(1); |
| 836 | } |
| 837 | |
| 838 | void tms340x0_device::pixblt_b_xy(UINT16 op) |
| 839 | { |
| 840 | int psize = pixelsize_lookup[IOREG(REG_PSIZE) & 0x1f]; |
| 841 | int trans = (IOREG(REG_CONTROL) & 0x20) >> 5; |
| 842 | int rop = (IOREG(REG_CONTROL) >> 10) & 0x1f; |
| 843 | int ix = trans | (rop << 1) | (psize << 6); |
| 844 | if (!P_FLAG()) LOGGFX(("%08X(%3d):PIXBLT B,XY (%d,%d) (%dx%d) depth=%d\n", m_pc, m_screen->vpos(), DADDR_X(), DADDR_Y(), DYDX_X(), DYDX_Y(), IOREG(REG_PSIZE) ? IOREG(REG_PSIZE) : 32)); |
| 845 | m_pixel_op = s_pixel_op_table[rop]; |
| 846 | m_pixel_op_timing = s_pixel_op_timing_table[rop]; |
| 847 | (this->*s_pixblt_b_op_table[ix])(0); |
| 848 | } |
| 849 | |
| 850 | void tms340x0_device::pixblt_l_l(UINT16 op) |
| 851 | { |
| 852 | int psize = pixelsize_lookup[IOREG(REG_PSIZE) & 0x1f]; |
| 853 | int trans = (IOREG(REG_CONTROL) & 0x20) >> 5; |
| 854 | int rop = (IOREG(REG_CONTROL) >> 10) & 0x1f; |
| 855 | int pbh = (IOREG(REG_CONTROL) >> 8) & 1; |
| 856 | int ix = trans | (rop << 1) | (psize << 6); |
| 857 | if (!P_FLAG()) LOGGFX(("%08X(%3d):PIXBLT L,L (%dx%d) depth=%d\n", m_pc, m_screen->vpos(), DYDX_X(), DYDX_Y(), IOREG(REG_PSIZE) ? IOREG(REG_PSIZE) : 32)); |
| 858 | m_pixel_op = s_pixel_op_table[rop]; |
| 859 | m_pixel_op_timing = s_pixel_op_timing_table[rop]; |
| 860 | if (!pbh) |
| 861 | (this->*s_pixblt_op_table[ix])(1, 1); |
| 862 | else |
| 863 | (this->*s_pixblt_r_op_table[ix])(1, 1); |
| 864 | } |
| 865 | |
| 866 | void tms340x0_device::pixblt_l_xy(UINT16 op) |
| 867 | { |
| 868 | int psize = pixelsize_lookup[IOREG(REG_PSIZE) & 0x1f]; |
| 869 | int trans = (IOREG(REG_CONTROL) & 0x20) >> 5; |
| 870 | int rop = (IOREG(REG_CONTROL) >> 10) & 0x1f; |
| 871 | int pbh = (IOREG(REG_CONTROL) >> 8) & 1; |
| 872 | int ix = trans | (rop << 1) | (psize << 6); |
| 873 | if (!P_FLAG()) LOGGFX(("%08X(%3d):PIXBLT L,XY (%d,%d) (%dx%d) depth=%d\n", m_pc, m_screen->vpos(), DADDR_X(), DADDR_Y(), DYDX_X(), DYDX_Y(), IOREG(REG_PSIZE) ? IOREG(REG_PSIZE) : 32)); |
| 874 | m_pixel_op = s_pixel_op_table[rop]; |
| 875 | m_pixel_op_timing = s_pixel_op_timing_table[rop]; |
| 876 | if (!pbh) |
| 877 | (this->*s_pixblt_op_table[ix])(1, 0); |
| 878 | else |
| 879 | (this->*s_pixblt_r_op_table[ix])(1, 0); |
| 880 | } |
| 881 | |
| 882 | void tms340x0_device::pixblt_xy_l(UINT16 op) |
| 883 | { |
| 884 | int psize = pixelsize_lookup[IOREG(REG_PSIZE) & 0x1f]; |
| 885 | int trans = (IOREG(REG_CONTROL) & 0x20) >> 5; |
| 886 | int rop = (IOREG(REG_CONTROL) >> 10) & 0x1f; |
| 887 | int pbh = (IOREG(REG_CONTROL) >> 8) & 1; |
| 888 | int ix = trans | (rop << 1) | (psize << 6); |
| 889 | if (!P_FLAG()) LOGGFX(("%08X(%3d):PIXBLT XY,L (%dx%d) depth=%d\n", m_pc, m_screen->vpos(), DYDX_X(), DYDX_Y(), IOREG(REG_PSIZE) ? IOREG(REG_PSIZE) : 32)); |
| 890 | m_pixel_op = s_pixel_op_table[rop]; |
| 891 | m_pixel_op_timing = s_pixel_op_timing_table[rop]; |
| 892 | if (!pbh) |
| 893 | (this->*s_pixblt_op_table[ix])(0, 1); |
| 894 | else |
| 895 | (this->*s_pixblt_r_op_table[ix])(0, 1); |
| 896 | } |
| 897 | |
| 898 | void tms340x0_device::pixblt_xy_xy(UINT16 op) |
| 899 | { |
| 900 | int psize = pixelsize_lookup[IOREG(REG_PSIZE) & 0x1f]; |
| 901 | int trans = (IOREG(REG_CONTROL) & 0x20) >> 5; |
| 902 | int rop = (IOREG(REG_CONTROL) >> 10) & 0x1f; |
| 903 | int pbh = (IOREG(REG_CONTROL) >> 8) & 1; |
| 904 | int ix = trans | (rop << 1) | (psize << 6); |
| 905 | if (!P_FLAG()) LOGGFX(("%08X(%3d):PIXBLT XY,XY (%dx%d) depth=%d\n", m_pc, m_screen->vpos(), DYDX_X(), DYDX_Y(), IOREG(REG_PSIZE) ? IOREG(REG_PSIZE) : 32)); |
| 906 | m_pixel_op = s_pixel_op_table[rop]; |
| 907 | m_pixel_op_timing = s_pixel_op_timing_table[rop]; |
| 908 | if (!pbh) |
| 909 | (this->*s_pixblt_op_table[ix])(0, 0); |
| 910 | else |
| 911 | (this->*s_pixblt_r_op_table[ix])(0, 0); |
| 912 | } |
| 913 | |
| 914 | void tms340x0_device::fill_l(UINT16 op) |
| 915 | { |
| 916 | int psize = pixelsize_lookup[IOREG(REG_PSIZE) & 0x1f]; |
| 917 | int trans = (IOREG(REG_CONTROL) & 0x20) >> 5; |
| 918 | int rop = (IOREG(REG_CONTROL) >> 10) & 0x1f; |
| 919 | int ix = trans | (rop << 1) | (psize << 6); |
| 920 | if (!P_FLAG()) LOGGFX(("%08X(%3d):FILL L (%dx%d) depth=%d\n", m_pc, m_screen->vpos(), DYDX_X(), DYDX_Y(), IOREG(REG_PSIZE) ? IOREG(REG_PSIZE) : 32)); |
| 921 | m_pixel_op = s_pixel_op_table[rop]; |
| 922 | m_pixel_op_timing = s_pixel_op_timing_table[rop]; |
| 923 | (this->*s_fill_op_table[ix])(1); |
| 924 | } |
| 925 | |
| 926 | void tms340x0_device::fill_xy(UINT16 op) |
| 927 | { |
| 928 | int psize = pixelsize_lookup[IOREG(REG_PSIZE) & 0x1f]; |
| 929 | int trans = (IOREG(REG_CONTROL) & 0x20) >> 5; |
| 930 | int rop = (IOREG(REG_CONTROL) >> 10) & 0x1f; |
| 931 | int ix = trans | (rop << 1) | (psize << 6); |
| 932 | if (!P_FLAG()) LOGGFX(("%08X(%3d):FILL XY (%d,%d) (%dx%d) depth=%d\n", m_pc, m_screen->vpos(), DADDR_X(), DADDR_Y(), DYDX_X(), DYDX_Y(), IOREG(REG_PSIZE) ? IOREG(REG_PSIZE) : 32)); |
| 933 | m_pixel_op = s_pixel_op_table[rop]; |
| 934 | m_pixel_op_timing = s_pixel_op_timing_table[rop]; |
| 935 | (this->*s_fill_op_table[ix])(0); |
| 936 | } |
| 937 | |
| 938 | |
| 939 | #else |
| 940 | |
| 941 | |
| 942 | #undef PIXELS_PER_WORD |
| 943 | #undef PIXEL_MASK |
| 944 | |
| 945 | #define PIXELS_PER_WORD (16 / BITS_PER_PIXEL) |
| 946 | #define PIXEL_MASK ((1 << BITS_PER_PIXEL) - 1) |
| 947 | |
| 948 | void FUNCTION_NAME(tms340x0_device::pixblt)(int src_is_linear, int dst_is_linear) |
| 949 | { |
| 950 | /* if this is the first time through, perform the operation */ |
| 951 | if (!P_FLAG()) |
| 952 | { |
| 953 | int dx, dy, x, y, /*words,*/ yreverse; |
| 954 | word_write_func word_write; |
| 955 | word_read_func word_read; |
| 956 | UINT32 readwrites = 0; |
| 957 | UINT32 saddr, daddr; |
| 958 | XY dstxy = { 0 }; |
| 959 | |
| 960 | /* determine read/write functions */ |
| 961 | if (IOREG(REG_DPYCTL) & 0x0800) |
| 962 | { |
| 963 | word_write = &tms340x0_device::shiftreg_w; |
| 964 | word_read = &tms340x0_device::shiftreg_r; |
| 965 | } |
| 966 | else |
| 967 | { |
| 968 | word_write = &tms340x0_device::memory_w; |
| 969 | word_read = &tms340x0_device::memory_r; |
| 970 | } |
| 971 | |
| 972 | /* compute the starting addresses */ |
| 973 | saddr = src_is_linear ? SADDR() : SXYTOL(SADDR_XY()); |
| 974 | |
| 975 | /* compute the bounds of the operation */ |
| 976 | dx = (INT16)DYDX_X(); |
| 977 | dy = (INT16)DYDX_Y(); |
| 978 | |
| 979 | /* apply the window for non-linear destinations */ |
| 980 | m_gfxcycles = 7 + (src_is_linear ? 0 : 2); |
| 981 | if (!dst_is_linear) |
| 982 | { |
| 983 | dstxy = DADDR_XY(); |
| 984 | m_gfxcycles += 2 + (!src_is_linear) + apply_window("PIXBLT", BITS_PER_PIXEL, &saddr, &dstxy, &dx, &dy); |
| 985 | daddr = DXYTOL(dstxy); |
| 986 | } |
| 987 | else |
| 988 | daddr = DADDR(); |
| 989 | daddr &= ~(BITS_PER_PIXEL - 1); |
| 990 | LOGGFX((" saddr=%08X daddr=%08X sptch=%08X dptch=%08X\n", saddr, daddr, SPTCH(), DPTCH())); |
| 991 | |
| 992 | /* bail if we're clipped */ |
| 993 | if (dx <= 0 || dy <= 0) |
| 994 | return; |
| 995 | |
| 996 | /* window mode 1: just return and interrupt if we are within the window */ |
| 997 | if (WINDOW_CHECKING() == 1 && !dst_is_linear) |
| 998 | { |
| 999 | CLR_V(); |
| 1000 | DADDR_XY() = dstxy; |
| 1001 | DYDX_X() = dx; |
| 1002 | DYDX_Y() = dy; |
| 1003 | IOREG(REG_INTPEND) |= TMS34010_WV; |
| 1004 | check_interrupt(); |
| 1005 | return; |
| 1006 | } |
| 1007 | |
| 1008 | /* handle flipping the addresses */ |
| 1009 | yreverse = (IOREG(REG_CONTROL) >> 9) & 1; |
| 1010 | if (!src_is_linear || !dst_is_linear) |
| 1011 | { |
| 1012 | if (yreverse) |
| 1013 | { |
| 1014 | saddr += (dy - 1) * m_convsp; |
| 1015 | daddr += (dy - 1) * m_convdp; |
| 1016 | } |
| 1017 | } |
| 1018 | |
| 1019 | m_st |= STBIT_P; |
| 1020 | |
| 1021 | /* loop over rows */ |
| 1022 | for (y = 0; y < dy; y++) |
| 1023 | { |
| 1024 | UINT32 srcwordaddr = saddr >> 4; |
| 1025 | UINT32 dstwordaddr = daddr >> 4; |
| 1026 | UINT8 srcbit = saddr & 15; |
| 1027 | UINT8 dstbit = daddr & 15; |
| 1028 | UINT32 srcword, dstword = 0; |
| 1029 | |
| 1030 | /* fetch the initial source word */ |
| 1031 | srcword = (this->*word_read)(*m_program, srcwordaddr++ << 1); |
| 1032 | readwrites++; |
| 1033 | |
| 1034 | /* fetch the initial dest word */ |
| 1035 | if (PIXEL_OP_REQUIRES_SOURCE || TRANSPARENCY || (daddr & 0x0f) != 0) |
| 1036 | { |
| 1037 | dstword = (this->*word_read)(*m_program, dstwordaddr << 1); |
| 1038 | readwrites++; |
| 1039 | } |
| 1040 | |
| 1041 | /* loop over pixels */ |
| 1042 | for (x = 0; x < dx; x++) |
| 1043 | { |
| 1044 | UINT32 dstmask; |
| 1045 | UINT32 pixel; |
| 1046 | |
| 1047 | /* fetch more words if necessary */ |
| 1048 | if (srcbit + BITS_PER_PIXEL > 16) |
| 1049 | { |
| 1050 | srcword |= (this->*word_read)(*m_program, srcwordaddr++ << 1) << 16; |
| 1051 | readwrites++; |
| 1052 | } |
| 1053 | |
| 1054 | /* extract pixel from source */ |
| 1055 | pixel = (srcword >> srcbit) & PIXEL_MASK; |
| 1056 | srcbit += BITS_PER_PIXEL; |
| 1057 | if (srcbit > 16) |
| 1058 | { |
| 1059 | srcbit -= 16; |
| 1060 | srcword >>= 16; |
| 1061 | } |
| 1062 | |
| 1063 | /* fetch additional destination word if necessary */ |
| 1064 | if (PIXEL_OP_REQUIRES_SOURCE || TRANSPARENCY) |
| 1065 | if (dstbit + BITS_PER_PIXEL > 16) |
| 1066 | { |
| 1067 | dstword |= (this->*word_read)(*m_program, (dstwordaddr + 1) << 1) << 16; |
| 1068 | readwrites++; |
| 1069 | } |
| 1070 | |
| 1071 | /* apply pixel operations */ |
| 1072 | pixel <<= dstbit; |
| 1073 | dstmask = PIXEL_MASK << dstbit; |
| 1074 | PIXEL_OP(dstword, dstmask, pixel); |
| 1075 | if (!TRANSPARENCY || pixel != 0) |
| 1076 | dstword = (dstword & ~dstmask) | pixel; |
| 1077 | |
| 1078 | /* flush destination words */ |
| 1079 | dstbit += BITS_PER_PIXEL; |
| 1080 | if (dstbit > 16) |
| 1081 | { |
| 1082 | (this->*word_write)(*m_program, dstwordaddr++ << 1, dstword); |
| 1083 | readwrites++; |
| 1084 | dstbit -= 16; |
| 1085 | dstword >>= 16; |
| 1086 | } |
| 1087 | } |
| 1088 | |
| 1089 | /* flush any remaining words */ |
| 1090 | if (dstbit > 0) |
| 1091 | { |
| 1092 | /* if we're right-partial, read and mask the remaining bits */ |
| 1093 | if (dstbit != 16) |
| 1094 | { |
| 1095 | UINT16 origdst = (this->*word_read)(*m_program, dstwordaddr << 1); |
| 1096 | UINT16 mask = 0xffff << dstbit; |
| 1097 | dstword = (dstword & ~mask) | (origdst & mask); |
| 1098 | readwrites++; |
| 1099 | } |
| 1100 | |
| 1101 | (this->*word_write)(*m_program, dstwordaddr++ << 1, dstword); |
| 1102 | readwrites++; |
| 1103 | } |
| 1104 | |
| 1105 | |
| 1106 | |
| 1107 | #if 0 |
| 1108 | int left_partials, right_partials, full_words, bitshift, bitshift_alt; |
| 1109 | UINT16 srcword, srcmask, dstword, dstmask, pixel; |
| 1110 | UINT32 swordaddr, dwordaddr; |
| 1111 | |
| 1112 | /* determine the bit shift to get from source to dest */ |
| 1113 | bitshift = ((daddr & 15) - (saddr & 15)) & 15; |
| 1114 | bitshift_alt = (16 - bitshift) & 15; |
| 1115 | |
| 1116 | /* how many left and right partial pixels do we have? */ |
| 1117 | left_partials = (PIXELS_PER_WORD - ((daddr & 15) / BITS_PER_PIXEL)) & (PIXELS_PER_WORD - 1); |
| 1118 | right_partials = ((daddr + dx * BITS_PER_PIXEL) & 15) / BITS_PER_PIXEL; |
| 1119 | full_words = dx - left_partials - right_partials; |
| 1120 | if (full_words < 0) |
| 1121 | left_partials = dx, right_partials = full_words = 0; |
| 1122 | else |
| 1123 | full_words /= PIXELS_PER_WORD; |
| 1124 | |
| 1125 | /* compute cycles */ |
| 1126 | m_gfxcycles += compute_pixblt_cycles(left_partials, right_partials, full_words, PIXEL_OP_TIMING); |
| 1127 | |
| 1128 | /* use word addresses each row */ |
| 1129 | swordaddr = saddr >> 4; |
| 1130 | dwordaddr = daddr >> 4; |
| 1131 | |
| 1132 | /* fetch the initial source word */ |
| 1133 | srcword = (this->*word_read)(*m_program, swordaddr++ << 1); |
| 1134 | srcmask = PIXEL_MASK << (saddr & 15); |
| 1135 | |
| 1136 | /* handle the left partial word */ |
| 1137 | if (left_partials != 0) |
| 1138 | { |
| 1139 | /* fetch the destination word */ |
| 1140 | dstword = (this->*word_read)(*m_program, dwordaddr << 1); |
| 1141 | dstmask = PIXEL_MASK << (daddr & 15); |
| 1142 | |
| 1143 | /* loop over partials */ |
| 1144 | for (x = 0; x < left_partials; x++) |
| 1145 | { |
| 1146 | /* fetch another word if necessary */ |
| 1147 | if (srcmask == 0) |
| 1148 | { |
| 1149 | srcword = (this->*word_read)(*m_program, swordaddr++ << 1); |
| 1150 | srcmask = PIXEL_MASK; |
| 1151 | } |
| 1152 | |
| 1153 | /* process the pixel */ |
| 1154 | pixel = srcword & srcmask; |
| 1155 | if (dstmask > srcmask) |
| 1156 | pixel <<= bitshift; |
| 1157 | else |
| 1158 | pixel >>= bitshift_alt; |
| 1159 | PIXEL_OP(dstword, dstmask, pixel); |
| 1160 | if (!TRANSPARENCY || pixel != 0) |
| 1161 | dstword = (dstword & ~dstmask) | pixel; |
| 1162 | |
| 1163 | /* update the source */ |
| 1164 | srcmask <<= BITS_PER_PIXEL; |
| 1165 | |
| 1166 | /* update the destination */ |
| 1167 | dstmask <<= BITS_PER_PIXEL; |
| 1168 | } |
| 1169 | |
| 1170 | /* write the result */ |
| 1171 | (this->*word_write)(*m_program, dwordaddr++ << 1, dstword); |
| 1172 | } |
| 1173 | |
| 1174 | /* loop over full words */ |
| 1175 | for (words = 0; words < full_words; words++) |
| 1176 | { |
| 1177 | /* fetch the destination word (if necessary) */ |
| 1178 | if (PIXEL_OP_REQUIRES_SOURCE || TRANSPARENCY) |
| 1179 | dstword = (this->*word_read)(*m_program, dwordaddr << 1); |
| 1180 | else |
| 1181 | dstword = 0; |
| 1182 | dstmask = PIXEL_MASK; |
| 1183 | |
| 1184 | /* loop over partials */ |
| 1185 | for (x = 0; x < PIXELS_PER_WORD; x++) |
| 1186 | { |
| 1187 | /* fetch another word if necessary */ |
| 1188 | if (srcmask == 0) |
| 1189 | { |
| 1190 | srcword = (this->*word_read)(*m_program, swordaddr++ << 1); |
| 1191 | srcmask = PIXEL_MASK; |
| 1192 | } |
| 1193 | |
| 1194 | /* process the pixel */ |
| 1195 | pixel = srcword & srcmask; |
| 1196 | if (dstmask > srcmask) |
| 1197 | pixel <<= bitshift; |
| 1198 | else |
| 1199 | pixel >>= bitshift_alt; |
| 1200 | PIXEL_OP(dstword, dstmask, pixel); |
| 1201 | if (!TRANSPARENCY || pixel != 0) |
| 1202 | dstword = (dstword & ~dstmask) | pixel; |
| 1203 | |
| 1204 | /* update the source */ |
| 1205 | srcmask <<= BITS_PER_PIXEL; |
| 1206 | |
| 1207 | /* update the destination */ |
| 1208 | dstmask <<= BITS_PER_PIXEL; |
| 1209 | } |
| 1210 | |
| 1211 | /* write the result */ |
| 1212 | (this->*word_write)(*m_program, dwordaddr++ << 1, dstword); |
| 1213 | } |
| 1214 | |
| 1215 | /* handle the right partial word */ |
| 1216 | if (right_partials != 0) |
| 1217 | { |
| 1218 | /* fetch the destination word */ |
| 1219 | dstword = (this->*word_read)(*m_program, dwordaddr << 1); |
| 1220 | dstmask = PIXEL_MASK; |
| 1221 | |
| 1222 | /* loop over partials */ |
| 1223 | for (x = 0; x < right_partials; x++) |
| 1224 | { |
| 1225 | /* fetch another word if necessary */ |
| 1226 | if (srcmask == 0) |
| 1227 | { |
| 1228 | LOGGFX((" right fetch @ %08x\n", swordaddr)); |
| 1229 | srcword = (this->*word_read)(*m_program, swordaddr++ << 1); |
| 1230 | srcmask = PIXEL_MASK; |
| 1231 | } |
| 1232 | |
| 1233 | /* process the pixel */ |
| 1234 | pixel = srcword & srcmask; |
| 1235 | if (dstmask > srcmask) |
| 1236 | pixel <<= bitshift; |
| 1237 | else |
| 1238 | pixel >>= bitshift_alt; |
| 1239 | PIXEL_OP(dstword, dstmask, pixel); |
| 1240 | if (!TRANSPARENCY || pixel != 0) |
| 1241 | dstword = (dstword & ~dstmask) | pixel; |
| 1242 | |
| 1243 | /* update the source */ |
| 1244 | srcmask <<= BITS_PER_PIXEL; |
| 1245 | |
| 1246 | /* update the destination */ |
| 1247 | dstmask <<= BITS_PER_PIXEL; |
| 1248 | } |
| 1249 | |
| 1250 | /* write the result */ |
| 1251 | (this->*word_write)(*m_program, dwordaddr++ << 1, dstword); |
| 1252 | } |
| 1253 | #endif |
| 1254 | |
| 1255 | /* update for next row */ |
| 1256 | if (!yreverse) |
| 1257 | { |
| 1258 | saddr += SPTCH(); |
| 1259 | daddr += DPTCH(); |
| 1260 | } |
| 1261 | else |
| 1262 | { |
| 1263 | saddr -= SPTCH(); |
| 1264 | daddr -= DPTCH(); |
| 1265 | } |
| 1266 | } |
| 1267 | |
| 1268 | m_gfxcycles += readwrites * 2 + dx * dy * (PIXEL_OP_TIMING - 2); |
| 1269 | |
| 1270 | LOGGFX((" (%d cycles)\n", m_gfxcycles)); |
| 1271 | } |
| 1272 | |
| 1273 | /* eat cycles */ |
| 1274 | if (m_gfxcycles > m_icount) |
| 1275 | { |
| 1276 | m_gfxcycles -= m_icount; |
| 1277 | m_icount = 0; |
| 1278 | m_pc -= 0x10; |
| 1279 | } |
| 1280 | else |
| 1281 | { |
| 1282 | m_icount -= m_gfxcycles; |
| 1283 | m_st &= ~STBIT_P; |
| 1284 | if (src_is_linear && dst_is_linear) |
| 1285 | SADDR() += DYDX_Y() * SPTCH(); |
| 1286 | else if (src_is_linear) |
| 1287 | SADDR() += DYDX_Y() * SPTCH(); |
| 1288 | else |
| 1289 | SADDR_Y() += DYDX_Y(); |
| 1290 | if (dst_is_linear) |
| 1291 | DADDR() += DYDX_Y() * DPTCH(); |
| 1292 | else |
| 1293 | DADDR_Y() += DYDX_Y(); |
| 1294 | } |
| 1295 | } |
| 1296 | |
| 1297 | void FUNCTION_NAME(tms340x0_device::pixblt_r)(int src_is_linear, int dst_is_linear) |
| 1298 | { |
| 1299 | /* if this is the first time through, perform the operation */ |
| 1300 | if (!P_FLAG()) |
| 1301 | { |
| 1302 | int dx, dy, x, y, words, yreverse; |
| 1303 | word_write_func word_write; |
| 1304 | word_read_func word_read; |
| 1305 | UINT32 saddr, daddr; |
| 1306 | XY dstxy = { 0 }; |
| 1307 | |
| 1308 | /* determine read/write functions */ |
| 1309 | if (IOREG(REG_DPYCTL) & 0x0800) |
| 1310 | { |
| 1311 | word_write = &tms340x0_device::shiftreg_w; |
| 1312 | word_read = &tms340x0_device::shiftreg_r; |
| 1313 | } |
| 1314 | else |
| 1315 | { |
| 1316 | word_write = &tms340x0_device::memory_w; |
| 1317 | word_read = &tms340x0_device::memory_r; |
| 1318 | } |
| 1319 | |
| 1320 | /* compute the starting addresses */ |
| 1321 | saddr = src_is_linear ? SADDR() : SXYTOL(SADDR_XY()); |
| 1322 | if ((saddr & (BITS_PER_PIXEL - 1)) != 0) osd_printf_debug("PIXBLT_R%d with odd saddr\n", BITS_PER_PIXEL); |
| 1323 | saddr &= ~(BITS_PER_PIXEL - 1); |
| 1324 | |
| 1325 | /* compute the bounds of the operation */ |
| 1326 | dx = (INT16)DYDX_X(); |
| 1327 | dy = (INT16)DYDX_Y(); |
| 1328 | |
| 1329 | /* apply the window for non-linear destinations */ |
| 1330 | m_gfxcycles = 7 + (src_is_linear ? 0 : 2); |
| 1331 | if (!dst_is_linear) |
| 1332 | { |
| 1333 | dstxy = DADDR_XY(); |
| 1334 | m_gfxcycles += 2 + (!src_is_linear) + apply_window("PIXBLT R", BITS_PER_PIXEL, &saddr, &dstxy, &dx, &dy); |
| 1335 | daddr = DXYTOL(dstxy); |
| 1336 | } |
| 1337 | else |
| 1338 | daddr = DADDR(); |
| 1339 | if ((daddr & (BITS_PER_PIXEL - 1)) != 0) osd_printf_debug("PIXBLT_R%d with odd daddr\n", BITS_PER_PIXEL); |
| 1340 | daddr &= ~(BITS_PER_PIXEL - 1); |
| 1341 | LOGGFX((" saddr=%08X daddr=%08X sptch=%08X dptch=%08X\n", saddr, daddr, SPTCH(), DPTCH())); |
| 1342 | |
| 1343 | /* bail if we're clipped */ |
| 1344 | if (dx <= 0 || dy <= 0) |
| 1345 | return; |
| 1346 | |
| 1347 | /* window mode 1: just return and interrupt if we are within the window */ |
| 1348 | if (WINDOW_CHECKING() == 1 && !dst_is_linear) |
| 1349 | { |
| 1350 | CLR_V(); |
| 1351 | DADDR_XY() = dstxy; |
| 1352 | DYDX_X() = dx; |
| 1353 | DYDX_Y() = dy; |
| 1354 | IOREG(REG_INTPEND) |= TMS34010_WV; |
| 1355 | check_interrupt(); |
| 1356 | return; |
| 1357 | } |
| 1358 | |
| 1359 | /* handle flipping the addresses */ |
| 1360 | yreverse = (IOREG(REG_CONTROL) >> 9) & 1; |
| 1361 | if (!src_is_linear || !dst_is_linear) |
| 1362 | { |
| 1363 | saddr += dx * BITS_PER_PIXEL; |
| 1364 | daddr += dx * BITS_PER_PIXEL; |
| 1365 | if (yreverse) |
| 1366 | { |
| 1367 | saddr += (dy - 1) * m_convsp; |
| 1368 | daddr += (dy - 1) * m_convdp; |
| 1369 | } |
| 1370 | } |
| 1371 | |
| 1372 | m_st |= STBIT_P; |
| 1373 | |
| 1374 | /* loop over rows */ |
| 1375 | for (y = 0; y < dy; y++) |
| 1376 | { |
| 1377 | int left_partials, right_partials, full_words, bitshift, bitshift_alt; |
| 1378 | UINT16 srcword, srcmask, dstword, dstmask, pixel; |
| 1379 | UINT32 swordaddr, dwordaddr; |
| 1380 | |
| 1381 | /* determine the bit shift to get from source to dest */ |
| 1382 | bitshift = ((daddr & 15) - (saddr & 15)) & 15; |
| 1383 | bitshift_alt = (16 - bitshift) & 15; |
| 1384 | |
| 1385 | /* how many left and right partial pixels do we have? */ |
| 1386 | left_partials = (PIXELS_PER_WORD - (((daddr - dx * BITS_PER_PIXEL) & 15) / BITS_PER_PIXEL)) & (PIXELS_PER_WORD - 1); |
| 1387 | right_partials = (daddr & 15) / BITS_PER_PIXEL; |
| 1388 | full_words = dx - left_partials - right_partials; |
| 1389 | if (full_words < 0) |
| 1390 | right_partials = dx, left_partials = full_words = 0; |
| 1391 | else |
| 1392 | full_words /= PIXELS_PER_WORD; |
| 1393 | |
| 1394 | /* compute cycles */ |
| 1395 | m_gfxcycles += compute_pixblt_cycles(left_partials, right_partials, full_words, PIXEL_OP_TIMING); |
| 1396 | |
| 1397 | /* use word addresses each row */ |
| 1398 | swordaddr = (saddr + 15) >> 4; |
| 1399 | dwordaddr = (daddr + 15) >> 4; |
| 1400 | |
| 1401 | /* fetch the initial source word */ |
| 1402 | srcword = (this->*word_read)(*m_program, --swordaddr << 1); |
| 1403 | srcmask = PIXEL_MASK << ((saddr - BITS_PER_PIXEL) & 15); |
| 1404 | |
| 1405 | /* handle the right partial word */ |
| 1406 | if (right_partials != 0) |
| 1407 | { |
| 1408 | /* fetch the destination word */ |
| 1409 | dstword = (this->*word_read)(*m_program, --dwordaddr << 1); |
| 1410 | dstmask = PIXEL_MASK << ((daddr - BITS_PER_PIXEL) & 15); |
| 1411 | |
| 1412 | /* loop over partials */ |
| 1413 | for (x = 0; x < right_partials; x++) |
| 1414 | { |
| 1415 | /* fetch source pixel if necessary */ |
| 1416 | if (srcmask == 0) |
| 1417 | { |
| 1418 | srcword = (this->*word_read)(*m_program, --swordaddr << 1); |
| 1419 | srcmask = PIXEL_MASK << (16 - BITS_PER_PIXEL); |
| 1420 | } |
| 1421 | |
| 1422 | /* process the pixel */ |
| 1423 | pixel = srcword & srcmask; |
| 1424 | if (dstmask > srcmask) |
| 1425 | pixel <<= bitshift; |
| 1426 | else |
| 1427 | pixel >>= bitshift_alt; |
| 1428 | PIXEL_OP(dstword, dstmask, pixel); |
| 1429 | if (!TRANSPARENCY || pixel != 0) |
| 1430 | dstword = (dstword & ~dstmask) | pixel; |
| 1431 | |
| 1432 | #if (BITS_PER_PIXEL<16) |
| 1433 | /* update the source */ |
| 1434 | srcmask >>= BITS_PER_PIXEL; |
| 1435 | |
| 1436 | /* update the destination */ |
| 1437 | dstmask >>= BITS_PER_PIXEL; |
| 1438 | #else |
| 1439 | srcmask = 0; |
| 1440 | dstmask = 0; |
| 1441 | #endif |
| 1442 | } |
| 1443 | |
| 1444 | /* write the result */ |
| 1445 | (this->*word_write)(*m_program, dwordaddr << 1, dstword); |
| 1446 | } |
| 1447 | |
| 1448 | /* loop over full words */ |
| 1449 | for (words = 0; words < full_words; words++) |
| 1450 | { |
| 1451 | /* fetch the destination word (if necessary) */ |
| 1452 | dwordaddr--; |
| 1453 | if (PIXEL_OP_REQUIRES_SOURCE || TRANSPARENCY) |
| 1454 | dstword = (this->*word_read)(*m_program, dwordaddr << 1); |
| 1455 | else |
| 1456 | dstword = 0; |
| 1457 | dstmask = PIXEL_MASK << (16 - BITS_PER_PIXEL); |
| 1458 | |
| 1459 | /* loop over partials */ |
| 1460 | for (x = 0; x < PIXELS_PER_WORD; x++) |
| 1461 | { |
| 1462 | /* fetch source pixel if necessary */ |
| 1463 | if (srcmask == 0) |
| 1464 | { |
| 1465 | srcword = (this->*word_read)(*m_program, --swordaddr << 1); |
| 1466 | srcmask = PIXEL_MASK << (16 - BITS_PER_PIXEL); |
| 1467 | } |
| 1468 | |
| 1469 | /* process the pixel */ |
| 1470 | pixel = srcword & srcmask; |
| 1471 | if (dstmask > srcmask) |
| 1472 | pixel <<= bitshift; |
| 1473 | else |
| 1474 | pixel >>= bitshift_alt; |
| 1475 | PIXEL_OP(dstword, dstmask, pixel); |
| 1476 | if (!TRANSPARENCY || pixel != 0) |
| 1477 | dstword = (dstword & ~dstmask) | pixel; |
| 1478 | |
| 1479 | #if (BITS_PER_PIXEL<16) |
| 1480 | /* update the source */ |
| 1481 | srcmask >>= BITS_PER_PIXEL; |
| 1482 | |
| 1483 | /* update the destination */ |
| 1484 | dstmask >>= BITS_PER_PIXEL; |
| 1485 | #else |
| 1486 | srcmask = 0; |
| 1487 | dstmask = 0; |
| 1488 | #endif |
| 1489 | } |
| 1490 | |
| 1491 | /* write the result */ |
| 1492 | (this->*word_write)(*m_program, dwordaddr << 1, dstword); |
| 1493 | } |
| 1494 | |
| 1495 | /* handle the left partial word */ |
| 1496 | if (left_partials != 0) |
| 1497 | { |
| 1498 | /* fetch the destination word */ |
| 1499 | dstword = (this->*word_read)(*m_program, --dwordaddr << 1); |
| 1500 | dstmask = PIXEL_MASK << (16 - BITS_PER_PIXEL); |
| 1501 | |
| 1502 | /* loop over partials */ |
| 1503 | for (x = 0; x < left_partials; x++) |
| 1504 | { |
| 1505 | /* fetch the source pixel if necessary */ |
| 1506 | if (srcmask == 0) |
| 1507 | { |
| 1508 | srcword = (this->*word_read)(*m_program, --swordaddr << 1); |
| 1509 | srcmask = PIXEL_MASK << (16 - BITS_PER_PIXEL); |
| 1510 | } |
| 1511 | |
| 1512 | /* process the pixel */ |
| 1513 | pixel = srcword & srcmask; |
| 1514 | if (dstmask > srcmask) |
| 1515 | pixel <<= bitshift; |
| 1516 | else |
| 1517 | pixel >>= bitshift_alt; |
| 1518 | PIXEL_OP(dstword, dstmask, pixel); |
| 1519 | if (!TRANSPARENCY || pixel != 0) |
| 1520 | dstword = (dstword & ~dstmask) | pixel; |
| 1521 | |
| 1522 | #if (BITS_PER_PIXEL<16) |
| 1523 | /* update the source */ |
| 1524 | srcmask >>= BITS_PER_PIXEL; |
| 1525 | |
| 1526 | /* update the destination */ |
| 1527 | dstmask >>= BITS_PER_PIXEL; |
| 1528 | #else |
| 1529 | srcmask = 0; |
| 1530 | dstmask = 0; |
| 1531 | #endif |
| 1532 | } |
| 1533 | |
| 1534 | /* write the result */ |
| 1535 | (this->*word_write)(*m_program, dwordaddr << 1, dstword); |
| 1536 | } |
| 1537 | |
| 1538 | /* update for next row */ |
| 1539 | if (!yreverse) |
| 1540 | { |
| 1541 | saddr += SPTCH(); |
| 1542 | daddr += DPTCH(); |
| 1543 | } |
| 1544 | else |
| 1545 | { |
| 1546 | saddr -= SPTCH(); |
| 1547 | daddr -= DPTCH(); |
| 1548 | } |
| 1549 | } |
| 1550 | LOGGFX((" (%d cycles)\n", m_gfxcycles)); |
| 1551 | } |
| 1552 | |
| 1553 | /* eat cycles */ |
| 1554 | if (m_gfxcycles > m_icount) |
| 1555 | { |
| 1556 | m_gfxcycles -= m_icount; |
| 1557 | m_icount = 0; |
| 1558 | m_pc -= 0x10; |
| 1559 | } |
| 1560 | else |
| 1561 | { |
| 1562 | m_icount -= m_gfxcycles; |
| 1563 | m_st &= ~STBIT_P; |
| 1564 | if (src_is_linear && dst_is_linear) |
| 1565 | SADDR() += DYDX_Y() * SPTCH(); |
| 1566 | else if (src_is_linear) |
| 1567 | SADDR() += DYDX_Y() * SPTCH(); |
| 1568 | else |
| 1569 | SADDR_Y() += DYDX_Y(); |
| 1570 | if (dst_is_linear) |
| 1571 | DADDR() += DYDX_Y() * DPTCH(); |
| 1572 | else |
| 1573 | DADDR_Y() += DYDX_Y(); |
| 1574 | } |
| 1575 | } |
| 1576 | |
| 1577 | void FUNCTION_NAME(tms340x0_device::pixblt_b)(int dst_is_linear) |
| 1578 | { |
| 1579 | /* if this is the first time through, perform the operation */ |
| 1580 | if (!P_FLAG()) |
| 1581 | { |
| 1582 | int dx, dy, x, y, words, left_partials, right_partials, full_words; |
| 1583 | word_write_func word_write; |
| 1584 | word_read_func word_read; |
| 1585 | UINT32 saddr, daddr; |
| 1586 | XY dstxy = { 0 }; |
| 1587 | |
| 1588 | /* determine read/write functions */ |
| 1589 | if (IOREG(REG_DPYCTL) & 0x0800) |
| 1590 | { |
| 1591 | word_write = &tms340x0_device::shiftreg_w; |
| 1592 | word_read = &tms340x0_device::shiftreg_r; |
| 1593 | } |
| 1594 | else |
| 1595 | { |
| 1596 | word_write = &tms340x0_device::memory_w; |
| 1597 | word_read = &tms340x0_device::memory_r; |
| 1598 | } |
| 1599 | |
| 1600 | /* compute the starting addresses */ |
| 1601 | saddr = SADDR(); |
| 1602 | |
| 1603 | /* compute the bounds of the operation */ |
| 1604 | dx = (INT16)DYDX_X(); |
| 1605 | dy = (INT16)DYDX_Y(); |
| 1606 | |
| 1607 | /* apply the window for non-linear destinations */ |
| 1608 | m_gfxcycles = 4; |
| 1609 | if (!dst_is_linear) |
| 1610 | { |
| 1611 | dstxy = DADDR_XY(); |
| 1612 | m_gfxcycles += 2 + apply_window("PIXBLT B", 1, &saddr, &dstxy, &dx, &dy); |
| 1613 | daddr = DXYTOL(dstxy); |
| 1614 | } |
| 1615 | else |
| 1616 | daddr = DADDR(); |
| 1617 | daddr &= ~(BITS_PER_PIXEL - 1); |
| 1618 | LOGGFX((" saddr=%08X daddr=%08X sptch=%08X dptch=%08X\n", saddr, daddr, SPTCH(), DPTCH())); |
| 1619 | |
| 1620 | /* bail if we're clipped */ |
| 1621 | if (dx <= 0 || dy <= 0) |
| 1622 | return; |
| 1623 | |
| 1624 | /* window mode 1: just return and interrupt if we are within the window */ |
| 1625 | if (WINDOW_CHECKING() == 1 && !dst_is_linear) |
| 1626 | { |
| 1627 | CLR_V(); |
| 1628 | DADDR_XY() = dstxy; |
| 1629 | DYDX_X() = dx; |
| 1630 | DYDX_Y() = dy; |
| 1631 | IOREG(REG_INTPEND) |= TMS34010_WV; |
| 1632 | check_interrupt(); |
| 1633 | return; |
| 1634 | } |
| 1635 | |
| 1636 | /* how many left and right partial pixels do we have? */ |
| 1637 | left_partials = (PIXELS_PER_WORD - ((daddr & 15) / BITS_PER_PIXEL)) & (PIXELS_PER_WORD - 1); |
| 1638 | right_partials = ((daddr + dx * BITS_PER_PIXEL) & 15) / BITS_PER_PIXEL; |
| 1639 | full_words = dx - left_partials - right_partials; |
| 1640 | if (full_words < 0) |
| 1641 | left_partials = dx, right_partials = full_words = 0; |
| 1642 | else |
| 1643 | full_words /= PIXELS_PER_WORD; |
| 1644 | |
| 1645 | /* compute cycles */ |
| 1646 | m_gfxcycles += compute_pixblt_b_cycles(left_partials, right_partials, full_words, dy, PIXEL_OP_TIMING, BITS_PER_PIXEL); |
| 1647 | m_st |= STBIT_P; |
| 1648 | |
| 1649 | /* loop over rows */ |
| 1650 | for (y = 0; y < dy; y++) |
| 1651 | { |
| 1652 | UINT16 srcword, srcmask, dstword, dstmask, pixel; |
| 1653 | UINT32 swordaddr, dwordaddr; |
| 1654 | |
| 1655 | /* use byte addresses each row */ |
| 1656 | swordaddr = saddr >> 4; |
| 1657 | dwordaddr = daddr >> 4; |
| 1658 | |
| 1659 | /* fetch the initial source word */ |
| 1660 | srcword = (this->*word_read)(*m_program, swordaddr++ << 1); |
| 1661 | srcmask = 1 << (saddr & 15); |
| 1662 | |
| 1663 | /* handle the left partial word */ |
| 1664 | if (left_partials != 0) |
| 1665 | { |
| 1666 | /* fetch the destination word */ |
| 1667 | dstword = (this->*word_read)(*m_program, dwordaddr << 1); |
| 1668 | dstmask = PIXEL_MASK << (daddr & 15); |
| 1669 | |
| 1670 | /* loop over partials */ |
| 1671 | for (x = 0; x < left_partials; x++) |
| 1672 | { |
| 1673 | /* process the pixel */ |
| 1674 | pixel = (srcword & srcmask) ? COLOR1() : COLOR0(); |
| 1675 | pixel &= dstmask; |
| 1676 | PIXEL_OP(dstword, dstmask, pixel); |
| 1677 | if (!TRANSPARENCY || pixel != 0) |
| 1678 | dstword = (dstword & ~dstmask) | pixel; |
| 1679 | |
| 1680 | /* update the source */ |
| 1681 | srcmask <<= 1; |
| 1682 | if (srcmask == 0) |
| 1683 | { |
| 1684 | srcword = (this->*word_read)(*m_program, swordaddr++ << 1); |
| 1685 | srcmask = 0x0001; |
| 1686 | } |
| 1687 | |
| 1688 | /* update the destination */ |
| 1689 | dstmask = dstmask << BITS_PER_PIXEL; |
| 1690 | } |
| 1691 | |
| 1692 | /* write the result */ |
| 1693 | (this->*word_write)(*m_program, dwordaddr++ << 1, dstword); |
| 1694 | } |
| 1695 | |
| 1696 | /* loop over full words */ |
| 1697 | for (words = 0; words < full_words; words++) |
| 1698 | { |
| 1699 | /* fetch the destination word (if necessary) */ |
| 1700 | if (PIXEL_OP_REQUIRES_SOURCE || TRANSPARENCY) |
| 1701 | dstword = (this->*word_read)(*m_program, dwordaddr << 1); |
| 1702 | else |
| 1703 | dstword = 0; |
| 1704 | dstmask = PIXEL_MASK; |
| 1705 | |
| 1706 | /* loop over partials */ |
| 1707 | for (x = 0; x < PIXELS_PER_WORD; x++) |
| 1708 | { |
| 1709 | /* process the pixel */ |
| 1710 | pixel = (srcword & srcmask) ? COLOR1() : COLOR0(); |
| 1711 | pixel &= dstmask; |
| 1712 | PIXEL_OP(dstword, dstmask, pixel); |
| 1713 | if (!TRANSPARENCY || pixel != 0) |
| 1714 | dstword = (dstword & ~dstmask) | pixel; |
| 1715 | |
| 1716 | /* update the source */ |
| 1717 | srcmask <<= 1; |
| 1718 | if (srcmask == 0) |
| 1719 | { |
| 1720 | srcword = (this->*word_read)(*m_program, swordaddr++ << 1); |
| 1721 | srcmask = 0x0001; |
| 1722 | } |
| 1723 | |
| 1724 | /* update the destination */ |
| 1725 | dstmask = dstmask << BITS_PER_PIXEL; |
| 1726 | } |
| 1727 | |
| 1728 | /* write the result */ |
| 1729 | (this->*word_write)(*m_program, dwordaddr++ << 1, dstword); |
| 1730 | } |
| 1731 | |
| 1732 | /* handle the right partial word */ |
| 1733 | if (right_partials != 0) |
| 1734 | { |
| 1735 | /* fetch the destination word */ |
| 1736 | dstword = (this->*word_read)(*m_program, dwordaddr << 1); |
| 1737 | dstmask = PIXEL_MASK; |
| 1738 | |
| 1739 | /* loop over partials */ |
| 1740 | for (x = 0; x < right_partials; x++) |
| 1741 | { |
| 1742 | /* process the pixel */ |
| 1743 | pixel = (srcword & srcmask) ? COLOR1() : COLOR0(); |
| 1744 | pixel &= dstmask; |
| 1745 | PIXEL_OP(dstword, dstmask, pixel); |
| 1746 | if (!TRANSPARENCY || pixel != 0) |
| 1747 | dstword = (dstword & ~dstmask) | pixel; |
| 1748 | |
| 1749 | /* update the source */ |
| 1750 | srcmask <<= 1; |
| 1751 | if (srcmask == 0) |
| 1752 | { |
| 1753 | srcword = (this->*word_read)(*m_program, swordaddr++ << 1); |
| 1754 | srcmask = 0x0001; |
| 1755 | } |
| 1756 | |
| 1757 | /* update the destination */ |
| 1758 | dstmask = dstmask << BITS_PER_PIXEL; |
| 1759 | } |
| 1760 | |
| 1761 | /* write the result */ |
| 1762 | (this->*word_write)(*m_program, dwordaddr++ << 1, dstword); |
| 1763 | } |
| 1764 | |
| 1765 | /* update for next row */ |
| 1766 | saddr += SPTCH(); |
| 1767 | daddr += DPTCH(); |
| 1768 | } |
| 1769 | LOGGFX((" (%d cycles)\n", m_gfxcycles)); |
| 1770 | } |
| 1771 | |
| 1772 | /* eat cycles */ |
| 1773 | if (m_gfxcycles > m_icount) |
| 1774 | { |
| 1775 | m_gfxcycles -= m_icount; |
| 1776 | m_icount = 0; |
| 1777 | m_pc -= 0x10; |
| 1778 | } |
| 1779 | else |
| 1780 | { |
| 1781 | m_icount -= m_gfxcycles; |
| 1782 | m_st &= ~STBIT_P; |
| 1783 | SADDR() += DYDX_Y() * SPTCH(); |
| 1784 | if (dst_is_linear) |
| 1785 | DADDR() += DYDX_Y() * DPTCH(); |
| 1786 | else |
| 1787 | DADDR_Y() += DYDX_Y(); |
| 1788 | } |
| 1789 | } |
| 1790 | |
| 1791 | void FUNCTION_NAME(tms340x0_device::fill)(int dst_is_linear) |
| 1792 | { |
| 1793 | /* if this is the first time through, perform the operation */ |
| 1794 | if (!P_FLAG()) |
| 1795 | { |
| 1796 | int dx, dy, x, y, words, left_partials, right_partials, full_words; |
| 1797 | word_write_func word_write; |
| 1798 | word_read_func word_read; |
| 1799 | UINT32 daddr; |
| 1800 | XY dstxy = { 0 }; |
| 1801 | |
| 1802 | /* determine read/write functions */ |
| 1803 | if (IOREG(REG_DPYCTL) & 0x0800) |
| 1804 | { |
| 1805 | word_write = &tms340x0_device::shiftreg_w; |
| 1806 | word_read = &tms340x0_device::dummy_shiftreg_r; |
| 1807 | } |
| 1808 | else |
| 1809 | { |
| 1810 | word_write = &tms340x0_device::memory_w; |
| 1811 | word_read = &tms340x0_device::memory_r; |
| 1812 | } |
| 1813 | |
| 1814 | /* compute the bounds of the operation */ |
| 1815 | dx = (INT16)DYDX_X(); |
| 1816 | dy = (INT16)DYDX_Y(); |
| 1817 | |
| 1818 | /* apply the window for non-linear destinations */ |
| 1819 | m_gfxcycles = 4; |
| 1820 | if (!dst_is_linear) |
| 1821 | { |
| 1822 | dstxy = DADDR_XY(); |
| 1823 | m_gfxcycles += 2 + apply_window("FILL", 0, NULL, &dstxy, &dx, &dy); |
| 1824 | daddr = DXYTOL(dstxy); |
| 1825 | } |
| 1826 | else |
| 1827 | daddr = DADDR(); |
| 1828 | daddr &= ~(BITS_PER_PIXEL - 1); |
| 1829 | LOGGFX((" daddr=%08X\n", daddr)); |
| 1830 | |
| 1831 | /* bail if we're clipped */ |
| 1832 | if (dx <= 0 || dy <= 0) |
| 1833 | return; |
| 1834 | |
| 1835 | /* window mode 1: just return and interrupt if we are within the window */ |
| 1836 | if (WINDOW_CHECKING() == 1 && !dst_is_linear) |
| 1837 | { |
| 1838 | CLR_V(); |
| 1839 | DADDR_XY() = dstxy; |
| 1840 | DYDX_X() = dx; |
| 1841 | DYDX_Y() = dy; |
| 1842 | IOREG(REG_INTPEND) |= TMS34010_WV; |
| 1843 | check_interrupt(); |
| 1844 | return; |
| 1845 | } |
| 1846 | |
| 1847 | /* how many left and right partial pixels do we have? */ |
| 1848 | left_partials = (PIXELS_PER_WORD - ((daddr & 15) / BITS_PER_PIXEL)) & (PIXELS_PER_WORD - 1); |
| 1849 | right_partials = ((daddr + dx * BITS_PER_PIXEL) & 15) / BITS_PER_PIXEL; |
| 1850 | full_words = dx - left_partials - right_partials; |
| 1851 | if (full_words < 0) |
| 1852 | left_partials = dx, right_partials = full_words = 0; |
| 1853 | else |
| 1854 | full_words /= PIXELS_PER_WORD; |
| 1855 | |
| 1856 | /* compute cycles */ |
| 1857 | m_gfxcycles += 2; |
| 1858 | m_st |= STBIT_P; |
| 1859 | |
| 1860 | /* loop over rows */ |
| 1861 | for (y = 0; y < dy; y++) |
| 1862 | { |
| 1863 | UINT16 dstword, dstmask, pixel; |
| 1864 | UINT32 dwordaddr; |
| 1865 | |
| 1866 | /* use byte addresses each row */ |
| 1867 | dwordaddr = daddr >> 4; |
| 1868 | |
| 1869 | /* compute cycles */ |
| 1870 | m_gfxcycles += compute_fill_cycles(left_partials, right_partials, full_words, PIXEL_OP_TIMING); |
| 1871 | |
| 1872 | /* handle the left partial word */ |
| 1873 | if (left_partials != 0) |
| 1874 | { |
| 1875 | /* fetch the destination word */ |
| 1876 | dstword = (this->*word_read)(*m_program, dwordaddr << 1); |
| 1877 | dstmask = PIXEL_MASK << (daddr & 15); |
| 1878 | |
| 1879 | /* loop over partials */ |
| 1880 | for (x = 0; x < left_partials; x++) |
| 1881 | { |
| 1882 | /* process the pixel */ |
| 1883 | pixel = COLOR1() & dstmask; |
| 1884 | PIXEL_OP(dstword, dstmask, pixel); |
| 1885 | if (!TRANSPARENCY || pixel != 0) |
| 1886 | dstword = (dstword & ~dstmask) | pixel; |
| 1887 | |
| 1888 | /* update the destination */ |
| 1889 | dstmask = dstmask << BITS_PER_PIXEL; |
| 1890 | } |
| 1891 | |
| 1892 | /* write the result */ |
| 1893 | (this->*word_write)(*m_program, dwordaddr++ << 1, dstword); |
| 1894 | } |
| 1895 | |
| 1896 | /* loop over full words */ |
| 1897 | for (words = 0; words < full_words; words++) |
| 1898 | { |
| 1899 | /* fetch the destination word (if necessary) */ |
| 1900 | if (PIXEL_OP_REQUIRES_SOURCE || TRANSPARENCY) |
| 1901 | dstword = (this->*word_read)(*m_program, dwordaddr << 1); |
| 1902 | else |
| 1903 | dstword = 0; |
| 1904 | dstmask = PIXEL_MASK; |
| 1905 | |
| 1906 | /* loop over partials */ |
| 1907 | for (x = 0; x < PIXELS_PER_WORD; x++) |
| 1908 | { |
| 1909 | /* process the pixel */ |
| 1910 | pixel = COLOR1() & dstmask; |
| 1911 | PIXEL_OP(dstword, dstmask, pixel); |
| 1912 | if (!TRANSPARENCY || pixel != 0) |
| 1913 | dstword = (dstword & ~dstmask) | pixel; |
| 1914 | |
| 1915 | /* update the destination */ |
| 1916 | dstmask = dstmask << BITS_PER_PIXEL; |
| 1917 | } |
| 1918 | |
| 1919 | /* write the result */ |
| 1920 | (this->*word_write)(*m_program, dwordaddr++ << 1, dstword); |
| 1921 | } |
| 1922 | |
| 1923 | /* handle the right partial word */ |
| 1924 | if (right_partials != 0) |
| 1925 | { |
| 1926 | /* fetch the destination word */ |
| 1927 | dstword = (this->*word_read)(*m_program, dwordaddr << 1); |
| 1928 | dstmask = PIXEL_MASK; |
| 1929 | |
| 1930 | /* loop over partials */ |
| 1931 | for (x = 0; x < right_partials; x++) |
| 1932 | { |
| 1933 | /* process the pixel */ |
| 1934 | pixel = COLOR1() & dstmask; |
| 1935 | PIXEL_OP(dstword, dstmask, pixel); |
| 1936 | if (!TRANSPARENCY || pixel != 0) |
| 1937 | dstword = (dstword & ~dstmask) | pixel; |
| 1938 | |
| 1939 | /* update the destination */ |
| 1940 | dstmask = dstmask << BITS_PER_PIXEL; |
| 1941 | } |
| 1942 | |
| 1943 | /* write the result */ |
| 1944 | (this->*word_write)(*m_program, dwordaddr++ << 1, dstword); |
| 1945 | } |
| 1946 | |
| 1947 | /* update for next row */ |
| 1948 | daddr += DPTCH(); |
| 1949 | } |
| 1950 | |
| 1951 | LOGGFX((" (%d cycles)\n", m_gfxcycles)); |
| 1952 | } |
| 1953 | |
| 1954 | /* eat cycles */ |
| 1955 | if (m_gfxcycles > m_icount) |
| 1956 | { |
| 1957 | m_gfxcycles -= m_icount; |
| 1958 | m_icount = 0; |
| 1959 | m_pc -= 0x10; |
| 1960 | } |
| 1961 | else |
| 1962 | { |
| 1963 | m_icount -= m_gfxcycles; |
| 1964 | m_st &= ~STBIT_P; |
| 1965 | if (dst_is_linear) |
| 1966 | DADDR() += DYDX_Y() * DPTCH(); |
| 1967 | else |
| 1968 | DADDR_Y() += DYDX_Y(); |
| 1969 | } |
| 1970 | } |
| 1971 | |
| 1972 | #endif |
trunk/src/devices/cpu/tms34010/34010ops.cpp
| r250221 | r250222 | |
|---|
| 1 | | // license:BSD-3-Clause |
| 2 | | // copyright-holders:Alex Pasadyn,Zsolt Vasvari |
| 3 | | /*************************************************************************** |
| 4 | | |
| 5 | | TMS34010: Portable Texas Instruments TMS34010 emulator |
| 6 | | |
| 7 | | Copyright Alex Pasadyn/Zsolt Vasvari |
| 8 | | Parts based on code by Aaron Giles |
| 9 | | |
| 10 | | ***************************************************************************/ |
| 11 | | |
| 12 | | |
| 13 | | |
| 14 | | /*************************************************************************** |
| 15 | | MISC MACROS |
| 16 | | ***************************************************************************/ |
| 17 | | |
| 18 | | #define ZEXTEND(val,width) if (width) (val) &= ((UINT32)0xffffffff >> (32 - (width))) |
| 19 | | #define SEXTEND(val,width) if (width) (val) = (INT32)((val) << (32 - (width))) >> (32 - (width)) |
| 20 | | |
| 21 | | #define SXYTOL(val) ((((INT16)(val).y * m_convsp) + ((INT16)(val).x << m_pixelshift)) + OFFSET()) |
| 22 | | #define DXYTOL(val) ((((INT16)(val).y * m_convdp) + ((INT16)(val).x << m_pixelshift)) + OFFSET()) |
| 23 | | #define MXYTOL(val) ((((INT16)(val).y * m_convmp) + ((INT16)(val).x << m_pixelshift)) + OFFSET()) |
| 24 | | |
| 25 | | #define COUNT_CYCLES(x) m_icount -= x |
| 26 | | #define COUNT_UNKNOWN_CYCLES(x) COUNT_CYCLES(x) |
| 27 | | |
| 28 | | #define CORRECT_ODD_PC(x) do { if (m_pc & 0x0f) logerror("%s to PC=%08X\n", x, m_pc); m_pc &= ~0x0f; } while (0) |
| 29 | | |
| 30 | | |
| 31 | | |
| 32 | | /*************************************************************************** |
| 33 | | FLAG HANDLING MACROS |
| 34 | | ***************************************************************************/ |
| 35 | | |
| 36 | | #define SIGN(val) ((val) & 0x80000000) |
| 37 | | |
| 38 | | #define CLR_Z() m_st &= ~STBIT_Z |
| 39 | | #define CLR_V() m_st &= ~STBIT_V |
| 40 | | #define CLR_C() m_st &= ~STBIT_C |
| 41 | | #define CLR_N() m_st &= ~STBIT_N |
| 42 | | #define CLR_NZ() m_st &= ~(STBIT_N | STBIT_Z) |
| 43 | | #define CLR_CZ() m_st &= ~(STBIT_C | STBIT_Z) |
| 44 | | #define CLR_ZV() m_st &= ~(STBIT_Z | STBIT_V) |
| 45 | | #define CLR_NZV() m_st &= ~(STBIT_N | STBIT_Z | STBIT_V) |
| 46 | | #define CLR_NCZ() m_st &= ~(STBIT_N | STBIT_C | STBIT_Z) |
| 47 | | #define CLR_NCZV() m_st &= ~(STBIT_N | STBIT_C | STBIT_Z | STBIT_V) |
| 48 | | |
| 49 | | #define SET_V_BIT_LO(val,bit) m_st |= ((val) << (28 - (bit))) & STBIT_V |
| 50 | | #define SET_V_BIT_HI(val,bit) m_st |= ((val) >> ((bit) - 28)) & STBIT_V |
| 51 | | #define SET_V_LOG(val) m_st |= (val) << 28 |
| 52 | | #define SET_Z_BIT_LO(val,bit) m_st |= ((val) << (29 - (bit))) & STBIT_Z |
| 53 | | #define SET_Z_BIT_HI(val,bit) m_st |= ((val) >> ((bit) - 29)) & STBIT_Z |
| 54 | | #define SET_Z_LOG(val) m_st |= (val) << 29 |
| 55 | | #define SET_C_BIT_LO(val,bit) m_st |= ((val) << (30 - (bit))) & STBIT_C |
| 56 | | #define SET_C_BIT_HI(val,bit) m_st |= ((val) >> ((bit) - 30)) & STBIT_C |
| 57 | | #define SET_C_LOG(val) m_st |= (val) << 30 |
| 58 | | #define SET_N_BIT(val,bit) m_st |= ((val) << (31 - (bit))) & STBIT_N |
| 59 | | #define SET_N_LOG(val) m_st |= (val) << 31 |
| 60 | | |
| 61 | | #define SET_Z_VAL(val) SET_Z_LOG((val) == 0) |
| 62 | | #define SET_N_VAL(val) SET_N_BIT(val, 31) |
| 63 | | #define SET_NZ_VAL(val) SET_Z_VAL(val); SET_N_VAL(val) |
| 64 | | #define SET_V_SUB(a,b,r) SET_V_BIT_HI(((a) ^ (b)) & ((a) ^ (r)), 31) |
| 65 | | #define SET_V_ADD(a,b,r) SET_V_BIT_HI(~((a) ^ (b)) & ((a) ^ (r)), 31) |
| 66 | | #define SET_C_SUB(a,b) SET_C_LOG((UINT32)(b) > (UINT32)(a)) |
| 67 | | #define SET_C_ADD(a,b) SET_C_LOG((UINT32)~(a) < (UINT32)(b)) |
| 68 | | #define SET_NZV_SUB(a,b,r) SET_NZ_VAL(r); SET_V_SUB(a,b,r) |
| 69 | | #define SET_NZCV_SUB(a,b,r) SET_NZV_SUB(a,b,r); SET_C_SUB(a,b) |
| 70 | | #define SET_NZCV_ADD(a,b,r) SET_NZ_VAL(r); SET_V_ADD(a,b,r); SET_C_ADD(a,b) |
| 71 | | |
| 72 | | static const UINT8 fw_inc[32] = { 32,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 }; |
| 73 | | |
| 74 | | |
| 75 | | /*************************************************************************** |
| 76 | | UNIMPLEMENTED INSTRUCTION |
| 77 | | ***************************************************************************/ |
| 78 | | |
| 79 | | void tms340x0_device::unimpl(UINT16 op) |
| 80 | | { |
| 81 | | /* kludge for Super High Impact -- this doesn't seem to cause */ |
| 82 | | /* an illegal opcode exception */ |
| 83 | | if (m_direct->read_word(TOBYTE(m_pc - 0x10)) == 0x0007) |
| 84 | | return; |
| 85 | | |
| 86 | | /* 9 Ball Shootout calls to FFDF7468, expecting it */ |
| 87 | | /* to execute the next instruction from FFDF7470 */ |
| 88 | | /* but the instruction at FFDF7460 is an 0x0001 */ |
| 89 | | if (m_direct->read_word(TOBYTE(m_pc - 0x10)) == 0x0001) |
| 90 | | return; |
| 91 | | |
| 92 | | PUSH(m_pc); |
| 93 | | PUSH(m_st); |
| 94 | | RESET_ST(); |
| 95 | | m_pc = RLONG(0xfffffc20); |
| 96 | | COUNT_UNKNOWN_CYCLES(16); |
| 97 | | |
| 98 | | /* extra check to prevent bad things */ |
| 99 | | if (m_pc == 0 || s_opcode_table[m_direct->read_word(TOBYTE(m_pc)) >> 4] == &tms34010_device::unimpl) |
| 100 | | { |
| 101 | | set_input_line(INPUT_LINE_HALT, ASSERT_LINE); |
| 102 | | debugger_break(machine()); |
| 103 | | } |
| 104 | | } |
| 105 | | |
| 106 | | |
| 107 | | |
| 108 | | /*************************************************************************** |
| 109 | | X/Y OPERATIONS |
| 110 | | ***************************************************************************/ |
| 111 | | |
| 112 | | #define ADD_XY(R) \ |
| 113 | | { \ |
| 114 | | XY a = R##REG_XY(SRCREG(op)); \ |
| 115 | | XY *b = &R##REG_XY(DSTREG(op)); \ |
| 116 | | CLR_NCZV(); \ |
| 117 | | b->x += a.x; \ |
| 118 | | b->y += a.y; \ |
| 119 | | SET_N_LOG(b->x == 0); \ |
| 120 | | SET_C_BIT_LO(b->y, 15); \ |
| 121 | | SET_Z_LOG(b->y == 0); \ |
| 122 | | SET_V_BIT_LO(b->x, 15); \ |
| 123 | | COUNT_CYCLES(1); \ |
| 124 | | } |
| 125 | | void tms340x0_device::add_xy_a(UINT16 op) { ADD_XY(A); } |
| 126 | | void tms340x0_device::add_xy_b(UINT16 op) { ADD_XY(B); } |
| 127 | | |
| 128 | | #define SUB_XY(R) \ |
| 129 | | { \ |
| 130 | | XY a = R##REG_XY(SRCREG(op)); \ |
| 131 | | XY *b = &R##REG_XY(DSTREG(op)); \ |
| 132 | | CLR_NCZV(); \ |
| 133 | | SET_N_LOG(a.x == b->x); \ |
| 134 | | SET_C_LOG(a.y > b->y); \ |
| 135 | | SET_Z_LOG(a.y == b->y); \ |
| 136 | | SET_V_LOG(a.x > b->x); \ |
| 137 | | b->x -= a.x; \ |
| 138 | | b->y -= a.y; \ |
| 139 | | COUNT_CYCLES(1); \ |
| 140 | | } |
| 141 | | void tms340x0_device::sub_xy_a(UINT16 op) { SUB_XY(A); } |
| 142 | | void tms340x0_device::sub_xy_b(UINT16 op) { SUB_XY(B); } |
| 143 | | |
| 144 | | #define CMP_XY(R) \ |
| 145 | | { \ |
| 146 | | INT16 res; \ |
| 147 | | XY a = R##REG_XY(DSTREG(op)); \ |
| 148 | | XY b = R##REG_XY(SRCREG(op)); \ |
| 149 | | CLR_NCZV(); \ |
| 150 | | res = a.x-b.x; \ |
| 151 | | SET_N_LOG(res == 0); \ |
| 152 | | SET_V_BIT_LO(res, 15); \ |
| 153 | | res = a.y-b.y; \ |
| 154 | | SET_Z_LOG(res == 0); \ |
| 155 | | SET_C_BIT_LO(res, 15); \ |
| 156 | | COUNT_CYCLES(1); \ |
| 157 | | } |
| 158 | | void tms340x0_device::cmp_xy_a(UINT16 op) { CMP_XY(A); } |
| 159 | | void tms340x0_device::cmp_xy_b(UINT16 op) { CMP_XY(B); } |
| 160 | | |
| 161 | | #define CPW(R) \ |
| 162 | | { \ |
| 163 | | INT32 res = 0; \ |
| 164 | | INT16 x = R##REG_X(SRCREG(op)); \ |
| 165 | | INT16 y = R##REG_Y(SRCREG(op)); \ |
| 166 | | \ |
| 167 | | CLR_V(); \ |
| 168 | | res |= ((WSTART_X() > x) ? 0x20 : 0); \ |
| 169 | | res |= ((x > WEND_X()) ? 0x40 : 0); \ |
| 170 | | res |= ((WSTART_Y() > y) ? 0x80 : 0); \ |
| 171 | | res |= ((y > WEND_Y()) ? 0x100 : 0); \ |
| 172 | | R##REG(DSTREG(op)) = res; \ |
| 173 | | SET_V_LOG(res != 0); \ |
| 174 | | COUNT_CYCLES(1); \ |
| 175 | | } |
| 176 | | void tms340x0_device::cpw_a(UINT16 op) { CPW(A); } |
| 177 | | void tms340x0_device::cpw_b(UINT16 op) { CPW(B); } |
| 178 | | |
| 179 | | #define CVXYL(R) \ |
| 180 | | { \ |
| 181 | | R##REG(DSTREG(op)) = DXYTOL(R##REG_XY(SRCREG(op))); \ |
| 182 | | COUNT_CYCLES(3); \ |
| 183 | | } |
| 184 | | void tms340x0_device::cvxyl_a(UINT16 op) { CVXYL(A); } |
| 185 | | void tms340x0_device::cvxyl_b(UINT16 op) { CVXYL(B); } |
| 186 | | |
| 187 | | #define MOVX(R) \ |
| 188 | | { \ |
| 189 | | R##REG(DSTREG(op)) = (R##REG(DSTREG(op)) & 0xffff0000) | (UINT16)R##REG(SRCREG(op)); \ |
| 190 | | COUNT_CYCLES(1); \ |
| 191 | | } |
| 192 | | void tms340x0_device::movx_a(UINT16 op) { MOVX(A); } |
| 193 | | void tms340x0_device::movx_b(UINT16 op) { MOVX(B); } |
| 194 | | |
| 195 | | #define MOVY(R) \ |
| 196 | | { \ |
| 197 | | R##REG(DSTREG(op)) = (R##REG(SRCREG(op)) & 0xffff0000) | (UINT16)R##REG(DSTREG(op)); \ |
| 198 | | COUNT_CYCLES(1); \ |
| 199 | | } |
| 200 | | void tms340x0_device::movy_a(UINT16 op) { MOVY(A); } |
| 201 | | void tms340x0_device::movy_b(UINT16 op) { MOVY(B); } |
| 202 | | |
| 203 | | |
| 204 | | |
| 205 | | /*************************************************************************** |
| 206 | | PIXEL TRANSFER OPERATIONS |
| 207 | | ***************************************************************************/ |
| 208 | | |
| 209 | | #define PIXT_RI(R) \ |
| 210 | | { \ |
| 211 | | WPIXEL(R##REG(DSTREG(op)),R##REG(SRCREG(op))); \ |
| 212 | | COUNT_UNKNOWN_CYCLES(2); \ |
| 213 | | } |
| 214 | | void tms340x0_device::pixt_ri_a(UINT16 op) { PIXT_RI(A); } |
| 215 | | void tms340x0_device::pixt_ri_b(UINT16 op) { PIXT_RI(B); } |
| 216 | | |
| 217 | | #define PIXT_RIXY(R) \ |
| 218 | | { \ |
| 219 | | if (WINDOW_CHECKING() != 0) \ |
| 220 | | { \ |
| 221 | | CLR_V(); \ |
| 222 | | if (R##REG_X(DSTREG(op)) < WSTART_X() || R##REG_X(DSTREG(op)) > WEND_X() || \ |
| 223 | | R##REG_Y(DSTREG(op)) < WSTART_Y() || R##REG_Y(DSTREG(op)) > WEND_Y()) \ |
| 224 | | { \ |
| 225 | | SET_V_LOG(1); \ |
| 226 | | goto skip; \ |
| 227 | | } \ |
| 228 | | if (WINDOW_CHECKING() == 1) goto skip; \ |
| 229 | | } \ |
| 230 | | WPIXEL(DXYTOL(R##REG_XY(DSTREG(op))),R##REG(SRCREG(op))); \ |
| 231 | | skip: \ |
| 232 | | COUNT_UNKNOWN_CYCLES(4); \ |
| 233 | | } |
| 234 | | void tms340x0_device::pixt_rixy_a(UINT16 op) { PIXT_RIXY(A); } |
| 235 | | void tms340x0_device::pixt_rixy_b(UINT16 op) { PIXT_RIXY(B); } |
| 236 | | |
| 237 | | #define PIXT_IR(R) \ |
| 238 | | { \ |
| 239 | | INT32 temp = RPIXEL(R##REG(SRCREG(op))); \ |
| 240 | | CLR_V(); \ |
| 241 | | R##REG(DSTREG(op)) = temp; \ |
| 242 | | SET_V_LOG(temp != 0); \ |
| 243 | | COUNT_CYCLES(4); \ |
| 244 | | } |
| 245 | | void tms340x0_device::pixt_ir_a(UINT16 op) { PIXT_IR(A); } |
| 246 | | void tms340x0_device::pixt_ir_b(UINT16 op) { PIXT_IR(B); } |
| 247 | | |
| 248 | | #define PIXT_II(R) \ |
| 249 | | { \ |
| 250 | | WPIXEL(R##REG(DSTREG(op)),RPIXEL(R##REG(SRCREG(op)))); \ |
| 251 | | COUNT_UNKNOWN_CYCLES(4); \ |
| 252 | | } |
| 253 | | void tms340x0_device::pixt_ii_a(UINT16 op) { PIXT_II(A); } |
| 254 | | void tms340x0_device::pixt_ii_b(UINT16 op) { PIXT_II(B); } |
| 255 | | |
| 256 | | #define PIXT_IXYR(R) \ |
| 257 | | { \ |
| 258 | | INT32 temp = RPIXEL(SXYTOL(R##REG_XY(SRCREG(op)))); \ |
| 259 | | CLR_V(); \ |
| 260 | | R##REG(DSTREG(op)) = temp; \ |
| 261 | | SET_V_LOG(temp != 0); \ |
| 262 | | COUNT_CYCLES(6); \ |
| 263 | | } |
| 264 | | void tms340x0_device::pixt_ixyr_a(UINT16 op) { PIXT_IXYR(A); } |
| 265 | | void tms340x0_device::pixt_ixyr_b(UINT16 op) { PIXT_IXYR(B); } |
| 266 | | |
| 267 | | #define PIXT_IXYIXY(R) \ |
| 268 | | { \ |
| 269 | | if (WINDOW_CHECKING() != 0) \ |
| 270 | | { \ |
| 271 | | CLR_V(); \ |
| 272 | | if (R##REG_X(DSTREG(op)) < WSTART_X() || R##REG_X(DSTREG(op)) > WEND_X() || \ |
| 273 | | R##REG_Y(DSTREG(op)) < WSTART_Y() || R##REG_Y(DSTREG(op)) > WEND_Y()) \ |
| 274 | | { \ |
| 275 | | SET_V_LOG(1); \ |
| 276 | | goto skip; \ |
| 277 | | } \ |
| 278 | | if (WINDOW_CHECKING() == 1) goto skip; \ |
| 279 | | } \ |
| 280 | | WPIXEL(DXYTOL(R##REG_XY(DSTREG(op))),RPIXEL(SXYTOL(R##REG_XY(SRCREG(op))))); \ |
| 281 | | skip: \ |
| 282 | | COUNT_UNKNOWN_CYCLES(7); \ |
| 283 | | } |
| 284 | | void tms340x0_device::pixt_ixyixy_a(UINT16 op) { PIXT_IXYIXY(A); } |
| 285 | | void tms340x0_device::pixt_ixyixy_b(UINT16 op) { PIXT_IXYIXY(B); } |
| 286 | | |
| 287 | | #define DRAV(R) \ |
| 288 | | { \ |
| 289 | | if (WINDOW_CHECKING() != 0) \ |
| 290 | | { \ |
| 291 | | CLR_V(); \ |
| 292 | | if (R##REG_X(DSTREG(op)) < WSTART_X() || R##REG_X(DSTREG(op)) > WEND_X() || \ |
| 293 | | R##REG_Y(DSTREG(op)) < WSTART_Y() || R##REG_Y(DSTREG(op)) > WEND_Y()) \ |
| 294 | | { \ |
| 295 | | SET_V_LOG(1); \ |
| 296 | | goto skip; \ |
| 297 | | } \ |
| 298 | | if (WINDOW_CHECKING() == 1) goto skip; \ |
| 299 | | } \ |
| 300 | | WPIXEL(DXYTOL(R##REG_XY(DSTREG(op))),COLOR1()); \ |
| 301 | | skip: \ |
| 302 | | R##REG_X(DSTREG(op)) += R##REG_X(SRCREG(op)); \ |
| 303 | | R##REG_Y(DSTREG(op)) += R##REG_Y(SRCREG(op)); \ |
| 304 | | COUNT_UNKNOWN_CYCLES(4); \ |
| 305 | | } |
| 306 | | void tms340x0_device::drav_a(UINT16 op) { DRAV(A); } |
| 307 | | void tms340x0_device::drav_b(UINT16 op) { DRAV(B); } |
| 308 | | |
| 309 | | |
| 310 | | |
| 311 | | /*************************************************************************** |
| 312 | | ARITHMETIC OPERATIONS |
| 313 | | ***************************************************************************/ |
| 314 | | |
| 315 | | #define ABS(R) \ |
| 316 | | { \ |
| 317 | | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 318 | | INT32 r = 0 - *rd; \ |
| 319 | | CLR_NZV(); \ |
| 320 | | if (r > 0) *rd = r; \ |
| 321 | | SET_NZ_VAL(r); \ |
| 322 | | SET_V_LOG(r == (INT32)0x80000000); \ |
| 323 | | COUNT_CYCLES(1); \ |
| 324 | | } |
| 325 | | void tms340x0_device::abs_a(UINT16 op) { ABS(A); } |
| 326 | | void tms340x0_device::abs_b(UINT16 op) { ABS(B); } |
| 327 | | |
| 328 | | #define ADD(R) \ |
| 329 | | { \ |
| 330 | | INT32 a = R##REG(SRCREG(op)); \ |
| 331 | | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 332 | | INT32 b = *rd; \ |
| 333 | | INT32 r = a + b; \ |
| 334 | | CLR_NCZV(); \ |
| 335 | | *rd = r; \ |
| 336 | | SET_NZCV_ADD(a,b,r); \ |
| 337 | | COUNT_CYCLES(1); \ |
| 338 | | } |
| 339 | | void tms340x0_device::add_a(UINT16 op) { ADD(A); } |
| 340 | | void tms340x0_device::add_b(UINT16 op) { ADD(B); } |
| 341 | | |
| 342 | | #define ADDC(R) \ |
| 343 | | { \ |
| 344 | | /* I'm not sure to which side the carry is added to, should */ \ |
| 345 | | /* verify it against the examples */ \ |
| 346 | | INT32 a = R##REG(SRCREG(op)); \ |
| 347 | | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 348 | | INT32 b = *rd; \ |
| 349 | | INT32 r = a + b + (C_FLAG() ? 1 : 0); \ |
| 350 | | CLR_NCZV(); \ |
| 351 | | *rd = r; \ |
| 352 | | SET_NZCV_ADD(a,b,r); \ |
| 353 | | COUNT_CYCLES(1); \ |
| 354 | | } |
| 355 | | void tms340x0_device::addc_a(UINT16 op) { ADDC(A); } |
| 356 | | void tms340x0_device::addc_b(UINT16 op) { ADDC(B); } |
| 357 | | |
| 358 | | #define ADDI_W(R) \ |
| 359 | | { \ |
| 360 | | INT32 a = PARAM_WORD(); \ |
| 361 | | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 362 | | INT32 b = *rd; \ |
| 363 | | INT32 r = a + b; \ |
| 364 | | CLR_NCZV(); \ |
| 365 | | *rd = r; \ |
| 366 | | SET_NZCV_ADD(a,b,r); \ |
| 367 | | COUNT_CYCLES(2); \ |
| 368 | | } |
| 369 | | void tms340x0_device::addi_w_a(UINT16 op) { ADDI_W(A); } |
| 370 | | void tms340x0_device::addi_w_b(UINT16 op) { ADDI_W(B); } |
| 371 | | |
| 372 | | #define ADDI_L(R) \ |
| 373 | | { \ |
| 374 | | INT32 a = PARAM_LONG(); \ |
| 375 | | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 376 | | INT32 b = *rd; \ |
| 377 | | INT32 r = a + b; \ |
| 378 | | CLR_NCZV(); \ |
| 379 | | *rd = r; \ |
| 380 | | SET_NZCV_ADD(a,b,r); \ |
| 381 | | COUNT_CYCLES(3); \ |
| 382 | | } |
| 383 | | void tms340x0_device::addi_l_a(UINT16 op) { ADDI_L(A); } |
| 384 | | void tms340x0_device::addi_l_b(UINT16 op) { ADDI_L(B); } |
| 385 | | |
| 386 | | #define ADDK(R) \ |
| 387 | | { \ |
| 388 | | INT32 a = fw_inc[PARAM_K(op)]; \ |
| 389 | | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 390 | | INT32 b = *rd; \ |
| 391 | | INT32 r = a + b; \ |
| 392 | | CLR_NCZV(); \ |
| 393 | | *rd = r; \ |
| 394 | | SET_NZCV_ADD(a,b,r); \ |
| 395 | | COUNT_CYCLES(1); \ |
| 396 | | } |
| 397 | | void tms340x0_device::addk_a(UINT16 op) { ADDK(A); } |
| 398 | | void tms340x0_device::addk_b(UINT16 op) { ADDK(B); } |
| 399 | | |
| 400 | | #define AND(R) \ |
| 401 | | { \ |
| 402 | | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 403 | | CLR_Z(); \ |
| 404 | | *rd &= R##REG(SRCREG(op)); \ |
| 405 | | SET_Z_VAL(*rd); \ |
| 406 | | COUNT_CYCLES(1); \ |
| 407 | | } |
| 408 | | void tms340x0_device::and_a(UINT16 op) { AND(A); } |
| 409 | | void tms340x0_device::and_b(UINT16 op) { AND(B); } |
| 410 | | |
| 411 | | #define ANDI(R) \ |
| 412 | | { \ |
| 413 | | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 414 | | CLR_Z(); \ |
| 415 | | *rd &= ~PARAM_LONG(); \ |
| 416 | | SET_Z_VAL(*rd); \ |
| 417 | | COUNT_CYCLES(3); \ |
| 418 | | } |
| 419 | | void tms340x0_device::andi_a(UINT16 op) { ANDI(A); } |
| 420 | | void tms340x0_device::andi_b(UINT16 op) { ANDI(B); } |
| 421 | | |
| 422 | | #define ANDN(R) \ |
| 423 | | { \ |
| 424 | | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 425 | | CLR_Z(); \ |
| 426 | | *rd &= ~R##REG(SRCREG(op)); \ |
| 427 | | SET_Z_VAL(*rd); \ |
| 428 | | COUNT_CYCLES(1); \ |
| 429 | | } |
| 430 | | void tms340x0_device::andn_a(UINT16 op) { ANDN(A); } |
| 431 | | void tms340x0_device::andn_b(UINT16 op) { ANDN(B); } |
| 432 | | |
| 433 | | #define BTST_K(R) \ |
| 434 | | { \ |
| 435 | | int bit = 31 - PARAM_K(op); \ |
| 436 | | CLR_Z(); \ |
| 437 | | if (bit <= 29) \ |
| 438 | | SET_Z_BIT_LO(~R##REG(DSTREG(op)), bit); \ |
| 439 | | else \ |
| 440 | | SET_Z_BIT_HI(~R##REG(DSTREG(op)), bit); \ |
| 441 | | COUNT_CYCLES(1); \ |
| 442 | | } |
| 443 | | void tms340x0_device::btst_k_a(UINT16 op) { BTST_K(A); } |
| 444 | | void tms340x0_device::btst_k_b(UINT16 op) { BTST_K(B); } |
| 445 | | |
| 446 | | #define BTST_R(R) \ |
| 447 | | { \ |
| 448 | | int bit = R##REG(SRCREG(op)) & 0x1f; \ |
| 449 | | CLR_Z(); \ |
| 450 | | if (bit <= 29) \ |
| 451 | | SET_Z_BIT_LO(~R##REG(DSTREG(op)), bit); \ |
| 452 | | else \ |
| 453 | | SET_Z_BIT_HI(~R##REG(DSTREG(op)), bit); \ |
| 454 | | COUNT_CYCLES(2); \ |
| 455 | | } |
| 456 | | void tms340x0_device::btst_r_a(UINT16 op) { BTST_R(A); } |
| 457 | | void tms340x0_device::btst_r_b(UINT16 op) { BTST_R(B); } |
| 458 | | |
| 459 | | void tms340x0_device::clrc(UINT16 op) |
| 460 | | { |
| 461 | | CLR_C(); |
| 462 | | COUNT_CYCLES(1); |
| 463 | | } |
| 464 | | |
| 465 | | #define CMP(R) \ |
| 466 | | { \ |
| 467 | | INT32 *rs = &R##REG(SRCREG(op)); \ |
| 468 | | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 469 | | INT32 r = *rd - *rs; \ |
| 470 | | CLR_NCZV(); \ |
| 471 | | SET_NZCV_SUB(*rd,*rs,r); \ |
| 472 | | COUNT_CYCLES(1); \ |
| 473 | | } |
| 474 | | void tms340x0_device::cmp_a(UINT16 op) { CMP(A); } |
| 475 | | void tms340x0_device::cmp_b(UINT16 op) { CMP(B); } |
| 476 | | |
| 477 | | #define CMPI_W(R) \ |
| 478 | | { \ |
| 479 | | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 480 | | INT32 t = (INT16)~PARAM_WORD(); \ |
| 481 | | INT32 r = *rd - t; \ |
| 482 | | CLR_NCZV(); \ |
| 483 | | SET_NZCV_SUB(*rd,t,r); \ |
| 484 | | COUNT_CYCLES(2); \ |
| 485 | | } |
| 486 | | void tms340x0_device::cmpi_w_a(UINT16 op) { CMPI_W(A); } |
| 487 | | void tms340x0_device::cmpi_w_b(UINT16 op) { CMPI_W(B); } |
| 488 | | |
| 489 | | #define CMPI_L(R) \ |
| 490 | | { \ |
| 491 | | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 492 | | INT32 t = ~PARAM_LONG(); \ |
| 493 | | INT32 r = *rd - t; \ |
| 494 | | CLR_NCZV(); \ |
| 495 | | SET_NZCV_SUB(*rd,t,r); \ |
| 496 | | COUNT_CYCLES(3); \ |
| 497 | | } |
| 498 | | void tms340x0_device::cmpi_l_a(UINT16 op) { CMPI_L(A); } |
| 499 | | void tms340x0_device::cmpi_l_b(UINT16 op) { CMPI_L(B); } |
| 500 | | |
| 501 | | void tms340x0_device::dint(UINT16 op) |
| 502 | | { |
| 503 | | m_st &= ~STBIT_IE; |
| 504 | | COUNT_CYCLES(3); |
| 505 | | } |
| 506 | | |
| 507 | | #define DIVS(R) \ |
| 508 | | { \ |
| 509 | | INT32 *rs = &R##REG(SRCREG(op)); \ |
| 510 | | INT32 *rd1 = &R##REG(DSTREG(op)); \ |
| 511 | | CLR_NZV(); \ |
| 512 | | if (!(DSTREG(op) & 1)) \ |
| 513 | | { \ |
| 514 | | if (!*rs) \ |
| 515 | | { \ |
| 516 | | SET_V_LOG(1); \ |
| 517 | | } \ |
| 518 | | else \ |
| 519 | | { \ |
| 520 | | INT32 *rd2 = &R##REG(DSTREG(op)+1); \ |
| 521 | | INT64 dividend = ((UINT64)*rd1 << 32) | (UINT32)*rd2; \ |
| 522 | | INT64 quotient = dividend / *rs; \ |
| 523 | | INT32 remainder = dividend % *rs; \ |
| 524 | | UINT32 signbits = (INT32)quotient >> 31; \ |
| 525 | | if (EXTRACT_64HI(quotient) != signbits) \ |
| 526 | | { \ |
| 527 | | SET_V_LOG(1); \ |
| 528 | | } \ |
| 529 | | else \ |
| 530 | | { \ |
| 531 | | *rd1 = quotient; \ |
| 532 | | *rd2 = remainder; \ |
| 533 | | SET_NZ_VAL(*rd1); \ |
| 534 | | } \ |
| 535 | | } \ |
| 536 | | COUNT_CYCLES(40); \ |
| 537 | | } \ |
| 538 | | else \ |
| 539 | | { \ |
| 540 | | if (!*rs) \ |
| 541 | | { \ |
| 542 | | SET_V_LOG(1); \ |
| 543 | | } \ |
| 544 | | else \ |
| 545 | | { \ |
| 546 | | *rd1 /= *rs; \ |
| 547 | | SET_NZ_VAL(*rd1); \ |
| 548 | | } \ |
| 549 | | COUNT_CYCLES(39); \ |
| 550 | | } \ |
| 551 | | } |
| 552 | | void tms340x0_device::divs_a(UINT16 op) { DIVS(A); } |
| 553 | | void tms340x0_device::divs_b(UINT16 op) { DIVS(B); } |
| 554 | | |
| 555 | | #define DIVU(R) \ |
| 556 | | { \ |
| 557 | | INT32 *rs = &R##REG(SRCREG(op)); \ |
| 558 | | INT32 *rd1 = &R##REG(DSTREG(op)); \ |
| 559 | | CLR_ZV(); \ |
| 560 | | if (!(DSTREG(op) & 1)) \ |
| 561 | | { \ |
| 562 | | if (!*rs) \ |
| 563 | | { \ |
| 564 | | SET_V_LOG(1); \ |
| 565 | | } \ |
| 566 | | else \ |
| 567 | | { \ |
| 568 | | INT32 *rd2 = &R##REG(DSTREG(op)+1); \ |
| 569 | | UINT64 dividend = ((UINT64)*rd1 << 32) | (UINT32)*rd2; \ |
| 570 | | UINT64 quotient = dividend / (UINT32)*rs; \ |
| 571 | | UINT32 remainder = dividend % (UINT32)*rs; \ |
| 572 | | if (EXTRACT_64HI(quotient) != 0) \ |
| 573 | | { \ |
| 574 | | SET_V_LOG(1); \ |
| 575 | | } \ |
| 576 | | else \ |
| 577 | | { \ |
| 578 | | *rd1 = quotient; \ |
| 579 | | *rd2 = remainder; \ |
| 580 | | SET_Z_VAL(*rd1); \ |
| 581 | | } \ |
| 582 | | } \ |
| 583 | | } \ |
| 584 | | else \ |
| 585 | | { \ |
| 586 | | if (!*rs) \ |
| 587 | | { \ |
| 588 | | SET_V_LOG(1); \ |
| 589 | | } \ |
| 590 | | else \ |
| 591 | | { \ |
| 592 | | *rd1 = (UINT32)*rd1 / (UINT32)*rs; \ |
| 593 | | SET_Z_VAL(*rd1); \ |
| 594 | | } \ |
| 595 | | } \ |
| 596 | | COUNT_CYCLES(37); \ |
| 597 | | } |
| 598 | | void tms340x0_device::divu_a(UINT16 op) { DIVU(A); } |
| 599 | | void tms340x0_device::divu_b(UINT16 op) { DIVU(B); } |
| 600 | | |
| 601 | | void tms340x0_device::eint(UINT16 op) |
| 602 | | { |
| 603 | | m_st |= STBIT_IE; |
| 604 | | check_interrupt(); |
| 605 | | COUNT_CYCLES(3); |
| 606 | | } |
| 607 | | |
| 608 | | #define EXGF(F,R) \ |
| 609 | | { \ |
| 610 | | UINT8 shift = F ? 6 : 0; \ |
| 611 | | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 612 | | UINT32 temp = (m_st >> shift) & 0x3f; \ |
| 613 | | m_st &= ~(0x3f << shift); \ |
| 614 | | m_st |= (*rd & 0x3f) << shift; \ |
| 615 | | *rd = temp; \ |
| 616 | | COUNT_CYCLES(1); \ |
| 617 | | } |
| 618 | | void tms340x0_device::exgf0_a(UINT16 op) { EXGF(0,A); } |
| 619 | | void tms340x0_device::exgf0_b(UINT16 op) { EXGF(0,B); } |
| 620 | | void tms340x0_device::exgf1_a(UINT16 op) { EXGF(1,A); } |
| 621 | | void tms340x0_device::exgf1_b(UINT16 op) { EXGF(1,B); } |
| 622 | | |
| 623 | | #define LMO(R) \ |
| 624 | | { \ |
| 625 | | UINT32 res = 0; \ |
| 626 | | UINT32 rs = R##REG(SRCREG(op)); \ |
| 627 | | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 628 | | CLR_Z(); \ |
| 629 | | SET_Z_VAL(rs); \ |
| 630 | | if (rs) \ |
| 631 | | { \ |
| 632 | | while (!(rs & 0x80000000)) \ |
| 633 | | { \ |
| 634 | | res++; \ |
| 635 | | rs <<= 1; \ |
| 636 | | } \ |
| 637 | | } \ |
| 638 | | *rd = res; \ |
| 639 | | COUNT_CYCLES(1); \ |
| 640 | | } |
| 641 | | void tms340x0_device::lmo_a(UINT16 op) { LMO(A); } |
| 642 | | void tms340x0_device::lmo_b(UINT16 op) { LMO(B); } |
| 643 | | |
| 644 | | #define MMFM(R) \ |
| 645 | | { \ |
| 646 | | INT32 i; \ |
| 647 | | UINT16 l = (UINT16) PARAM_WORD(); \ |
| 648 | | COUNT_CYCLES(3); \ |
| 649 | | { \ |
| 650 | | INT32 rd = DSTREG(op); \ |
| 651 | | for (i = 15; i >= 0 ; i--) \ |
| 652 | | { \ |
| 653 | | if (l & 0x8000) \ |
| 654 | | { \ |
| 655 | | R##REG(i) = RLONG(R##REG(rd)); \ |
| 656 | | R##REG(rd) += 0x20; \ |
| 657 | | COUNT_CYCLES(4); \ |
| 658 | | } \ |
| 659 | | l <<= 1; \ |
| 660 | | } \ |
| 661 | | } \ |
| 662 | | } |
| 663 | | void tms340x0_device::mmfm_a(UINT16 op) { MMFM(A); } |
| 664 | | void tms340x0_device::mmfm_b(UINT16 op) { MMFM(B); } |
| 665 | | |
| 666 | | #define MMTM(R) \ |
| 667 | | { \ |
| 668 | | UINT32 i; \ |
| 669 | | UINT16 l = (UINT16) PARAM_WORD(); \ |
| 670 | | COUNT_CYCLES(2); \ |
| 671 | | { \ |
| 672 | | INT32 rd = DSTREG(op); \ |
| 673 | | if (m_is_34020) \ |
| 674 | | { \ |
| 675 | | CLR_N(); \ |
| 676 | | SET_N_VAL(R##REG(rd) ^ 0x80000000); \ |
| 677 | | } \ |
| 678 | | for (i = 0; i < 16; i++) \ |
| 679 | | { \ |
| 680 | | if (l & 0x8000) \ |
| 681 | | { \ |
| 682 | | R##REG(rd) -= 0x20; \ |
| 683 | | WLONG(R##REG(rd),R##REG(i)); \ |
| 684 | | COUNT_CYCLES(4); \ |
| 685 | | } \ |
| 686 | | l <<= 1; \ |
| 687 | | } \ |
| 688 | | } \ |
| 689 | | } |
| 690 | | void tms340x0_device::mmtm_a(UINT16 op) { MMTM(A); } |
| 691 | | void tms340x0_device::mmtm_b(UINT16 op) { MMTM(B); } |
| 692 | | |
| 693 | | #define MODS(R) \ |
| 694 | | { \ |
| 695 | | INT32 *rs = &R##REG(SRCREG(op)); \ |
| 696 | | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 697 | | CLR_NZV(); \ |
| 698 | | if (*rs != 0) \ |
| 699 | | { \ |
| 700 | | *rd %= *rs; \ |
| 701 | | SET_NZ_VAL(*rd); \ |
| 702 | | } \ |
| 703 | | else \ |
| 704 | | SET_V_LOG(1); \ |
| 705 | | COUNT_CYCLES(40); \ |
| 706 | | } |
| 707 | | void tms340x0_device::mods_a(UINT16 op) { MODS(A); } |
| 708 | | void tms340x0_device::mods_b(UINT16 op) { MODS(B); } |
| 709 | | |
| 710 | | #define MODU(R) \ |
| 711 | | { \ |
| 712 | | INT32 *rs = &R##REG(SRCREG(op)); \ |
| 713 | | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 714 | | CLR_ZV(); \ |
| 715 | | if (*rs != 0) \ |
| 716 | | { \ |
| 717 | | *rd = (UINT32)*rd % (UINT32)*rs; \ |
| 718 | | SET_Z_VAL(*rd); \ |
| 719 | | } \ |
| 720 | | else \ |
| 721 | | SET_V_LOG(1); \ |
| 722 | | COUNT_CYCLES(35); \ |
| 723 | | } |
| 724 | | void tms340x0_device::modu_a(UINT16 op) { MODU(A); } |
| 725 | | void tms340x0_device::modu_b(UINT16 op) { MODU(B); } |
| 726 | | |
| 727 | | #define MPYS(R) \ |
| 728 | | { \ |
| 729 | | INT32 *rd1 = &R##REG(DSTREG(op)); \ |
| 730 | | INT32 m1 = R##REG(SRCREG(op)); \ |
| 731 | | INT64 product; \ |
| 732 | | \ |
| 733 | | SEXTEND(m1, FW(1)); \ |
| 734 | | CLR_NZ(); \ |
| 735 | | product = mul_32x32(m1, *rd1); \ |
| 736 | | SET_Z_LOG(product == 0); \ |
| 737 | | SET_N_BIT(product >> 32, 31); \ |
| 738 | | \ |
| 739 | | *rd1 = EXTRACT_64HI(product); \ |
| 740 | | R##REG(DSTREG(op)|1) = EXTRACT_64LO(product); \ |
| 741 | | \ |
| 742 | | COUNT_CYCLES(20); \ |
| 743 | | } |
| 744 | | void tms340x0_device::mpys_a(UINT16 op) { MPYS(A); } |
| 745 | | void tms340x0_device::mpys_b(UINT16 op) { MPYS(B); } |
| 746 | | |
| 747 | | #define MPYU(R) \ |
| 748 | | { \ |
| 749 | | INT32 *rd1 = &R##REG(DSTREG(op)); \ |
| 750 | | UINT32 m1 = R##REG(SRCREG(op)); \ |
| 751 | | UINT64 product; \ |
| 752 | | \ |
| 753 | | ZEXTEND(m1, FW(1)); \ |
| 754 | | CLR_Z(); \ |
| 755 | | product = mulu_32x32(m1, *rd1); \ |
| 756 | | SET_Z_LOG(product == 0); \ |
| 757 | | \ |
| 758 | | *rd1 = EXTRACT_64HI(product); \ |
| 759 | | R##REG(DSTREG(op)|1) = EXTRACT_64LO(product); \ |
| 760 | | \ |
| 761 | | COUNT_CYCLES(21); \ |
| 762 | | } |
| 763 | | void tms340x0_device::mpyu_a(UINT16 op) { MPYU(A); } |
| 764 | | void tms340x0_device::mpyu_b(UINT16 op) { MPYU(B); } |
| 765 | | |
| 766 | | #define NEG(R) \ |
| 767 | | { \ |
| 768 | | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 769 | | INT32 r = 0 - *rd; \ |
| 770 | | CLR_NCZV(); \ |
| 771 | | SET_NZCV_SUB(0,*rd,r); \ |
| 772 | | *rd = r; \ |
| 773 | | COUNT_CYCLES(1); \ |
| 774 | | } |
| 775 | | void tms340x0_device::neg_a(UINT16 op) { NEG(A); } |
| 776 | | void tms340x0_device::neg_b(UINT16 op) { NEG(B); } |
| 777 | | |
| 778 | | #define NEGB(R) \ |
| 779 | | { \ |
| 780 | | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 781 | | INT32 t = *rd + (C_FLAG() ? 1 : 0); \ |
| 782 | | INT32 r = 0 - t; \ |
| 783 | | CLR_NCZV(); \ |
| 784 | | SET_NZCV_SUB(0,t,r); \ |
| 785 | | *rd = r; \ |
| 786 | | COUNT_CYCLES(1); \ |
| 787 | | } |
| 788 | | void tms340x0_device::negb_a(UINT16 op) { NEGB(A); } |
| 789 | | void tms340x0_device::negb_b(UINT16 op) { NEGB(B); } |
| 790 | | |
| 791 | | void tms340x0_device::nop(UINT16 op) |
| 792 | | { |
| 793 | | COUNT_CYCLES(1); |
| 794 | | } |
| 795 | | |
| 796 | | #define NOT(R) \ |
| 797 | | { \ |
| 798 | | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 799 | | CLR_Z(); \ |
| 800 | | *rd = ~(*rd); \ |
| 801 | | SET_Z_VAL(*rd); \ |
| 802 | | COUNT_CYCLES(1); \ |
| 803 | | } |
| 804 | | void tms340x0_device::not_a(UINT16 op) { NOT(A); } |
| 805 | | void tms340x0_device::not_b(UINT16 op) { NOT(B); } |
| 806 | | |
| 807 | | #define OR(R) \ |
| 808 | | { \ |
| 809 | | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 810 | | CLR_Z(); \ |
| 811 | | *rd |= R##REG(SRCREG(op)); \ |
| 812 | | SET_Z_VAL(*rd); \ |
| 813 | | COUNT_CYCLES(1); \ |
| 814 | | } |
| 815 | | void tms340x0_device::or_a(UINT16 op) { OR(A); } |
| 816 | | void tms340x0_device::or_b(UINT16 op) { OR(B); } |
| 817 | | |
| 818 | | #define ORI(R) \ |
| 819 | | { \ |
| 820 | | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 821 | | CLR_Z(); \ |
| 822 | | *rd |= PARAM_LONG(); \ |
| 823 | | SET_Z_VAL(*rd); \ |
| 824 | | COUNT_CYCLES(3); \ |
| 825 | | } |
| 826 | | void tms340x0_device::ori_a(UINT16 op) { ORI(A); } |
| 827 | | void tms340x0_device::ori_b(UINT16 op) { ORI(B); } |
| 828 | | |
| 829 | | void tms340x0_device::setc(UINT16 op) |
| 830 | | { |
| 831 | | SET_C_LOG(1); |
| 832 | | COUNT_CYCLES(1); |
| 833 | | } |
| 834 | | |
| 835 | | #define SETF(F) \ |
| 836 | | { \ |
| 837 | | UINT8 shift = F ? 6 : 0; \ |
| 838 | | m_st &= ~(0x3f << shift); \ |
| 839 | | m_st |= (op & 0x3f) << shift; \ |
| 840 | | COUNT_CYCLES(1+F); \ |
| 841 | | } |
| 842 | | void tms340x0_device::setf0(UINT16 op) { SETF(0); } |
| 843 | | void tms340x0_device::setf1(UINT16 op) { SETF(1); } |
| 844 | | |
| 845 | | #define SEXT(F,R) \ |
| 846 | | { \ |
| 847 | | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 848 | | CLR_NZ(); \ |
| 849 | | SEXTEND(*rd,FW(F)); \ |
| 850 | | SET_NZ_VAL(*rd); \ |
| 851 | | COUNT_CYCLES(3); \ |
| 852 | | } |
| 853 | | void tms340x0_device::sext0_a(UINT16 op) { SEXT(0,A); } |
| 854 | | void tms340x0_device::sext0_b(UINT16 op) { SEXT(0,B); } |
| 855 | | void tms340x0_device::sext1_a(UINT16 op) { SEXT(1,A); } |
| 856 | | void tms340x0_device::sext1_b(UINT16 op) { SEXT(1,B); } |
| 857 | | |
| 858 | | #define RL(R,K) \ |
| 859 | | { \ |
| 860 | | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 861 | | INT32 res = *rd; \ |
| 862 | | INT32 k = (K); \ |
| 863 | | CLR_CZ(); \ |
| 864 | | if (k) \ |
| 865 | | { \ |
| 866 | | res<<=(k-1); \ |
| 867 | | SET_C_BIT_HI(res, 31); \ |
| 868 | | res<<=1; \ |
| 869 | | res |= (((UINT32)*rd)>>((-k)&0x1f)); \ |
| 870 | | *rd = res; \ |
| 871 | | } \ |
| 872 | | SET_Z_VAL(res); \ |
| 873 | | COUNT_CYCLES(1); \ |
| 874 | | } |
| 875 | | void tms340x0_device::rl_k_a(UINT16 op) { RL(A,PARAM_K(op)); } |
| 876 | | void tms340x0_device::rl_k_b(UINT16 op) { RL(B,PARAM_K(op)); } |
| 877 | | void tms340x0_device::rl_r_a(UINT16 op) { RL(A,AREG(SRCREG(op))&0x1f); } |
| 878 | | void tms340x0_device::rl_r_b(UINT16 op) { RL(B,BREG(SRCREG(op))&0x1f); } |
| 879 | | |
| 880 | | #define SLA(R,K) \ |
| 881 | | { \ |
| 882 | | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 883 | | UINT32 res = *rd; \ |
| 884 | | INT32 k = K; \ |
| 885 | | CLR_NCZV(); \ |
| 886 | | if (k) \ |
| 887 | | { \ |
| 888 | | UINT32 mask = (0xffffffff<<(31-k))&0x7fffffff; \ |
| 889 | | UINT32 res2 = SIGN(res) ? res^mask : res; \ |
| 890 | | SET_V_LOG((res2 & mask) != 0); \ |
| 891 | | \ |
| 892 | | res<<=(k-1); \ |
| 893 | | SET_C_BIT_HI(res, 31); \ |
| 894 | | res<<=1; \ |
| 895 | | *rd = res; \ |
| 896 | | } \ |
| 897 | | SET_NZ_VAL(res); \ |
| 898 | | COUNT_CYCLES(3); \ |
| 899 | | } |
| 900 | | void tms340x0_device::sla_k_a(UINT16 op) { SLA(A,PARAM_K(op)); } |
| 901 | | void tms340x0_device::sla_k_b(UINT16 op) { SLA(B,PARAM_K(op)); } |
| 902 | | void tms340x0_device::sla_r_a(UINT16 op) { SLA(A,AREG(SRCREG(op))&0x1f); } |
| 903 | | void tms340x0_device::sla_r_b(UINT16 op) { SLA(B,BREG(SRCREG(op))&0x1f); } |
| 904 | | |
| 905 | | #define SLL(R,K) \ |
| 906 | | { \ |
| 907 | | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 908 | | UINT32 res = *rd; \ |
| 909 | | INT32 k = K; \ |
| 910 | | CLR_CZ(); \ |
| 911 | | if (k) \ |
| 912 | | { \ |
| 913 | | res<<=(k-1); \ |
| 914 | | SET_C_BIT_HI(res, 31); \ |
| 915 | | res<<=1; \ |
| 916 | | *rd = res; \ |
| 917 | | } \ |
| 918 | | SET_Z_VAL(res); \ |
| 919 | | COUNT_CYCLES(1); \ |
| 920 | | } |
| 921 | | void tms340x0_device::sll_k_a(UINT16 op) { SLL(A,PARAM_K(op)); } |
| 922 | | void tms340x0_device::sll_k_b(UINT16 op) { SLL(B,PARAM_K(op)); } |
| 923 | | void tms340x0_device::sll_r_a(UINT16 op) { SLL(A,AREG(SRCREG(op))&0x1f); } |
| 924 | | void tms340x0_device::sll_r_b(UINT16 op) { SLL(B,BREG(SRCREG(op))&0x1f); } |
| 925 | | |
| 926 | | #define SRA(R,K) \ |
| 927 | | { \ |
| 928 | | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 929 | | INT32 res = *rd; \ |
| 930 | | INT32 k = (-(K)) & 0x1f; \ |
| 931 | | CLR_NCZ(); \ |
| 932 | | if (k) \ |
| 933 | | { \ |
| 934 | | res>>=(k-1); \ |
| 935 | | SET_C_BIT_LO(res, 0); \ |
| 936 | | res>>=1; \ |
| 937 | | *rd = res; \ |
| 938 | | } \ |
| 939 | | SET_NZ_VAL(res); \ |
| 940 | | COUNT_CYCLES(1); \ |
| 941 | | } |
| 942 | | void tms340x0_device::sra_k_a(UINT16 op) { SRA(A,PARAM_K(op)); } |
| 943 | | void tms340x0_device::sra_k_b(UINT16 op) { SRA(B,PARAM_K(op)); } |
| 944 | | void tms340x0_device::sra_r_a(UINT16 op) { SRA(A,AREG(SRCREG(op))); } |
| 945 | | void tms340x0_device::sra_r_b(UINT16 op) { SRA(B,BREG(SRCREG(op))); } |
| 946 | | |
| 947 | | #define SRL(R,K) \ |
| 948 | | { \ |
| 949 | | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 950 | | UINT32 res = *rd; \ |
| 951 | | INT32 k = (-(K)) & 0x1f; \ |
| 952 | | CLR_CZ(); \ |
| 953 | | if (k) \ |
| 954 | | { \ |
| 955 | | res>>=(k-1); \ |
| 956 | | SET_C_BIT_LO(res, 0); \ |
| 957 | | res>>=1; \ |
| 958 | | *rd = res; \ |
| 959 | | } \ |
| 960 | | SET_Z_VAL(res); \ |
| 961 | | COUNT_CYCLES(1); \ |
| 962 | | } |
| 963 | | void tms340x0_device::srl_k_a(UINT16 op) { SRL(A,PARAM_K(op)); } |
| 964 | | void tms340x0_device::srl_k_b(UINT16 op) { SRL(B,PARAM_K(op)); } |
| 965 | | void tms340x0_device::srl_r_a(UINT16 op) { SRL(A,AREG(SRCREG(op))); } |
| 966 | | void tms340x0_device::srl_r_b(UINT16 op) { SRL(B,BREG(SRCREG(op))); } |
| 967 | | |
| 968 | | #define SUB(R) \ |
| 969 | | { \ |
| 970 | | INT32 *rs = &R##REG(SRCREG(op)); \ |
| 971 | | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 972 | | INT32 r = *rd - *rs; \ |
| 973 | | CLR_NCZV(); \ |
| 974 | | SET_NZCV_SUB(*rd,*rs,r); \ |
| 975 | | *rd = r; \ |
| 976 | | COUNT_CYCLES(1); \ |
| 977 | | } |
| 978 | | void tms340x0_device::sub_a(UINT16 op) { SUB(A); } |
| 979 | | void tms340x0_device::sub_b(UINT16 op) { SUB(B); } |
| 980 | | |
| 981 | | #define SUBB(R) \ |
| 982 | | { \ |
| 983 | | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 984 | | INT32 t = R##REG(SRCREG(op)); \ |
| 985 | | INT32 r = *rd - t - (C_FLAG() ? 1 : 0); \ |
| 986 | | CLR_NCZV(); \ |
| 987 | | SET_NZCV_SUB(*rd,t,r); \ |
| 988 | | *rd = r; \ |
| 989 | | COUNT_CYCLES(1); \ |
| 990 | | } |
| 991 | | void tms340x0_device::subb_a(UINT16 op) { SUBB(A); } |
| 992 | | void tms340x0_device::subb_b(UINT16 op) { SUBB(B); } |
| 993 | | |
| 994 | | #define SUBI_W(R) \ |
| 995 | | { \ |
| 996 | | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 997 | | INT32 r; \ |
| 998 | | INT32 t = ~PARAM_WORD(); \ |
| 999 | | CLR_NCZV(); \ |
| 1000 | | r = *rd - t; \ |
| 1001 | | SET_NZCV_SUB(*rd,t,r); \ |
| 1002 | | *rd = r; \ |
| 1003 | | COUNT_CYCLES(2); \ |
| 1004 | | } |
| 1005 | | void tms340x0_device::subi_w_a(UINT16 op) { SUBI_W(A); } |
| 1006 | | void tms340x0_device::subi_w_b(UINT16 op) { SUBI_W(B); } |
| 1007 | | |
| 1008 | | #define SUBI_L(R) \ |
| 1009 | | { \ |
| 1010 | | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 1011 | | INT32 t = ~PARAM_LONG(); \ |
| 1012 | | INT32 r = *rd - t; \ |
| 1013 | | CLR_NCZV(); \ |
| 1014 | | SET_NZCV_SUB(*rd,t,r); \ |
| 1015 | | *rd = r; \ |
| 1016 | | COUNT_CYCLES(3); \ |
| 1017 | | } |
| 1018 | | void tms340x0_device::subi_l_a(UINT16 op) { SUBI_L(A); } |
| 1019 | | void tms340x0_device::subi_l_b(UINT16 op) { SUBI_L(B); } |
| 1020 | | |
| 1021 | | #define SUBK(R) \ |
| 1022 | | { \ |
| 1023 | | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 1024 | | INT32 t = fw_inc[PARAM_K(op)]; \ |
| 1025 | | INT32 r = *rd - t; \ |
| 1026 | | CLR_NCZV(); \ |
| 1027 | | SET_NZCV_SUB(*rd,t,r); \ |
| 1028 | | *rd = r; \ |
| 1029 | | COUNT_CYCLES(1); \ |
| 1030 | | } |
| 1031 | | void tms340x0_device::subk_a(UINT16 op) { SUBK(A); } |
| 1032 | | void tms340x0_device::subk_b(UINT16 op) { SUBK(B); } |
| 1033 | | |
| 1034 | | #define XOR(R) \ |
| 1035 | | { \ |
| 1036 | | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 1037 | | CLR_Z(); \ |
| 1038 | | *rd ^= R##REG(SRCREG(op)); \ |
| 1039 | | SET_Z_VAL(*rd); \ |
| 1040 | | COUNT_CYCLES(1); \ |
| 1041 | | } |
| 1042 | | void tms340x0_device::xor_a(UINT16 op) { XOR(A); } |
| 1043 | | void tms340x0_device::xor_b(UINT16 op) { XOR(B); } |
| 1044 | | |
| 1045 | | #define XORI(R) \ |
| 1046 | | { \ |
| 1047 | | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 1048 | | CLR_Z(); \ |
| 1049 | | *rd ^= PARAM_LONG(); \ |
| 1050 | | SET_Z_VAL(*rd); \ |
| 1051 | | COUNT_CYCLES(3); \ |
| 1052 | | } |
| 1053 | | void tms340x0_device::xori_a(UINT16 op) { XORI(A); } |
| 1054 | | void tms340x0_device::xori_b(UINT16 op) { XORI(B); } |
| 1055 | | |
| 1056 | | #define ZEXT(F,R) \ |
| 1057 | | { \ |
| 1058 | | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 1059 | | CLR_Z(); \ |
| 1060 | | ZEXTEND(*rd,FW(F)); \ |
| 1061 | | SET_Z_VAL(*rd); \ |
| 1062 | | COUNT_CYCLES(1); \ |
| 1063 | | } |
| 1064 | | void tms340x0_device::zext0_a(UINT16 op) { ZEXT(0,A); } |
| 1065 | | void tms340x0_device::zext0_b(UINT16 op) { ZEXT(0,B); } |
| 1066 | | void tms340x0_device::zext1_a(UINT16 op) { ZEXT(1,A); } |
| 1067 | | void tms340x0_device::zext1_b(UINT16 op) { ZEXT(1,B); } |
| 1068 | | |
| 1069 | | |
| 1070 | | |
| 1071 | | /*************************************************************************** |
| 1072 | | MOVE INSTRUCTIONS |
| 1073 | | ***************************************************************************/ |
| 1074 | | |
| 1075 | | #define MOVI_W(R) \ |
| 1076 | | { \ |
| 1077 | | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 1078 | | CLR_NZV(); \ |
| 1079 | | *rd=PARAM_WORD(); \ |
| 1080 | | SET_NZ_VAL(*rd); \ |
| 1081 | | COUNT_CYCLES(2); \ |
| 1082 | | } |
| 1083 | | void tms340x0_device::movi_w_a(UINT16 op) { MOVI_W(A); } |
| 1084 | | void tms340x0_device::movi_w_b(UINT16 op) { MOVI_W(B); } |
| 1085 | | |
| 1086 | | #define MOVI_L(R) \ |
| 1087 | | { \ |
| 1088 | | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 1089 | | CLR_NZV(); \ |
| 1090 | | *rd=PARAM_LONG(); \ |
| 1091 | | SET_NZ_VAL(*rd); \ |
| 1092 | | COUNT_CYCLES(3); \ |
| 1093 | | } |
| 1094 | | void tms340x0_device::movi_l_a(UINT16 op) { MOVI_L(A); } |
| 1095 | | void tms340x0_device::movi_l_b(UINT16 op) { MOVI_L(B); } |
| 1096 | | |
| 1097 | | #define MOVK(R) \ |
| 1098 | | { \ |
| 1099 | | INT32 k = PARAM_K(op); if (!k) k = 32; \ |
| 1100 | | R##REG(DSTREG(op)) = k; \ |
| 1101 | | COUNT_CYCLES(1); \ |
| 1102 | | } |
| 1103 | | void tms340x0_device::movk_a(UINT16 op) { MOVK(A); } |
| 1104 | | void tms340x0_device::movk_b(UINT16 op) { MOVK(B); } |
| 1105 | | |
| 1106 | | #define MOVB_RN(R) \ |
| 1107 | | { \ |
| 1108 | | WBYTE(R##REG(DSTREG(op)),R##REG(SRCREG(op))); \ |
| 1109 | | COUNT_CYCLES(1); \ |
| 1110 | | } |
| 1111 | | void tms340x0_device::movb_rn_a(UINT16 op) { MOVB_RN(A); } |
| 1112 | | void tms340x0_device::movb_rn_b(UINT16 op) { MOVB_RN(B); } |
| 1113 | | |
| 1114 | | #define MOVB_NR(R) \ |
| 1115 | | { \ |
| 1116 | | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 1117 | | CLR_NZV(); \ |
| 1118 | | *rd = (INT8)RBYTE(R##REG(SRCREG(op))); \ |
| 1119 | | SET_NZ_VAL(*rd); \ |
| 1120 | | COUNT_CYCLES(3); \ |
| 1121 | | } |
| 1122 | | void tms340x0_device::movb_nr_a(UINT16 op) { MOVB_NR(A); } |
| 1123 | | void tms340x0_device::movb_nr_b(UINT16 op) { MOVB_NR(B); } |
| 1124 | | |
| 1125 | | #define MOVB_NN(R) \ |
| 1126 | | { \ |
| 1127 | | WBYTE(R##REG(DSTREG(op)),(UINT32)(UINT8)RBYTE(R##REG(SRCREG(op))));\ |
| 1128 | | COUNT_CYCLES(3); \ |
| 1129 | | } |
| 1130 | | void tms340x0_device::movb_nn_a(UINT16 op) { MOVB_NN(A); } |
| 1131 | | void tms340x0_device::movb_nn_b(UINT16 op) { MOVB_NN(B); } |
| 1132 | | |
| 1133 | | #define MOVB_R_NO(R) \ |
| 1134 | | { \ |
| 1135 | | INT32 o = PARAM_WORD(); \ |
| 1136 | | WBYTE(R##REG(DSTREG(op))+o,R##REG(SRCREG(op))); \ |
| 1137 | | COUNT_CYCLES(3); \ |
| 1138 | | } |
| 1139 | | void tms340x0_device::movb_r_no_a(UINT16 op) { MOVB_R_NO(A); } |
| 1140 | | void tms340x0_device::movb_r_no_b(UINT16 op) { MOVB_R_NO(B); } |
| 1141 | | |
| 1142 | | #define MOVB_NO_R(R) \ |
| 1143 | | { \ |
| 1144 | | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 1145 | | INT32 o = PARAM_WORD(); \ |
| 1146 | | CLR_NZV(); \ |
| 1147 | | *rd = (INT8)RBYTE(R##REG(SRCREG(op))+o); \ |
| 1148 | | SET_NZ_VAL(*rd); \ |
| 1149 | | COUNT_CYCLES(5); \ |
| 1150 | | } |
| 1151 | | void tms340x0_device::movb_no_r_a(UINT16 op) { MOVB_NO_R(A); } |
| 1152 | | void tms340x0_device::movb_no_r_b(UINT16 op) { MOVB_NO_R(B); } |
| 1153 | | |
| 1154 | | #define MOVB_NO_NO(R) \ |
| 1155 | | { \ |
| 1156 | | INT32 o1 = PARAM_WORD(); \ |
| 1157 | | INT32 o2 = PARAM_WORD(); \ |
| 1158 | | WBYTE(R##REG(DSTREG(op))+o2,(UINT32)(UINT8)RBYTE(R##REG(SRCREG(op))+o1)); \ |
| 1159 | | COUNT_CYCLES(5); \ |
| 1160 | | } |
| 1161 | | void tms340x0_device::movb_no_no_a(UINT16 op) { MOVB_NO_NO(A); } |
| 1162 | | void tms340x0_device::movb_no_no_b(UINT16 op) { MOVB_NO_NO(B); } |
| 1163 | | |
| 1164 | | #define MOVB_RA(R) \ |
| 1165 | | { \ |
| 1166 | | WBYTE(PARAM_LONG(),R##REG(DSTREG(op))); \ |
| 1167 | | COUNT_CYCLES(1); \ |
| 1168 | | } |
| 1169 | | void tms340x0_device::movb_ra_a(UINT16 op) { MOVB_RA(A); } |
| 1170 | | void tms340x0_device::movb_ra_b(UINT16 op) { MOVB_RA(B); } |
| 1171 | | |
| 1172 | | #define MOVB_AR(R) \ |
| 1173 | | { \ |
| 1174 | | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 1175 | | CLR_NZV(); \ |
| 1176 | | *rd = (INT8)RBYTE(PARAM_LONG()); \ |
| 1177 | | SET_NZ_VAL(*rd); \ |
| 1178 | | COUNT_CYCLES(5); \ |
| 1179 | | } |
| 1180 | | void tms340x0_device::movb_ar_a(UINT16 op) { MOVB_AR(A); } |
| 1181 | | void tms340x0_device::movb_ar_b(UINT16 op) { MOVB_AR(B); } |
| 1182 | | |
| 1183 | | void tms340x0_device::movb_aa(UINT16 op) |
| 1184 | | { |
| 1185 | | UINT32 bitaddrs=PARAM_LONG(); |
| 1186 | | WBYTE(PARAM_LONG(),(UINT32)(UINT8)RBYTE(bitaddrs)); |
| 1187 | | COUNT_CYCLES(6); |
| 1188 | | } |
| 1189 | | |
| 1190 | | #define MOVE_RR(RS,RD) \ |
| 1191 | | { \ |
| 1192 | | INT32 *rd = &RD##REG(DSTREG(op)); \ |
| 1193 | | CLR_NZV(); \ |
| 1194 | | *rd = RS##REG(SRCREG(op)); \ |
| 1195 | | SET_NZ_VAL(*rd); \ |
| 1196 | | COUNT_CYCLES(1); \ |
| 1197 | | } |
| 1198 | | void tms340x0_device::move_rr_a (UINT16 op) { MOVE_RR(A,A); } |
| 1199 | | void tms340x0_device::move_rr_b (UINT16 op) { MOVE_RR(B,B); } |
| 1200 | | void tms340x0_device::move_rr_ax(UINT16 op) { MOVE_RR(A,B); } |
| 1201 | | void tms340x0_device::move_rr_bx(UINT16 op) { MOVE_RR(B,A); } |
| 1202 | | |
| 1203 | | #define MOVE_RN(F,R) \ |
| 1204 | | { \ |
| 1205 | | WFIELD##F(R##REG(DSTREG(op)),R##REG(SRCREG(op))); \ |
| 1206 | | COUNT_CYCLES(1); \ |
| 1207 | | } |
| 1208 | | void tms340x0_device::move0_rn_a (UINT16 op) { MOVE_RN(0,A); } |
| 1209 | | void tms340x0_device::move0_rn_b (UINT16 op) { MOVE_RN(0,B); } |
| 1210 | | void tms340x0_device::move1_rn_a (UINT16 op) { MOVE_RN(1,A); } |
| 1211 | | void tms340x0_device::move1_rn_b (UINT16 op) { MOVE_RN(1,B); } |
| 1212 | | |
| 1213 | | #define MOVE_R_DN(F,R) \ |
| 1214 | | { \ |
| 1215 | | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 1216 | | *rd-=fw_inc[FW(F)]; \ |
| 1217 | | WFIELD##F(*rd,R##REG(SRCREG(op))); \ |
| 1218 | | COUNT_CYCLES(2); \ |
| 1219 | | } |
| 1220 | | void tms340x0_device::move0_r_dn_a (UINT16 op) { MOVE_R_DN(0,A); } |
| 1221 | | void tms340x0_device::move0_r_dn_b (UINT16 op) { MOVE_R_DN(0,B); } |
| 1222 | | void tms340x0_device::move1_r_dn_a (UINT16 op) { MOVE_R_DN(1,A); } |
| 1223 | | void tms340x0_device::move1_r_dn_b (UINT16 op) { MOVE_R_DN(1,B); } |
| 1224 | | |
| 1225 | | #define MOVE_R_NI(F,R) \ |
| 1226 | | { \ |
| 1227 | | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 1228 | | WFIELD##F(*rd,R##REG(SRCREG(op))); \ |
| 1229 | | *rd+=fw_inc[FW(F)]; \ |
| 1230 | | COUNT_CYCLES(1); \ |
| 1231 | | } |
| 1232 | | void tms340x0_device::move0_r_ni_a (UINT16 op) { MOVE_R_NI(0,A); } |
| 1233 | | void tms340x0_device::move0_r_ni_b (UINT16 op) { MOVE_R_NI(0,B); } |
| 1234 | | void tms340x0_device::move1_r_ni_a (UINT16 op) { MOVE_R_NI(1,A); } |
| 1235 | | void tms340x0_device::move1_r_ni_b (UINT16 op) { MOVE_R_NI(1,B); } |
| 1236 | | |
| 1237 | | #define MOVE_NR(F,R) \ |
| 1238 | | { \ |
| 1239 | | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 1240 | | CLR_NZV(); \ |
| 1241 | | *rd = RFIELD##F(R##REG(SRCREG(op))); \ |
| 1242 | | SET_NZ_VAL(*rd); \ |
| 1243 | | COUNT_CYCLES(3); \ |
| 1244 | | } |
| 1245 | | void tms340x0_device::move0_nr_a (UINT16 op) { MOVE_NR(0,A); } |
| 1246 | | void tms340x0_device::move0_nr_b (UINT16 op) { MOVE_NR(0,B); } |
| 1247 | | void tms340x0_device::move1_nr_a (UINT16 op) { MOVE_NR(1,A); } |
| 1248 | | void tms340x0_device::move1_nr_b (UINT16 op) { MOVE_NR(1,B); } |
| 1249 | | |
| 1250 | | #define MOVE_DN_R(F,R) \ |
| 1251 | | { \ |
| 1252 | | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 1253 | | INT32 *rs = &R##REG(SRCREG(op)); \ |
| 1254 | | CLR_NZV(); \ |
| 1255 | | *rs-=fw_inc[FW(F)]; \ |
| 1256 | | *rd = RFIELD##F(*rs); \ |
| 1257 | | SET_NZ_VAL(*rd); \ |
| 1258 | | COUNT_CYCLES(4); \ |
| 1259 | | } |
| 1260 | | void tms340x0_device::move0_dn_r_a (UINT16 op) { MOVE_DN_R(0,A); } |
| 1261 | | void tms340x0_device::move0_dn_r_b (UINT16 op) { MOVE_DN_R(0,B); } |
| 1262 | | void tms340x0_device::move1_dn_r_a (UINT16 op) { MOVE_DN_R(1,A); } |
| 1263 | | void tms340x0_device::move1_dn_r_b (UINT16 op) { MOVE_DN_R(1,B); } |
| 1264 | | |
| 1265 | | #define MOVE_NI_R(F,R) \ |
| 1266 | | { \ |
| 1267 | | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 1268 | | INT32 *rs = &R##REG(SRCREG(op)); \ |
| 1269 | | INT32 data = RFIELD##F(*rs); \ |
| 1270 | | CLR_NZV(); \ |
| 1271 | | *rs+=fw_inc[FW(F)]; \ |
| 1272 | | *rd = data; \ |
| 1273 | | SET_NZ_VAL(*rd); \ |
| 1274 | | COUNT_CYCLES(3); \ |
| 1275 | | } |
| 1276 | | void tms340x0_device::move0_ni_r_a (UINT16 op) { MOVE_NI_R(0,A); } |
| 1277 | | void tms340x0_device::move0_ni_r_b (UINT16 op) { MOVE_NI_R(0,B); } |
| 1278 | | void tms340x0_device::move1_ni_r_a (UINT16 op) { MOVE_NI_R(1,A); } |
| 1279 | | void tms340x0_device::move1_ni_r_b (UINT16 op) { MOVE_NI_R(1,B); } |
| 1280 | | |
| 1281 | | #define MOVE_NN(F,R) \ |
| 1282 | | { \ |
| 1283 | | WFIELD##F(R##REG(DSTREG(op)),RFIELD##F(R##REG(SRCREG(op)))); \ |
| 1284 | | COUNT_CYCLES(3); \ |
| 1285 | | } |
| 1286 | | void tms340x0_device::move0_nn_a (UINT16 op) { MOVE_NN(0,A); } |
| 1287 | | void tms340x0_device::move0_nn_b (UINT16 op) { MOVE_NN(0,B); } |
| 1288 | | void tms340x0_device::move1_nn_a (UINT16 op) { MOVE_NN(1,A); } |
| 1289 | | void tms340x0_device::move1_nn_b (UINT16 op) { MOVE_NN(1,B); } |
| 1290 | | |
| 1291 | | #define MOVE_DN_DN(F,R) \ |
| 1292 | | { \ |
| 1293 | | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 1294 | | INT32 *rs = &R##REG(SRCREG(op)); \ |
| 1295 | | INT32 data; \ |
| 1296 | | *rs-=fw_inc[FW(F)]; \ |
| 1297 | | data = RFIELD##F(*rs); \ |
| 1298 | | *rd-=fw_inc[FW(F)]; \ |
| 1299 | | WFIELD##F(*rd,data); \ |
| 1300 | | COUNT_CYCLES(4); \ |
| 1301 | | } |
| 1302 | | void tms340x0_device::move0_dn_dn_a (UINT16 op) { MOVE_DN_DN(0,A); } |
| 1303 | | void tms340x0_device::move0_dn_dn_b (UINT16 op) { MOVE_DN_DN(0,B); } |
| 1304 | | void tms340x0_device::move1_dn_dn_a (UINT16 op) { MOVE_DN_DN(1,A); } |
| 1305 | | void tms340x0_device::move1_dn_dn_b (UINT16 op) { MOVE_DN_DN(1,B); } |
| 1306 | | |
| 1307 | | #define MOVE_NI_NI(F,R) \ |
| 1308 | | { \ |
| 1309 | | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 1310 | | INT32 *rs = &R##REG(SRCREG(op)); \ |
| 1311 | | INT32 data = RFIELD##F(*rs); \ |
| 1312 | | *rs+=fw_inc[FW(F)]; \ |
| 1313 | | WFIELD##F(*rd,data); \ |
| 1314 | | *rd+=fw_inc[FW(F)]; \ |
| 1315 | | COUNT_CYCLES(4); \ |
| 1316 | | } |
| 1317 | | void tms340x0_device::move0_ni_ni_a (UINT16 op) { MOVE_NI_NI(0,A); } |
| 1318 | | void tms340x0_device::move0_ni_ni_b (UINT16 op) { MOVE_NI_NI(0,B); } |
| 1319 | | void tms340x0_device::move1_ni_ni_a (UINT16 op) { MOVE_NI_NI(1,A); } |
| 1320 | | void tms340x0_device::move1_ni_ni_b (UINT16 op) { MOVE_NI_NI(1,B); } |
| 1321 | | |
| 1322 | | #define MOVE_R_NO(F,R) \ |
| 1323 | | { \ |
| 1324 | | INT32 o = PARAM_WORD(); \ |
| 1325 | | WFIELD##F(R##REG(DSTREG(op))+o,R##REG(SRCREG(op))); \ |
| 1326 | | COUNT_CYCLES(3); \ |
| 1327 | | } |
| 1328 | | void tms340x0_device::move0_r_no_a (UINT16 op) { MOVE_R_NO(0,A); } |
| 1329 | | void tms340x0_device::move0_r_no_b (UINT16 op) { MOVE_R_NO(0,B); } |
| 1330 | | void tms340x0_device::move1_r_no_a (UINT16 op) { MOVE_R_NO(1,A); } |
| 1331 | | void tms340x0_device::move1_r_no_b (UINT16 op) { MOVE_R_NO(1,B); } |
| 1332 | | |
| 1333 | | #define MOVE_NO_R(F,R) \ |
| 1334 | | { \ |
| 1335 | | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 1336 | | INT32 o = PARAM_WORD(); \ |
| 1337 | | CLR_NZV(); \ |
| 1338 | | *rd = RFIELD##F(R##REG(SRCREG(op))+o); \ |
| 1339 | | SET_NZ_VAL(*rd); \ |
| 1340 | | COUNT_CYCLES(5); \ |
| 1341 | | } |
| 1342 | | void tms340x0_device::move0_no_r_a (UINT16 op) { MOVE_NO_R(0,A); } |
| 1343 | | void tms340x0_device::move0_no_r_b (UINT16 op) { MOVE_NO_R(0,B); } |
| 1344 | | void tms340x0_device::move1_no_r_a (UINT16 op) { MOVE_NO_R(1,A); } |
| 1345 | | void tms340x0_device::move1_no_r_b (UINT16 op) { MOVE_NO_R(1,B); } |
| 1346 | | |
| 1347 | | #define MOVE_NO_NI(F,R) \ |
| 1348 | | { \ |
| 1349 | | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 1350 | | INT32 o = PARAM_WORD(); \ |
| 1351 | | INT32 data = RFIELD##F(R##REG(SRCREG(op))+o); \ |
| 1352 | | WFIELD##F(*rd,data); \ |
| 1353 | | *rd+=fw_inc[FW(F)]; \ |
| 1354 | | COUNT_CYCLES(5); \ |
| 1355 | | } |
| 1356 | | void tms340x0_device::move0_no_ni_a (UINT16 op) { MOVE_NO_NI(0,A); } |
| 1357 | | void tms340x0_device::move0_no_ni_b (UINT16 op) { MOVE_NO_NI(0,B); } |
| 1358 | | void tms340x0_device::move1_no_ni_a (UINT16 op) { MOVE_NO_NI(1,A); } |
| 1359 | | void tms340x0_device::move1_no_ni_b (UINT16 op) { MOVE_NO_NI(1,B); } |
| 1360 | | |
| 1361 | | #define MOVE_NO_NO(F,R) \ |
| 1362 | | { \ |
| 1363 | | INT32 o1 = PARAM_WORD(); \ |
| 1364 | | INT32 o2 = PARAM_WORD(); \ |
| 1365 | | INT32 data = RFIELD##F(R##REG(SRCREG(op))+o1); \ |
| 1366 | | WFIELD##F(R##REG(DSTREG(op))+o2,data); \ |
| 1367 | | COUNT_CYCLES(5); \ |
| 1368 | | } |
| 1369 | | void tms340x0_device::move0_no_no_a (UINT16 op) { MOVE_NO_NO(0,A); } |
| 1370 | | void tms340x0_device::move0_no_no_b (UINT16 op) { MOVE_NO_NO(0,B); } |
| 1371 | | void tms340x0_device::move1_no_no_a (UINT16 op) { MOVE_NO_NO(1,A); } |
| 1372 | | void tms340x0_device::move1_no_no_b (UINT16 op) { MOVE_NO_NO(1,B); } |
| 1373 | | |
| 1374 | | #define MOVE_RA(F,R) \ |
| 1375 | | { \ |
| 1376 | | WFIELD##F(PARAM_LONG(),R##REG(DSTREG(op))); \ |
| 1377 | | COUNT_CYCLES(3); \ |
| 1378 | | } |
| 1379 | | void tms340x0_device::move0_ra_a (UINT16 op) { MOVE_RA(0,A); } |
| 1380 | | void tms340x0_device::move0_ra_b (UINT16 op) { MOVE_RA(0,B); } |
| 1381 | | void tms340x0_device::move1_ra_a (UINT16 op) { MOVE_RA(1,A); } |
| 1382 | | void tms340x0_device::move1_ra_b (UINT16 op) { MOVE_RA(1,B); } |
| 1383 | | |
| 1384 | | #define MOVE_AR(F,R) \ |
| 1385 | | { \ |
| 1386 | | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 1387 | | CLR_NZV(); \ |
| 1388 | | *rd = RFIELD##F(PARAM_LONG()); \ |
| 1389 | | SET_NZ_VAL(*rd); \ |
| 1390 | | COUNT_CYCLES(5); \ |
| 1391 | | } |
| 1392 | | void tms340x0_device::move0_ar_a (UINT16 op) { MOVE_AR(0,A); } |
| 1393 | | void tms340x0_device::move0_ar_b (UINT16 op) { MOVE_AR(0,B); } |
| 1394 | | void tms340x0_device::move1_ar_a (UINT16 op) { MOVE_AR(1,A); } |
| 1395 | | void tms340x0_device::move1_ar_b (UINT16 op) { MOVE_AR(1,B); } |
| 1396 | | |
| 1397 | | #define MOVE_A_NI(F,R) \ |
| 1398 | | { \ |
| 1399 | | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 1400 | | WFIELD##F(*rd,RFIELD##F(PARAM_LONG())); \ |
| 1401 | | *rd+=fw_inc[FW(F)]; \ |
| 1402 | | COUNT_CYCLES(5); \ |
| 1403 | | } |
| 1404 | | void tms340x0_device::move0_a_ni_a (UINT16 op) { MOVE_A_NI(0,A); } |
| 1405 | | void tms340x0_device::move0_a_ni_b (UINT16 op) { MOVE_A_NI(0,B); } |
| 1406 | | void tms340x0_device::move1_a_ni_a (UINT16 op) { MOVE_A_NI(1,A); } |
| 1407 | | void tms340x0_device::move1_a_ni_b (UINT16 op) { MOVE_A_NI(1,B); } |
| 1408 | | |
| 1409 | | #define MOVE_AA(F) \ |
| 1410 | | { \ |
| 1411 | | UINT32 bitaddrs=PARAM_LONG(); \ |
| 1412 | | WFIELD##F(PARAM_LONG(),RFIELD##F(bitaddrs)); \ |
| 1413 | | COUNT_CYCLES(7); \ |
| 1414 | | } |
| 1415 | | void tms340x0_device::move0_aa (UINT16 op) { MOVE_AA(0); } |
| 1416 | | void tms340x0_device::move1_aa (UINT16 op) { MOVE_AA(1); } |
| 1417 | | |
| 1418 | | |
| 1419 | | |
| 1420 | | /*************************************************************************** |
| 1421 | | PROGRAM CONTROL INSTRUCTIONS |
| 1422 | | ***************************************************************************/ |
| 1423 | | |
| 1424 | | #define CALL(R) \ |
| 1425 | | { \ |
| 1426 | | PUSH(m_pc); \ |
| 1427 | | m_pc = R##REG(DSTREG(op)); \ |
| 1428 | | CORRECT_ODD_PC("CALL"); \ |
| 1429 | | COUNT_CYCLES(3); \ |
| 1430 | | } |
| 1431 | | void tms340x0_device::call_a (UINT16 op) { CALL(A); } |
| 1432 | | void tms340x0_device::call_b (UINT16 op) { CALL(B); } |
| 1433 | | |
| 1434 | | void tms340x0_device::callr(UINT16 op) |
| 1435 | | { |
| 1436 | | PUSH(m_pc+0x10); |
| 1437 | | m_pc += (PARAM_WORD_NO_INC()<<4)+0x10; |
| 1438 | | COUNT_CYCLES(3); |
| 1439 | | } |
| 1440 | | |
| 1441 | | void tms340x0_device::calla(UINT16 op) |
| 1442 | | { |
| 1443 | | PUSH(m_pc+0x20); |
| 1444 | | m_pc = PARAM_LONG_NO_INC(); |
| 1445 | | CORRECT_ODD_PC("CALLA"); |
| 1446 | | COUNT_CYCLES(4); |
| 1447 | | } |
| 1448 | | |
| 1449 | | #define DSJ(R) \ |
| 1450 | | { \ |
| 1451 | | if (--R##REG(DSTREG(op))) \ |
| 1452 | | { \ |
| 1453 | | m_pc += (PARAM_WORD_NO_INC()<<4)+0x10; \ |
| 1454 | | COUNT_CYCLES(3); \ |
| 1455 | | } \ |
| 1456 | | else \ |
| 1457 | | { \ |
| 1458 | | SKIP_WORD(); \ |
| 1459 | | COUNT_CYCLES(2); \ |
| 1460 | | } \ |
| 1461 | | } |
| 1462 | | void tms340x0_device::dsj_a (UINT16 op) { DSJ(A); } |
| 1463 | | void tms340x0_device::dsj_b (UINT16 op) { DSJ(B); } |
| 1464 | | |
| 1465 | | #define DSJEQ(R) \ |
| 1466 | | { \ |
| 1467 | | if (Z_FLAG()) \ |
| 1468 | | { \ |
| 1469 | | if (--R##REG(DSTREG(op))) \ |
| 1470 | | { \ |
| 1471 | | m_pc += (PARAM_WORD_NO_INC()<<4)+0x10; \ |
| 1472 | | COUNT_CYCLES(3); \ |
| 1473 | | } \ |
| 1474 | | else \ |
| 1475 | | { \ |
| 1476 | | SKIP_WORD(); \ |
| 1477 | | COUNT_CYCLES(2); \ |
| 1478 | | } \ |
| 1479 | | } \ |
| 1480 | | else \ |
| 1481 | | { \ |
| 1482 | | SKIP_WORD(); \ |
| 1483 | | COUNT_CYCLES(2); \ |
| 1484 | | } \ |
| 1485 | | } |
| 1486 | | void tms340x0_device::dsjeq_a (UINT16 op) { DSJEQ(A); } |
| 1487 | | void tms340x0_device::dsjeq_b (UINT16 op) { DSJEQ(B); } |
| 1488 | | |
| 1489 | | #define DSJNE(R) \ |
| 1490 | | { \ |
| 1491 | | if (!Z_FLAG()) \ |
| 1492 | | { \ |
| 1493 | | if (--R##REG(DSTREG(op))) \ |
| 1494 | | { \ |
| 1495 | | m_pc += (PARAM_WORD_NO_INC()<<4)+0x10; \ |
| 1496 | | COUNT_CYCLES(3); \ |
| 1497 | | } \ |
| 1498 | | else \ |
| 1499 | | { \ |
| 1500 | | SKIP_WORD(); \ |
| 1501 | | COUNT_CYCLES(2); \ |
| 1502 | | } \ |
| 1503 | | } \ |
| 1504 | | else \ |
| 1505 | | { \ |
| 1506 | | SKIP_WORD(); \ |
| 1507 | | COUNT_CYCLES(2); \ |
| 1508 | | } \ |
| 1509 | | } |
| 1510 | | void tms340x0_device::dsjne_a (UINT16 op) { DSJNE(A); } |
| 1511 | | void tms340x0_device::dsjne_b (UINT16 op) { DSJNE(B); } |
| 1512 | | |
| 1513 | | #define DSJS(R) \ |
| 1514 | | { \ |
| 1515 | | if (op & 0x0400) \ |
| 1516 | | { \ |
| 1517 | | if (--R##REG(DSTREG(op))) \ |
| 1518 | | { \ |
| 1519 | | m_pc -= ((PARAM_K(op))<<4); \ |
| 1520 | | COUNT_CYCLES(2); \ |
| 1521 | | } \ |
| 1522 | | else \ |
| 1523 | | COUNT_CYCLES(3); \ |
| 1524 | | } \ |
| 1525 | | else \ |
| 1526 | | { \ |
| 1527 | | if (--R##REG(DSTREG(op))) \ |
| 1528 | | { \ |
| 1529 | | m_pc += ((PARAM_K(op))<<4); \ |
| 1530 | | COUNT_CYCLES(2); \ |
| 1531 | | } \ |
| 1532 | | else \ |
| 1533 | | COUNT_CYCLES(3); \ |
| 1534 | | } \ |
| 1535 | | } |
| 1536 | | void tms340x0_device::dsjs_a (UINT16 op) { DSJS(A); } |
| 1537 | | void tms340x0_device::dsjs_b (UINT16 op) { DSJS(B); } |
| 1538 | | |
| 1539 | | void tms340x0_device::emu(UINT16 op) |
| 1540 | | { |
| 1541 | | /* in RUN state, this instruction is a NOP */ |
| 1542 | | COUNT_CYCLES(6); |
| 1543 | | } |
| 1544 | | |
| 1545 | | #define EXGPC(R) \ |
| 1546 | | { \ |
| 1547 | | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 1548 | | INT32 temppc = *rd; \ |
| 1549 | | *rd = m_pc; \ |
| 1550 | | m_pc = temppc; \ |
| 1551 | | CORRECT_ODD_PC("EXGPC"); \ |
| 1552 | | COUNT_CYCLES(2); \ |
| 1553 | | } |
| 1554 | | void tms340x0_device::exgpc_a (UINT16 op) { EXGPC(A); } |
| 1555 | | void tms340x0_device::exgpc_b (UINT16 op) { EXGPC(B); } |
| 1556 | | |
| 1557 | | #define GETPC(R) \ |
| 1558 | | { \ |
| 1559 | | R##REG(DSTREG(op)) = m_pc; \ |
| 1560 | | COUNT_CYCLES(1); \ |
| 1561 | | } |
| 1562 | | void tms340x0_device::getpc_a (UINT16 op) { GETPC(A); } |
| 1563 | | void tms340x0_device::getpc_b (UINT16 op) { GETPC(B); } |
| 1564 | | |
| 1565 | | #define GETST(R) \ |
| 1566 | | { \ |
| 1567 | | R##REG(DSTREG(op)) = m_st; \ |
| 1568 | | COUNT_CYCLES(1); \ |
| 1569 | | } |
| 1570 | | void tms340x0_device::getst_a (UINT16 op) { GETST(A); } |
| 1571 | | void tms340x0_device::getst_b (UINT16 op) { GETST(B); } |
| 1572 | | |
| 1573 | | #define j_xx_8(TAKE) \ |
| 1574 | | { \ |
| 1575 | | if (DSTREG(op)) \ |
| 1576 | | { \ |
| 1577 | | if (TAKE) \ |
| 1578 | | { \ |
| 1579 | | m_pc += (PARAM_REL8(op) << 4); \ |
| 1580 | | COUNT_CYCLES(2); \ |
| 1581 | | } \ |
| 1582 | | else \ |
| 1583 | | COUNT_CYCLES(1); \ |
| 1584 | | } \ |
| 1585 | | else \ |
| 1586 | | { \ |
| 1587 | | if (TAKE) \ |
| 1588 | | { \ |
| 1589 | | m_pc = PARAM_LONG_NO_INC(); \ |
| 1590 | | CORRECT_ODD_PC("J_XX_8"); \ |
| 1591 | | COUNT_CYCLES(3); \ |
| 1592 | | } \ |
| 1593 | | else \ |
| 1594 | | { \ |
| 1595 | | SKIP_LONG(); \ |
| 1596 | | COUNT_CYCLES(4); \ |
| 1597 | | } \ |
| 1598 | | } \ |
| 1599 | | } |
| 1600 | | |
| 1601 | | #define j_xx_0(TAKE) \ |
| 1602 | | { \ |
| 1603 | | if (DSTREG(op)) \ |
| 1604 | | { \ |
| 1605 | | if (TAKE) \ |
| 1606 | | { \ |
| 1607 | | m_pc += (PARAM_REL8(op) << 4); \ |
| 1608 | | COUNT_CYCLES(2); \ |
| 1609 | | } \ |
| 1610 | | else \ |
| 1611 | | COUNT_CYCLES(1); \ |
| 1612 | | } \ |
| 1613 | | else \ |
| 1614 | | { \ |
| 1615 | | if (TAKE) \ |
| 1616 | | { \ |
| 1617 | | m_pc += (PARAM_WORD_NO_INC()<<4)+0x10; \ |
| 1618 | | COUNT_CYCLES(3); \ |
| 1619 | | } \ |
| 1620 | | else \ |
| 1621 | | { \ |
| 1622 | | SKIP_WORD(); \ |
| 1623 | | COUNT_CYCLES(2); \ |
| 1624 | | } \ |
| 1625 | | } \ |
| 1626 | | } |
| 1627 | | |
| 1628 | | #define j_xx_x(TAKE) \ |
| 1629 | | { \ |
| 1630 | | if (TAKE) \ |
| 1631 | | { \ |
| 1632 | | m_pc += (PARAM_REL8(op) << 4); \ |
| 1633 | | COUNT_CYCLES(2); \ |
| 1634 | | } \ |
| 1635 | | else \ |
| 1636 | | COUNT_CYCLES(1); \ |
| 1637 | | } |
| 1638 | | |
| 1639 | | void tms340x0_device::j_UC_0(UINT16 op) |
| 1640 | | { |
| 1641 | | j_xx_0(1); |
| 1642 | | } |
| 1643 | | void tms340x0_device::j_UC_8(UINT16 op) |
| 1644 | | { |
| 1645 | | j_xx_8(1); |
| 1646 | | } |
| 1647 | | void tms340x0_device::j_UC_x(UINT16 op) |
| 1648 | | { |
| 1649 | | j_xx_x(1); |
| 1650 | | } |
| 1651 | | void tms340x0_device::j_P_0(UINT16 op) |
| 1652 | | { |
| 1653 | | j_xx_0(!N_FLAG() && !Z_FLAG()); |
| 1654 | | } |
| 1655 | | void tms340x0_device::j_P_8(UINT16 op) |
| 1656 | | { |
| 1657 | | j_xx_8(!N_FLAG() && !Z_FLAG()); |
| 1658 | | } |
| 1659 | | void tms340x0_device::j_P_x(UINT16 op) |
| 1660 | | { |
| 1661 | | j_xx_x(!N_FLAG() && !Z_FLAG()); |
| 1662 | | } |
| 1663 | | void tms340x0_device::j_LS_0(UINT16 op) |
| 1664 | | { |
| 1665 | | j_xx_0(C_FLAG() || Z_FLAG()); |
| 1666 | | } |
| 1667 | | void tms340x0_device::j_LS_8(UINT16 op) |
| 1668 | | { |
| 1669 | | j_xx_8(C_FLAG() || Z_FLAG()); |
| 1670 | | } |
| 1671 | | void tms340x0_device::j_LS_x(UINT16 op) |
| 1672 | | { |
| 1673 | | j_xx_x(C_FLAG() || Z_FLAG()); |
| 1674 | | } |
| 1675 | | void tms340x0_device::j_HI_0(UINT16 op) |
| 1676 | | { |
| 1677 | | j_xx_0(!C_FLAG() && !Z_FLAG()); |
| 1678 | | } |
| 1679 | | void tms340x0_device::j_HI_8(UINT16 op) |
| 1680 | | { |
| 1681 | | j_xx_8(!C_FLAG() && !Z_FLAG()); |
| 1682 | | } |
| 1683 | | void tms340x0_device::j_HI_x(UINT16 op) |
| 1684 | | { |
| 1685 | | j_xx_x(!C_FLAG() && !Z_FLAG()); |
| 1686 | | } |
| 1687 | | void tms340x0_device::j_LT_0(UINT16 op) |
| 1688 | | { |
| 1689 | | j_xx_0((N_FLAG() && !V_FLAG()) || (!N_FLAG() && V_FLAG())); |
| 1690 | | } |
| 1691 | | void tms340x0_device::j_LT_8(UINT16 op) |
| 1692 | | { |
| 1693 | | j_xx_8((N_FLAG() && !V_FLAG()) || (!N_FLAG() && V_FLAG())); |
| 1694 | | } |
| 1695 | | void tms340x0_device::j_LT_x(UINT16 op) |
| 1696 | | { |
| 1697 | | j_xx_x((N_FLAG() && !V_FLAG()) || (!N_FLAG() && V_FLAG())); |
| 1698 | | } |
| 1699 | | void tms340x0_device::j_GE_0(UINT16 op) |
| 1700 | | { |
| 1701 | | j_xx_0((N_FLAG() && V_FLAG()) || (!N_FLAG() && !V_FLAG())); |
| 1702 | | } |
| 1703 | | void tms340x0_device::j_GE_8(UINT16 op) |
| 1704 | | { |
| 1705 | | j_xx_8((N_FLAG() && V_FLAG()) || (!N_FLAG() && !V_FLAG())); |
| 1706 | | } |
| 1707 | | void tms340x0_device::j_GE_x(UINT16 op) |
| 1708 | | { |
| 1709 | | j_xx_x((N_FLAG() && V_FLAG()) || (!N_FLAG() && !V_FLAG())); |
| 1710 | | } |
| 1711 | | void tms340x0_device::j_LE_0(UINT16 op) |
| 1712 | | { |
| 1713 | | j_xx_0((N_FLAG() && !V_FLAG()) || (!N_FLAG() && V_FLAG()) || Z_FLAG()); |
| 1714 | | } |
| 1715 | | void tms340x0_device::j_LE_8(UINT16 op) |
| 1716 | | { |
| 1717 | | j_xx_8((N_FLAG() && !V_FLAG()) || (!N_FLAG() && V_FLAG()) || Z_FLAG()); |
| 1718 | | } |
| 1719 | | void tms340x0_device::j_LE_x(UINT16 op) |
| 1720 | | { |
| 1721 | | j_xx_x((N_FLAG() && !V_FLAG()) || (!N_FLAG() && V_FLAG()) || Z_FLAG()); |
| 1722 | | } |
| 1723 | | void tms340x0_device::j_GT_0(UINT16 op) |
| 1724 | | { |
| 1725 | | j_xx_0((N_FLAG() && V_FLAG() && !Z_FLAG()) || (!N_FLAG() && !V_FLAG() && !Z_FLAG())); |
| 1726 | | } |
| 1727 | | void tms340x0_device::j_GT_8(UINT16 op) |
| 1728 | | { |
| 1729 | | j_xx_8((N_FLAG() && V_FLAG() && !Z_FLAG()) || (!N_FLAG() && !V_FLAG() && !Z_FLAG())); |
| 1730 | | } |
| 1731 | | void tms340x0_device::j_GT_x(UINT16 op) |
| 1732 | | { |
| 1733 | | j_xx_x((N_FLAG() && V_FLAG() && !Z_FLAG()) || (!N_FLAG() && !V_FLAG() && !Z_FLAG())); |
| 1734 | | } |
| 1735 | | void tms340x0_device::j_C_0(UINT16 op) |
| 1736 | | { |
| 1737 | | j_xx_0(C_FLAG()); |
| 1738 | | } |
| 1739 | | void tms340x0_device::j_C_8(UINT16 op) |
| 1740 | | { |
| 1741 | | j_xx_8(C_FLAG()); |
| 1742 | | } |
| 1743 | | void tms340x0_device::j_C_x(UINT16 op) |
| 1744 | | { |
| 1745 | | j_xx_x(C_FLAG()); |
| 1746 | | } |
| 1747 | | void tms340x0_device::j_NC_0(UINT16 op) |
| 1748 | | { |
| 1749 | | j_xx_0(!C_FLAG()); |
| 1750 | | } |
| 1751 | | void tms340x0_device::j_NC_8(UINT16 op) |
| 1752 | | { |
| 1753 | | j_xx_8(!C_FLAG()); |
| 1754 | | } |
| 1755 | | void tms340x0_device::j_NC_x(UINT16 op) |
| 1756 | | { |
| 1757 | | j_xx_x(!C_FLAG()); |
| 1758 | | } |
| 1759 | | void tms340x0_device::j_EQ_0(UINT16 op) |
| 1760 | | { |
| 1761 | | j_xx_0(Z_FLAG()); |
| 1762 | | } |
| 1763 | | void tms340x0_device::j_EQ_8(UINT16 op) |
| 1764 | | { |
| 1765 | | j_xx_8(Z_FLAG()); |
| 1766 | | } |
| 1767 | | void tms340x0_device::j_EQ_x(UINT16 op) |
| 1768 | | { |
| 1769 | | j_xx_x(Z_FLAG()); |
| 1770 | | } |
| 1771 | | void tms340x0_device::j_NE_0(UINT16 op) |
| 1772 | | { |
| 1773 | | j_xx_0(!Z_FLAG()); |
| 1774 | | } |
| 1775 | | void tms340x0_device::j_NE_8(UINT16 op) |
| 1776 | | { |
| 1777 | | j_xx_8(!Z_FLAG()); |
| 1778 | | } |
| 1779 | | void tms340x0_device::j_NE_x(UINT16 op) |
| 1780 | | { |
| 1781 | | j_xx_x(!Z_FLAG()); |
| 1782 | | } |
| 1783 | | void tms340x0_device::j_V_0(UINT16 op) |
| 1784 | | { |
| 1785 | | j_xx_0(V_FLAG()); |
| 1786 | | } |
| 1787 | | void tms340x0_device::j_V_8(UINT16 op) |
| 1788 | | { |
| 1789 | | j_xx_8(V_FLAG()); |
| 1790 | | } |
| 1791 | | void tms340x0_device::j_V_x(UINT16 op) |
| 1792 | | { |
| 1793 | | j_xx_x(V_FLAG()); |
| 1794 | | } |
| 1795 | | void tms340x0_device::j_NV_0(UINT16 op) |
| 1796 | | { |
| 1797 | | j_xx_0(!V_FLAG()); |
| 1798 | | } |
| 1799 | | void tms340x0_device::j_NV_8(UINT16 op) |
| 1800 | | { |
| 1801 | | j_xx_8(!V_FLAG()); |
| 1802 | | } |
| 1803 | | void tms340x0_device::j_NV_x(UINT16 op) |
| 1804 | | { |
| 1805 | | j_xx_x(!V_FLAG()); |
| 1806 | | } |
| 1807 | | void tms340x0_device::j_N_0(UINT16 op) |
| 1808 | | { |
| 1809 | | j_xx_0(N_FLAG()); |
| 1810 | | } |
| 1811 | | void tms340x0_device::j_N_8(UINT16 op) |
| 1812 | | { |
| 1813 | | j_xx_8(N_FLAG()); |
| 1814 | | } |
| 1815 | | void tms340x0_device::j_N_x(UINT16 op) |
| 1816 | | { |
| 1817 | | j_xx_x(N_FLAG()); |
| 1818 | | } |
| 1819 | | void tms340x0_device::j_NN_0(UINT16 op) |
| 1820 | | { |
| 1821 | | j_xx_0(!N_FLAG()); |
| 1822 | | } |
| 1823 | | void tms340x0_device::j_NN_8(UINT16 op) |
| 1824 | | { |
| 1825 | | j_xx_8(!N_FLAG()); |
| 1826 | | } |
| 1827 | | void tms340x0_device::j_NN_x(UINT16 op) |
| 1828 | | { |
| 1829 | | j_xx_x(!N_FLAG()); |
| 1830 | | } |
| 1831 | | |
| 1832 | | #define JUMP(R) \ |
| 1833 | | { \ |
| 1834 | | m_pc = R##REG(DSTREG(op)); \ |
| 1835 | | CORRECT_ODD_PC("JUMP"); \ |
| 1836 | | COUNT_CYCLES(2); \ |
| 1837 | | } |
| 1838 | | void tms340x0_device::jump_a (UINT16 op) { JUMP(A); } |
| 1839 | | void tms340x0_device::jump_b (UINT16 op) { JUMP(B); } |
| 1840 | | |
| 1841 | | void tms340x0_device::popst(UINT16 op) |
| 1842 | | { |
| 1843 | | SET_ST(POP()); |
| 1844 | | COUNT_CYCLES(8); |
| 1845 | | } |
| 1846 | | |
| 1847 | | void tms340x0_device::pushst(UINT16 op) |
| 1848 | | { |
| 1849 | | PUSH(m_st); |
| 1850 | | COUNT_CYCLES(2); |
| 1851 | | } |
| 1852 | | |
| 1853 | | #define PUTST(R) \ |
| 1854 | | { \ |
| 1855 | | SET_ST(R##REG(DSTREG(op))); \ |
| 1856 | | COUNT_CYCLES(3); \ |
| 1857 | | } |
| 1858 | | void tms340x0_device::putst_a (UINT16 op) { PUTST(A); } |
| 1859 | | void tms340x0_device::putst_b (UINT16 op) { PUTST(B); } |
| 1860 | | |
| 1861 | | void tms340x0_device::reti(UINT16 op) |
| 1862 | | { |
| 1863 | | INT32 st = POP(); |
| 1864 | | m_pc = POP(); |
| 1865 | | CORRECT_ODD_PC("RETI"); |
| 1866 | | SET_ST(st); |
| 1867 | | COUNT_CYCLES(11); |
| 1868 | | } |
| 1869 | | |
| 1870 | | void tms340x0_device::rets(UINT16 op) |
| 1871 | | { |
| 1872 | | UINT32 offs; |
| 1873 | | m_pc = POP(); |
| 1874 | | CORRECT_ODD_PC("RETS"); |
| 1875 | | offs = PARAM_N(op); |
| 1876 | | if (offs) |
| 1877 | | { |
| 1878 | | SP()+=(offs<<4); |
| 1879 | | } |
| 1880 | | COUNT_CYCLES(7); |
| 1881 | | } |
| 1882 | | |
| 1883 | | #define REV(R) \ |
| 1884 | | { \ |
| 1885 | | R##REG(DSTREG(op)) = 0x0008; \ |
| 1886 | | COUNT_CYCLES(1); \ |
| 1887 | | } |
| 1888 | | void tms340x0_device::rev_a (UINT16 op) { REV(A); } |
| 1889 | | void tms340x0_device::rev_b (UINT16 op) { REV(B); } |
| 1890 | | |
| 1891 | | void tms340x0_device::trap(UINT16 op) |
| 1892 | | { |
| 1893 | | UINT32 t = PARAM_N(op); |
| 1894 | | if (t) |
| 1895 | | { |
| 1896 | | PUSH(m_pc); |
| 1897 | | PUSH(m_st); |
| 1898 | | } |
| 1899 | | RESET_ST(); |
| 1900 | | m_pc = RLONG(0xffffffe0-(t<<5)); |
| 1901 | | CORRECT_ODD_PC("TRAP"); |
| 1902 | | COUNT_CYCLES(16); |
| 1903 | | } |
| 1904 | | |
| 1905 | | |
| 1906 | | |
| 1907 | | /*************************************************************************** |
| 1908 | | 34020 INSTRUCTIONS |
| 1909 | | ***************************************************************************/ |
| 1910 | | |
| 1911 | | /************************************ |
| 1912 | | |
| 1913 | | New 34020 ops: |
| 1914 | | |
| 1915 | | 0000 1100 000R dddd = ADDXYI IL,Rd |
| 1916 | | iiii iiii iiii iiii |
| 1917 | | iiii iiii iiii iiii |
| 1918 | | |
| 1919 | | 0000 0000 1111 00SD = BLMOVE S,D |
| 1920 | | |
| 1921 | | 0000 0110 0000 0000 = CEXEC S,c,ID,L |
| 1922 | | cccc cccc S000 0000 |
| 1923 | | iiic cccc cccc cccc |
| 1924 | | |
| 1925 | | 1101 1000 0ccc cccS = CEXEC S,c,ID |
| 1926 | | iiic cccc cccc cccc |
| 1927 | | |
| 1928 | | 0000 1000 1111 0010 = CLIP |
| 1929 | | |
| 1930 | | 0000 0110 011R dddd = CMOVCG Rd1,Rd2,S,c,ID |
| 1931 | | cccc cccc S00R dddd |
| 1932 | | iiic cccc cccc cccc |
| 1933 | | |
| 1934 | | 0000 0110 101R dddd = CMOVCM *Rd+,n,S,c,ID |
| 1935 | | cccc cccc S00n nnnn |
| 1936 | | iiic cccc cccc cccc |
| 1937 | | |
| 1938 | | 0000 0110 110R dddd = CMOVCM -*Rd,n,S,c,ID |
| 1939 | | cccc cccc S00n nnnn |
| 1940 | | iiic cccc cccc cccc |
| 1941 | | |
| 1942 | | 0000 0110 0110 0000 = CMOVCS c,ID |
| 1943 | | cccc cccc 0000 0001 |
| 1944 | | iiic cccc cccc cccc |
| 1945 | | |
| 1946 | | 0000 0110 001R ssss = CMOVGC Rs,c,ID |
| 1947 | | cccc cccc 0000 0000 |
| 1948 | | iiic cccc cccc cccc |
| 1949 | | |
| 1950 | | 0000 0110 010R ssss = CMOVGC Rs1,Rs2,S,c,ID |
| 1951 | | cccc cccc S00R ssss |
| 1952 | | iiic cccc cccc cccc |
| 1953 | | |
| 1954 | | 0000 0110 100n nnnn = CMOVMC *Rs+,n,S,c,ID |
| 1955 | | cccc cccc S00R ssss |
| 1956 | | iiic cccc cccc cccc |
| 1957 | | |
| 1958 | | 0000 1000 001n nnnn = CMOVMC -*Rs,n,S,c,ID |
| 1959 | | cccc cccc S00R ssss |
| 1960 | | iiic cccc cccc cccc |
| 1961 | | |
| 1962 | | 0000 0110 111R dddd = CMOVMC *Rs+,Rd,S,c,ID |
| 1963 | | cccc cccc S00R ssss |
| 1964 | | iiic cccc cccc cccc |
| 1965 | | |
| 1966 | | 0011 01kk kkkR dddd = CMPK k,Rd |
| 1967 | | |
| 1968 | | 0000 1010 100R dddd = CVDXYL Rd |
| 1969 | | |
| 1970 | | 0000 1010 011R dddd = CVMXYL Rd |
| 1971 | | |
| 1972 | | 1110 101s sssR dddd = CVSXYL Rs,Rd |
| 1973 | | |
| 1974 | | 0000 0010 101R dddd = EXGPS Rd |
| 1975 | | |
| 1976 | | 1101 1110 Z001 1010 = FLINE Z |
| 1977 | | |
| 1978 | | 0000 1010 1011 1011 = FPIXEQ |
| 1979 | | |
| 1980 | | 0000 1010 1101 1011 = FPIXNE |
| 1981 | | |
| 1982 | | 0000 0010 110R dddd = GETPS Rd |
| 1983 | | |
| 1984 | | 0000 0000 0100 0000 = IDLE |
| 1985 | | |
| 1986 | | 0000 1100 0101 0111 = LINIT |
| 1987 | | |
| 1988 | | 0000 0000 1000 0000 = MWAIT |
| 1989 | | |
| 1990 | | 0000 1010 0011 0111 = PFILL XY |
| 1991 | | |
| 1992 | | 0000 1110 0001 0111 = PIXBLT L,M,L |
| 1993 | | |
| 1994 | | 0000 1000 0110 0000 = RETM |
| 1995 | | |
| 1996 | | 0111 101s sssR dddd = RMO Rs,Rd |
| 1997 | | |
| 1998 | | 0000 0010 100R dddd = RPIX Rd |
| 1999 | | |
| 2000 | | 0000 0010 0111 0011 = SETCDP |
| 2001 | | |
| 2002 | | 0000 0010 1111 1011 = SETCMP |
| 2003 | | |
| 2004 | | 0000 0010 0101 0001 = SETCSP |
| 2005 | | |
| 2006 | | 0111 111s sssR dddd = SWAPF *Rs,Rd,0 |
| 2007 | | |
| 2008 | | 0000 1110 1111 1010 = TFILL XY |
| 2009 | | |
| 2010 | | 0000 1000 0000 1111 = TRAPL |
| 2011 | | |
| 2012 | | 0000 1000 0101 0111 = VBLT B,L |
| 2013 | | |
| 2014 | | 0000 1010 0101 0111 = VFILL L |
| 2015 | | |
| 2016 | | 0000 1010 0000 0000 = VLCOL |
| 2017 | | |
| 2018 | | ************************************/ |
| 2019 | | |
| 2020 | | |
| 2021 | | #define ADD_XYI(R) \ |
| 2022 | | { \ |
| 2023 | | UINT32 a = PARAM_LONG(); \ |
| 2024 | | XY *b = &R##REG_XY(DSTREG(op)); \ |
| 2025 | | CLR_NCZV(); \ |
| 2026 | | b->x += (INT16)(a & 0xffff); \ |
| 2027 | | b->y += ((INT32)a >> 16); \ |
| 2028 | | SET_N_LOG(b->x == 0); \ |
| 2029 | | SET_C_BIT_LO(b->y, 15); \ |
| 2030 | | SET_Z_LOG(b->y == 0); \ |
| 2031 | | SET_V_BIT_LO(b->x, 15); \ |
| 2032 | | COUNT_CYCLES(1); \ |
| 2033 | | } |
| 2034 | | void tms340x0_device::addxyi_a(UINT16 op) |
| 2035 | | { |
| 2036 | | if (!m_is_34020) { unimpl(op); return; } |
| 2037 | | ADD_XYI(A); |
| 2038 | | } |
| 2039 | | void tms340x0_device::addxyi_b(UINT16 op) |
| 2040 | | { |
| 2041 | | if (!m_is_34020) { unimpl(op); return; } |
| 2042 | | ADD_XYI(B); |
| 2043 | | } |
| 2044 | | |
| 2045 | | void tms340x0_device::blmove(UINT16 op) |
| 2046 | | { |
| 2047 | | offs_t src = BREG(0); |
| 2048 | | offs_t dst = BREG(2); |
| 2049 | | offs_t bits = BREG(7); |
| 2050 | | |
| 2051 | | if (!m_is_34020) { unimpl(op); return; } |
| 2052 | | |
| 2053 | | /* src and dst are aligned */ |
| 2054 | | if (!(src & 0x0f) && !(dst & 0x0f)) |
| 2055 | | { |
| 2056 | | while (bits >= 16 && m_icount > 0) |
| 2057 | | { |
| 2058 | | TMS34010_WRMEM_WORD(TOBYTE(dst), TMS34010_RDMEM_WORD(TOBYTE(src))); |
| 2059 | | src += 0x10; |
| 2060 | | dst += 0x10; |
| 2061 | | bits -= 0x10; |
| 2062 | | m_icount -= 2; |
| 2063 | | } |
| 2064 | | if (bits != 0 && m_icount > 0) |
| 2065 | | { |
| 2066 | | (this->*s_wfield_functions[bits])(dst, (this->*s_rfield_functions[bits])(src)); |
| 2067 | | dst += bits; |
| 2068 | | src += bits; |
| 2069 | | bits = 0; |
| 2070 | | m_icount -= 2; |
| 2071 | | } |
| 2072 | | } |
| 2073 | | |
| 2074 | | /* src is aligned, dst is not */ |
| 2075 | | else if (!(src & 0x0f)) |
| 2076 | | { |
| 2077 | | logerror("020:BLMOVE with aligned src and unaligned dst\n"); |
| 2078 | | } |
| 2079 | | |
| 2080 | | /* dst is aligned, src is not */ |
| 2081 | | else if (!(dst & 0x0f)) |
| 2082 | | { |
| 2083 | | logerror("020:BLMOVE with unaligned src and aligned dst\n"); |
| 2084 | | } |
| 2085 | | |
| 2086 | | /* neither are aligned */ |
| 2087 | | else |
| 2088 | | { |
| 2089 | | logerror("020:BLMOVE with completely unaligned src and dst\n"); |
| 2090 | | } |
| 2091 | | |
| 2092 | | /* update the final results */ |
| 2093 | | BREG(0) = src; |
| 2094 | | BREG(2) = dst; |
| 2095 | | BREG(7) = bits; |
| 2096 | | |
| 2097 | | /* if we're not done yet, back up the PC */ |
| 2098 | | if (bits != 0) |
| 2099 | | m_pc -= 0x10; |
| 2100 | | } |
| 2101 | | |
| 2102 | | void tms340x0_device::cexec_l(UINT16 op) |
| 2103 | | { |
| 2104 | | if (!m_is_34020) { unimpl(op); return; } |
| 2105 | | logerror("020:cexec_l\n"); |
| 2106 | | } |
| 2107 | | |
| 2108 | | void tms340x0_device::cexec_s(UINT16 op) |
| 2109 | | { |
| 2110 | | if (!m_is_34020) { unimpl(op); return; } |
| 2111 | | logerror("020:cexec_s\n"); |
| 2112 | | } |
| 2113 | | |
| 2114 | | void tms340x0_device::clip(UINT16 op) |
| 2115 | | { |
| 2116 | | if (!m_is_34020) { unimpl(op); return; } |
| 2117 | | logerror("020:clip\n"); |
| 2118 | | } |
| 2119 | | |
| 2120 | | void tms340x0_device::cmovcg_a(UINT16 op) |
| 2121 | | { |
| 2122 | | if (!m_is_34020) { unimpl(op); return; } |
| 2123 | | logerror("020:cmovcg_a\n"); |
| 2124 | | } |
| 2125 | | |
| 2126 | | void tms340x0_device::cmovcg_b(UINT16 op) |
| 2127 | | { |
| 2128 | | if (!m_is_34020) { unimpl(op); return; } |
| 2129 | | logerror("020:cmovcg_b\n"); |
| 2130 | | } |
| 2131 | | |
| 2132 | | void tms340x0_device::cmovcm_f(UINT16 op) |
| 2133 | | { |
| 2134 | | if (!m_is_34020) { unimpl(op); return; } |
| 2135 | | logerror("020:cmovcm_f\n"); |
| 2136 | | } |
| 2137 | | |
| 2138 | | void tms340x0_device::cmovcm_b(UINT16 op) |
| 2139 | | { |
| 2140 | | if (!m_is_34020) { unimpl(op); return; } |
| 2141 | | logerror("020:cmovcm_b\n"); |
| 2142 | | } |
| 2143 | | |
| 2144 | | void tms340x0_device::cmovgc_a(UINT16 op) |
| 2145 | | { |
| 2146 | | if (!m_is_34020) { unimpl(op); return; } |
| 2147 | | logerror("020:cmovgc_a\n"); |
| 2148 | | } |
| 2149 | | |
| 2150 | | void tms340x0_device::cmovgc_b(UINT16 op) |
| 2151 | | { |
| 2152 | | if (!m_is_34020) { unimpl(op); return; } |
| 2153 | | logerror("020:cmovgc_b\n"); |
| 2154 | | } |
| 2155 | | |
| 2156 | | void tms340x0_device::cmovgc_a_s(UINT16 op) |
| 2157 | | { |
| 2158 | | if (!m_is_34020) { unimpl(op); return; } |
| 2159 | | logerror("020:cmovgc_a_s\n"); |
| 2160 | | } |
| 2161 | | |
| 2162 | | void tms340x0_device::cmovgc_b_s(UINT16 op) |
| 2163 | | { |
| 2164 | | if (!m_is_34020) { unimpl(op); return; } |
| 2165 | | logerror("020:cmovgc_b_s\n"); |
| 2166 | | } |
| 2167 | | |
| 2168 | | void tms340x0_device::cmovmc_f(UINT16 op) |
| 2169 | | { |
| 2170 | | if (!m_is_34020) { unimpl(op); return; } |
| 2171 | | logerror("020:cmovmc_f\n"); |
| 2172 | | } |
| 2173 | | |
| 2174 | | void tms340x0_device::cmovmc_f_va(UINT16 op) |
| 2175 | | { |
| 2176 | | if (!m_is_34020) { unimpl(op); return; } |
| 2177 | | logerror("020:cmovmc_f_va\n"); |
| 2178 | | } |
| 2179 | | |
| 2180 | | void tms340x0_device::cmovmc_f_vb(UINT16 op) |
| 2181 | | { |
| 2182 | | if (!m_is_34020) { unimpl(op); return; } |
| 2183 | | logerror("020:cmovmc_f_vb\n"); |
| 2184 | | } |
| 2185 | | |
| 2186 | | void tms340x0_device::cmovmc_b(UINT16 op) |
| 2187 | | { |
| 2188 | | if (!m_is_34020) { unimpl(op); return; } |
| 2189 | | logerror("020:cmovmc_b\n"); |
| 2190 | | } |
| 2191 | | |
| 2192 | | #define CMPK(R) \ |
| 2193 | | { \ |
| 2194 | | INT32 r; \ |
| 2195 | | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 2196 | | INT32 t = PARAM_K(op); if (!t) t = 32; \ |
| 2197 | | CLR_NCZV(); \ |
| 2198 | | r = *rd - t; \ |
| 2199 | | SET_NZCV_SUB(*rd,t,r); \ |
| 2200 | | COUNT_CYCLES(1); \ |
| 2201 | | } |
| 2202 | | void tms340x0_device::cmp_k_a(UINT16 op) |
| 2203 | | { |
| 2204 | | if (!m_is_34020) { unimpl(op); return; } |
| 2205 | | CMPK(A); |
| 2206 | | } |
| 2207 | | void tms340x0_device::cmp_k_b(UINT16 op) |
| 2208 | | { |
| 2209 | | if (!m_is_34020) { unimpl(op); return; } |
| 2210 | | CMPK(B); |
| 2211 | | } |
| 2212 | | |
| 2213 | | void tms340x0_device::cvdxyl_a(UINT16 op) |
| 2214 | | { |
| 2215 | | if (!m_is_34020) { unimpl(op); return; } |
| 2216 | | logerror("020:cvdxyl_a\n"); |
| 2217 | | } |
| 2218 | | |
| 2219 | | void tms340x0_device::cvdxyl_b(UINT16 op) |
| 2220 | | { |
| 2221 | | if (!m_is_34020) { unimpl(op); return; } |
| 2222 | | logerror("020:cvdxyl_b\n"); |
| 2223 | | } |
| 2224 | | |
| 2225 | | void tms340x0_device::cvmxyl_a(UINT16 op) |
| 2226 | | { |
| 2227 | | if (!m_is_34020) { unimpl(op); return; } |
| 2228 | | logerror("020:cvmxyl_a\n"); |
| 2229 | | } |
| 2230 | | |
| 2231 | | void tms340x0_device::cvmxyl_b(UINT16 op) |
| 2232 | | { |
| 2233 | | if (!m_is_34020) { unimpl(op); return; } |
| 2234 | | logerror("020:cvmxyl_b\n"); |
| 2235 | | } |
| 2236 | | |
| 2237 | | void tms340x0_device::cvsxyl_a(UINT16 op) |
| 2238 | | { |
| 2239 | | if (!m_is_34020) { unimpl(op); return; } |
| 2240 | | logerror("020:cvsxyl_a\n"); |
| 2241 | | } |
| 2242 | | |
| 2243 | | void tms340x0_device::cvsxyl_b(UINT16 op) |
| 2244 | | { |
| 2245 | | if (!m_is_34020) { unimpl(op); return; } |
| 2246 | | logerror("020:cvsxyl_b\n"); |
| 2247 | | } |
| 2248 | | |
| 2249 | | void tms340x0_device::exgps_a(UINT16 op) |
| 2250 | | { |
| 2251 | | if (!m_is_34020) { unimpl(op); return; } |
| 2252 | | logerror("020:exgps_a\n"); |
| 2253 | | } |
| 2254 | | |
| 2255 | | void tms340x0_device::exgps_b(UINT16 op) |
| 2256 | | { |
| 2257 | | if (!m_is_34020) { unimpl(op); return; } |
| 2258 | | logerror("020:exgps_b\n"); |
| 2259 | | } |
| 2260 | | |
| 2261 | | void tms340x0_device::fline(UINT16 op) |
| 2262 | | { |
| 2263 | | if (!m_is_34020) { unimpl(op); return; } |
| 2264 | | logerror("020:fline\n"); |
| 2265 | | } |
| 2266 | | |
| 2267 | | void tms340x0_device::fpixeq(UINT16 op) |
| 2268 | | { |
| 2269 | | if (!m_is_34020) { unimpl(op); return; } |
| 2270 | | logerror("020:fpixeq\n"); |
| 2271 | | } |
| 2272 | | |
| 2273 | | void tms340x0_device::fpixne(UINT16 op) |
| 2274 | | { |
| 2275 | | if (!m_is_34020) { unimpl(op); return; } |
| 2276 | | logerror("020:fpixne\n"); |
| 2277 | | } |
| 2278 | | |
| 2279 | | void tms340x0_device::getps_a(UINT16 op) |
| 2280 | | { |
| 2281 | | if (!m_is_34020) { unimpl(op); return; } |
| 2282 | | logerror("020:getps_a\n"); |
| 2283 | | } |
| 2284 | | |
| 2285 | | void tms340x0_device::getps_b(UINT16 op) |
| 2286 | | { |
| 2287 | | if (!m_is_34020) { unimpl(op); return; } |
| 2288 | | logerror("020:getps_b\n"); |
| 2289 | | } |
| 2290 | | |
| 2291 | | void tms340x0_device::idle(UINT16 op) |
| 2292 | | { |
| 2293 | | if (!m_is_34020) { unimpl(op); return; } |
| 2294 | | logerror("020:idle\n"); |
| 2295 | | } |
| 2296 | | |
| 2297 | | void tms340x0_device::linit(UINT16 op) |
| 2298 | | { |
| 2299 | | if (!m_is_34020) { unimpl(op); return; } |
| 2300 | | logerror("020:linit\n"); |
| 2301 | | } |
| 2302 | | |
| 2303 | | void tms340x0_device::mwait(UINT16 op) |
| 2304 | | { |
| 2305 | | if (!m_is_34020) { unimpl(op); return; } |
| 2306 | | } |
| 2307 | | |
| 2308 | | void tms340x0_device::pfill_xy(UINT16 op) |
| 2309 | | { |
| 2310 | | if (!m_is_34020) { unimpl(op); return; } |
| 2311 | | logerror("020:pfill_xy\n"); |
| 2312 | | } |
| 2313 | | |
| 2314 | | void tms340x0_device::pixblt_l_m_l(UINT16 op) |
| 2315 | | { |
| 2316 | | if (!m_is_34020) { unimpl(op); return; } |
| 2317 | | logerror("020:pixblt_l_m_l\n"); |
| 2318 | | } |
| 2319 | | |
| 2320 | | void tms340x0_device::retm(UINT16 op) |
| 2321 | | { |
| 2322 | | if (!m_is_34020) { unimpl(op); return; } |
| 2323 | | logerror("020:retm\n"); |
| 2324 | | } |
| 2325 | | |
| 2326 | | #define RMO(R) \ |
| 2327 | | { \ |
| 2328 | | UINT32 res = 0; \ |
| 2329 | | UINT32 rs = R##REG(SRCREG(op)); \ |
| 2330 | | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 2331 | | CLR_Z(); \ |
| 2332 | | SET_Z_VAL(rs); \ |
| 2333 | | if (rs) \ |
| 2334 | | { \ |
| 2335 | | while (!(rs & 0x00000001)) \ |
| 2336 | | { \ |
| 2337 | | res++; \ |
| 2338 | | rs >>= 1; \ |
| 2339 | | } \ |
| 2340 | | } \ |
| 2341 | | *rd = res; \ |
| 2342 | | COUNT_CYCLES(1); \ |
| 2343 | | } |
| 2344 | | |
| 2345 | | void tms340x0_device::rmo_a(UINT16 op) { RMO(A); } |
| 2346 | | void tms340x0_device::rmo_b(UINT16 op) { RMO(B); } |
| 2347 | | |
| 2348 | | #define RPIX(R) \ |
| 2349 | | { \ |
| 2350 | | UINT32 v = R##REG(DSTREG(op)); \ |
| 2351 | | switch (m_pixelshift) \ |
| 2352 | | { \ |
| 2353 | | case 0: \ |
| 2354 | | v = (v & 1) ? 0xffffffff : 0x00000000;\ |
| 2355 | | COUNT_CYCLES(8); \ |
| 2356 | | break; \ |
| 2357 | | case 1: \ |
| 2358 | | v &= 3; \ |
| 2359 | | v |= v << 2; \ |
| 2360 | | v |= v << 4; \ |
| 2361 | | v |= v << 8; \ |
| 2362 | | v |= v << 16; \ |
| 2363 | | COUNT_CYCLES(7); \ |
| 2364 | | break; \ |
| 2365 | | case 2: \ |
| 2366 | | v &= 0x0f; \ |
| 2367 | | v |= v << 4; \ |
| 2368 | | v |= v << 8; \ |
| 2369 | | v |= v << 16; \ |
| 2370 | | COUNT_CYCLES(6); \ |
| 2371 | | break; \ |
| 2372 | | case 3: \ |
| 2373 | | v &= 0xff; \ |
| 2374 | | v |= v << 8; \ |
| 2375 | | v |= v << 16; \ |
| 2376 | | COUNT_CYCLES(5); \ |
| 2377 | | break; \ |
| 2378 | | case 4: \ |
| 2379 | | v &= 0xffff; \ |
| 2380 | | v |= v << 16; \ |
| 2381 | | COUNT_CYCLES(4); \ |
| 2382 | | break; \ |
| 2383 | | case 5: \ |
| 2384 | | COUNT_CYCLES(2); \ |
| 2385 | | break; \ |
| 2386 | | } \ |
| 2387 | | R##REG(DSTREG(op)) = v; \ |
| 2388 | | } |
| 2389 | | |
| 2390 | | void tms340x0_device::rpix_a(UINT16 op) |
| 2391 | | { |
| 2392 | | if (!m_is_34020) { unimpl(op); return; } |
| 2393 | | RPIX(A); |
| 2394 | | } |
| 2395 | | |
| 2396 | | void tms340x0_device::rpix_b(UINT16 op) |
| 2397 | | { |
| 2398 | | if (!m_is_34020) { unimpl(op); return; } |
| 2399 | | RPIX(B); |
| 2400 | | } |
| 2401 | | |
| 2402 | | void tms340x0_device::setcdp(UINT16 op) |
| 2403 | | { |
| 2404 | | if (!m_is_34020) { unimpl(op); return; } |
| 2405 | | logerror("020:setcdp\n"); |
| 2406 | | } |
| 2407 | | |
| 2408 | | void tms340x0_device::setcmp(UINT16 op) |
| 2409 | | { |
| 2410 | | if (!m_is_34020) { unimpl(op); return; } |
| 2411 | | logerror("020:setcmp\n"); |
| 2412 | | } |
| 2413 | | |
| 2414 | | void tms340x0_device::setcsp(UINT16 op) |
| 2415 | | { |
| 2416 | | if (!m_is_34020) { unimpl(op); return; } |
| 2417 | | logerror("020:setcsp\n"); |
| 2418 | | } |
| 2419 | | |
| 2420 | | void tms340x0_device::swapf_a(UINT16 op) |
| 2421 | | { |
| 2422 | | if (!m_is_34020) { unimpl(op); return; } |
| 2423 | | logerror("020:swapf_a\n"); |
| 2424 | | } |
| 2425 | | |
| 2426 | | void tms340x0_device::swapf_b(UINT16 op) |
| 2427 | | { |
| 2428 | | if (!m_is_34020) { unimpl(op); return; } |
| 2429 | | logerror("020:swapf_b\n"); |
| 2430 | | } |
| 2431 | | |
| 2432 | | void tms340x0_device::tfill_xy(UINT16 op) |
| 2433 | | { |
| 2434 | | if (!m_is_34020) { unimpl(op); return; } |
| 2435 | | logerror("020:tfill_xy\n"); |
| 2436 | | } |
| 2437 | | |
| 2438 | | void tms340x0_device::trapl(UINT16 op) |
| 2439 | | { |
| 2440 | | if (!m_is_34020) { unimpl(op); return; } |
| 2441 | | logerror("020:trapl\n"); |
| 2442 | | } |
| 2443 | | |
| 2444 | | void tms340x0_device::vblt_b_l(UINT16 op) |
| 2445 | | { |
| 2446 | | if (!m_is_34020) { unimpl(op); return; } |
| 2447 | | logerror("020:vblt_b_l\n"); |
| 2448 | | } |
| 2449 | | |
| 2450 | | void tms340x0_device::vfill_l(UINT16 op) |
| 2451 | | { |
| 2452 | | if (!m_is_34020) { unimpl(op); return; } |
| 2453 | | logerror("020:vfill_l\n"); |
| 2454 | | } |
| 2455 | | |
| 2456 | | void tms340x0_device::vlcol(UINT16 op) |
| 2457 | | { |
| 2458 | | if (!m_is_34020) { unimpl(op); return; } |
| 2459 | | logerror("020:vlcol\n"); |
| 2460 | | } |
trunk/src/devices/cpu/tms34010/34010ops.inc
| r0 | r250222 | |
|---|
| 1 | // license:BSD-3-Clause |
| 2 | // copyright-holders:Alex Pasadyn,Zsolt Vasvari |
| 3 | /*************************************************************************** |
| 4 | |
| 5 | TMS34010: Portable Texas Instruments TMS34010 emulator |
| 6 | |
| 7 | Copyright Alex Pasadyn/Zsolt Vasvari |
| 8 | Parts based on code by Aaron Giles |
| 9 | |
| 10 | ***************************************************************************/ |
| 11 | |
| 12 | |
| 13 | |
| 14 | /*************************************************************************** |
| 15 | MISC MACROS |
| 16 | ***************************************************************************/ |
| 17 | |
| 18 | #define ZEXTEND(val,width) if (width) (val) &= ((UINT32)0xffffffff >> (32 - (width))) |
| 19 | #define SEXTEND(val,width) if (width) (val) = (INT32)((val) << (32 - (width))) >> (32 - (width)) |
| 20 | |
| 21 | #define SXYTOL(val) ((((INT16)(val).y * m_convsp) + ((INT16)(val).x << m_pixelshift)) + OFFSET()) |
| 22 | #define DXYTOL(val) ((((INT16)(val).y * m_convdp) + ((INT16)(val).x << m_pixelshift)) + OFFSET()) |
| 23 | #define MXYTOL(val) ((((INT16)(val).y * m_convmp) + ((INT16)(val).x << m_pixelshift)) + OFFSET()) |
| 24 | |
| 25 | #define COUNT_CYCLES(x) m_icount -= x |
| 26 | #define COUNT_UNKNOWN_CYCLES(x) COUNT_CYCLES(x) |
| 27 | |
| 28 | #define CORRECT_ODD_PC(x) do { if (m_pc & 0x0f) logerror("%s to PC=%08X\n", x, m_pc); m_pc &= ~0x0f; } while (0) |
| 29 | |
| 30 | |
| 31 | |
| 32 | /*************************************************************************** |
| 33 | FLAG HANDLING MACROS |
| 34 | ***************************************************************************/ |
| 35 | |
| 36 | #define SIGN(val) ((val) & 0x80000000) |
| 37 | |
| 38 | #define CLR_Z() m_st &= ~STBIT_Z |
| 39 | #define CLR_V() m_st &= ~STBIT_V |
| 40 | #define CLR_C() m_st &= ~STBIT_C |
| 41 | #define CLR_N() m_st &= ~STBIT_N |
| 42 | #define CLR_NZ() m_st &= ~(STBIT_N | STBIT_Z) |
| 43 | #define CLR_CZ() m_st &= ~(STBIT_C | STBIT_Z) |
| 44 | #define CLR_ZV() m_st &= ~(STBIT_Z | STBIT_V) |
| 45 | #define CLR_NZV() m_st &= ~(STBIT_N | STBIT_Z | STBIT_V) |
| 46 | #define CLR_NCZ() m_st &= ~(STBIT_N | STBIT_C | STBIT_Z) |
| 47 | #define CLR_NCZV() m_st &= ~(STBIT_N | STBIT_C | STBIT_Z | STBIT_V) |
| 48 | |
| 49 | #define SET_V_BIT_LO(val,bit) m_st |= ((val) << (28 - (bit))) & STBIT_V |
| 50 | #define SET_V_BIT_HI(val,bit) m_st |= ((val) >> ((bit) - 28)) & STBIT_V |
| 51 | #define SET_V_LOG(val) m_st |= (val) << 28 |
| 52 | #define SET_Z_BIT_LO(val,bit) m_st |= ((val) << (29 - (bit))) & STBIT_Z |
| 53 | #define SET_Z_BIT_HI(val,bit) m_st |= ((val) >> ((bit) - 29)) & STBIT_Z |
| 54 | #define SET_Z_LOG(val) m_st |= (val) << 29 |
| 55 | #define SET_C_BIT_LO(val,bit) m_st |= ((val) << (30 - (bit))) & STBIT_C |
| 56 | #define SET_C_BIT_HI(val,bit) m_st |= ((val) >> ((bit) - 30)) & STBIT_C |
| 57 | #define SET_C_LOG(val) m_st |= (val) << 30 |
| 58 | #define SET_N_BIT(val,bit) m_st |= ((val) << (31 - (bit))) & STBIT_N |
| 59 | #define SET_N_LOG(val) m_st |= (val) << 31 |
| 60 | |
| 61 | #define SET_Z_VAL(val) SET_Z_LOG((val) == 0) |
| 62 | #define SET_N_VAL(val) SET_N_BIT(val, 31) |
| 63 | #define SET_NZ_VAL(val) SET_Z_VAL(val); SET_N_VAL(val) |
| 64 | #define SET_V_SUB(a,b,r) SET_V_BIT_HI(((a) ^ (b)) & ((a) ^ (r)), 31) |
| 65 | #define SET_V_ADD(a,b,r) SET_V_BIT_HI(~((a) ^ (b)) & ((a) ^ (r)), 31) |
| 66 | #define SET_C_SUB(a,b) SET_C_LOG((UINT32)(b) > (UINT32)(a)) |
| 67 | #define SET_C_ADD(a,b) SET_C_LOG((UINT32)~(a) < (UINT32)(b)) |
| 68 | #define SET_NZV_SUB(a,b,r) SET_NZ_VAL(r); SET_V_SUB(a,b,r) |
| 69 | #define SET_NZCV_SUB(a,b,r) SET_NZV_SUB(a,b,r); SET_C_SUB(a,b) |
| 70 | #define SET_NZCV_ADD(a,b,r) SET_NZ_VAL(r); SET_V_ADD(a,b,r); SET_C_ADD(a,b) |
| 71 | |
| 72 | static const UINT8 fw_inc[32] = { 32,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 }; |
| 73 | |
| 74 | |
| 75 | /*************************************************************************** |
| 76 | UNIMPLEMENTED INSTRUCTION |
| 77 | ***************************************************************************/ |
| 78 | |
| 79 | void tms340x0_device::unimpl(UINT16 op) |
| 80 | { |
| 81 | /* kludge for Super High Impact -- this doesn't seem to cause */ |
| 82 | /* an illegal opcode exception */ |
| 83 | if (m_direct->read_word(TOBYTE(m_pc - 0x10)) == 0x0007) |
| 84 | return; |
| 85 | |
| 86 | /* 9 Ball Shootout calls to FFDF7468, expecting it */ |
| 87 | /* to execute the next instruction from FFDF7470 */ |
| 88 | /* but the instruction at FFDF7460 is an 0x0001 */ |
| 89 | if (m_direct->read_word(TOBYTE(m_pc - 0x10)) == 0x0001) |
| 90 | return; |
| 91 | |
| 92 | PUSH(m_pc); |
| 93 | PUSH(m_st); |
| 94 | RESET_ST(); |
| 95 | m_pc = RLONG(0xfffffc20); |
| 96 | COUNT_UNKNOWN_CYCLES(16); |
| 97 | |
| 98 | /* extra check to prevent bad things */ |
| 99 | if (m_pc == 0 || s_opcode_table[m_direct->read_word(TOBYTE(m_pc)) >> 4] == &tms34010_device::unimpl) |
| 100 | { |
| 101 | set_input_line(INPUT_LINE_HALT, ASSERT_LINE); |
| 102 | debugger_break(machine()); |
| 103 | } |
| 104 | } |
| 105 | |
| 106 | |
| 107 | |
| 108 | /*************************************************************************** |
| 109 | X/Y OPERATIONS |
| 110 | ***************************************************************************/ |
| 111 | |
| 112 | #define ADD_XY(R) \ |
| 113 | { \ |
| 114 | XY a = R##REG_XY(SRCREG(op)); \ |
| 115 | XY *b = &R##REG_XY(DSTREG(op)); \ |
| 116 | CLR_NCZV(); \ |
| 117 | b->x += a.x; \ |
| 118 | b->y += a.y; \ |
| 119 | SET_N_LOG(b->x == 0); \ |
| 120 | SET_C_BIT_LO(b->y, 15); \ |
| 121 | SET_Z_LOG(b->y == 0); \ |
| 122 | SET_V_BIT_LO(b->x, 15); \ |
| 123 | COUNT_CYCLES(1); \ |
| 124 | } |
| 125 | void tms340x0_device::add_xy_a(UINT16 op) { ADD_XY(A); } |
| 126 | void tms340x0_device::add_xy_b(UINT16 op) { ADD_XY(B); } |
| 127 | |
| 128 | #define SUB_XY(R) \ |
| 129 | { \ |
| 130 | XY a = R##REG_XY(SRCREG(op)); \ |
| 131 | XY *b = &R##REG_XY(DSTREG(op)); \ |
| 132 | CLR_NCZV(); \ |
| 133 | SET_N_LOG(a.x == b->x); \ |
| 134 | SET_C_LOG(a.y > b->y); \ |
| 135 | SET_Z_LOG(a.y == b->y); \ |
| 136 | SET_V_LOG(a.x > b->x); \ |
| 137 | b->x -= a.x; \ |
| 138 | b->y -= a.y; \ |
| 139 | COUNT_CYCLES(1); \ |
| 140 | } |
| 141 | void tms340x0_device::sub_xy_a(UINT16 op) { SUB_XY(A); } |
| 142 | void tms340x0_device::sub_xy_b(UINT16 op) { SUB_XY(B); } |
| 143 | |
| 144 | #define CMP_XY(R) \ |
| 145 | { \ |
| 146 | INT16 res; \ |
| 147 | XY a = R##REG_XY(DSTREG(op)); \ |
| 148 | XY b = R##REG_XY(SRCREG(op)); \ |
| 149 | CLR_NCZV(); \ |
| 150 | res = a.x-b.x; \ |
| 151 | SET_N_LOG(res == 0); \ |
| 152 | SET_V_BIT_LO(res, 15); \ |
| 153 | res = a.y-b.y; \ |
| 154 | SET_Z_LOG(res == 0); \ |
| 155 | SET_C_BIT_LO(res, 15); \ |
| 156 | COUNT_CYCLES(1); \ |
| 157 | } |
| 158 | void tms340x0_device::cmp_xy_a(UINT16 op) { CMP_XY(A); } |
| 159 | void tms340x0_device::cmp_xy_b(UINT16 op) { CMP_XY(B); } |
| 160 | |
| 161 | #define CPW(R) \ |
| 162 | { \ |
| 163 | INT32 res = 0; \ |
| 164 | INT16 x = R##REG_X(SRCREG(op)); \ |
| 165 | INT16 y = R##REG_Y(SRCREG(op)); \ |
| 166 | \ |
| 167 | CLR_V(); \ |
| 168 | res |= ((WSTART_X() > x) ? 0x20 : 0); \ |
| 169 | res |= ((x > WEND_X()) ? 0x40 : 0); \ |
| 170 | res |= ((WSTART_Y() > y) ? 0x80 : 0); \ |
| 171 | res |= ((y > WEND_Y()) ? 0x100 : 0); \ |
| 172 | R##REG(DSTREG(op)) = res; \ |
| 173 | SET_V_LOG(res != 0); \ |
| 174 | COUNT_CYCLES(1); \ |
| 175 | } |
| 176 | void tms340x0_device::cpw_a(UINT16 op) { CPW(A); } |
| 177 | void tms340x0_device::cpw_b(UINT16 op) { CPW(B); } |
| 178 | |
| 179 | #define CVXYL(R) \ |
| 180 | { \ |
| 181 | R##REG(DSTREG(op)) = DXYTOL(R##REG_XY(SRCREG(op))); \ |
| 182 | COUNT_CYCLES(3); \ |
| 183 | } |
| 184 | void tms340x0_device::cvxyl_a(UINT16 op) { CVXYL(A); } |
| 185 | void tms340x0_device::cvxyl_b(UINT16 op) { CVXYL(B); } |
| 186 | |
| 187 | #define MOVX(R) \ |
| 188 | { \ |
| 189 | R##REG(DSTREG(op)) = (R##REG(DSTREG(op)) & 0xffff0000) | (UINT16)R##REG(SRCREG(op)); \ |
| 190 | COUNT_CYCLES(1); \ |
| 191 | } |
| 192 | void tms340x0_device::movx_a(UINT16 op) { MOVX(A); } |
| 193 | void tms340x0_device::movx_b(UINT16 op) { MOVX(B); } |
| 194 | |
| 195 | #define MOVY(R) \ |
| 196 | { \ |
| 197 | R##REG(DSTREG(op)) = (R##REG(SRCREG(op)) & 0xffff0000) | (UINT16)R##REG(DSTREG(op)); \ |
| 198 | COUNT_CYCLES(1); \ |
| 199 | } |
| 200 | void tms340x0_device::movy_a(UINT16 op) { MOVY(A); } |
| 201 | void tms340x0_device::movy_b(UINT16 op) { MOVY(B); } |
| 202 | |
| 203 | |
| 204 | |
| 205 | /*************************************************************************** |
| 206 | PIXEL TRANSFER OPERATIONS |
| 207 | ***************************************************************************/ |
| 208 | |
| 209 | #define PIXT_RI(R) \ |
| 210 | { \ |
| 211 | WPIXEL(R##REG(DSTREG(op)),R##REG(SRCREG(op))); \ |
| 212 | COUNT_UNKNOWN_CYCLES(2); \ |
| 213 | } |
| 214 | void tms340x0_device::pixt_ri_a(UINT16 op) { PIXT_RI(A); } |
| 215 | void tms340x0_device::pixt_ri_b(UINT16 op) { PIXT_RI(B); } |
| 216 | |
| 217 | #define PIXT_RIXY(R) \ |
| 218 | { \ |
| 219 | if (WINDOW_CHECKING() != 0) \ |
| 220 | { \ |
| 221 | CLR_V(); \ |
| 222 | if (R##REG_X(DSTREG(op)) < WSTART_X() || R##REG_X(DSTREG(op)) > WEND_X() || \ |
| 223 | R##REG_Y(DSTREG(op)) < WSTART_Y() || R##REG_Y(DSTREG(op)) > WEND_Y()) \ |
| 224 | { \ |
| 225 | SET_V_LOG(1); \ |
| 226 | goto skip; \ |
| 227 | } \ |
| 228 | if (WINDOW_CHECKING() == 1) goto skip; \ |
| 229 | } \ |
| 230 | WPIXEL(DXYTOL(R##REG_XY(DSTREG(op))),R##REG(SRCREG(op))); \ |
| 231 | skip: \ |
| 232 | COUNT_UNKNOWN_CYCLES(4); \ |
| 233 | } |
| 234 | void tms340x0_device::pixt_rixy_a(UINT16 op) { PIXT_RIXY(A); } |
| 235 | void tms340x0_device::pixt_rixy_b(UINT16 op) { PIXT_RIXY(B); } |
| 236 | |
| 237 | #define PIXT_IR(R) \ |
| 238 | { \ |
| 239 | INT32 temp = RPIXEL(R##REG(SRCREG(op))); \ |
| 240 | CLR_V(); \ |
| 241 | R##REG(DSTREG(op)) = temp; \ |
| 242 | SET_V_LOG(temp != 0); \ |
| 243 | COUNT_CYCLES(4); \ |
| 244 | } |
| 245 | void tms340x0_device::pixt_ir_a(UINT16 op) { PIXT_IR(A); } |
| 246 | void tms340x0_device::pixt_ir_b(UINT16 op) { PIXT_IR(B); } |
| 247 | |
| 248 | #define PIXT_II(R) \ |
| 249 | { \ |
| 250 | WPIXEL(R##REG(DSTREG(op)),RPIXEL(R##REG(SRCREG(op)))); \ |
| 251 | COUNT_UNKNOWN_CYCLES(4); \ |
| 252 | } |
| 253 | void tms340x0_device::pixt_ii_a(UINT16 op) { PIXT_II(A); } |
| 254 | void tms340x0_device::pixt_ii_b(UINT16 op) { PIXT_II(B); } |
| 255 | |
| 256 | #define PIXT_IXYR(R) \ |
| 257 | { \ |
| 258 | INT32 temp = RPIXEL(SXYTOL(R##REG_XY(SRCREG(op)))); \ |
| 259 | CLR_V(); \ |
| 260 | R##REG(DSTREG(op)) = temp; \ |
| 261 | SET_V_LOG(temp != 0); \ |
| 262 | COUNT_CYCLES(6); \ |
| 263 | } |
| 264 | void tms340x0_device::pixt_ixyr_a(UINT16 op) { PIXT_IXYR(A); } |
| 265 | void tms340x0_device::pixt_ixyr_b(UINT16 op) { PIXT_IXYR(B); } |
| 266 | |
| 267 | #define PIXT_IXYIXY(R) \ |
| 268 | { \ |
| 269 | if (WINDOW_CHECKING() != 0) \ |
| 270 | { \ |
| 271 | CLR_V(); \ |
| 272 | if (R##REG_X(DSTREG(op)) < WSTART_X() || R##REG_X(DSTREG(op)) > WEND_X() || \ |
| 273 | R##REG_Y(DSTREG(op)) < WSTART_Y() || R##REG_Y(DSTREG(op)) > WEND_Y()) \ |
| 274 | { \ |
| 275 | SET_V_LOG(1); \ |
| 276 | goto skip; \ |
| 277 | } \ |
| 278 | if (WINDOW_CHECKING() == 1) goto skip; \ |
| 279 | } \ |
| 280 | WPIXEL(DXYTOL(R##REG_XY(DSTREG(op))),RPIXEL(SXYTOL(R##REG_XY(SRCREG(op))))); \ |
| 281 | skip: \ |
| 282 | COUNT_UNKNOWN_CYCLES(7); \ |
| 283 | } |
| 284 | void tms340x0_device::pixt_ixyixy_a(UINT16 op) { PIXT_IXYIXY(A); } |
| 285 | void tms340x0_device::pixt_ixyixy_b(UINT16 op) { PIXT_IXYIXY(B); } |
| 286 | |
| 287 | #define DRAV(R) \ |
| 288 | { \ |
| 289 | if (WINDOW_CHECKING() != 0) \ |
| 290 | { \ |
| 291 | CLR_V(); \ |
| 292 | if (R##REG_X(DSTREG(op)) < WSTART_X() || R##REG_X(DSTREG(op)) > WEND_X() || \ |
| 293 | R##REG_Y(DSTREG(op)) < WSTART_Y() || R##REG_Y(DSTREG(op)) > WEND_Y()) \ |
| 294 | { \ |
| 295 | SET_V_LOG(1); \ |
| 296 | goto skip; \ |
| 297 | } \ |
| 298 | if (WINDOW_CHECKING() == 1) goto skip; \ |
| 299 | } \ |
| 300 | WPIXEL(DXYTOL(R##REG_XY(DSTREG(op))),COLOR1()); \ |
| 301 | skip: \ |
| 302 | R##REG_X(DSTREG(op)) += R##REG_X(SRCREG(op)); \ |
| 303 | R##REG_Y(DSTREG(op)) += R##REG_Y(SRCREG(op)); \ |
| 304 | COUNT_UNKNOWN_CYCLES(4); \ |
| 305 | } |
| 306 | void tms340x0_device::drav_a(UINT16 op) { DRAV(A); } |
| 307 | void tms340x0_device::drav_b(UINT16 op) { DRAV(B); } |
| 308 | |
| 309 | |
| 310 | |
| 311 | /*************************************************************************** |
| 312 | ARITHMETIC OPERATIONS |
| 313 | ***************************************************************************/ |
| 314 | |
| 315 | #define ABS(R) \ |
| 316 | { \ |
| 317 | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 318 | INT32 r = 0 - *rd; \ |
| 319 | CLR_NZV(); \ |
| 320 | if (r > 0) *rd = r; \ |
| 321 | SET_NZ_VAL(r); \ |
| 322 | SET_V_LOG(r == (INT32)0x80000000); \ |
| 323 | COUNT_CYCLES(1); \ |
| 324 | } |
| 325 | void tms340x0_device::abs_a(UINT16 op) { ABS(A); } |
| 326 | void tms340x0_device::abs_b(UINT16 op) { ABS(B); } |
| 327 | |
| 328 | #define ADD(R) \ |
| 329 | { \ |
| 330 | INT32 a = R##REG(SRCREG(op)); \ |
| 331 | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 332 | INT32 b = *rd; \ |
| 333 | INT32 r = a + b; \ |
| 334 | CLR_NCZV(); \ |
| 335 | *rd = r; \ |
| 336 | SET_NZCV_ADD(a,b,r); \ |
| 337 | COUNT_CYCLES(1); \ |
| 338 | } |
| 339 | void tms340x0_device::add_a(UINT16 op) { ADD(A); } |
| 340 | void tms340x0_device::add_b(UINT16 op) { ADD(B); } |
| 341 | |
| 342 | #define ADDC(R) \ |
| 343 | { \ |
| 344 | /* I'm not sure to which side the carry is added to, should */ \ |
| 345 | /* verify it against the examples */ \ |
| 346 | INT32 a = R##REG(SRCREG(op)); \ |
| 347 | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 348 | INT32 b = *rd; \ |
| 349 | INT32 r = a + b + (C_FLAG() ? 1 : 0); \ |
| 350 | CLR_NCZV(); \ |
| 351 | *rd = r; \ |
| 352 | SET_NZCV_ADD(a,b,r); \ |
| 353 | COUNT_CYCLES(1); \ |
| 354 | } |
| 355 | void tms340x0_device::addc_a(UINT16 op) { ADDC(A); } |
| 356 | void tms340x0_device::addc_b(UINT16 op) { ADDC(B); } |
| 357 | |
| 358 | #define ADDI_W(R) \ |
| 359 | { \ |
| 360 | INT32 a = PARAM_WORD(); \ |
| 361 | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 362 | INT32 b = *rd; \ |
| 363 | INT32 r = a + b; \ |
| 364 | CLR_NCZV(); \ |
| 365 | *rd = r; \ |
| 366 | SET_NZCV_ADD(a,b,r); \ |
| 367 | COUNT_CYCLES(2); \ |
| 368 | } |
| 369 | void tms340x0_device::addi_w_a(UINT16 op) { ADDI_W(A); } |
| 370 | void tms340x0_device::addi_w_b(UINT16 op) { ADDI_W(B); } |
| 371 | |
| 372 | #define ADDI_L(R) \ |
| 373 | { \ |
| 374 | INT32 a = PARAM_LONG(); \ |
| 375 | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 376 | INT32 b = *rd; \ |
| 377 | INT32 r = a + b; \ |
| 378 | CLR_NCZV(); \ |
| 379 | *rd = r; \ |
| 380 | SET_NZCV_ADD(a,b,r); \ |
| 381 | COUNT_CYCLES(3); \ |
| 382 | } |
| 383 | void tms340x0_device::addi_l_a(UINT16 op) { ADDI_L(A); } |
| 384 | void tms340x0_device::addi_l_b(UINT16 op) { ADDI_L(B); } |
| 385 | |
| 386 | #define ADDK(R) \ |
| 387 | { \ |
| 388 | INT32 a = fw_inc[PARAM_K(op)]; \ |
| 389 | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 390 | INT32 b = *rd; \ |
| 391 | INT32 r = a + b; \ |
| 392 | CLR_NCZV(); \ |
| 393 | *rd = r; \ |
| 394 | SET_NZCV_ADD(a,b,r); \ |
| 395 | COUNT_CYCLES(1); \ |
| 396 | } |
| 397 | void tms340x0_device::addk_a(UINT16 op) { ADDK(A); } |
| 398 | void tms340x0_device::addk_b(UINT16 op) { ADDK(B); } |
| 399 | |
| 400 | #define AND(R) \ |
| 401 | { \ |
| 402 | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 403 | CLR_Z(); \ |
| 404 | *rd &= R##REG(SRCREG(op)); \ |
| 405 | SET_Z_VAL(*rd); \ |
| 406 | COUNT_CYCLES(1); \ |
| 407 | } |
| 408 | void tms340x0_device::and_a(UINT16 op) { AND(A); } |
| 409 | void tms340x0_device::and_b(UINT16 op) { AND(B); } |
| 410 | |
| 411 | #define ANDI(R) \ |
| 412 | { \ |
| 413 | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 414 | CLR_Z(); \ |
| 415 | *rd &= ~PARAM_LONG(); \ |
| 416 | SET_Z_VAL(*rd); \ |
| 417 | COUNT_CYCLES(3); \ |
| 418 | } |
| 419 | void tms340x0_device::andi_a(UINT16 op) { ANDI(A); } |
| 420 | void tms340x0_device::andi_b(UINT16 op) { ANDI(B); } |
| 421 | |
| 422 | #define ANDN(R) \ |
| 423 | { \ |
| 424 | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 425 | CLR_Z(); \ |
| 426 | *rd &= ~R##REG(SRCREG(op)); \ |
| 427 | SET_Z_VAL(*rd); \ |
| 428 | COUNT_CYCLES(1); \ |
| 429 | } |
| 430 | void tms340x0_device::andn_a(UINT16 op) { ANDN(A); } |
| 431 | void tms340x0_device::andn_b(UINT16 op) { ANDN(B); } |
| 432 | |
| 433 | #define BTST_K(R) \ |
| 434 | { \ |
| 435 | int bit = 31 - PARAM_K(op); \ |
| 436 | CLR_Z(); \ |
| 437 | if (bit <= 29) \ |
| 438 | SET_Z_BIT_LO(~R##REG(DSTREG(op)), bit); \ |
| 439 | else \ |
| 440 | SET_Z_BIT_HI(~R##REG(DSTREG(op)), bit); \ |
| 441 | COUNT_CYCLES(1); \ |
| 442 | } |
| 443 | void tms340x0_device::btst_k_a(UINT16 op) { BTST_K(A); } |
| 444 | void tms340x0_device::btst_k_b(UINT16 op) { BTST_K(B); } |
| 445 | |
| 446 | #define BTST_R(R) \ |
| 447 | { \ |
| 448 | int bit = R##REG(SRCREG(op)) & 0x1f; \ |
| 449 | CLR_Z(); \ |
| 450 | if (bit <= 29) \ |
| 451 | SET_Z_BIT_LO(~R##REG(DSTREG(op)), bit); \ |
| 452 | else \ |
| 453 | SET_Z_BIT_HI(~R##REG(DSTREG(op)), bit); \ |
| 454 | COUNT_CYCLES(2); \ |
| 455 | } |
| 456 | void tms340x0_device::btst_r_a(UINT16 op) { BTST_R(A); } |
| 457 | void tms340x0_device::btst_r_b(UINT16 op) { BTST_R(B); } |
| 458 | |
| 459 | void tms340x0_device::clrc(UINT16 op) |
| 460 | { |
| 461 | CLR_C(); |
| 462 | COUNT_CYCLES(1); |
| 463 | } |
| 464 | |
| 465 | #define CMP(R) \ |
| 466 | { \ |
| 467 | INT32 *rs = &R##REG(SRCREG(op)); \ |
| 468 | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 469 | INT32 r = *rd - *rs; \ |
| 470 | CLR_NCZV(); \ |
| 471 | SET_NZCV_SUB(*rd,*rs,r); \ |
| 472 | COUNT_CYCLES(1); \ |
| 473 | } |
| 474 | void tms340x0_device::cmp_a(UINT16 op) { CMP(A); } |
| 475 | void tms340x0_device::cmp_b(UINT16 op) { CMP(B); } |
| 476 | |
| 477 | #define CMPI_W(R) \ |
| 478 | { \ |
| 479 | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 480 | INT32 t = (INT16)~PARAM_WORD(); \ |
| 481 | INT32 r = *rd - t; \ |
| 482 | CLR_NCZV(); \ |
| 483 | SET_NZCV_SUB(*rd,t,r); \ |
| 484 | COUNT_CYCLES(2); \ |
| 485 | } |
| 486 | void tms340x0_device::cmpi_w_a(UINT16 op) { CMPI_W(A); } |
| 487 | void tms340x0_device::cmpi_w_b(UINT16 op) { CMPI_W(B); } |
| 488 | |
| 489 | #define CMPI_L(R) \ |
| 490 | { \ |
| 491 | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 492 | INT32 t = ~PARAM_LONG(); \ |
| 493 | INT32 r = *rd - t; \ |
| 494 | CLR_NCZV(); \ |
| 495 | SET_NZCV_SUB(*rd,t,r); \ |
| 496 | COUNT_CYCLES(3); \ |
| 497 | } |
| 498 | void tms340x0_device::cmpi_l_a(UINT16 op) { CMPI_L(A); } |
| 499 | void tms340x0_device::cmpi_l_b(UINT16 op) { CMPI_L(B); } |
| 500 | |
| 501 | void tms340x0_device::dint(UINT16 op) |
| 502 | { |
| 503 | m_st &= ~STBIT_IE; |
| 504 | COUNT_CYCLES(3); |
| 505 | } |
| 506 | |
| 507 | #define DIVS(R) \ |
| 508 | { \ |
| 509 | INT32 *rs = &R##REG(SRCREG(op)); \ |
| 510 | INT32 *rd1 = &R##REG(DSTREG(op)); \ |
| 511 | CLR_NZV(); \ |
| 512 | if (!(DSTREG(op) & 1)) \ |
| 513 | { \ |
| 514 | if (!*rs) \ |
| 515 | { \ |
| 516 | SET_V_LOG(1); \ |
| 517 | } \ |
| 518 | else \ |
| 519 | { \ |
| 520 | INT32 *rd2 = &R##REG(DSTREG(op)+1); \ |
| 521 | INT64 dividend = ((UINT64)*rd1 << 32) | (UINT32)*rd2; \ |
| 522 | INT64 quotient = dividend / *rs; \ |
| 523 | INT32 remainder = dividend % *rs; \ |
| 524 | UINT32 signbits = (INT32)quotient >> 31; \ |
| 525 | if (EXTRACT_64HI(quotient) != signbits) \ |
| 526 | { \ |
| 527 | SET_V_LOG(1); \ |
| 528 | } \ |
| 529 | else \ |
| 530 | { \ |
| 531 | *rd1 = quotient; \ |
| 532 | *rd2 = remainder; \ |
| 533 | SET_NZ_VAL(*rd1); \ |
| 534 | } \ |
| 535 | } \ |
| 536 | COUNT_CYCLES(40); \ |
| 537 | } \ |
| 538 | else \ |
| 539 | { \ |
| 540 | if (!*rs) \ |
| 541 | { \ |
| 542 | SET_V_LOG(1); \ |
| 543 | } \ |
| 544 | else \ |
| 545 | { \ |
| 546 | *rd1 /= *rs; \ |
| 547 | SET_NZ_VAL(*rd1); \ |
| 548 | } \ |
| 549 | COUNT_CYCLES(39); \ |
| 550 | } \ |
| 551 | } |
| 552 | void tms340x0_device::divs_a(UINT16 op) { DIVS(A); } |
| 553 | void tms340x0_device::divs_b(UINT16 op) { DIVS(B); } |
| 554 | |
| 555 | #define DIVU(R) \ |
| 556 | { \ |
| 557 | INT32 *rs = &R##REG(SRCREG(op)); \ |
| 558 | INT32 *rd1 = &R##REG(DSTREG(op)); \ |
| 559 | CLR_ZV(); \ |
| 560 | if (!(DSTREG(op) & 1)) \ |
| 561 | { \ |
| 562 | if (!*rs) \ |
| 563 | { \ |
| 564 | SET_V_LOG(1); \ |
| 565 | } \ |
| 566 | else \ |
| 567 | { \ |
| 568 | INT32 *rd2 = &R##REG(DSTREG(op)+1); \ |
| 569 | UINT64 dividend = ((UINT64)*rd1 << 32) | (UINT32)*rd2; \ |
| 570 | UINT64 quotient = dividend / (UINT32)*rs; \ |
| 571 | UINT32 remainder = dividend % (UINT32)*rs; \ |
| 572 | if (EXTRACT_64HI(quotient) != 0) \ |
| 573 | { \ |
| 574 | SET_V_LOG(1); \ |
| 575 | } \ |
| 576 | else \ |
| 577 | { \ |
| 578 | *rd1 = quotient; \ |
| 579 | *rd2 = remainder; \ |
| 580 | SET_Z_VAL(*rd1); \ |
| 581 | } \ |
| 582 | } \ |
| 583 | } \ |
| 584 | else \ |
| 585 | { \ |
| 586 | if (!*rs) \ |
| 587 | { \ |
| 588 | SET_V_LOG(1); \ |
| 589 | } \ |
| 590 | else \ |
| 591 | { \ |
| 592 | *rd1 = (UINT32)*rd1 / (UINT32)*rs; \ |
| 593 | SET_Z_VAL(*rd1); \ |
| 594 | } \ |
| 595 | } \ |
| 596 | COUNT_CYCLES(37); \ |
| 597 | } |
| 598 | void tms340x0_device::divu_a(UINT16 op) { DIVU(A); } |
| 599 | void tms340x0_device::divu_b(UINT16 op) { DIVU(B); } |
| 600 | |
| 601 | void tms340x0_device::eint(UINT16 op) |
| 602 | { |
| 603 | m_st |= STBIT_IE; |
| 604 | check_interrupt(); |
| 605 | COUNT_CYCLES(3); |
| 606 | } |
| 607 | |
| 608 | #define EXGF(F,R) \ |
| 609 | { \ |
| 610 | UINT8 shift = F ? 6 : 0; \ |
| 611 | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 612 | UINT32 temp = (m_st >> shift) & 0x3f; \ |
| 613 | m_st &= ~(0x3f << shift); \ |
| 614 | m_st |= (*rd & 0x3f) << shift; \ |
| 615 | *rd = temp; \ |
| 616 | COUNT_CYCLES(1); \ |
| 617 | } |
| 618 | void tms340x0_device::exgf0_a(UINT16 op) { EXGF(0,A); } |
| 619 | void tms340x0_device::exgf0_b(UINT16 op) { EXGF(0,B); } |
| 620 | void tms340x0_device::exgf1_a(UINT16 op) { EXGF(1,A); } |
| 621 | void tms340x0_device::exgf1_b(UINT16 op) { EXGF(1,B); } |
| 622 | |
| 623 | #define LMO(R) \ |
| 624 | { \ |
| 625 | UINT32 res = 0; \ |
| 626 | UINT32 rs = R##REG(SRCREG(op)); \ |
| 627 | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 628 | CLR_Z(); \ |
| 629 | SET_Z_VAL(rs); \ |
| 630 | if (rs) \ |
| 631 | { \ |
| 632 | while (!(rs & 0x80000000)) \ |
| 633 | { \ |
| 634 | res++; \ |
| 635 | rs <<= 1; \ |
| 636 | } \ |
| 637 | } \ |
| 638 | *rd = res; \ |
| 639 | COUNT_CYCLES(1); \ |
| 640 | } |
| 641 | void tms340x0_device::lmo_a(UINT16 op) { LMO(A); } |
| 642 | void tms340x0_device::lmo_b(UINT16 op) { LMO(B); } |
| 643 | |
| 644 | #define MMFM(R) \ |
| 645 | { \ |
| 646 | INT32 i; \ |
| 647 | UINT16 l = (UINT16) PARAM_WORD(); \ |
| 648 | COUNT_CYCLES(3); \ |
| 649 | { \ |
| 650 | INT32 rd = DSTREG(op); \ |
| 651 | for (i = 15; i >= 0 ; i--) \ |
| 652 | { \ |
| 653 | if (l & 0x8000) \ |
| 654 | { \ |
| 655 | R##REG(i) = RLONG(R##REG(rd)); \ |
| 656 | R##REG(rd) += 0x20; \ |
| 657 | COUNT_CYCLES(4); \ |
| 658 | } \ |
| 659 | l <<= 1; \ |
| 660 | } \ |
| 661 | } \ |
| 662 | } |
| 663 | void tms340x0_device::mmfm_a(UINT16 op) { MMFM(A); } |
| 664 | void tms340x0_device::mmfm_b(UINT16 op) { MMFM(B); } |
| 665 | |
| 666 | #define MMTM(R) \ |
| 667 | { \ |
| 668 | UINT32 i; \ |
| 669 | UINT16 l = (UINT16) PARAM_WORD(); \ |
| 670 | COUNT_CYCLES(2); \ |
| 671 | { \ |
| 672 | INT32 rd = DSTREG(op); \ |
| 673 | if (m_is_34020) \ |
| 674 | { \ |
| 675 | CLR_N(); \ |
| 676 | SET_N_VAL(R##REG(rd) ^ 0x80000000); \ |
| 677 | } \ |
| 678 | for (i = 0; i < 16; i++) \ |
| 679 | { \ |
| 680 | if (l & 0x8000) \ |
| 681 | { \ |
| 682 | R##REG(rd) -= 0x20; \ |
| 683 | WLONG(R##REG(rd),R##REG(i)); \ |
| 684 | COUNT_CYCLES(4); \ |
| 685 | } \ |
| 686 | l <<= 1; \ |
| 687 | } \ |
| 688 | } \ |
| 689 | } |
| 690 | void tms340x0_device::mmtm_a(UINT16 op) { MMTM(A); } |
| 691 | void tms340x0_device::mmtm_b(UINT16 op) { MMTM(B); } |
| 692 | |
| 693 | #define MODS(R) \ |
| 694 | { \ |
| 695 | INT32 *rs = &R##REG(SRCREG(op)); \ |
| 696 | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 697 | CLR_NZV(); \ |
| 698 | if (*rs != 0) \ |
| 699 | { \ |
| 700 | *rd %= *rs; \ |
| 701 | SET_NZ_VAL(*rd); \ |
| 702 | } \ |
| 703 | else \ |
| 704 | SET_V_LOG(1); \ |
| 705 | COUNT_CYCLES(40); \ |
| 706 | } |
| 707 | void tms340x0_device::mods_a(UINT16 op) { MODS(A); } |
| 708 | void tms340x0_device::mods_b(UINT16 op) { MODS(B); } |
| 709 | |
| 710 | #define MODU(R) \ |
| 711 | { \ |
| 712 | INT32 *rs = &R##REG(SRCREG(op)); \ |
| 713 | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 714 | CLR_ZV(); \ |
| 715 | if (*rs != 0) \ |
| 716 | { \ |
| 717 | *rd = (UINT32)*rd % (UINT32)*rs; \ |
| 718 | SET_Z_VAL(*rd); \ |
| 719 | } \ |
| 720 | else \ |
| 721 | SET_V_LOG(1); \ |
| 722 | COUNT_CYCLES(35); \ |
| 723 | } |
| 724 | void tms340x0_device::modu_a(UINT16 op) { MODU(A); } |
| 725 | void tms340x0_device::modu_b(UINT16 op) { MODU(B); } |
| 726 | |
| 727 | #define MPYS(R) \ |
| 728 | { \ |
| 729 | INT32 *rd1 = &R##REG(DSTREG(op)); \ |
| 730 | INT32 m1 = R##REG(SRCREG(op)); \ |
| 731 | INT64 product; \ |
| 732 | \ |
| 733 | SEXTEND(m1, FW(1)); \ |
| 734 | CLR_NZ(); \ |
| 735 | product = mul_32x32(m1, *rd1); \ |
| 736 | SET_Z_LOG(product == 0); \ |
| 737 | SET_N_BIT(product >> 32, 31); \ |
| 738 | \ |
| 739 | *rd1 = EXTRACT_64HI(product); \ |
| 740 | R##REG(DSTREG(op)|1) = EXTRACT_64LO(product); \ |
| 741 | \ |
| 742 | COUNT_CYCLES(20); \ |
| 743 | } |
| 744 | void tms340x0_device::mpys_a(UINT16 op) { MPYS(A); } |
| 745 | void tms340x0_device::mpys_b(UINT16 op) { MPYS(B); } |
| 746 | |
| 747 | #define MPYU(R) \ |
| 748 | { \ |
| 749 | INT32 *rd1 = &R##REG(DSTREG(op)); \ |
| 750 | UINT32 m1 = R##REG(SRCREG(op)); \ |
| 751 | UINT64 product; \ |
| 752 | \ |
| 753 | ZEXTEND(m1, FW(1)); \ |
| 754 | CLR_Z(); \ |
| 755 | product = mulu_32x32(m1, *rd1); \ |
| 756 | SET_Z_LOG(product == 0); \ |
| 757 | \ |
| 758 | *rd1 = EXTRACT_64HI(product); \ |
| 759 | R##REG(DSTREG(op)|1) = EXTRACT_64LO(product); \ |
| 760 | \ |
| 761 | COUNT_CYCLES(21); \ |
| 762 | } |
| 763 | void tms340x0_device::mpyu_a(UINT16 op) { MPYU(A); } |
| 764 | void tms340x0_device::mpyu_b(UINT16 op) { MPYU(B); } |
| 765 | |
| 766 | #define NEG(R) \ |
| 767 | { \ |
| 768 | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 769 | INT32 r = 0 - *rd; \ |
| 770 | CLR_NCZV(); \ |
| 771 | SET_NZCV_SUB(0,*rd,r); \ |
| 772 | *rd = r; \ |
| 773 | COUNT_CYCLES(1); \ |
| 774 | } |
| 775 | void tms340x0_device::neg_a(UINT16 op) { NEG(A); } |
| 776 | void tms340x0_device::neg_b(UINT16 op) { NEG(B); } |
| 777 | |
| 778 | #define NEGB(R) \ |
| 779 | { \ |
| 780 | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 781 | INT32 t = *rd + (C_FLAG() ? 1 : 0); \ |
| 782 | INT32 r = 0 - t; \ |
| 783 | CLR_NCZV(); \ |
| 784 | SET_NZCV_SUB(0,t,r); \ |
| 785 | *rd = r; \ |
| 786 | COUNT_CYCLES(1); \ |
| 787 | } |
| 788 | void tms340x0_device::negb_a(UINT16 op) { NEGB(A); } |
| 789 | void tms340x0_device::negb_b(UINT16 op) { NEGB(B); } |
| 790 | |
| 791 | void tms340x0_device::nop(UINT16 op) |
| 792 | { |
| 793 | COUNT_CYCLES(1); |
| 794 | } |
| 795 | |
| 796 | #define NOT(R) \ |
| 797 | { \ |
| 798 | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 799 | CLR_Z(); \ |
| 800 | *rd = ~(*rd); \ |
| 801 | SET_Z_VAL(*rd); \ |
| 802 | COUNT_CYCLES(1); \ |
| 803 | } |
| 804 | void tms340x0_device::not_a(UINT16 op) { NOT(A); } |
| 805 | void tms340x0_device::not_b(UINT16 op) { NOT(B); } |
| 806 | |
| 807 | #define OR(R) \ |
| 808 | { \ |
| 809 | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 810 | CLR_Z(); \ |
| 811 | *rd |= R##REG(SRCREG(op)); \ |
| 812 | SET_Z_VAL(*rd); \ |
| 813 | COUNT_CYCLES(1); \ |
| 814 | } |
| 815 | void tms340x0_device::or_a(UINT16 op) { OR(A); } |
| 816 | void tms340x0_device::or_b(UINT16 op) { OR(B); } |
| 817 | |
| 818 | #define ORI(R) \ |
| 819 | { \ |
| 820 | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 821 | CLR_Z(); \ |
| 822 | *rd |= PARAM_LONG(); \ |
| 823 | SET_Z_VAL(*rd); \ |
| 824 | COUNT_CYCLES(3); \ |
| 825 | } |
| 826 | void tms340x0_device::ori_a(UINT16 op) { ORI(A); } |
| 827 | void tms340x0_device::ori_b(UINT16 op) { ORI(B); } |
| 828 | |
| 829 | void tms340x0_device::setc(UINT16 op) |
| 830 | { |
| 831 | SET_C_LOG(1); |
| 832 | COUNT_CYCLES(1); |
| 833 | } |
| 834 | |
| 835 | #define SETF(F) \ |
| 836 | { \ |
| 837 | UINT8 shift = F ? 6 : 0; \ |
| 838 | m_st &= ~(0x3f << shift); \ |
| 839 | m_st |= (op & 0x3f) << shift; \ |
| 840 | COUNT_CYCLES(1+F); \ |
| 841 | } |
| 842 | void tms340x0_device::setf0(UINT16 op) { SETF(0); } |
| 843 | void tms340x0_device::setf1(UINT16 op) { SETF(1); } |
| 844 | |
| 845 | #define SEXT(F,R) \ |
| 846 | { \ |
| 847 | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 848 | CLR_NZ(); \ |
| 849 | SEXTEND(*rd,FW(F)); \ |
| 850 | SET_NZ_VAL(*rd); \ |
| 851 | COUNT_CYCLES(3); \ |
| 852 | } |
| 853 | void tms340x0_device::sext0_a(UINT16 op) { SEXT(0,A); } |
| 854 | void tms340x0_device::sext0_b(UINT16 op) { SEXT(0,B); } |
| 855 | void tms340x0_device::sext1_a(UINT16 op) { SEXT(1,A); } |
| 856 | void tms340x0_device::sext1_b(UINT16 op) { SEXT(1,B); } |
| 857 | |
| 858 | #define RL(R,K) \ |
| 859 | { \ |
| 860 | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 861 | INT32 res = *rd; \ |
| 862 | INT32 k = (K); \ |
| 863 | CLR_CZ(); \ |
| 864 | if (k) \ |
| 865 | { \ |
| 866 | res<<=(k-1); \ |
| 867 | SET_C_BIT_HI(res, 31); \ |
| 868 | res<<=1; \ |
| 869 | res |= (((UINT32)*rd)>>((-k)&0x1f)); \ |
| 870 | *rd = res; \ |
| 871 | } \ |
| 872 | SET_Z_VAL(res); \ |
| 873 | COUNT_CYCLES(1); \ |
| 874 | } |
| 875 | void tms340x0_device::rl_k_a(UINT16 op) { RL(A,PARAM_K(op)); } |
| 876 | void tms340x0_device::rl_k_b(UINT16 op) { RL(B,PARAM_K(op)); } |
| 877 | void tms340x0_device::rl_r_a(UINT16 op) { RL(A,AREG(SRCREG(op))&0x1f); } |
| 878 | void tms340x0_device::rl_r_b(UINT16 op) { RL(B,BREG(SRCREG(op))&0x1f); } |
| 879 | |
| 880 | #define SLA(R,K) \ |
| 881 | { \ |
| 882 | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 883 | UINT32 res = *rd; \ |
| 884 | INT32 k = K; \ |
| 885 | CLR_NCZV(); \ |
| 886 | if (k) \ |
| 887 | { \ |
| 888 | UINT32 mask = (0xffffffff<<(31-k))&0x7fffffff; \ |
| 889 | UINT32 res2 = SIGN(res) ? res^mask : res; \ |
| 890 | SET_V_LOG((res2 & mask) != 0); \ |
| 891 | \ |
| 892 | res<<=(k-1); \ |
| 893 | SET_C_BIT_HI(res, 31); \ |
| 894 | res<<=1; \ |
| 895 | *rd = res; \ |
| 896 | } \ |
| 897 | SET_NZ_VAL(res); \ |
| 898 | COUNT_CYCLES(3); \ |
| 899 | } |
| 900 | void tms340x0_device::sla_k_a(UINT16 op) { SLA(A,PARAM_K(op)); } |
| 901 | void tms340x0_device::sla_k_b(UINT16 op) { SLA(B,PARAM_K(op)); } |
| 902 | void tms340x0_device::sla_r_a(UINT16 op) { SLA(A,AREG(SRCREG(op))&0x1f); } |
| 903 | void tms340x0_device::sla_r_b(UINT16 op) { SLA(B,BREG(SRCREG(op))&0x1f); } |
| 904 | |
| 905 | #define SLL(R,K) \ |
| 906 | { \ |
| 907 | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 908 | UINT32 res = *rd; \ |
| 909 | INT32 k = K; \ |
| 910 | CLR_CZ(); \ |
| 911 | if (k) \ |
| 912 | { \ |
| 913 | res<<=(k-1); \ |
| 914 | SET_C_BIT_HI(res, 31); \ |
| 915 | res<<=1; \ |
| 916 | *rd = res; \ |
| 917 | } \ |
| 918 | SET_Z_VAL(res); \ |
| 919 | COUNT_CYCLES(1); \ |
| 920 | } |
| 921 | void tms340x0_device::sll_k_a(UINT16 op) { SLL(A,PARAM_K(op)); } |
| 922 | void tms340x0_device::sll_k_b(UINT16 op) { SLL(B,PARAM_K(op)); } |
| 923 | void tms340x0_device::sll_r_a(UINT16 op) { SLL(A,AREG(SRCREG(op))&0x1f); } |
| 924 | void tms340x0_device::sll_r_b(UINT16 op) { SLL(B,BREG(SRCREG(op))&0x1f); } |
| 925 | |
| 926 | #define SRA(R,K) \ |
| 927 | { \ |
| 928 | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 929 | INT32 res = *rd; \ |
| 930 | INT32 k = (-(K)) & 0x1f; \ |
| 931 | CLR_NCZ(); \ |
| 932 | if (k) \ |
| 933 | { \ |
| 934 | res>>=(k-1); \ |
| 935 | SET_C_BIT_LO(res, 0); \ |
| 936 | res>>=1; \ |
| 937 | *rd = res; \ |
| 938 | } \ |
| 939 | SET_NZ_VAL(res); \ |
| 940 | COUNT_CYCLES(1); \ |
| 941 | } |
| 942 | void tms340x0_device::sra_k_a(UINT16 op) { SRA(A,PARAM_K(op)); } |
| 943 | void tms340x0_device::sra_k_b(UINT16 op) { SRA(B,PARAM_K(op)); } |
| 944 | void tms340x0_device::sra_r_a(UINT16 op) { SRA(A,AREG(SRCREG(op))); } |
| 945 | void tms340x0_device::sra_r_b(UINT16 op) { SRA(B,BREG(SRCREG(op))); } |
| 946 | |
| 947 | #define SRL(R,K) \ |
| 948 | { \ |
| 949 | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 950 | UINT32 res = *rd; \ |
| 951 | INT32 k = (-(K)) & 0x1f; \ |
| 952 | CLR_CZ(); \ |
| 953 | if (k) \ |
| 954 | { \ |
| 955 | res>>=(k-1); \ |
| 956 | SET_C_BIT_LO(res, 0); \ |
| 957 | res>>=1; \ |
| 958 | *rd = res; \ |
| 959 | } \ |
| 960 | SET_Z_VAL(res); \ |
| 961 | COUNT_CYCLES(1); \ |
| 962 | } |
| 963 | void tms340x0_device::srl_k_a(UINT16 op) { SRL(A,PARAM_K(op)); } |
| 964 | void tms340x0_device::srl_k_b(UINT16 op) { SRL(B,PARAM_K(op)); } |
| 965 | void tms340x0_device::srl_r_a(UINT16 op) { SRL(A,AREG(SRCREG(op))); } |
| 966 | void tms340x0_device::srl_r_b(UINT16 op) { SRL(B,BREG(SRCREG(op))); } |
| 967 | |
| 968 | #define SUB(R) \ |
| 969 | { \ |
| 970 | INT32 *rs = &R##REG(SRCREG(op)); \ |
| 971 | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 972 | INT32 r = *rd - *rs; \ |
| 973 | CLR_NCZV(); \ |
| 974 | SET_NZCV_SUB(*rd,*rs,r); \ |
| 975 | *rd = r; \ |
| 976 | COUNT_CYCLES(1); \ |
| 977 | } |
| 978 | void tms340x0_device::sub_a(UINT16 op) { SUB(A); } |
| 979 | void tms340x0_device::sub_b(UINT16 op) { SUB(B); } |
| 980 | |
| 981 | #define SUBB(R) \ |
| 982 | { \ |
| 983 | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 984 | INT32 t = R##REG(SRCREG(op)); \ |
| 985 | INT32 r = *rd - t - (C_FLAG() ? 1 : 0); \ |
| 986 | CLR_NCZV(); \ |
| 987 | SET_NZCV_SUB(*rd,t,r); \ |
| 988 | *rd = r; \ |
| 989 | COUNT_CYCLES(1); \ |
| 990 | } |
| 991 | void tms340x0_device::subb_a(UINT16 op) { SUBB(A); } |
| 992 | void tms340x0_device::subb_b(UINT16 op) { SUBB(B); } |
| 993 | |
| 994 | #define SUBI_W(R) \ |
| 995 | { \ |
| 996 | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 997 | INT32 r; \ |
| 998 | INT32 t = ~PARAM_WORD(); \ |
| 999 | CLR_NCZV(); \ |
| 1000 | r = *rd - t; \ |
| 1001 | SET_NZCV_SUB(*rd,t,r); \ |
| 1002 | *rd = r; \ |
| 1003 | COUNT_CYCLES(2); \ |
| 1004 | } |
| 1005 | void tms340x0_device::subi_w_a(UINT16 op) { SUBI_W(A); } |
| 1006 | void tms340x0_device::subi_w_b(UINT16 op) { SUBI_W(B); } |
| 1007 | |
| 1008 | #define SUBI_L(R) \ |
| 1009 | { \ |
| 1010 | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 1011 | INT32 t = ~PARAM_LONG(); \ |
| 1012 | INT32 r = *rd - t; \ |
| 1013 | CLR_NCZV(); \ |
| 1014 | SET_NZCV_SUB(*rd,t,r); \ |
| 1015 | *rd = r; \ |
| 1016 | COUNT_CYCLES(3); \ |
| 1017 | } |
| 1018 | void tms340x0_device::subi_l_a(UINT16 op) { SUBI_L(A); } |
| 1019 | void tms340x0_device::subi_l_b(UINT16 op) { SUBI_L(B); } |
| 1020 | |
| 1021 | #define SUBK(R) \ |
| 1022 | { \ |
| 1023 | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 1024 | INT32 t = fw_inc[PARAM_K(op)]; \ |
| 1025 | INT32 r = *rd - t; \ |
| 1026 | CLR_NCZV(); \ |
| 1027 | SET_NZCV_SUB(*rd,t,r); \ |
| 1028 | *rd = r; \ |
| 1029 | COUNT_CYCLES(1); \ |
| 1030 | } |
| 1031 | void tms340x0_device::subk_a(UINT16 op) { SUBK(A); } |
| 1032 | void tms340x0_device::subk_b(UINT16 op) { SUBK(B); } |
| 1033 | |
| 1034 | #define XOR(R) \ |
| 1035 | { \ |
| 1036 | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 1037 | CLR_Z(); \ |
| 1038 | *rd ^= R##REG(SRCREG(op)); \ |
| 1039 | SET_Z_VAL(*rd); \ |
| 1040 | COUNT_CYCLES(1); \ |
| 1041 | } |
| 1042 | void tms340x0_device::xor_a(UINT16 op) { XOR(A); } |
| 1043 | void tms340x0_device::xor_b(UINT16 op) { XOR(B); } |
| 1044 | |
| 1045 | #define XORI(R) \ |
| 1046 | { \ |
| 1047 | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 1048 | CLR_Z(); \ |
| 1049 | *rd ^= PARAM_LONG(); \ |
| 1050 | SET_Z_VAL(*rd); \ |
| 1051 | COUNT_CYCLES(3); \ |
| 1052 | } |
| 1053 | void tms340x0_device::xori_a(UINT16 op) { XORI(A); } |
| 1054 | void tms340x0_device::xori_b(UINT16 op) { XORI(B); } |
| 1055 | |
| 1056 | #define ZEXT(F,R) \ |
| 1057 | { \ |
| 1058 | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 1059 | CLR_Z(); \ |
| 1060 | ZEXTEND(*rd,FW(F)); \ |
| 1061 | SET_Z_VAL(*rd); \ |
| 1062 | COUNT_CYCLES(1); \ |
| 1063 | } |
| 1064 | void tms340x0_device::zext0_a(UINT16 op) { ZEXT(0,A); } |
| 1065 | void tms340x0_device::zext0_b(UINT16 op) { ZEXT(0,B); } |
| 1066 | void tms340x0_device::zext1_a(UINT16 op) { ZEXT(1,A); } |
| 1067 | void tms340x0_device::zext1_b(UINT16 op) { ZEXT(1,B); } |
| 1068 | |
| 1069 | |
| 1070 | |
| 1071 | /*************************************************************************** |
| 1072 | MOVE INSTRUCTIONS |
| 1073 | ***************************************************************************/ |
| 1074 | |
| 1075 | #define MOVI_W(R) \ |
| 1076 | { \ |
| 1077 | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 1078 | CLR_NZV(); \ |
| 1079 | *rd=PARAM_WORD(); \ |
| 1080 | SET_NZ_VAL(*rd); \ |
| 1081 | COUNT_CYCLES(2); \ |
| 1082 | } |
| 1083 | void tms340x0_device::movi_w_a(UINT16 op) { MOVI_W(A); } |
| 1084 | void tms340x0_device::movi_w_b(UINT16 op) { MOVI_W(B); } |
| 1085 | |
| 1086 | #define MOVI_L(R) \ |
| 1087 | { \ |
| 1088 | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 1089 | CLR_NZV(); \ |
| 1090 | *rd=PARAM_LONG(); \ |
| 1091 | SET_NZ_VAL(*rd); \ |
| 1092 | COUNT_CYCLES(3); \ |
| 1093 | } |
| 1094 | void tms340x0_device::movi_l_a(UINT16 op) { MOVI_L(A); } |
| 1095 | void tms340x0_device::movi_l_b(UINT16 op) { MOVI_L(B); } |
| 1096 | |
| 1097 | #define MOVK(R) \ |
| 1098 | { \ |
| 1099 | INT32 k = PARAM_K(op); if (!k) k = 32; \ |
| 1100 | R##REG(DSTREG(op)) = k; \ |
| 1101 | COUNT_CYCLES(1); \ |
| 1102 | } |
| 1103 | void tms340x0_device::movk_a(UINT16 op) { MOVK(A); } |
| 1104 | void tms340x0_device::movk_b(UINT16 op) { MOVK(B); } |
| 1105 | |
| 1106 | #define MOVB_RN(R) \ |
| 1107 | { \ |
| 1108 | WBYTE(R##REG(DSTREG(op)),R##REG(SRCREG(op))); \ |
| 1109 | COUNT_CYCLES(1); \ |
| 1110 | } |
| 1111 | void tms340x0_device::movb_rn_a(UINT16 op) { MOVB_RN(A); } |
| 1112 | void tms340x0_device::movb_rn_b(UINT16 op) { MOVB_RN(B); } |
| 1113 | |
| 1114 | #define MOVB_NR(R) \ |
| 1115 | { \ |
| 1116 | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 1117 | CLR_NZV(); \ |
| 1118 | *rd = (INT8)RBYTE(R##REG(SRCREG(op))); \ |
| 1119 | SET_NZ_VAL(*rd); \ |
| 1120 | COUNT_CYCLES(3); \ |
| 1121 | } |
| 1122 | void tms340x0_device::movb_nr_a(UINT16 op) { MOVB_NR(A); } |
| 1123 | void tms340x0_device::movb_nr_b(UINT16 op) { MOVB_NR(B); } |
| 1124 | |
| 1125 | #define MOVB_NN(R) \ |
| 1126 | { \ |
| 1127 | WBYTE(R##REG(DSTREG(op)),(UINT32)(UINT8)RBYTE(R##REG(SRCREG(op))));\ |
| 1128 | COUNT_CYCLES(3); \ |
| 1129 | } |
| 1130 | void tms340x0_device::movb_nn_a(UINT16 op) { MOVB_NN(A); } |
| 1131 | void tms340x0_device::movb_nn_b(UINT16 op) { MOVB_NN(B); } |
| 1132 | |
| 1133 | #define MOVB_R_NO(R) \ |
| 1134 | { \ |
| 1135 | INT32 o = PARAM_WORD(); \ |
| 1136 | WBYTE(R##REG(DSTREG(op))+o,R##REG(SRCREG(op))); \ |
| 1137 | COUNT_CYCLES(3); \ |
| 1138 | } |
| 1139 | void tms340x0_device::movb_r_no_a(UINT16 op) { MOVB_R_NO(A); } |
| 1140 | void tms340x0_device::movb_r_no_b(UINT16 op) { MOVB_R_NO(B); } |
| 1141 | |
| 1142 | #define MOVB_NO_R(R) \ |
| 1143 | { \ |
| 1144 | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 1145 | INT32 o = PARAM_WORD(); \ |
| 1146 | CLR_NZV(); \ |
| 1147 | *rd = (INT8)RBYTE(R##REG(SRCREG(op))+o); \ |
| 1148 | SET_NZ_VAL(*rd); \ |
| 1149 | COUNT_CYCLES(5); \ |
| 1150 | } |
| 1151 | void tms340x0_device::movb_no_r_a(UINT16 op) { MOVB_NO_R(A); } |
| 1152 | void tms340x0_device::movb_no_r_b(UINT16 op) { MOVB_NO_R(B); } |
| 1153 | |
| 1154 | #define MOVB_NO_NO(R) \ |
| 1155 | { \ |
| 1156 | INT32 o1 = PARAM_WORD(); \ |
| 1157 | INT32 o2 = PARAM_WORD(); \ |
| 1158 | WBYTE(R##REG(DSTREG(op))+o2,(UINT32)(UINT8)RBYTE(R##REG(SRCREG(op))+o1)); \ |
| 1159 | COUNT_CYCLES(5); \ |
| 1160 | } |
| 1161 | void tms340x0_device::movb_no_no_a(UINT16 op) { MOVB_NO_NO(A); } |
| 1162 | void tms340x0_device::movb_no_no_b(UINT16 op) { MOVB_NO_NO(B); } |
| 1163 | |
| 1164 | #define MOVB_RA(R) \ |
| 1165 | { \ |
| 1166 | WBYTE(PARAM_LONG(),R##REG(DSTREG(op))); \ |
| 1167 | COUNT_CYCLES(1); \ |
| 1168 | } |
| 1169 | void tms340x0_device::movb_ra_a(UINT16 op) { MOVB_RA(A); } |
| 1170 | void tms340x0_device::movb_ra_b(UINT16 op) { MOVB_RA(B); } |
| 1171 | |
| 1172 | #define MOVB_AR(R) \ |
| 1173 | { \ |
| 1174 | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 1175 | CLR_NZV(); \ |
| 1176 | *rd = (INT8)RBYTE(PARAM_LONG()); \ |
| 1177 | SET_NZ_VAL(*rd); \ |
| 1178 | COUNT_CYCLES(5); \ |
| 1179 | } |
| 1180 | void tms340x0_device::movb_ar_a(UINT16 op) { MOVB_AR(A); } |
| 1181 | void tms340x0_device::movb_ar_b(UINT16 op) { MOVB_AR(B); } |
| 1182 | |
| 1183 | void tms340x0_device::movb_aa(UINT16 op) |
| 1184 | { |
| 1185 | UINT32 bitaddrs=PARAM_LONG(); |
| 1186 | WBYTE(PARAM_LONG(),(UINT32)(UINT8)RBYTE(bitaddrs)); |
| 1187 | COUNT_CYCLES(6); |
| 1188 | } |
| 1189 | |
| 1190 | #define MOVE_RR(RS,RD) \ |
| 1191 | { \ |
| 1192 | INT32 *rd = &RD##REG(DSTREG(op)); \ |
| 1193 | CLR_NZV(); \ |
| 1194 | *rd = RS##REG(SRCREG(op)); \ |
| 1195 | SET_NZ_VAL(*rd); \ |
| 1196 | COUNT_CYCLES(1); \ |
| 1197 | } |
| 1198 | void tms340x0_device::move_rr_a (UINT16 op) { MOVE_RR(A,A); } |
| 1199 | void tms340x0_device::move_rr_b (UINT16 op) { MOVE_RR(B,B); } |
| 1200 | void tms340x0_device::move_rr_ax(UINT16 op) { MOVE_RR(A,B); } |
| 1201 | void tms340x0_device::move_rr_bx(UINT16 op) { MOVE_RR(B,A); } |
| 1202 | |
| 1203 | #define MOVE_RN(F,R) \ |
| 1204 | { \ |
| 1205 | WFIELD##F(R##REG(DSTREG(op)),R##REG(SRCREG(op))); \ |
| 1206 | COUNT_CYCLES(1); \ |
| 1207 | } |
| 1208 | void tms340x0_device::move0_rn_a (UINT16 op) { MOVE_RN(0,A); } |
| 1209 | void tms340x0_device::move0_rn_b (UINT16 op) { MOVE_RN(0,B); } |
| 1210 | void tms340x0_device::move1_rn_a (UINT16 op) { MOVE_RN(1,A); } |
| 1211 | void tms340x0_device::move1_rn_b (UINT16 op) { MOVE_RN(1,B); } |
| 1212 | |
| 1213 | #define MOVE_R_DN(F,R) \ |
| 1214 | { \ |
| 1215 | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 1216 | *rd-=fw_inc[FW(F)]; \ |
| 1217 | WFIELD##F(*rd,R##REG(SRCREG(op))); \ |
| 1218 | COUNT_CYCLES(2); \ |
| 1219 | } |
| 1220 | void tms340x0_device::move0_r_dn_a (UINT16 op) { MOVE_R_DN(0,A); } |
| 1221 | void tms340x0_device::move0_r_dn_b (UINT16 op) { MOVE_R_DN(0,B); } |
| 1222 | void tms340x0_device::move1_r_dn_a (UINT16 op) { MOVE_R_DN(1,A); } |
| 1223 | void tms340x0_device::move1_r_dn_b (UINT16 op) { MOVE_R_DN(1,B); } |
| 1224 | |
| 1225 | #define MOVE_R_NI(F,R) \ |
| 1226 | { \ |
| 1227 | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 1228 | WFIELD##F(*rd,R##REG(SRCREG(op))); \ |
| 1229 | *rd+=fw_inc[FW(F)]; \ |
| 1230 | COUNT_CYCLES(1); \ |
| 1231 | } |
| 1232 | void tms340x0_device::move0_r_ni_a (UINT16 op) { MOVE_R_NI(0,A); } |
| 1233 | void tms340x0_device::move0_r_ni_b (UINT16 op) { MOVE_R_NI(0,B); } |
| 1234 | void tms340x0_device::move1_r_ni_a (UINT16 op) { MOVE_R_NI(1,A); } |
| 1235 | void tms340x0_device::move1_r_ni_b (UINT16 op) { MOVE_R_NI(1,B); } |
| 1236 | |
| 1237 | #define MOVE_NR(F,R) \ |
| 1238 | { \ |
| 1239 | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 1240 | CLR_NZV(); \ |
| 1241 | *rd = RFIELD##F(R##REG(SRCREG(op))); \ |
| 1242 | SET_NZ_VAL(*rd); \ |
| 1243 | COUNT_CYCLES(3); \ |
| 1244 | } |
| 1245 | void tms340x0_device::move0_nr_a (UINT16 op) { MOVE_NR(0,A); } |
| 1246 | void tms340x0_device::move0_nr_b (UINT16 op) { MOVE_NR(0,B); } |
| 1247 | void tms340x0_device::move1_nr_a (UINT16 op) { MOVE_NR(1,A); } |
| 1248 | void tms340x0_device::move1_nr_b (UINT16 op) { MOVE_NR(1,B); } |
| 1249 | |
| 1250 | #define MOVE_DN_R(F,R) \ |
| 1251 | { \ |
| 1252 | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 1253 | INT32 *rs = &R##REG(SRCREG(op)); \ |
| 1254 | CLR_NZV(); \ |
| 1255 | *rs-=fw_inc[FW(F)]; \ |
| 1256 | *rd = RFIELD##F(*rs); \ |
| 1257 | SET_NZ_VAL(*rd); \ |
| 1258 | COUNT_CYCLES(4); \ |
| 1259 | } |
| 1260 | void tms340x0_device::move0_dn_r_a (UINT16 op) { MOVE_DN_R(0,A); } |
| 1261 | void tms340x0_device::move0_dn_r_b (UINT16 op) { MOVE_DN_R(0,B); } |
| 1262 | void tms340x0_device::move1_dn_r_a (UINT16 op) { MOVE_DN_R(1,A); } |
| 1263 | void tms340x0_device::move1_dn_r_b (UINT16 op) { MOVE_DN_R(1,B); } |
| 1264 | |
| 1265 | #define MOVE_NI_R(F,R) \ |
| 1266 | { \ |
| 1267 | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 1268 | INT32 *rs = &R##REG(SRCREG(op)); \ |
| 1269 | INT32 data = RFIELD##F(*rs); \ |
| 1270 | CLR_NZV(); \ |
| 1271 | *rs+=fw_inc[FW(F)]; \ |
| 1272 | *rd = data; \ |
| 1273 | SET_NZ_VAL(*rd); \ |
| 1274 | COUNT_CYCLES(3); \ |
| 1275 | } |
| 1276 | void tms340x0_device::move0_ni_r_a (UINT16 op) { MOVE_NI_R(0,A); } |
| 1277 | void tms340x0_device::move0_ni_r_b (UINT16 op) { MOVE_NI_R(0,B); } |
| 1278 | void tms340x0_device::move1_ni_r_a (UINT16 op) { MOVE_NI_R(1,A); } |
| 1279 | void tms340x0_device::move1_ni_r_b (UINT16 op) { MOVE_NI_R(1,B); } |
| 1280 | |
| 1281 | #define MOVE_NN(F,R) \ |
| 1282 | { \ |
| 1283 | WFIELD##F(R##REG(DSTREG(op)),RFIELD##F(R##REG(SRCREG(op)))); \ |
| 1284 | COUNT_CYCLES(3); \ |
| 1285 | } |
| 1286 | void tms340x0_device::move0_nn_a (UINT16 op) { MOVE_NN(0,A); } |
| 1287 | void tms340x0_device::move0_nn_b (UINT16 op) { MOVE_NN(0,B); } |
| 1288 | void tms340x0_device::move1_nn_a (UINT16 op) { MOVE_NN(1,A); } |
| 1289 | void tms340x0_device::move1_nn_b (UINT16 op) { MOVE_NN(1,B); } |
| 1290 | |
| 1291 | #define MOVE_DN_DN(F,R) \ |
| 1292 | { \ |
| 1293 | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 1294 | INT32 *rs = &R##REG(SRCREG(op)); \ |
| 1295 | INT32 data; \ |
| 1296 | *rs-=fw_inc[FW(F)]; \ |
| 1297 | data = RFIELD##F(*rs); \ |
| 1298 | *rd-=fw_inc[FW(F)]; \ |
| 1299 | WFIELD##F(*rd,data); \ |
| 1300 | COUNT_CYCLES(4); \ |
| 1301 | } |
| 1302 | void tms340x0_device::move0_dn_dn_a (UINT16 op) { MOVE_DN_DN(0,A); } |
| 1303 | void tms340x0_device::move0_dn_dn_b (UINT16 op) { MOVE_DN_DN(0,B); } |
| 1304 | void tms340x0_device::move1_dn_dn_a (UINT16 op) { MOVE_DN_DN(1,A); } |
| 1305 | void tms340x0_device::move1_dn_dn_b (UINT16 op) { MOVE_DN_DN(1,B); } |
| 1306 | |
| 1307 | #define MOVE_NI_NI(F,R) \ |
| 1308 | { \ |
| 1309 | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 1310 | INT32 *rs = &R##REG(SRCREG(op)); \ |
| 1311 | INT32 data = RFIELD##F(*rs); \ |
| 1312 | *rs+=fw_inc[FW(F)]; \ |
| 1313 | WFIELD##F(*rd,data); \ |
| 1314 | *rd+=fw_inc[FW(F)]; \ |
| 1315 | COUNT_CYCLES(4); \ |
| 1316 | } |
| 1317 | void tms340x0_device::move0_ni_ni_a (UINT16 op) { MOVE_NI_NI(0,A); } |
| 1318 | void tms340x0_device::move0_ni_ni_b (UINT16 op) { MOVE_NI_NI(0,B); } |
| 1319 | void tms340x0_device::move1_ni_ni_a (UINT16 op) { MOVE_NI_NI(1,A); } |
| 1320 | void tms340x0_device::move1_ni_ni_b (UINT16 op) { MOVE_NI_NI(1,B); } |
| 1321 | |
| 1322 | #define MOVE_R_NO(F,R) \ |
| 1323 | { \ |
| 1324 | INT32 o = PARAM_WORD(); \ |
| 1325 | WFIELD##F(R##REG(DSTREG(op))+o,R##REG(SRCREG(op))); \ |
| 1326 | COUNT_CYCLES(3); \ |
| 1327 | } |
| 1328 | void tms340x0_device::move0_r_no_a (UINT16 op) { MOVE_R_NO(0,A); } |
| 1329 | void tms340x0_device::move0_r_no_b (UINT16 op) { MOVE_R_NO(0,B); } |
| 1330 | void tms340x0_device::move1_r_no_a (UINT16 op) { MOVE_R_NO(1,A); } |
| 1331 | void tms340x0_device::move1_r_no_b (UINT16 op) { MOVE_R_NO(1,B); } |
| 1332 | |
| 1333 | #define MOVE_NO_R(F,R) \ |
| 1334 | { \ |
| 1335 | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 1336 | INT32 o = PARAM_WORD(); \ |
| 1337 | CLR_NZV(); \ |
| 1338 | *rd = RFIELD##F(R##REG(SRCREG(op))+o); \ |
| 1339 | SET_NZ_VAL(*rd); \ |
| 1340 | COUNT_CYCLES(5); \ |
| 1341 | } |
| 1342 | void tms340x0_device::move0_no_r_a (UINT16 op) { MOVE_NO_R(0,A); } |
| 1343 | void tms340x0_device::move0_no_r_b (UINT16 op) { MOVE_NO_R(0,B); } |
| 1344 | void tms340x0_device::move1_no_r_a (UINT16 op) { MOVE_NO_R(1,A); } |
| 1345 | void tms340x0_device::move1_no_r_b (UINT16 op) { MOVE_NO_R(1,B); } |
| 1346 | |
| 1347 | #define MOVE_NO_NI(F,R) \ |
| 1348 | { \ |
| 1349 | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 1350 | INT32 o = PARAM_WORD(); \ |
| 1351 | INT32 data = RFIELD##F(R##REG(SRCREG(op))+o); \ |
| 1352 | WFIELD##F(*rd,data); \ |
| 1353 | *rd+=fw_inc[FW(F)]; \ |
| 1354 | COUNT_CYCLES(5); \ |
| 1355 | } |
| 1356 | void tms340x0_device::move0_no_ni_a (UINT16 op) { MOVE_NO_NI(0,A); } |
| 1357 | void tms340x0_device::move0_no_ni_b (UINT16 op) { MOVE_NO_NI(0,B); } |
| 1358 | void tms340x0_device::move1_no_ni_a (UINT16 op) { MOVE_NO_NI(1,A); } |
| 1359 | void tms340x0_device::move1_no_ni_b (UINT16 op) { MOVE_NO_NI(1,B); } |
| 1360 | |
| 1361 | #define MOVE_NO_NO(F,R) \ |
| 1362 | { \ |
| 1363 | INT32 o1 = PARAM_WORD(); \ |
| 1364 | INT32 o2 = PARAM_WORD(); \ |
| 1365 | INT32 data = RFIELD##F(R##REG(SRCREG(op))+o1); \ |
| 1366 | WFIELD##F(R##REG(DSTREG(op))+o2,data); \ |
| 1367 | COUNT_CYCLES(5); \ |
| 1368 | } |
| 1369 | void tms340x0_device::move0_no_no_a (UINT16 op) { MOVE_NO_NO(0,A); } |
| 1370 | void tms340x0_device::move0_no_no_b (UINT16 op) { MOVE_NO_NO(0,B); } |
| 1371 | void tms340x0_device::move1_no_no_a (UINT16 op) { MOVE_NO_NO(1,A); } |
| 1372 | void tms340x0_device::move1_no_no_b (UINT16 op) { MOVE_NO_NO(1,B); } |
| 1373 | |
| 1374 | #define MOVE_RA(F,R) \ |
| 1375 | { \ |
| 1376 | WFIELD##F(PARAM_LONG(),R##REG(DSTREG(op))); \ |
| 1377 | COUNT_CYCLES(3); \ |
| 1378 | } |
| 1379 | void tms340x0_device::move0_ra_a (UINT16 op) { MOVE_RA(0,A); } |
| 1380 | void tms340x0_device::move0_ra_b (UINT16 op) { MOVE_RA(0,B); } |
| 1381 | void tms340x0_device::move1_ra_a (UINT16 op) { MOVE_RA(1,A); } |
| 1382 | void tms340x0_device::move1_ra_b (UINT16 op) { MOVE_RA(1,B); } |
| 1383 | |
| 1384 | #define MOVE_AR(F,R) \ |
| 1385 | { \ |
| 1386 | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 1387 | CLR_NZV(); \ |
| 1388 | *rd = RFIELD##F(PARAM_LONG()); \ |
| 1389 | SET_NZ_VAL(*rd); \ |
| 1390 | COUNT_CYCLES(5); \ |
| 1391 | } |
| 1392 | void tms340x0_device::move0_ar_a (UINT16 op) { MOVE_AR(0,A); } |
| 1393 | void tms340x0_device::move0_ar_b (UINT16 op) { MOVE_AR(0,B); } |
| 1394 | void tms340x0_device::move1_ar_a (UINT16 op) { MOVE_AR(1,A); } |
| 1395 | void tms340x0_device::move1_ar_b (UINT16 op) { MOVE_AR(1,B); } |
| 1396 | |
| 1397 | #define MOVE_A_NI(F,R) \ |
| 1398 | { \ |
| 1399 | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 1400 | WFIELD##F(*rd,RFIELD##F(PARAM_LONG())); \ |
| 1401 | *rd+=fw_inc[FW(F)]; \ |
| 1402 | COUNT_CYCLES(5); \ |
| 1403 | } |
| 1404 | void tms340x0_device::move0_a_ni_a (UINT16 op) { MOVE_A_NI(0,A); } |
| 1405 | void tms340x0_device::move0_a_ni_b (UINT16 op) { MOVE_A_NI(0,B); } |
| 1406 | void tms340x0_device::move1_a_ni_a (UINT16 op) { MOVE_A_NI(1,A); } |
| 1407 | void tms340x0_device::move1_a_ni_b (UINT16 op) { MOVE_A_NI(1,B); } |
| 1408 | |
| 1409 | #define MOVE_AA(F) \ |
| 1410 | { \ |
| 1411 | UINT32 bitaddrs=PARAM_LONG(); \ |
| 1412 | WFIELD##F(PARAM_LONG(),RFIELD##F(bitaddrs)); \ |
| 1413 | COUNT_CYCLES(7); \ |
| 1414 | } |
| 1415 | void tms340x0_device::move0_aa (UINT16 op) { MOVE_AA(0); } |
| 1416 | void tms340x0_device::move1_aa (UINT16 op) { MOVE_AA(1); } |
| 1417 | |
| 1418 | |
| 1419 | |
| 1420 | /*************************************************************************** |
| 1421 | PROGRAM CONTROL INSTRUCTIONS |
| 1422 | ***************************************************************************/ |
| 1423 | |
| 1424 | #define CALL(R) \ |
| 1425 | { \ |
| 1426 | PUSH(m_pc); \ |
| 1427 | m_pc = R##REG(DSTREG(op)); \ |
| 1428 | CORRECT_ODD_PC("CALL"); \ |
| 1429 | COUNT_CYCLES(3); \ |
| 1430 | } |
| 1431 | void tms340x0_device::call_a (UINT16 op) { CALL(A); } |
| 1432 | void tms340x0_device::call_b (UINT16 op) { CALL(B); } |
| 1433 | |
| 1434 | void tms340x0_device::callr(UINT16 op) |
| 1435 | { |
| 1436 | PUSH(m_pc+0x10); |
| 1437 | m_pc += (PARAM_WORD_NO_INC()<<4)+0x10; |
| 1438 | COUNT_CYCLES(3); |
| 1439 | } |
| 1440 | |
| 1441 | void tms340x0_device::calla(UINT16 op) |
| 1442 | { |
| 1443 | PUSH(m_pc+0x20); |
| 1444 | m_pc = PARAM_LONG_NO_INC(); |
| 1445 | CORRECT_ODD_PC("CALLA"); |
| 1446 | COUNT_CYCLES(4); |
| 1447 | } |
| 1448 | |
| 1449 | #define DSJ(R) \ |
| 1450 | { \ |
| 1451 | if (--R##REG(DSTREG(op))) \ |
| 1452 | { \ |
| 1453 | m_pc += (PARAM_WORD_NO_INC()<<4)+0x10; \ |
| 1454 | COUNT_CYCLES(3); \ |
| 1455 | } \ |
| 1456 | else \ |
| 1457 | { \ |
| 1458 | SKIP_WORD(); \ |
| 1459 | COUNT_CYCLES(2); \ |
| 1460 | } \ |
| 1461 | } |
| 1462 | void tms340x0_device::dsj_a (UINT16 op) { DSJ(A); } |
| 1463 | void tms340x0_device::dsj_b (UINT16 op) { DSJ(B); } |
| 1464 | |
| 1465 | #define DSJEQ(R) \ |
| 1466 | { \ |
| 1467 | if (Z_FLAG()) \ |
| 1468 | { \ |
| 1469 | if (--R##REG(DSTREG(op))) \ |
| 1470 | { \ |
| 1471 | m_pc += (PARAM_WORD_NO_INC()<<4)+0x10; \ |
| 1472 | COUNT_CYCLES(3); \ |
| 1473 | } \ |
| 1474 | else \ |
| 1475 | { \ |
| 1476 | SKIP_WORD(); \ |
| 1477 | COUNT_CYCLES(2); \ |
| 1478 | } \ |
| 1479 | } \ |
| 1480 | else \ |
| 1481 | { \ |
| 1482 | SKIP_WORD(); \ |
| 1483 | COUNT_CYCLES(2); \ |
| 1484 | } \ |
| 1485 | } |
| 1486 | void tms340x0_device::dsjeq_a (UINT16 op) { DSJEQ(A); } |
| 1487 | void tms340x0_device::dsjeq_b (UINT16 op) { DSJEQ(B); } |
| 1488 | |
| 1489 | #define DSJNE(R) \ |
| 1490 | { \ |
| 1491 | if (!Z_FLAG()) \ |
| 1492 | { \ |
| 1493 | if (--R##REG(DSTREG(op))) \ |
| 1494 | { \ |
| 1495 | m_pc += (PARAM_WORD_NO_INC()<<4)+0x10; \ |
| 1496 | COUNT_CYCLES(3); \ |
| 1497 | } \ |
| 1498 | else \ |
| 1499 | { \ |
| 1500 | SKIP_WORD(); \ |
| 1501 | COUNT_CYCLES(2); \ |
| 1502 | } \ |
| 1503 | } \ |
| 1504 | else \ |
| 1505 | { \ |
| 1506 | SKIP_WORD(); \ |
| 1507 | COUNT_CYCLES(2); \ |
| 1508 | } \ |
| 1509 | } |
| 1510 | void tms340x0_device::dsjne_a (UINT16 op) { DSJNE(A); } |
| 1511 | void tms340x0_device::dsjne_b (UINT16 op) { DSJNE(B); } |
| 1512 | |
| 1513 | #define DSJS(R) \ |
| 1514 | { \ |
| 1515 | if (op & 0x0400) \ |
| 1516 | { \ |
| 1517 | if (--R##REG(DSTREG(op))) \ |
| 1518 | { \ |
| 1519 | m_pc -= ((PARAM_K(op))<<4); \ |
| 1520 | COUNT_CYCLES(2); \ |
| 1521 | } \ |
| 1522 | else \ |
| 1523 | COUNT_CYCLES(3); \ |
| 1524 | } \ |
| 1525 | else \ |
| 1526 | { \ |
| 1527 | if (--R##REG(DSTREG(op))) \ |
| 1528 | { \ |
| 1529 | m_pc += ((PARAM_K(op))<<4); \ |
| 1530 | COUNT_CYCLES(2); \ |
| 1531 | } \ |
| 1532 | else \ |
| 1533 | COUNT_CYCLES(3); \ |
| 1534 | } \ |
| 1535 | } |
| 1536 | void tms340x0_device::dsjs_a (UINT16 op) { DSJS(A); } |
| 1537 | void tms340x0_device::dsjs_b (UINT16 op) { DSJS(B); } |
| 1538 | |
| 1539 | void tms340x0_device::emu(UINT16 op) |
| 1540 | { |
| 1541 | /* in RUN state, this instruction is a NOP */ |
| 1542 | COUNT_CYCLES(6); |
| 1543 | } |
| 1544 | |
| 1545 | #define EXGPC(R) \ |
| 1546 | { \ |
| 1547 | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 1548 | INT32 temppc = *rd; \ |
| 1549 | *rd = m_pc; \ |
| 1550 | m_pc = temppc; \ |
| 1551 | CORRECT_ODD_PC("EXGPC"); \ |
| 1552 | COUNT_CYCLES(2); \ |
| 1553 | } |
| 1554 | void tms340x0_device::exgpc_a (UINT16 op) { EXGPC(A); } |
| 1555 | void tms340x0_device::exgpc_b (UINT16 op) { EXGPC(B); } |
| 1556 | |
| 1557 | #define GETPC(R) \ |
| 1558 | { \ |
| 1559 | R##REG(DSTREG(op)) = m_pc; \ |
| 1560 | COUNT_CYCLES(1); \ |
| 1561 | } |
| 1562 | void tms340x0_device::getpc_a (UINT16 op) { GETPC(A); } |
| 1563 | void tms340x0_device::getpc_b (UINT16 op) { GETPC(B); } |
| 1564 | |
| 1565 | #define GETST(R) \ |
| 1566 | { \ |
| 1567 | R##REG(DSTREG(op)) = m_st; \ |
| 1568 | COUNT_CYCLES(1); \ |
| 1569 | } |
| 1570 | void tms340x0_device::getst_a (UINT16 op) { GETST(A); } |
| 1571 | void tms340x0_device::getst_b (UINT16 op) { GETST(B); } |
| 1572 | |
| 1573 | #define j_xx_8(TAKE) \ |
| 1574 | { \ |
| 1575 | if (DSTREG(op)) \ |
| 1576 | { \ |
| 1577 | if (TAKE) \ |
| 1578 | { \ |
| 1579 | m_pc += (PARAM_REL8(op) << 4); \ |
| 1580 | COUNT_CYCLES(2); \ |
| 1581 | } \ |
| 1582 | else \ |
| 1583 | COUNT_CYCLES(1); \ |
| 1584 | } \ |
| 1585 | else \ |
| 1586 | { \ |
| 1587 | if (TAKE) \ |
| 1588 | { \ |
| 1589 | m_pc = PARAM_LONG_NO_INC(); \ |
| 1590 | CORRECT_ODD_PC("J_XX_8"); \ |
| 1591 | COUNT_CYCLES(3); \ |
| 1592 | } \ |
| 1593 | else \ |
| 1594 | { \ |
| 1595 | SKIP_LONG(); \ |
| 1596 | COUNT_CYCLES(4); \ |
| 1597 | } \ |
| 1598 | } \ |
| 1599 | } |
| 1600 | |
| 1601 | #define j_xx_0(TAKE) \ |
| 1602 | { \ |
| 1603 | if (DSTREG(op)) \ |
| 1604 | { \ |
| 1605 | if (TAKE) \ |
| 1606 | { \ |
| 1607 | m_pc += (PARAM_REL8(op) << 4); \ |
| 1608 | COUNT_CYCLES(2); \ |
| 1609 | } \ |
| 1610 | else \ |
| 1611 | COUNT_CYCLES(1); \ |
| 1612 | } \ |
| 1613 | else \ |
| 1614 | { \ |
| 1615 | if (TAKE) \ |
| 1616 | { \ |
| 1617 | m_pc += (PARAM_WORD_NO_INC()<<4)+0x10; \ |
| 1618 | COUNT_CYCLES(3); \ |
| 1619 | } \ |
| 1620 | else \ |
| 1621 | { \ |
| 1622 | SKIP_WORD(); \ |
| 1623 | COUNT_CYCLES(2); \ |
| 1624 | } \ |
| 1625 | } \ |
| 1626 | } |
| 1627 | |
| 1628 | #define j_xx_x(TAKE) \ |
| 1629 | { \ |
| 1630 | if (TAKE) \ |
| 1631 | { \ |
| 1632 | m_pc += (PARAM_REL8(op) << 4); \ |
| 1633 | COUNT_CYCLES(2); \ |
| 1634 | } \ |
| 1635 | else \ |
| 1636 | COUNT_CYCLES(1); \ |
| 1637 | } |
| 1638 | |
| 1639 | void tms340x0_device::j_UC_0(UINT16 op) |
| 1640 | { |
| 1641 | j_xx_0(1); |
| 1642 | } |
| 1643 | void tms340x0_device::j_UC_8(UINT16 op) |
| 1644 | { |
| 1645 | j_xx_8(1); |
| 1646 | } |
| 1647 | void tms340x0_device::j_UC_x(UINT16 op) |
| 1648 | { |
| 1649 | j_xx_x(1); |
| 1650 | } |
| 1651 | void tms340x0_device::j_P_0(UINT16 op) |
| 1652 | { |
| 1653 | j_xx_0(!N_FLAG() && !Z_FLAG()); |
| 1654 | } |
| 1655 | void tms340x0_device::j_P_8(UINT16 op) |
| 1656 | { |
| 1657 | j_xx_8(!N_FLAG() && !Z_FLAG()); |
| 1658 | } |
| 1659 | void tms340x0_device::j_P_x(UINT16 op) |
| 1660 | { |
| 1661 | j_xx_x(!N_FLAG() && !Z_FLAG()); |
| 1662 | } |
| 1663 | void tms340x0_device::j_LS_0(UINT16 op) |
| 1664 | { |
| 1665 | j_xx_0(C_FLAG() || Z_FLAG()); |
| 1666 | } |
| 1667 | void tms340x0_device::j_LS_8(UINT16 op) |
| 1668 | { |
| 1669 | j_xx_8(C_FLAG() || Z_FLAG()); |
| 1670 | } |
| 1671 | void tms340x0_device::j_LS_x(UINT16 op) |
| 1672 | { |
| 1673 | j_xx_x(C_FLAG() || Z_FLAG()); |
| 1674 | } |
| 1675 | void tms340x0_device::j_HI_0(UINT16 op) |
| 1676 | { |
| 1677 | j_xx_0(!C_FLAG() && !Z_FLAG()); |
| 1678 | } |
| 1679 | void tms340x0_device::j_HI_8(UINT16 op) |
| 1680 | { |
| 1681 | j_xx_8(!C_FLAG() && !Z_FLAG()); |
| 1682 | } |
| 1683 | void tms340x0_device::j_HI_x(UINT16 op) |
| 1684 | { |
| 1685 | j_xx_x(!C_FLAG() && !Z_FLAG()); |
| 1686 | } |
| 1687 | void tms340x0_device::j_LT_0(UINT16 op) |
| 1688 | { |
| 1689 | j_xx_0((N_FLAG() && !V_FLAG()) || (!N_FLAG() && V_FLAG())); |
| 1690 | } |
| 1691 | void tms340x0_device::j_LT_8(UINT16 op) |
| 1692 | { |
| 1693 | j_xx_8((N_FLAG() && !V_FLAG()) || (!N_FLAG() && V_FLAG())); |
| 1694 | } |
| 1695 | void tms340x0_device::j_LT_x(UINT16 op) |
| 1696 | { |
| 1697 | j_xx_x((N_FLAG() && !V_FLAG()) || (!N_FLAG() && V_FLAG())); |
| 1698 | } |
| 1699 | void tms340x0_device::j_GE_0(UINT16 op) |
| 1700 | { |
| 1701 | j_xx_0((N_FLAG() && V_FLAG()) || (!N_FLAG() && !V_FLAG())); |
| 1702 | } |
| 1703 | void tms340x0_device::j_GE_8(UINT16 op) |
| 1704 | { |
| 1705 | j_xx_8((N_FLAG() && V_FLAG()) || (!N_FLAG() && !V_FLAG())); |
| 1706 | } |
| 1707 | void tms340x0_device::j_GE_x(UINT16 op) |
| 1708 | { |
| 1709 | j_xx_x((N_FLAG() && V_FLAG()) || (!N_FLAG() && !V_FLAG())); |
| 1710 | } |
| 1711 | void tms340x0_device::j_LE_0(UINT16 op) |
| 1712 | { |
| 1713 | j_xx_0((N_FLAG() && !V_FLAG()) || (!N_FLAG() && V_FLAG()) || Z_FLAG()); |
| 1714 | } |
| 1715 | void tms340x0_device::j_LE_8(UINT16 op) |
| 1716 | { |
| 1717 | j_xx_8((N_FLAG() && !V_FLAG()) || (!N_FLAG() && V_FLAG()) || Z_FLAG()); |
| 1718 | } |
| 1719 | void tms340x0_device::j_LE_x(UINT16 op) |
| 1720 | { |
| 1721 | j_xx_x((N_FLAG() && !V_FLAG()) || (!N_FLAG() && V_FLAG()) || Z_FLAG()); |
| 1722 | } |
| 1723 | void tms340x0_device::j_GT_0(UINT16 op) |
| 1724 | { |
| 1725 | j_xx_0((N_FLAG() && V_FLAG() && !Z_FLAG()) || (!N_FLAG() && !V_FLAG() && !Z_FLAG())); |
| 1726 | } |
| 1727 | void tms340x0_device::j_GT_8(UINT16 op) |
| 1728 | { |
| 1729 | j_xx_8((N_FLAG() && V_FLAG() && !Z_FLAG()) || (!N_FLAG() && !V_FLAG() && !Z_FLAG())); |
| 1730 | } |
| 1731 | void tms340x0_device::j_GT_x(UINT16 op) |
| 1732 | { |
| 1733 | j_xx_x((N_FLAG() && V_FLAG() && !Z_FLAG()) || (!N_FLAG() && !V_FLAG() && !Z_FLAG())); |
| 1734 | } |
| 1735 | void tms340x0_device::j_C_0(UINT16 op) |
| 1736 | { |
| 1737 | j_xx_0(C_FLAG()); |
| 1738 | } |
| 1739 | void tms340x0_device::j_C_8(UINT16 op) |
| 1740 | { |
| 1741 | j_xx_8(C_FLAG()); |
| 1742 | } |
| 1743 | void tms340x0_device::j_C_x(UINT16 op) |
| 1744 | { |
| 1745 | j_xx_x(C_FLAG()); |
| 1746 | } |
| 1747 | void tms340x0_device::j_NC_0(UINT16 op) |
| 1748 | { |
| 1749 | j_xx_0(!C_FLAG()); |
| 1750 | } |
| 1751 | void tms340x0_device::j_NC_8(UINT16 op) |
| 1752 | { |
| 1753 | j_xx_8(!C_FLAG()); |
| 1754 | } |
| 1755 | void tms340x0_device::j_NC_x(UINT16 op) |
| 1756 | { |
| 1757 | j_xx_x(!C_FLAG()); |
| 1758 | } |
| 1759 | void tms340x0_device::j_EQ_0(UINT16 op) |
| 1760 | { |
| 1761 | j_xx_0(Z_FLAG()); |
| 1762 | } |
| 1763 | void tms340x0_device::j_EQ_8(UINT16 op) |
| 1764 | { |
| 1765 | j_xx_8(Z_FLAG()); |
| 1766 | } |
| 1767 | void tms340x0_device::j_EQ_x(UINT16 op) |
| 1768 | { |
| 1769 | j_xx_x(Z_FLAG()); |
| 1770 | } |
| 1771 | void tms340x0_device::j_NE_0(UINT16 op) |
| 1772 | { |
| 1773 | j_xx_0(!Z_FLAG()); |
| 1774 | } |
| 1775 | void tms340x0_device::j_NE_8(UINT16 op) |
| 1776 | { |
| 1777 | j_xx_8(!Z_FLAG()); |
| 1778 | } |
| 1779 | void tms340x0_device::j_NE_x(UINT16 op) |
| 1780 | { |
| 1781 | j_xx_x(!Z_FLAG()); |
| 1782 | } |
| 1783 | void tms340x0_device::j_V_0(UINT16 op) |
| 1784 | { |
| 1785 | j_xx_0(V_FLAG()); |
| 1786 | } |
| 1787 | void tms340x0_device::j_V_8(UINT16 op) |
| 1788 | { |
| 1789 | j_xx_8(V_FLAG()); |
| 1790 | } |
| 1791 | void tms340x0_device::j_V_x(UINT16 op) |
| 1792 | { |
| 1793 | j_xx_x(V_FLAG()); |
| 1794 | } |
| 1795 | void tms340x0_device::j_NV_0(UINT16 op) |
| 1796 | { |
| 1797 | j_xx_0(!V_FLAG()); |
| 1798 | } |
| 1799 | void tms340x0_device::j_NV_8(UINT16 op) |
| 1800 | { |
| 1801 | j_xx_8(!V_FLAG()); |
| 1802 | } |
| 1803 | void tms340x0_device::j_NV_x(UINT16 op) |
| 1804 | { |
| 1805 | j_xx_x(!V_FLAG()); |
| 1806 | } |
| 1807 | void tms340x0_device::j_N_0(UINT16 op) |
| 1808 | { |
| 1809 | j_xx_0(N_FLAG()); |
| 1810 | } |
| 1811 | void tms340x0_device::j_N_8(UINT16 op) |
| 1812 | { |
| 1813 | j_xx_8(N_FLAG()); |
| 1814 | } |
| 1815 | void tms340x0_device::j_N_x(UINT16 op) |
| 1816 | { |
| 1817 | j_xx_x(N_FLAG()); |
| 1818 | } |
| 1819 | void tms340x0_device::j_NN_0(UINT16 op) |
| 1820 | { |
| 1821 | j_xx_0(!N_FLAG()); |
| 1822 | } |
| 1823 | void tms340x0_device::j_NN_8(UINT16 op) |
| 1824 | { |
| 1825 | j_xx_8(!N_FLAG()); |
| 1826 | } |
| 1827 | void tms340x0_device::j_NN_x(UINT16 op) |
| 1828 | { |
| 1829 | j_xx_x(!N_FLAG()); |
| 1830 | } |
| 1831 | |
| 1832 | #define JUMP(R) \ |
| 1833 | { \ |
| 1834 | m_pc = R##REG(DSTREG(op)); \ |
| 1835 | CORRECT_ODD_PC("JUMP"); \ |
| 1836 | COUNT_CYCLES(2); \ |
| 1837 | } |
| 1838 | void tms340x0_device::jump_a (UINT16 op) { JUMP(A); } |
| 1839 | void tms340x0_device::jump_b (UINT16 op) { JUMP(B); } |
| 1840 | |
| 1841 | void tms340x0_device::popst(UINT16 op) |
| 1842 | { |
| 1843 | SET_ST(POP()); |
| 1844 | COUNT_CYCLES(8); |
| 1845 | } |
| 1846 | |
| 1847 | void tms340x0_device::pushst(UINT16 op) |
| 1848 | { |
| 1849 | PUSH(m_st); |
| 1850 | COUNT_CYCLES(2); |
| 1851 | } |
| 1852 | |
| 1853 | #define PUTST(R) \ |
| 1854 | { \ |
| 1855 | SET_ST(R##REG(DSTREG(op))); \ |
| 1856 | COUNT_CYCLES(3); \ |
| 1857 | } |
| 1858 | void tms340x0_device::putst_a (UINT16 op) { PUTST(A); } |
| 1859 | void tms340x0_device::putst_b (UINT16 op) { PUTST(B); } |
| 1860 | |
| 1861 | void tms340x0_device::reti(UINT16 op) |
| 1862 | { |
| 1863 | INT32 st = POP(); |
| 1864 | m_pc = POP(); |
| 1865 | CORRECT_ODD_PC("RETI"); |
| 1866 | SET_ST(st); |
| 1867 | COUNT_CYCLES(11); |
| 1868 | } |
| 1869 | |
| 1870 | void tms340x0_device::rets(UINT16 op) |
| 1871 | { |
| 1872 | UINT32 offs; |
| 1873 | m_pc = POP(); |
| 1874 | CORRECT_ODD_PC("RETS"); |
| 1875 | offs = PARAM_N(op); |
| 1876 | if (offs) |
| 1877 | { |
| 1878 | SP()+=(offs<<4); |
| 1879 | } |
| 1880 | COUNT_CYCLES(7); |
| 1881 | } |
| 1882 | |
| 1883 | #define REV(R) \ |
| 1884 | { \ |
| 1885 | R##REG(DSTREG(op)) = 0x0008; \ |
| 1886 | COUNT_CYCLES(1); \ |
| 1887 | } |
| 1888 | void tms340x0_device::rev_a (UINT16 op) { REV(A); } |
| 1889 | void tms340x0_device::rev_b (UINT16 op) { REV(B); } |
| 1890 | |
| 1891 | void tms340x0_device::trap(UINT16 op) |
| 1892 | { |
| 1893 | UINT32 t = PARAM_N(op); |
| 1894 | if (t) |
| 1895 | { |
| 1896 | PUSH(m_pc); |
| 1897 | PUSH(m_st); |
| 1898 | } |
| 1899 | RESET_ST(); |
| 1900 | m_pc = RLONG(0xffffffe0-(t<<5)); |
| 1901 | CORRECT_ODD_PC("TRAP"); |
| 1902 | COUNT_CYCLES(16); |
| 1903 | } |
| 1904 | |
| 1905 | |
| 1906 | |
| 1907 | /*************************************************************************** |
| 1908 | 34020 INSTRUCTIONS |
| 1909 | ***************************************************************************/ |
| 1910 | |
| 1911 | /************************************ |
| 1912 | |
| 1913 | New 34020 ops: |
| 1914 | |
| 1915 | 0000 1100 000R dddd = ADDXYI IL,Rd |
| 1916 | iiii iiii iiii iiii |
| 1917 | iiii iiii iiii iiii |
| 1918 | |
| 1919 | 0000 0000 1111 00SD = BLMOVE S,D |
| 1920 | |
| 1921 | 0000 0110 0000 0000 = CEXEC S,c,ID,L |
| 1922 | cccc cccc S000 0000 |
| 1923 | iiic cccc cccc cccc |
| 1924 | |
| 1925 | 1101 1000 0ccc cccS = CEXEC S,c,ID |
| 1926 | iiic cccc cccc cccc |
| 1927 | |
| 1928 | 0000 1000 1111 0010 = CLIP |
| 1929 | |
| 1930 | 0000 0110 011R dddd = CMOVCG Rd1,Rd2,S,c,ID |
| 1931 | cccc cccc S00R dddd |
| 1932 | iiic cccc cccc cccc |
| 1933 | |
| 1934 | 0000 0110 101R dddd = CMOVCM *Rd+,n,S,c,ID |
| 1935 | cccc cccc S00n nnnn |
| 1936 | iiic cccc cccc cccc |
| 1937 | |
| 1938 | 0000 0110 110R dddd = CMOVCM -*Rd,n,S,c,ID |
| 1939 | cccc cccc S00n nnnn |
| 1940 | iiic cccc cccc cccc |
| 1941 | |
| 1942 | 0000 0110 0110 0000 = CMOVCS c,ID |
| 1943 | cccc cccc 0000 0001 |
| 1944 | iiic cccc cccc cccc |
| 1945 | |
| 1946 | 0000 0110 001R ssss = CMOVGC Rs,c,ID |
| 1947 | cccc cccc 0000 0000 |
| 1948 | iiic cccc cccc cccc |
| 1949 | |
| 1950 | 0000 0110 010R ssss = CMOVGC Rs1,Rs2,S,c,ID |
| 1951 | cccc cccc S00R ssss |
| 1952 | iiic cccc cccc cccc |
| 1953 | |
| 1954 | 0000 0110 100n nnnn = CMOVMC *Rs+,n,S,c,ID |
| 1955 | cccc cccc S00R ssss |
| 1956 | iiic cccc cccc cccc |
| 1957 | |
| 1958 | 0000 1000 001n nnnn = CMOVMC -*Rs,n,S,c,ID |
| 1959 | cccc cccc S00R ssss |
| 1960 | iiic cccc cccc cccc |
| 1961 | |
| 1962 | 0000 0110 111R dddd = CMOVMC *Rs+,Rd,S,c,ID |
| 1963 | cccc cccc S00R ssss |
| 1964 | iiic cccc cccc cccc |
| 1965 | |
| 1966 | 0011 01kk kkkR dddd = CMPK k,Rd |
| 1967 | |
| 1968 | 0000 1010 100R dddd = CVDXYL Rd |
| 1969 | |
| 1970 | 0000 1010 011R dddd = CVMXYL Rd |
| 1971 | |
| 1972 | 1110 101s sssR dddd = CVSXYL Rs,Rd |
| 1973 | |
| 1974 | 0000 0010 101R dddd = EXGPS Rd |
| 1975 | |
| 1976 | 1101 1110 Z001 1010 = FLINE Z |
| 1977 | |
| 1978 | 0000 1010 1011 1011 = FPIXEQ |
| 1979 | |
| 1980 | 0000 1010 1101 1011 = FPIXNE |
| 1981 | |
| 1982 | 0000 0010 110R dddd = GETPS Rd |
| 1983 | |
| 1984 | 0000 0000 0100 0000 = IDLE |
| 1985 | |
| 1986 | 0000 1100 0101 0111 = LINIT |
| 1987 | |
| 1988 | 0000 0000 1000 0000 = MWAIT |
| 1989 | |
| 1990 | 0000 1010 0011 0111 = PFILL XY |
| 1991 | |
| 1992 | 0000 1110 0001 0111 = PIXBLT L,M,L |
| 1993 | |
| 1994 | 0000 1000 0110 0000 = RETM |
| 1995 | |
| 1996 | 0111 101s sssR dddd = RMO Rs,Rd |
| 1997 | |
| 1998 | 0000 0010 100R dddd = RPIX Rd |
| 1999 | |
| 2000 | 0000 0010 0111 0011 = SETCDP |
| 2001 | |
| 2002 | 0000 0010 1111 1011 = SETCMP |
| 2003 | |
| 2004 | 0000 0010 0101 0001 = SETCSP |
| 2005 | |
| 2006 | 0111 111s sssR dddd = SWAPF *Rs,Rd,0 |
| 2007 | |
| 2008 | 0000 1110 1111 1010 = TFILL XY |
| 2009 | |
| 2010 | 0000 1000 0000 1111 = TRAPL |
| 2011 | |
| 2012 | 0000 1000 0101 0111 = VBLT B,L |
| 2013 | |
| 2014 | 0000 1010 0101 0111 = VFILL L |
| 2015 | |
| 2016 | 0000 1010 0000 0000 = VLCOL |
| 2017 | |
| 2018 | ************************************/ |
| 2019 | |
| 2020 | |
| 2021 | #define ADD_XYI(R) \ |
| 2022 | { \ |
| 2023 | UINT32 a = PARAM_LONG(); \ |
| 2024 | XY *b = &R##REG_XY(DSTREG(op)); \ |
| 2025 | CLR_NCZV(); \ |
| 2026 | b->x += (INT16)(a & 0xffff); \ |
| 2027 | b->y += ((INT32)a >> 16); \ |
| 2028 | SET_N_LOG(b->x == 0); \ |
| 2029 | SET_C_BIT_LO(b->y, 15); \ |
| 2030 | SET_Z_LOG(b->y == 0); \ |
| 2031 | SET_V_BIT_LO(b->x, 15); \ |
| 2032 | COUNT_CYCLES(1); \ |
| 2033 | } |
| 2034 | void tms340x0_device::addxyi_a(UINT16 op) |
| 2035 | { |
| 2036 | if (!m_is_34020) { unimpl(op); return; } |
| 2037 | ADD_XYI(A); |
| 2038 | } |
| 2039 | void tms340x0_device::addxyi_b(UINT16 op) |
| 2040 | { |
| 2041 | if (!m_is_34020) { unimpl(op); return; } |
| 2042 | ADD_XYI(B); |
| 2043 | } |
| 2044 | |
| 2045 | void tms340x0_device::blmove(UINT16 op) |
| 2046 | { |
| 2047 | offs_t src = BREG(0); |
| 2048 | offs_t dst = BREG(2); |
| 2049 | offs_t bits = BREG(7); |
| 2050 | |
| 2051 | if (!m_is_34020) { unimpl(op); return; } |
| 2052 | |
| 2053 | /* src and dst are aligned */ |
| 2054 | if (!(src & 0x0f) && !(dst & 0x0f)) |
| 2055 | { |
| 2056 | while (bits >= 16 && m_icount > 0) |
| 2057 | { |
| 2058 | TMS34010_WRMEM_WORD(TOBYTE(dst), TMS34010_RDMEM_WORD(TOBYTE(src))); |
| 2059 | src += 0x10; |
| 2060 | dst += 0x10; |
| 2061 | bits -= 0x10; |
| 2062 | m_icount -= 2; |
| 2063 | } |
| 2064 | if (bits != 0 && m_icount > 0) |
| 2065 | { |
| 2066 | (this->*s_wfield_functions[bits])(dst, (this->*s_rfield_functions[bits])(src)); |
| 2067 | dst += bits; |
| 2068 | src += bits; |
| 2069 | bits = 0; |
| 2070 | m_icount -= 2; |
| 2071 | } |
| 2072 | } |
| 2073 | |
| 2074 | /* src is aligned, dst is not */ |
| 2075 | else if (!(src & 0x0f)) |
| 2076 | { |
| 2077 | logerror("020:BLMOVE with aligned src and unaligned dst\n"); |
| 2078 | } |
| 2079 | |
| 2080 | /* dst is aligned, src is not */ |
| 2081 | else if (!(dst & 0x0f)) |
| 2082 | { |
| 2083 | logerror("020:BLMOVE with unaligned src and aligned dst\n"); |
| 2084 | } |
| 2085 | |
| 2086 | /* neither are aligned */ |
| 2087 | else |
| 2088 | { |
| 2089 | logerror("020:BLMOVE with completely unaligned src and dst\n"); |
| 2090 | } |
| 2091 | |
| 2092 | /* update the final results */ |
| 2093 | BREG(0) = src; |
| 2094 | BREG(2) = dst; |
| 2095 | BREG(7) = bits; |
| 2096 | |
| 2097 | /* if we're not done yet, back up the PC */ |
| 2098 | if (bits != 0) |
| 2099 | m_pc -= 0x10; |
| 2100 | } |
| 2101 | |
| 2102 | void tms340x0_device::cexec_l(UINT16 op) |
| 2103 | { |
| 2104 | if (!m_is_34020) { unimpl(op); return; } |
| 2105 | logerror("020:cexec_l\n"); |
| 2106 | } |
| 2107 | |
| 2108 | void tms340x0_device::cexec_s(UINT16 op) |
| 2109 | { |
| 2110 | if (!m_is_34020) { unimpl(op); return; } |
| 2111 | logerror("020:cexec_s\n"); |
| 2112 | } |
| 2113 | |
| 2114 | void tms340x0_device::clip(UINT16 op) |
| 2115 | { |
| 2116 | if (!m_is_34020) { unimpl(op); return; } |
| 2117 | logerror("020:clip\n"); |
| 2118 | } |
| 2119 | |
| 2120 | void tms340x0_device::cmovcg_a(UINT16 op) |
| 2121 | { |
| 2122 | if (!m_is_34020) { unimpl(op); return; } |
| 2123 | logerror("020:cmovcg_a\n"); |
| 2124 | } |
| 2125 | |
| 2126 | void tms340x0_device::cmovcg_b(UINT16 op) |
| 2127 | { |
| 2128 | if (!m_is_34020) { unimpl(op); return; } |
| 2129 | logerror("020:cmovcg_b\n"); |
| 2130 | } |
| 2131 | |
| 2132 | void tms340x0_device::cmovcm_f(UINT16 op) |
| 2133 | { |
| 2134 | if (!m_is_34020) { unimpl(op); return; } |
| 2135 | logerror("020:cmovcm_f\n"); |
| 2136 | } |
| 2137 | |
| 2138 | void tms340x0_device::cmovcm_b(UINT16 op) |
| 2139 | { |
| 2140 | if (!m_is_34020) { unimpl(op); return; } |
| 2141 | logerror("020:cmovcm_b\n"); |
| 2142 | } |
| 2143 | |
| 2144 | void tms340x0_device::cmovgc_a(UINT16 op) |
| 2145 | { |
| 2146 | if (!m_is_34020) { unimpl(op); return; } |
| 2147 | logerror("020:cmovgc_a\n"); |
| 2148 | } |
| 2149 | |
| 2150 | void tms340x0_device::cmovgc_b(UINT16 op) |
| 2151 | { |
| 2152 | if (!m_is_34020) { unimpl(op); return; } |
| 2153 | logerror("020:cmovgc_b\n"); |
| 2154 | } |
| 2155 | |
| 2156 | void tms340x0_device::cmovgc_a_s(UINT16 op) |
| 2157 | { |
| 2158 | if (!m_is_34020) { unimpl(op); return; } |
| 2159 | logerror("020:cmovgc_a_s\n"); |
| 2160 | } |
| 2161 | |
| 2162 | void tms340x0_device::cmovgc_b_s(UINT16 op) |
| 2163 | { |
| 2164 | if (!m_is_34020) { unimpl(op); return; } |
| 2165 | logerror("020:cmovgc_b_s\n"); |
| 2166 | } |
| 2167 | |
| 2168 | void tms340x0_device::cmovmc_f(UINT16 op) |
| 2169 | { |
| 2170 | if (!m_is_34020) { unimpl(op); return; } |
| 2171 | logerror("020:cmovmc_f\n"); |
| 2172 | } |
| 2173 | |
| 2174 | void tms340x0_device::cmovmc_f_va(UINT16 op) |
| 2175 | { |
| 2176 | if (!m_is_34020) { unimpl(op); return; } |
| 2177 | logerror("020:cmovmc_f_va\n"); |
| 2178 | } |
| 2179 | |
| 2180 | void tms340x0_device::cmovmc_f_vb(UINT16 op) |
| 2181 | { |
| 2182 | if (!m_is_34020) { unimpl(op); return; } |
| 2183 | logerror("020:cmovmc_f_vb\n"); |
| 2184 | } |
| 2185 | |
| 2186 | void tms340x0_device::cmovmc_b(UINT16 op) |
| 2187 | { |
| 2188 | if (!m_is_34020) { unimpl(op); return; } |
| 2189 | logerror("020:cmovmc_b\n"); |
| 2190 | } |
| 2191 | |
| 2192 | #define CMPK(R) \ |
| 2193 | { \ |
| 2194 | INT32 r; \ |
| 2195 | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 2196 | INT32 t = PARAM_K(op); if (!t) t = 32; \ |
| 2197 | CLR_NCZV(); \ |
| 2198 | r = *rd - t; \ |
| 2199 | SET_NZCV_SUB(*rd,t,r); \ |
| 2200 | COUNT_CYCLES(1); \ |
| 2201 | } |
| 2202 | void tms340x0_device::cmp_k_a(UINT16 op) |
| 2203 | { |
| 2204 | if (!m_is_34020) { unimpl(op); return; } |
| 2205 | CMPK(A); |
| 2206 | } |
| 2207 | void tms340x0_device::cmp_k_b(UINT16 op) |
| 2208 | { |
| 2209 | if (!m_is_34020) { unimpl(op); return; } |
| 2210 | CMPK(B); |
| 2211 | } |
| 2212 | |
| 2213 | void tms340x0_device::cvdxyl_a(UINT16 op) |
| 2214 | { |
| 2215 | if (!m_is_34020) { unimpl(op); return; } |
| 2216 | logerror("020:cvdxyl_a\n"); |
| 2217 | } |
| 2218 | |
| 2219 | void tms340x0_device::cvdxyl_b(UINT16 op) |
| 2220 | { |
| 2221 | if (!m_is_34020) { unimpl(op); return; } |
| 2222 | logerror("020:cvdxyl_b\n"); |
| 2223 | } |
| 2224 | |
| 2225 | void tms340x0_device::cvmxyl_a(UINT16 op) |
| 2226 | { |
| 2227 | if (!m_is_34020) { unimpl(op); return; } |
| 2228 | logerror("020:cvmxyl_a\n"); |
| 2229 | } |
| 2230 | |
| 2231 | void tms340x0_device::cvmxyl_b(UINT16 op) |
| 2232 | { |
| 2233 | if (!m_is_34020) { unimpl(op); return; } |
| 2234 | logerror("020:cvmxyl_b\n"); |
| 2235 | } |
| 2236 | |
| 2237 | void tms340x0_device::cvsxyl_a(UINT16 op) |
| 2238 | { |
| 2239 | if (!m_is_34020) { unimpl(op); return; } |
| 2240 | logerror("020:cvsxyl_a\n"); |
| 2241 | } |
| 2242 | |
| 2243 | void tms340x0_device::cvsxyl_b(UINT16 op) |
| 2244 | { |
| 2245 | if (!m_is_34020) { unimpl(op); return; } |
| 2246 | logerror("020:cvsxyl_b\n"); |
| 2247 | } |
| 2248 | |
| 2249 | void tms340x0_device::exgps_a(UINT16 op) |
| 2250 | { |
| 2251 | if (!m_is_34020) { unimpl(op); return; } |
| 2252 | logerror("020:exgps_a\n"); |
| 2253 | } |
| 2254 | |
| 2255 | void tms340x0_device::exgps_b(UINT16 op) |
| 2256 | { |
| 2257 | if (!m_is_34020) { unimpl(op); return; } |
| 2258 | logerror("020:exgps_b\n"); |
| 2259 | } |
| 2260 | |
| 2261 | void tms340x0_device::fline(UINT16 op) |
| 2262 | { |
| 2263 | if (!m_is_34020) { unimpl(op); return; } |
| 2264 | logerror("020:fline\n"); |
| 2265 | } |
| 2266 | |
| 2267 | void tms340x0_device::fpixeq(UINT16 op) |
| 2268 | { |
| 2269 | if (!m_is_34020) { unimpl(op); return; } |
| 2270 | logerror("020:fpixeq\n"); |
| 2271 | } |
| 2272 | |
| 2273 | void tms340x0_device::fpixne(UINT16 op) |
| 2274 | { |
| 2275 | if (!m_is_34020) { unimpl(op); return; } |
| 2276 | logerror("020:fpixne\n"); |
| 2277 | } |
| 2278 | |
| 2279 | void tms340x0_device::getps_a(UINT16 op) |
| 2280 | { |
| 2281 | if (!m_is_34020) { unimpl(op); return; } |
| 2282 | logerror("020:getps_a\n"); |
| 2283 | } |
| 2284 | |
| 2285 | void tms340x0_device::getps_b(UINT16 op) |
| 2286 | { |
| 2287 | if (!m_is_34020) { unimpl(op); return; } |
| 2288 | logerror("020:getps_b\n"); |
| 2289 | } |
| 2290 | |
| 2291 | void tms340x0_device::idle(UINT16 op) |
| 2292 | { |
| 2293 | if (!m_is_34020) { unimpl(op); return; } |
| 2294 | logerror("020:idle\n"); |
| 2295 | } |
| 2296 | |
| 2297 | void tms340x0_device::linit(UINT16 op) |
| 2298 | { |
| 2299 | if (!m_is_34020) { unimpl(op); return; } |
| 2300 | logerror("020:linit\n"); |
| 2301 | } |
| 2302 | |
| 2303 | void tms340x0_device::mwait(UINT16 op) |
| 2304 | { |
| 2305 | if (!m_is_34020) { unimpl(op); return; } |
| 2306 | } |
| 2307 | |
| 2308 | void tms340x0_device::pfill_xy(UINT16 op) |
| 2309 | { |
| 2310 | if (!m_is_34020) { unimpl(op); return; } |
| 2311 | logerror("020:pfill_xy\n"); |
| 2312 | } |
| 2313 | |
| 2314 | void tms340x0_device::pixblt_l_m_l(UINT16 op) |
| 2315 | { |
| 2316 | if (!m_is_34020) { unimpl(op); return; } |
| 2317 | logerror("020:pixblt_l_m_l\n"); |
| 2318 | } |
| 2319 | |
| 2320 | void tms340x0_device::retm(UINT16 op) |
| 2321 | { |
| 2322 | if (!m_is_34020) { unimpl(op); return; } |
| 2323 | logerror("020:retm\n"); |
| 2324 | } |
| 2325 | |
| 2326 | #define RMO(R) \ |
| 2327 | { \ |
| 2328 | UINT32 res = 0; \ |
| 2329 | UINT32 rs = R##REG(SRCREG(op)); \ |
| 2330 | INT32 *rd = &R##REG(DSTREG(op)); \ |
| 2331 | CLR_Z(); \ |
| 2332 | SET_Z_VAL(rs); \ |
| 2333 | if (rs) \ |
| 2334 | { \ |
| 2335 | while (!(rs & 0x00000001)) \ |
| 2336 | { \ |
| 2337 | res++; \ |
| 2338 | rs >>= 1; \ |
| 2339 | } \ |
| 2340 | } \ |
| 2341 | *rd = res; \ |
| 2342 | COUNT_CYCLES(1); \ |
| 2343 | } |
| 2344 | |
| 2345 | void tms340x0_device::rmo_a(UINT16 op) { RMO(A); } |
| 2346 | void tms340x0_device::rmo_b(UINT16 op) { RMO(B); } |
| 2347 | |
| 2348 | #define RPIX(R) \ |
| 2349 | { \ |
| 2350 | UINT32 v = R##REG(DSTREG(op)); \ |
| 2351 | switch (m_pixelshift) \ |
| 2352 | { \ |
| 2353 | case 0: \ |
| 2354 | v = (v & 1) ? 0xffffffff : 0x00000000;\ |
| 2355 | COUNT_CYCLES(8); \ |
| 2356 | break; \ |
| 2357 | case 1: \ |
| 2358 | v &= 3; \ |
| 2359 | v |= v << 2; \ |
| 2360 | v |= v << 4; \ |
| 2361 | v |= v << 8; \ |
| 2362 | v |= v << 16; \ |
| 2363 | COUNT_CYCLES(7); \ |
| 2364 | break; \ |
| 2365 | case 2: \ |
| 2366 | v &= 0x0f; \ |
| 2367 | v |= v << 4; \ |
| 2368 | v |= v << 8; \ |
| 2369 | v |= v << 16; \ |
| 2370 | COUNT_CYCLES(6); \ |
| 2371 | break; \ |
| 2372 | case 3: \ |
| 2373 | v &= 0xff; \ |
| 2374 | v |= v << 8; \ |
| 2375 | v |= v << 16; \ |
| 2376 | COUNT_CYCLES(5); \ |
| 2377 | break; \ |
| 2378 | case 4: \ |
| 2379 | v &= 0xffff; \ |
| 2380 | v |= v << 16; \ |
| 2381 | COUNT_CYCLES(4); \ |
| 2382 | break; \ |
| 2383 | case 5: \ |
| 2384 | COUNT_CYCLES(2); \ |
| 2385 | break; \ |
| 2386 | } \ |
| 2387 | R##REG(DSTREG(op)) = v; \ |
| 2388 | } |
| 2389 | |
| 2390 | void tms340x0_device::rpix_a(UINT16 op) |
| 2391 | { |
| 2392 | if (!m_is_34020) { unimpl(op); return; } |
| 2393 | RPIX(A); |
| 2394 | } |
| 2395 | |
| 2396 | void tms340x0_device::rpix_b(UINT16 op) |
| 2397 | { |
| 2398 | if (!m_is_34020) { unimpl(op); return; } |
| 2399 | RPIX(B); |
| 2400 | } |
| 2401 | |
| 2402 | void tms340x0_device::setcdp(UINT16 op) |
| 2403 | { |
| 2404 | if (!m_is_34020) { unimpl(op); return; } |
| 2405 | logerror("020:setcdp\n"); |
| 2406 | } |
| 2407 | |
| 2408 | void tms340x0_device::setcmp(UINT16 op) |
| 2409 | { |
| 2410 | if (!m_is_34020) { unimpl(op); return; } |
| 2411 | logerror("020:setcmp\n"); |
| 2412 | } |
| 2413 | |
| 2414 | void tms340x0_device::setcsp(UINT16 op) |
| 2415 | { |
| 2416 | if (!m_is_34020) { unimpl(op); return; } |
| 2417 | logerror("020:setcsp\n"); |
| 2418 | } |
| 2419 | |
| 2420 | void tms340x0_device::swapf_a(UINT16 op) |
| 2421 | { |
| 2422 | if (!m_is_34020) { unimpl(op); return; } |
| 2423 | logerror("020:swapf_a\n"); |
| 2424 | } |
| 2425 | |
| 2426 | void tms340x0_device::swapf_b(UINT16 op) |
| 2427 | { |
| 2428 | if (!m_is_34020) { unimpl(op); return; } |
| 2429 | logerror("020:swapf_b\n"); |
| 2430 | } |
| 2431 | |
| 2432 | void tms340x0_device::tfill_xy(UINT16 op) |
| 2433 | { |
| 2434 | if (!m_is_34020) { unimpl(op); return; } |
| 2435 | logerror("020:tfill_xy\n"); |
| 2436 | } |
| 2437 | |
| 2438 | void tms340x0_device::trapl(UINT16 op) |
| 2439 | { |
| 2440 | if (!m_is_34020) { unimpl(op); return; } |
| 2441 | logerror("020:trapl\n"); |
| 2442 | } |
| 2443 | |
| 2444 | void tms340x0_device::vblt_b_l(UINT16 op) |
| 2445 | { |
| 2446 | if (!m_is_34020) { unimpl(op); return; } |
| 2447 | logerror("020:vblt_b_l\n"); |
| 2448 | } |
| 2449 | |
| 2450 | void tms340x0_device::vfill_l(UINT16 op) |
| 2451 | { |
| 2452 | if (!m_is_34020) { unimpl(op); return; } |
| 2453 | logerror("020:vfill_l\n"); |
| 2454 | } |
| 2455 | |
| 2456 | void tms340x0_device::vlcol(UINT16 op) |
| 2457 | { |
| 2458 | if (!m_is_34020) { unimpl(op); return; } |
| 2459 | logerror("020:vlcol\n"); |
| 2460 | } |
trunk/src/devices/cpu/tms34010/34010tbl.cpp
| r250221 | r250222 | |
|---|
| 1 | | // license:BSD-3-Clause |
| 2 | | // copyright-holders:Alex Pasadyn,Zsolt Vasvari |
| 3 | | /*** TMS34010: Portable TMS34010 emulator *********************************** |
| 4 | | |
| 5 | | Copyright Alex Pasadyn/Zsolt Vasvari |
| 6 | | |
| 7 | | Opcode Table |
| 8 | | |
| 9 | | *****************************************************************************/ |
| 10 | | |
| 11 | | /* Opcode Table */ |
| 12 | | const tms340x0_device::opcode_func tms340x0_device::s_opcode_table[65536 >> 4] = |
| 13 | | { |
| 14 | | /* 0x0000 0x0010 0x0020 0x0030 ... 0x00f0 */ |
| 15 | | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::rev_a, &tms340x0_device::rev_b, &tms340x0_device::idle, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 16 | | &tms340x0_device::mwait, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::blmove, |
| 17 | | /* 0x0100 */ |
| 18 | | &tms340x0_device::emu, &tms340x0_device::unimpl, &tms340x0_device::exgpc_a, &tms340x0_device::exgpc_b, &tms340x0_device::getpc_a, &tms340x0_device::getpc_b, &tms340x0_device::jump_a, &tms340x0_device::jump_b, |
| 19 | | &tms340x0_device::getst_a, &tms340x0_device::getst_b, &tms340x0_device::putst_a, &tms340x0_device::putst_b, &tms340x0_device::popst, &tms340x0_device::unimpl, &tms340x0_device::pushst, &tms340x0_device::unimpl, |
| 20 | | /* 0x0200 */ |
| 21 | | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::setcsp, &tms340x0_device::unimpl, &tms340x0_device::setcdp, |
| 22 | | &tms340x0_device::rpix_a, &tms340x0_device::rpix_b, &tms340x0_device::exgps_a, &tms340x0_device::exgps_b, &tms340x0_device::getps_a, &tms340x0_device::getps_b, &tms340x0_device::unimpl, &tms340x0_device::setcmp, |
| 23 | | /* 0x0300 */ |
| 24 | | &tms340x0_device::nop, &tms340x0_device::unimpl, &tms340x0_device::clrc, &tms340x0_device::unimpl, &tms340x0_device::movb_aa, &tms340x0_device::unimpl, &tms340x0_device::dint, &tms340x0_device::unimpl, |
| 25 | | &tms340x0_device::abs_a, &tms340x0_device::abs_b, &tms340x0_device::neg_a, &tms340x0_device::neg_b, &tms340x0_device::negb_a, &tms340x0_device::negb_b, &tms340x0_device::not_a, &tms340x0_device::not_b, |
| 26 | | /* 0x0400 */ |
| 27 | | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 28 | | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 29 | | /* 0x0500 */ |
| 30 | | &tms340x0_device::sext0_a, &tms340x0_device::sext0_b, &tms340x0_device::zext0_a, &tms340x0_device::zext0_b, &tms340x0_device::setf0, &tms340x0_device::setf0, &tms340x0_device::setf0, &tms340x0_device::setf0, |
| 31 | | &tms340x0_device::move0_ra_a, &tms340x0_device::move0_ra_b, &tms340x0_device::move0_ar_a, &tms340x0_device::move0_ar_b, &tms340x0_device::move0_aa, &tms340x0_device::unimpl, &tms340x0_device::movb_ra_a, &tms340x0_device::movb_ra_b, |
| 32 | | /* 0x0600 */ |
| 33 | | &tms340x0_device::cexec_l, &tms340x0_device::unimpl, &tms340x0_device::cmovgc_a, &tms340x0_device::cmovgc_b, &tms340x0_device::cmovgc_a_s, &tms340x0_device::cmovgc_b_s, &tms340x0_device::cmovcg_a, &tms340x0_device::cmovcg_b, |
| 34 | | &tms340x0_device::cmovmc_f, &tms340x0_device::cmovmc_f, &tms340x0_device::cmovcm_f, &tms340x0_device::cmovcm_f, &tms340x0_device::cmovcm_b, &tms340x0_device::cmovcm_b, &tms340x0_device::cmovmc_f_va,&tms340x0_device::cmovmc_f_vb, |
| 35 | | /* 0x0700 */ |
| 36 | | &tms340x0_device::sext1_a, &tms340x0_device::sext1_b, &tms340x0_device::zext1_a, &tms340x0_device::zext1_b, &tms340x0_device::setf1, &tms340x0_device::setf1, &tms340x0_device::setf1, &tms340x0_device::setf1, |
| 37 | | &tms340x0_device::move1_ra_a, &tms340x0_device::move1_ra_b, &tms340x0_device::move1_ar_a, &tms340x0_device::move1_ar_b, &tms340x0_device::move1_aa, &tms340x0_device::unimpl, &tms340x0_device::movb_ar_a, &tms340x0_device::movb_ar_b, |
| 38 | | /* 0x0800 */ |
| 39 | | &tms340x0_device::trapl, &tms340x0_device::unimpl, &tms340x0_device::cmovmc_b, &tms340x0_device::cmovmc_b, &tms340x0_device::unimpl, &tms340x0_device::vblt_b_l, &tms340x0_device::retm, &tms340x0_device::unimpl, |
| 40 | | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::clip, |
| 41 | | /* 0x0900 */ |
| 42 | | &tms340x0_device::trap, &tms340x0_device::trap, &tms340x0_device::call_a, &tms340x0_device::call_b, &tms340x0_device::reti, &tms340x0_device::unimpl, &tms340x0_device::rets, &tms340x0_device::rets, |
| 43 | | &tms340x0_device::mmtm_a, &tms340x0_device::mmtm_b, &tms340x0_device::mmfm_a, &tms340x0_device::mmfm_b, &tms340x0_device::movi_w_a, &tms340x0_device::movi_w_b, &tms340x0_device::movi_l_a, &tms340x0_device::movi_l_b, |
| 44 | | /* 0x0a00 */ |
| 45 | | &tms340x0_device::vlcol, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::pfill_xy, &tms340x0_device::unimpl, &tms340x0_device::vfill_l, &tms340x0_device::cvmxyl_a, &tms340x0_device::cvmxyl_b, |
| 46 | | &tms340x0_device::cvdxyl_a, &tms340x0_device::cvdxyl_b, &tms340x0_device::unimpl, &tms340x0_device::fpixeq, &tms340x0_device::unimpl, &tms340x0_device::fpixne, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 47 | | /* 0x0b00 */ |
| 48 | | &tms340x0_device::addi_w_a, &tms340x0_device::addi_w_b, &tms340x0_device::addi_l_a, &tms340x0_device::addi_l_b, &tms340x0_device::cmpi_w_a, &tms340x0_device::cmpi_w_b, &tms340x0_device::cmpi_l_a, &tms340x0_device::cmpi_l_b, |
| 49 | | &tms340x0_device::andi_a, &tms340x0_device::andi_b, &tms340x0_device::ori_a, &tms340x0_device::ori_b, &tms340x0_device::xori_a, &tms340x0_device::xori_b, &tms340x0_device::subi_w_a, &tms340x0_device::subi_w_b, |
| 50 | | /* 0x0c00 */ |
| 51 | | &tms340x0_device::addxyi_a, &tms340x0_device::addxyi_b, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::linit, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 52 | | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 53 | | /* 0x0d00 */ |
| 54 | | &tms340x0_device::subi_l_a, &tms340x0_device::subi_l_b, &tms340x0_device::unimpl, &tms340x0_device::callr, &tms340x0_device::unimpl, &tms340x0_device::calla, &tms340x0_device::eint, &tms340x0_device::unimpl, |
| 55 | | &tms340x0_device::dsj_a, &tms340x0_device::dsj_b, &tms340x0_device::dsjeq_a, &tms340x0_device::dsjeq_b, &tms340x0_device::dsjne_a, &tms340x0_device::dsjne_b, &tms340x0_device::setc, &tms340x0_device::unimpl, |
| 56 | | /* 0x0e00 */ |
| 57 | | &tms340x0_device::unimpl, &tms340x0_device::pixblt_l_m_l,&tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 58 | | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::tfill_xy, |
| 59 | | /* 0x0f00 */ |
| 60 | | &tms340x0_device::pixblt_l_l, &tms340x0_device::unimpl, &tms340x0_device::pixblt_l_xy,&tms340x0_device::unimpl, &tms340x0_device::pixblt_xy_l,&tms340x0_device::unimpl, &tms340x0_device::pixblt_xy_xy,&tms340x0_device::unimpl, |
| 61 | | &tms340x0_device::pixblt_b_l, &tms340x0_device::unimpl, &tms340x0_device::pixblt_b_xy,&tms340x0_device::unimpl, &tms340x0_device::fill_l, &tms340x0_device::unimpl, &tms340x0_device::fill_xy, &tms340x0_device::unimpl, |
| 62 | | /* 0x1000 */ |
| 63 | | &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, |
| 64 | | &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, |
| 65 | | /* 0x1100 */ |
| 66 | | &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, |
| 67 | | &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, |
| 68 | | /* 0x1200 */ |
| 69 | | &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, |
| 70 | | &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, |
| 71 | | /* 0x1300 */ |
| 72 | | &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, |
| 73 | | &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, |
| 74 | | /* 0x1400 */ |
| 75 | | &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, |
| 76 | | &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, |
| 77 | | /* 0x1500 */ |
| 78 | | &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, |
| 79 | | &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, |
| 80 | | /* 0x1600 */ |
| 81 | | &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, |
| 82 | | &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, |
| 83 | | /* 0x1700 */ |
| 84 | | &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, |
| 85 | | &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, |
| 86 | | /* 0x1800 */ |
| 87 | | &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, |
| 88 | | &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, |
| 89 | | /* 0x1900 */ |
| 90 | | &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, |
| 91 | | &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, |
| 92 | | /* 0x1a00 */ |
| 93 | | &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, |
| 94 | | &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, |
| 95 | | /* 0x1b00 */ |
| 96 | | &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, |
| 97 | | &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, |
| 98 | | /* 0x1c00 */ |
| 99 | | &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, |
| 100 | | &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, |
| 101 | | /* 0x1d00 */ |
| 102 | | &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, |
| 103 | | &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, |
| 104 | | /* 0x1e00 */ |
| 105 | | &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, |
| 106 | | &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, |
| 107 | | /* 0x1f00 */ |
| 108 | | &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, |
| 109 | | &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, |
| 110 | | /* 0x2000 */ |
| 111 | | &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, |
| 112 | | &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, |
| 113 | | /* 0x2100 */ |
| 114 | | &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, |
| 115 | | &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, |
| 116 | | /* 0x2200 */ |
| 117 | | &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, |
| 118 | | &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, |
| 119 | | /* 0x2300 */ |
| 120 | | &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, |
| 121 | | &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, |
| 122 | | /* 0x2400 */ |
| 123 | | &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, |
| 124 | | &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, |
| 125 | | /* 0x2500 */ |
| 126 | | &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, |
| 127 | | &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, |
| 128 | | /* 0x2600 */ |
| 129 | | &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, |
| 130 | | &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, |
| 131 | | /* 0x2700 */ |
| 132 | | &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, |
| 133 | | &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, |
| 134 | | /* 0x2800 */ |
| 135 | | &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, |
| 136 | | &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, |
| 137 | | /* 0x2900 */ |
| 138 | | &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, |
| 139 | | &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, |
| 140 | | /* 0x2a00 */ |
| 141 | | &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, |
| 142 | | &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, |
| 143 | | /* 0x2b00 */ |
| 144 | | &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, |
| 145 | | &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, |
| 146 | | /* 0x2c00 */ |
| 147 | | &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, |
| 148 | | &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, |
| 149 | | /* 0x2d00 */ |
| 150 | | &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, |
| 151 | | &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, |
| 152 | | /* 0x2e00 */ |
| 153 | | &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, |
| 154 | | &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, |
| 155 | | /* 0x2f00 */ |
| 156 | | &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, |
| 157 | | &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, |
| 158 | | /* 0x3000 */ |
| 159 | | &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, |
| 160 | | &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, |
| 161 | | /* 0x3100 */ |
| 162 | | &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, |
| 163 | | &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, |
| 164 | | /* 0x3200 */ |
| 165 | | &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, |
| 166 | | &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, |
| 167 | | /* 0x3300 */ |
| 168 | | &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, |
| 169 | | &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, |
| 170 | | /* 0x3400 */ |
| 171 | | &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, |
| 172 | | &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, |
| 173 | | /* 0x3500 */ |
| 174 | | &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, |
| 175 | | &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, |
| 176 | | /* 0x3600 */ |
| 177 | | &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, |
| 178 | | &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, |
| 179 | | /* 0x3700 */ |
| 180 | | &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, |
| 181 | | &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, |
| 182 | | /* 0x3800 */ |
| 183 | | &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, |
| 184 | | &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, |
| 185 | | /* 0x3900 */ |
| 186 | | &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, |
| 187 | | &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, |
| 188 | | /* 0x3a00 */ |
| 189 | | &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, |
| 190 | | &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, |
| 191 | | /* 0x3b00 */ |
| 192 | | &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, |
| 193 | | &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, |
| 194 | | /* 0x3c00 */ |
| 195 | | &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, |
| 196 | | &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, |
| 197 | | /* 0x3d00 */ |
| 198 | | &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, |
| 199 | | &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, |
| 200 | | /* 0x3e00 */ |
| 201 | | &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, |
| 202 | | &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, |
| 203 | | /* 0x3f00 */ |
| 204 | | &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, |
| 205 | | &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, |
| 206 | | /* 0x4000 */ |
| 207 | | &tms340x0_device::add_a, &tms340x0_device::add_b, &tms340x0_device::add_a, &tms340x0_device::add_b, &tms340x0_device::add_a, &tms340x0_device::add_b, &tms340x0_device::add_a, &tms340x0_device::add_b, |
| 208 | | &tms340x0_device::add_a, &tms340x0_device::add_b, &tms340x0_device::add_a, &tms340x0_device::add_b, &tms340x0_device::add_a, &tms340x0_device::add_b, &tms340x0_device::add_a, &tms340x0_device::add_b, |
| 209 | | /* 0x4100 */ |
| 210 | | &tms340x0_device::add_a, &tms340x0_device::add_b, &tms340x0_device::add_a, &tms340x0_device::add_b, &tms340x0_device::add_a, &tms340x0_device::add_b, &tms340x0_device::add_a, &tms340x0_device::add_b, |
| 211 | | &tms340x0_device::add_a, &tms340x0_device::add_b, &tms340x0_device::add_a, &tms340x0_device::add_b, &tms340x0_device::add_a, &tms340x0_device::add_b, &tms340x0_device::add_a, &tms340x0_device::add_b, |
| 212 | | /* 0x4200 */ |
| 213 | | &tms340x0_device::addc_a, &tms340x0_device::addc_b, &tms340x0_device::addc_a, &tms340x0_device::addc_b, &tms340x0_device::addc_a, &tms340x0_device::addc_b, &tms340x0_device::addc_a, &tms340x0_device::addc_b, |
| 214 | | &tms340x0_device::addc_a, &tms340x0_device::addc_b, &tms340x0_device::addc_a, &tms340x0_device::addc_b, &tms340x0_device::addc_a, &tms340x0_device::addc_b, &tms340x0_device::addc_a, &tms340x0_device::addc_b, |
| 215 | | /* 0x4300 */ |
| 216 | | &tms340x0_device::addc_a, &tms340x0_device::addc_b, &tms340x0_device::addc_a, &tms340x0_device::addc_b, &tms340x0_device::addc_a, &tms340x0_device::addc_b, &tms340x0_device::addc_a, &tms340x0_device::addc_b, |
| 217 | | &tms340x0_device::addc_a, &tms340x0_device::addc_b, &tms340x0_device::addc_a, &tms340x0_device::addc_b, &tms340x0_device::addc_a, &tms340x0_device::addc_b, &tms340x0_device::addc_a, &tms340x0_device::addc_b, |
| 218 | | /* 0x4400 */ |
| 219 | | &tms340x0_device::sub_a, &tms340x0_device::sub_b, &tms340x0_device::sub_a, &tms340x0_device::sub_b, &tms340x0_device::sub_a, &tms340x0_device::sub_b, &tms340x0_device::sub_a, &tms340x0_device::sub_b, |
| 220 | | &tms340x0_device::sub_a, &tms340x0_device::sub_b, &tms340x0_device::sub_a, &tms340x0_device::sub_b, &tms340x0_device::sub_a, &tms340x0_device::sub_b, &tms340x0_device::sub_a, &tms340x0_device::sub_b, |
| 221 | | /* 0x4500 */ |
| 222 | | &tms340x0_device::sub_a, &tms340x0_device::sub_b, &tms340x0_device::sub_a, &tms340x0_device::sub_b, &tms340x0_device::sub_a, &tms340x0_device::sub_b, &tms340x0_device::sub_a, &tms340x0_device::sub_b, |
| 223 | | &tms340x0_device::sub_a, &tms340x0_device::sub_b, &tms340x0_device::sub_a, &tms340x0_device::sub_b, &tms340x0_device::sub_a, &tms340x0_device::sub_b, &tms340x0_device::sub_a, &tms340x0_device::sub_b, |
| 224 | | /* 0x4600 */ |
| 225 | | &tms340x0_device::subb_a, &tms340x0_device::subb_b, &tms340x0_device::subb_a, &tms340x0_device::subb_b, &tms340x0_device::subb_a, &tms340x0_device::subb_b, &tms340x0_device::subb_a, &tms340x0_device::subb_b, |
| 226 | | &tms340x0_device::subb_a, &tms340x0_device::subb_b, &tms340x0_device::subb_a, &tms340x0_device::subb_b, &tms340x0_device::subb_a, &tms340x0_device::subb_b, &tms340x0_device::subb_a, &tms340x0_device::subb_b, |
| 227 | | /* 0x4700 */ |
| 228 | | &tms340x0_device::subb_a, &tms340x0_device::subb_b, &tms340x0_device::subb_a, &tms340x0_device::subb_b, &tms340x0_device::subb_a, &tms340x0_device::subb_b, &tms340x0_device::subb_a, &tms340x0_device::subb_b, |
| 229 | | &tms340x0_device::subb_a, &tms340x0_device::subb_b, &tms340x0_device::subb_a, &tms340x0_device::subb_b, &tms340x0_device::subb_a, &tms340x0_device::subb_b, &tms340x0_device::subb_a, &tms340x0_device::subb_b, |
| 230 | | /* 0x4800 */ |
| 231 | | &tms340x0_device::cmp_a, &tms340x0_device::cmp_b, &tms340x0_device::cmp_a, &tms340x0_device::cmp_b, &tms340x0_device::cmp_a, &tms340x0_device::cmp_b, &tms340x0_device::cmp_a, &tms340x0_device::cmp_b, |
| 232 | | &tms340x0_device::cmp_a, &tms340x0_device::cmp_b, &tms340x0_device::cmp_a, &tms340x0_device::cmp_b, &tms340x0_device::cmp_a, &tms340x0_device::cmp_b, &tms340x0_device::cmp_a, &tms340x0_device::cmp_b, |
| 233 | | /* 0x4900 */ |
| 234 | | &tms340x0_device::cmp_a, &tms340x0_device::cmp_b, &tms340x0_device::cmp_a, &tms340x0_device::cmp_b, &tms340x0_device::cmp_a, &tms340x0_device::cmp_b, &tms340x0_device::cmp_a, &tms340x0_device::cmp_b, |
| 235 | | &tms340x0_device::cmp_a, &tms340x0_device::cmp_b, &tms340x0_device::cmp_a, &tms340x0_device::cmp_b, &tms340x0_device::cmp_a, &tms340x0_device::cmp_b, &tms340x0_device::cmp_a, &tms340x0_device::cmp_b, |
| 236 | | /* 0x4a00 */ |
| 237 | | &tms340x0_device::btst_r_a, &tms340x0_device::btst_r_b, &tms340x0_device::btst_r_a, &tms340x0_device::btst_r_b, &tms340x0_device::btst_r_a, &tms340x0_device::btst_r_b, &tms340x0_device::btst_r_a, &tms340x0_device::btst_r_b, |
| 238 | | &tms340x0_device::btst_r_a, &tms340x0_device::btst_r_b, &tms340x0_device::btst_r_a, &tms340x0_device::btst_r_b, &tms340x0_device::btst_r_a, &tms340x0_device::btst_r_b, &tms340x0_device::btst_r_a, &tms340x0_device::btst_r_b, |
| 239 | | /* 0x4b00 */ |
| 240 | | &tms340x0_device::btst_r_a, &tms340x0_device::btst_r_b, &tms340x0_device::btst_r_a, &tms340x0_device::btst_r_b, &tms340x0_device::btst_r_a, &tms340x0_device::btst_r_b, &tms340x0_device::btst_r_a, &tms340x0_device::btst_r_b, |
| 241 | | &tms340x0_device::btst_r_a, &tms340x0_device::btst_r_b, &tms340x0_device::btst_r_a, &tms340x0_device::btst_r_b, &tms340x0_device::btst_r_a, &tms340x0_device::btst_r_b, &tms340x0_device::btst_r_a, &tms340x0_device::btst_r_b, |
| 242 | | /* 0x4c00 */ |
| 243 | | &tms340x0_device::move_rr_a, &tms340x0_device::move_rr_b, &tms340x0_device::move_rr_a, &tms340x0_device::move_rr_b, &tms340x0_device::move_rr_a, &tms340x0_device::move_rr_b, &tms340x0_device::move_rr_a, &tms340x0_device::move_rr_b, |
| 244 | | &tms340x0_device::move_rr_a, &tms340x0_device::move_rr_b, &tms340x0_device::move_rr_a, &tms340x0_device::move_rr_b, &tms340x0_device::move_rr_a, &tms340x0_device::move_rr_b, &tms340x0_device::move_rr_a, &tms340x0_device::move_rr_b, |
| 245 | | /* 0x4d00 */ |
| 246 | | &tms340x0_device::move_rr_a, &tms340x0_device::move_rr_b, &tms340x0_device::move_rr_a, &tms340x0_device::move_rr_b, &tms340x0_device::move_rr_a, &tms340x0_device::move_rr_b, &tms340x0_device::move_rr_a, &tms340x0_device::move_rr_b, |
| 247 | | &tms340x0_device::move_rr_a, &tms340x0_device::move_rr_b, &tms340x0_device::move_rr_a, &tms340x0_device::move_rr_b, &tms340x0_device::move_rr_a, &tms340x0_device::move_rr_b, &tms340x0_device::move_rr_a, &tms340x0_device::move_rr_b, |
| 248 | | /* 0x4e00 */ |
| 249 | | &tms340x0_device::move_rr_ax, &tms340x0_device::move_rr_bx, &tms340x0_device::move_rr_ax, &tms340x0_device::move_rr_bx, &tms340x0_device::move_rr_ax, &tms340x0_device::move_rr_bx, &tms340x0_device::move_rr_ax, &tms340x0_device::move_rr_bx, |
| 250 | | &tms340x0_device::move_rr_ax, &tms340x0_device::move_rr_bx, &tms340x0_device::move_rr_ax, &tms340x0_device::move_rr_bx, &tms340x0_device::move_rr_ax, &tms340x0_device::move_rr_bx, &tms340x0_device::move_rr_ax, &tms340x0_device::move_rr_bx, |
| 251 | | /* 0x4f00 */ |
| 252 | | &tms340x0_device::move_rr_ax, &tms340x0_device::move_rr_bx, &tms340x0_device::move_rr_ax, &tms340x0_device::move_rr_bx, &tms340x0_device::move_rr_ax, &tms340x0_device::move_rr_bx, &tms340x0_device::move_rr_ax, &tms340x0_device::move_rr_bx, |
| 253 | | &tms340x0_device::move_rr_ax, &tms340x0_device::move_rr_bx, &tms340x0_device::move_rr_ax, &tms340x0_device::move_rr_bx, &tms340x0_device::move_rr_ax, &tms340x0_device::move_rr_bx, &tms340x0_device::move_rr_ax, &tms340x0_device::move_rr_bx, |
| 254 | | /* 0x5000 */ |
| 255 | | &tms340x0_device::and_a, &tms340x0_device::and_b, &tms340x0_device::and_a, &tms340x0_device::and_b, &tms340x0_device::and_a, &tms340x0_device::and_b, &tms340x0_device::and_a, &tms340x0_device::and_b, |
| 256 | | &tms340x0_device::and_a, &tms340x0_device::and_b, &tms340x0_device::and_a, &tms340x0_device::and_b, &tms340x0_device::and_a, &tms340x0_device::and_b, &tms340x0_device::and_a, &tms340x0_device::and_b, |
| 257 | | /* 0x5100 */ |
| 258 | | &tms340x0_device::and_a, &tms340x0_device::and_b, &tms340x0_device::and_a, &tms340x0_device::and_b, &tms340x0_device::and_a, &tms340x0_device::and_b, &tms340x0_device::and_a, &tms340x0_device::and_b, |
| 259 | | &tms340x0_device::and_a, &tms340x0_device::and_b, &tms340x0_device::and_a, &tms340x0_device::and_b, &tms340x0_device::and_a, &tms340x0_device::and_b, &tms340x0_device::and_a, &tms340x0_device::and_b, |
| 260 | | /* 0x5200 */ |
| 261 | | &tms340x0_device::andn_a, &tms340x0_device::andn_b, &tms340x0_device::andn_a, &tms340x0_device::andn_b, &tms340x0_device::andn_a, &tms340x0_device::andn_b, &tms340x0_device::andn_a, &tms340x0_device::andn_b, |
| 262 | | &tms340x0_device::andn_a, &tms340x0_device::andn_b, &tms340x0_device::andn_a, &tms340x0_device::andn_b, &tms340x0_device::andn_a, &tms340x0_device::andn_b, &tms340x0_device::andn_a, &tms340x0_device::andn_b, |
| 263 | | /* 0x5300 */ |
| 264 | | &tms340x0_device::andn_a, &tms340x0_device::andn_b, &tms340x0_device::andn_a, &tms340x0_device::andn_b, &tms340x0_device::andn_a, &tms340x0_device::andn_b, &tms340x0_device::andn_a, &tms340x0_device::andn_b, |
| 265 | | &tms340x0_device::andn_a, &tms340x0_device::andn_b, &tms340x0_device::andn_a, &tms340x0_device::andn_b, &tms340x0_device::andn_a, &tms340x0_device::andn_b, &tms340x0_device::andn_a, &tms340x0_device::andn_b, |
| 266 | | /* 0x5400 */ |
| 267 | | &tms340x0_device::or_a, &tms340x0_device::or_b, &tms340x0_device::or_a, &tms340x0_device::or_b, &tms340x0_device::or_a, &tms340x0_device::or_b, &tms340x0_device::or_a, &tms340x0_device::or_b, |
| 268 | | &tms340x0_device::or_a, &tms340x0_device::or_b, &tms340x0_device::or_a, &tms340x0_device::or_b, &tms340x0_device::or_a, &tms340x0_device::or_b, &tms340x0_device::or_a, &tms340x0_device::or_b, |
| 269 | | /* 0x5500 */ |
| 270 | | &tms340x0_device::or_a, &tms340x0_device::or_b, &tms340x0_device::or_a, &tms340x0_device::or_b, &tms340x0_device::or_a, &tms340x0_device::or_b, &tms340x0_device::or_a, &tms340x0_device::or_b, |
| 271 | | &tms340x0_device::or_a, &tms340x0_device::or_b, &tms340x0_device::or_a, &tms340x0_device::or_b, &tms340x0_device::or_a, &tms340x0_device::or_b, &tms340x0_device::or_a, &tms340x0_device::or_b, |
| 272 | | /* 0x5600 */ |
| 273 | | &tms340x0_device::xor_a, &tms340x0_device::xor_b, &tms340x0_device::xor_a, &tms340x0_device::xor_b, &tms340x0_device::xor_a, &tms340x0_device::xor_b, &tms340x0_device::xor_a, &tms340x0_device::xor_b, |
| 274 | | &tms340x0_device::xor_a, &tms340x0_device::xor_b, &tms340x0_device::xor_a, &tms340x0_device::xor_b, &tms340x0_device::xor_a, &tms340x0_device::xor_b, &tms340x0_device::xor_a, &tms340x0_device::xor_b, |
| 275 | | /* 0x5700 */ |
| 276 | | &tms340x0_device::xor_a, &tms340x0_device::xor_b, &tms340x0_device::xor_a, &tms340x0_device::xor_b, &tms340x0_device::xor_a, &tms340x0_device::xor_b, &tms340x0_device::xor_a, &tms340x0_device::xor_b, |
| 277 | | &tms340x0_device::xor_a, &tms340x0_device::xor_b, &tms340x0_device::xor_a, &tms340x0_device::xor_b, &tms340x0_device::xor_a, &tms340x0_device::xor_b, &tms340x0_device::xor_a, &tms340x0_device::xor_b, |
| 278 | | /* 0x5800 */ |
| 279 | | &tms340x0_device::divs_a, &tms340x0_device::divs_b, &tms340x0_device::divs_a, &tms340x0_device::divs_b, &tms340x0_device::divs_a, &tms340x0_device::divs_b, &tms340x0_device::divs_a, &tms340x0_device::divs_b, |
| 280 | | &tms340x0_device::divs_a, &tms340x0_device::divs_b, &tms340x0_device::divs_a, &tms340x0_device::divs_b, &tms340x0_device::divs_a, &tms340x0_device::divs_b, &tms340x0_device::divs_a, &tms340x0_device::divs_b, |
| 281 | | /* 0x5900 */ |
| 282 | | &tms340x0_device::divs_a, &tms340x0_device::divs_b, &tms340x0_device::divs_a, &tms340x0_device::divs_b, &tms340x0_device::divs_a, &tms340x0_device::divs_b, &tms340x0_device::divs_a, &tms340x0_device::divs_b, |
| 283 | | &tms340x0_device::divs_a, &tms340x0_device::divs_b, &tms340x0_device::divs_a, &tms340x0_device::divs_b, &tms340x0_device::divs_a, &tms340x0_device::divs_b, &tms340x0_device::divs_a, &tms340x0_device::divs_b, |
| 284 | | /* 0x5a00 */ |
| 285 | | &tms340x0_device::divu_a, &tms340x0_device::divu_b, &tms340x0_device::divu_a, &tms340x0_device::divu_b, &tms340x0_device::divu_a, &tms340x0_device::divu_b, &tms340x0_device::divu_a, &tms340x0_device::divu_b, |
| 286 | | &tms340x0_device::divu_a, &tms340x0_device::divu_b, &tms340x0_device::divu_a, &tms340x0_device::divu_b, &tms340x0_device::divu_a, &tms340x0_device::divu_b, &tms340x0_device::divu_a, &tms340x0_device::divu_b, |
| 287 | | /* 0x5b00 */ |
| 288 | | &tms340x0_device::divu_a, &tms340x0_device::divu_b, &tms340x0_device::divu_a, &tms340x0_device::divu_b, &tms340x0_device::divu_a, &tms340x0_device::divu_b, &tms340x0_device::divu_a, &tms340x0_device::divu_b, |
| 289 | | &tms340x0_device::divu_a, &tms340x0_device::divu_b, &tms340x0_device::divu_a, &tms340x0_device::divu_b, &tms340x0_device::divu_a, &tms340x0_device::divu_b, &tms340x0_device::divu_a, &tms340x0_device::divu_b, |
| 290 | | /* 0x5c00 */ |
| 291 | | &tms340x0_device::mpys_a, &tms340x0_device::mpys_b, &tms340x0_device::mpys_a, &tms340x0_device::mpys_b, &tms340x0_device::mpys_a, &tms340x0_device::mpys_b, &tms340x0_device::mpys_a, &tms340x0_device::mpys_b, |
| 292 | | &tms340x0_device::mpys_a, &tms340x0_device::mpys_b, &tms340x0_device::mpys_a, &tms340x0_device::mpys_b, &tms340x0_device::mpys_a, &tms340x0_device::mpys_b, &tms340x0_device::mpys_a, &tms340x0_device::mpys_b, |
| 293 | | /* 0x5d00 */ |
| 294 | | &tms340x0_device::mpys_a, &tms340x0_device::mpys_b, &tms340x0_device::mpys_a, &tms340x0_device::mpys_b, &tms340x0_device::mpys_a, &tms340x0_device::mpys_b, &tms340x0_device::mpys_a, &tms340x0_device::mpys_b, |
| 295 | | &tms340x0_device::mpys_a, &tms340x0_device::mpys_b, &tms340x0_device::mpys_a, &tms340x0_device::mpys_b, &tms340x0_device::mpys_a, &tms340x0_device::mpys_b, &tms340x0_device::mpys_a, &tms340x0_device::mpys_b, |
| 296 | | /* 0x5e00 */ |
| 297 | | &tms340x0_device::mpyu_a, &tms340x0_device::mpyu_b, &tms340x0_device::mpyu_a, &tms340x0_device::mpyu_b, &tms340x0_device::mpyu_a, &tms340x0_device::mpyu_b, &tms340x0_device::mpyu_a, &tms340x0_device::mpyu_b, |
| 298 | | &tms340x0_device::mpyu_a, &tms340x0_device::mpyu_b, &tms340x0_device::mpyu_a, &tms340x0_device::mpyu_b, &tms340x0_device::mpyu_a, &tms340x0_device::mpyu_b, &tms340x0_device::mpyu_a, &tms340x0_device::mpyu_b, |
| 299 | | /* 0x5f00 */ |
| 300 | | &tms340x0_device::mpyu_a, &tms340x0_device::mpyu_b, &tms340x0_device::mpyu_a, &tms340x0_device::mpyu_b, &tms340x0_device::mpyu_a, &tms340x0_device::mpyu_b, &tms340x0_device::mpyu_a, &tms340x0_device::mpyu_b, |
| 301 | | &tms340x0_device::mpyu_a, &tms340x0_device::mpyu_b, &tms340x0_device::mpyu_a, &tms340x0_device::mpyu_b, &tms340x0_device::mpyu_a, &tms340x0_device::mpyu_b, &tms340x0_device::mpyu_a, &tms340x0_device::mpyu_b, |
| 302 | | /* 0x6000 */ |
| 303 | | &tms340x0_device::sla_r_a, &tms340x0_device::sla_r_b, &tms340x0_device::sla_r_a, &tms340x0_device::sla_r_b, &tms340x0_device::sla_r_a, &tms340x0_device::sla_r_b, &tms340x0_device::sla_r_a, &tms340x0_device::sla_r_b, |
| 304 | | &tms340x0_device::sla_r_a, &tms340x0_device::sla_r_b, &tms340x0_device::sla_r_a, &tms340x0_device::sla_r_b, &tms340x0_device::sla_r_a, &tms340x0_device::sla_r_b, &tms340x0_device::sla_r_a, &tms340x0_device::sla_r_b, |
| 305 | | /* 0x6100 */ |
| 306 | | &tms340x0_device::sla_r_a, &tms340x0_device::sla_r_b, &tms340x0_device::sla_r_a, &tms340x0_device::sla_r_b, &tms340x0_device::sla_r_a, &tms340x0_device::sla_r_b, &tms340x0_device::sla_r_a, &tms340x0_device::sla_r_b, |
| 307 | | &tms340x0_device::sla_r_a, &tms340x0_device::sla_r_b, &tms340x0_device::sla_r_a, &tms340x0_device::sla_r_b, &tms340x0_device::sla_r_a, &tms340x0_device::sla_r_b, &tms340x0_device::sla_r_a, &tms340x0_device::sla_r_b, |
| 308 | | /* 0x6200 */ |
| 309 | | &tms340x0_device::sll_r_a, &tms340x0_device::sll_r_b, &tms340x0_device::sll_r_a, &tms340x0_device::sll_r_b, &tms340x0_device::sll_r_a, &tms340x0_device::sll_r_b, &tms340x0_device::sll_r_a, &tms340x0_device::sll_r_b, |
| 310 | | &tms340x0_device::sll_r_a, &tms340x0_device::sll_r_b, &tms340x0_device::sll_r_a, &tms340x0_device::sll_r_b, &tms340x0_device::sll_r_a, &tms340x0_device::sll_r_b, &tms340x0_device::sll_r_a, &tms340x0_device::sll_r_b, |
| 311 | | /* 0x6300 */ |
| 312 | | &tms340x0_device::sll_r_a, &tms340x0_device::sll_r_b, &tms340x0_device::sll_r_a, &tms340x0_device::sll_r_b, &tms340x0_device::sll_r_a, &tms340x0_device::sll_r_b, &tms340x0_device::sll_r_a, &tms340x0_device::sll_r_b, |
| 313 | | &tms340x0_device::sll_r_a, &tms340x0_device::sll_r_b, &tms340x0_device::sll_r_a, &tms340x0_device::sll_r_b, &tms340x0_device::sll_r_a, &tms340x0_device::sll_r_b, &tms340x0_device::sll_r_a, &tms340x0_device::sll_r_b, |
| 314 | | /* 0x6400 */ |
| 315 | | &tms340x0_device::sra_r_a, &tms340x0_device::sra_r_b, &tms340x0_device::sra_r_a, &tms340x0_device::sra_r_b, &tms340x0_device::sra_r_a, &tms340x0_device::sra_r_b, &tms340x0_device::sra_r_a, &tms340x0_device::sra_r_b, |
| 316 | | &tms340x0_device::sra_r_a, &tms340x0_device::sra_r_b, &tms340x0_device::sra_r_a, &tms340x0_device::sra_r_b, &tms340x0_device::sra_r_a, &tms340x0_device::sra_r_b, &tms340x0_device::sra_r_a, &tms340x0_device::sra_r_b, |
| 317 | | /* 0x6500 */ |
| 318 | | &tms340x0_device::sra_r_a, &tms340x0_device::sra_r_b, &tms340x0_device::sra_r_a, &tms340x0_device::sra_r_b, &tms340x0_device::sra_r_a, &tms340x0_device::sra_r_b, &tms340x0_device::sra_r_a, &tms340x0_device::sra_r_b, |
| 319 | | &tms340x0_device::sra_r_a, &tms340x0_device::sra_r_b, &tms340x0_device::sra_r_a, &tms340x0_device::sra_r_b, &tms340x0_device::sra_r_a, &tms340x0_device::sra_r_b, &tms340x0_device::sra_r_a, &tms340x0_device::sra_r_b, |
| 320 | | /* 0x6600 */ |
| 321 | | &tms340x0_device::srl_r_a, &tms340x0_device::srl_r_b, &tms340x0_device::srl_r_a, &tms340x0_device::srl_r_b, &tms340x0_device::srl_r_a, &tms340x0_device::srl_r_b, &tms340x0_device::srl_r_a, &tms340x0_device::srl_r_b, |
| 322 | | &tms340x0_device::srl_r_a, &tms340x0_device::srl_r_b, &tms340x0_device::srl_r_a, &tms340x0_device::srl_r_b, &tms340x0_device::srl_r_a, &tms340x0_device::srl_r_b, &tms340x0_device::srl_r_a, &tms340x0_device::srl_r_b, |
| 323 | | /* 0x6700 */ |
| 324 | | &tms340x0_device::srl_r_a, &tms340x0_device::srl_r_b, &tms340x0_device::srl_r_a, &tms340x0_device::srl_r_b, &tms340x0_device::srl_r_a, &tms340x0_device::srl_r_b, &tms340x0_device::srl_r_a, &tms340x0_device::srl_r_b, |
| 325 | | &tms340x0_device::srl_r_a, &tms340x0_device::srl_r_b, &tms340x0_device::srl_r_a, &tms340x0_device::srl_r_b, &tms340x0_device::srl_r_a, &tms340x0_device::srl_r_b, &tms340x0_device::srl_r_a, &tms340x0_device::srl_r_b, |
| 326 | | /* 0x6800 */ |
| 327 | | &tms340x0_device::rl_r_a, &tms340x0_device::rl_r_b, &tms340x0_device::rl_r_a, &tms340x0_device::rl_r_b, &tms340x0_device::rl_r_a, &tms340x0_device::rl_r_b, &tms340x0_device::rl_r_a, &tms340x0_device::rl_r_b, |
| 328 | | &tms340x0_device::rl_r_a, &tms340x0_device::rl_r_b, &tms340x0_device::rl_r_a, &tms340x0_device::rl_r_b, &tms340x0_device::rl_r_a, &tms340x0_device::rl_r_b, &tms340x0_device::rl_r_a, &tms340x0_device::rl_r_b, |
| 329 | | /* 0x6900 */ |
| 330 | | &tms340x0_device::rl_r_a, &tms340x0_device::rl_r_b, &tms340x0_device::rl_r_a, &tms340x0_device::rl_r_b, &tms340x0_device::rl_r_a, &tms340x0_device::rl_r_b, &tms340x0_device::rl_r_a, &tms340x0_device::rl_r_b, |
| 331 | | &tms340x0_device::rl_r_a, &tms340x0_device::rl_r_b, &tms340x0_device::rl_r_a, &tms340x0_device::rl_r_b, &tms340x0_device::rl_r_a, &tms340x0_device::rl_r_b, &tms340x0_device::rl_r_a, &tms340x0_device::rl_r_b, |
| 332 | | /* 0x6a00 */ |
| 333 | | &tms340x0_device::lmo_a, &tms340x0_device::lmo_b, &tms340x0_device::lmo_a, &tms340x0_device::lmo_b, &tms340x0_device::lmo_a, &tms340x0_device::lmo_b, &tms340x0_device::lmo_a, &tms340x0_device::lmo_b, |
| 334 | | &tms340x0_device::lmo_a, &tms340x0_device::lmo_b, &tms340x0_device::lmo_a, &tms340x0_device::lmo_b, &tms340x0_device::lmo_a, &tms340x0_device::lmo_b, &tms340x0_device::lmo_a, &tms340x0_device::lmo_b, |
| 335 | | /* 0x6b00 */ |
| 336 | | &tms340x0_device::lmo_a, &tms340x0_device::lmo_b, &tms340x0_device::lmo_a, &tms340x0_device::lmo_b, &tms340x0_device::lmo_a, &tms340x0_device::lmo_b, &tms340x0_device::lmo_a, &tms340x0_device::lmo_b, |
| 337 | | &tms340x0_device::lmo_a, &tms340x0_device::lmo_b, &tms340x0_device::lmo_a, &tms340x0_device::lmo_b, &tms340x0_device::lmo_a, &tms340x0_device::lmo_b, &tms340x0_device::lmo_a, &tms340x0_device::lmo_b, |
| 338 | | /* 0x6c00 */ |
| 339 | | &tms340x0_device::mods_a, &tms340x0_device::mods_b, &tms340x0_device::mods_a, &tms340x0_device::mods_b, &tms340x0_device::mods_a, &tms340x0_device::mods_b, &tms340x0_device::mods_a, &tms340x0_device::mods_b, |
| 340 | | &tms340x0_device::mods_a, &tms340x0_device::mods_b, &tms340x0_device::mods_a, &tms340x0_device::mods_b, &tms340x0_device::mods_a, &tms340x0_device::mods_b, &tms340x0_device::mods_a, &tms340x0_device::mods_b, |
| 341 | | /* 0x6d00 */ |
| 342 | | &tms340x0_device::mods_a, &tms340x0_device::mods_b, &tms340x0_device::mods_a, &tms340x0_device::mods_b, &tms340x0_device::mods_a, &tms340x0_device::mods_b, &tms340x0_device::mods_a, &tms340x0_device::mods_b, |
| 343 | | &tms340x0_device::mods_a, &tms340x0_device::mods_b, &tms340x0_device::mods_a, &tms340x0_device::mods_b, &tms340x0_device::mods_a, &tms340x0_device::mods_b, &tms340x0_device::mods_a, &tms340x0_device::mods_b, |
| 344 | | /* 0x6e00 */ |
| 345 | | &tms340x0_device::modu_a, &tms340x0_device::modu_b, &tms340x0_device::modu_a, &tms340x0_device::modu_b, &tms340x0_device::modu_a, &tms340x0_device::modu_b, &tms340x0_device::modu_a, &tms340x0_device::modu_b, |
| 346 | | &tms340x0_device::modu_a, &tms340x0_device::modu_b, &tms340x0_device::modu_a, &tms340x0_device::modu_b, &tms340x0_device::modu_a, &tms340x0_device::modu_b, &tms340x0_device::modu_a, &tms340x0_device::modu_b, |
| 347 | | /* 0x6f00 */ |
| 348 | | &tms340x0_device::modu_a, &tms340x0_device::modu_b, &tms340x0_device::modu_a, &tms340x0_device::modu_b, &tms340x0_device::modu_a, &tms340x0_device::modu_b, &tms340x0_device::modu_a, &tms340x0_device::modu_b, |
| 349 | | &tms340x0_device::modu_a, &tms340x0_device::modu_b, &tms340x0_device::modu_a, &tms340x0_device::modu_b, &tms340x0_device::modu_a, &tms340x0_device::modu_b, &tms340x0_device::modu_a, &tms340x0_device::modu_b, |
| 350 | | /* 0x7000 */ |
| 351 | | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 352 | | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 353 | | /* 0x7100 */ |
| 354 | | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 355 | | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 356 | | /* 0x7200 */ |
| 357 | | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 358 | | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 359 | | /* 0x7300 */ |
| 360 | | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 361 | | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 362 | | /* 0x7400 */ |
| 363 | | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 364 | | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 365 | | /* 0x7500 */ |
| 366 | | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 367 | | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 368 | | /* 0x7600 */ |
| 369 | | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 370 | | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 371 | | /* 0x7700 */ |
| 372 | | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 373 | | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 374 | | /* 0x7800 */ |
| 375 | | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 376 | | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 377 | | /* 0x7900 */ |
| 378 | | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 379 | | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 380 | | /* 0x7a00 */ |
| 381 | | &tms340x0_device::rmo_a, &tms340x0_device::rmo_b, &tms340x0_device::rmo_a, &tms340x0_device::rmo_b, &tms340x0_device::rmo_a, &tms340x0_device::rmo_b, &tms340x0_device::rmo_a, &tms340x0_device::rmo_b, |
| 382 | | &tms340x0_device::rmo_a, &tms340x0_device::rmo_b, &tms340x0_device::rmo_a, &tms340x0_device::rmo_b, &tms340x0_device::rmo_a, &tms340x0_device::rmo_b, &tms340x0_device::rmo_a, &tms340x0_device::rmo_b, |
| 383 | | /* 0x7b00 */ |
| 384 | | &tms340x0_device::rmo_a, &tms340x0_device::rmo_b, &tms340x0_device::rmo_a, &tms340x0_device::rmo_b, &tms340x0_device::rmo_a, &tms340x0_device::rmo_b, &tms340x0_device::rmo_a, &tms340x0_device::rmo_b, |
| 385 | | &tms340x0_device::rmo_a, &tms340x0_device::rmo_b, &tms340x0_device::rmo_a, &tms340x0_device::rmo_b, &tms340x0_device::rmo_a, &tms340x0_device::rmo_b, &tms340x0_device::rmo_a, &tms340x0_device::rmo_b, |
| 386 | | /* 0x7c00 */ |
| 387 | | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 388 | | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 389 | | /* 0x7d00 */ |
| 390 | | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 391 | | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 392 | | /* 0x7e00 */ |
| 393 | | &tms340x0_device::swapf_a, &tms340x0_device::swapf_b, &tms340x0_device::swapf_a, &tms340x0_device::swapf_b, &tms340x0_device::swapf_a, &tms340x0_device::swapf_b, &tms340x0_device::swapf_a, &tms340x0_device::swapf_b, |
| 394 | | &tms340x0_device::swapf_a, &tms340x0_device::swapf_b, &tms340x0_device::swapf_a, &tms340x0_device::swapf_b, &tms340x0_device::swapf_a, &tms340x0_device::swapf_b, &tms340x0_device::swapf_a, &tms340x0_device::swapf_b, |
| 395 | | /* 0x7f00 */ |
| 396 | | &tms340x0_device::swapf_a, &tms340x0_device::swapf_b, &tms340x0_device::swapf_a, &tms340x0_device::swapf_b, &tms340x0_device::swapf_a, &tms340x0_device::swapf_b, &tms340x0_device::swapf_a, &tms340x0_device::swapf_b, |
| 397 | | &tms340x0_device::swapf_a, &tms340x0_device::swapf_b, &tms340x0_device::swapf_a, &tms340x0_device::swapf_b, &tms340x0_device::swapf_a, &tms340x0_device::swapf_b, &tms340x0_device::swapf_a, &tms340x0_device::swapf_b, |
| 398 | | /* 0x8000 */ |
| 399 | | &tms340x0_device::move0_rn_a, &tms340x0_device::move0_rn_b, &tms340x0_device::move0_rn_a, &tms340x0_device::move0_rn_b, &tms340x0_device::move0_rn_a, &tms340x0_device::move0_rn_b, &tms340x0_device::move0_rn_a, &tms340x0_device::move0_rn_b, |
| 400 | | &tms340x0_device::move0_rn_a, &tms340x0_device::move0_rn_b, &tms340x0_device::move0_rn_a, &tms340x0_device::move0_rn_b, &tms340x0_device::move0_rn_a, &tms340x0_device::move0_rn_b, &tms340x0_device::move0_rn_a, &tms340x0_device::move0_rn_b, |
| 401 | | /* 0x8100 */ |
| 402 | | &tms340x0_device::move0_rn_a, &tms340x0_device::move0_rn_b, &tms340x0_device::move0_rn_a, &tms340x0_device::move0_rn_b, &tms340x0_device::move0_rn_a, &tms340x0_device::move0_rn_b, &tms340x0_device::move0_rn_a, &tms340x0_device::move0_rn_b, |
| 403 | | &tms340x0_device::move0_rn_a, &tms340x0_device::move0_rn_b, &tms340x0_device::move0_rn_a, &tms340x0_device::move0_rn_b, &tms340x0_device::move0_rn_a, &tms340x0_device::move0_rn_b, &tms340x0_device::move0_rn_a, &tms340x0_device::move0_rn_b, |
| 404 | | /* 0x8200 */ |
| 405 | | &tms340x0_device::move1_rn_a, &tms340x0_device::move1_rn_b, &tms340x0_device::move1_rn_a, &tms340x0_device::move1_rn_b, &tms340x0_device::move1_rn_a, &tms340x0_device::move1_rn_b, &tms340x0_device::move1_rn_a, &tms340x0_device::move1_rn_b, |
| 406 | | &tms340x0_device::move1_rn_a, &tms340x0_device::move1_rn_b, &tms340x0_device::move1_rn_a, &tms340x0_device::move1_rn_b, &tms340x0_device::move1_rn_a, &tms340x0_device::move1_rn_b, &tms340x0_device::move1_rn_a, &tms340x0_device::move1_rn_b, |
| 407 | | /* 0x8300 */ |
| 408 | | &tms340x0_device::move1_rn_a, &tms340x0_device::move1_rn_b, &tms340x0_device::move1_rn_a, &tms340x0_device::move1_rn_b, &tms340x0_device::move1_rn_a, &tms340x0_device::move1_rn_b, &tms340x0_device::move1_rn_a, &tms340x0_device::move1_rn_b, |
| 409 | | &tms340x0_device::move1_rn_a, &tms340x0_device::move1_rn_b, &tms340x0_device::move1_rn_a, &tms340x0_device::move1_rn_b, &tms340x0_device::move1_rn_a, &tms340x0_device::move1_rn_b, &tms340x0_device::move1_rn_a, &tms340x0_device::move1_rn_b, |
| 410 | | /* 0x8400 */ |
| 411 | | &tms340x0_device::move0_nr_a, &tms340x0_device::move0_nr_b, &tms340x0_device::move0_nr_a, &tms340x0_device::move0_nr_b, &tms340x0_device::move0_nr_a, &tms340x0_device::move0_nr_b, &tms340x0_device::move0_nr_a, &tms340x0_device::move0_nr_b, |
| 412 | | &tms340x0_device::move0_nr_a, &tms340x0_device::move0_nr_b, &tms340x0_device::move0_nr_a, &tms340x0_device::move0_nr_b, &tms340x0_device::move0_nr_a, &tms340x0_device::move0_nr_b, &tms340x0_device::move0_nr_a, &tms340x0_device::move0_nr_b, |
| 413 | | /* 0x8500 */ |
| 414 | | &tms340x0_device::move0_nr_a, &tms340x0_device::move0_nr_b, &tms340x0_device::move0_nr_a, &tms340x0_device::move0_nr_b, &tms340x0_device::move0_nr_a, &tms340x0_device::move0_nr_b, &tms340x0_device::move0_nr_a, &tms340x0_device::move0_nr_b, |
| 415 | | &tms340x0_device::move0_nr_a, &tms340x0_device::move0_nr_b, &tms340x0_device::move0_nr_a, &tms340x0_device::move0_nr_b, &tms340x0_device::move0_nr_a, &tms340x0_device::move0_nr_b, &tms340x0_device::move0_nr_a, &tms340x0_device::move0_nr_b, |
| 416 | | /* 0x8600 */ |
| 417 | | &tms340x0_device::move1_nr_a, &tms340x0_device::move1_nr_b, &tms340x0_device::move1_nr_a, &tms340x0_device::move1_nr_b, &tms340x0_device::move1_nr_a, &tms340x0_device::move1_nr_b, &tms340x0_device::move1_nr_a, &tms340x0_device::move1_nr_b, |
| 418 | | &tms340x0_device::move1_nr_a, &tms340x0_device::move1_nr_b, &tms340x0_device::move1_nr_a, &tms340x0_device::move1_nr_b, &tms340x0_device::move1_nr_a, &tms340x0_device::move1_nr_b, &tms340x0_device::move1_nr_a, &tms340x0_device::move1_nr_b, |
| 419 | | /* 0x8700 */ |
| 420 | | &tms340x0_device::move1_nr_a, &tms340x0_device::move1_nr_b, &tms340x0_device::move1_nr_a, &tms340x0_device::move1_nr_b, &tms340x0_device::move1_nr_a, &tms340x0_device::move1_nr_b, &tms340x0_device::move1_nr_a, &tms340x0_device::move1_nr_b, |
| 421 | | &tms340x0_device::move1_nr_a, &tms340x0_device::move1_nr_b, &tms340x0_device::move1_nr_a, &tms340x0_device::move1_nr_b, &tms340x0_device::move1_nr_a, &tms340x0_device::move1_nr_b, &tms340x0_device::move1_nr_a, &tms340x0_device::move1_nr_b, |
| 422 | | /* 0x8800 */ |
| 423 | | &tms340x0_device::move0_nn_a, &tms340x0_device::move0_nn_b, &tms340x0_device::move0_nn_a, &tms340x0_device::move0_nn_b, &tms340x0_device::move0_nn_a, &tms340x0_device::move0_nn_b, &tms340x0_device::move0_nn_a, &tms340x0_device::move0_nn_b, |
| 424 | | &tms340x0_device::move0_nn_a, &tms340x0_device::move0_nn_b, &tms340x0_device::move0_nn_a, &tms340x0_device::move0_nn_b, &tms340x0_device::move0_nn_a, &tms340x0_device::move0_nn_b, &tms340x0_device::move0_nn_a, &tms340x0_device::move0_nn_b, |
| 425 | | /* 0x8900 */ |
| 426 | | &tms340x0_device::move0_nn_a, &tms340x0_device::move0_nn_b, &tms340x0_device::move0_nn_a, &tms340x0_device::move0_nn_b, &tms340x0_device::move0_nn_a, &tms340x0_device::move0_nn_b, &tms340x0_device::move0_nn_a, &tms340x0_device::move0_nn_b, |
| 427 | | &tms340x0_device::move0_nn_a, &tms340x0_device::move0_nn_b, &tms340x0_device::move0_nn_a, &tms340x0_device::move0_nn_b, &tms340x0_device::move0_nn_a, &tms340x0_device::move0_nn_b, &tms340x0_device::move0_nn_a, &tms340x0_device::move0_nn_b, |
| 428 | | /* 0x8a00 */ |
| 429 | | &tms340x0_device::move1_nn_a, &tms340x0_device::move1_nn_b, &tms340x0_device::move1_nn_a, &tms340x0_device::move1_nn_b, &tms340x0_device::move1_nn_a, &tms340x0_device::move1_nn_b, &tms340x0_device::move1_nn_a, &tms340x0_device::move1_nn_b, |
| 430 | | &tms340x0_device::move1_nn_a, &tms340x0_device::move1_nn_b, &tms340x0_device::move1_nn_a, &tms340x0_device::move1_nn_b, &tms340x0_device::move1_nn_a, &tms340x0_device::move1_nn_b, &tms340x0_device::move1_nn_a, &tms340x0_device::move1_nn_b, |
| 431 | | /* 0x8b00 */ |
| 432 | | &tms340x0_device::move1_nn_a, &tms340x0_device::move1_nn_b, &tms340x0_device::move1_nn_a, &tms340x0_device::move1_nn_b, &tms340x0_device::move1_nn_a, &tms340x0_device::move1_nn_b, &tms340x0_device::move1_nn_a, &tms340x0_device::move1_nn_b, |
| 433 | | &tms340x0_device::move1_nn_a, &tms340x0_device::move1_nn_b, &tms340x0_device::move1_nn_a, &tms340x0_device::move1_nn_b, &tms340x0_device::move1_nn_a, &tms340x0_device::move1_nn_b, &tms340x0_device::move1_nn_a, &tms340x0_device::move1_nn_b, |
| 434 | | /* 0x8c00 */ |
| 435 | | &tms340x0_device::movb_rn_a, &tms340x0_device::movb_rn_b, &tms340x0_device::movb_rn_a, &tms340x0_device::movb_rn_b, &tms340x0_device::movb_rn_a, &tms340x0_device::movb_rn_b, &tms340x0_device::movb_rn_a, &tms340x0_device::movb_rn_b, |
| 436 | | &tms340x0_device::movb_rn_a, &tms340x0_device::movb_rn_b, &tms340x0_device::movb_rn_a, &tms340x0_device::movb_rn_b, &tms340x0_device::movb_rn_a, &tms340x0_device::movb_rn_b, &tms340x0_device::movb_rn_a, &tms340x0_device::movb_rn_b, |
| 437 | | /* 0x8d00 */ |
| 438 | | &tms340x0_device::movb_rn_a, &tms340x0_device::movb_rn_b, &tms340x0_device::movb_rn_a, &tms340x0_device::movb_rn_b, &tms340x0_device::movb_rn_a, &tms340x0_device::movb_rn_b, &tms340x0_device::movb_rn_a, &tms340x0_device::movb_rn_b, |
| 439 | | &tms340x0_device::movb_rn_a, &tms340x0_device::movb_rn_b, &tms340x0_device::movb_rn_a, &tms340x0_device::movb_rn_b, &tms340x0_device::movb_rn_a, &tms340x0_device::movb_rn_b, &tms340x0_device::movb_rn_a, &tms340x0_device::movb_rn_b, |
| 440 | | /* 0x8e00 */ |
| 441 | | &tms340x0_device::movb_nr_a, &tms340x0_device::movb_nr_b, &tms340x0_device::movb_nr_a, &tms340x0_device::movb_nr_b, &tms340x0_device::movb_nr_a, &tms340x0_device::movb_nr_b, &tms340x0_device::movb_nr_a, &tms340x0_device::movb_nr_b, |
| 442 | | &tms340x0_device::movb_nr_a, &tms340x0_device::movb_nr_b, &tms340x0_device::movb_nr_a, &tms340x0_device::movb_nr_b, &tms340x0_device::movb_nr_a, &tms340x0_device::movb_nr_b, &tms340x0_device::movb_nr_a, &tms340x0_device::movb_nr_b, |
| 443 | | /* 0x8f00 */ |
| 444 | | &tms340x0_device::movb_nr_a, &tms340x0_device::movb_nr_b, &tms340x0_device::movb_nr_a, &tms340x0_device::movb_nr_b, &tms340x0_device::movb_nr_a, &tms340x0_device::movb_nr_b, &tms340x0_device::movb_nr_a, &tms340x0_device::movb_nr_b, |
| 445 | | &tms340x0_device::movb_nr_a, &tms340x0_device::movb_nr_b, &tms340x0_device::movb_nr_a, &tms340x0_device::movb_nr_b, &tms340x0_device::movb_nr_a, &tms340x0_device::movb_nr_b, &tms340x0_device::movb_nr_a, &tms340x0_device::movb_nr_b, |
| 446 | | /* 0x9000 */ |
| 447 | | &tms340x0_device::move0_r_ni_a, &tms340x0_device::move0_r_ni_b, &tms340x0_device::move0_r_ni_a, &tms340x0_device::move0_r_ni_b, &tms340x0_device::move0_r_ni_a, &tms340x0_device::move0_r_ni_b, &tms340x0_device::move0_r_ni_a, &tms340x0_device::move0_r_ni_b, |
| 448 | | &tms340x0_device::move0_r_ni_a, &tms340x0_device::move0_r_ni_b, &tms340x0_device::move0_r_ni_a, &tms340x0_device::move0_r_ni_b, &tms340x0_device::move0_r_ni_a, &tms340x0_device::move0_r_ni_b, &tms340x0_device::move0_r_ni_a, &tms340x0_device::move0_r_ni_b, |
| 449 | | /* 0x9100 */ |
| 450 | | &tms340x0_device::move0_r_ni_a, &tms340x0_device::move0_r_ni_b, &tms340x0_device::move0_r_ni_a, &tms340x0_device::move0_r_ni_b, &tms340x0_device::move0_r_ni_a, &tms340x0_device::move0_r_ni_b, &tms340x0_device::move0_r_ni_a, &tms340x0_device::move0_r_ni_b, |
| 451 | | &tms340x0_device::move0_r_ni_a, &tms340x0_device::move0_r_ni_b, &tms340x0_device::move0_r_ni_a, &tms340x0_device::move0_r_ni_b, &tms340x0_device::move0_r_ni_a, &tms340x0_device::move0_r_ni_b, &tms340x0_device::move0_r_ni_a, &tms340x0_device::move0_r_ni_b, |
| 452 | | /* 0x9200 */ |
| 453 | | &tms340x0_device::move1_r_ni_a, &tms340x0_device::move1_r_ni_b, &tms340x0_device::move1_r_ni_a, &tms340x0_device::move1_r_ni_b, &tms340x0_device::move1_r_ni_a, &tms340x0_device::move1_r_ni_b, &tms340x0_device::move1_r_ni_a, &tms340x0_device::move1_r_ni_b, |
| 454 | | &tms340x0_device::move1_r_ni_a, &tms340x0_device::move1_r_ni_b, &tms340x0_device::move1_r_ni_a, &tms340x0_device::move1_r_ni_b, &tms340x0_device::move1_r_ni_a, &tms340x0_device::move1_r_ni_b, &tms340x0_device::move1_r_ni_a, &tms340x0_device::move1_r_ni_b, |
| 455 | | /* 0x9300 */ |
| 456 | | &tms340x0_device::move1_r_ni_a, &tms340x0_device::move1_r_ni_b, &tms340x0_device::move1_r_ni_a, &tms340x0_device::move1_r_ni_b, &tms340x0_device::move1_r_ni_a, &tms340x0_device::move1_r_ni_b, &tms340x0_device::move1_r_ni_a, &tms340x0_device::move1_r_ni_b, |
| 457 | | &tms340x0_device::move1_r_ni_a, &tms340x0_device::move1_r_ni_b, &tms340x0_device::move1_r_ni_a, &tms340x0_device::move1_r_ni_b, &tms340x0_device::move1_r_ni_a, &tms340x0_device::move1_r_ni_b, &tms340x0_device::move1_r_ni_a, &tms340x0_device::move1_r_ni_b, |
| 458 | | /* 0x9400 */ |
| 459 | | &tms340x0_device::move0_ni_r_a, &tms340x0_device::move0_ni_r_b, &tms340x0_device::move0_ni_r_a, &tms340x0_device::move0_ni_r_b, &tms340x0_device::move0_ni_r_a, &tms340x0_device::move0_ni_r_b, &tms340x0_device::move0_ni_r_a, &tms340x0_device::move0_ni_r_b, |
| 460 | | &tms340x0_device::move0_ni_r_a, &tms340x0_device::move0_ni_r_b, &tms340x0_device::move0_ni_r_a, &tms340x0_device::move0_ni_r_b, &tms340x0_device::move0_ni_r_a, &tms340x0_device::move0_ni_r_b, &tms340x0_device::move0_ni_r_a, &tms340x0_device::move0_ni_r_b, |
| 461 | | /* 0x9500 */ |
| 462 | | &tms340x0_device::move0_ni_r_a, &tms340x0_device::move0_ni_r_b, &tms340x0_device::move0_ni_r_a, &tms340x0_device::move0_ni_r_b, &tms340x0_device::move0_ni_r_a, &tms340x0_device::move0_ni_r_b, &tms340x0_device::move0_ni_r_a, &tms340x0_device::move0_ni_r_b, |
| 463 | | &tms340x0_device::move0_ni_r_a, &tms340x0_device::move0_ni_r_b, &tms340x0_device::move0_ni_r_a, &tms340x0_device::move0_ni_r_b, &tms340x0_device::move0_ni_r_a, &tms340x0_device::move0_ni_r_b, &tms340x0_device::move0_ni_r_a, &tms340x0_device::move0_ni_r_b, |
| 464 | | /* 0x9600 */ |
| 465 | | &tms340x0_device::move1_ni_r_a, &tms340x0_device::move1_ni_r_b, &tms340x0_device::move1_ni_r_a, &tms340x0_device::move1_ni_r_b, &tms340x0_device::move1_ni_r_a, &tms340x0_device::move1_ni_r_b, &tms340x0_device::move1_ni_r_a, &tms340x0_device::move1_ni_r_b, |
| 466 | | &tms340x0_device::move1_ni_r_a, &tms340x0_device::move1_ni_r_b, &tms340x0_device::move1_ni_r_a, &tms340x0_device::move1_ni_r_b, &tms340x0_device::move1_ni_r_a, &tms340x0_device::move1_ni_r_b, &tms340x0_device::move1_ni_r_a, &tms340x0_device::move1_ni_r_b, |
| 467 | | /* 0x9700 */ |
| 468 | | &tms340x0_device::move1_ni_r_a, &tms340x0_device::move1_ni_r_b, &tms340x0_device::move1_ni_r_a, &tms340x0_device::move1_ni_r_b, &tms340x0_device::move1_ni_r_a, &tms340x0_device::move1_ni_r_b, &tms340x0_device::move1_ni_r_a, &tms340x0_device::move1_ni_r_b, |
| 469 | | &tms340x0_device::move1_ni_r_a, &tms340x0_device::move1_ni_r_b, &tms340x0_device::move1_ni_r_a, &tms340x0_device::move1_ni_r_b, &tms340x0_device::move1_ni_r_a, &tms340x0_device::move1_ni_r_b, &tms340x0_device::move1_ni_r_a, &tms340x0_device::move1_ni_r_b, |
| 470 | | /* 0x9800 */ |
| 471 | | &tms340x0_device::move0_ni_ni_a, &tms340x0_device::move0_ni_ni_b, &tms340x0_device::move0_ni_ni_a, &tms340x0_device::move0_ni_ni_b, &tms340x0_device::move0_ni_ni_a, &tms340x0_device::move0_ni_ni_b, &tms340x0_device::move0_ni_ni_a, &tms340x0_device::move0_ni_ni_b, |
| 472 | | &tms340x0_device::move0_ni_ni_a, &tms340x0_device::move0_ni_ni_b, &tms340x0_device::move0_ni_ni_a, &tms340x0_device::move0_ni_ni_b, &tms340x0_device::move0_ni_ni_a, &tms340x0_device::move0_ni_ni_b, &tms340x0_device::move0_ni_ni_a, &tms340x0_device::move0_ni_ni_b, |
| 473 | | /* 0x9900 */ |
| 474 | | &tms340x0_device::move0_ni_ni_a, &tms340x0_device::move0_ni_ni_b, &tms340x0_device::move0_ni_ni_a, &tms340x0_device::move0_ni_ni_b, &tms340x0_device::move0_ni_ni_a, &tms340x0_device::move0_ni_ni_b, &tms340x0_device::move0_ni_ni_a, &tms340x0_device::move0_ni_ni_b, |
| 475 | | &tms340x0_device::move0_ni_ni_a, &tms340x0_device::move0_ni_ni_b, &tms340x0_device::move0_ni_ni_a, &tms340x0_device::move0_ni_ni_b, &tms340x0_device::move0_ni_ni_a, &tms340x0_device::move0_ni_ni_b, &tms340x0_device::move0_ni_ni_a, &tms340x0_device::move0_ni_ni_b, |
| 476 | | /* 0x9a00 */ |
| 477 | | &tms340x0_device::move1_ni_ni_a, &tms340x0_device::move1_ni_ni_b, &tms340x0_device::move1_ni_ni_a, &tms340x0_device::move1_ni_ni_b, &tms340x0_device::move1_ni_ni_a, &tms340x0_device::move1_ni_ni_b, &tms340x0_device::move1_ni_ni_a, &tms340x0_device::move1_ni_ni_b, |
| 478 | | &tms340x0_device::move1_ni_ni_a, &tms340x0_device::move1_ni_ni_b, &tms340x0_device::move1_ni_ni_a, &tms340x0_device::move1_ni_ni_b, &tms340x0_device::move1_ni_ni_a, &tms340x0_device::move1_ni_ni_b, &tms340x0_device::move1_ni_ni_a, &tms340x0_device::move1_ni_ni_b, |
| 479 | | /* 0x9b00 */ |
| 480 | | &tms340x0_device::move1_ni_ni_a, &tms340x0_device::move1_ni_ni_b, &tms340x0_device::move1_ni_ni_a, &tms340x0_device::move1_ni_ni_b, &tms340x0_device::move1_ni_ni_a, &tms340x0_device::move1_ni_ni_b, &tms340x0_device::move1_ni_ni_a, &tms340x0_device::move1_ni_ni_b, |
| 481 | | &tms340x0_device::move1_ni_ni_a, &tms340x0_device::move1_ni_ni_b, &tms340x0_device::move1_ni_ni_a, &tms340x0_device::move1_ni_ni_b, &tms340x0_device::move1_ni_ni_a, &tms340x0_device::move1_ni_ni_b, &tms340x0_device::move1_ni_ni_a, &tms340x0_device::move1_ni_ni_b, |
| 482 | | /* 0x9c00 */ |
| 483 | | &tms340x0_device::movb_nn_a, &tms340x0_device::movb_nn_b, &tms340x0_device::movb_nn_a, &tms340x0_device::movb_nn_b, &tms340x0_device::movb_nn_a, &tms340x0_device::movb_nn_b, &tms340x0_device::movb_nn_a, &tms340x0_device::movb_nn_b, |
| 484 | | &tms340x0_device::movb_nn_a, &tms340x0_device::movb_nn_b, &tms340x0_device::movb_nn_a, &tms340x0_device::movb_nn_b, &tms340x0_device::movb_nn_a, &tms340x0_device::movb_nn_b, &tms340x0_device::movb_nn_a, &tms340x0_device::movb_nn_b, |
| 485 | | /* 0x9d00 */ |
| 486 | | &tms340x0_device::movb_nn_a, &tms340x0_device::movb_nn_b, &tms340x0_device::movb_nn_a, &tms340x0_device::movb_nn_b, &tms340x0_device::movb_nn_a, &tms340x0_device::movb_nn_b, &tms340x0_device::movb_nn_a, &tms340x0_device::movb_nn_b, |
| 487 | | &tms340x0_device::movb_nn_a, &tms340x0_device::movb_nn_b, &tms340x0_device::movb_nn_a, &tms340x0_device::movb_nn_b, &tms340x0_device::movb_nn_a, &tms340x0_device::movb_nn_b, &tms340x0_device::movb_nn_a, &tms340x0_device::movb_nn_b, |
| 488 | | /* 0x9e00 */ |
| 489 | | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 490 | | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 491 | | /* 0x9f00 */ |
| 492 | | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 493 | | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 494 | | /* 0xa000 */ |
| 495 | | &tms340x0_device::move0_r_dn_a, &tms340x0_device::move0_r_dn_b, &tms340x0_device::move0_r_dn_a, &tms340x0_device::move0_r_dn_b, &tms340x0_device::move0_r_dn_a, &tms340x0_device::move0_r_dn_b, &tms340x0_device::move0_r_dn_a, &tms340x0_device::move0_r_dn_b, |
| 496 | | &tms340x0_device::move0_r_dn_a, &tms340x0_device::move0_r_dn_b, &tms340x0_device::move0_r_dn_a, &tms340x0_device::move0_r_dn_b, &tms340x0_device::move0_r_dn_a, &tms340x0_device::move0_r_dn_b, &tms340x0_device::move0_r_dn_a, &tms340x0_device::move0_r_dn_b, |
| 497 | | /* 0xa100 */ |
| 498 | | &tms340x0_device::move0_r_dn_a, &tms340x0_device::move0_r_dn_b, &tms340x0_device::move0_r_dn_a, &tms340x0_device::move0_r_dn_b, &tms340x0_device::move0_r_dn_a, &tms340x0_device::move0_r_dn_b, &tms340x0_device::move0_r_dn_a, &tms340x0_device::move0_r_dn_b, |
| 499 | | &tms340x0_device::move0_r_dn_a, &tms340x0_device::move0_r_dn_b, &tms340x0_device::move0_r_dn_a, &tms340x0_device::move0_r_dn_b, &tms340x0_device::move0_r_dn_a, &tms340x0_device::move0_r_dn_b, &tms340x0_device::move0_r_dn_a, &tms340x0_device::move0_r_dn_b, |
| 500 | | /* 0xa200 */ |
| 501 | | &tms340x0_device::move1_r_dn_a, &tms340x0_device::move1_r_dn_b, &tms340x0_device::move1_r_dn_a, &tms340x0_device::move1_r_dn_b, &tms340x0_device::move1_r_dn_a, &tms340x0_device::move1_r_dn_b, &tms340x0_device::move1_r_dn_a, &tms340x0_device::move1_r_dn_b, |
| 502 | | &tms340x0_device::move1_r_dn_a, &tms340x0_device::move1_r_dn_b, &tms340x0_device::move1_r_dn_a, &tms340x0_device::move1_r_dn_b, &tms340x0_device::move1_r_dn_a, &tms340x0_device::move1_r_dn_b, &tms340x0_device::move1_r_dn_a, &tms340x0_device::move1_r_dn_b, |
| 503 | | /* 0xa300 */ |
| 504 | | &tms340x0_device::move1_r_dn_a, &tms340x0_device::move1_r_dn_b, &tms340x0_device::move1_r_dn_a, &tms340x0_device::move1_r_dn_b, &tms340x0_device::move1_r_dn_a, &tms340x0_device::move1_r_dn_b, &tms340x0_device::move1_r_dn_a, &tms340x0_device::move1_r_dn_b, |
| 505 | | &tms340x0_device::move1_r_dn_a, &tms340x0_device::move1_r_dn_b, &tms340x0_device::move1_r_dn_a, &tms340x0_device::move1_r_dn_b, &tms340x0_device::move1_r_dn_a, &tms340x0_device::move1_r_dn_b, &tms340x0_device::move1_r_dn_a, &tms340x0_device::move1_r_dn_b, |
| 506 | | /* 0xa400 */ |
| 507 | | &tms340x0_device::move0_dn_r_a, &tms340x0_device::move0_dn_r_b, &tms340x0_device::move0_dn_r_a, &tms340x0_device::move0_dn_r_b, &tms340x0_device::move0_dn_r_a, &tms340x0_device::move0_dn_r_b, &tms340x0_device::move0_dn_r_a, &tms340x0_device::move0_dn_r_b, |
| 508 | | &tms340x0_device::move0_dn_r_a, &tms340x0_device::move0_dn_r_b, &tms340x0_device::move0_dn_r_a, &tms340x0_device::move0_dn_r_b, &tms340x0_device::move0_dn_r_a, &tms340x0_device::move0_dn_r_b, &tms340x0_device::move0_dn_r_a, &tms340x0_device::move0_dn_r_b, |
| 509 | | /* 0xa500 */ |
| 510 | | &tms340x0_device::move0_dn_r_a, &tms340x0_device::move0_dn_r_b, &tms340x0_device::move0_dn_r_a, &tms340x0_device::move0_dn_r_b, &tms340x0_device::move0_dn_r_a, &tms340x0_device::move0_dn_r_b, &tms340x0_device::move0_dn_r_a, &tms340x0_device::move0_dn_r_b, |
| 511 | | &tms340x0_device::move0_dn_r_a, &tms340x0_device::move0_dn_r_b, &tms340x0_device::move0_dn_r_a, &tms340x0_device::move0_dn_r_b, &tms340x0_device::move0_dn_r_a, &tms340x0_device::move0_dn_r_b, &tms340x0_device::move0_dn_r_a, &tms340x0_device::move0_dn_r_b, |
| 512 | | /* 0xa600 */ |
| 513 | | &tms340x0_device::move1_dn_r_a, &tms340x0_device::move1_dn_r_b, &tms340x0_device::move1_dn_r_a, &tms340x0_device::move1_dn_r_b, &tms340x0_device::move1_dn_r_a, &tms340x0_device::move1_dn_r_b, &tms340x0_device::move1_dn_r_a, &tms340x0_device::move1_dn_r_b, |
| 514 | | &tms340x0_device::move1_dn_r_a, &tms340x0_device::move1_dn_r_b, &tms340x0_device::move1_dn_r_a, &tms340x0_device::move1_dn_r_b, &tms340x0_device::move1_dn_r_a, &tms340x0_device::move1_dn_r_b, &tms340x0_device::move1_dn_r_a, &tms340x0_device::move1_dn_r_b, |
| 515 | | /* 0xa700 */ |
| 516 | | &tms340x0_device::move1_dn_r_a, &tms340x0_device::move1_dn_r_b, &tms340x0_device::move1_dn_r_a, &tms340x0_device::move1_dn_r_b, &tms340x0_device::move1_dn_r_a, &tms340x0_device::move1_dn_r_b, &tms340x0_device::move1_dn_r_a, &tms340x0_device::move1_dn_r_b, |
| 517 | | &tms340x0_device::move1_dn_r_a, &tms340x0_device::move1_dn_r_b, &tms340x0_device::move1_dn_r_a, &tms340x0_device::move1_dn_r_b, &tms340x0_device::move1_dn_r_a, &tms340x0_device::move1_dn_r_b, &tms340x0_device::move1_dn_r_a, &tms340x0_device::move1_dn_r_b, |
| 518 | | /* 0xa800 */ |
| 519 | | &tms340x0_device::move0_dn_dn_a, &tms340x0_device::move0_dn_dn_b, &tms340x0_device::move0_dn_dn_a, &tms340x0_device::move0_dn_dn_b, &tms340x0_device::move0_dn_dn_a, &tms340x0_device::move0_dn_dn_b, &tms340x0_device::move0_dn_dn_a, &tms340x0_device::move0_dn_dn_b, |
| 520 | | &tms340x0_device::move0_dn_dn_a, &tms340x0_device::move0_dn_dn_b, &tms340x0_device::move0_dn_dn_a, &tms340x0_device::move0_dn_dn_b, &tms340x0_device::move0_dn_dn_a, &tms340x0_device::move0_dn_dn_b, &tms340x0_device::move0_dn_dn_a, &tms340x0_device::move0_dn_dn_b, |
| 521 | | /* 0xa900 */ |
| 522 | | &tms340x0_device::move0_dn_dn_a, &tms340x0_device::move0_dn_dn_b, &tms340x0_device::move0_dn_dn_a, &tms340x0_device::move0_dn_dn_b, &tms340x0_device::move0_dn_dn_a, &tms340x0_device::move0_dn_dn_b, &tms340x0_device::move0_dn_dn_a, &tms340x0_device::move0_dn_dn_b, |
| 523 | | &tms340x0_device::move0_dn_dn_a, &tms340x0_device::move0_dn_dn_b, &tms340x0_device::move0_dn_dn_a, &tms340x0_device::move0_dn_dn_b, &tms340x0_device::move0_dn_dn_a, &tms340x0_device::move0_dn_dn_b, &tms340x0_device::move0_dn_dn_a, &tms340x0_device::move0_dn_dn_b, |
| 524 | | /* 0xaa00 */ |
| 525 | | &tms340x0_device::move1_dn_dn_a, &tms340x0_device::move1_dn_dn_b, &tms340x0_device::move1_dn_dn_a, &tms340x0_device::move1_dn_dn_b, &tms340x0_device::move1_dn_dn_a, &tms340x0_device::move1_dn_dn_b, &tms340x0_device::move1_dn_dn_a, &tms340x0_device::move1_dn_dn_b, |
| 526 | | &tms340x0_device::move1_dn_dn_a, &tms340x0_device::move1_dn_dn_b, &tms340x0_device::move1_dn_dn_a, &tms340x0_device::move1_dn_dn_b, &tms340x0_device::move1_dn_dn_a, &tms340x0_device::move1_dn_dn_b, &tms340x0_device::move1_dn_dn_a, &tms340x0_device::move1_dn_dn_b, |
| 527 | | /* 0xab00 */ |
| 528 | | &tms340x0_device::move1_dn_dn_a, &tms340x0_device::move1_dn_dn_b, &tms340x0_device::move1_dn_dn_a, &tms340x0_device::move1_dn_dn_b, &tms340x0_device::move1_dn_dn_a, &tms340x0_device::move1_dn_dn_b, &tms340x0_device::move1_dn_dn_a, &tms340x0_device::move1_dn_dn_b, |
| 529 | | &tms340x0_device::move1_dn_dn_a, &tms340x0_device::move1_dn_dn_b, &tms340x0_device::move1_dn_dn_a, &tms340x0_device::move1_dn_dn_b, &tms340x0_device::move1_dn_dn_a, &tms340x0_device::move1_dn_dn_b, &tms340x0_device::move1_dn_dn_a, &tms340x0_device::move1_dn_dn_b, |
| 530 | | /* 0xac00 */ |
| 531 | | &tms340x0_device::movb_r_no_a, &tms340x0_device::movb_r_no_b, &tms340x0_device::movb_r_no_a, &tms340x0_device::movb_r_no_b, &tms340x0_device::movb_r_no_a, &tms340x0_device::movb_r_no_b, &tms340x0_device::movb_r_no_a, &tms340x0_device::movb_r_no_b, |
| 532 | | &tms340x0_device::movb_r_no_a, &tms340x0_device::movb_r_no_b, &tms340x0_device::movb_r_no_a, &tms340x0_device::movb_r_no_b, &tms340x0_device::movb_r_no_a, &tms340x0_device::movb_r_no_b, &tms340x0_device::movb_r_no_a, &tms340x0_device::movb_r_no_b, |
| 533 | | /* 0xad00 */ |
| 534 | | &tms340x0_device::movb_r_no_a, &tms340x0_device::movb_r_no_b, &tms340x0_device::movb_r_no_a, &tms340x0_device::movb_r_no_b, &tms340x0_device::movb_r_no_a, &tms340x0_device::movb_r_no_b, &tms340x0_device::movb_r_no_a, &tms340x0_device::movb_r_no_b, |
| 535 | | &tms340x0_device::movb_r_no_a, &tms340x0_device::movb_r_no_b, &tms340x0_device::movb_r_no_a, &tms340x0_device::movb_r_no_b, &tms340x0_device::movb_r_no_a, &tms340x0_device::movb_r_no_b, &tms340x0_device::movb_r_no_a, &tms340x0_device::movb_r_no_b, |
| 536 | | /* 0xae00 */ |
| 537 | | &tms340x0_device::movb_no_r_a, &tms340x0_device::movb_no_r_b, &tms340x0_device::movb_no_r_a, &tms340x0_device::movb_no_r_b, &tms340x0_device::movb_no_r_a, &tms340x0_device::movb_no_r_b, &tms340x0_device::movb_no_r_a, &tms340x0_device::movb_no_r_b, |
| 538 | | &tms340x0_device::movb_no_r_a, &tms340x0_device::movb_no_r_b, &tms340x0_device::movb_no_r_a, &tms340x0_device::movb_no_r_b, &tms340x0_device::movb_no_r_a, &tms340x0_device::movb_no_r_b, &tms340x0_device::movb_no_r_a, &tms340x0_device::movb_no_r_b, |
| 539 | | /* 0xaf00 */ |
| 540 | | &tms340x0_device::movb_no_r_a, &tms340x0_device::movb_no_r_b, &tms340x0_device::movb_no_r_a, &tms340x0_device::movb_no_r_b, &tms340x0_device::movb_no_r_a, &tms340x0_device::movb_no_r_b, &tms340x0_device::movb_no_r_a, &tms340x0_device::movb_no_r_b, |
| 541 | | &tms340x0_device::movb_no_r_a, &tms340x0_device::movb_no_r_b, &tms340x0_device::movb_no_r_a, &tms340x0_device::movb_no_r_b, &tms340x0_device::movb_no_r_a, &tms340x0_device::movb_no_r_b, &tms340x0_device::movb_no_r_a, &tms340x0_device::movb_no_r_b, |
| 542 | | /* 0xb000 */ |
| 543 | | &tms340x0_device::move0_r_no_a, &tms340x0_device::move0_r_no_b, &tms340x0_device::move0_r_no_a, &tms340x0_device::move0_r_no_b, &tms340x0_device::move0_r_no_a, &tms340x0_device::move0_r_no_b, &tms340x0_device::move0_r_no_a, &tms340x0_device::move0_r_no_b, |
| 544 | | &tms340x0_device::move0_r_no_a, &tms340x0_device::move0_r_no_b, &tms340x0_device::move0_r_no_a, &tms340x0_device::move0_r_no_b, &tms340x0_device::move0_r_no_a, &tms340x0_device::move0_r_no_b, &tms340x0_device::move0_r_no_a, &tms340x0_device::move0_r_no_b, |
| 545 | | /* 0xb100 */ |
| 546 | | &tms340x0_device::move0_r_no_a, &tms340x0_device::move0_r_no_b, &tms340x0_device::move0_r_no_a, &tms340x0_device::move0_r_no_b, &tms340x0_device::move0_r_no_a, &tms340x0_device::move0_r_no_b, &tms340x0_device::move0_r_no_a, &tms340x0_device::move0_r_no_b, |
| 547 | | &tms340x0_device::move0_r_no_a, &tms340x0_device::move0_r_no_b, &tms340x0_device::move0_r_no_a, &tms340x0_device::move0_r_no_b, &tms340x0_device::move0_r_no_a, &tms340x0_device::move0_r_no_b, &tms340x0_device::move0_r_no_a, &tms340x0_device::move0_r_no_b, |
| 548 | | /* 0xb200 */ |
| 549 | | &tms340x0_device::move1_r_no_a, &tms340x0_device::move1_r_no_b, &tms340x0_device::move1_r_no_a, &tms340x0_device::move1_r_no_b, &tms340x0_device::move1_r_no_a, &tms340x0_device::move1_r_no_b, &tms340x0_device::move1_r_no_a, &tms340x0_device::move1_r_no_b, |
| 550 | | &tms340x0_device::move1_r_no_a, &tms340x0_device::move1_r_no_b, &tms340x0_device::move1_r_no_a, &tms340x0_device::move1_r_no_b, &tms340x0_device::move1_r_no_a, &tms340x0_device::move1_r_no_b, &tms340x0_device::move1_r_no_a, &tms340x0_device::move1_r_no_b, |
| 551 | | /* 0xb300 */ |
| 552 | | &tms340x0_device::move1_r_no_a, &tms340x0_device::move1_r_no_b, &tms340x0_device::move1_r_no_a, &tms340x0_device::move1_r_no_b, &tms340x0_device::move1_r_no_a, &tms340x0_device::move1_r_no_b, &tms340x0_device::move1_r_no_a, &tms340x0_device::move1_r_no_b, |
| 553 | | &tms340x0_device::move1_r_no_a, &tms340x0_device::move1_r_no_b, &tms340x0_device::move1_r_no_a, &tms340x0_device::move1_r_no_b, &tms340x0_device::move1_r_no_a, &tms340x0_device::move1_r_no_b, &tms340x0_device::move1_r_no_a, &tms340x0_device::move1_r_no_b, |
| 554 | | /* 0xb400 */ |
| 555 | | &tms340x0_device::move0_no_r_a, &tms340x0_device::move0_no_r_b, &tms340x0_device::move0_no_r_a, &tms340x0_device::move0_no_r_b, &tms340x0_device::move0_no_r_a, &tms340x0_device::move0_no_r_b, &tms340x0_device::move0_no_r_a, &tms340x0_device::move0_no_r_b, |
| 556 | | &tms340x0_device::move0_no_r_a, &tms340x0_device::move0_no_r_b, &tms340x0_device::move0_no_r_a, &tms340x0_device::move0_no_r_b, &tms340x0_device::move0_no_r_a, &tms340x0_device::move0_no_r_b, &tms340x0_device::move0_no_r_a, &tms340x0_device::move0_no_r_b, |
| 557 | | /* 0xb500 */ |
| 558 | | &tms340x0_device::move0_no_r_a, &tms340x0_device::move0_no_r_b, &tms340x0_device::move0_no_r_a, &tms340x0_device::move0_no_r_b, &tms340x0_device::move0_no_r_a, &tms340x0_device::move0_no_r_b, &tms340x0_device::move0_no_r_a, &tms340x0_device::move0_no_r_b, |
| 559 | | &tms340x0_device::move0_no_r_a, &tms340x0_device::move0_no_r_b, &tms340x0_device::move0_no_r_a, &tms340x0_device::move0_no_r_b, &tms340x0_device::move0_no_r_a, &tms340x0_device::move0_no_r_b, &tms340x0_device::move0_no_r_a, &tms340x0_device::move0_no_r_b, |
| 560 | | /* 0xb600 */ |
| 561 | | &tms340x0_device::move1_no_r_a, &tms340x0_device::move1_no_r_b, &tms340x0_device::move1_no_r_a, &tms340x0_device::move1_no_r_b, &tms340x0_device::move1_no_r_a, &tms340x0_device::move1_no_r_b, &tms340x0_device::move1_no_r_a, &tms340x0_device::move1_no_r_b, |
| 562 | | &tms340x0_device::move1_no_r_a, &tms340x0_device::move1_no_r_b, &tms340x0_device::move1_no_r_a, &tms340x0_device::move1_no_r_b, &tms340x0_device::move1_no_r_a, &tms340x0_device::move1_no_r_b, &tms340x0_device::move1_no_r_a, &tms340x0_device::move1_no_r_b, |
| 563 | | /* 0xb700 */ |
| 564 | | &tms340x0_device::move1_no_r_a, &tms340x0_device::move1_no_r_b, &tms340x0_device::move1_no_r_a, &tms340x0_device::move1_no_r_b, &tms340x0_device::move1_no_r_a, &tms340x0_device::move1_no_r_b, &tms340x0_device::move1_no_r_a, &tms340x0_device::move1_no_r_b, |
| 565 | | &tms340x0_device::move1_no_r_a, &tms340x0_device::move1_no_r_b, &tms340x0_device::move1_no_r_a, &tms340x0_device::move1_no_r_b, &tms340x0_device::move1_no_r_a, &tms340x0_device::move1_no_r_b, &tms340x0_device::move1_no_r_a, &tms340x0_device::move1_no_r_b, |
| 566 | | /* 0xb800 */ |
| 567 | | &tms340x0_device::move0_no_no_a, &tms340x0_device::move0_no_no_b, &tms340x0_device::move0_no_no_a, &tms340x0_device::move0_no_no_b, &tms340x0_device::move0_no_no_a, &tms340x0_device::move0_no_no_b, &tms340x0_device::move0_no_no_a, &tms340x0_device::move0_no_no_b, |
| 568 | | &tms340x0_device::move0_no_no_a, &tms340x0_device::move0_no_no_b, &tms340x0_device::move0_no_no_a, &tms340x0_device::move0_no_no_b, &tms340x0_device::move0_no_no_a, &tms340x0_device::move0_no_no_b, &tms340x0_device::move0_no_no_a, &tms340x0_device::move0_no_no_b, |
| 569 | | /* 0xb900 */ |
| 570 | | &tms340x0_device::move0_no_no_a, &tms340x0_device::move0_no_no_b, &tms340x0_device::move0_no_no_a, &tms340x0_device::move0_no_no_b, &tms340x0_device::move0_no_no_a, &tms340x0_device::move0_no_no_b, &tms340x0_device::move0_no_no_a, &tms340x0_device::move0_no_no_b, |
| 571 | | &tms340x0_device::move0_no_no_a, &tms340x0_device::move0_no_no_b, &tms340x0_device::move0_no_no_a, &tms340x0_device::move0_no_no_b, &tms340x0_device::move0_no_no_a, &tms340x0_device::move0_no_no_b, &tms340x0_device::move0_no_no_a, &tms340x0_device::move0_no_no_b, |
| 572 | | /* 0xba00 */ |
| 573 | | &tms340x0_device::move1_no_no_a, &tms340x0_device::move1_no_no_b, &tms340x0_device::move1_no_no_a, &tms340x0_device::move1_no_no_b, &tms340x0_device::move1_no_no_a, &tms340x0_device::move1_no_no_b, &tms340x0_device::move1_no_no_a, &tms340x0_device::move1_no_no_b, |
| 574 | | &tms340x0_device::move1_no_no_a, &tms340x0_device::move1_no_no_b, &tms340x0_device::move1_no_no_a, &tms340x0_device::move1_no_no_b, &tms340x0_device::move1_no_no_a, &tms340x0_device::move1_no_no_b, &tms340x0_device::move1_no_no_a, &tms340x0_device::move1_no_no_b, |
| 575 | | /* 0xbb00 */ |
| 576 | | &tms340x0_device::move1_no_no_a, &tms340x0_device::move1_no_no_b, &tms340x0_device::move1_no_no_a, &tms340x0_device::move1_no_no_b, &tms340x0_device::move1_no_no_a, &tms340x0_device::move1_no_no_b, &tms340x0_device::move1_no_no_a, &tms340x0_device::move1_no_no_b, |
| 577 | | &tms340x0_device::move1_no_no_a, &tms340x0_device::move1_no_no_b, &tms340x0_device::move1_no_no_a, &tms340x0_device::move1_no_no_b, &tms340x0_device::move1_no_no_a, &tms340x0_device::move1_no_no_b, &tms340x0_device::move1_no_no_a, &tms340x0_device::move1_no_no_b, |
| 578 | | /* 0xbc00 */ |
| 579 | | &tms340x0_device::movb_no_no_a, &tms340x0_device::movb_no_no_b, &tms340x0_device::movb_no_no_a, &tms340x0_device::movb_no_no_b, &tms340x0_device::movb_no_no_a, &tms340x0_device::movb_no_no_b, &tms340x0_device::movb_no_no_a, &tms340x0_device::movb_no_no_b, |
| 580 | | &tms340x0_device::movb_no_no_a, &tms340x0_device::movb_no_no_b, &tms340x0_device::movb_no_no_a, &tms340x0_device::movb_no_no_b, &tms340x0_device::movb_no_no_a, &tms340x0_device::movb_no_no_b, &tms340x0_device::movb_no_no_a, &tms340x0_device::movb_no_no_b, |
| 581 | | /* 0xbd00 */ |
| 582 | | &tms340x0_device::movb_no_no_a, &tms340x0_device::movb_no_no_b, &tms340x0_device::movb_no_no_a, &tms340x0_device::movb_no_no_b, &tms340x0_device::movb_no_no_a, &tms340x0_device::movb_no_no_b, &tms340x0_device::movb_no_no_a, &tms340x0_device::movb_no_no_b, |
| 583 | | &tms340x0_device::movb_no_no_a, &tms340x0_device::movb_no_no_b, &tms340x0_device::movb_no_no_a, &tms340x0_device::movb_no_no_b, &tms340x0_device::movb_no_no_a, &tms340x0_device::movb_no_no_b, &tms340x0_device::movb_no_no_a, &tms340x0_device::movb_no_no_b, |
| 584 | | /* 0xbe00 */ |
| 585 | | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 586 | | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 587 | | /* 0xbf00 */ |
| 588 | | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 589 | | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 590 | | /* 0xc000 */ |
| 591 | | &tms340x0_device::j_UC_0, &tms340x0_device::j_UC_x, &tms340x0_device::j_UC_x, &tms340x0_device::j_UC_x, &tms340x0_device::j_UC_x, &tms340x0_device::j_UC_x, &tms340x0_device::j_UC_x, &tms340x0_device::j_UC_x, |
| 592 | | &tms340x0_device::j_UC_8, &tms340x0_device::j_UC_x, &tms340x0_device::j_UC_x, &tms340x0_device::j_UC_x, &tms340x0_device::j_UC_x, &tms340x0_device::j_UC_x, &tms340x0_device::j_UC_x, &tms340x0_device::j_UC_x, |
| 593 | | /* 0xc100 */ |
| 594 | | &tms340x0_device::j_P_0, &tms340x0_device::j_P_x, &tms340x0_device::j_P_x, &tms340x0_device::j_P_x, &tms340x0_device::j_P_x, &tms340x0_device::j_P_x, &tms340x0_device::j_P_x, &tms340x0_device::j_P_x, |
| 595 | | &tms340x0_device::j_P_8, &tms340x0_device::j_P_x, &tms340x0_device::j_P_x, &tms340x0_device::j_P_x, &tms340x0_device::j_P_x, &tms340x0_device::j_P_x, &tms340x0_device::j_P_x, &tms340x0_device::j_P_x, |
| 596 | | /* 0xc200 */ |
| 597 | | &tms340x0_device::j_LS_0, &tms340x0_device::j_LS_x, &tms340x0_device::j_LS_x, &tms340x0_device::j_LS_x, &tms340x0_device::j_LS_x, &tms340x0_device::j_LS_x, &tms340x0_device::j_LS_x, &tms340x0_device::j_LS_x, |
| 598 | | &tms340x0_device::j_LS_8, &tms340x0_device::j_LS_x, &tms340x0_device::j_LS_x, &tms340x0_device::j_LS_x, &tms340x0_device::j_LS_x, &tms340x0_device::j_LS_x, &tms340x0_device::j_LS_x, &tms340x0_device::j_LS_x, |
| 599 | | /* 0xc300 */ |
| 600 | | &tms340x0_device::j_HI_0, &tms340x0_device::j_HI_x, &tms340x0_device::j_HI_x, &tms340x0_device::j_HI_x, &tms340x0_device::j_HI_x, &tms340x0_device::j_HI_x, &tms340x0_device::j_HI_x, &tms340x0_device::j_HI_x, |
| 601 | | &tms340x0_device::j_HI_8, &tms340x0_device::j_HI_x, &tms340x0_device::j_HI_x, &tms340x0_device::j_HI_x, &tms340x0_device::j_HI_x, &tms340x0_device::j_HI_x, &tms340x0_device::j_HI_x, &tms340x0_device::j_HI_x, |
| 602 | | /* 0xc400 */ |
| 603 | | &tms340x0_device::j_LT_0, &tms340x0_device::j_LT_x, &tms340x0_device::j_LT_x, &tms340x0_device::j_LT_x, &tms340x0_device::j_LT_x, &tms340x0_device::j_LT_x, &tms340x0_device::j_LT_x, &tms340x0_device::j_LT_x, |
| 604 | | &tms340x0_device::j_LT_8, &tms340x0_device::j_LT_x, &tms340x0_device::j_LT_x, &tms340x0_device::j_LT_x, &tms340x0_device::j_LT_x, &tms340x0_device::j_LT_x, &tms340x0_device::j_LT_x, &tms340x0_device::j_LT_x, |
| 605 | | /* 0xc500 */ |
| 606 | | &tms340x0_device::j_GE_0, &tms340x0_device::j_GE_x, &tms340x0_device::j_GE_x, &tms340x0_device::j_GE_x, &tms340x0_device::j_GE_x, &tms340x0_device::j_GE_x, &tms340x0_device::j_GE_x, &tms340x0_device::j_GE_x, |
| 607 | | &tms340x0_device::j_GE_8, &tms340x0_device::j_GE_x, &tms340x0_device::j_GE_x, &tms340x0_device::j_GE_x, &tms340x0_device::j_GE_x, &tms340x0_device::j_GE_x, &tms340x0_device::j_GE_x, &tms340x0_device::j_GE_x, |
| 608 | | /* 0xc600 */ |
| 609 | | &tms340x0_device::j_LE_0, &tms340x0_device::j_LE_x, &tms340x0_device::j_LE_x, &tms340x0_device::j_LE_x, &tms340x0_device::j_LE_x, &tms340x0_device::j_LE_x, &tms340x0_device::j_LE_x, &tms340x0_device::j_LE_x, |
| 610 | | &tms340x0_device::j_LE_8, &tms340x0_device::j_LE_x, &tms340x0_device::j_LE_x, &tms340x0_device::j_LE_x, &tms340x0_device::j_LE_x, &tms340x0_device::j_LE_x, &tms340x0_device::j_LE_x, &tms340x0_device::j_LE_x, |
| 611 | | /* 0xc700 */ |
| 612 | | &tms340x0_device::j_GT_0, &tms340x0_device::j_GT_x, &tms340x0_device::j_GT_x, &tms340x0_device::j_GT_x, &tms340x0_device::j_GT_x, &tms340x0_device::j_GT_x, &tms340x0_device::j_GT_x, &tms340x0_device::j_GT_x, |
| 613 | | &tms340x0_device::j_GT_8, &tms340x0_device::j_GT_x, &tms340x0_device::j_GT_x, &tms340x0_device::j_GT_x, &tms340x0_device::j_GT_x, &tms340x0_device::j_GT_x, &tms340x0_device::j_GT_x, &tms340x0_device::j_GT_x, |
| 614 | | /* 0xc800 */ |
| 615 | | &tms340x0_device::j_C_0, &tms340x0_device::j_C_x, &tms340x0_device::j_C_x, &tms340x0_device::j_C_x, &tms340x0_device::j_C_x, &tms340x0_device::j_C_x, &tms340x0_device::j_C_x, &tms340x0_device::j_C_x, |
| 616 | | &tms340x0_device::j_C_8, &tms340x0_device::j_C_x, &tms340x0_device::j_C_x, &tms340x0_device::j_C_x, &tms340x0_device::j_C_x, &tms340x0_device::j_C_x, &tms340x0_device::j_C_x, &tms340x0_device::j_C_x, |
| 617 | | /* 0xc900 */ |
| 618 | | &tms340x0_device::j_NC_0, &tms340x0_device::j_NC_x, &tms340x0_device::j_NC_x, &tms340x0_device::j_NC_x, &tms340x0_device::j_NC_x, &tms340x0_device::j_NC_x, &tms340x0_device::j_NC_x, &tms340x0_device::j_NC_x, |
| 619 | | &tms340x0_device::j_NC_8, &tms340x0_device::j_NC_x, &tms340x0_device::j_NC_x, &tms340x0_device::j_NC_x, &tms340x0_device::j_NC_x, &tms340x0_device::j_NC_x, &tms340x0_device::j_NC_x, &tms340x0_device::j_NC_x, |
| 620 | | /* 0xca00 */ |
| 621 | | &tms340x0_device::j_EQ_0, &tms340x0_device::j_EQ_x, &tms340x0_device::j_EQ_x, &tms340x0_device::j_EQ_x, &tms340x0_device::j_EQ_x, &tms340x0_device::j_EQ_x, &tms340x0_device::j_EQ_x, &tms340x0_device::j_EQ_x, |
| 622 | | &tms340x0_device::j_EQ_8, &tms340x0_device::j_EQ_x, &tms340x0_device::j_EQ_x, &tms340x0_device::j_EQ_x, &tms340x0_device::j_EQ_x, &tms340x0_device::j_EQ_x, &tms340x0_device::j_EQ_x, &tms340x0_device::j_EQ_x, |
| 623 | | /* 0xcb00 */ |
| 624 | | &tms340x0_device::j_NE_0, &tms340x0_device::j_NE_x, &tms340x0_device::j_NE_x, &tms340x0_device::j_NE_x, &tms340x0_device::j_NE_x, &tms340x0_device::j_NE_x, &tms340x0_device::j_NE_x, &tms340x0_device::j_NE_x, |
| 625 | | &tms340x0_device::j_NE_8, &tms340x0_device::j_NE_x, &tms340x0_device::j_NE_x, &tms340x0_device::j_NE_x, &tms340x0_device::j_NE_x, &tms340x0_device::j_NE_x, &tms340x0_device::j_NE_x, &tms340x0_device::j_NE_x, |
| 626 | | /* 0xcc00 */ |
| 627 | | &tms340x0_device::j_V_0, &tms340x0_device::j_V_x, &tms340x0_device::j_V_x, &tms340x0_device::j_V_x, &tms340x0_device::j_V_x, &tms340x0_device::j_V_x, &tms340x0_device::j_V_x, &tms340x0_device::j_V_x, |
| 628 | | &tms340x0_device::j_V_8, &tms340x0_device::j_V_x, &tms340x0_device::j_V_x, &tms340x0_device::j_V_x, &tms340x0_device::j_V_x, &tms340x0_device::j_V_x, &tms340x0_device::j_V_x, &tms340x0_device::j_V_x, |
| 629 | | /* 0xcd00 */ |
| 630 | | &tms340x0_device::j_NV_0, &tms340x0_device::j_NV_x, &tms340x0_device::j_NV_x, &tms340x0_device::j_NV_x, &tms340x0_device::j_NV_x, &tms340x0_device::j_NV_x, &tms340x0_device::j_NV_x, &tms340x0_device::j_NV_x, |
| 631 | | &tms340x0_device::j_NV_8, &tms340x0_device::j_NV_x, &tms340x0_device::j_NV_x, &tms340x0_device::j_NV_x, &tms340x0_device::j_NV_x, &tms340x0_device::j_NV_x, &tms340x0_device::j_NV_x, &tms340x0_device::j_NV_x, |
| 632 | | /* 0xce00 */ |
| 633 | | &tms340x0_device::j_N_0, &tms340x0_device::j_N_x, &tms340x0_device::j_N_x, &tms340x0_device::j_N_x, &tms340x0_device::j_N_x, &tms340x0_device::j_N_x, &tms340x0_device::j_N_x, &tms340x0_device::j_N_x, |
| 634 | | &tms340x0_device::j_N_8, &tms340x0_device::j_N_x, &tms340x0_device::j_N_x, &tms340x0_device::j_N_x, &tms340x0_device::j_N_x, &tms340x0_device::j_N_x, &tms340x0_device::j_N_x, &tms340x0_device::j_N_x, |
| 635 | | /* 0xcf00 */ |
| 636 | | &tms340x0_device::j_NN_0, &tms340x0_device::j_NN_x, &tms340x0_device::j_NN_x, &tms340x0_device::j_NN_x, &tms340x0_device::j_NN_x, &tms340x0_device::j_NN_x, &tms340x0_device::j_NN_x, &tms340x0_device::j_NN_x, |
| 637 | | &tms340x0_device::j_NN_8, &tms340x0_device::j_NN_x, &tms340x0_device::j_NN_x, &tms340x0_device::j_NN_x, &tms340x0_device::j_NN_x, &tms340x0_device::j_NN_x, &tms340x0_device::j_NN_x, &tms340x0_device::j_NN_x, |
| 638 | | /* 0xd000 */ |
| 639 | | &tms340x0_device::move0_no_ni_a, &tms340x0_device::move0_no_ni_b, &tms340x0_device::move0_no_ni_a, &tms340x0_device::move0_no_ni_b, &tms340x0_device::move0_no_ni_a, &tms340x0_device::move0_no_ni_b, &tms340x0_device::move0_no_ni_a, &tms340x0_device::move0_no_ni_b, |
| 640 | | &tms340x0_device::move0_no_ni_a, &tms340x0_device::move0_no_ni_b, &tms340x0_device::move0_no_ni_a, &tms340x0_device::move0_no_ni_b, &tms340x0_device::move0_no_ni_a, &tms340x0_device::move0_no_ni_b, &tms340x0_device::move0_no_ni_a, &tms340x0_device::move0_no_ni_b, |
| 641 | | /* 0xd100 */ |
| 642 | | &tms340x0_device::move0_no_ni_a, &tms340x0_device::move0_no_ni_b, &tms340x0_device::move0_no_ni_a, &tms340x0_device::move0_no_ni_b, &tms340x0_device::move0_no_ni_a, &tms340x0_device::move0_no_ni_b, &tms340x0_device::move0_no_ni_a, &tms340x0_device::move0_no_ni_b, |
| 643 | | &tms340x0_device::move0_no_ni_a, &tms340x0_device::move0_no_ni_b, &tms340x0_device::move0_no_ni_a, &tms340x0_device::move0_no_ni_b, &tms340x0_device::move0_no_ni_a, &tms340x0_device::move0_no_ni_b, &tms340x0_device::move0_no_ni_a, &tms340x0_device::move0_no_ni_b, |
| 644 | | /* 0xd200 */ |
| 645 | | &tms340x0_device::move1_no_ni_a, &tms340x0_device::move1_no_ni_b, &tms340x0_device::move1_no_ni_a, &tms340x0_device::move1_no_ni_b, &tms340x0_device::move1_no_ni_a, &tms340x0_device::move1_no_ni_b, &tms340x0_device::move1_no_ni_a, &tms340x0_device::move1_no_ni_b, |
| 646 | | &tms340x0_device::move1_no_ni_a, &tms340x0_device::move1_no_ni_b, &tms340x0_device::move1_no_ni_a, &tms340x0_device::move1_no_ni_b, &tms340x0_device::move1_no_ni_a, &tms340x0_device::move1_no_ni_b, &tms340x0_device::move1_no_ni_a, &tms340x0_device::move1_no_ni_b, |
| 647 | | /* 0xd300 */ |
| 648 | | &tms340x0_device::move1_no_ni_a, &tms340x0_device::move1_no_ni_b, &tms340x0_device::move1_no_ni_a, &tms340x0_device::move1_no_ni_b, &tms340x0_device::move1_no_ni_a, &tms340x0_device::move1_no_ni_b, &tms340x0_device::move1_no_ni_a, &tms340x0_device::move1_no_ni_b, |
| 649 | | &tms340x0_device::move1_no_ni_a, &tms340x0_device::move1_no_ni_b, &tms340x0_device::move1_no_ni_a, &tms340x0_device::move1_no_ni_b, &tms340x0_device::move1_no_ni_a, &tms340x0_device::move1_no_ni_b, &tms340x0_device::move1_no_ni_a, &tms340x0_device::move1_no_ni_b, |
| 650 | | /* 0xd400 */ |
| 651 | | &tms340x0_device::move0_a_ni_a,&tms340x0_device::move0_a_ni_b,&tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 652 | | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 653 | | /* 0xd500 */ |
| 654 | | &tms340x0_device::exgf0_a, &tms340x0_device::exgf0_b, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 655 | | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 656 | | /* 0xd600 */ |
| 657 | | &tms340x0_device::move1_a_ni_a,&tms340x0_device::move1_a_ni_b,&tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 658 | | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 659 | | /* 0xd700 */ |
| 660 | | &tms340x0_device::exgf1_a, &tms340x0_device::exgf1_b, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 661 | | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 662 | | /* 0xd800 */ |
| 663 | | &tms340x0_device::cexec_s, &tms340x0_device::cexec_s, &tms340x0_device::cexec_s, &tms340x0_device::cexec_s, &tms340x0_device::cexec_s, &tms340x0_device::cexec_s, &tms340x0_device::cexec_s, &tms340x0_device::cexec_s, |
| 664 | | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 665 | | /* 0xd900 */ |
| 666 | | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 667 | | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 668 | | /* 0xda00 */ |
| 669 | | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 670 | | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 671 | | /* 0xdb00 */ |
| 672 | | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 673 | | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 674 | | /* 0xdc00 */ |
| 675 | | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 676 | | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 677 | | /* 0xdd00 */ |
| 678 | | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 679 | | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 680 | | /* 0xde00 */ |
| 681 | | &tms340x0_device::unimpl, &tms340x0_device::fline, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 682 | | &tms340x0_device::unimpl, &tms340x0_device::fline, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 683 | | /* 0xdf00 */ |
| 684 | | &tms340x0_device::unimpl, &tms340x0_device::line, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 685 | | &tms340x0_device::unimpl, &tms340x0_device::line, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 686 | | /* 0xe000 */ |
| 687 | | &tms340x0_device::add_xy_a, &tms340x0_device::add_xy_b, &tms340x0_device::add_xy_a, &tms340x0_device::add_xy_b, &tms340x0_device::add_xy_a, &tms340x0_device::add_xy_b, &tms340x0_device::add_xy_a, &tms340x0_device::add_xy_b, |
| 688 | | &tms340x0_device::add_xy_a, &tms340x0_device::add_xy_b, &tms340x0_device::add_xy_a, &tms340x0_device::add_xy_b, &tms340x0_device::add_xy_a, &tms340x0_device::add_xy_b, &tms340x0_device::add_xy_a, &tms340x0_device::add_xy_b, |
| 689 | | /* 0xe100 */ |
| 690 | | &tms340x0_device::add_xy_a, &tms340x0_device::add_xy_b, &tms340x0_device::add_xy_a, &tms340x0_device::add_xy_b, &tms340x0_device::add_xy_a, &tms340x0_device::add_xy_b, &tms340x0_device::add_xy_a, &tms340x0_device::add_xy_b, |
| 691 | | &tms340x0_device::add_xy_a, &tms340x0_device::add_xy_b, &tms340x0_device::add_xy_a, &tms340x0_device::add_xy_b, &tms340x0_device::add_xy_a, &tms340x0_device::add_xy_b, &tms340x0_device::add_xy_a, &tms340x0_device::add_xy_b, |
| 692 | | /* 0xe200 */ |
| 693 | | &tms340x0_device::sub_xy_a, &tms340x0_device::sub_xy_b, &tms340x0_device::sub_xy_a, &tms340x0_device::sub_xy_b, &tms340x0_device::sub_xy_a, &tms340x0_device::sub_xy_b, &tms340x0_device::sub_xy_a, &tms340x0_device::sub_xy_b, |
| 694 | | &tms340x0_device::sub_xy_a, &tms340x0_device::sub_xy_b, &tms340x0_device::sub_xy_a, &tms340x0_device::sub_xy_b, &tms340x0_device::sub_xy_a, &tms340x0_device::sub_xy_b, &tms340x0_device::sub_xy_a, &tms340x0_device::sub_xy_b, |
| 695 | | /* 0xe300 */ |
| 696 | | &tms340x0_device::sub_xy_a, &tms340x0_device::sub_xy_b, &tms340x0_device::sub_xy_a, &tms340x0_device::sub_xy_b, &tms340x0_device::sub_xy_a, &tms340x0_device::sub_xy_b, &tms340x0_device::sub_xy_a, &tms340x0_device::sub_xy_b, |
| 697 | | &tms340x0_device::sub_xy_a, &tms340x0_device::sub_xy_b, &tms340x0_device::sub_xy_a, &tms340x0_device::sub_xy_b, &tms340x0_device::sub_xy_a, &tms340x0_device::sub_xy_b, &tms340x0_device::sub_xy_a, &tms340x0_device::sub_xy_b, |
| 698 | | /* 0xe400 */ |
| 699 | | &tms340x0_device::cmp_xy_a, &tms340x0_device::cmp_xy_b, &tms340x0_device::cmp_xy_a, &tms340x0_device::cmp_xy_b, &tms340x0_device::cmp_xy_a, &tms340x0_device::cmp_xy_b, &tms340x0_device::cmp_xy_a, &tms340x0_device::cmp_xy_b, |
| 700 | | &tms340x0_device::cmp_xy_a, &tms340x0_device::cmp_xy_b, &tms340x0_device::cmp_xy_a, &tms340x0_device::cmp_xy_b, &tms340x0_device::cmp_xy_a, &tms340x0_device::cmp_xy_b, &tms340x0_device::cmp_xy_a, &tms340x0_device::cmp_xy_b, |
| 701 | | /* 0xe500 */ |
| 702 | | &tms340x0_device::cmp_xy_a, &tms340x0_device::cmp_xy_b, &tms340x0_device::cmp_xy_a, &tms340x0_device::cmp_xy_b, &tms340x0_device::cmp_xy_a, &tms340x0_device::cmp_xy_b, &tms340x0_device::cmp_xy_a, &tms340x0_device::cmp_xy_b, |
| 703 | | &tms340x0_device::cmp_xy_a, &tms340x0_device::cmp_xy_b, &tms340x0_device::cmp_xy_a, &tms340x0_device::cmp_xy_b, &tms340x0_device::cmp_xy_a, &tms340x0_device::cmp_xy_b, &tms340x0_device::cmp_xy_a, &tms340x0_device::cmp_xy_b, |
| 704 | | /* 0xe600 */ |
| 705 | | &tms340x0_device::cpw_a, &tms340x0_device::cpw_b, &tms340x0_device::cpw_a, &tms340x0_device::cpw_b, &tms340x0_device::cpw_a, &tms340x0_device::cpw_b, &tms340x0_device::cpw_a, &tms340x0_device::cpw_b, |
| 706 | | &tms340x0_device::cpw_a, &tms340x0_device::cpw_b, &tms340x0_device::cpw_a, &tms340x0_device::cpw_b, &tms340x0_device::cpw_a, &tms340x0_device::cpw_b, &tms340x0_device::cpw_a, &tms340x0_device::cpw_b, |
| 707 | | /* 0xe700 */ |
| 708 | | &tms340x0_device::cpw_a, &tms340x0_device::cpw_b, &tms340x0_device::cpw_a, &tms340x0_device::cpw_b, &tms340x0_device::cpw_a, &tms340x0_device::cpw_b, &tms340x0_device::cpw_a, &tms340x0_device::cpw_b, |
| 709 | | &tms340x0_device::cpw_a, &tms340x0_device::cpw_b, &tms340x0_device::cpw_a, &tms340x0_device::cpw_b, &tms340x0_device::cpw_a, &tms340x0_device::cpw_b, &tms340x0_device::cpw_a, &tms340x0_device::cpw_b, |
| 710 | | /* 0xe800 */ |
| 711 | | &tms340x0_device::cvxyl_a, &tms340x0_device::cvxyl_b, &tms340x0_device::cvxyl_a, &tms340x0_device::cvxyl_b, &tms340x0_device::cvxyl_a, &tms340x0_device::cvxyl_b, &tms340x0_device::cvxyl_a, &tms340x0_device::cvxyl_b, |
| 712 | | &tms340x0_device::cvxyl_a, &tms340x0_device::cvxyl_b, &tms340x0_device::cvxyl_a, &tms340x0_device::cvxyl_b, &tms340x0_device::cvxyl_a, &tms340x0_device::cvxyl_b, &tms340x0_device::cvxyl_a, &tms340x0_device::cvxyl_b, |
| 713 | | /* 0xe900 */ |
| 714 | | &tms340x0_device::cvxyl_a, &tms340x0_device::cvxyl_b, &tms340x0_device::cvxyl_a, &tms340x0_device::cvxyl_b, &tms340x0_device::cvxyl_a, &tms340x0_device::cvxyl_b, &tms340x0_device::cvxyl_a, &tms340x0_device::cvxyl_b, |
| 715 | | &tms340x0_device::cvxyl_a, &tms340x0_device::cvxyl_b, &tms340x0_device::cvxyl_a, &tms340x0_device::cvxyl_b, &tms340x0_device::cvxyl_a, &tms340x0_device::cvxyl_b, &tms340x0_device::cvxyl_a, &tms340x0_device::cvxyl_b, |
| 716 | | /* 0xea00 */ |
| 717 | | &tms340x0_device::cvsxyl_a, &tms340x0_device::cvsxyl_b, &tms340x0_device::cvsxyl_a, &tms340x0_device::cvsxyl_b, &tms340x0_device::cvsxyl_a, &tms340x0_device::cvsxyl_b, &tms340x0_device::cvsxyl_a, &tms340x0_device::cvsxyl_b, |
| 718 | | &tms340x0_device::cvsxyl_a, &tms340x0_device::cvsxyl_b, &tms340x0_device::cvsxyl_a, &tms340x0_device::cvsxyl_b, &tms340x0_device::cvsxyl_a, &tms340x0_device::cvsxyl_b, &tms340x0_device::cvsxyl_a, &tms340x0_device::cvsxyl_b, |
| 719 | | /* 0xeb00 */ |
| 720 | | &tms340x0_device::cvsxyl_a, &tms340x0_device::cvsxyl_b, &tms340x0_device::cvsxyl_a, &tms340x0_device::cvsxyl_b, &tms340x0_device::cvsxyl_a, &tms340x0_device::cvsxyl_b, &tms340x0_device::cvsxyl_a, &tms340x0_device::cvsxyl_b, |
| 721 | | &tms340x0_device::cvsxyl_a, &tms340x0_device::cvsxyl_b, &tms340x0_device::cvsxyl_a, &tms340x0_device::cvsxyl_b, &tms340x0_device::cvsxyl_a, &tms340x0_device::cvsxyl_b, &tms340x0_device::cvsxyl_a, &tms340x0_device::cvsxyl_b, |
| 722 | | /* 0xec00 */ |
| 723 | | &tms340x0_device::movx_a, &tms340x0_device::movx_b, &tms340x0_device::movx_a, &tms340x0_device::movx_b, &tms340x0_device::movx_a, &tms340x0_device::movx_b, &tms340x0_device::movx_a, &tms340x0_device::movx_b, |
| 724 | | &tms340x0_device::movx_a, &tms340x0_device::movx_b, &tms340x0_device::movx_a, &tms340x0_device::movx_b, &tms340x0_device::movx_a, &tms340x0_device::movx_b, &tms340x0_device::movx_a, &tms340x0_device::movx_b, |
| 725 | | /* 0xed00 */ |
| 726 | | &tms340x0_device::movx_a, &tms340x0_device::movx_b, &tms340x0_device::movx_a, &tms340x0_device::movx_b, &tms340x0_device::movx_a, &tms340x0_device::movx_b, &tms340x0_device::movx_a, &tms340x0_device::movx_b, |
| 727 | | &tms340x0_device::movx_a, &tms340x0_device::movx_b, &tms340x0_device::movx_a, &tms340x0_device::movx_b, &tms340x0_device::movx_a, &tms340x0_device::movx_b, &tms340x0_device::movx_a, &tms340x0_device::movx_b, |
| 728 | | /* 0xee00 */ |
| 729 | | &tms340x0_device::movy_a, &tms340x0_device::movy_b, &tms340x0_device::movy_a, &tms340x0_device::movy_b, &tms340x0_device::movy_a, &tms340x0_device::movy_b, &tms340x0_device::movy_a, &tms340x0_device::movy_b, |
| 730 | | &tms340x0_device::movy_a, &tms340x0_device::movy_b, &tms340x0_device::movy_a, &tms340x0_device::movy_b, &tms340x0_device::movy_a, &tms340x0_device::movy_b, &tms340x0_device::movy_a, &tms340x0_device::movy_b, |
| 731 | | /* 0xef00 */ |
| 732 | | &tms340x0_device::movy_a, &tms340x0_device::movy_b, &tms340x0_device::movy_a, &tms340x0_device::movy_b, &tms340x0_device::movy_a, &tms340x0_device::movy_b, &tms340x0_device::movy_a, &tms340x0_device::movy_b, |
| 733 | | &tms340x0_device::movy_a, &tms340x0_device::movy_b, &tms340x0_device::movy_a, &tms340x0_device::movy_b, &tms340x0_device::movy_a, &tms340x0_device::movy_b, &tms340x0_device::movy_a, &tms340x0_device::movy_b, |
| 734 | | /* 0xf000 */ |
| 735 | | &tms340x0_device::pixt_rixy_a, &tms340x0_device::pixt_rixy_b, &tms340x0_device::pixt_rixy_a, &tms340x0_device::pixt_rixy_b, &tms340x0_device::pixt_rixy_a, &tms340x0_device::pixt_rixy_b, &tms340x0_device::pixt_rixy_a, &tms340x0_device::pixt_rixy_b, |
| 736 | | &tms340x0_device::pixt_rixy_a, &tms340x0_device::pixt_rixy_b, &tms340x0_device::pixt_rixy_a, &tms340x0_device::pixt_rixy_b, &tms340x0_device::pixt_rixy_a, &tms340x0_device::pixt_rixy_b, &tms340x0_device::pixt_rixy_a, &tms340x0_device::pixt_rixy_b, |
| 737 | | /* 0xf100 */ |
| 738 | | &tms340x0_device::pixt_rixy_a, &tms340x0_device::pixt_rixy_b, &tms340x0_device::pixt_rixy_a, &tms340x0_device::pixt_rixy_b, &tms340x0_device::pixt_rixy_a, &tms340x0_device::pixt_rixy_b, &tms340x0_device::pixt_rixy_a, &tms340x0_device::pixt_rixy_b, |
| 739 | | &tms340x0_device::pixt_rixy_a, &tms340x0_device::pixt_rixy_b, &tms340x0_device::pixt_rixy_a, &tms340x0_device::pixt_rixy_b, &tms340x0_device::pixt_rixy_a, &tms340x0_device::pixt_rixy_b, &tms340x0_device::pixt_rixy_a, &tms340x0_device::pixt_rixy_b, |
| 740 | | /* 0xf200 */ |
| 741 | | &tms340x0_device::pixt_ixyr_a, &tms340x0_device::pixt_ixyr_b, &tms340x0_device::pixt_ixyr_a, &tms340x0_device::pixt_ixyr_b, &tms340x0_device::pixt_ixyr_a, &tms340x0_device::pixt_ixyr_b, &tms340x0_device::pixt_ixyr_a, &tms340x0_device::pixt_ixyr_b, |
| 742 | | &tms340x0_device::pixt_ixyr_a, &tms340x0_device::pixt_ixyr_b, &tms340x0_device::pixt_ixyr_a, &tms340x0_device::pixt_ixyr_b, &tms340x0_device::pixt_ixyr_a, &tms340x0_device::pixt_ixyr_b, &tms340x0_device::pixt_ixyr_a, &tms340x0_device::pixt_ixyr_b, |
| 743 | | /* 0xf300 */ |
| 744 | | &tms340x0_device::pixt_ixyr_a, &tms340x0_device::pixt_ixyr_b, &tms340x0_device::pixt_ixyr_a, &tms340x0_device::pixt_ixyr_b, &tms340x0_device::pixt_ixyr_a, &tms340x0_device::pixt_ixyr_b, &tms340x0_device::pixt_ixyr_a, &tms340x0_device::pixt_ixyr_b, |
| 745 | | &tms340x0_device::pixt_ixyr_a, &tms340x0_device::pixt_ixyr_b, &tms340x0_device::pixt_ixyr_a, &tms340x0_device::pixt_ixyr_b, &tms340x0_device::pixt_ixyr_a, &tms340x0_device::pixt_ixyr_b, &tms340x0_device::pixt_ixyr_a, &tms340x0_device::pixt_ixyr_b, |
| 746 | | /* 0xf400 */ |
| 747 | | &tms340x0_device::pixt_ixyixy_a, &tms340x0_device::pixt_ixyixy_b, &tms340x0_device::pixt_ixyixy_a, &tms340x0_device::pixt_ixyixy_b, &tms340x0_device::pixt_ixyixy_a, &tms340x0_device::pixt_ixyixy_b, &tms340x0_device::pixt_ixyixy_a, &tms340x0_device::pixt_ixyixy_b, |
| 748 | | &tms340x0_device::pixt_ixyixy_a, &tms340x0_device::pixt_ixyixy_b, &tms340x0_device::pixt_ixyixy_a, &tms340x0_device::pixt_ixyixy_b, &tms340x0_device::pixt_ixyixy_a, &tms340x0_device::pixt_ixyixy_b, &tms340x0_device::pixt_ixyixy_a, &tms340x0_device::pixt_ixyixy_b, |
| 749 | | /* 0xf500 */ |
| 750 | | &tms340x0_device::pixt_ixyixy_a, &tms340x0_device::pixt_ixyixy_b, &tms340x0_device::pixt_ixyixy_a, &tms340x0_device::pixt_ixyixy_b, &tms340x0_device::pixt_ixyixy_a, &tms340x0_device::pixt_ixyixy_b, &tms340x0_device::pixt_ixyixy_a, &tms340x0_device::pixt_ixyixy_b, |
| 751 | | &tms340x0_device::pixt_ixyixy_a, &tms340x0_device::pixt_ixyixy_b, &tms340x0_device::pixt_ixyixy_a, &tms340x0_device::pixt_ixyixy_b, &tms340x0_device::pixt_ixyixy_a, &tms340x0_device::pixt_ixyixy_b, &tms340x0_device::pixt_ixyixy_a, &tms340x0_device::pixt_ixyixy_b, |
| 752 | | /* 0xf600 */ |
| 753 | | &tms340x0_device::drav_a, &tms340x0_device::drav_b, &tms340x0_device::drav_a, &tms340x0_device::drav_b, &tms340x0_device::drav_a, &tms340x0_device::drav_b, &tms340x0_device::drav_a, &tms340x0_device::drav_b, |
| 754 | | &tms340x0_device::drav_a, &tms340x0_device::drav_b, &tms340x0_device::drav_a, &tms340x0_device::drav_b, &tms340x0_device::drav_a, &tms340x0_device::drav_b, &tms340x0_device::drav_a, &tms340x0_device::drav_b, |
| 755 | | /* 0xf700 */ |
| 756 | | &tms340x0_device::drav_a, &tms340x0_device::drav_b, &tms340x0_device::drav_a, &tms340x0_device::drav_b, &tms340x0_device::drav_a, &tms340x0_device::drav_b, &tms340x0_device::drav_a, &tms340x0_device::drav_b, |
| 757 | | &tms340x0_device::drav_a, &tms340x0_device::drav_b, &tms340x0_device::drav_a, &tms340x0_device::drav_b, &tms340x0_device::drav_a, &tms340x0_device::drav_b, &tms340x0_device::drav_a, &tms340x0_device::drav_b, |
| 758 | | /* 0xf800 */ |
| 759 | | &tms340x0_device::pixt_ri_a, &tms340x0_device::pixt_ri_b, &tms340x0_device::pixt_ri_a, &tms340x0_device::pixt_ri_b, &tms340x0_device::pixt_ri_a, &tms340x0_device::pixt_ri_b, &tms340x0_device::pixt_ri_a, &tms340x0_device::pixt_ri_b, |
| 760 | | &tms340x0_device::pixt_ri_a, &tms340x0_device::pixt_ri_b, &tms340x0_device::pixt_ri_a, &tms340x0_device::pixt_ri_b, &tms340x0_device::pixt_ri_a, &tms340x0_device::pixt_ri_b, &tms340x0_device::pixt_ri_a, &tms340x0_device::pixt_ri_b, |
| 761 | | /* 0xf900 */ |
| 762 | | &tms340x0_device::pixt_ri_a, &tms340x0_device::pixt_ri_b, &tms340x0_device::pixt_ri_a, &tms340x0_device::pixt_ri_b, &tms340x0_device::pixt_ri_a, &tms340x0_device::pixt_ri_b, &tms340x0_device::pixt_ri_a, &tms340x0_device::pixt_ri_b, |
| 763 | | &tms340x0_device::pixt_ri_a, &tms340x0_device::pixt_ri_b, &tms340x0_device::pixt_ri_a, &tms340x0_device::pixt_ri_b, &tms340x0_device::pixt_ri_a, &tms340x0_device::pixt_ri_b, &tms340x0_device::pixt_ri_a, &tms340x0_device::pixt_ri_b, |
| 764 | | /* 0xfa00 */ |
| 765 | | &tms340x0_device::pixt_ir_a, &tms340x0_device::pixt_ir_b, &tms340x0_device::pixt_ir_a, &tms340x0_device::pixt_ir_b, &tms340x0_device::pixt_ir_a, &tms340x0_device::pixt_ir_b, &tms340x0_device::pixt_ir_a, &tms340x0_device::pixt_ir_b, |
| 766 | | &tms340x0_device::pixt_ir_a, &tms340x0_device::pixt_ir_b, &tms340x0_device::pixt_ir_a, &tms340x0_device::pixt_ir_b, &tms340x0_device::pixt_ir_a, &tms340x0_device::pixt_ir_b, &tms340x0_device::pixt_ir_a, &tms340x0_device::pixt_ir_b, |
| 767 | | /* 0xfb00 */ |
| 768 | | &tms340x0_device::pixt_ir_a, &tms340x0_device::pixt_ir_b, &tms340x0_device::pixt_ir_a, &tms340x0_device::pixt_ir_b, &tms340x0_device::pixt_ir_a, &tms340x0_device::pixt_ir_b, &tms340x0_device::pixt_ir_a, &tms340x0_device::pixt_ir_b, |
| 769 | | &tms340x0_device::pixt_ir_a, &tms340x0_device::pixt_ir_b, &tms340x0_device::pixt_ir_a, &tms340x0_device::pixt_ir_b, &tms340x0_device::pixt_ir_a, &tms340x0_device::pixt_ir_b, &tms340x0_device::pixt_ir_a, &tms340x0_device::pixt_ir_b, |
| 770 | | /* 0xfc00 */ |
| 771 | | &tms340x0_device::pixt_ii_a, &tms340x0_device::pixt_ii_b, &tms340x0_device::pixt_ii_a, &tms340x0_device::pixt_ii_b, &tms340x0_device::pixt_ii_a, &tms340x0_device::pixt_ii_b, &tms340x0_device::pixt_ii_a, &tms340x0_device::pixt_ii_b, |
| 772 | | &tms340x0_device::pixt_ii_a, &tms340x0_device::pixt_ii_b, &tms340x0_device::pixt_ii_a, &tms340x0_device::pixt_ii_b, &tms340x0_device::pixt_ii_a, &tms340x0_device::pixt_ii_b, &tms340x0_device::pixt_ii_a, &tms340x0_device::pixt_ii_b, |
| 773 | | /* 0xfd00 */ |
| 774 | | &tms340x0_device::pixt_ii_a, &tms340x0_device::pixt_ii_b, &tms340x0_device::pixt_ii_a, &tms340x0_device::pixt_ii_b, &tms340x0_device::pixt_ii_a, &tms340x0_device::pixt_ii_b, &tms340x0_device::pixt_ii_a, &tms340x0_device::pixt_ii_b, |
| 775 | | &tms340x0_device::pixt_ii_a, &tms340x0_device::pixt_ii_b, &tms340x0_device::pixt_ii_a, &tms340x0_device::pixt_ii_b, &tms340x0_device::pixt_ii_a, &tms340x0_device::pixt_ii_b, &tms340x0_device::pixt_ii_a, &tms340x0_device::pixt_ii_b, |
| 776 | | /* 0xfe00 */ |
| 777 | | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 778 | | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 779 | | /* 0xff00 */ |
| 780 | | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 781 | | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl |
| 782 | | }; |
trunk/src/devices/cpu/tms34010/34010tbl.inc
| r0 | r250222 | |
|---|
| 1 | // license:BSD-3-Clause |
| 2 | // copyright-holders:Alex Pasadyn,Zsolt Vasvari |
| 3 | /*** TMS34010: Portable TMS34010 emulator *********************************** |
| 4 | |
| 5 | Copyright Alex Pasadyn/Zsolt Vasvari |
| 6 | |
| 7 | Opcode Table |
| 8 | |
| 9 | *****************************************************************************/ |
| 10 | |
| 11 | /* Opcode Table */ |
| 12 | const tms340x0_device::opcode_func tms340x0_device::s_opcode_table[65536 >> 4] = |
| 13 | { |
| 14 | /* 0x0000 0x0010 0x0020 0x0030 ... 0x00f0 */ |
| 15 | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::rev_a, &tms340x0_device::rev_b, &tms340x0_device::idle, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 16 | &tms340x0_device::mwait, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::blmove, |
| 17 | /* 0x0100 */ |
| 18 | &tms340x0_device::emu, &tms340x0_device::unimpl, &tms340x0_device::exgpc_a, &tms340x0_device::exgpc_b, &tms340x0_device::getpc_a, &tms340x0_device::getpc_b, &tms340x0_device::jump_a, &tms340x0_device::jump_b, |
| 19 | &tms340x0_device::getst_a, &tms340x0_device::getst_b, &tms340x0_device::putst_a, &tms340x0_device::putst_b, &tms340x0_device::popst, &tms340x0_device::unimpl, &tms340x0_device::pushst, &tms340x0_device::unimpl, |
| 20 | /* 0x0200 */ |
| 21 | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::setcsp, &tms340x0_device::unimpl, &tms340x0_device::setcdp, |
| 22 | &tms340x0_device::rpix_a, &tms340x0_device::rpix_b, &tms340x0_device::exgps_a, &tms340x0_device::exgps_b, &tms340x0_device::getps_a, &tms340x0_device::getps_b, &tms340x0_device::unimpl, &tms340x0_device::setcmp, |
| 23 | /* 0x0300 */ |
| 24 | &tms340x0_device::nop, &tms340x0_device::unimpl, &tms340x0_device::clrc, &tms340x0_device::unimpl, &tms340x0_device::movb_aa, &tms340x0_device::unimpl, &tms340x0_device::dint, &tms340x0_device::unimpl, |
| 25 | &tms340x0_device::abs_a, &tms340x0_device::abs_b, &tms340x0_device::neg_a, &tms340x0_device::neg_b, &tms340x0_device::negb_a, &tms340x0_device::negb_b, &tms340x0_device::not_a, &tms340x0_device::not_b, |
| 26 | /* 0x0400 */ |
| 27 | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 28 | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 29 | /* 0x0500 */ |
| 30 | &tms340x0_device::sext0_a, &tms340x0_device::sext0_b, &tms340x0_device::zext0_a, &tms340x0_device::zext0_b, &tms340x0_device::setf0, &tms340x0_device::setf0, &tms340x0_device::setf0, &tms340x0_device::setf0, |
| 31 | &tms340x0_device::move0_ra_a, &tms340x0_device::move0_ra_b, &tms340x0_device::move0_ar_a, &tms340x0_device::move0_ar_b, &tms340x0_device::move0_aa, &tms340x0_device::unimpl, &tms340x0_device::movb_ra_a, &tms340x0_device::movb_ra_b, |
| 32 | /* 0x0600 */ |
| 33 | &tms340x0_device::cexec_l, &tms340x0_device::unimpl, &tms340x0_device::cmovgc_a, &tms340x0_device::cmovgc_b, &tms340x0_device::cmovgc_a_s, &tms340x0_device::cmovgc_b_s, &tms340x0_device::cmovcg_a, &tms340x0_device::cmovcg_b, |
| 34 | &tms340x0_device::cmovmc_f, &tms340x0_device::cmovmc_f, &tms340x0_device::cmovcm_f, &tms340x0_device::cmovcm_f, &tms340x0_device::cmovcm_b, &tms340x0_device::cmovcm_b, &tms340x0_device::cmovmc_f_va,&tms340x0_device::cmovmc_f_vb, |
| 35 | /* 0x0700 */ |
| 36 | &tms340x0_device::sext1_a, &tms340x0_device::sext1_b, &tms340x0_device::zext1_a, &tms340x0_device::zext1_b, &tms340x0_device::setf1, &tms340x0_device::setf1, &tms340x0_device::setf1, &tms340x0_device::setf1, |
| 37 | &tms340x0_device::move1_ra_a, &tms340x0_device::move1_ra_b, &tms340x0_device::move1_ar_a, &tms340x0_device::move1_ar_b, &tms340x0_device::move1_aa, &tms340x0_device::unimpl, &tms340x0_device::movb_ar_a, &tms340x0_device::movb_ar_b, |
| 38 | /* 0x0800 */ |
| 39 | &tms340x0_device::trapl, &tms340x0_device::unimpl, &tms340x0_device::cmovmc_b, &tms340x0_device::cmovmc_b, &tms340x0_device::unimpl, &tms340x0_device::vblt_b_l, &tms340x0_device::retm, &tms340x0_device::unimpl, |
| 40 | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::clip, |
| 41 | /* 0x0900 */ |
| 42 | &tms340x0_device::trap, &tms340x0_device::trap, &tms340x0_device::call_a, &tms340x0_device::call_b, &tms340x0_device::reti, &tms340x0_device::unimpl, &tms340x0_device::rets, &tms340x0_device::rets, |
| 43 | &tms340x0_device::mmtm_a, &tms340x0_device::mmtm_b, &tms340x0_device::mmfm_a, &tms340x0_device::mmfm_b, &tms340x0_device::movi_w_a, &tms340x0_device::movi_w_b, &tms340x0_device::movi_l_a, &tms340x0_device::movi_l_b, |
| 44 | /* 0x0a00 */ |
| 45 | &tms340x0_device::vlcol, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::pfill_xy, &tms340x0_device::unimpl, &tms340x0_device::vfill_l, &tms340x0_device::cvmxyl_a, &tms340x0_device::cvmxyl_b, |
| 46 | &tms340x0_device::cvdxyl_a, &tms340x0_device::cvdxyl_b, &tms340x0_device::unimpl, &tms340x0_device::fpixeq, &tms340x0_device::unimpl, &tms340x0_device::fpixne, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 47 | /* 0x0b00 */ |
| 48 | &tms340x0_device::addi_w_a, &tms340x0_device::addi_w_b, &tms340x0_device::addi_l_a, &tms340x0_device::addi_l_b, &tms340x0_device::cmpi_w_a, &tms340x0_device::cmpi_w_b, &tms340x0_device::cmpi_l_a, &tms340x0_device::cmpi_l_b, |
| 49 | &tms340x0_device::andi_a, &tms340x0_device::andi_b, &tms340x0_device::ori_a, &tms340x0_device::ori_b, &tms340x0_device::xori_a, &tms340x0_device::xori_b, &tms340x0_device::subi_w_a, &tms340x0_device::subi_w_b, |
| 50 | /* 0x0c00 */ |
| 51 | &tms340x0_device::addxyi_a, &tms340x0_device::addxyi_b, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::linit, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 52 | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 53 | /* 0x0d00 */ |
| 54 | &tms340x0_device::subi_l_a, &tms340x0_device::subi_l_b, &tms340x0_device::unimpl, &tms340x0_device::callr, &tms340x0_device::unimpl, &tms340x0_device::calla, &tms340x0_device::eint, &tms340x0_device::unimpl, |
| 55 | &tms340x0_device::dsj_a, &tms340x0_device::dsj_b, &tms340x0_device::dsjeq_a, &tms340x0_device::dsjeq_b, &tms340x0_device::dsjne_a, &tms340x0_device::dsjne_b, &tms340x0_device::setc, &tms340x0_device::unimpl, |
| 56 | /* 0x0e00 */ |
| 57 | &tms340x0_device::unimpl, &tms340x0_device::pixblt_l_m_l,&tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 58 | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::tfill_xy, |
| 59 | /* 0x0f00 */ |
| 60 | &tms340x0_device::pixblt_l_l, &tms340x0_device::unimpl, &tms340x0_device::pixblt_l_xy,&tms340x0_device::unimpl, &tms340x0_device::pixblt_xy_l,&tms340x0_device::unimpl, &tms340x0_device::pixblt_xy_xy,&tms340x0_device::unimpl, |
| 61 | &tms340x0_device::pixblt_b_l, &tms340x0_device::unimpl, &tms340x0_device::pixblt_b_xy,&tms340x0_device::unimpl, &tms340x0_device::fill_l, &tms340x0_device::unimpl, &tms340x0_device::fill_xy, &tms340x0_device::unimpl, |
| 62 | /* 0x1000 */ |
| 63 | &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, |
| 64 | &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, |
| 65 | /* 0x1100 */ |
| 66 | &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, |
| 67 | &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, |
| 68 | /* 0x1200 */ |
| 69 | &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, |
| 70 | &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, |
| 71 | /* 0x1300 */ |
| 72 | &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, |
| 73 | &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, &tms340x0_device::addk_a, &tms340x0_device::addk_b, |
| 74 | /* 0x1400 */ |
| 75 | &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, |
| 76 | &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, |
| 77 | /* 0x1500 */ |
| 78 | &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, |
| 79 | &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, |
| 80 | /* 0x1600 */ |
| 81 | &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, |
| 82 | &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, |
| 83 | /* 0x1700 */ |
| 84 | &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, |
| 85 | &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, &tms340x0_device::subk_a, &tms340x0_device::subk_b, |
| 86 | /* 0x1800 */ |
| 87 | &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, |
| 88 | &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, |
| 89 | /* 0x1900 */ |
| 90 | &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, |
| 91 | &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, |
| 92 | /* 0x1a00 */ |
| 93 | &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, |
| 94 | &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, |
| 95 | /* 0x1b00 */ |
| 96 | &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, |
| 97 | &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, &tms340x0_device::movk_a, &tms340x0_device::movk_b, |
| 98 | /* 0x1c00 */ |
| 99 | &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, |
| 100 | &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, |
| 101 | /* 0x1d00 */ |
| 102 | &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, |
| 103 | &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, |
| 104 | /* 0x1e00 */ |
| 105 | &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, |
| 106 | &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, |
| 107 | /* 0x1f00 */ |
| 108 | &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, |
| 109 | &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, &tms340x0_device::btst_k_a, &tms340x0_device::btst_k_b, |
| 110 | /* 0x2000 */ |
| 111 | &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, |
| 112 | &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, |
| 113 | /* 0x2100 */ |
| 114 | &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, |
| 115 | &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, |
| 116 | /* 0x2200 */ |
| 117 | &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, |
| 118 | &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, |
| 119 | /* 0x2300 */ |
| 120 | &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, |
| 121 | &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, &tms340x0_device::sla_k_a, &tms340x0_device::sla_k_b, |
| 122 | /* 0x2400 */ |
| 123 | &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, |
| 124 | &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, |
| 125 | /* 0x2500 */ |
| 126 | &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, |
| 127 | &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, |
| 128 | /* 0x2600 */ |
| 129 | &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, |
| 130 | &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, |
| 131 | /* 0x2700 */ |
| 132 | &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, |
| 133 | &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, &tms340x0_device::sll_k_a, &tms340x0_device::sll_k_b, |
| 134 | /* 0x2800 */ |
| 135 | &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, |
| 136 | &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, |
| 137 | /* 0x2900 */ |
| 138 | &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, |
| 139 | &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, |
| 140 | /* 0x2a00 */ |
| 141 | &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, |
| 142 | &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, |
| 143 | /* 0x2b00 */ |
| 144 | &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, |
| 145 | &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, &tms340x0_device::sra_k_a, &tms340x0_device::sra_k_b, |
| 146 | /* 0x2c00 */ |
| 147 | &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, |
| 148 | &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, |
| 149 | /* 0x2d00 */ |
| 150 | &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, |
| 151 | &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, |
| 152 | /* 0x2e00 */ |
| 153 | &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, |
| 154 | &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, |
| 155 | /* 0x2f00 */ |
| 156 | &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, |
| 157 | &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, &tms340x0_device::srl_k_a, &tms340x0_device::srl_k_b, |
| 158 | /* 0x3000 */ |
| 159 | &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, |
| 160 | &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, |
| 161 | /* 0x3100 */ |
| 162 | &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, |
| 163 | &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, |
| 164 | /* 0x3200 */ |
| 165 | &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, |
| 166 | &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, |
| 167 | /* 0x3300 */ |
| 168 | &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, |
| 169 | &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, &tms340x0_device::rl_k_a, &tms340x0_device::rl_k_b, |
| 170 | /* 0x3400 */ |
| 171 | &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, |
| 172 | &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, |
| 173 | /* 0x3500 */ |
| 174 | &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, |
| 175 | &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, |
| 176 | /* 0x3600 */ |
| 177 | &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, |
| 178 | &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, |
| 179 | /* 0x3700 */ |
| 180 | &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, |
| 181 | &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, &tms340x0_device::cmp_k_a, &tms340x0_device::cmp_k_b, |
| 182 | /* 0x3800 */ |
| 183 | &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, |
| 184 | &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, |
| 185 | /* 0x3900 */ |
| 186 | &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, |
| 187 | &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, |
| 188 | /* 0x3a00 */ |
| 189 | &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, |
| 190 | &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, |
| 191 | /* 0x3b00 */ |
| 192 | &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, |
| 193 | &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, |
| 194 | /* 0x3c00 */ |
| 195 | &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, |
| 196 | &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, |
| 197 | /* 0x3d00 */ |
| 198 | &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, |
| 199 | &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, |
| 200 | /* 0x3e00 */ |
| 201 | &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, |
| 202 | &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, |
| 203 | /* 0x3f00 */ |
| 204 | &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, |
| 205 | &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, &tms340x0_device::dsjs_a, &tms340x0_device::dsjs_b, |
| 206 | /* 0x4000 */ |
| 207 | &tms340x0_device::add_a, &tms340x0_device::add_b, &tms340x0_device::add_a, &tms340x0_device::add_b, &tms340x0_device::add_a, &tms340x0_device::add_b, &tms340x0_device::add_a, &tms340x0_device::add_b, |
| 208 | &tms340x0_device::add_a, &tms340x0_device::add_b, &tms340x0_device::add_a, &tms340x0_device::add_b, &tms340x0_device::add_a, &tms340x0_device::add_b, &tms340x0_device::add_a, &tms340x0_device::add_b, |
| 209 | /* 0x4100 */ |
| 210 | &tms340x0_device::add_a, &tms340x0_device::add_b, &tms340x0_device::add_a, &tms340x0_device::add_b, &tms340x0_device::add_a, &tms340x0_device::add_b, &tms340x0_device::add_a, &tms340x0_device::add_b, |
| 211 | &tms340x0_device::add_a, &tms340x0_device::add_b, &tms340x0_device::add_a, &tms340x0_device::add_b, &tms340x0_device::add_a, &tms340x0_device::add_b, &tms340x0_device::add_a, &tms340x0_device::add_b, |
| 212 | /* 0x4200 */ |
| 213 | &tms340x0_device::addc_a, &tms340x0_device::addc_b, &tms340x0_device::addc_a, &tms340x0_device::addc_b, &tms340x0_device::addc_a, &tms340x0_device::addc_b, &tms340x0_device::addc_a, &tms340x0_device::addc_b, |
| 214 | &tms340x0_device::addc_a, &tms340x0_device::addc_b, &tms340x0_device::addc_a, &tms340x0_device::addc_b, &tms340x0_device::addc_a, &tms340x0_device::addc_b, &tms340x0_device::addc_a, &tms340x0_device::addc_b, |
| 215 | /* 0x4300 */ |
| 216 | &tms340x0_device::addc_a, &tms340x0_device::addc_b, &tms340x0_device::addc_a, &tms340x0_device::addc_b, &tms340x0_device::addc_a, &tms340x0_device::addc_b, &tms340x0_device::addc_a, &tms340x0_device::addc_b, |
| 217 | &tms340x0_device::addc_a, &tms340x0_device::addc_b, &tms340x0_device::addc_a, &tms340x0_device::addc_b, &tms340x0_device::addc_a, &tms340x0_device::addc_b, &tms340x0_device::addc_a, &tms340x0_device::addc_b, |
| 218 | /* 0x4400 */ |
| 219 | &tms340x0_device::sub_a, &tms340x0_device::sub_b, &tms340x0_device::sub_a, &tms340x0_device::sub_b, &tms340x0_device::sub_a, &tms340x0_device::sub_b, &tms340x0_device::sub_a, &tms340x0_device::sub_b, |
| 220 | &tms340x0_device::sub_a, &tms340x0_device::sub_b, &tms340x0_device::sub_a, &tms340x0_device::sub_b, &tms340x0_device::sub_a, &tms340x0_device::sub_b, &tms340x0_device::sub_a, &tms340x0_device::sub_b, |
| 221 | /* 0x4500 */ |
| 222 | &tms340x0_device::sub_a, &tms340x0_device::sub_b, &tms340x0_device::sub_a, &tms340x0_device::sub_b, &tms340x0_device::sub_a, &tms340x0_device::sub_b, &tms340x0_device::sub_a, &tms340x0_device::sub_b, |
| 223 | &tms340x0_device::sub_a, &tms340x0_device::sub_b, &tms340x0_device::sub_a, &tms340x0_device::sub_b, &tms340x0_device::sub_a, &tms340x0_device::sub_b, &tms340x0_device::sub_a, &tms340x0_device::sub_b, |
| 224 | /* 0x4600 */ |
| 225 | &tms340x0_device::subb_a, &tms340x0_device::subb_b, &tms340x0_device::subb_a, &tms340x0_device::subb_b, &tms340x0_device::subb_a, &tms340x0_device::subb_b, &tms340x0_device::subb_a, &tms340x0_device::subb_b, |
| 226 | &tms340x0_device::subb_a, &tms340x0_device::subb_b, &tms340x0_device::subb_a, &tms340x0_device::subb_b, &tms340x0_device::subb_a, &tms340x0_device::subb_b, &tms340x0_device::subb_a, &tms340x0_device::subb_b, |
| 227 | /* 0x4700 */ |
| 228 | &tms340x0_device::subb_a, &tms340x0_device::subb_b, &tms340x0_device::subb_a, &tms340x0_device::subb_b, &tms340x0_device::subb_a, &tms340x0_device::subb_b, &tms340x0_device::subb_a, &tms340x0_device::subb_b, |
| 229 | &tms340x0_device::subb_a, &tms340x0_device::subb_b, &tms340x0_device::subb_a, &tms340x0_device::subb_b, &tms340x0_device::subb_a, &tms340x0_device::subb_b, &tms340x0_device::subb_a, &tms340x0_device::subb_b, |
| 230 | /* 0x4800 */ |
| 231 | &tms340x0_device::cmp_a, &tms340x0_device::cmp_b, &tms340x0_device::cmp_a, &tms340x0_device::cmp_b, &tms340x0_device::cmp_a, &tms340x0_device::cmp_b, &tms340x0_device::cmp_a, &tms340x0_device::cmp_b, |
| 232 | &tms340x0_device::cmp_a, &tms340x0_device::cmp_b, &tms340x0_device::cmp_a, &tms340x0_device::cmp_b, &tms340x0_device::cmp_a, &tms340x0_device::cmp_b, &tms340x0_device::cmp_a, &tms340x0_device::cmp_b, |
| 233 | /* 0x4900 */ |
| 234 | &tms340x0_device::cmp_a, &tms340x0_device::cmp_b, &tms340x0_device::cmp_a, &tms340x0_device::cmp_b, &tms340x0_device::cmp_a, &tms340x0_device::cmp_b, &tms340x0_device::cmp_a, &tms340x0_device::cmp_b, |
| 235 | &tms340x0_device::cmp_a, &tms340x0_device::cmp_b, &tms340x0_device::cmp_a, &tms340x0_device::cmp_b, &tms340x0_device::cmp_a, &tms340x0_device::cmp_b, &tms340x0_device::cmp_a, &tms340x0_device::cmp_b, |
| 236 | /* 0x4a00 */ |
| 237 | &tms340x0_device::btst_r_a, &tms340x0_device::btst_r_b, &tms340x0_device::btst_r_a, &tms340x0_device::btst_r_b, &tms340x0_device::btst_r_a, &tms340x0_device::btst_r_b, &tms340x0_device::btst_r_a, &tms340x0_device::btst_r_b, |
| 238 | &tms340x0_device::btst_r_a, &tms340x0_device::btst_r_b, &tms340x0_device::btst_r_a, &tms340x0_device::btst_r_b, &tms340x0_device::btst_r_a, &tms340x0_device::btst_r_b, &tms340x0_device::btst_r_a, &tms340x0_device::btst_r_b, |
| 239 | /* 0x4b00 */ |
| 240 | &tms340x0_device::btst_r_a, &tms340x0_device::btst_r_b, &tms340x0_device::btst_r_a, &tms340x0_device::btst_r_b, &tms340x0_device::btst_r_a, &tms340x0_device::btst_r_b, &tms340x0_device::btst_r_a, &tms340x0_device::btst_r_b, |
| 241 | &tms340x0_device::btst_r_a, &tms340x0_device::btst_r_b, &tms340x0_device::btst_r_a, &tms340x0_device::btst_r_b, &tms340x0_device::btst_r_a, &tms340x0_device::btst_r_b, &tms340x0_device::btst_r_a, &tms340x0_device::btst_r_b, |
| 242 | /* 0x4c00 */ |
| 243 | &tms340x0_device::move_rr_a, &tms340x0_device::move_rr_b, &tms340x0_device::move_rr_a, &tms340x0_device::move_rr_b, &tms340x0_device::move_rr_a, &tms340x0_device::move_rr_b, &tms340x0_device::move_rr_a, &tms340x0_device::move_rr_b, |
| 244 | &tms340x0_device::move_rr_a, &tms340x0_device::move_rr_b, &tms340x0_device::move_rr_a, &tms340x0_device::move_rr_b, &tms340x0_device::move_rr_a, &tms340x0_device::move_rr_b, &tms340x0_device::move_rr_a, &tms340x0_device::move_rr_b, |
| 245 | /* 0x4d00 */ |
| 246 | &tms340x0_device::move_rr_a, &tms340x0_device::move_rr_b, &tms340x0_device::move_rr_a, &tms340x0_device::move_rr_b, &tms340x0_device::move_rr_a, &tms340x0_device::move_rr_b, &tms340x0_device::move_rr_a, &tms340x0_device::move_rr_b, |
| 247 | &tms340x0_device::move_rr_a, &tms340x0_device::move_rr_b, &tms340x0_device::move_rr_a, &tms340x0_device::move_rr_b, &tms340x0_device::move_rr_a, &tms340x0_device::move_rr_b, &tms340x0_device::move_rr_a, &tms340x0_device::move_rr_b, |
| 248 | /* 0x4e00 */ |
| 249 | &tms340x0_device::move_rr_ax, &tms340x0_device::move_rr_bx, &tms340x0_device::move_rr_ax, &tms340x0_device::move_rr_bx, &tms340x0_device::move_rr_ax, &tms340x0_device::move_rr_bx, &tms340x0_device::move_rr_ax, &tms340x0_device::move_rr_bx, |
| 250 | &tms340x0_device::move_rr_ax, &tms340x0_device::move_rr_bx, &tms340x0_device::move_rr_ax, &tms340x0_device::move_rr_bx, &tms340x0_device::move_rr_ax, &tms340x0_device::move_rr_bx, &tms340x0_device::move_rr_ax, &tms340x0_device::move_rr_bx, |
| 251 | /* 0x4f00 */ |
| 252 | &tms340x0_device::move_rr_ax, &tms340x0_device::move_rr_bx, &tms340x0_device::move_rr_ax, &tms340x0_device::move_rr_bx, &tms340x0_device::move_rr_ax, &tms340x0_device::move_rr_bx, &tms340x0_device::move_rr_ax, &tms340x0_device::move_rr_bx, |
| 253 | &tms340x0_device::move_rr_ax, &tms340x0_device::move_rr_bx, &tms340x0_device::move_rr_ax, &tms340x0_device::move_rr_bx, &tms340x0_device::move_rr_ax, &tms340x0_device::move_rr_bx, &tms340x0_device::move_rr_ax, &tms340x0_device::move_rr_bx, |
| 254 | /* 0x5000 */ |
| 255 | &tms340x0_device::and_a, &tms340x0_device::and_b, &tms340x0_device::and_a, &tms340x0_device::and_b, &tms340x0_device::and_a, &tms340x0_device::and_b, &tms340x0_device::and_a, &tms340x0_device::and_b, |
| 256 | &tms340x0_device::and_a, &tms340x0_device::and_b, &tms340x0_device::and_a, &tms340x0_device::and_b, &tms340x0_device::and_a, &tms340x0_device::and_b, &tms340x0_device::and_a, &tms340x0_device::and_b, |
| 257 | /* 0x5100 */ |
| 258 | &tms340x0_device::and_a, &tms340x0_device::and_b, &tms340x0_device::and_a, &tms340x0_device::and_b, &tms340x0_device::and_a, &tms340x0_device::and_b, &tms340x0_device::and_a, &tms340x0_device::and_b, |
| 259 | &tms340x0_device::and_a, &tms340x0_device::and_b, &tms340x0_device::and_a, &tms340x0_device::and_b, &tms340x0_device::and_a, &tms340x0_device::and_b, &tms340x0_device::and_a, &tms340x0_device::and_b, |
| 260 | /* 0x5200 */ |
| 261 | &tms340x0_device::andn_a, &tms340x0_device::andn_b, &tms340x0_device::andn_a, &tms340x0_device::andn_b, &tms340x0_device::andn_a, &tms340x0_device::andn_b, &tms340x0_device::andn_a, &tms340x0_device::andn_b, |
| 262 | &tms340x0_device::andn_a, &tms340x0_device::andn_b, &tms340x0_device::andn_a, &tms340x0_device::andn_b, &tms340x0_device::andn_a, &tms340x0_device::andn_b, &tms340x0_device::andn_a, &tms340x0_device::andn_b, |
| 263 | /* 0x5300 */ |
| 264 | &tms340x0_device::andn_a, &tms340x0_device::andn_b, &tms340x0_device::andn_a, &tms340x0_device::andn_b, &tms340x0_device::andn_a, &tms340x0_device::andn_b, &tms340x0_device::andn_a, &tms340x0_device::andn_b, |
| 265 | &tms340x0_device::andn_a, &tms340x0_device::andn_b, &tms340x0_device::andn_a, &tms340x0_device::andn_b, &tms340x0_device::andn_a, &tms340x0_device::andn_b, &tms340x0_device::andn_a, &tms340x0_device::andn_b, |
| 266 | /* 0x5400 */ |
| 267 | &tms340x0_device::or_a, &tms340x0_device::or_b, &tms340x0_device::or_a, &tms340x0_device::or_b, &tms340x0_device::or_a, &tms340x0_device::or_b, &tms340x0_device::or_a, &tms340x0_device::or_b, |
| 268 | &tms340x0_device::or_a, &tms340x0_device::or_b, &tms340x0_device::or_a, &tms340x0_device::or_b, &tms340x0_device::or_a, &tms340x0_device::or_b, &tms340x0_device::or_a, &tms340x0_device::or_b, |
| 269 | /* 0x5500 */ |
| 270 | &tms340x0_device::or_a, &tms340x0_device::or_b, &tms340x0_device::or_a, &tms340x0_device::or_b, &tms340x0_device::or_a, &tms340x0_device::or_b, &tms340x0_device::or_a, &tms340x0_device::or_b, |
| 271 | &tms340x0_device::or_a, &tms340x0_device::or_b, &tms340x0_device::or_a, &tms340x0_device::or_b, &tms340x0_device::or_a, &tms340x0_device::or_b, &tms340x0_device::or_a, &tms340x0_device::or_b, |
| 272 | /* 0x5600 */ |
| 273 | &tms340x0_device::xor_a, &tms340x0_device::xor_b, &tms340x0_device::xor_a, &tms340x0_device::xor_b, &tms340x0_device::xor_a, &tms340x0_device::xor_b, &tms340x0_device::xor_a, &tms340x0_device::xor_b, |
| 274 | &tms340x0_device::xor_a, &tms340x0_device::xor_b, &tms340x0_device::xor_a, &tms340x0_device::xor_b, &tms340x0_device::xor_a, &tms340x0_device::xor_b, &tms340x0_device::xor_a, &tms340x0_device::xor_b, |
| 275 | /* 0x5700 */ |
| 276 | &tms340x0_device::xor_a, &tms340x0_device::xor_b, &tms340x0_device::xor_a, &tms340x0_device::xor_b, &tms340x0_device::xor_a, &tms340x0_device::xor_b, &tms340x0_device::xor_a, &tms340x0_device::xor_b, |
| 277 | &tms340x0_device::xor_a, &tms340x0_device::xor_b, &tms340x0_device::xor_a, &tms340x0_device::xor_b, &tms340x0_device::xor_a, &tms340x0_device::xor_b, &tms340x0_device::xor_a, &tms340x0_device::xor_b, |
| 278 | /* 0x5800 */ |
| 279 | &tms340x0_device::divs_a, &tms340x0_device::divs_b, &tms340x0_device::divs_a, &tms340x0_device::divs_b, &tms340x0_device::divs_a, &tms340x0_device::divs_b, &tms340x0_device::divs_a, &tms340x0_device::divs_b, |
| 280 | &tms340x0_device::divs_a, &tms340x0_device::divs_b, &tms340x0_device::divs_a, &tms340x0_device::divs_b, &tms340x0_device::divs_a, &tms340x0_device::divs_b, &tms340x0_device::divs_a, &tms340x0_device::divs_b, |
| 281 | /* 0x5900 */ |
| 282 | &tms340x0_device::divs_a, &tms340x0_device::divs_b, &tms340x0_device::divs_a, &tms340x0_device::divs_b, &tms340x0_device::divs_a, &tms340x0_device::divs_b, &tms340x0_device::divs_a, &tms340x0_device::divs_b, |
| 283 | &tms340x0_device::divs_a, &tms340x0_device::divs_b, &tms340x0_device::divs_a, &tms340x0_device::divs_b, &tms340x0_device::divs_a, &tms340x0_device::divs_b, &tms340x0_device::divs_a, &tms340x0_device::divs_b, |
| 284 | /* 0x5a00 */ |
| 285 | &tms340x0_device::divu_a, &tms340x0_device::divu_b, &tms340x0_device::divu_a, &tms340x0_device::divu_b, &tms340x0_device::divu_a, &tms340x0_device::divu_b, &tms340x0_device::divu_a, &tms340x0_device::divu_b, |
| 286 | &tms340x0_device::divu_a, &tms340x0_device::divu_b, &tms340x0_device::divu_a, &tms340x0_device::divu_b, &tms340x0_device::divu_a, &tms340x0_device::divu_b, &tms340x0_device::divu_a, &tms340x0_device::divu_b, |
| 287 | /* 0x5b00 */ |
| 288 | &tms340x0_device::divu_a, &tms340x0_device::divu_b, &tms340x0_device::divu_a, &tms340x0_device::divu_b, &tms340x0_device::divu_a, &tms340x0_device::divu_b, &tms340x0_device::divu_a, &tms340x0_device::divu_b, |
| 289 | &tms340x0_device::divu_a, &tms340x0_device::divu_b, &tms340x0_device::divu_a, &tms340x0_device::divu_b, &tms340x0_device::divu_a, &tms340x0_device::divu_b, &tms340x0_device::divu_a, &tms340x0_device::divu_b, |
| 290 | /* 0x5c00 */ |
| 291 | &tms340x0_device::mpys_a, &tms340x0_device::mpys_b, &tms340x0_device::mpys_a, &tms340x0_device::mpys_b, &tms340x0_device::mpys_a, &tms340x0_device::mpys_b, &tms340x0_device::mpys_a, &tms340x0_device::mpys_b, |
| 292 | &tms340x0_device::mpys_a, &tms340x0_device::mpys_b, &tms340x0_device::mpys_a, &tms340x0_device::mpys_b, &tms340x0_device::mpys_a, &tms340x0_device::mpys_b, &tms340x0_device::mpys_a, &tms340x0_device::mpys_b, |
| 293 | /* 0x5d00 */ |
| 294 | &tms340x0_device::mpys_a, &tms340x0_device::mpys_b, &tms340x0_device::mpys_a, &tms340x0_device::mpys_b, &tms340x0_device::mpys_a, &tms340x0_device::mpys_b, &tms340x0_device::mpys_a, &tms340x0_device::mpys_b, |
| 295 | &tms340x0_device::mpys_a, &tms340x0_device::mpys_b, &tms340x0_device::mpys_a, &tms340x0_device::mpys_b, &tms340x0_device::mpys_a, &tms340x0_device::mpys_b, &tms340x0_device::mpys_a, &tms340x0_device::mpys_b, |
| 296 | /* 0x5e00 */ |
| 297 | &tms340x0_device::mpyu_a, &tms340x0_device::mpyu_b, &tms340x0_device::mpyu_a, &tms340x0_device::mpyu_b, &tms340x0_device::mpyu_a, &tms340x0_device::mpyu_b, &tms340x0_device::mpyu_a, &tms340x0_device::mpyu_b, |
| 298 | &tms340x0_device::mpyu_a, &tms340x0_device::mpyu_b, &tms340x0_device::mpyu_a, &tms340x0_device::mpyu_b, &tms340x0_device::mpyu_a, &tms340x0_device::mpyu_b, &tms340x0_device::mpyu_a, &tms340x0_device::mpyu_b, |
| 299 | /* 0x5f00 */ |
| 300 | &tms340x0_device::mpyu_a, &tms340x0_device::mpyu_b, &tms340x0_device::mpyu_a, &tms340x0_device::mpyu_b, &tms340x0_device::mpyu_a, &tms340x0_device::mpyu_b, &tms340x0_device::mpyu_a, &tms340x0_device::mpyu_b, |
| 301 | &tms340x0_device::mpyu_a, &tms340x0_device::mpyu_b, &tms340x0_device::mpyu_a, &tms340x0_device::mpyu_b, &tms340x0_device::mpyu_a, &tms340x0_device::mpyu_b, &tms340x0_device::mpyu_a, &tms340x0_device::mpyu_b, |
| 302 | /* 0x6000 */ |
| 303 | &tms340x0_device::sla_r_a, &tms340x0_device::sla_r_b, &tms340x0_device::sla_r_a, &tms340x0_device::sla_r_b, &tms340x0_device::sla_r_a, &tms340x0_device::sla_r_b, &tms340x0_device::sla_r_a, &tms340x0_device::sla_r_b, |
| 304 | &tms340x0_device::sla_r_a, &tms340x0_device::sla_r_b, &tms340x0_device::sla_r_a, &tms340x0_device::sla_r_b, &tms340x0_device::sla_r_a, &tms340x0_device::sla_r_b, &tms340x0_device::sla_r_a, &tms340x0_device::sla_r_b, |
| 305 | /* 0x6100 */ |
| 306 | &tms340x0_device::sla_r_a, &tms340x0_device::sla_r_b, &tms340x0_device::sla_r_a, &tms340x0_device::sla_r_b, &tms340x0_device::sla_r_a, &tms340x0_device::sla_r_b, &tms340x0_device::sla_r_a, &tms340x0_device::sla_r_b, |
| 307 | &tms340x0_device::sla_r_a, &tms340x0_device::sla_r_b, &tms340x0_device::sla_r_a, &tms340x0_device::sla_r_b, &tms340x0_device::sla_r_a, &tms340x0_device::sla_r_b, &tms340x0_device::sla_r_a, &tms340x0_device::sla_r_b, |
| 308 | /* 0x6200 */ |
| 309 | &tms340x0_device::sll_r_a, &tms340x0_device::sll_r_b, &tms340x0_device::sll_r_a, &tms340x0_device::sll_r_b, &tms340x0_device::sll_r_a, &tms340x0_device::sll_r_b, &tms340x0_device::sll_r_a, &tms340x0_device::sll_r_b, |
| 310 | &tms340x0_device::sll_r_a, &tms340x0_device::sll_r_b, &tms340x0_device::sll_r_a, &tms340x0_device::sll_r_b, &tms340x0_device::sll_r_a, &tms340x0_device::sll_r_b, &tms340x0_device::sll_r_a, &tms340x0_device::sll_r_b, |
| 311 | /* 0x6300 */ |
| 312 | &tms340x0_device::sll_r_a, &tms340x0_device::sll_r_b, &tms340x0_device::sll_r_a, &tms340x0_device::sll_r_b, &tms340x0_device::sll_r_a, &tms340x0_device::sll_r_b, &tms340x0_device::sll_r_a, &tms340x0_device::sll_r_b, |
| 313 | &tms340x0_device::sll_r_a, &tms340x0_device::sll_r_b, &tms340x0_device::sll_r_a, &tms340x0_device::sll_r_b, &tms340x0_device::sll_r_a, &tms340x0_device::sll_r_b, &tms340x0_device::sll_r_a, &tms340x0_device::sll_r_b, |
| 314 | /* 0x6400 */ |
| 315 | &tms340x0_device::sra_r_a, &tms340x0_device::sra_r_b, &tms340x0_device::sra_r_a, &tms340x0_device::sra_r_b, &tms340x0_device::sra_r_a, &tms340x0_device::sra_r_b, &tms340x0_device::sra_r_a, &tms340x0_device::sra_r_b, |
| 316 | &tms340x0_device::sra_r_a, &tms340x0_device::sra_r_b, &tms340x0_device::sra_r_a, &tms340x0_device::sra_r_b, &tms340x0_device::sra_r_a, &tms340x0_device::sra_r_b, &tms340x0_device::sra_r_a, &tms340x0_device::sra_r_b, |
| 317 | /* 0x6500 */ |
| 318 | &tms340x0_device::sra_r_a, &tms340x0_device::sra_r_b, &tms340x0_device::sra_r_a, &tms340x0_device::sra_r_b, &tms340x0_device::sra_r_a, &tms340x0_device::sra_r_b, &tms340x0_device::sra_r_a, &tms340x0_device::sra_r_b, |
| 319 | &tms340x0_device::sra_r_a, &tms340x0_device::sra_r_b, &tms340x0_device::sra_r_a, &tms340x0_device::sra_r_b, &tms340x0_device::sra_r_a, &tms340x0_device::sra_r_b, &tms340x0_device::sra_r_a, &tms340x0_device::sra_r_b, |
| 320 | /* 0x6600 */ |
| 321 | &tms340x0_device::srl_r_a, &tms340x0_device::srl_r_b, &tms340x0_device::srl_r_a, &tms340x0_device::srl_r_b, &tms340x0_device::srl_r_a, &tms340x0_device::srl_r_b, &tms340x0_device::srl_r_a, &tms340x0_device::srl_r_b, |
| 322 | &tms340x0_device::srl_r_a, &tms340x0_device::srl_r_b, &tms340x0_device::srl_r_a, &tms340x0_device::srl_r_b, &tms340x0_device::srl_r_a, &tms340x0_device::srl_r_b, &tms340x0_device::srl_r_a, &tms340x0_device::srl_r_b, |
| 323 | /* 0x6700 */ |
| 324 | &tms340x0_device::srl_r_a, &tms340x0_device::srl_r_b, &tms340x0_device::srl_r_a, &tms340x0_device::srl_r_b, &tms340x0_device::srl_r_a, &tms340x0_device::srl_r_b, &tms340x0_device::srl_r_a, &tms340x0_device::srl_r_b, |
| 325 | &tms340x0_device::srl_r_a, &tms340x0_device::srl_r_b, &tms340x0_device::srl_r_a, &tms340x0_device::srl_r_b, &tms340x0_device::srl_r_a, &tms340x0_device::srl_r_b, &tms340x0_device::srl_r_a, &tms340x0_device::srl_r_b, |
| 326 | /* 0x6800 */ |
| 327 | &tms340x0_device::rl_r_a, &tms340x0_device::rl_r_b, &tms340x0_device::rl_r_a, &tms340x0_device::rl_r_b, &tms340x0_device::rl_r_a, &tms340x0_device::rl_r_b, &tms340x0_device::rl_r_a, &tms340x0_device::rl_r_b, |
| 328 | &tms340x0_device::rl_r_a, &tms340x0_device::rl_r_b, &tms340x0_device::rl_r_a, &tms340x0_device::rl_r_b, &tms340x0_device::rl_r_a, &tms340x0_device::rl_r_b, &tms340x0_device::rl_r_a, &tms340x0_device::rl_r_b, |
| 329 | /* 0x6900 */ |
| 330 | &tms340x0_device::rl_r_a, &tms340x0_device::rl_r_b, &tms340x0_device::rl_r_a, &tms340x0_device::rl_r_b, &tms340x0_device::rl_r_a, &tms340x0_device::rl_r_b, &tms340x0_device::rl_r_a, &tms340x0_device::rl_r_b, |
| 331 | &tms340x0_device::rl_r_a, &tms340x0_device::rl_r_b, &tms340x0_device::rl_r_a, &tms340x0_device::rl_r_b, &tms340x0_device::rl_r_a, &tms340x0_device::rl_r_b, &tms340x0_device::rl_r_a, &tms340x0_device::rl_r_b, |
| 332 | /* 0x6a00 */ |
| 333 | &tms340x0_device::lmo_a, &tms340x0_device::lmo_b, &tms340x0_device::lmo_a, &tms340x0_device::lmo_b, &tms340x0_device::lmo_a, &tms340x0_device::lmo_b, &tms340x0_device::lmo_a, &tms340x0_device::lmo_b, |
| 334 | &tms340x0_device::lmo_a, &tms340x0_device::lmo_b, &tms340x0_device::lmo_a, &tms340x0_device::lmo_b, &tms340x0_device::lmo_a, &tms340x0_device::lmo_b, &tms340x0_device::lmo_a, &tms340x0_device::lmo_b, |
| 335 | /* 0x6b00 */ |
| 336 | &tms340x0_device::lmo_a, &tms340x0_device::lmo_b, &tms340x0_device::lmo_a, &tms340x0_device::lmo_b, &tms340x0_device::lmo_a, &tms340x0_device::lmo_b, &tms340x0_device::lmo_a, &tms340x0_device::lmo_b, |
| 337 | &tms340x0_device::lmo_a, &tms340x0_device::lmo_b, &tms340x0_device::lmo_a, &tms340x0_device::lmo_b, &tms340x0_device::lmo_a, &tms340x0_device::lmo_b, &tms340x0_device::lmo_a, &tms340x0_device::lmo_b, |
| 338 | /* 0x6c00 */ |
| 339 | &tms340x0_device::mods_a, &tms340x0_device::mods_b, &tms340x0_device::mods_a, &tms340x0_device::mods_b, &tms340x0_device::mods_a, &tms340x0_device::mods_b, &tms340x0_device::mods_a, &tms340x0_device::mods_b, |
| 340 | &tms340x0_device::mods_a, &tms340x0_device::mods_b, &tms340x0_device::mods_a, &tms340x0_device::mods_b, &tms340x0_device::mods_a, &tms340x0_device::mods_b, &tms340x0_device::mods_a, &tms340x0_device::mods_b, |
| 341 | /* 0x6d00 */ |
| 342 | &tms340x0_device::mods_a, &tms340x0_device::mods_b, &tms340x0_device::mods_a, &tms340x0_device::mods_b, &tms340x0_device::mods_a, &tms340x0_device::mods_b, &tms340x0_device::mods_a, &tms340x0_device::mods_b, |
| 343 | &tms340x0_device::mods_a, &tms340x0_device::mods_b, &tms340x0_device::mods_a, &tms340x0_device::mods_b, &tms340x0_device::mods_a, &tms340x0_device::mods_b, &tms340x0_device::mods_a, &tms340x0_device::mods_b, |
| 344 | /* 0x6e00 */ |
| 345 | &tms340x0_device::modu_a, &tms340x0_device::modu_b, &tms340x0_device::modu_a, &tms340x0_device::modu_b, &tms340x0_device::modu_a, &tms340x0_device::modu_b, &tms340x0_device::modu_a, &tms340x0_device::modu_b, |
| 346 | &tms340x0_device::modu_a, &tms340x0_device::modu_b, &tms340x0_device::modu_a, &tms340x0_device::modu_b, &tms340x0_device::modu_a, &tms340x0_device::modu_b, &tms340x0_device::modu_a, &tms340x0_device::modu_b, |
| 347 | /* 0x6f00 */ |
| 348 | &tms340x0_device::modu_a, &tms340x0_device::modu_b, &tms340x0_device::modu_a, &tms340x0_device::modu_b, &tms340x0_device::modu_a, &tms340x0_device::modu_b, &tms340x0_device::modu_a, &tms340x0_device::modu_b, |
| 349 | &tms340x0_device::modu_a, &tms340x0_device::modu_b, &tms340x0_device::modu_a, &tms340x0_device::modu_b, &tms340x0_device::modu_a, &tms340x0_device::modu_b, &tms340x0_device::modu_a, &tms340x0_device::modu_b, |
| 350 | /* 0x7000 */ |
| 351 | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 352 | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 353 | /* 0x7100 */ |
| 354 | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 355 | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 356 | /* 0x7200 */ |
| 357 | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 358 | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 359 | /* 0x7300 */ |
| 360 | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 361 | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 362 | /* 0x7400 */ |
| 363 | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 364 | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 365 | /* 0x7500 */ |
| 366 | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 367 | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 368 | /* 0x7600 */ |
| 369 | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 370 | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 371 | /* 0x7700 */ |
| 372 | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 373 | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 374 | /* 0x7800 */ |
| 375 | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 376 | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 377 | /* 0x7900 */ |
| 378 | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 379 | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 380 | /* 0x7a00 */ |
| 381 | &tms340x0_device::rmo_a, &tms340x0_device::rmo_b, &tms340x0_device::rmo_a, &tms340x0_device::rmo_b, &tms340x0_device::rmo_a, &tms340x0_device::rmo_b, &tms340x0_device::rmo_a, &tms340x0_device::rmo_b, |
| 382 | &tms340x0_device::rmo_a, &tms340x0_device::rmo_b, &tms340x0_device::rmo_a, &tms340x0_device::rmo_b, &tms340x0_device::rmo_a, &tms340x0_device::rmo_b, &tms340x0_device::rmo_a, &tms340x0_device::rmo_b, |
| 383 | /* 0x7b00 */ |
| 384 | &tms340x0_device::rmo_a, &tms340x0_device::rmo_b, &tms340x0_device::rmo_a, &tms340x0_device::rmo_b, &tms340x0_device::rmo_a, &tms340x0_device::rmo_b, &tms340x0_device::rmo_a, &tms340x0_device::rmo_b, |
| 385 | &tms340x0_device::rmo_a, &tms340x0_device::rmo_b, &tms340x0_device::rmo_a, &tms340x0_device::rmo_b, &tms340x0_device::rmo_a, &tms340x0_device::rmo_b, &tms340x0_device::rmo_a, &tms340x0_device::rmo_b, |
| 386 | /* 0x7c00 */ |
| 387 | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 388 | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 389 | /* 0x7d00 */ |
| 390 | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 391 | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 392 | /* 0x7e00 */ |
| 393 | &tms340x0_device::swapf_a, &tms340x0_device::swapf_b, &tms340x0_device::swapf_a, &tms340x0_device::swapf_b, &tms340x0_device::swapf_a, &tms340x0_device::swapf_b, &tms340x0_device::swapf_a, &tms340x0_device::swapf_b, |
| 394 | &tms340x0_device::swapf_a, &tms340x0_device::swapf_b, &tms340x0_device::swapf_a, &tms340x0_device::swapf_b, &tms340x0_device::swapf_a, &tms340x0_device::swapf_b, &tms340x0_device::swapf_a, &tms340x0_device::swapf_b, |
| 395 | /* 0x7f00 */ |
| 396 | &tms340x0_device::swapf_a, &tms340x0_device::swapf_b, &tms340x0_device::swapf_a, &tms340x0_device::swapf_b, &tms340x0_device::swapf_a, &tms340x0_device::swapf_b, &tms340x0_device::swapf_a, &tms340x0_device::swapf_b, |
| 397 | &tms340x0_device::swapf_a, &tms340x0_device::swapf_b, &tms340x0_device::swapf_a, &tms340x0_device::swapf_b, &tms340x0_device::swapf_a, &tms340x0_device::swapf_b, &tms340x0_device::swapf_a, &tms340x0_device::swapf_b, |
| 398 | /* 0x8000 */ |
| 399 | &tms340x0_device::move0_rn_a, &tms340x0_device::move0_rn_b, &tms340x0_device::move0_rn_a, &tms340x0_device::move0_rn_b, &tms340x0_device::move0_rn_a, &tms340x0_device::move0_rn_b, &tms340x0_device::move0_rn_a, &tms340x0_device::move0_rn_b, |
| 400 | &tms340x0_device::move0_rn_a, &tms340x0_device::move0_rn_b, &tms340x0_device::move0_rn_a, &tms340x0_device::move0_rn_b, &tms340x0_device::move0_rn_a, &tms340x0_device::move0_rn_b, &tms340x0_device::move0_rn_a, &tms340x0_device::move0_rn_b, |
| 401 | /* 0x8100 */ |
| 402 | &tms340x0_device::move0_rn_a, &tms340x0_device::move0_rn_b, &tms340x0_device::move0_rn_a, &tms340x0_device::move0_rn_b, &tms340x0_device::move0_rn_a, &tms340x0_device::move0_rn_b, &tms340x0_device::move0_rn_a, &tms340x0_device::move0_rn_b, |
| 403 | &tms340x0_device::move0_rn_a, &tms340x0_device::move0_rn_b, &tms340x0_device::move0_rn_a, &tms340x0_device::move0_rn_b, &tms340x0_device::move0_rn_a, &tms340x0_device::move0_rn_b, &tms340x0_device::move0_rn_a, &tms340x0_device::move0_rn_b, |
| 404 | /* 0x8200 */ |
| 405 | &tms340x0_device::move1_rn_a, &tms340x0_device::move1_rn_b, &tms340x0_device::move1_rn_a, &tms340x0_device::move1_rn_b, &tms340x0_device::move1_rn_a, &tms340x0_device::move1_rn_b, &tms340x0_device::move1_rn_a, &tms340x0_device::move1_rn_b, |
| 406 | &tms340x0_device::move1_rn_a, &tms340x0_device::move1_rn_b, &tms340x0_device::move1_rn_a, &tms340x0_device::move1_rn_b, &tms340x0_device::move1_rn_a, &tms340x0_device::move1_rn_b, &tms340x0_device::move1_rn_a, &tms340x0_device::move1_rn_b, |
| 407 | /* 0x8300 */ |
| 408 | &tms340x0_device::move1_rn_a, &tms340x0_device::move1_rn_b, &tms340x0_device::move1_rn_a, &tms340x0_device::move1_rn_b, &tms340x0_device::move1_rn_a, &tms340x0_device::move1_rn_b, &tms340x0_device::move1_rn_a, &tms340x0_device::move1_rn_b, |
| 409 | &tms340x0_device::move1_rn_a, &tms340x0_device::move1_rn_b, &tms340x0_device::move1_rn_a, &tms340x0_device::move1_rn_b, &tms340x0_device::move1_rn_a, &tms340x0_device::move1_rn_b, &tms340x0_device::move1_rn_a, &tms340x0_device::move1_rn_b, |
| 410 | /* 0x8400 */ |
| 411 | &tms340x0_device::move0_nr_a, &tms340x0_device::move0_nr_b, &tms340x0_device::move0_nr_a, &tms340x0_device::move0_nr_b, &tms340x0_device::move0_nr_a, &tms340x0_device::move0_nr_b, &tms340x0_device::move0_nr_a, &tms340x0_device::move0_nr_b, |
| 412 | &tms340x0_device::move0_nr_a, &tms340x0_device::move0_nr_b, &tms340x0_device::move0_nr_a, &tms340x0_device::move0_nr_b, &tms340x0_device::move0_nr_a, &tms340x0_device::move0_nr_b, &tms340x0_device::move0_nr_a, &tms340x0_device::move0_nr_b, |
| 413 | /* 0x8500 */ |
| 414 | &tms340x0_device::move0_nr_a, &tms340x0_device::move0_nr_b, &tms340x0_device::move0_nr_a, &tms340x0_device::move0_nr_b, &tms340x0_device::move0_nr_a, &tms340x0_device::move0_nr_b, &tms340x0_device::move0_nr_a, &tms340x0_device::move0_nr_b, |
| 415 | &tms340x0_device::move0_nr_a, &tms340x0_device::move0_nr_b, &tms340x0_device::move0_nr_a, &tms340x0_device::move0_nr_b, &tms340x0_device::move0_nr_a, &tms340x0_device::move0_nr_b, &tms340x0_device::move0_nr_a, &tms340x0_device::move0_nr_b, |
| 416 | /* 0x8600 */ |
| 417 | &tms340x0_device::move1_nr_a, &tms340x0_device::move1_nr_b, &tms340x0_device::move1_nr_a, &tms340x0_device::move1_nr_b, &tms340x0_device::move1_nr_a, &tms340x0_device::move1_nr_b, &tms340x0_device::move1_nr_a, &tms340x0_device::move1_nr_b, |
| 418 | &tms340x0_device::move1_nr_a, &tms340x0_device::move1_nr_b, &tms340x0_device::move1_nr_a, &tms340x0_device::move1_nr_b, &tms340x0_device::move1_nr_a, &tms340x0_device::move1_nr_b, &tms340x0_device::move1_nr_a, &tms340x0_device::move1_nr_b, |
| 419 | /* 0x8700 */ |
| 420 | &tms340x0_device::move1_nr_a, &tms340x0_device::move1_nr_b, &tms340x0_device::move1_nr_a, &tms340x0_device::move1_nr_b, &tms340x0_device::move1_nr_a, &tms340x0_device::move1_nr_b, &tms340x0_device::move1_nr_a, &tms340x0_device::move1_nr_b, |
| 421 | &tms340x0_device::move1_nr_a, &tms340x0_device::move1_nr_b, &tms340x0_device::move1_nr_a, &tms340x0_device::move1_nr_b, &tms340x0_device::move1_nr_a, &tms340x0_device::move1_nr_b, &tms340x0_device::move1_nr_a, &tms340x0_device::move1_nr_b, |
| 422 | /* 0x8800 */ |
| 423 | &tms340x0_device::move0_nn_a, &tms340x0_device::move0_nn_b, &tms340x0_device::move0_nn_a, &tms340x0_device::move0_nn_b, &tms340x0_device::move0_nn_a, &tms340x0_device::move0_nn_b, &tms340x0_device::move0_nn_a, &tms340x0_device::move0_nn_b, |
| 424 | &tms340x0_device::move0_nn_a, &tms340x0_device::move0_nn_b, &tms340x0_device::move0_nn_a, &tms340x0_device::move0_nn_b, &tms340x0_device::move0_nn_a, &tms340x0_device::move0_nn_b, &tms340x0_device::move0_nn_a, &tms340x0_device::move0_nn_b, |
| 425 | /* 0x8900 */ |
| 426 | &tms340x0_device::move0_nn_a, &tms340x0_device::move0_nn_b, &tms340x0_device::move0_nn_a, &tms340x0_device::move0_nn_b, &tms340x0_device::move0_nn_a, &tms340x0_device::move0_nn_b, &tms340x0_device::move0_nn_a, &tms340x0_device::move0_nn_b, |
| 427 | &tms340x0_device::move0_nn_a, &tms340x0_device::move0_nn_b, &tms340x0_device::move0_nn_a, &tms340x0_device::move0_nn_b, &tms340x0_device::move0_nn_a, &tms340x0_device::move0_nn_b, &tms340x0_device::move0_nn_a, &tms340x0_device::move0_nn_b, |
| 428 | /* 0x8a00 */ |
| 429 | &tms340x0_device::move1_nn_a, &tms340x0_device::move1_nn_b, &tms340x0_device::move1_nn_a, &tms340x0_device::move1_nn_b, &tms340x0_device::move1_nn_a, &tms340x0_device::move1_nn_b, &tms340x0_device::move1_nn_a, &tms340x0_device::move1_nn_b, |
| 430 | &tms340x0_device::move1_nn_a, &tms340x0_device::move1_nn_b, &tms340x0_device::move1_nn_a, &tms340x0_device::move1_nn_b, &tms340x0_device::move1_nn_a, &tms340x0_device::move1_nn_b, &tms340x0_device::move1_nn_a, &tms340x0_device::move1_nn_b, |
| 431 | /* 0x8b00 */ |
| 432 | &tms340x0_device::move1_nn_a, &tms340x0_device::move1_nn_b, &tms340x0_device::move1_nn_a, &tms340x0_device::move1_nn_b, &tms340x0_device::move1_nn_a, &tms340x0_device::move1_nn_b, &tms340x0_device::move1_nn_a, &tms340x0_device::move1_nn_b, |
| 433 | &tms340x0_device::move1_nn_a, &tms340x0_device::move1_nn_b, &tms340x0_device::move1_nn_a, &tms340x0_device::move1_nn_b, &tms340x0_device::move1_nn_a, &tms340x0_device::move1_nn_b, &tms340x0_device::move1_nn_a, &tms340x0_device::move1_nn_b, |
| 434 | /* 0x8c00 */ |
| 435 | &tms340x0_device::movb_rn_a, &tms340x0_device::movb_rn_b, &tms340x0_device::movb_rn_a, &tms340x0_device::movb_rn_b, &tms340x0_device::movb_rn_a, &tms340x0_device::movb_rn_b, &tms340x0_device::movb_rn_a, &tms340x0_device::movb_rn_b, |
| 436 | &tms340x0_device::movb_rn_a, &tms340x0_device::movb_rn_b, &tms340x0_device::movb_rn_a, &tms340x0_device::movb_rn_b, &tms340x0_device::movb_rn_a, &tms340x0_device::movb_rn_b, &tms340x0_device::movb_rn_a, &tms340x0_device::movb_rn_b, |
| 437 | /* 0x8d00 */ |
| 438 | &tms340x0_device::movb_rn_a, &tms340x0_device::movb_rn_b, &tms340x0_device::movb_rn_a, &tms340x0_device::movb_rn_b, &tms340x0_device::movb_rn_a, &tms340x0_device::movb_rn_b, &tms340x0_device::movb_rn_a, &tms340x0_device::movb_rn_b, |
| 439 | &tms340x0_device::movb_rn_a, &tms340x0_device::movb_rn_b, &tms340x0_device::movb_rn_a, &tms340x0_device::movb_rn_b, &tms340x0_device::movb_rn_a, &tms340x0_device::movb_rn_b, &tms340x0_device::movb_rn_a, &tms340x0_device::movb_rn_b, |
| 440 | /* 0x8e00 */ |
| 441 | &tms340x0_device::movb_nr_a, &tms340x0_device::movb_nr_b, &tms340x0_device::movb_nr_a, &tms340x0_device::movb_nr_b, &tms340x0_device::movb_nr_a, &tms340x0_device::movb_nr_b, &tms340x0_device::movb_nr_a, &tms340x0_device::movb_nr_b, |
| 442 | &tms340x0_device::movb_nr_a, &tms340x0_device::movb_nr_b, &tms340x0_device::movb_nr_a, &tms340x0_device::movb_nr_b, &tms340x0_device::movb_nr_a, &tms340x0_device::movb_nr_b, &tms340x0_device::movb_nr_a, &tms340x0_device::movb_nr_b, |
| 443 | /* 0x8f00 */ |
| 444 | &tms340x0_device::movb_nr_a, &tms340x0_device::movb_nr_b, &tms340x0_device::movb_nr_a, &tms340x0_device::movb_nr_b, &tms340x0_device::movb_nr_a, &tms340x0_device::movb_nr_b, &tms340x0_device::movb_nr_a, &tms340x0_device::movb_nr_b, |
| 445 | &tms340x0_device::movb_nr_a, &tms340x0_device::movb_nr_b, &tms340x0_device::movb_nr_a, &tms340x0_device::movb_nr_b, &tms340x0_device::movb_nr_a, &tms340x0_device::movb_nr_b, &tms340x0_device::movb_nr_a, &tms340x0_device::movb_nr_b, |
| 446 | /* 0x9000 */ |
| 447 | &tms340x0_device::move0_r_ni_a, &tms340x0_device::move0_r_ni_b, &tms340x0_device::move0_r_ni_a, &tms340x0_device::move0_r_ni_b, &tms340x0_device::move0_r_ni_a, &tms340x0_device::move0_r_ni_b, &tms340x0_device::move0_r_ni_a, &tms340x0_device::move0_r_ni_b, |
| 448 | &tms340x0_device::move0_r_ni_a, &tms340x0_device::move0_r_ni_b, &tms340x0_device::move0_r_ni_a, &tms340x0_device::move0_r_ni_b, &tms340x0_device::move0_r_ni_a, &tms340x0_device::move0_r_ni_b, &tms340x0_device::move0_r_ni_a, &tms340x0_device::move0_r_ni_b, |
| 449 | /* 0x9100 */ |
| 450 | &tms340x0_device::move0_r_ni_a, &tms340x0_device::move0_r_ni_b, &tms340x0_device::move0_r_ni_a, &tms340x0_device::move0_r_ni_b, &tms340x0_device::move0_r_ni_a, &tms340x0_device::move0_r_ni_b, &tms340x0_device::move0_r_ni_a, &tms340x0_device::move0_r_ni_b, |
| 451 | &tms340x0_device::move0_r_ni_a, &tms340x0_device::move0_r_ni_b, &tms340x0_device::move0_r_ni_a, &tms340x0_device::move0_r_ni_b, &tms340x0_device::move0_r_ni_a, &tms340x0_device::move0_r_ni_b, &tms340x0_device::move0_r_ni_a, &tms340x0_device::move0_r_ni_b, |
| 452 | /* 0x9200 */ |
| 453 | &tms340x0_device::move1_r_ni_a, &tms340x0_device::move1_r_ni_b, &tms340x0_device::move1_r_ni_a, &tms340x0_device::move1_r_ni_b, &tms340x0_device::move1_r_ni_a, &tms340x0_device::move1_r_ni_b, &tms340x0_device::move1_r_ni_a, &tms340x0_device::move1_r_ni_b, |
| 454 | &tms340x0_device::move1_r_ni_a, &tms340x0_device::move1_r_ni_b, &tms340x0_device::move1_r_ni_a, &tms340x0_device::move1_r_ni_b, &tms340x0_device::move1_r_ni_a, &tms340x0_device::move1_r_ni_b, &tms340x0_device::move1_r_ni_a, &tms340x0_device::move1_r_ni_b, |
| 455 | /* 0x9300 */ |
| 456 | &tms340x0_device::move1_r_ni_a, &tms340x0_device::move1_r_ni_b, &tms340x0_device::move1_r_ni_a, &tms340x0_device::move1_r_ni_b, &tms340x0_device::move1_r_ni_a, &tms340x0_device::move1_r_ni_b, &tms340x0_device::move1_r_ni_a, &tms340x0_device::move1_r_ni_b, |
| 457 | &tms340x0_device::move1_r_ni_a, &tms340x0_device::move1_r_ni_b, &tms340x0_device::move1_r_ni_a, &tms340x0_device::move1_r_ni_b, &tms340x0_device::move1_r_ni_a, &tms340x0_device::move1_r_ni_b, &tms340x0_device::move1_r_ni_a, &tms340x0_device::move1_r_ni_b, |
| 458 | /* 0x9400 */ |
| 459 | &tms340x0_device::move0_ni_r_a, &tms340x0_device::move0_ni_r_b, &tms340x0_device::move0_ni_r_a, &tms340x0_device::move0_ni_r_b, &tms340x0_device::move0_ni_r_a, &tms340x0_device::move0_ni_r_b, &tms340x0_device::move0_ni_r_a, &tms340x0_device::move0_ni_r_b, |
| 460 | &tms340x0_device::move0_ni_r_a, &tms340x0_device::move0_ni_r_b, &tms340x0_device::move0_ni_r_a, &tms340x0_device::move0_ni_r_b, &tms340x0_device::move0_ni_r_a, &tms340x0_device::move0_ni_r_b, &tms340x0_device::move0_ni_r_a, &tms340x0_device::move0_ni_r_b, |
| 461 | /* 0x9500 */ |
| 462 | &tms340x0_device::move0_ni_r_a, &tms340x0_device::move0_ni_r_b, &tms340x0_device::move0_ni_r_a, &tms340x0_device::move0_ni_r_b, &tms340x0_device::move0_ni_r_a, &tms340x0_device::move0_ni_r_b, &tms340x0_device::move0_ni_r_a, &tms340x0_device::move0_ni_r_b, |
| 463 | &tms340x0_device::move0_ni_r_a, &tms340x0_device::move0_ni_r_b, &tms340x0_device::move0_ni_r_a, &tms340x0_device::move0_ni_r_b, &tms340x0_device::move0_ni_r_a, &tms340x0_device::move0_ni_r_b, &tms340x0_device::move0_ni_r_a, &tms340x0_device::move0_ni_r_b, |
| 464 | /* 0x9600 */ |
| 465 | &tms340x0_device::move1_ni_r_a, &tms340x0_device::move1_ni_r_b, &tms340x0_device::move1_ni_r_a, &tms340x0_device::move1_ni_r_b, &tms340x0_device::move1_ni_r_a, &tms340x0_device::move1_ni_r_b, &tms340x0_device::move1_ni_r_a, &tms340x0_device::move1_ni_r_b, |
| 466 | &tms340x0_device::move1_ni_r_a, &tms340x0_device::move1_ni_r_b, &tms340x0_device::move1_ni_r_a, &tms340x0_device::move1_ni_r_b, &tms340x0_device::move1_ni_r_a, &tms340x0_device::move1_ni_r_b, &tms340x0_device::move1_ni_r_a, &tms340x0_device::move1_ni_r_b, |
| 467 | /* 0x9700 */ |
| 468 | &tms340x0_device::move1_ni_r_a, &tms340x0_device::move1_ni_r_b, &tms340x0_device::move1_ni_r_a, &tms340x0_device::move1_ni_r_b, &tms340x0_device::move1_ni_r_a, &tms340x0_device::move1_ni_r_b, &tms340x0_device::move1_ni_r_a, &tms340x0_device::move1_ni_r_b, |
| 469 | &tms340x0_device::move1_ni_r_a, &tms340x0_device::move1_ni_r_b, &tms340x0_device::move1_ni_r_a, &tms340x0_device::move1_ni_r_b, &tms340x0_device::move1_ni_r_a, &tms340x0_device::move1_ni_r_b, &tms340x0_device::move1_ni_r_a, &tms340x0_device::move1_ni_r_b, |
| 470 | /* 0x9800 */ |
| 471 | &tms340x0_device::move0_ni_ni_a, &tms340x0_device::move0_ni_ni_b, &tms340x0_device::move0_ni_ni_a, &tms340x0_device::move0_ni_ni_b, &tms340x0_device::move0_ni_ni_a, &tms340x0_device::move0_ni_ni_b, &tms340x0_device::move0_ni_ni_a, &tms340x0_device::move0_ni_ni_b, |
| 472 | &tms340x0_device::move0_ni_ni_a, &tms340x0_device::move0_ni_ni_b, &tms340x0_device::move0_ni_ni_a, &tms340x0_device::move0_ni_ni_b, &tms340x0_device::move0_ni_ni_a, &tms340x0_device::move0_ni_ni_b, &tms340x0_device::move0_ni_ni_a, &tms340x0_device::move0_ni_ni_b, |
| 473 | /* 0x9900 */ |
| 474 | &tms340x0_device::move0_ni_ni_a, &tms340x0_device::move0_ni_ni_b, &tms340x0_device::move0_ni_ni_a, &tms340x0_device::move0_ni_ni_b, &tms340x0_device::move0_ni_ni_a, &tms340x0_device::move0_ni_ni_b, &tms340x0_device::move0_ni_ni_a, &tms340x0_device::move0_ni_ni_b, |
| 475 | &tms340x0_device::move0_ni_ni_a, &tms340x0_device::move0_ni_ni_b, &tms340x0_device::move0_ni_ni_a, &tms340x0_device::move0_ni_ni_b, &tms340x0_device::move0_ni_ni_a, &tms340x0_device::move0_ni_ni_b, &tms340x0_device::move0_ni_ni_a, &tms340x0_device::move0_ni_ni_b, |
| 476 | /* 0x9a00 */ |
| 477 | &tms340x0_device::move1_ni_ni_a, &tms340x0_device::move1_ni_ni_b, &tms340x0_device::move1_ni_ni_a, &tms340x0_device::move1_ni_ni_b, &tms340x0_device::move1_ni_ni_a, &tms340x0_device::move1_ni_ni_b, &tms340x0_device::move1_ni_ni_a, &tms340x0_device::move1_ni_ni_b, |
| 478 | &tms340x0_device::move1_ni_ni_a, &tms340x0_device::move1_ni_ni_b, &tms340x0_device::move1_ni_ni_a, &tms340x0_device::move1_ni_ni_b, &tms340x0_device::move1_ni_ni_a, &tms340x0_device::move1_ni_ni_b, &tms340x0_device::move1_ni_ni_a, &tms340x0_device::move1_ni_ni_b, |
| 479 | /* 0x9b00 */ |
| 480 | &tms340x0_device::move1_ni_ni_a, &tms340x0_device::move1_ni_ni_b, &tms340x0_device::move1_ni_ni_a, &tms340x0_device::move1_ni_ni_b, &tms340x0_device::move1_ni_ni_a, &tms340x0_device::move1_ni_ni_b, &tms340x0_device::move1_ni_ni_a, &tms340x0_device::move1_ni_ni_b, |
| 481 | &tms340x0_device::move1_ni_ni_a, &tms340x0_device::move1_ni_ni_b, &tms340x0_device::move1_ni_ni_a, &tms340x0_device::move1_ni_ni_b, &tms340x0_device::move1_ni_ni_a, &tms340x0_device::move1_ni_ni_b, &tms340x0_device::move1_ni_ni_a, &tms340x0_device::move1_ni_ni_b, |
| 482 | /* 0x9c00 */ |
| 483 | &tms340x0_device::movb_nn_a, &tms340x0_device::movb_nn_b, &tms340x0_device::movb_nn_a, &tms340x0_device::movb_nn_b, &tms340x0_device::movb_nn_a, &tms340x0_device::movb_nn_b, &tms340x0_device::movb_nn_a, &tms340x0_device::movb_nn_b, |
| 484 | &tms340x0_device::movb_nn_a, &tms340x0_device::movb_nn_b, &tms340x0_device::movb_nn_a, &tms340x0_device::movb_nn_b, &tms340x0_device::movb_nn_a, &tms340x0_device::movb_nn_b, &tms340x0_device::movb_nn_a, &tms340x0_device::movb_nn_b, |
| 485 | /* 0x9d00 */ |
| 486 | &tms340x0_device::movb_nn_a, &tms340x0_device::movb_nn_b, &tms340x0_device::movb_nn_a, &tms340x0_device::movb_nn_b, &tms340x0_device::movb_nn_a, &tms340x0_device::movb_nn_b, &tms340x0_device::movb_nn_a, &tms340x0_device::movb_nn_b, |
| 487 | &tms340x0_device::movb_nn_a, &tms340x0_device::movb_nn_b, &tms340x0_device::movb_nn_a, &tms340x0_device::movb_nn_b, &tms340x0_device::movb_nn_a, &tms340x0_device::movb_nn_b, &tms340x0_device::movb_nn_a, &tms340x0_device::movb_nn_b, |
| 488 | /* 0x9e00 */ |
| 489 | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 490 | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 491 | /* 0x9f00 */ |
| 492 | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 493 | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 494 | /* 0xa000 */ |
| 495 | &tms340x0_device::move0_r_dn_a, &tms340x0_device::move0_r_dn_b, &tms340x0_device::move0_r_dn_a, &tms340x0_device::move0_r_dn_b, &tms340x0_device::move0_r_dn_a, &tms340x0_device::move0_r_dn_b, &tms340x0_device::move0_r_dn_a, &tms340x0_device::move0_r_dn_b, |
| 496 | &tms340x0_device::move0_r_dn_a, &tms340x0_device::move0_r_dn_b, &tms340x0_device::move0_r_dn_a, &tms340x0_device::move0_r_dn_b, &tms340x0_device::move0_r_dn_a, &tms340x0_device::move0_r_dn_b, &tms340x0_device::move0_r_dn_a, &tms340x0_device::move0_r_dn_b, |
| 497 | /* 0xa100 */ |
| 498 | &tms340x0_device::move0_r_dn_a, &tms340x0_device::move0_r_dn_b, &tms340x0_device::move0_r_dn_a, &tms340x0_device::move0_r_dn_b, &tms340x0_device::move0_r_dn_a, &tms340x0_device::move0_r_dn_b, &tms340x0_device::move0_r_dn_a, &tms340x0_device::move0_r_dn_b, |
| 499 | &tms340x0_device::move0_r_dn_a, &tms340x0_device::move0_r_dn_b, &tms340x0_device::move0_r_dn_a, &tms340x0_device::move0_r_dn_b, &tms340x0_device::move0_r_dn_a, &tms340x0_device::move0_r_dn_b, &tms340x0_device::move0_r_dn_a, &tms340x0_device::move0_r_dn_b, |
| 500 | /* 0xa200 */ |
| 501 | &tms340x0_device::move1_r_dn_a, &tms340x0_device::move1_r_dn_b, &tms340x0_device::move1_r_dn_a, &tms340x0_device::move1_r_dn_b, &tms340x0_device::move1_r_dn_a, &tms340x0_device::move1_r_dn_b, &tms340x0_device::move1_r_dn_a, &tms340x0_device::move1_r_dn_b, |
| 502 | &tms340x0_device::move1_r_dn_a, &tms340x0_device::move1_r_dn_b, &tms340x0_device::move1_r_dn_a, &tms340x0_device::move1_r_dn_b, &tms340x0_device::move1_r_dn_a, &tms340x0_device::move1_r_dn_b, &tms340x0_device::move1_r_dn_a, &tms340x0_device::move1_r_dn_b, |
| 503 | /* 0xa300 */ |
| 504 | &tms340x0_device::move1_r_dn_a, &tms340x0_device::move1_r_dn_b, &tms340x0_device::move1_r_dn_a, &tms340x0_device::move1_r_dn_b, &tms340x0_device::move1_r_dn_a, &tms340x0_device::move1_r_dn_b, &tms340x0_device::move1_r_dn_a, &tms340x0_device::move1_r_dn_b, |
| 505 | &tms340x0_device::move1_r_dn_a, &tms340x0_device::move1_r_dn_b, &tms340x0_device::move1_r_dn_a, &tms340x0_device::move1_r_dn_b, &tms340x0_device::move1_r_dn_a, &tms340x0_device::move1_r_dn_b, &tms340x0_device::move1_r_dn_a, &tms340x0_device::move1_r_dn_b, |
| 506 | /* 0xa400 */ |
| 507 | &tms340x0_device::move0_dn_r_a, &tms340x0_device::move0_dn_r_b, &tms340x0_device::move0_dn_r_a, &tms340x0_device::move0_dn_r_b, &tms340x0_device::move0_dn_r_a, &tms340x0_device::move0_dn_r_b, &tms340x0_device::move0_dn_r_a, &tms340x0_device::move0_dn_r_b, |
| 508 | &tms340x0_device::move0_dn_r_a, &tms340x0_device::move0_dn_r_b, &tms340x0_device::move0_dn_r_a, &tms340x0_device::move0_dn_r_b, &tms340x0_device::move0_dn_r_a, &tms340x0_device::move0_dn_r_b, &tms340x0_device::move0_dn_r_a, &tms340x0_device::move0_dn_r_b, |
| 509 | /* 0xa500 */ |
| 510 | &tms340x0_device::move0_dn_r_a, &tms340x0_device::move0_dn_r_b, &tms340x0_device::move0_dn_r_a, &tms340x0_device::move0_dn_r_b, &tms340x0_device::move0_dn_r_a, &tms340x0_device::move0_dn_r_b, &tms340x0_device::move0_dn_r_a, &tms340x0_device::move0_dn_r_b, |
| 511 | &tms340x0_device::move0_dn_r_a, &tms340x0_device::move0_dn_r_b, &tms340x0_device::move0_dn_r_a, &tms340x0_device::move0_dn_r_b, &tms340x0_device::move0_dn_r_a, &tms340x0_device::move0_dn_r_b, &tms340x0_device::move0_dn_r_a, &tms340x0_device::move0_dn_r_b, |
| 512 | /* 0xa600 */ |
| 513 | &tms340x0_device::move1_dn_r_a, &tms340x0_device::move1_dn_r_b, &tms340x0_device::move1_dn_r_a, &tms340x0_device::move1_dn_r_b, &tms340x0_device::move1_dn_r_a, &tms340x0_device::move1_dn_r_b, &tms340x0_device::move1_dn_r_a, &tms340x0_device::move1_dn_r_b, |
| 514 | &tms340x0_device::move1_dn_r_a, &tms340x0_device::move1_dn_r_b, &tms340x0_device::move1_dn_r_a, &tms340x0_device::move1_dn_r_b, &tms340x0_device::move1_dn_r_a, &tms340x0_device::move1_dn_r_b, &tms340x0_device::move1_dn_r_a, &tms340x0_device::move1_dn_r_b, |
| 515 | /* 0xa700 */ |
| 516 | &tms340x0_device::move1_dn_r_a, &tms340x0_device::move1_dn_r_b, &tms340x0_device::move1_dn_r_a, &tms340x0_device::move1_dn_r_b, &tms340x0_device::move1_dn_r_a, &tms340x0_device::move1_dn_r_b, &tms340x0_device::move1_dn_r_a, &tms340x0_device::move1_dn_r_b, |
| 517 | &tms340x0_device::move1_dn_r_a, &tms340x0_device::move1_dn_r_b, &tms340x0_device::move1_dn_r_a, &tms340x0_device::move1_dn_r_b, &tms340x0_device::move1_dn_r_a, &tms340x0_device::move1_dn_r_b, &tms340x0_device::move1_dn_r_a, &tms340x0_device::move1_dn_r_b, |
| 518 | /* 0xa800 */ |
| 519 | &tms340x0_device::move0_dn_dn_a, &tms340x0_device::move0_dn_dn_b, &tms340x0_device::move0_dn_dn_a, &tms340x0_device::move0_dn_dn_b, &tms340x0_device::move0_dn_dn_a, &tms340x0_device::move0_dn_dn_b, &tms340x0_device::move0_dn_dn_a, &tms340x0_device::move0_dn_dn_b, |
| 520 | &tms340x0_device::move0_dn_dn_a, &tms340x0_device::move0_dn_dn_b, &tms340x0_device::move0_dn_dn_a, &tms340x0_device::move0_dn_dn_b, &tms340x0_device::move0_dn_dn_a, &tms340x0_device::move0_dn_dn_b, &tms340x0_device::move0_dn_dn_a, &tms340x0_device::move0_dn_dn_b, |
| 521 | /* 0xa900 */ |
| 522 | &tms340x0_device::move0_dn_dn_a, &tms340x0_device::move0_dn_dn_b, &tms340x0_device::move0_dn_dn_a, &tms340x0_device::move0_dn_dn_b, &tms340x0_device::move0_dn_dn_a, &tms340x0_device::move0_dn_dn_b, &tms340x0_device::move0_dn_dn_a, &tms340x0_device::move0_dn_dn_b, |
| 523 | &tms340x0_device::move0_dn_dn_a, &tms340x0_device::move0_dn_dn_b, &tms340x0_device::move0_dn_dn_a, &tms340x0_device::move0_dn_dn_b, &tms340x0_device::move0_dn_dn_a, &tms340x0_device::move0_dn_dn_b, &tms340x0_device::move0_dn_dn_a, &tms340x0_device::move0_dn_dn_b, |
| 524 | /* 0xaa00 */ |
| 525 | &tms340x0_device::move1_dn_dn_a, &tms340x0_device::move1_dn_dn_b, &tms340x0_device::move1_dn_dn_a, &tms340x0_device::move1_dn_dn_b, &tms340x0_device::move1_dn_dn_a, &tms340x0_device::move1_dn_dn_b, &tms340x0_device::move1_dn_dn_a, &tms340x0_device::move1_dn_dn_b, |
| 526 | &tms340x0_device::move1_dn_dn_a, &tms340x0_device::move1_dn_dn_b, &tms340x0_device::move1_dn_dn_a, &tms340x0_device::move1_dn_dn_b, &tms340x0_device::move1_dn_dn_a, &tms340x0_device::move1_dn_dn_b, &tms340x0_device::move1_dn_dn_a, &tms340x0_device::move1_dn_dn_b, |
| 527 | /* 0xab00 */ |
| 528 | &tms340x0_device::move1_dn_dn_a, &tms340x0_device::move1_dn_dn_b, &tms340x0_device::move1_dn_dn_a, &tms340x0_device::move1_dn_dn_b, &tms340x0_device::move1_dn_dn_a, &tms340x0_device::move1_dn_dn_b, &tms340x0_device::move1_dn_dn_a, &tms340x0_device::move1_dn_dn_b, |
| 529 | &tms340x0_device::move1_dn_dn_a, &tms340x0_device::move1_dn_dn_b, &tms340x0_device::move1_dn_dn_a, &tms340x0_device::move1_dn_dn_b, &tms340x0_device::move1_dn_dn_a, &tms340x0_device::move1_dn_dn_b, &tms340x0_device::move1_dn_dn_a, &tms340x0_device::move1_dn_dn_b, |
| 530 | /* 0xac00 */ |
| 531 | &tms340x0_device::movb_r_no_a, &tms340x0_device::movb_r_no_b, &tms340x0_device::movb_r_no_a, &tms340x0_device::movb_r_no_b, &tms340x0_device::movb_r_no_a, &tms340x0_device::movb_r_no_b, &tms340x0_device::movb_r_no_a, &tms340x0_device::movb_r_no_b, |
| 532 | &tms340x0_device::movb_r_no_a, &tms340x0_device::movb_r_no_b, &tms340x0_device::movb_r_no_a, &tms340x0_device::movb_r_no_b, &tms340x0_device::movb_r_no_a, &tms340x0_device::movb_r_no_b, &tms340x0_device::movb_r_no_a, &tms340x0_device::movb_r_no_b, |
| 533 | /* 0xad00 */ |
| 534 | &tms340x0_device::movb_r_no_a, &tms340x0_device::movb_r_no_b, &tms340x0_device::movb_r_no_a, &tms340x0_device::movb_r_no_b, &tms340x0_device::movb_r_no_a, &tms340x0_device::movb_r_no_b, &tms340x0_device::movb_r_no_a, &tms340x0_device::movb_r_no_b, |
| 535 | &tms340x0_device::movb_r_no_a, &tms340x0_device::movb_r_no_b, &tms340x0_device::movb_r_no_a, &tms340x0_device::movb_r_no_b, &tms340x0_device::movb_r_no_a, &tms340x0_device::movb_r_no_b, &tms340x0_device::movb_r_no_a, &tms340x0_device::movb_r_no_b, |
| 536 | /* 0xae00 */ |
| 537 | &tms340x0_device::movb_no_r_a, &tms340x0_device::movb_no_r_b, &tms340x0_device::movb_no_r_a, &tms340x0_device::movb_no_r_b, &tms340x0_device::movb_no_r_a, &tms340x0_device::movb_no_r_b, &tms340x0_device::movb_no_r_a, &tms340x0_device::movb_no_r_b, |
| 538 | &tms340x0_device::movb_no_r_a, &tms340x0_device::movb_no_r_b, &tms340x0_device::movb_no_r_a, &tms340x0_device::movb_no_r_b, &tms340x0_device::movb_no_r_a, &tms340x0_device::movb_no_r_b, &tms340x0_device::movb_no_r_a, &tms340x0_device::movb_no_r_b, |
| 539 | /* 0xaf00 */ |
| 540 | &tms340x0_device::movb_no_r_a, &tms340x0_device::movb_no_r_b, &tms340x0_device::movb_no_r_a, &tms340x0_device::movb_no_r_b, &tms340x0_device::movb_no_r_a, &tms340x0_device::movb_no_r_b, &tms340x0_device::movb_no_r_a, &tms340x0_device::movb_no_r_b, |
| 541 | &tms340x0_device::movb_no_r_a, &tms340x0_device::movb_no_r_b, &tms340x0_device::movb_no_r_a, &tms340x0_device::movb_no_r_b, &tms340x0_device::movb_no_r_a, &tms340x0_device::movb_no_r_b, &tms340x0_device::movb_no_r_a, &tms340x0_device::movb_no_r_b, |
| 542 | /* 0xb000 */ |
| 543 | &tms340x0_device::move0_r_no_a, &tms340x0_device::move0_r_no_b, &tms340x0_device::move0_r_no_a, &tms340x0_device::move0_r_no_b, &tms340x0_device::move0_r_no_a, &tms340x0_device::move0_r_no_b, &tms340x0_device::move0_r_no_a, &tms340x0_device::move0_r_no_b, |
| 544 | &tms340x0_device::move0_r_no_a, &tms340x0_device::move0_r_no_b, &tms340x0_device::move0_r_no_a, &tms340x0_device::move0_r_no_b, &tms340x0_device::move0_r_no_a, &tms340x0_device::move0_r_no_b, &tms340x0_device::move0_r_no_a, &tms340x0_device::move0_r_no_b, |
| 545 | /* 0xb100 */ |
| 546 | &tms340x0_device::move0_r_no_a, &tms340x0_device::move0_r_no_b, &tms340x0_device::move0_r_no_a, &tms340x0_device::move0_r_no_b, &tms340x0_device::move0_r_no_a, &tms340x0_device::move0_r_no_b, &tms340x0_device::move0_r_no_a, &tms340x0_device::move0_r_no_b, |
| 547 | &tms340x0_device::move0_r_no_a, &tms340x0_device::move0_r_no_b, &tms340x0_device::move0_r_no_a, &tms340x0_device::move0_r_no_b, &tms340x0_device::move0_r_no_a, &tms340x0_device::move0_r_no_b, &tms340x0_device::move0_r_no_a, &tms340x0_device::move0_r_no_b, |
| 548 | /* 0xb200 */ |
| 549 | &tms340x0_device::move1_r_no_a, &tms340x0_device::move1_r_no_b, &tms340x0_device::move1_r_no_a, &tms340x0_device::move1_r_no_b, &tms340x0_device::move1_r_no_a, &tms340x0_device::move1_r_no_b, &tms340x0_device::move1_r_no_a, &tms340x0_device::move1_r_no_b, |
| 550 | &tms340x0_device::move1_r_no_a, &tms340x0_device::move1_r_no_b, &tms340x0_device::move1_r_no_a, &tms340x0_device::move1_r_no_b, &tms340x0_device::move1_r_no_a, &tms340x0_device::move1_r_no_b, &tms340x0_device::move1_r_no_a, &tms340x0_device::move1_r_no_b, |
| 551 | /* 0xb300 */ |
| 552 | &tms340x0_device::move1_r_no_a, &tms340x0_device::move1_r_no_b, &tms340x0_device::move1_r_no_a, &tms340x0_device::move1_r_no_b, &tms340x0_device::move1_r_no_a, &tms340x0_device::move1_r_no_b, &tms340x0_device::move1_r_no_a, &tms340x0_device::move1_r_no_b, |
| 553 | &tms340x0_device::move1_r_no_a, &tms340x0_device::move1_r_no_b, &tms340x0_device::move1_r_no_a, &tms340x0_device::move1_r_no_b, &tms340x0_device::move1_r_no_a, &tms340x0_device::move1_r_no_b, &tms340x0_device::move1_r_no_a, &tms340x0_device::move1_r_no_b, |
| 554 | /* 0xb400 */ |
| 555 | &tms340x0_device::move0_no_r_a, &tms340x0_device::move0_no_r_b, &tms340x0_device::move0_no_r_a, &tms340x0_device::move0_no_r_b, &tms340x0_device::move0_no_r_a, &tms340x0_device::move0_no_r_b, &tms340x0_device::move0_no_r_a, &tms340x0_device::move0_no_r_b, |
| 556 | &tms340x0_device::move0_no_r_a, &tms340x0_device::move0_no_r_b, &tms340x0_device::move0_no_r_a, &tms340x0_device::move0_no_r_b, &tms340x0_device::move0_no_r_a, &tms340x0_device::move0_no_r_b, &tms340x0_device::move0_no_r_a, &tms340x0_device::move0_no_r_b, |
| 557 | /* 0xb500 */ |
| 558 | &tms340x0_device::move0_no_r_a, &tms340x0_device::move0_no_r_b, &tms340x0_device::move0_no_r_a, &tms340x0_device::move0_no_r_b, &tms340x0_device::move0_no_r_a, &tms340x0_device::move0_no_r_b, &tms340x0_device::move0_no_r_a, &tms340x0_device::move0_no_r_b, |
| 559 | &tms340x0_device::move0_no_r_a, &tms340x0_device::move0_no_r_b, &tms340x0_device::move0_no_r_a, &tms340x0_device::move0_no_r_b, &tms340x0_device::move0_no_r_a, &tms340x0_device::move0_no_r_b, &tms340x0_device::move0_no_r_a, &tms340x0_device::move0_no_r_b, |
| 560 | /* 0xb600 */ |
| 561 | &tms340x0_device::move1_no_r_a, &tms340x0_device::move1_no_r_b, &tms340x0_device::move1_no_r_a, &tms340x0_device::move1_no_r_b, &tms340x0_device::move1_no_r_a, &tms340x0_device::move1_no_r_b, &tms340x0_device::move1_no_r_a, &tms340x0_device::move1_no_r_b, |
| 562 | &tms340x0_device::move1_no_r_a, &tms340x0_device::move1_no_r_b, &tms340x0_device::move1_no_r_a, &tms340x0_device::move1_no_r_b, &tms340x0_device::move1_no_r_a, &tms340x0_device::move1_no_r_b, &tms340x0_device::move1_no_r_a, &tms340x0_device::move1_no_r_b, |
| 563 | /* 0xb700 */ |
| 564 | &tms340x0_device::move1_no_r_a, &tms340x0_device::move1_no_r_b, &tms340x0_device::move1_no_r_a, &tms340x0_device::move1_no_r_b, &tms340x0_device::move1_no_r_a, &tms340x0_device::move1_no_r_b, &tms340x0_device::move1_no_r_a, &tms340x0_device::move1_no_r_b, |
| 565 | &tms340x0_device::move1_no_r_a, &tms340x0_device::move1_no_r_b, &tms340x0_device::move1_no_r_a, &tms340x0_device::move1_no_r_b, &tms340x0_device::move1_no_r_a, &tms340x0_device::move1_no_r_b, &tms340x0_device::move1_no_r_a, &tms340x0_device::move1_no_r_b, |
| 566 | /* 0xb800 */ |
| 567 | &tms340x0_device::move0_no_no_a, &tms340x0_device::move0_no_no_b, &tms340x0_device::move0_no_no_a, &tms340x0_device::move0_no_no_b, &tms340x0_device::move0_no_no_a, &tms340x0_device::move0_no_no_b, &tms340x0_device::move0_no_no_a, &tms340x0_device::move0_no_no_b, |
| 568 | &tms340x0_device::move0_no_no_a, &tms340x0_device::move0_no_no_b, &tms340x0_device::move0_no_no_a, &tms340x0_device::move0_no_no_b, &tms340x0_device::move0_no_no_a, &tms340x0_device::move0_no_no_b, &tms340x0_device::move0_no_no_a, &tms340x0_device::move0_no_no_b, |
| 569 | /* 0xb900 */ |
| 570 | &tms340x0_device::move0_no_no_a, &tms340x0_device::move0_no_no_b, &tms340x0_device::move0_no_no_a, &tms340x0_device::move0_no_no_b, &tms340x0_device::move0_no_no_a, &tms340x0_device::move0_no_no_b, &tms340x0_device::move0_no_no_a, &tms340x0_device::move0_no_no_b, |
| 571 | &tms340x0_device::move0_no_no_a, &tms340x0_device::move0_no_no_b, &tms340x0_device::move0_no_no_a, &tms340x0_device::move0_no_no_b, &tms340x0_device::move0_no_no_a, &tms340x0_device::move0_no_no_b, &tms340x0_device::move0_no_no_a, &tms340x0_device::move0_no_no_b, |
| 572 | /* 0xba00 */ |
| 573 | &tms340x0_device::move1_no_no_a, &tms340x0_device::move1_no_no_b, &tms340x0_device::move1_no_no_a, &tms340x0_device::move1_no_no_b, &tms340x0_device::move1_no_no_a, &tms340x0_device::move1_no_no_b, &tms340x0_device::move1_no_no_a, &tms340x0_device::move1_no_no_b, |
| 574 | &tms340x0_device::move1_no_no_a, &tms340x0_device::move1_no_no_b, &tms340x0_device::move1_no_no_a, &tms340x0_device::move1_no_no_b, &tms340x0_device::move1_no_no_a, &tms340x0_device::move1_no_no_b, &tms340x0_device::move1_no_no_a, &tms340x0_device::move1_no_no_b, |
| 575 | /* 0xbb00 */ |
| 576 | &tms340x0_device::move1_no_no_a, &tms340x0_device::move1_no_no_b, &tms340x0_device::move1_no_no_a, &tms340x0_device::move1_no_no_b, &tms340x0_device::move1_no_no_a, &tms340x0_device::move1_no_no_b, &tms340x0_device::move1_no_no_a, &tms340x0_device::move1_no_no_b, |
| 577 | &tms340x0_device::move1_no_no_a, &tms340x0_device::move1_no_no_b, &tms340x0_device::move1_no_no_a, &tms340x0_device::move1_no_no_b, &tms340x0_device::move1_no_no_a, &tms340x0_device::move1_no_no_b, &tms340x0_device::move1_no_no_a, &tms340x0_device::move1_no_no_b, |
| 578 | /* 0xbc00 */ |
| 579 | &tms340x0_device::movb_no_no_a, &tms340x0_device::movb_no_no_b, &tms340x0_device::movb_no_no_a, &tms340x0_device::movb_no_no_b, &tms340x0_device::movb_no_no_a, &tms340x0_device::movb_no_no_b, &tms340x0_device::movb_no_no_a, &tms340x0_device::movb_no_no_b, |
| 580 | &tms340x0_device::movb_no_no_a, &tms340x0_device::movb_no_no_b, &tms340x0_device::movb_no_no_a, &tms340x0_device::movb_no_no_b, &tms340x0_device::movb_no_no_a, &tms340x0_device::movb_no_no_b, &tms340x0_device::movb_no_no_a, &tms340x0_device::movb_no_no_b, |
| 581 | /* 0xbd00 */ |
| 582 | &tms340x0_device::movb_no_no_a, &tms340x0_device::movb_no_no_b, &tms340x0_device::movb_no_no_a, &tms340x0_device::movb_no_no_b, &tms340x0_device::movb_no_no_a, &tms340x0_device::movb_no_no_b, &tms340x0_device::movb_no_no_a, &tms340x0_device::movb_no_no_b, |
| 583 | &tms340x0_device::movb_no_no_a, &tms340x0_device::movb_no_no_b, &tms340x0_device::movb_no_no_a, &tms340x0_device::movb_no_no_b, &tms340x0_device::movb_no_no_a, &tms340x0_device::movb_no_no_b, &tms340x0_device::movb_no_no_a, &tms340x0_device::movb_no_no_b, |
| 584 | /* 0xbe00 */ |
| 585 | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 586 | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 587 | /* 0xbf00 */ |
| 588 | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 589 | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 590 | /* 0xc000 */ |
| 591 | &tms340x0_device::j_UC_0, &tms340x0_device::j_UC_x, &tms340x0_device::j_UC_x, &tms340x0_device::j_UC_x, &tms340x0_device::j_UC_x, &tms340x0_device::j_UC_x, &tms340x0_device::j_UC_x, &tms340x0_device::j_UC_x, |
| 592 | &tms340x0_device::j_UC_8, &tms340x0_device::j_UC_x, &tms340x0_device::j_UC_x, &tms340x0_device::j_UC_x, &tms340x0_device::j_UC_x, &tms340x0_device::j_UC_x, &tms340x0_device::j_UC_x, &tms340x0_device::j_UC_x, |
| 593 | /* 0xc100 */ |
| 594 | &tms340x0_device::j_P_0, &tms340x0_device::j_P_x, &tms340x0_device::j_P_x, &tms340x0_device::j_P_x, &tms340x0_device::j_P_x, &tms340x0_device::j_P_x, &tms340x0_device::j_P_x, &tms340x0_device::j_P_x, |
| 595 | &tms340x0_device::j_P_8, &tms340x0_device::j_P_x, &tms340x0_device::j_P_x, &tms340x0_device::j_P_x, &tms340x0_device::j_P_x, &tms340x0_device::j_P_x, &tms340x0_device::j_P_x, &tms340x0_device::j_P_x, |
| 596 | /* 0xc200 */ |
| 597 | &tms340x0_device::j_LS_0, &tms340x0_device::j_LS_x, &tms340x0_device::j_LS_x, &tms340x0_device::j_LS_x, &tms340x0_device::j_LS_x, &tms340x0_device::j_LS_x, &tms340x0_device::j_LS_x, &tms340x0_device::j_LS_x, |
| 598 | &tms340x0_device::j_LS_8, &tms340x0_device::j_LS_x, &tms340x0_device::j_LS_x, &tms340x0_device::j_LS_x, &tms340x0_device::j_LS_x, &tms340x0_device::j_LS_x, &tms340x0_device::j_LS_x, &tms340x0_device::j_LS_x, |
| 599 | /* 0xc300 */ |
| 600 | &tms340x0_device::j_HI_0, &tms340x0_device::j_HI_x, &tms340x0_device::j_HI_x, &tms340x0_device::j_HI_x, &tms340x0_device::j_HI_x, &tms340x0_device::j_HI_x, &tms340x0_device::j_HI_x, &tms340x0_device::j_HI_x, |
| 601 | &tms340x0_device::j_HI_8, &tms340x0_device::j_HI_x, &tms340x0_device::j_HI_x, &tms340x0_device::j_HI_x, &tms340x0_device::j_HI_x, &tms340x0_device::j_HI_x, &tms340x0_device::j_HI_x, &tms340x0_device::j_HI_x, |
| 602 | /* 0xc400 */ |
| 603 | &tms340x0_device::j_LT_0, &tms340x0_device::j_LT_x, &tms340x0_device::j_LT_x, &tms340x0_device::j_LT_x, &tms340x0_device::j_LT_x, &tms340x0_device::j_LT_x, &tms340x0_device::j_LT_x, &tms340x0_device::j_LT_x, |
| 604 | &tms340x0_device::j_LT_8, &tms340x0_device::j_LT_x, &tms340x0_device::j_LT_x, &tms340x0_device::j_LT_x, &tms340x0_device::j_LT_x, &tms340x0_device::j_LT_x, &tms340x0_device::j_LT_x, &tms340x0_device::j_LT_x, |
| 605 | /* 0xc500 */ |
| 606 | &tms340x0_device::j_GE_0, &tms340x0_device::j_GE_x, &tms340x0_device::j_GE_x, &tms340x0_device::j_GE_x, &tms340x0_device::j_GE_x, &tms340x0_device::j_GE_x, &tms340x0_device::j_GE_x, &tms340x0_device::j_GE_x, |
| 607 | &tms340x0_device::j_GE_8, &tms340x0_device::j_GE_x, &tms340x0_device::j_GE_x, &tms340x0_device::j_GE_x, &tms340x0_device::j_GE_x, &tms340x0_device::j_GE_x, &tms340x0_device::j_GE_x, &tms340x0_device::j_GE_x, |
| 608 | /* 0xc600 */ |
| 609 | &tms340x0_device::j_LE_0, &tms340x0_device::j_LE_x, &tms340x0_device::j_LE_x, &tms340x0_device::j_LE_x, &tms340x0_device::j_LE_x, &tms340x0_device::j_LE_x, &tms340x0_device::j_LE_x, &tms340x0_device::j_LE_x, |
| 610 | &tms340x0_device::j_LE_8, &tms340x0_device::j_LE_x, &tms340x0_device::j_LE_x, &tms340x0_device::j_LE_x, &tms340x0_device::j_LE_x, &tms340x0_device::j_LE_x, &tms340x0_device::j_LE_x, &tms340x0_device::j_LE_x, |
| 611 | /* 0xc700 */ |
| 612 | &tms340x0_device::j_GT_0, &tms340x0_device::j_GT_x, &tms340x0_device::j_GT_x, &tms340x0_device::j_GT_x, &tms340x0_device::j_GT_x, &tms340x0_device::j_GT_x, &tms340x0_device::j_GT_x, &tms340x0_device::j_GT_x, |
| 613 | &tms340x0_device::j_GT_8, &tms340x0_device::j_GT_x, &tms340x0_device::j_GT_x, &tms340x0_device::j_GT_x, &tms340x0_device::j_GT_x, &tms340x0_device::j_GT_x, &tms340x0_device::j_GT_x, &tms340x0_device::j_GT_x, |
| 614 | /* 0xc800 */ |
| 615 | &tms340x0_device::j_C_0, &tms340x0_device::j_C_x, &tms340x0_device::j_C_x, &tms340x0_device::j_C_x, &tms340x0_device::j_C_x, &tms340x0_device::j_C_x, &tms340x0_device::j_C_x, &tms340x0_device::j_C_x, |
| 616 | &tms340x0_device::j_C_8, &tms340x0_device::j_C_x, &tms340x0_device::j_C_x, &tms340x0_device::j_C_x, &tms340x0_device::j_C_x, &tms340x0_device::j_C_x, &tms340x0_device::j_C_x, &tms340x0_device::j_C_x, |
| 617 | /* 0xc900 */ |
| 618 | &tms340x0_device::j_NC_0, &tms340x0_device::j_NC_x, &tms340x0_device::j_NC_x, &tms340x0_device::j_NC_x, &tms340x0_device::j_NC_x, &tms340x0_device::j_NC_x, &tms340x0_device::j_NC_x, &tms340x0_device::j_NC_x, |
| 619 | &tms340x0_device::j_NC_8, &tms340x0_device::j_NC_x, &tms340x0_device::j_NC_x, &tms340x0_device::j_NC_x, &tms340x0_device::j_NC_x, &tms340x0_device::j_NC_x, &tms340x0_device::j_NC_x, &tms340x0_device::j_NC_x, |
| 620 | /* 0xca00 */ |
| 621 | &tms340x0_device::j_EQ_0, &tms340x0_device::j_EQ_x, &tms340x0_device::j_EQ_x, &tms340x0_device::j_EQ_x, &tms340x0_device::j_EQ_x, &tms340x0_device::j_EQ_x, &tms340x0_device::j_EQ_x, &tms340x0_device::j_EQ_x, |
| 622 | &tms340x0_device::j_EQ_8, &tms340x0_device::j_EQ_x, &tms340x0_device::j_EQ_x, &tms340x0_device::j_EQ_x, &tms340x0_device::j_EQ_x, &tms340x0_device::j_EQ_x, &tms340x0_device::j_EQ_x, &tms340x0_device::j_EQ_x, |
| 623 | /* 0xcb00 */ |
| 624 | &tms340x0_device::j_NE_0, &tms340x0_device::j_NE_x, &tms340x0_device::j_NE_x, &tms340x0_device::j_NE_x, &tms340x0_device::j_NE_x, &tms340x0_device::j_NE_x, &tms340x0_device::j_NE_x, &tms340x0_device::j_NE_x, |
| 625 | &tms340x0_device::j_NE_8, &tms340x0_device::j_NE_x, &tms340x0_device::j_NE_x, &tms340x0_device::j_NE_x, &tms340x0_device::j_NE_x, &tms340x0_device::j_NE_x, &tms340x0_device::j_NE_x, &tms340x0_device::j_NE_x, |
| 626 | /* 0xcc00 */ |
| 627 | &tms340x0_device::j_V_0, &tms340x0_device::j_V_x, &tms340x0_device::j_V_x, &tms340x0_device::j_V_x, &tms340x0_device::j_V_x, &tms340x0_device::j_V_x, &tms340x0_device::j_V_x, &tms340x0_device::j_V_x, |
| 628 | &tms340x0_device::j_V_8, &tms340x0_device::j_V_x, &tms340x0_device::j_V_x, &tms340x0_device::j_V_x, &tms340x0_device::j_V_x, &tms340x0_device::j_V_x, &tms340x0_device::j_V_x, &tms340x0_device::j_V_x, |
| 629 | /* 0xcd00 */ |
| 630 | &tms340x0_device::j_NV_0, &tms340x0_device::j_NV_x, &tms340x0_device::j_NV_x, &tms340x0_device::j_NV_x, &tms340x0_device::j_NV_x, &tms340x0_device::j_NV_x, &tms340x0_device::j_NV_x, &tms340x0_device::j_NV_x, |
| 631 | &tms340x0_device::j_NV_8, &tms340x0_device::j_NV_x, &tms340x0_device::j_NV_x, &tms340x0_device::j_NV_x, &tms340x0_device::j_NV_x, &tms340x0_device::j_NV_x, &tms340x0_device::j_NV_x, &tms340x0_device::j_NV_x, |
| 632 | /* 0xce00 */ |
| 633 | &tms340x0_device::j_N_0, &tms340x0_device::j_N_x, &tms340x0_device::j_N_x, &tms340x0_device::j_N_x, &tms340x0_device::j_N_x, &tms340x0_device::j_N_x, &tms340x0_device::j_N_x, &tms340x0_device::j_N_x, |
| 634 | &tms340x0_device::j_N_8, &tms340x0_device::j_N_x, &tms340x0_device::j_N_x, &tms340x0_device::j_N_x, &tms340x0_device::j_N_x, &tms340x0_device::j_N_x, &tms340x0_device::j_N_x, &tms340x0_device::j_N_x, |
| 635 | /* 0xcf00 */ |
| 636 | &tms340x0_device::j_NN_0, &tms340x0_device::j_NN_x, &tms340x0_device::j_NN_x, &tms340x0_device::j_NN_x, &tms340x0_device::j_NN_x, &tms340x0_device::j_NN_x, &tms340x0_device::j_NN_x, &tms340x0_device::j_NN_x, |
| 637 | &tms340x0_device::j_NN_8, &tms340x0_device::j_NN_x, &tms340x0_device::j_NN_x, &tms340x0_device::j_NN_x, &tms340x0_device::j_NN_x, &tms340x0_device::j_NN_x, &tms340x0_device::j_NN_x, &tms340x0_device::j_NN_x, |
| 638 | /* 0xd000 */ |
| 639 | &tms340x0_device::move0_no_ni_a, &tms340x0_device::move0_no_ni_b, &tms340x0_device::move0_no_ni_a, &tms340x0_device::move0_no_ni_b, &tms340x0_device::move0_no_ni_a, &tms340x0_device::move0_no_ni_b, &tms340x0_device::move0_no_ni_a, &tms340x0_device::move0_no_ni_b, |
| 640 | &tms340x0_device::move0_no_ni_a, &tms340x0_device::move0_no_ni_b, &tms340x0_device::move0_no_ni_a, &tms340x0_device::move0_no_ni_b, &tms340x0_device::move0_no_ni_a, &tms340x0_device::move0_no_ni_b, &tms340x0_device::move0_no_ni_a, &tms340x0_device::move0_no_ni_b, |
| 641 | /* 0xd100 */ |
| 642 | &tms340x0_device::move0_no_ni_a, &tms340x0_device::move0_no_ni_b, &tms340x0_device::move0_no_ni_a, &tms340x0_device::move0_no_ni_b, &tms340x0_device::move0_no_ni_a, &tms340x0_device::move0_no_ni_b, &tms340x0_device::move0_no_ni_a, &tms340x0_device::move0_no_ni_b, |
| 643 | &tms340x0_device::move0_no_ni_a, &tms340x0_device::move0_no_ni_b, &tms340x0_device::move0_no_ni_a, &tms340x0_device::move0_no_ni_b, &tms340x0_device::move0_no_ni_a, &tms340x0_device::move0_no_ni_b, &tms340x0_device::move0_no_ni_a, &tms340x0_device::move0_no_ni_b, |
| 644 | /* 0xd200 */ |
| 645 | &tms340x0_device::move1_no_ni_a, &tms340x0_device::move1_no_ni_b, &tms340x0_device::move1_no_ni_a, &tms340x0_device::move1_no_ni_b, &tms340x0_device::move1_no_ni_a, &tms340x0_device::move1_no_ni_b, &tms340x0_device::move1_no_ni_a, &tms340x0_device::move1_no_ni_b, |
| 646 | &tms340x0_device::move1_no_ni_a, &tms340x0_device::move1_no_ni_b, &tms340x0_device::move1_no_ni_a, &tms340x0_device::move1_no_ni_b, &tms340x0_device::move1_no_ni_a, &tms340x0_device::move1_no_ni_b, &tms340x0_device::move1_no_ni_a, &tms340x0_device::move1_no_ni_b, |
| 647 | /* 0xd300 */ |
| 648 | &tms340x0_device::move1_no_ni_a, &tms340x0_device::move1_no_ni_b, &tms340x0_device::move1_no_ni_a, &tms340x0_device::move1_no_ni_b, &tms340x0_device::move1_no_ni_a, &tms340x0_device::move1_no_ni_b, &tms340x0_device::move1_no_ni_a, &tms340x0_device::move1_no_ni_b, |
| 649 | &tms340x0_device::move1_no_ni_a, &tms340x0_device::move1_no_ni_b, &tms340x0_device::move1_no_ni_a, &tms340x0_device::move1_no_ni_b, &tms340x0_device::move1_no_ni_a, &tms340x0_device::move1_no_ni_b, &tms340x0_device::move1_no_ni_a, &tms340x0_device::move1_no_ni_b, |
| 650 | /* 0xd400 */ |
| 651 | &tms340x0_device::move0_a_ni_a,&tms340x0_device::move0_a_ni_b,&tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 652 | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 653 | /* 0xd500 */ |
| 654 | &tms340x0_device::exgf0_a, &tms340x0_device::exgf0_b, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 655 | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 656 | /* 0xd600 */ |
| 657 | &tms340x0_device::move1_a_ni_a,&tms340x0_device::move1_a_ni_b,&tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 658 | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 659 | /* 0xd700 */ |
| 660 | &tms340x0_device::exgf1_a, &tms340x0_device::exgf1_b, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 661 | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 662 | /* 0xd800 */ |
| 663 | &tms340x0_device::cexec_s, &tms340x0_device::cexec_s, &tms340x0_device::cexec_s, &tms340x0_device::cexec_s, &tms340x0_device::cexec_s, &tms340x0_device::cexec_s, &tms340x0_device::cexec_s, &tms340x0_device::cexec_s, |
| 664 | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 665 | /* 0xd900 */ |
| 666 | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 667 | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 668 | /* 0xda00 */ |
| 669 | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 670 | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 671 | /* 0xdb00 */ |
| 672 | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 673 | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 674 | /* 0xdc00 */ |
| 675 | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 676 | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 677 | /* 0xdd00 */ |
| 678 | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 679 | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 680 | /* 0xde00 */ |
| 681 | &tms340x0_device::unimpl, &tms340x0_device::fline, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 682 | &tms340x0_device::unimpl, &tms340x0_device::fline, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 683 | /* 0xdf00 */ |
| 684 | &tms340x0_device::unimpl, &tms340x0_device::line, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 685 | &tms340x0_device::unimpl, &tms340x0_device::line, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 686 | /* 0xe000 */ |
| 687 | &tms340x0_device::add_xy_a, &tms340x0_device::add_xy_b, &tms340x0_device::add_xy_a, &tms340x0_device::add_xy_b, &tms340x0_device::add_xy_a, &tms340x0_device::add_xy_b, &tms340x0_device::add_xy_a, &tms340x0_device::add_xy_b, |
| 688 | &tms340x0_device::add_xy_a, &tms340x0_device::add_xy_b, &tms340x0_device::add_xy_a, &tms340x0_device::add_xy_b, &tms340x0_device::add_xy_a, &tms340x0_device::add_xy_b, &tms340x0_device::add_xy_a, &tms340x0_device::add_xy_b, |
| 689 | /* 0xe100 */ |
| 690 | &tms340x0_device::add_xy_a, &tms340x0_device::add_xy_b, &tms340x0_device::add_xy_a, &tms340x0_device::add_xy_b, &tms340x0_device::add_xy_a, &tms340x0_device::add_xy_b, &tms340x0_device::add_xy_a, &tms340x0_device::add_xy_b, |
| 691 | &tms340x0_device::add_xy_a, &tms340x0_device::add_xy_b, &tms340x0_device::add_xy_a, &tms340x0_device::add_xy_b, &tms340x0_device::add_xy_a, &tms340x0_device::add_xy_b, &tms340x0_device::add_xy_a, &tms340x0_device::add_xy_b, |
| 692 | /* 0xe200 */ |
| 693 | &tms340x0_device::sub_xy_a, &tms340x0_device::sub_xy_b, &tms340x0_device::sub_xy_a, &tms340x0_device::sub_xy_b, &tms340x0_device::sub_xy_a, &tms340x0_device::sub_xy_b, &tms340x0_device::sub_xy_a, &tms340x0_device::sub_xy_b, |
| 694 | &tms340x0_device::sub_xy_a, &tms340x0_device::sub_xy_b, &tms340x0_device::sub_xy_a, &tms340x0_device::sub_xy_b, &tms340x0_device::sub_xy_a, &tms340x0_device::sub_xy_b, &tms340x0_device::sub_xy_a, &tms340x0_device::sub_xy_b, |
| 695 | /* 0xe300 */ |
| 696 | &tms340x0_device::sub_xy_a, &tms340x0_device::sub_xy_b, &tms340x0_device::sub_xy_a, &tms340x0_device::sub_xy_b, &tms340x0_device::sub_xy_a, &tms340x0_device::sub_xy_b, &tms340x0_device::sub_xy_a, &tms340x0_device::sub_xy_b, |
| 697 | &tms340x0_device::sub_xy_a, &tms340x0_device::sub_xy_b, &tms340x0_device::sub_xy_a, &tms340x0_device::sub_xy_b, &tms340x0_device::sub_xy_a, &tms340x0_device::sub_xy_b, &tms340x0_device::sub_xy_a, &tms340x0_device::sub_xy_b, |
| 698 | /* 0xe400 */ |
| 699 | &tms340x0_device::cmp_xy_a, &tms340x0_device::cmp_xy_b, &tms340x0_device::cmp_xy_a, &tms340x0_device::cmp_xy_b, &tms340x0_device::cmp_xy_a, &tms340x0_device::cmp_xy_b, &tms340x0_device::cmp_xy_a, &tms340x0_device::cmp_xy_b, |
| 700 | &tms340x0_device::cmp_xy_a, &tms340x0_device::cmp_xy_b, &tms340x0_device::cmp_xy_a, &tms340x0_device::cmp_xy_b, &tms340x0_device::cmp_xy_a, &tms340x0_device::cmp_xy_b, &tms340x0_device::cmp_xy_a, &tms340x0_device::cmp_xy_b, |
| 701 | /* 0xe500 */ |
| 702 | &tms340x0_device::cmp_xy_a, &tms340x0_device::cmp_xy_b, &tms340x0_device::cmp_xy_a, &tms340x0_device::cmp_xy_b, &tms340x0_device::cmp_xy_a, &tms340x0_device::cmp_xy_b, &tms340x0_device::cmp_xy_a, &tms340x0_device::cmp_xy_b, |
| 703 | &tms340x0_device::cmp_xy_a, &tms340x0_device::cmp_xy_b, &tms340x0_device::cmp_xy_a, &tms340x0_device::cmp_xy_b, &tms340x0_device::cmp_xy_a, &tms340x0_device::cmp_xy_b, &tms340x0_device::cmp_xy_a, &tms340x0_device::cmp_xy_b, |
| 704 | /* 0xe600 */ |
| 705 | &tms340x0_device::cpw_a, &tms340x0_device::cpw_b, &tms340x0_device::cpw_a, &tms340x0_device::cpw_b, &tms340x0_device::cpw_a, &tms340x0_device::cpw_b, &tms340x0_device::cpw_a, &tms340x0_device::cpw_b, |
| 706 | &tms340x0_device::cpw_a, &tms340x0_device::cpw_b, &tms340x0_device::cpw_a, &tms340x0_device::cpw_b, &tms340x0_device::cpw_a, &tms340x0_device::cpw_b, &tms340x0_device::cpw_a, &tms340x0_device::cpw_b, |
| 707 | /* 0xe700 */ |
| 708 | &tms340x0_device::cpw_a, &tms340x0_device::cpw_b, &tms340x0_device::cpw_a, &tms340x0_device::cpw_b, &tms340x0_device::cpw_a, &tms340x0_device::cpw_b, &tms340x0_device::cpw_a, &tms340x0_device::cpw_b, |
| 709 | &tms340x0_device::cpw_a, &tms340x0_device::cpw_b, &tms340x0_device::cpw_a, &tms340x0_device::cpw_b, &tms340x0_device::cpw_a, &tms340x0_device::cpw_b, &tms340x0_device::cpw_a, &tms340x0_device::cpw_b, |
| 710 | /* 0xe800 */ |
| 711 | &tms340x0_device::cvxyl_a, &tms340x0_device::cvxyl_b, &tms340x0_device::cvxyl_a, &tms340x0_device::cvxyl_b, &tms340x0_device::cvxyl_a, &tms340x0_device::cvxyl_b, &tms340x0_device::cvxyl_a, &tms340x0_device::cvxyl_b, |
| 712 | &tms340x0_device::cvxyl_a, &tms340x0_device::cvxyl_b, &tms340x0_device::cvxyl_a, &tms340x0_device::cvxyl_b, &tms340x0_device::cvxyl_a, &tms340x0_device::cvxyl_b, &tms340x0_device::cvxyl_a, &tms340x0_device::cvxyl_b, |
| 713 | /* 0xe900 */ |
| 714 | &tms340x0_device::cvxyl_a, &tms340x0_device::cvxyl_b, &tms340x0_device::cvxyl_a, &tms340x0_device::cvxyl_b, &tms340x0_device::cvxyl_a, &tms340x0_device::cvxyl_b, &tms340x0_device::cvxyl_a, &tms340x0_device::cvxyl_b, |
| 715 | &tms340x0_device::cvxyl_a, &tms340x0_device::cvxyl_b, &tms340x0_device::cvxyl_a, &tms340x0_device::cvxyl_b, &tms340x0_device::cvxyl_a, &tms340x0_device::cvxyl_b, &tms340x0_device::cvxyl_a, &tms340x0_device::cvxyl_b, |
| 716 | /* 0xea00 */ |
| 717 | &tms340x0_device::cvsxyl_a, &tms340x0_device::cvsxyl_b, &tms340x0_device::cvsxyl_a, &tms340x0_device::cvsxyl_b, &tms340x0_device::cvsxyl_a, &tms340x0_device::cvsxyl_b, &tms340x0_device::cvsxyl_a, &tms340x0_device::cvsxyl_b, |
| 718 | &tms340x0_device::cvsxyl_a, &tms340x0_device::cvsxyl_b, &tms340x0_device::cvsxyl_a, &tms340x0_device::cvsxyl_b, &tms340x0_device::cvsxyl_a, &tms340x0_device::cvsxyl_b, &tms340x0_device::cvsxyl_a, &tms340x0_device::cvsxyl_b, |
| 719 | /* 0xeb00 */ |
| 720 | &tms340x0_device::cvsxyl_a, &tms340x0_device::cvsxyl_b, &tms340x0_device::cvsxyl_a, &tms340x0_device::cvsxyl_b, &tms340x0_device::cvsxyl_a, &tms340x0_device::cvsxyl_b, &tms340x0_device::cvsxyl_a, &tms340x0_device::cvsxyl_b, |
| 721 | &tms340x0_device::cvsxyl_a, &tms340x0_device::cvsxyl_b, &tms340x0_device::cvsxyl_a, &tms340x0_device::cvsxyl_b, &tms340x0_device::cvsxyl_a, &tms340x0_device::cvsxyl_b, &tms340x0_device::cvsxyl_a, &tms340x0_device::cvsxyl_b, |
| 722 | /* 0xec00 */ |
| 723 | &tms340x0_device::movx_a, &tms340x0_device::movx_b, &tms340x0_device::movx_a, &tms340x0_device::movx_b, &tms340x0_device::movx_a, &tms340x0_device::movx_b, &tms340x0_device::movx_a, &tms340x0_device::movx_b, |
| 724 | &tms340x0_device::movx_a, &tms340x0_device::movx_b, &tms340x0_device::movx_a, &tms340x0_device::movx_b, &tms340x0_device::movx_a, &tms340x0_device::movx_b, &tms340x0_device::movx_a, &tms340x0_device::movx_b, |
| 725 | /* 0xed00 */ |
| 726 | &tms340x0_device::movx_a, &tms340x0_device::movx_b, &tms340x0_device::movx_a, &tms340x0_device::movx_b, &tms340x0_device::movx_a, &tms340x0_device::movx_b, &tms340x0_device::movx_a, &tms340x0_device::movx_b, |
| 727 | &tms340x0_device::movx_a, &tms340x0_device::movx_b, &tms340x0_device::movx_a, &tms340x0_device::movx_b, &tms340x0_device::movx_a, &tms340x0_device::movx_b, &tms340x0_device::movx_a, &tms340x0_device::movx_b, |
| 728 | /* 0xee00 */ |
| 729 | &tms340x0_device::movy_a, &tms340x0_device::movy_b, &tms340x0_device::movy_a, &tms340x0_device::movy_b, &tms340x0_device::movy_a, &tms340x0_device::movy_b, &tms340x0_device::movy_a, &tms340x0_device::movy_b, |
| 730 | &tms340x0_device::movy_a, &tms340x0_device::movy_b, &tms340x0_device::movy_a, &tms340x0_device::movy_b, &tms340x0_device::movy_a, &tms340x0_device::movy_b, &tms340x0_device::movy_a, &tms340x0_device::movy_b, |
| 731 | /* 0xef00 */ |
| 732 | &tms340x0_device::movy_a, &tms340x0_device::movy_b, &tms340x0_device::movy_a, &tms340x0_device::movy_b, &tms340x0_device::movy_a, &tms340x0_device::movy_b, &tms340x0_device::movy_a, &tms340x0_device::movy_b, |
| 733 | &tms340x0_device::movy_a, &tms340x0_device::movy_b, &tms340x0_device::movy_a, &tms340x0_device::movy_b, &tms340x0_device::movy_a, &tms340x0_device::movy_b, &tms340x0_device::movy_a, &tms340x0_device::movy_b, |
| 734 | /* 0xf000 */ |
| 735 | &tms340x0_device::pixt_rixy_a, &tms340x0_device::pixt_rixy_b, &tms340x0_device::pixt_rixy_a, &tms340x0_device::pixt_rixy_b, &tms340x0_device::pixt_rixy_a, &tms340x0_device::pixt_rixy_b, &tms340x0_device::pixt_rixy_a, &tms340x0_device::pixt_rixy_b, |
| 736 | &tms340x0_device::pixt_rixy_a, &tms340x0_device::pixt_rixy_b, &tms340x0_device::pixt_rixy_a, &tms340x0_device::pixt_rixy_b, &tms340x0_device::pixt_rixy_a, &tms340x0_device::pixt_rixy_b, &tms340x0_device::pixt_rixy_a, &tms340x0_device::pixt_rixy_b, |
| 737 | /* 0xf100 */ |
| 738 | &tms340x0_device::pixt_rixy_a, &tms340x0_device::pixt_rixy_b, &tms340x0_device::pixt_rixy_a, &tms340x0_device::pixt_rixy_b, &tms340x0_device::pixt_rixy_a, &tms340x0_device::pixt_rixy_b, &tms340x0_device::pixt_rixy_a, &tms340x0_device::pixt_rixy_b, |
| 739 | &tms340x0_device::pixt_rixy_a, &tms340x0_device::pixt_rixy_b, &tms340x0_device::pixt_rixy_a, &tms340x0_device::pixt_rixy_b, &tms340x0_device::pixt_rixy_a, &tms340x0_device::pixt_rixy_b, &tms340x0_device::pixt_rixy_a, &tms340x0_device::pixt_rixy_b, |
| 740 | /* 0xf200 */ |
| 741 | &tms340x0_device::pixt_ixyr_a, &tms340x0_device::pixt_ixyr_b, &tms340x0_device::pixt_ixyr_a, &tms340x0_device::pixt_ixyr_b, &tms340x0_device::pixt_ixyr_a, &tms340x0_device::pixt_ixyr_b, &tms340x0_device::pixt_ixyr_a, &tms340x0_device::pixt_ixyr_b, |
| 742 | &tms340x0_device::pixt_ixyr_a, &tms340x0_device::pixt_ixyr_b, &tms340x0_device::pixt_ixyr_a, &tms340x0_device::pixt_ixyr_b, &tms340x0_device::pixt_ixyr_a, &tms340x0_device::pixt_ixyr_b, &tms340x0_device::pixt_ixyr_a, &tms340x0_device::pixt_ixyr_b, |
| 743 | /* 0xf300 */ |
| 744 | &tms340x0_device::pixt_ixyr_a, &tms340x0_device::pixt_ixyr_b, &tms340x0_device::pixt_ixyr_a, &tms340x0_device::pixt_ixyr_b, &tms340x0_device::pixt_ixyr_a, &tms340x0_device::pixt_ixyr_b, &tms340x0_device::pixt_ixyr_a, &tms340x0_device::pixt_ixyr_b, |
| 745 | &tms340x0_device::pixt_ixyr_a, &tms340x0_device::pixt_ixyr_b, &tms340x0_device::pixt_ixyr_a, &tms340x0_device::pixt_ixyr_b, &tms340x0_device::pixt_ixyr_a, &tms340x0_device::pixt_ixyr_b, &tms340x0_device::pixt_ixyr_a, &tms340x0_device::pixt_ixyr_b, |
| 746 | /* 0xf400 */ |
| 747 | &tms340x0_device::pixt_ixyixy_a, &tms340x0_device::pixt_ixyixy_b, &tms340x0_device::pixt_ixyixy_a, &tms340x0_device::pixt_ixyixy_b, &tms340x0_device::pixt_ixyixy_a, &tms340x0_device::pixt_ixyixy_b, &tms340x0_device::pixt_ixyixy_a, &tms340x0_device::pixt_ixyixy_b, |
| 748 | &tms340x0_device::pixt_ixyixy_a, &tms340x0_device::pixt_ixyixy_b, &tms340x0_device::pixt_ixyixy_a, &tms340x0_device::pixt_ixyixy_b, &tms340x0_device::pixt_ixyixy_a, &tms340x0_device::pixt_ixyixy_b, &tms340x0_device::pixt_ixyixy_a, &tms340x0_device::pixt_ixyixy_b, |
| 749 | /* 0xf500 */ |
| 750 | &tms340x0_device::pixt_ixyixy_a, &tms340x0_device::pixt_ixyixy_b, &tms340x0_device::pixt_ixyixy_a, &tms340x0_device::pixt_ixyixy_b, &tms340x0_device::pixt_ixyixy_a, &tms340x0_device::pixt_ixyixy_b, &tms340x0_device::pixt_ixyixy_a, &tms340x0_device::pixt_ixyixy_b, |
| 751 | &tms340x0_device::pixt_ixyixy_a, &tms340x0_device::pixt_ixyixy_b, &tms340x0_device::pixt_ixyixy_a, &tms340x0_device::pixt_ixyixy_b, &tms340x0_device::pixt_ixyixy_a, &tms340x0_device::pixt_ixyixy_b, &tms340x0_device::pixt_ixyixy_a, &tms340x0_device::pixt_ixyixy_b, |
| 752 | /* 0xf600 */ |
| 753 | &tms340x0_device::drav_a, &tms340x0_device::drav_b, &tms340x0_device::drav_a, &tms340x0_device::drav_b, &tms340x0_device::drav_a, &tms340x0_device::drav_b, &tms340x0_device::drav_a, &tms340x0_device::drav_b, |
| 754 | &tms340x0_device::drav_a, &tms340x0_device::drav_b, &tms340x0_device::drav_a, &tms340x0_device::drav_b, &tms340x0_device::drav_a, &tms340x0_device::drav_b, &tms340x0_device::drav_a, &tms340x0_device::drav_b, |
| 755 | /* 0xf700 */ |
| 756 | &tms340x0_device::drav_a, &tms340x0_device::drav_b, &tms340x0_device::drav_a, &tms340x0_device::drav_b, &tms340x0_device::drav_a, &tms340x0_device::drav_b, &tms340x0_device::drav_a, &tms340x0_device::drav_b, |
| 757 | &tms340x0_device::drav_a, &tms340x0_device::drav_b, &tms340x0_device::drav_a, &tms340x0_device::drav_b, &tms340x0_device::drav_a, &tms340x0_device::drav_b, &tms340x0_device::drav_a, &tms340x0_device::drav_b, |
| 758 | /* 0xf800 */ |
| 759 | &tms340x0_device::pixt_ri_a, &tms340x0_device::pixt_ri_b, &tms340x0_device::pixt_ri_a, &tms340x0_device::pixt_ri_b, &tms340x0_device::pixt_ri_a, &tms340x0_device::pixt_ri_b, &tms340x0_device::pixt_ri_a, &tms340x0_device::pixt_ri_b, |
| 760 | &tms340x0_device::pixt_ri_a, &tms340x0_device::pixt_ri_b, &tms340x0_device::pixt_ri_a, &tms340x0_device::pixt_ri_b, &tms340x0_device::pixt_ri_a, &tms340x0_device::pixt_ri_b, &tms340x0_device::pixt_ri_a, &tms340x0_device::pixt_ri_b, |
| 761 | /* 0xf900 */ |
| 762 | &tms340x0_device::pixt_ri_a, &tms340x0_device::pixt_ri_b, &tms340x0_device::pixt_ri_a, &tms340x0_device::pixt_ri_b, &tms340x0_device::pixt_ri_a, &tms340x0_device::pixt_ri_b, &tms340x0_device::pixt_ri_a, &tms340x0_device::pixt_ri_b, |
| 763 | &tms340x0_device::pixt_ri_a, &tms340x0_device::pixt_ri_b, &tms340x0_device::pixt_ri_a, &tms340x0_device::pixt_ri_b, &tms340x0_device::pixt_ri_a, &tms340x0_device::pixt_ri_b, &tms340x0_device::pixt_ri_a, &tms340x0_device::pixt_ri_b, |
| 764 | /* 0xfa00 */ |
| 765 | &tms340x0_device::pixt_ir_a, &tms340x0_device::pixt_ir_b, &tms340x0_device::pixt_ir_a, &tms340x0_device::pixt_ir_b, &tms340x0_device::pixt_ir_a, &tms340x0_device::pixt_ir_b, &tms340x0_device::pixt_ir_a, &tms340x0_device::pixt_ir_b, |
| 766 | &tms340x0_device::pixt_ir_a, &tms340x0_device::pixt_ir_b, &tms340x0_device::pixt_ir_a, &tms340x0_device::pixt_ir_b, &tms340x0_device::pixt_ir_a, &tms340x0_device::pixt_ir_b, &tms340x0_device::pixt_ir_a, &tms340x0_device::pixt_ir_b, |
| 767 | /* 0xfb00 */ |
| 768 | &tms340x0_device::pixt_ir_a, &tms340x0_device::pixt_ir_b, &tms340x0_device::pixt_ir_a, &tms340x0_device::pixt_ir_b, &tms340x0_device::pixt_ir_a, &tms340x0_device::pixt_ir_b, &tms340x0_device::pixt_ir_a, &tms340x0_device::pixt_ir_b, |
| 769 | &tms340x0_device::pixt_ir_a, &tms340x0_device::pixt_ir_b, &tms340x0_device::pixt_ir_a, &tms340x0_device::pixt_ir_b, &tms340x0_device::pixt_ir_a, &tms340x0_device::pixt_ir_b, &tms340x0_device::pixt_ir_a, &tms340x0_device::pixt_ir_b, |
| 770 | /* 0xfc00 */ |
| 771 | &tms340x0_device::pixt_ii_a, &tms340x0_device::pixt_ii_b, &tms340x0_device::pixt_ii_a, &tms340x0_device::pixt_ii_b, &tms340x0_device::pixt_ii_a, &tms340x0_device::pixt_ii_b, &tms340x0_device::pixt_ii_a, &tms340x0_device::pixt_ii_b, |
| 772 | &tms340x0_device::pixt_ii_a, &tms340x0_device::pixt_ii_b, &tms340x0_device::pixt_ii_a, &tms340x0_device::pixt_ii_b, &tms340x0_device::pixt_ii_a, &tms340x0_device::pixt_ii_b, &tms340x0_device::pixt_ii_a, &tms340x0_device::pixt_ii_b, |
| 773 | /* 0xfd00 */ |
| 774 | &tms340x0_device::pixt_ii_a, &tms340x0_device::pixt_ii_b, &tms340x0_device::pixt_ii_a, &tms340x0_device::pixt_ii_b, &tms340x0_device::pixt_ii_a, &tms340x0_device::pixt_ii_b, &tms340x0_device::pixt_ii_a, &tms340x0_device::pixt_ii_b, |
| 775 | &tms340x0_device::pixt_ii_a, &tms340x0_device::pixt_ii_b, &tms340x0_device::pixt_ii_a, &tms340x0_device::pixt_ii_b, &tms340x0_device::pixt_ii_a, &tms340x0_device::pixt_ii_b, &tms340x0_device::pixt_ii_a, &tms340x0_device::pixt_ii_b, |
| 776 | /* 0xfe00 */ |
| 777 | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 778 | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 779 | /* 0xff00 */ |
| 780 | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, |
| 781 | &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl, &tms340x0_device::unimpl |
| 782 | }; |