MAME SVN History

199869 Revisions

r41618 Friday 6th November, 2015 at 14:55:31 UTC by Miodrag Milanović
Cleanup devcpu.h (nw)

trunk/src/devices/cpu/arm7/arm7.h
r250129	r250130
31	31	#define ARM7_MAX_FASTRAM 4
32	32	#define ARM7_MAX_HOTSPOTS 16
33	33
34		enum
35		{
36		CPUINFO_INT_ARM7_DRC_OPTIONS = CPUINFO_INT_CPU_SPECIFIC,
37	34
38		CPUINFO_INT_ARM7_FASTRAM_SELECT,
39		CPUINFO_INT_ARM7_FASTRAM_START,
40		CPUINFO_INT_ARM7_FASTRAM_END,
41		CPUINFO_INT_ARM7_FASTRAM_READONLY,
42
43		CPUINFO_INT_ARM7_HOTSPOT_SELECT,
44		CPUINFO_INT_ARM7_HOTSPOT_PC,
45		CPUINFO_INT_ARM7_HOTSPOT_OPCODE,
46		CPUINFO_INT_ARM7_HOTSPOT_CYCLES,
47
48		CPUINFO_PTR_ARM7_FASTRAM_BASE = CPUINFO_PTR_CPU_SPECIFIC
49		};
50
51	35	/***************************************************************************
52	36	COMPILER-SPECIFIC OPTIONS
53	37	***************************************************************************/

trunk/src/devices/cpu/i4004/i4004.c
r250129	r250130
526	526	return CPU_DISASSEMBLE_NAME(i4004)(this, buffer, pc, oprom, opram, options);
527	527	}
528	528
529		// case CPUINFO_IS_OCTAL: info->i = true; break;

trunk/src/devices/cpu/m68000/m68kcpu.c
r250129	r250130
2157	2157	define_state();
2158	2158	}
2159	2159
2160
2161
2162
2163
2164
2165		/*
2166		case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break;
2167		case CPUINFO_INT_CLOCK_DIVIDER: info->i = 1; break;
2168
2169		case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 24; break;
2170		case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = 0; break;
2171
2172		case CPUINFO_INT_INPUT_STATE + 0: info->i = 0; // there is no level 0
2173		case CPUINFO_INT_INPUT_STATE + 1: info->i = (m68k->virq_state >> 1) & 1; break;
2174		case CPUINFO_INT_INPUT_STATE + 2: info->i = (m68k->virq_state >> 2) & 1; break;
2175		case CPUINFO_INT_INPUT_STATE + 3: info->i = (m68k->virq_state >> 3) & 1; break;
2176		case CPUINFO_INT_INPUT_STATE + 4: info->i = (m68k->virq_state >> 4) & 1; break;
2177		case CPUINFO_INT_INPUT_STATE + 5: info->i = (m68k->virq_state >> 5) & 1; break;
2178		case CPUINFO_INT_INPUT_STATE + 6: info->i = (m68k->virq_state >> 6) & 1; break;
2179		case CPUINFO_INT_INPUT_STATE + 7: info->i = (m68k->virq_state >> 7) & 1; break;
2180
2181		case CPUINFO_STR_FAMILY: strcpy(info->s, "Motorola 68K"); break;
2182		case CPUINFO_STR_VERSION: strcpy(info->s, "4.95"); break;
2183		case CPUINFO_STR_SOURCE_FILE: strcpy(info->s, __FILE__); break;
2184		case CPUINFO_STR_CREDITS: strcpy(info->s, "Copyright Karl Stenerud. All rights reserved. (2.1 fixes HJB, FPU+MMU by RB+HO+OG)"); break;
2185
2186
2187		*/
2188
2189
2190
2191
2192
2193	2160	CPU_DISASSEMBLE( dasm_m68000 )
2194	2161	{
2195	2162	return m68k_disassemble_raw(buffer, pc, oprom, opram, M68K_CPU_TYPE_68000);

trunk/src/devices/cpu/mips/mips3.h
r250129	r250130
197	197	#define MIPS3_MAX_FASTRAM 3
198	198	#define MIPS3_MAX_HOTSPOTS 16
199	199
200		enum
201		{
202		CPUINFO_INT_MIPS3_DRC_OPTIONS = CPUINFO_INT_CPU_SPECIFIC,
203
204		CPUINFO_INT_MIPS3_FASTRAM_SELECT,
205		CPUINFO_INT_MIPS3_FASTRAM_START,
206		CPUINFO_INT_MIPS3_FASTRAM_END,
207		CPUINFO_INT_MIPS3_FASTRAM_READONLY,
208
209		CPUINFO_INT_MIPS3_HOTSPOT_SELECT,
210		CPUINFO_INT_MIPS3_HOTSPOT_PC,
211		CPUINFO_INT_MIPS3_HOTSPOT_OPCODE,
212		CPUINFO_INT_MIPS3_HOTSPOT_CYCLES,
213
214		CPUINFO_PTR_MIPS3_FASTRAM_BASE = CPUINFO_PTR_CPU_SPECIFIC
215		};
216
217
218
219	200	/***************************************************************************
220	201	INTERRUPT CONSTANTS
221	202	***************************************************************************/

trunk/src/devices/cpu/sh2/sh2.h
r250129	r250130
82	82	#define SH2DRC_COMPATIBLE_OPTIONS (SH2DRC_STRICT_VERIFY \| SH2DRC_FLUSH_PC \| SH2DRC_STRICT_PCREL)
83	83	#define SH2DRC_FASTEST_OPTIONS (0)
84	84
85		enum
86		{
87		CPUINFO_INT_SH2_DRC_OPTIONS = CPUINFO_INT_CPU_SPECIFIC,
88
89		CPUINFO_INT_SH2_FASTRAM_SELECT,
90		CPUINFO_INT_SH2_FASTRAM_START,
91		CPUINFO_INT_SH2_FASTRAM_END,
92		CPUINFO_INT_SH2_FASTRAM_READONLY,
93
94		CPUINFO_PTR_SH2_FASTRAM_BASE = CPUINFO_PTR_CPU_SPECIFIC
95		};
96
97	85	#define SH2_MAX_FASTRAM 4
98	86
99	87	class sh2_frontend;

trunk/src/devices/cpu/z180/z180.h
r250129	r250130
120	120	Z180_TABLE_ex /* cycles counts for taken jr/jp/call and interrupt latency (rst opcodes) */
121	121	};
122	122
123		enum
124		{
125		CPUINFO_PTR_Z180_CYCLE_TABLE = CPUINFO_PTR_CPU_SPECIFIC,
126		CPUINFO_PTR_Z180_CYCLE_TABLE_LAST = CPUINFO_PTR_Z180_CYCLE_TABLE + Z180_TABLE_ex
127		};
128
129
130	123	#define Z180_IRQ0 0 /* Execute IRQ1 */
131	124	#define Z180_IRQ1 1 /* Execute IRQ1 */
132	125	#define Z180_IRQ2 2 /* Execute IRQ2 */

trunk/src/emu/devcpu.h
r250129	r250130
17	17	#ifndef __DEVCPU_H__
18	18	#define __DEVCPU_H__
19	19
20		#include "emuopts.h"
21
22	20	//**************************************************************************
23		// CONSTANTS
24		//**************************************************************************
25
26		// CPU information constants
27		const int MAX_REGS = 256;
28		enum
29		{
30		// --- the following bits of info are returned as 64-bit signed integers ---
31		CPUINFO_INT_FIRST = 0x00000,
32
33		CPUINFO_INT_CPU_SPECIFIC = 0x08000, // R/W: CPU-specific values start here
34
35		// --- the following bits of info are returned as pointers to data or functions ---
36		CPUINFO_PTR_FIRST = 0x10000,
37
38		// CPU-specific additions
39		CPUINFO_PTR_INSTRUCTION_COUNTER = 0x14000,
40		// R/O: int *icount
41
42		CPUINFO_PTR_CPU_SPECIFIC = 0x18000, // R/W: CPU-specific values start here
43
44		// --- the following bits of info are returned as pointers to functions ---
45		CPUINFO_FCT_FIRST = 0x20000,
46
47		CPUINFO_FCT_CPU_SPECIFIC = 0x28000, // R/W: CPU-specific values start here
48
49		// --- the following bits of info are returned as NULL-terminated strings ---
50		CPUINFO_STR_FIRST = 0x30000,
51
52		CPUINFO_STR_CPU_SPECIFIC = 0x38000 // R/W: CPU-specific values start here
53		};
54
55
56
57		//**************************************************************************
58	21	// CPU DEVICE CONFIGURATION MACROS
59	22	//**************************************************************************
60	23

199869 Revisions