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r41593 Thursday 5th November, 2015 at 01:21:46 UTC by Robbbert
mZ700 wip: - Increased speed of basic (MT 06058) by using bankdev; - Fixed shift, ctrl, function keys; - Fixed crash when ramdisk accessed; - Patched MZ800 to allow tapes to load; - MZ1500 now starts up and can run some programs;

[src/mame/drivers]	a2600.c mz700.c
[src/mame/includes]	mz700.h
[src/mame/machine]	mz700.c
[src/mame/video]	mz700.c

trunk/src/mame/drivers/a2600.c

r250104	r250105
10	10
11	11	***************************************************************************/
12	12
13		// the new RIOT does not work with the SuperCharger
14		// for example "mame64 a2600 scharger -cass offifrog" fails to load after playing the tape
15		#define USE_NEW_RIOT 0
16
17
18	13	#include "emu.h"
19
	14	#include "machine/mos6530n.h"
20	15	#include "cpu/m6502/m6507.h"
21	16	#include "sound/tiaintf.h"
22	17	#include "video/tia.h"
r250104	r250105
28	23	#include "bus/vcs/compumat.h"
29	24	#include "bus/vcs_ctrl/ctrl.h"
30	25
31
32
33		#if USE_NEW_RIOT
34		#include "machine/mos6530n.h"
35		#else
36		#include "machine/6532riot.h"
37		#endif
38
39
40	26	#define CONTROL1_TAG    "joyport1"
41	27	#define CONTROL2_TAG    "joyport2"
42	28
43	29
44
45	30	class a2600_state : public driver_device
46	31	{
47	32	public:
r250104	r250105
88	73	required_device<m6507_device> m_maincpu;
89	74	required_device<screen_device> m_screen;
90	75	required_ioport m_swb;
91		#if USE_NEW_RIOT
92	76	required_device<mos6532_t> m_riot;
93		#else
94		required_device<riot6532_device> m_riot;
95		#endif
96
97	77	};
98	78
99	79
r250104	r250105
108	88	static ADDRESS_MAP_START(a2600_mem, AS_PROGRAM, 8, a2600_state ) // 6507 has 13-bit address space, 0x0000 - 0x1fff
109	89	AM_RANGE(0x0000, 0x007f) AM_MIRROR(0x0f00) AM_DEVREADWRITE("tia_video", tia_video_device, read, write)
110	90	AM_RANGE(0x0080, 0x00ff) AM_MIRROR(0x0d00) AM_RAM AM_SHARE("riot_ram")
111		#if USE_NEW_RIOT
112	91	AM_RANGE(0x0280, 0x029f) AM_MIRROR(0x0d00) AM_DEVICE("riot", mos6532_t, io_map)
113		#else
114		AM_RANGE(0x0280, 0x029f) AM_MIRROR(0x0d00) AM_DEVREADWRITE("riot", riot6532_device, read, write)
115		#endif
116	92	// AM_RANGE(0x1000, 0x1fff) is cart data and it is configured at reset time, depending on the mounted cart!
117	93	ADDRESS_MAP_END
118	94
r250104	r250105
140	116	}
141	117	else if (masked_offset < 0x2a0)
142	118	{
143		#if USE_NEW_RIOT
144	119	ret = m_riot->io_r(space, masked_offset);
145		#else
146		ret = m_riot->read(space, masked_offset);
147		#endif
148	120	}
149	121	else if (masked_offset < 0x300)
150	122	{
r250104	r250105
176	148	}
177	149	else if (masked_offset < 0x2a0)
178	150	{
179		#if USE_NEW_RIOT
180	151	m_riot->io_w(space, masked_offset, data);
181		#else
182		m_riot->write(space, masked_offset, data);
183		#endif
184	152	}
185	153	else if (masked_offset < 0x300)
186	154	{
r250104	r250105
595	563	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.90)
596	564
597	565	/* devices */
598		#if USE_NEW_RIOT
599	566	MCFG_DEVICE_ADD("riot", MOS6532n, MASTER_CLOCK_NTSC / 3)
600		MCFG_MOS6530n_IN_PA_CB(READ8(a2600_state, switch_A_r))
601		MCFG_MOS6530n_OUT_PA_CB(WRITE8(a2600_state, switch_A_w))
602		MCFG_MOS6530n_IN_PB_CB(READ8(a2600_state, riot_input_port_8_r))
603		MCFG_MOS6530n_OUT_PB_CB(WRITE8(a2600_state, switch_B_w))
604		MCFG_MOS6530n_IRQ_CB(WRITELINE(a2600_state, irq_callback))
605		#else
606		MCFG_DEVICE_ADD("riot", RIOT6532, MASTER_CLOCK_NTSC / 3)
607		MCFG_RIOT6532_IN_PA_CB(READ8(a2600_state, switch_A_r))
608		MCFG_RIOT6532_OUT_PA_CB(WRITE8(a2600_state, switch_A_w))
609		MCFG_RIOT6532_IN_PB_CB(READ8(a2600_state, riot_input_port_8_r))
610		MCFG_RIOT6532_OUT_PB_CB(WRITE8(a2600_state, switch_B_w))
611		MCFG_RIOT6532_IRQ_CB(WRITELINE(a2600_state, irq_callback))
612		#endif
	567	MCFG_MOS6530n_IN_PA_CB(READ8(a2600_state, switch_A_r))
	568	MCFG_MOS6530n_OUT_PA_CB(WRITE8(a2600_state, switch_A_w))
	569	MCFG_MOS6530n_IN_PB_CB(READ8(a2600_state, riot_input_port_8_r))
	570	MCFG_MOS6530n_OUT_PB_CB(WRITE8(a2600_state, switch_B_w))
	571	MCFG_MOS6530n_IRQ_CB(WRITELINE(a2600_state, irq_callback))
613	572
614	573	MCFG_VCS_CONTROL_PORT_ADD(CONTROL1_TAG, vcs_control_port_devices, "joy")
615	574	MCFG_VCS_CONTROL_PORT_ADD(CONTROL2_TAG, vcs_control_port_devices, NULL)
r250104	r250105
645	604	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.90)
646	605
647	606	/* devices */
648		#if USE_NEW_RIOT
649		MCFG_DEVICE_ADD("riot", MOS6532n, MASTER_CLOCK_PAL / 3)
650		MCFG_MOS6530n_IN_PA_CB(READ8(a2600_state, switch_A_r))
651		MCFG_MOS6530n_OUT_PA_CB(WRITE8(a2600_state, switch_A_w))
652		MCFG_MOS6530n_IN_PB_CB(READ8(a2600_state, riot_input_port_8_r))
653		MCFG_MOS6530n_OUT_PB_CB(WRITE8(a2600_state, switch_B_w))
654		MCFG_MOS6530n_IRQ_CB(WRITELINE(a2600_state, irq_callback))
655		#else
656		MCFG_DEVICE_ADD("riot", RIOT6532, MASTER_CLOCK_PAL / 3)
657		MCFG_RIOT6532_IN_PA_CB(READ8(a2600_state, switch_A_r))
658		MCFG_RIOT6532_OUT_PA_CB(WRITE8(a2600_state, switch_A_w))
659		MCFG_RIOT6532_IN_PB_CB(READ8(a2600_state, riot_input_port_8_r))
660		MCFG_RIOT6532_OUT_PB_CB(WRITE8(a2600_state, switch_B_w))
661		MCFG_RIOT6532_IRQ_CB(WRITELINE(a2600_state, irq_callback))
662		#endif
	607	MCFG_DEVICE_ADD("riot", MOS6532n, MASTER_CLOCK_PAL / 3)
	608	MCFG_MOS6530n_IN_PA_CB(READ8(a2600_state, switch_A_r))
	609	MCFG_MOS6530n_OUT_PA_CB(WRITE8(a2600_state, switch_A_w))
	610	MCFG_MOS6530n_IN_PB_CB(READ8(a2600_state, riot_input_port_8_r))
	611	MCFG_MOS6530n_OUT_PB_CB(WRITE8(a2600_state, switch_B_w))
	612	MCFG_MOS6530n_IRQ_CB(WRITELINE(a2600_state, irq_callback))
663	613
664	614	MCFG_VCS_CONTROL_PORT_ADD(CONTROL1_TAG, vcs_control_port_devices, "joy")
665	615	MCFG_VCS_CONTROL_PORT_ADD(CONTROL2_TAG, vcs_control_port_devices, NULL)

trunk/src/mame/drivers/mz700.c

r250104	r250105
59	59	*  D000-DFFF   videoram or RAM
60	60	*  E000-FFFF   memory mapped IO or RAM
61	61	*
	62	*  ToDo:
	63	- slows down while making sound
	64	- MZ800:
	65	- Had to patch the rom to load cassettes
	66	- Port CF not done.
	67	- Dips not connected.
	68	- MZ800-mode display not working /Hi-res not coded.
	69	- The CRTC is a very complex custom device, mostly unemulated.
	70	- MZ1500:
	71	- Various ports not done.
	72	- Floppy disk and quick disk not done.
	73	- F4 display is blank.
	74	- Need manuals.
	75
	76	Note: MZ800 hardware starts in memory map (mode A), but switches to MZ700
	77	compatibility mode (mode B) as soon as it starts up. We start in Mode B
	78	because it helps MZ1500 get started and it doesn't break anything.
	79
	80	*
62	81	*****************************************************************************/
63	82
64	83	#include "emu.h"
r250104	r250105
97	116	***************************************************************************/
98	117
99	118	static ADDRESS_MAP_START( mz700_mem, AS_PROGRAM, 8, mz_state )
	119	AM_RANGE(0x0000, 0x0fff) AM_READ_BANK("bankr0") AM_WRITE_BANK("bankw0")
	120	AM_RANGE(0x1000, 0xcfff) AM_RAM
	121	AM_RANGE(0xd000, 0xdfff) AM_RAMBANK("bankd")
	122	AM_RANGE(0xe000, 0xffff) AM_DEVICE("banke", address_map_bank_device, amap8)
100	123	ADDRESS_MAP_END
101	124
	125	static ADDRESS_MAP_START( mz700_banke, AS_PROGRAM, 8, mz_state )
	126	// bank 0: ram (mz700_bank1)
	127	AM_RANGE(0x0000, 0x1fff) AM_RAM
	128	// bank 1: devices (mz700_bank3)
	129	AM_RANGE(0x2000, 0x2003) AM_MIRROR(0x1ff0) AM_DEVREADWRITE("ppi8255", i8255_device, read, write)
	130	AM_RANGE(0x2004, 0x2007) AM_MIRROR(0x1ff0) AM_DEVREADWRITE("pit8253", pit8253_device, read, write)
	131	AM_RANGE(0x2008, 0x200b) AM_MIRROR(0x1ff0) AM_READWRITE(mz700_e008_r,mz700_e008_w)
	132	AM_RANGE(0x200c, 0x200f) AM_MIRROR(0x1ff0) AM_NOP
	133	// bank 2: switched out (mz700_bank5)
	134	AM_RANGE(0x4000, 0x5fff) AM_NOP
	135	ADDRESS_MAP_END
	136
102	137	static ADDRESS_MAP_START( mz700_io, AS_IO, 8, mz_state )
103	138	ADDRESS_MAP_GLOBAL_MASK(0xff)
104	139	AM_RANGE(0xe0, 0xe0) AM_WRITE(mz700_bank_0_w)
r250104	r250105
111	146	ADDRESS_MAP_END
112	147
113	148	static ADDRESS_MAP_START( mz800_mem, AS_PROGRAM, 8, mz_state )
	149	AM_RANGE(0x0000, 0x0fff) AM_READ_BANK("bankr0") AM_WRITE_BANK("bankw0")
	150	AM_RANGE(0x1000, 0x1fff) AM_RAMBANK("bank1")
	151	AM_RANGE(0x2000, 0x7fff) AM_RAM
	152	AM_RANGE(0x8000, 0xbfff) AM_RAMBANK("banka")
	153	AM_RANGE(0xc000, 0xcfff) AM_RAMBANK("bankc")
	154	AM_RANGE(0xd000, 0xdfff) AM_RAMBANK("bankd")
	155	AM_RANGE(0xe000, 0xffff) AM_DEVICE("bankf", address_map_bank_device, amap8)
114	156	ADDRESS_MAP_END
115	157
	158	static ADDRESS_MAP_START( mz800_bankf, AS_PROGRAM, 8, mz_state )
	159	// bank 0: ram (mz700_bank1)
	160	AM_RANGE(0x0000, 0x1fff) AM_RAM
	161	// bank 1: devices (mz700_bank3)
	162	AM_RANGE(0x2000, 0x2003) AM_DEVREADWRITE("ppi8255", i8255_device, read, write)
	163	AM_RANGE(0x2004, 0x2007) AM_DEVREADWRITE("pit8253", pit8253_device, read, write)
	164	AM_RANGE(0x2008, 0x200b) AM_READWRITE(mz700_e008_r,mz700_e008_w)
	165	AM_RANGE(0x200c, 0x200f) AM_NOP
	166	AM_RANGE(0x2010, 0x3fff) AM_ROM AM_REGION("monitor", 0x2010)
	167	// bank 2: switched out (mz700_bank5)
	168	AM_RANGE(0x4000, 0x5fff) AM_NOP
	169	ADDRESS_MAP_END
	170
116	171	static ADDRESS_MAP_START( mz800_io, AS_IO, 8, mz_state )
117	172	ADDRESS_MAP_GLOBAL_MASK(0xff)
118	173	AM_RANGE(0xcc, 0xcc) AM_WRITE(mz800_write_format_w )
r250104	r250105
303	358	};
304	359
305	360	static GFXDECODE_START( mz700 )
306		GFXDECODE_ENTRY("cgrom", 0, mz700_layout, 0, 256)
	361	GFXDECODE_ENTRY("cgrom", 0, mz700_layout, 0, 4)
307	362	GFXDECODE_END
308	363
309	364	static GFXDECODE_START( mz800 )
310		GFXDECODE_ENTRY(NULL, 0, mz700_layout, 0, 256)
311		GFXDECODE_ENTRY("monitor", 0x1000, mz700_layout, 0, 256)    // for mz800 viewer only
	365	GFXDECODE_ENTRY("monitor", 0x1000, mz700_layout, 0, 4)    // for mz800 viewer only
312	366	GFXDECODE_END
313	367
314	368
r250104	r250105
321	375	MCFG_CPU_ADD("maincpu", Z80, XTAL_17_73447MHz/5)
322	376	MCFG_CPU_PROGRAM_MAP(mz700_mem)
323	377	MCFG_CPU_IO_MAP(mz700_io)
	378	MCFG_DEVICE_ADD("banke", ADDRESS_MAP_BANK, 0)
	379	MCFG_DEVICE_PROGRAM_MAP(mz700_banke)
	380	MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
	381	MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
	382	MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(16)
	383	MCFG_ADDRESS_MAP_BANK_STRIDE(0x2000)
324	384
	385	MCFG_MACHINE_RESET_OVERRIDE(mz_state, mz700)
325	386
326	387	/* video hardware */
327	388	MCFG_SCREEN_ADD("screen", RASTER)
328	389	MCFG_SCREEN_RAW_PARAMS(XTAL_17_73447MHz/2, 568, 0, 40*8, 312, 0, 25*8)
329	390	MCFG_SCREEN_UPDATE_DRIVER(mz_state, screen_update_mz700)
330	391	MCFG_SCREEN_PALETTE("palette")
	392	MCFG_PALETTE_ADD_3BIT_RGB("palette")
331	393
332	394	MCFG_GFXDECODE_ADD("gfxdecode", "palette", mz700)
333		MCFG_PALETTE_ADD("palette", 256*2)
334		MCFG_PALETTE_INDIRECT_ENTRIES(8)
335		MCFG_PALETTE_INIT_OWNER(mz_state, mz)
336	395
337	396	/* sound hardware */
338	397	MCFG_SPEAKER_STANDARD_MONO("mono")
339	398	MCFG_SOUND_WAVE_ADD(WAVE_TAG, "cassette")
340		MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.25)
	399	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.05)
341	400	MCFG_SOUND_ADD("speaker", SPEAKER_SOUND, 0)
342	401	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.50)
343	402
r250104	r250105
376	435
377	436
378	437	static MACHINE_CONFIG_DERIVED( mz800, mz700 )
	438	MCFG_DEVICE_REMOVE("banke")
379	439
380	440	/* basic machine hardware */
381	441	MCFG_CPU_MODIFY("maincpu")
382	442	MCFG_CPU_PROGRAM_MAP(mz800_mem)
383	443	MCFG_CPU_IO_MAP(mz800_io)
	444	MCFG_DEVICE_ADD("bankf", ADDRESS_MAP_BANK, 0)
	445	MCFG_DEVICE_PROGRAM_MAP(mz800_bankf)
	446	MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
	447	MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
	448	MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(16)
	449	MCFG_ADDRESS_MAP_BANK_STRIDE(0x2000)
384	450
	451	MCFG_MACHINE_RESET_OVERRIDE(mz_state, mz800)
385	452	MCFG_GFXDECODE_MODIFY("gfxdecode",mz800)
386	453
387		MCFG_VIDEO_START_OVERRIDE(mz_state,mz800)
388
389	454	MCFG_SCREEN_MODIFY("screen")
390	455	MCFG_SCREEN_UPDATE_DRIVER(mz_state, screen_update_mz800)
391	456
r250104	r250105
435	500	ROM_START( mz800 )
436	501	ROM_REGION( 0x4000, "monitor", 0 )
437	502	ROM_LOAD( "mz800.rom", 0x0000, 0x4000, CRC(600d17e1) SHA1(950ce4b51429916f8036e41ba6130fac149b36e4) )
	503	// fix cassette loading
	504	ROM_FILL(0x761,1,0x13)
	505	ROM_FILL(0xA4B,1,0x45)
	506
	507	ROM_REGION( 0x10000, "user1", ROMREGION_ERASE00 ) // ramdisk
438	508	ROM_END
439	509
440	510	ROM_START( mz1500 )
441	511	ROM_REGION( 0x4000, "monitor", 0 )
442		ROM_LOAD( "9z-502m.rom",  0x0000, 0x2800, CRC(643db428) SHA1(c2ad8af2ef00db32afde54d5741b07de5d4da16a))
	512	ROM_LOAD( "9z-502m.rom",  0x0000, 0x1000, CRC(643db428) SHA1(c2ad8af2ef00db32afde54d5741b07de5d4da16a))
	513	ROM_CONTINUE(0x2800, 0x1800)
	514
443	515	ROM_REGION( 0x1000, "cgrom", 0 )
444	516	//ROM_LOAD( "mz700fon.jp", 0x0000, 0x1000, CRC(697ec121) SHA1(5eb1d42d273b1fd2cab120486279ab8ff6c85dc7))
445	517	ROM_LOAD( "mz700fon.jpn", 0x0000, 0x1000, CRC(425eedf5) SHA1(bd2cc750f2d2f63e50a59786668509e81a276e32) )
	518
	519	ROM_REGION( 0x10000, "user1", ROMREGION_ERASE00 ) // ramdisk
446	520	ROM_END
447	521
448	522	/***************************************************************************

trunk/src/mame/includes/mz700.h

r250104	r250105
16	16	#include "sound/speaker.h"
17	17	#include "imagedev/cassette.h"
18	18	#include "bus/centronics/ctronics.h"
	19	#include "machine/bankdev.h"
19	20	#include "machine/ram.h"
20	21
21	22	class mz_state : public driver_device
22	23	{
23	24	public:
24	25	mz_state(const machine_config &mconfig, device_type type, const char *tag)
25		: driver_device(mconfig, type, tag),
26		m_maincpu(*this, "maincpu"),
27		m_speaker(*this, "speaker"),
28		m_pit(*this, "pit8253"),
29		m_ppi(*this, "ppi8255"),
30		m_cassette(*this, "cassette"),
31		m_centronics(*this, "centronics"),
32		m_ram(*this, RAM_TAG),
33		m_gfxdecode(*this, "gfxdecode"),
34		m_palette(*this, "palette")  { }
	26	: driver_device(mconfig, type, tag)
	27	, m_maincpu(*this, "maincpu")
	28	, m_speaker(*this, "speaker")
	29	, m_pit(*this, "pit8253")
	30	, m_ppi(*this, "ppi8255")
	31	, m_cassette(*this, "cassette")
	32	, m_centronics(*this, "centronics")
	33	, m_ram(*this, RAM_TAG)
	34	, m_palette(*this, "palette")
	35	, m_banke(*this, "banke")
	36	, m_bankf(*this, "bankf")
	37	{ }
35	38
36		int m_mz700;                /* 1 if running on an mz700 */
37
38		int m_cursor_timer;
39		int m_other_timer;
40
41		int m_intmsk;   /* PPI8255 pin PC2 */
42
43		int m_mz700_ram_lock;       /* 1 if ram lock is active */
44		int m_mz700_ram_vram;       /* 1 if vram is banked in */
45
46		/* mz800 specific */
47		UINT8 *m_cgram;
48
49		int m_mz700_mode;           /* 1 if in mz700 mode */
50		int m_mz800_ram_lock;       /* 1 if lock is active */
51		int m_mz800_ram_monitor;    /* 1 if monitor rom banked in */
52
53		int m_hires_mode;           /* 1 if in 640x200 mode */
54		int m_screennum;           /* screen designation */
55
56		int m_centronics_busy;
57		int m_centronics_perror;
58
59		UINT8 *m_colorram;
60		UINT8 *m_videoram;
61		UINT8 m_speaker_level;
62		UINT8 m_prev_state;
63		UINT16 m_mz800_ramaddr;
64		UINT8 m_mz800_palette[4];
65		UINT8 m_mz800_palette_bank;
66	39	DECLARE_READ8_MEMBER(mz700_e008_r);
67	40	DECLARE_WRITE8_MEMBER(mz700_e008_w);
68	41	DECLARE_READ8_MEMBER(mz800_bank_0_r);
r250104	r250105
87	60	DECLARE_WRITE8_MEMBER(mz800_cgram_w);
88	61	DECLARE_DRIVER_INIT(mz800);
89	62	DECLARE_DRIVER_INIT(mz700);
	63	DECLARE_MACHINE_RESET(mz700);
	64	DECLARE_MACHINE_RESET(mz800);
90	65	virtual void machine_start();
91		DECLARE_PALETTE_INIT(mz);
92		DECLARE_VIDEO_START(mz800);
93	66	UINT32 screen_update_mz700(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
94	67	UINT32 screen_update_mz800(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
95	68	TIMER_DEVICE_CALLBACK_MEMBER(ne556_cursor_callback);
r250104	r250105
105	78	DECLARE_WRITE8_MEMBER(mz800_z80pio_port_a_w);
106	79	DECLARE_WRITE_LINE_MEMBER(write_centronics_busy);
107	80	DECLARE_WRITE_LINE_MEMBER(write_centronics_perror);
	81
	82	private:
	83	int m_mz700;                /* 1 if running on an mz700 */
	84
	85	int m_cursor_timer;
	86	int m_other_timer;
	87
	88	int m_intmsk;   /* PPI8255 pin PC2 */
	89
	90	int m_mz700_ram_lock;       /* 1 if ram lock is active */
	91	int m_mz700_ram_vram;       /* 1 if vram is banked in */
	92
	93	/* mz800 specific */
	94	UINT8 *m_cgram;
	95	UINT8 *m_p_chargen;
	96
	97	int m_mz700_mode;           /* 1 if in mz700 mode */
	98	int m_mz800_ram_lock;       /* 1 if lock is active */
	99	int m_mz800_ram_monitor;    /* 1 if monitor rom banked in */
	100
	101	int m_hires_mode;           /* 1 if in 640x200 mode */
	102	int m_screennum;           /* screen designation */
	103
	104	int m_centronics_busy;
	105	int m_centronics_perror;
	106
	107	UINT8 *m_colorram;
	108	UINT8 *m_videoram;
	109	UINT8 m_speaker_level;
	110	UINT8 m_prev_state;
	111	UINT16 m_mz800_ramaddr;
	112	UINT8 m_mz800_palette[4];
	113	UINT8 m_mz800_palette_bank;
	114
108	115	required_device<cpu_device> m_maincpu;
109	116	required_device<speaker_sound_device> m_speaker;
110	117	required_device<pit8253_device> m_pit;
r250104	r250105
112	119	required_device<cassette_image_device> m_cassette;
113	120	optional_device<centronics_device> m_centronics;
114	121	required_device<ram_device> m_ram;
115		required_device<gfxdecode_device> m_gfxdecode;
116	122	required_device<palette_device> m_palette;
	123	optional_device<address_map_bank_device> m_banke;
	124	optional_device<address_map_bank_device> m_bankf;
117	125	};
118	126
119	127	#endif /* MZ700_H_ */

trunk/src/mame/machine/mz700.c

r250104	r250105
42	42	m_mz700 = TRUE;
43	43	m_mz700_mode = TRUE;
44	44
45		m_videoram = auto_alloc_array(machine(), UINT8, 0x800);
46		memset(m_videoram, 0, sizeof(UINT8) * 0x800);
47		m_colorram = auto_alloc_array(machine(), UINT8, 0x800);
48		memset(m_colorram, 0, sizeof(UINT8) * 0x800);
	45	m_videoram = auto_alloc_array(machine(), UINT8, 0x1000);
	46	memset(m_videoram, 0, sizeof(UINT8) * 0x1000);
	47	m_colorram = m_videoram + 0x800;
	48
	49	m_p_chargen = memregion("cgrom")->base();
	50	UINT8 *rom = memregion("monitor")->base();
	51	UINT8 *ram = m_ram->pointer();
	52	membank("bankr0")->configure_entry(0, &ram[0]); // ram
	53	membank("bankr0")->configure_entry(1, &rom[0]); // rom
	54	membank("bankw0")->configure_entry(0, &ram[0]); // ram
	55	membank("bankd")->configure_entry(0, &ram[0xd000]); // ram
	56	membank("bankd")->configure_entry(1, m_videoram); // vram
49	57	}
50	58
51	59	DRIVER_INIT_MEMBER(mz_state,mz800)
52	60	{
53	61	m_mz700 = FALSE;
54		m_mz700_mode = FALSE;
	62	m_mz700_mode = true;//FALSE;
55	63
56	64	/* video ram */
57	65	m_videoram = auto_alloc_array(machine(), UINT8, 0x4000);
r250104	r250105
61	69	/* character generator ram */
62	70	m_cgram = auto_alloc_array(machine(), UINT8, 0x1000);
63	71	memset(m_cgram, 0, sizeof(UINT8) * 0x1000);
	72
	73	m_p_chargen = memregion("cgrom")->base();
	74	if (!m_p_chargen)
	75	m_p_chargen = m_cgram;
	76	UINT8 *rom = memregion("monitor")->base();
	77	UINT8 *ram = m_ram->pointer();
	78	// configure banks (0 = RAM in all cases)
	79	membank("bankr0")->configure_entry(0, &ram[0]); // ram
	80	membank("bankr0")->configure_entry(1, &rom[0]); // rom
	81	membank("bankw0")->configure_entry(0, &ram[0]); // ram
	82	membank("bank1")->configure_entry(0, &ram[0x1000]); // ram
	83	membank("bank1")->configure_entry(1, &rom[0x1000]); // chargen
	84	membank("banka")->configure_entry(0, &ram[0x8000]); // ram
	85	membank("banka")->configure_entry(1, m_videoram); // vram in mz800 mode
	86	membank("bankc")->configure_entry(0, &ram[0xc000]); // ram
	87	membank("bankc")->configure_entry(1, m_cgram); // cgram in mz800 mode
	88	membank("bankd")->configure_entry(0, &ram[0xd000]); // ram
	89	membank("bankd")->configure_entry(1, m_videoram); // vram in mz700 mode
64	90	}
65	91
66	92	void mz_state::machine_start()
67	93	{
68	94	/* reset memory map to defaults */
69		mz700_bank_4_w(m_maincpu->space(AS_PROGRAM), 0, 0);
	95	mz700_bank_4_w(m_maincpu->space(AS_IO), 0, 0);
70	96	}
71	97
	98	MACHINE_RESET_MEMBER( mz_state, mz700 )
	99	{
	100	membank("bankr0")->set_entry(1); //rom
	101	membank("bankw0")->set_entry(0); //ram
	102	membank("bankd")->set_entry(1); //vram
	103	m_banke->set_bank(1); //devices
	104	}
72	105
	106	MACHINE_RESET_MEMBER( mz_state, mz800 )
	107	{
	108	// default to mz700 mode or mz1500 won't start.
	109	membank("bankr0")->set_entry(1); //rom
	110	membank("bankw0")->set_entry(0); //ram
	111	membank("bank1")->set_entry(0); //ram
	112	membank("banka")->set_entry(0); //ram
	113	membank("bankc")->set_entry(0); //ram
	114	membank("bankd")->set_entry(1); //vram
	115	m_bankf->set_bank(1); //devices
	116	}
	117
	118
73	119	/***************************************************************************
74	120	MMIO
75	121	***************************************************************************/
r250104	r250105
99	145
100	146	READ8_MEMBER(mz_state::mz800_bank_0_r)
101	147	{
102		UINT8 *videoram = m_videoram;
103	148	address_space &spc = m_maincpu->space(AS_PROGRAM);
104	149
105	150	/* switch in cgrom */
106		spc.install_read_bank(0x1000, 0x1fff, "bank2");
107		spc.nop_write(0x1000, 0x1fff);
108		membank("bank2")->set_base(memregion("monitor")->base() + 0x1000);
	151	//spc.install_read_bank(0x1000, 0x1fff, "bank2");
	152	//spc.nop_write(0x1000, 0x1fff);
	153	//membank("bank2")->set_base(memregion("monitor")->base() + 0x1000);
	154	membank("bank1")->set_entry(1);
109	155
110	156	if (m_mz700_mode)
111	157	{
112	158	/* cgram from 0xc000 to 0xcfff */
113		spc.install_read_bank(0xc000, 0xcfff, "bank6");
114		spc.install_write_handler(0xc000, 0xcfff, write8_delegate(FUNC(mz_state::mz800_cgram_w),this));
115		membank("bank6")->set_base(m_cgram);
	159	//spc.install_read_bank(0xc000, 0xcfff, "bank6");
	160	//spc.install_write_handler(0xc000, 0xcfff, write8_delegate(FUNC(mz_state::mz800_cgram_w),this));
	161	//membank("bank6")->set_base(m_cgram);
	162	membank("bankc")->set_entry(1);
116	163	}
117	164	else
118	165	{
119	166	if (m_hires_mode)
120	167	{
121	168	/* vram from 0x8000 to 0xbfff */
122		spc.install_readwrite_bank(0x8000, 0xbfff, "bank4");
123		membank("bank4")->set_base(videoram);
	169	//spc.install_readwrite_bank(0x8000, 0xbfff, "bank4");
	170	//membank("bank4")->set_base(m_videoram);
	171	membank("banka")->set_entry(1);
124	172	}
125	173	else
126	174	{
127	175	/* vram from 0x8000 to 0x9fff */
128		spc.install_readwrite_bank(0x8000, 0x9fff, "bank4");
129		membank("bank4")->set_base(videoram);
	176	//spc.install_readwrite_bank(0x8000, 0x9fff, "bank4");
	177	//membank("bank4")->set_base(m_videoram);
130	178
131	179	/* ram from 0xa000 to 0xbfff */
132		spc.install_readwrite_bank(0xa000, 0xbfff, "bank5");
133		membank("bank5")->set_base(m_ram->pointer() + 0xa000);
	180	//spc.install_readwrite_bank(0xa000, 0xbfff, "bank5");
	181	//membank("bank5")->set_base(m_ram->pointer() + 0xa000);
	182	membank("bank1")->set_entry(1);
134	183	}
135	184	}
136	185
r250104	r250105
141	190	{
142	191	address_space &spc = m_maincpu->space(AS_PROGRAM);
143	192
144		spc.install_readwrite_bank(0x0000, 0x0fff, "bank1");
145		membank("bank1")->set_base(m_ram->pointer());
	193	//spc.install_readwrite_bank(0x0000, 0x0fff, "bank1a");
	194	//membank("bank1a")->set_base(m_ram->pointer());
	195	membank("bankr0")->set_entry(0); // ram
146	196	}
147	197
148	198	WRITE8_MEMBER(mz_state::mz800_bank_0_w)
149	199	{
150		address_space &spc = m_maincpu->space(AS_PROGRAM);
	200	//address_space &spc = m_maincpu->space(AS_PROGRAM);
151	201
152		spc.install_readwrite_bank(0x0000, 0x7fff, "bank1");
153		membank("bank1")->set_base(m_ram->pointer());
	202	//spc.install_readwrite_bank(0x0000, 0x7fff, "bank1a");
	203	//membank("bank1a")->set_base(m_ram->pointer());
	204	membank("bank1")->set_entry(0); // ram
	205	membank("bankr0")->set_entry(0); // ram
154	206	}
155	207
156	208	READ8_MEMBER(mz_state::mz800_bank_1_r)
r250104	r250105
158	210	address_space &spc = m_maincpu->space(AS_PROGRAM);
159	211
160	212	/* switch in ram from 0x1000 to 0x1fff */
161		spc.install_readwrite_bank(0x1000, 0x1fff, "bank2");
162		membank("bank2")->set_base(m_ram->pointer() + 0x1000);
	213	//spc.install_readwrite_bank(0x1000, 0x1fff, "bank2");
	214	//membank("bank2")->set_base(m_ram->pointer() + 0x1000);
	215	membank("bank1")->set_entry(0); // ram
163	216
164	217	if (m_mz700_mode)
165	218	{
166	219	/* ram from 0xc000 to 0xcfff */
167		spc.install_readwrite_bank(0xc000, 0xcfff, "bank6");
168		membank("bank6")->set_base(m_ram->pointer() + 0xc000);
	220	//spc.install_readwrite_bank(0xc000, 0xcfff, "bank6");
	221	//membank("bank6")->set_base(m_ram->pointer() + 0xc000);
	222	membank("bankc")->set_entry(0); // ram
169	223	}
170	224	else
171	225	{
172	226	/* ram from 0x8000 to 0xbfff */
173		spc.install_readwrite_bank(0x8000, 0xbfff, "bank4");
174		membank("bank4")->set_base(m_ram->pointer() + 0x8000);
	227	//spc.install_readwrite_bank(0x8000, 0xbfff, "bank4");
	228	//membank("bank4")->set_base(m_ram->pointer() + 0x8000);
	229	membank("banka")->set_entry(0); // ram
175	230	}
176	231
177	232	return 0xff;
r250104	r250105
180	235	WRITE8_MEMBER(mz_state::mz700_bank_1_w)
181	236	{
182	237	address_space &spc = m_maincpu->space(AS_PROGRAM);
	238	membank("bankd")->set_entry(0); // ram
183	239
184	240	if (m_mz700_mode)
185	241	{
186	242	/* switch in ram when not locked */
187	243	if (!m_mz700_ram_lock)
188	244	{
189		spc.install_readwrite_bank(0xd000, 0xffff, "bank7");
190		membank("bank7")->set_base(m_ram->pointer() + 0xd000);
	245	if (m_mz700)
	246	{
	247	//membank("bankd")->set_entry(0); // ram
	248	m_banke->set_bank(0); //ram
	249	}
	250	else
	251	{
	252	//spc.install_readwrite_bank(0xd000, 0xffff, "bank7");
	253	//spc.install_readwrite_bank(0xd000, 0xdfff, "bank7");
	254	//membank("bank7")->set_base(m_ram->pointer() + 0xd000);
	255	m_bankf->set_bank(0); //ram
	256	}
191	257	m_mz700_ram_vram = FALSE;
192	258	}
193	259	}
r250104	r250105
196	262	/* switch in ram when not locked */
197	263	if (!m_mz800_ram_lock)
198	264	{
199		spc.install_readwrite_bank(0xe000, 0xffff, "bank8");
200		membank("bank8")->set_base(m_ram->pointer() + 0xe000);
	265	//spc.install_readwrite_bank(0xe000, 0xffff, "bank8");
	266	//membank("bank8")->set_base(m_ram->pointer() + 0xe000);
	267	m_bankf->set_bank(0); //ram
201	268	m_mz800_ram_monitor = FALSE;
202	269	}
203	270	}
r250104	r250105
205	272
206	273	WRITE8_MEMBER(mz_state::mz700_bank_2_w)
207	274	{
208		address_space &spc = m_maincpu->space(AS_PROGRAM);
	275	//address_space &spc = m_maincpu->space(AS_PROGRAM);
209	276
210		spc.install_read_bank(0x0000, 0x0fff, "bank1");
211		spc.nop_write(0x0000, 0x0fff);
212		membank("bank1")->set_base(memregion("monitor")->base());
	277	//spc.install_read_bank(0x0000, 0x0fff, "bank1a");
	278	//spc.nop_write(0x0000, 0x0fff);
	279	//membank("bank1a")->set_base(memregion("monitor")->base());
	280	membank("bankr0")->set_entry(1); // rom
	281
213	282	}
214	283
215	284	WRITE8_MEMBER(mz_state::mz700_bank_3_w)
216	285	{
217		UINT8 *videoram = m_videoram;
218	286	address_space &spc = m_maincpu->space(AS_PROGRAM);
219	287
220	288	if (m_mz700_mode)
221	289	{
222	290	if (!m_mz700_ram_lock)
223	291	{
224		/* switch in videoram */
225		spc.install_readwrite_bank(0xd000, 0xd7ff, "bank7");
226		membank("bank7")->set_base(videoram);
	292	if (m_mz700)
	293	membank("bankd")->set_entry(1);
	294	else
	295	{
	296	/* switch in videoram */
	297	//spc.install_readwrite_bank(0xd000, 0xd7ff, "bank7");
	298	//membank("bank7")->set_base(m_videoram);
227	299
228		/* switch in colorram */
229		spc.install_readwrite_bank(0xd800, 0xdfff, "bank9");
230		membank("bank9")->set_base(m_colorram);
231
	300	/* switch in colorram */
	301	//spc.install_readwrite_bank(0xd800, 0xdfff, "bank9");
	302	//membank("bank9")->set_base(m_colorram);
	303	membank("bankd")->set_entry(1);
	304	}
232	305	m_mz700_ram_vram = TRUE;
233	306
234	307	/* switch in memory mapped i/o devices */
235	308	if (m_mz700)
236	309	{
237		spc.install_readwrite_handler(0xe000, 0xfff3, 0, 0x1ff0, read8_delegate(FUNC(i8255_device::read), (i8255_device*)m_ppi), write8_delegate(FUNC(i8255_device::write), (i8255_device*)m_ppi));
238		spc.install_readwrite_handler(0xe004, 0xfff7, 0, 0x1ff0, read8_delegate(FUNC(pit8253_device::read), (pit8253_device*)m_pit), write8_delegate(FUNC(pit8253_device::write), (pit8253_device*)m_pit));
239		spc.install_readwrite_handler(0xe008, 0xfff8, 0, 0x1ff0, read8_delegate(FUNC(mz_state::mz700_e008_r),this), write8_delegate(FUNC(mz_state::mz700_e008_w),this));
	310	m_banke->set_bank(1); //devices
240	311	}
241	312	else
242	313	{
243		spc.install_readwrite_handler(0xe000, 0xe003, read8_delegate(FUNC(i8255_device::read), (i8255_device*)m_ppi), write8_delegate(FUNC(i8255_device::write), (i8255_device*)m_ppi));
244		spc.install_readwrite_handler(0xe004, 0xe007, read8_delegate(FUNC(pit8253_device::read), (pit8253_device*)m_pit), write8_delegate(FUNC(pit8253_device::write), (pit8253_device*)m_pit));
245		spc.install_readwrite_handler(0xe008, 0xe008, read8_delegate(FUNC(mz_state::mz700_e008_r),this), write8_delegate(FUNC(mz_state::mz700_e008_w),this));
	314	m_bankf->set_bank(1); //devices
246	315	}
247	316	}
248	317	}
r250104	r250105
251	320	if (!m_mz800_ram_lock)
252	321	{
253	322	/* switch in mz800 monitor rom if not locked */
254		spc.install_read_bank(0xe000, 0xffff, "bank8");
255		spc.nop_write(0xe000, 0xffff);
256		membank("bank8")->set_base(memregion("monitor")->base() + 0x2000);
	323	//spc.install_read_bank(0xe000, 0xffff, "bank8");
	324	//spc.nop_write(0xe000, 0xffff);
	325	//membank("bank8")->set_base(memregion("monitor")->base() + 0x2000);
	326	m_bankf->set_bank(1); // devices + rom
257	327	m_mz800_ram_monitor = TRUE;
258	328	}
259	329	}
r250104	r250105
261	331
262	332	WRITE8_MEMBER(mz_state::mz700_bank_4_w)
263	333	{
264		UINT8 *videoram = m_videoram;
265	334	address_space &spc = m_maincpu->space(AS_PROGRAM);
266	335
267	336	if (m_mz700_mode)
r250104	r250105
270	339	mz700_bank_2_w(space, 0, 0);    /* switch in monitor rom */
271	340	mz700_bank_3_w(space, 0, 0);    /* switch in videoram, colorram, and mmio */
272	341
273		/* rest is ram is always ram in mz700 mode */
274		spc.install_readwrite_bank(0x1000, 0xcfff, "bank2");
275		membank("bank2")->set_base(m_ram->pointer() + 0x1000);
	342	if (!m_mz700)
	343	{
	344	/* rest is ram is always ram in mz700 mode */
	345	//spc.install_readwrite_bank(0x1000, 0xcfff, "bank2");
	346	//membank("bank2")->set_base(m_ram->pointer() + 0x1000);
	347	membank("bankr0")->set_entry(1); // rom
	348	membank("bank1")->set_entry(0); // ram
	349	membank("bankc")->set_entry(0); // ram
	350	}
276	351	}
277	352	else
278	353	{
279	354	/* monitor rom and cgrom */
280		spc.install_read_bank(0x0000, 0x1fff, "bank1");
281		spc.nop_write(0x0000, 0x1fff);
282		membank("bank1")->set_base(memregion("monitor")->base());
	355	//spc.install_read_bank(0x0000, 0x1fff, "bank1a");
	356	//spc.nop_write(0x0000, 0x1fff);
	357	//membank("bank1a")->set_base(memregion("monitor")->base());
	358	membank("bankr0")->set_entry(1); // rom
	359	membank("bank1")->set_entry(1); // rom
283	360
284	361	/* ram from 0x2000 to 0x7fff */
285		spc.install_readwrite_bank(0x2000, 0x7fff, "bank3");
286		membank("bank3")->set_base(m_ram->pointer());
	362	//spc.install_readwrite_bank(0x2000, 0x7fff, "bank3");
	363	//membank("bank3")->set_base(m_ram->pointer());
287	364
288	365	if (m_hires_mode)
289	366	{
290	367	/* vram from 0x8000 to 0xbfff */
291		spc.install_readwrite_bank(0x8000, 0xbfff, "bank4");
292		membank("bank4")->set_base(videoram);
	368	//spc.install_readwrite_bank(0x8000, 0xbfff, "bank4");
	369	//membank("bank4")->set_base(m_videoram);
	370	membank("banka")->set_entry(1); // vram
293	371	}
294	372	else
295	373	{
296	374	/* vram from 0x8000 to 0x9fff */
297		spc.install_readwrite_bank(0x8000, 0x9fff, "bank4");
298		membank("bank4")->set_base(videoram);
	375	//spc.install_readwrite_bank(0x8000, 0x9fff, "bank4");
	376	//membank("bank4")->set_base(m_videoram);
	377	membank("banka")->set_entry(1); // vram
299	378
300	379	/* ram from 0xa000 to 0xbfff */
301		spc.install_readwrite_bank(0xa000, 0xbfff, "bank5");
302		membank("bank5")->set_base(m_ram->pointer() + 0xa000);
	380	//spc.install_readwrite_bank(0xa000, 0xbfff, "bank5");
	381	//membank("bank5")->set_base(m_ram->pointer() + 0xa000);
303	382	}
304	383
305	384	/* ram from 0xc000 to 0xdfff */
306		spc.install_readwrite_bank(0xc000, 0xdfff, "bank6");
307		membank("bank6")->set_base(m_ram->pointer() + 0xc000);
	385	//spc.install_readwrite_bank(0xc000, 0xdfff, "bank6");
	386	//membank("bank6")->set_base(m_ram->pointer() + 0xc000);
	387	membank("bankd")->set_entry(0); // ram
308	388
309	389	/* mz800 monitor rom from 0xe000 to 0xffff */
310		spc.install_read_bank(0xe000, 0xffff, "bank8");
311		spc.nop_write(0xe000, 0xffff);
312		membank("bank8")->set_base(memregion("monitor")->base() + 0x2000);
	390	//spc.install_read_bank(0xe000, 0xffff, "bank8");
	391	//spc.nop_write(0xe000, 0xffff);
	392	//membank("bank8")->set_base(memregion("monitor")->base() + 0x2000);
	393	m_bankf->set_bank(1); // devices + rom
313	394	m_mz800_ram_monitor = TRUE;
314	395
315	396	m_mz800_ram_lock = FALSE; /* reset lock? */
r250104	r250105
324	405	{
325	406	/* prevent access from 0xd000 to 0xffff */
326	407	m_mz700_ram_lock = TRUE;
327		spc.nop_readwrite(0xd000, 0xffff);
	408	if (m_mz700)
	409	m_banke->set_bank(2);
	410	else
	411	//spc.nop_readwrite(0xd000, 0xdfff);
	412	//spc.nop_readwrite(0xd000, 0xffff);
	413	m_bankf->set_bank(2);
328	414	}
329	415	else
330	416	{
331	417	/* prevent access from 0xe000 to 0xffff */
332	418	m_mz800_ram_lock = TRUE;
333		spc.nop_readwrite(0xe000, 0xffff);
	419	//spc.nop_readwrite(0xe000, 0xffff);
	420	m_bankf->set_bank(2);
334	421	}
335	422	}
336	423
r250104	r250105
435	522	LOG(2,"mz700_pio_port_a_w",("%02X\n", data),machine());
436	523
437	524	/* the ls145 is connected to PA0-PA3 */
438		dynamic_cast<ttl74145_device *>(device)->write(data & 0x07);
	525	dynamic_cast<ttl74145_device *>(device)->write(data & 0x0f);
439	526
440	527	/* ne556 reset is connected to PA7 */
441	528	timer->enable(BIT(data, 7));

trunk/src/mame/video/mz700.c

r250104	r250105
15	15	#include "includes/mz700.h"
16	16
17	17
18		#ifndef VERBOSE
19		#define VERBOSE 1
20		#endif
21
22		#define LOG(N,M,A)  \
23		do { \
24		if(VERBOSE>=N) \
25		{ \
26		if( M ) \
27		logerror("%11.6f: %-24s",machine.time().as_double(),(char*)M ); \
28		logerror A; \
29		} \
30		} while (0)
31
32
33		PALETTE_INIT_MEMBER(mz_state, mz)
34		{
35		int i;
36
37		for (i = 0; i < 8; i++)
38		m_palette->set_indirect_color(i, rgb_t((i & 2) ? 0xff : 0x00, (i & 4) ? 0xff : 0x00, (i & 1) ? 0xff : 0x00));
39
40		for (i = 0; i < 256; i++)
41		{
42		m_palette->set_pen_indirect(i*2, i & 7);
43		m_palette->set_pen_indirect(i*2+1, (i >> 4) & 7);
44		}
45		}
46
47
48	18	UINT32 mz_state::screen_update_mz700(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
49	19	{
50		UINT8 *videoram = m_videoram;
51		int offs;
	20	UINT8 y,ra,gfx,col,bg=0,fg=0,oldcol=0x7e;
	21	UINT16 sy=0,ma=0,x,chr;
52	22
53		bitmap.fill(m_palette->black_pen(), cliprect);
54
55		for(offs = 0; offs < 40*25; offs++)
	23	for (y = 0; y < 25; y++)
56	24	{
57		int sx, sy, code, color;
	25	for (ra = 0; ra < 8; ra++)
	26	{
	27	UINT16 *p = &bitmap.pix16(sy++);
58	28
59		sy = (offs / 40) * 8;
60		sx = (offs % 40) * 8;
	29	for (x = ma; x < ma + 40; x++)
	30	{
	31	col = m_colorram[x];
	32	if (col != oldcol)
	33	{
	34	oldcol = col;
	35	col = BITSWAP8(col, 7, 3, 4, 6, 5, 0, 2, 1); // turn BRG into RGB
	36	bg = col & 7;
	37	fg = (col >> 3) & 7;
	38	}
	39	chr = m_videoram[x] | (BIT(col, 7)<<8);
	40	gfx = m_p_chargen[(chr<<3) | ra ];
61	41
62		color = m_colorram[offs];
63		code = videoram[offs] | (color & 0x80) << 1;
64
65		m_gfxdecode->gfx(0)->opaque(bitmap,cliprect, code, color, 0, 0, sx, sy);
	42	/* Display a scanline of a character */
	43	*p++ = BIT(gfx, 0) ? fg : bg;
	44	*p++ = BIT(gfx, 1) ? fg : bg;
	45	*p++ = BIT(gfx, 2) ? fg : bg;
	46	*p++ = BIT(gfx, 3) ? fg : bg;
	47	*p++ = BIT(gfx, 4) ? fg : bg;
	48	*p++ = BIT(gfx, 5) ? fg : bg;
	49	*p++ = BIT(gfx, 6) ? fg : bg;
	50	*p++ = BIT(gfx, 7) ? fg : bg;
	51	}
	52	}
	53	ma+=40;
66	54	}
67
68	55	return 0;
69	56	}
70	57
71	58
72	59	/***************************************************************************
73	60	MZ-800
	61	Not working.
74	62	***************************************************************************/
75	63
76		VIDEO_START_MEMBER(mz_state,mz800)
77		{
78		m_gfxdecode->gfx(0)->set_source(m_cgram);
79		}
80
81	64	UINT32 mz_state::screen_update_mz800(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
82	65	{
83		UINT8 *videoram = m_videoram;
84
85		bitmap.fill(m_palette->black_pen(), cliprect);
86
87	66	if (m_mz700_mode)
88	67	return screen_update_mz700(screen, bitmap, cliprect);
89	68	else
r250104	r250105
94	73	else
95	74	{
96	75	int x, y;
97		UINT8 *start_addr = videoram;
98	76
99	77	for (x = 0; x < 40; x++)
100	78	{
101	79	for (y = 0; y < 200; y++)
102	80	{
103		bitmap.pix16(y, x * 8 + 0) = BIT(start_addr[x * 8 + y], 0);
104		bitmap.pix16(y, x * 8 + 1) = BIT(start_addr[x * 8 + y], 1);
105		bitmap.pix16(y, x * 8 + 2) = BIT(start_addr[x * 8 + y], 2);
106		bitmap.pix16(y, x * 8 + 3) = BIT(start_addr[x * 8 + y], 3);
107		bitmap.pix16(y, x * 8 + 4) = BIT(start_addr[x * 8 + y], 4);
108		bitmap.pix16(y, x * 8 + 5) = BIT(start_addr[x * 8 + y], 5);
109		bitmap.pix16(y, x * 8 + 6) = BIT(start_addr[x * 8 + y], 6);
110		bitmap.pix16(y, x * 8 + 7) = BIT(start_addr[x * 8 + y], 7);
	81	bitmap.pix16(y, x * 8 + 0) = BIT(m_videoram[x * 8 + y], 0) ? 7 : 0;
	82	bitmap.pix16(y, x * 8 + 1) = BIT(m_videoram[x * 8 + y], 1) ? 7 : 0;
	83	bitmap.pix16(y, x * 8 + 2) = BIT(m_videoram[x * 8 + y], 2) ? 7 : 0;
	84	bitmap.pix16(y, x * 8 + 3) = BIT(m_videoram[x * 8 + y], 3) ? 7 : 0;
	85	bitmap.pix16(y, x * 8 + 4) = BIT(m_videoram[x * 8 + y], 4) ? 7 : 0;
	86	bitmap.pix16(y, x * 8 + 5) = BIT(m_videoram[x * 8 + y], 5) ? 7 : 0;
	87	bitmap.pix16(y, x * 8 + 6) = BIT(m_videoram[x * 8 + y], 6) ? 7 : 0;
	88	bitmap.pix16(y, x * 8 + 7) = BIT(m_videoram[x * 8 + y], 7) ? 7 : 0;
111	89	}
112	90	}
113	91	}
r250104	r250105
123	101	WRITE8_MEMBER(mz_state::mz800_cgram_w)
124	102	{
125	103	m_cgram[offset] = data;
126
127		m_gfxdecode->gfx(0)->mark_dirty(offset/8);
128	104	}

https://github.com/mamedev/mame/commit/a2cc039c0578aa49fc78b7176dfe974e39f92d7a

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