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r41454 Thursday 29th October, 2015 at 17:10:14 UTC by David Haywood
call it harmony/melody, that more accurately represents what we're emulating, dpc+ seems to be a software implementation on the ARM of the Harmony (nw)

[hash]	a2600.xml
[scripts/src]	bus.lua
[src/devices/bus/vcs]	dpcplus.c dpcplus.h harmony_melody.c* harmony_melody.h* vcs_slot.c vcs_slot.h
[src/mame/drivers]	a2600.c

trunk/hash/a2600.xml

r249965	r249966
17955	17955	</part>
17956	17956	</software>
17957	17957
17958		<!-- This was released by the author, also available via Atariage, are both versions the same? needs DPC+ emulation -->
	17958	<!-- This was released by the author, also available via Atariage, are both versions the same? needs HARMONY/MELODY emulation -->
17959	17959	<software name="stayfr2" supported="no">
17960	17960	<description>Stay Frosty 2 (NTSC)</description>
17961	17961	<year>2013</year>
17962	17962	<publisher>Spiceware</publisher>
17963	17963	<sharedfeat name="compatibility" value="NTSC" />
17964	17964	<part name="cart" interface="a2600_cart">
17965		<feature name="slot" value="a26_dpcplus" />
	17965	<feature name="slot" value="a26_harmony" />
17966	17966	<dataarea name="rom" size="0x8000">
17967	17967	<rom name="SF2_20131217_RC8_NTSC.bin" size="0x8000" crc="4eb739ab" sha1="5eceaf8e90bd9a002f4935f082df7b25716dceb0" offset="0" />
17968	17968	</dataarea>
r249965	r249966
17975	17975	<publisher>Spiceware</publisher>
17976	17976	<sharedfeat name="compatibility" value="NTSC" />
17977	17977	<part name="cart" interface="a2600_cart">
17978		<feature name="slot" value="a26_dpcplus" />
	17978	<feature name="slot" value="a26_harmony" />
17979	17979	<dataarea name="rom" size="0x8000">
17980	17980	<rom name="SF2_demo_NTSC.bin" size="0x8000" crc="fd850bd6" sha1="bd8166da7777c66e6bb3ab0c77563193d8289f5f" offset="0" />
17981	17981	</dataarea>
r249965	r249966
17989	17989	<publisher>Spiceware</publisher>
17990	17990	<sharedfeat name="compatibility" value="PAL" />
17991	17991	<part name="cart" interface="a2600_cart">
17992		<feature name="slot" value="a26_dpcplus" />
	17992	<feature name="slot" value="a26_harmony" />
17993	17993	<dataarea name="rom" size="0x8000">
17994	17994	<rom name="SF2_20131217_RC8_PAL.bin" size="0x8000" crc="7b495dc3" sha1="1625ef74b0a48c2968fad832ab8e2edc8187a53f" offset="0" />
17995	17995	</dataarea>
r249965	r249966
18002	18002	<publisher>Spiceware</publisher>
18003	18003	<sharedfeat name="compatibility" value="PAL" />
18004	18004	<part name="cart" interface="a2600_cart">
18005		<feature name="slot" value="a26_dpcplus" />
	18005	<feature name="slot" value="a26_harmony" />
18006	18006	<dataarea name="rom" size="0x8000">
18007	18007	<rom name="SF2_demo_PAL.bin" size="0x8000" crc="b47582f3" sha1="73625429e73f1b354e0cbe6a360d79590032de2b" offset="0" />
18008	18008	</dataarea>
r249965	r249966
18015	18015	<publisher>Spiceware</publisher>
18016	18016	<sharedfeat name="compatibility" value="NTSC" />
18017	18017	<part name="cart" interface="a2600_cart">
18018		<feature name="slot" value="a26_dpcplus" />
	18018	<feature name="slot" value="a26_harmony" />
18019	18019	<dataarea name="rom" size="0x8000">
18020	18020	<rom name="spacerocks20121129_NTSC.bin" size="0x8000" crc="c5d8eb83" sha1="bf3af5c76bb4dded5cb9c9b232c369250ad20ac4" offset="0" />
18021	18021	</dataarea>
r249965	r249966
18028	18028	<publisher>Spiceware</publisher>
18029	18029	<sharedfeat name="compatibility" value="PAL" />
18030	18030	<part name="cart" interface="a2600_cart">
18031		<feature name="slot" value="a26_dpcplus" />
	18031	<feature name="slot" value="a26_harmony" />
18032	18032	<dataarea name="rom" size="0x8000">
18033	18033	<rom name="spacerocks20121129_PAL.bin" size="0x8000" crc="133cb923" sha1="0511a35ee435227fbb5665e8488590eb993256f7" offset="0" />
18034	18034	</dataarea>
18035	18035	</part>
18036		</software>
	18036	</software>
18037	18037
	18038	<software name="frantic" supported="no">
	18039	<description>Frantic (20140305, NTSC)</description>
	18040	<year>2014</year>
	18041	<publisher>Spiceware</publisher>
	18042	<sharedfeat name="compatibility" value="NTSC" />
	18043	<part name="cart" interface="a2600_cart">
	18044	<feature name="slot" value="a26_harmony" />
	18045	<dataarea name="rom" size="0x8000">
	18046	<rom name="frantic20140305.bin" size="0x8000" crc="04d0f558" sha1="ee2a004a50861c5fdfbdabfa5ed4bf825333ec43" offset="0" />
	18047	</dataarea>
	18048	</part>
	18049	</software>
	18050
	18051	<software name="harmbios" supported="no">  <!-- I think these are the bios roms if you're using it as a multi-game cart? -->
	18052	<description>Harmony Bios Updater</description>
	18053	<year>2014</year>
	18054	<publisher>Harmony</publisher>
	18055	<sharedfeat name="compatibility" value="NTSC" />
	18056	<part name="cart" interface="a2600_cart">
	18057	<feature name="slot" value="a26_harmony" />
	18058	<dataarea name="rom" size="0x8000">
	18059	<rom name="bios_updater_NTSC.cu" size="0x8000" crc="03153eb2" sha1="cd9ee1d820737b3887ebe5fc6fe96a2a043ab009" offset="0" />
	18060	</dataarea>
	18061	<dataarea name="bios" size="0x21400">
	18062	<rom name="hbios_106_NTSC_official_beta.bin" size="0x21400" crc="1e1d237b" sha1="8fd74e0119bce43a89bcc4998b750bc6884971da" offset="0" />
	18063	<rom name="hbios_106_NTSC_beta_2.bin"        size="0x21400" crc="807b86bd" sha1="633960295c30e7430b3ce58f6244495f4b708e9d" offset="0" />
	18064	<rom name="hbios_106_NTSC.bin"               size="0x21400" crc="48664301" sha1="aaa5e839f307734306c2a9ccbe38482579c70391" offset="0" />
	18065
	18066	<rom name="hbios_105_NTSC.bin"  size="0x19400" crc="c0b8aae9" sha1="68b10153695da505756eb7dc7cc4a7e93fe68860" offset="0" />
	18067	<rom name="hbios_105_PAL50.bin" size="0x19400" crc="fb942c80" sha1="81bba9d9c245d23cc4b9503180ebe2d67bf1e117" offset="0" />
	18068	<rom name="hbios_105_PAL60.bin" size="0x19400" crc="b59ebe6d" sha1="873830286c66935fd23e3ea7c192e6573e056cbd" offset="0" />
	18069
	18070	<rom name="eeloader_104e_NTSC.bin"  size="0x36f8" crc="ad04a8d9" sha1="c83d724299875cd5ea8d6be05db12d688ce8eff1" offset="0" />
	18071	<rom name="eeloader_104e_PAL50.bin" size="0x36f8" crc="4868ba51" sha1="e6a65523824ecf4f2a5145e2c5118cfb4bee059d" offset="0" />
	18072	<rom name="eeloader_104e_PAL60.bin" size="0x36f8" crc="58845532" sha1="255b5c9f4f2f7322c20d2619126cd150a1b8f71c" offset="0" />
	18073
	18074	</dataarea>
	18075
	18076	</part>
	18077	</software>
	18078
18038	18079	</softwarelist>
18039	18080
18040	18081

trunk/scripts/src/bus.lua

r249965	r249966
1161	1161	MAME_DIR .. "src/devices/bus/vcs/compumat.h",
1162	1162	MAME_DIR .. "src/devices/bus/vcs/dpc.c",
1163	1163	MAME_DIR .. "src/devices/bus/vcs/dpc.h",
1164		MAME_DIR .. "src/devices/bus/vcs/dpcplus.c",
1165		MAME_DIR .. "src/devices/bus/vcs/dpcplus.h",
	1164	MAME_DIR .. "src/devices/bus/vcs/harmony_melody.c",
	1165	MAME_DIR .. "src/devices/bus/vcs/harmony_melody.h",
1166	1166	MAME_DIR .. "src/devices/bus/vcs/scharger.c",
1167	1167	MAME_DIR .. "src/devices/bus/vcs/scharger.h",
1168	1168	}

trunk/src/devices/bus/vcs/dpcplus.c

r249965	r249966
1		// license:BSD-3-Clause
2		// copyright-holders:David Haywood
3		/***************************************************************************
4
5		Atari 2600 cart with DPC+
6
7		the DPC+ adds an ARM CPU, including video improvements plus an extra synthesizer.
8
9		Some info on the DPC+ hardware can be found on Darrell Spice Jr's guides:
10		http://atariage.com/forums/blog/148/entry-11811-dpcarm-part-6-dpc-cartridge-layout/
11		http://atariage.com/forums/blog/148/entry-11883-dpcarm-part-7-6507arm-exchange-of-information/
12		http://atariage.com/forums/blog/148/entry-11903-dpcarm-part-8-multiple-functions/
13		http://atariage.com/forums/blog/148/entry-11935-dpcarm-part-9-functional-menu/
14		http://atariage.com/forums/blog/148/entry-11964-dpcarm-part-10-score-timer-display/
15		http://atariage.com/forums/blog/148/entry-11988-dpcarm-part-12-gamepad-support/
16
17		map:
18		Bankswitching uses addresses $FFF6-$FFFB
19
20		* ARM RAM mapped at $40000000 in this area
21		$0000-$0BFF: DPC+ driver (not accessible by 2600 itself) (copied to $40000000 - $40000bff on startup by ARM)
22		$0C00-$1BFF: Bank 0 (each bank can map to 0x1000 - 0x1fff in 6507 space, like other carts)
23		$1C00-$2BFF: Bank 1
24		$2C00-$3BFF: Bank 2
25		$3C00-$4BFF: Bank 3
26		$4C00-$5BFF: Bank 4
27		$5C00-$6BFF: Bank 5 (default bank is bank 5)
28		$6C00-$7BFF: Display Data (indirect access) (copied to $40000C00 - $40001bff on startup by ARM)
29		$7C00-$7FFF: Synth Frequency Data (not accessible by 2600 itself) (copied to $40001C00 - $40001fff on startup by ARM)
30
31		***************************************************************************/
32
33
34		#include "emu.h"
35		#include "dpcplus.h"
36
37
38
39
40
41		// cart device
42
43		const device_type A26_ROM_DPCPLUS = &device_creator<a26_rom_dpcplus_device>;
44
45
46		a26_rom_dpcplus_device::a26_rom_dpcplus_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
47		: a26_rom_f8_device(mconfig, A26_ROM_DPCPLUS, "Atari 2600 ROM Cart DPC+", tag, owner, clock, "a2600_dpcplus", __FILE__)
48		{
49		}
50
51		//-------------------------------------------------
52		//  mapper specific start/reset
53		//-------------------------------------------------
54
55		void a26_rom_dpcplus_device::device_start()
56		{
57		save_item(NAME(m_base_bank));
58		}
59
60		void a26_rom_dpcplus_device::device_reset()
61		{
62		m_base_bank = 5;
63		}
64
65
66		READ8_MEMBER(a26_rom_dpcplus_device::read8_r)
67		{
68		return m_rom[offset + (m_base_bank * 0x1000)];
69		}
70
71
72		READ32_MEMBER(a26_rom_dpcplus_device::armrom_r)
73		{
74		UINT32 ret = (m_rom[offset * 4 + 3] << 24) |
75		(m_rom[offset * 4 + 2] << 16) |
76		(m_rom[offset * 4 + 1] << 8) |
77		(m_rom[offset * 4 + 0] << 0);
78		return ret;
79		}
80
81		WRITE32_MEMBER(a26_rom_dpcplus_device::armrom_w)
82		{
83
84		}
85
86		READ32_MEMBER(a26_rom_dpcplus_device::arm_E01FC088_r)
87		{
88		return 0xffffffff;
89		}
90
91		static ADDRESS_MAP_START( dpcplus_arm7_map, AS_PROGRAM, 32, a26_rom_dpcplus_device )
92		// todo: implement all this correctly
93		AM_RANGE(0x00000000, 0x00007fff) AM_READWRITE(armrom_r,armrom_w) // flash, 32k
94		AM_RANGE(0x40000000, 0x40001fff) AM_RAM // sram, 8k
95
96		AM_RANGE(0xE01FC088, 0xE01FC08b) AM_READ(arm_E01FC088_r)
97		ADDRESS_MAP_END
98
99		static MACHINE_CONFIG_FRAGMENT( a26_dpcplus )
100		MCFG_CPU_ADD("arm", ARM7, 70000000)
101		MCFG_CPU_PROGRAM_MAP(dpcplus_arm7_map)
102		MACHINE_CONFIG_END
103
104		machine_config_constructor a26_rom_dpcplus_device::device_mconfig_additions() const
105		{
106		return MACHINE_CONFIG_NAME( a26_dpcplus );
107		}
108
109		void a26_rom_dpcplus_device::check_bankswitch(offs_t offset)
110		{
111		switch (offset)
112		{
113		case 0x0FF6: m_base_bank = 0; break;
114		case 0x0FF7: m_base_bank = 1; break;
115		case 0x0FF8: m_base_bank = 2; break;
116		case 0x0FF9: m_base_bank = 3; break;
117		case 0x0FFa: m_base_bank = 4; break;
118		case 0x0FFb: m_base_bank = 5; break;
119		default: break;
120		}
121		}
122
123		READ8_MEMBER(a26_rom_dpcplus_device::read_rom)
124		{
125		UINT8 retvalue = read8_r(space, offset + 0xc00); // banks start at 0xc00
126
127		check_bankswitch(offset);
128
129		return retvalue;
130		}
131
132		WRITE8_MEMBER(a26_rom_dpcplus_device::write_bank)
133		{
134		check_bankswitch(offset);
135		//   a26_rom_f8_device::write_bank(space, offset, data);
136		}

trunk/src/devices/bus/vcs/dpcplus.h

r249965	r249966
1		// license:BSD-3-Clause
2		// copyright-holders:David Haywood
3		#ifndef __VCS_DPCPLUS_H
4		#define __VCS_DPCPLUS_H
5
6		#include "rom.h"
7		#include "cpu/arm7/arm7.h"
8
9
10		// ======================> a26_rom_dpcplus_device
11
12		class a26_rom_dpcplus_device : public a26_rom_f8_device
13		{
14		public:
15		// construction/destruction
16		a26_rom_dpcplus_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
17
18		// device-level overrides
19		virtual void device_start();
20		virtual machine_config_constructor device_mconfig_additions() const;
21		virtual void device_reset();
22
23		// reading and writing
24		virtual DECLARE_READ8_MEMBER(read_rom);
25		virtual DECLARE_WRITE8_MEMBER(write_bank);
26
27		DECLARE_READ32_MEMBER(armrom_r);
28		DECLARE_WRITE32_MEMBER(armrom_w);
29
30		DECLARE_READ8_MEMBER(read8_r);
31
32		DECLARE_READ32_MEMBER(arm_E01FC088_r);
33
34		void check_bankswitch(offs_t offset);
35
36		protected:
37		};
38
39
40		// device type definition
41		extern const device_type A26_ROM_DPCPLUS;
42
43		#endif

trunk/src/devices/bus/vcs/harmony_melody.c

r0	r249966
	1	// license:BSD-3-Clause
	2	// copyright-holders:David Haywood
	3	/***************************************************************************
	4
	5	Harmony / Melody cart for the A2600
	6
	7	The Harmony cart is a 'modern' A2600 cartridge, used for homebrew etc. It has
	8	an SD slot and can be connected to a PC, roms can be transfered to it with
	9	software on the PC side.  It uses an ARM7TDMI-S LPC2103 @ 70 Mhz to emulate
	10	the mapper behavior of other cartridges.  It has an SD card slot for storing
	11	game data.
	12
	13	The Melody version of the cartridge has been used for several recent A2600
	14	commercial releases as well as some reproductions due to it's ability to be
	15	programmed as any other cartridge type.  This lacks the SD slot?
	16
	17	The 'DPC+' games by SpiceWare run on a Harmony / Melody cart, DPC+ seems to
	18	be a virtual 'software mapper' programmed on the ARM rather than a real mapper.
	19
	20
	21	There is also a 'Harmony Encore' cartridge which adds support for some of the
	22	games the original couldn't handle due to them having larger ROMs and more
	23	complex banking schemes (Stella's Stocking etc.)
	24
	25	some Harmony cart details can be found at
	26	http://atariage.com/forums/topic/156500-latest-harmony-cart-software/
	27
	28
	29	DPC+ notes
	30	----------
	31
	32	Some info on the Harmony / Melody when configured as DPC+ hardware can be found on Darrell Spice Jr's guides:
	33	http://atariage.com/forums/blog/148/entry-11811-dpcarm-part-6-dpc-cartridge-layout/
	34	http://atariage.com/forums/blog/148/entry-11883-dpcarm-part-7-6507arm-exchange-of-information/
	35	http://atariage.com/forums/blog/148/entry-11903-dpcarm-part-8-multiple-functions/
	36	http://atariage.com/forums/blog/148/entry-11935-dpcarm-part-9-functional-menu/
	37	http://atariage.com/forums/blog/148/entry-11964-dpcarm-part-10-score-timer-display/
	38	http://atariage.com/forums/blog/148/entry-11988-dpcarm-part-12-gamepad-support/
	39
	40	map:
	41	Bankswitching uses addresses $FFF6-$FFFB
	42
	43	* ARM RAM mapped at $40000000 in this area
	44	$0000-$0BFF: HARMONY/MELODY driver (not accessible by 2600 itself) (copied to $40000000 - $40000bff on startup by ARM)
	45	$0C00-$1BFF: Bank 0 (each bank can map to 0x1000 - 0x1fff in 6507 space, like other carts)
	46	$1C00-$2BFF: Bank 1
	47	$2C00-$3BFF: Bank 2
	48	$3C00-$4BFF: Bank 3
	49	$4C00-$5BFF: Bank 4
	50	$5C00-$6BFF: Bank 5 (default bank is bank 5)
	51	$6C00-$7BFF: Display Data (indirect access) (copied to $40000C00 - $40001bff on startup by ARM)
	52	$7C00-$7FFF: Synth Frequency Data (not accessible by 2600 itself) (copied to $40001C00 - $40001fff on startup by ARM)
	53
	54	***************************************************************************/
	55
	56
	57	#include "emu.h"
	58	#include "harmony_melody.h"
	59
	60
	61
	62
	63
	64	// cart device
	65
	66	const device_type A26_ROM_HARMONY = &device_creator<a26_rom_harmony_device>;
	67
	68
	69	a26_rom_harmony_device::a26_rom_harmony_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	70	: a26_rom_f8_device(mconfig, A26_ROM_HARMONY, "Atari 2600 ROM Cart HARMONY/MELODY", tag, owner, clock, "a2600_harmony", __FILE__)
	71	{
	72	}
	73
	74	//-------------------------------------------------
	75	//  mapper specific start/reset
	76	//-------------------------------------------------
	77
	78	void a26_rom_harmony_device::device_start()
	79	{
	80	save_item(NAME(m_base_bank));
	81	}
	82
	83	void a26_rom_harmony_device::device_reset()
	84	{
	85	m_base_bank = 5;
	86	}
	87
	88
	89	READ8_MEMBER(a26_rom_harmony_device::read8_r)
	90	{
	91	return m_rom[offset + (m_base_bank * 0x1000)];
	92	}
	93
	94
	95	READ32_MEMBER(a26_rom_harmony_device::armrom_r)
	96	{
	97	UINT32 ret = (m_rom[offset * 4 + 3] << 24) |
	98	(m_rom[offset * 4 + 2] << 16) |
	99	(m_rom[offset * 4 + 1] << 8) |
	100	(m_rom[offset * 4 + 0] << 0);
	101	return ret;
	102	}
	103
	104	WRITE32_MEMBER(a26_rom_harmony_device::armrom_w)
	105	{
	106
	107	}
	108
	109	READ32_MEMBER(a26_rom_harmony_device::arm_E01FC088_r)
	110	{
	111	return 0xffffffff;
	112	}
	113
	114	static ADDRESS_MAP_START( harmony_arm7_map, AS_PROGRAM, 32, a26_rom_harmony_device )
	115	// todo: implement all this correctly
	116	AM_RANGE(0x00000000, 0x00007fff) AM_READWRITE(armrom_r,armrom_w) // flash, 32k
	117	AM_RANGE(0x40000000, 0x40001fff) AM_RAM // sram, 8k
	118
	119	AM_RANGE(0xE01FC088, 0xE01FC08b) AM_READ(arm_E01FC088_r)
	120	ADDRESS_MAP_END
	121
	122	static MACHINE_CONFIG_FRAGMENT( a26_harmony )
	123	MCFG_CPU_ADD("arm", ARM7, 70000000)
	124	MCFG_CPU_PROGRAM_MAP(harmony_arm7_map)
	125	MACHINE_CONFIG_END
	126
	127	machine_config_constructor a26_rom_harmony_device::device_mconfig_additions() const
	128	{
	129	return MACHINE_CONFIG_NAME( a26_harmony );
	130	}
	131
	132	// actually if the ARM code is doing this and providing every opcode to the main CPU based
	133	// on bus activity then we shouldn't be doing this here.
	134	void a26_rom_harmony_device::check_bankswitch(offs_t offset)
	135	{
	136	switch (offset)
	137	{
	138	case 0x0FF6: m_base_bank = 0; break;
	139	case 0x0FF7: m_base_bank = 1; break;
	140	case 0x0FF8: m_base_bank = 2; break;
	141	case 0x0FF9: m_base_bank = 3; break;
	142	case 0x0FFa: m_base_bank = 4; break;
	143	case 0x0FFb: m_base_bank = 5; break;
	144	default: break;
	145	}
	146	}
	147
	148	READ8_MEMBER(a26_rom_harmony_device::read_rom)
	149	{
	150	UINT8 retvalue = read8_r(space, offset + 0xc00); // banks start at 0xc00
	151
	152	check_bankswitch(offset);
	153
	154	return retvalue;
	155	}
	156
	157	WRITE8_MEMBER(a26_rom_harmony_device::write_bank)
	158	{
	159	check_bankswitch(offset);
	160	//   a26_rom_f8_device::write_bank(space, offset, data);
	161	}

trunk/src/devices/bus/vcs/harmony_melody.h

r0	r249966
	1	// license:BSD-3-Clause
	2	// copyright-holders:David Haywood
	3	#ifndef __VCS_HARMONY_H
	4	#define __VCS_HARMONY_H
	5
	6	#include "rom.h"
	7	#include "cpu/arm7/arm7.h"
	8
	9
	10	// ======================> a26_rom_harmony_device
	11
	12	class a26_rom_harmony_device : public a26_rom_f8_device
	13	{
	14	public:
	15	// construction/destruction
	16	a26_rom_harmony_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	17
	18	// device-level overrides
	19	virtual void device_start();
	20	virtual machine_config_constructor device_mconfig_additions() const;
	21	virtual void device_reset();
	22
	23	// reading and writing
	24	virtual DECLARE_READ8_MEMBER(read_rom);
	25	virtual DECLARE_WRITE8_MEMBER(write_bank);
	26
	27	DECLARE_READ32_MEMBER(armrom_r);
	28	DECLARE_WRITE32_MEMBER(armrom_w);
	29
	30	DECLARE_READ8_MEMBER(read8_r);
	31
	32	DECLARE_READ32_MEMBER(arm_E01FC088_r);
	33
	34	void check_bankswitch(offs_t offset);
	35
	36	protected:
	37	};
	38
	39
	40	// device type definition
	41	extern const device_type A26_ROM_HARMONY;
	42
	43	#endif

trunk/src/devices/bus/vcs/vcs_slot.c

r249965	r249966
157	157	{ A26_8IN1, "a26_8in1" },
158	158	{ A26_32IN1, "a26_32in1" },
159	159	{ A26_X07, "a26_x07" },
160		{ A26_DPCPLUS, "a26_dpcplus" },
	160	{ A26_HARMONY, "a26_harmony" },
161	161	};
162	162
163	163	static int vcs_get_pcb_id(const char *slot)

trunk/src/devices/bus/vcs/vcs_slot.h

r249965	r249966
36	36	A26_SS,
37	37	A26_CM,
38	38	A26_X07,
39		A26_DPCPLUS,
	39	A26_HARMONY,
40	40	};
41	41
42	42

trunk/src/mame/drivers/a2600.c

r249965	r249966
18	18	#include "bus/vcs/vcs_slot.h"
19	19	#include "bus/vcs/rom.h"
20	20	#include "bus/vcs/dpc.h"
21		#include "bus/vcs/dpcplus.h"
	21	#include "bus/vcs/harmony_melody.h"
22	22	#include "bus/vcs/scharger.h"
23	23	#include "bus/vcs/compumat.h"
24	24	#include "bus/vcs_ctrl/ctrl.h"
r249965	r249966
391	391	m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0x1000, 0x1fff, read8_delegate(FUNC(vcs_cart_slot_device::read_rom),(vcs_cart_slot_device*)m_cart), write8_delegate(FUNC(vcs_cart_slot_device::write_bank),(vcs_cart_slot_device*)m_cart));
392	392	m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0x0000, 0x0fff, read8_delegate(FUNC(a2600_state::cart_over_all_r), this), write8_delegate(FUNC(a2600_state::cart_over_all_w), this));
393	393	break;
394		case A26_DPCPLUS:
	394	case A26_HARMONY:
395	395	m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0x1000, 0x1fff, read8_delegate(FUNC(vcs_cart_slot_device::read_rom),(vcs_cart_slot_device*)m_cart), write8_delegate(FUNC(vcs_cart_slot_device::write_bank),(vcs_cart_slot_device*)m_cart));
396	396	break;
397	397	}
r249965	r249966
528	528	SLOT_INTERFACE_INTERNAL("a26_8in1",  A26_ROM_8IN1)
529	529	SLOT_INTERFACE_INTERNAL("a26_32in1", A26_ROM_32IN1)
530	530	SLOT_INTERFACE_INTERNAL("a26_x07",    A26_ROM_X07)
531		SLOT_INTERFACE_INTERNAL("a26_dpcplus",   A26_ROM_DPCPLUS)
	531	SLOT_INTERFACE_INTERNAL("a26_harmony",   A26_ROM_HARMONY)
532	532	SLOT_INTERFACE_END
533	533
534	534	static MACHINE_CONFIG_FRAGMENT(a2600_cartslot)

https://github.com/mamedev/mame/commit/7793b9af43d45f25e4cbf6c6d0d0c8df965e7dd6

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