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r41451 Thursday 29th October, 2015 at 14:40:04 UTC by Robbbert
Osborne Vixen: fixed screen (thanks to OG who added M1 support to the Z80). Various other fixes. Marked as Working [Robbbert]
[src/mame/drivers]vixen.c
[src/mame/includes]vixen.h

trunk/src/mame/drivers/vixen.c
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11// license:BSD-3-Clause
2// copyright-holders:Curt Coder
2// copyright-holders:Curt Coder, Robbbert
33/*
44
55Osborne 4 Vixen
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4747
4848    TODO:
4949
50    - video line buffer
51    - floppy
52    - keyboard
5350    - RS232 RI interrupt
5451    - PCB layouts
5552
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7673}
7774
7875
79//-------------------------------------------------
80//  ctl_w - command write
81//-------------------------------------------------
82
83WRITE8_MEMBER( vixen_state::ctl_w )
76READ8_MEMBER( vixen_state::opram_r )
8477{
85   logerror("CTL %u\n", data);
78   membank("bank3")->set_entry(0); // read videoram
79   return m_program->read_byte(offset);
80}
8681
87   membank("bank3")->set_entry(BIT(data, 0));
82READ8_MEMBER( vixen_state::oprom_r )
83{
84   membank("bank3")->set_entry(1); // read rom
85   return m_rom[offset];
8886}
8987
90
9188//-------------------------------------------------
9289//  status_r - status read
9390//-------------------------------------------------
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256253//  ADDRESS_MAP( vixen_mem )
257254//-------------------------------------------------
258255
256// when M1 is inactive: read and write of data
259257static ADDRESS_MAP_START( vixen_mem, AS_PROGRAM, 8, vixen_state )
260258   ADDRESS_MAP_UNMAP_HIGH
261   AM_RANGE(0x0000, 0xefff) AM_READ_BANK("bank1") AM_WRITE_BANK("bank2")
259   AM_RANGE(0x0000, 0xefff) AM_RAM
262260   AM_RANGE(0xf000, 0xffff) AM_READ_BANK("bank3") AM_WRITE_BANK("bank4") AM_SHARE("video_ram")
263261ADDRESS_MAP_END
264262
263// when M1 is active: read opcodes
264static ADDRESS_MAP_START( bios_mem, AS_DECRYPTED_OPCODES, 8, vixen_state )
265   ADDRESS_MAP_UNMAP_HIGH
266   AM_RANGE(0x0000, 0xefff) AM_READ(opram_r)
267   AM_RANGE(0xf000, 0xffff) AM_READ(oprom_r)
268ADDRESS_MAP_END
265269
270
266271//-------------------------------------------------
267272//  ADDRESS_MAP( vixen_io )
268273//-------------------------------------------------
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296301
297302INPUT_PORTS_START( vixen )
298303   PORT_START("KEY.0")
299   PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD )
300   PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD )
301   PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD )
302   PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD )
303   PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD )
304   PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD )
305   PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD )
306   PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD )
304   PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_ESC) PORT_CHAR(0x1B)
305   PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_TAB) PORT_CHAR(0x09)
306   PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_LCONTROL) PORT_CODE(KEYCODE_RCONTROL)
307   PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_CAPSLOCK) PORT_TOGGLE
308   PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_LSHIFT) PORT_CODE(KEYCODE_RSHIFT)
309   PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_ENTER) PORT_CHAR(0x0D)
310   PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_QUOTE) PORT_CHAR(0x27) PORT_CHAR(0x22)
311   PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_OPENBRACE) PORT_CHAR('[') PORT_CHAR(']')
307312
308313   PORT_START("KEY.1")
309   PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD )
310   PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD )
311   PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD )
312   PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD )
313   PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD )
314   PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD )
315   PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD )
316   PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD )
314   PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_1) PORT_CHAR('1') PORT_CHAR('!')
315   PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_2) PORT_CHAR('2') PORT_CHAR('@')
316   PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_3) PORT_CHAR('3') PORT_CHAR('#')
317   PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_4) PORT_CHAR('4') PORT_CHAR('$')
318   PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_5) PORT_CHAR('5') PORT_CHAR('%')
319   PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_6) PORT_CHAR('6') PORT_CHAR('^')
320   PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_7) PORT_CHAR('7') PORT_CHAR('&')
321   PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_8) PORT_CHAR('8') PORT_CHAR('*')
317322
318323   PORT_START("KEY.2")
319   PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD )
320   PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD )
321   PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD )
322   PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD )
323   PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD )
324   PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD )
325   PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD )
326   PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD )
324   PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_Q) PORT_CHAR('Q') PORT_CHAR('q')
325   PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_W) PORT_CHAR('W') PORT_CHAR('w')
326   PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_E) PORT_CHAR('E') PORT_CHAR('e')
327   PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_R) PORT_CHAR('R') PORT_CHAR('r')
328   PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_T) PORT_CHAR('T') PORT_CHAR('t')
329   PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_Y) PORT_CHAR('Y') PORT_CHAR('y')
330   PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_U) PORT_CHAR('U') PORT_CHAR('u')
331   PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_I) PORT_CHAR('I') PORT_CHAR('i')
327332
328333   PORT_START("KEY.3")
329   PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD )
330   PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD )
331   PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD )
332   PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD )
333   PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD )
334   PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD )
335   PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD )
336   PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD )
334   PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_A) PORT_CHAR('A') PORT_CHAR('a')
335   PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_S) PORT_CHAR('S') PORT_CHAR('s')
336   PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_D) PORT_CHAR('D') PORT_CHAR('d')
337   PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_F) PORT_CHAR('F') PORT_CHAR('f')
338   PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_G) PORT_CHAR('G') PORT_CHAR('g')
339   PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_H) PORT_CHAR('H') PORT_CHAR('h')
340   PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_J) PORT_CHAR('J') PORT_CHAR('j')
341   PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_K) PORT_CHAR('K') PORT_CHAR('k')
337342
338343   PORT_START("KEY.4")
339   PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD )
340   PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD )
341   PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD )
342   PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD )
343   PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD )
344   PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD )
345   PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD )
346   PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD )
344   PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_Z) PORT_CHAR('Z') PORT_CHAR('z')
345   PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_X) PORT_CHAR('X') PORT_CHAR('x')
346   PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_C) PORT_CHAR('C') PORT_CHAR('c')
347   PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_V) PORT_CHAR('V') PORT_CHAR('v')
348   PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_B) PORT_CHAR('B') PORT_CHAR('b')
349   PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_N) PORT_CHAR('N') PORT_CHAR('n')
350   PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_M) PORT_CHAR('M') PORT_CHAR('m')
351   PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_COMMA) PORT_CHAR(',') PORT_CHAR('<')
347352
348353   PORT_START("KEY.5")
349   PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD )
350   PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD )
351   PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD )
352   PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD )
353   PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD )
354   PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD )
355   PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD )
356   PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD )
354   PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_UP)
355   PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_LEFT) PORT_CODE(KEYCODE_BACKSPACE) PORT_CHAR(8)
356   PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_0) PORT_CHAR('0') PORT_CHAR(')')
357   PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_SPACE) PORT_CHAR(' ')
358   PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_STOP) PORT_CHAR('.') PORT_CHAR('>')
359   PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_P) PORT_CHAR('P') PORT_CHAR('p')
360   PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_O) PORT_CHAR('O') PORT_CHAR('o')
361   PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_9) PORT_CHAR('9') PORT_CHAR('(')
357362
358363   PORT_START("KEY.6")
359   PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD )
360   PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD )
361   PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD )
362   PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD )
363   PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD )
364   PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD )
365   PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD )
366   PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD )
364   PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_RIGHT)
365   PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_DOWN)
366   PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_MINUS) PORT_CHAR('-') PORT_CHAR('_')
367   PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_SLASH) PORT_CHAR('/') PORT_CHAR('?')
368   PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_COLON) PORT_CHAR(';') PORT_CHAR(':')
369   PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_BACKSLASH) PORT_CHAR('\\') PORT_CHAR('|')
370   PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_L) PORT_CHAR('L') PORT_CHAR('l')
371   PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_EQUALS) PORT_CHAR('=') PORT_CHAR('+')
367372
368373   PORT_START("KEY.7")
369   PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD )
370   PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD )
374   PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_DEL) PORT_CHAR(127)
375   PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_CLOSEBRACE) PORT_CHAR('{') PORT_CHAR('}')
371376   PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD )
372377   PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD )
373378   PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD )
374379   PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD )
375380   PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD )
376   PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD )
381   PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_END) // FUNC key
377382INPUT_PORTS_END
378383
379384
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412417UINT32 vixen_state::screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
413418{
414419   const pen_t *pen = m_palette->pens();
420   UINT8 x, y, chr, gfx, inv, ra;
415421
416   for (int txadr = 0; txadr < 26; txadr++)
422   for (y = 0; y < 26; y++)
417423   {
418      for (int scan = 0; scan < 10; scan++)
424      for (ra = 0; ra < 10; ra++)
419425      {
420         for (int chadr = 0; chadr < 128; chadr++)
426         for (x = 0; x < 128; x++)
421427         {
422            UINT16 sync_addr = (txadr << 7) | chadr;
423            UINT8 sync_data = m_sync_rom[sync_addr];
424            int blank = BIT(sync_data, 4);
428            UINT16 sync_addr = ((y+1) << 7) + x + 1; // it's out by a row and a column
429            UINT8 sync_data = m_sync_rom[sync_addr & 0xfff];
430            bool blank = BIT(sync_data, 4);
425431            /*
426432            int clrchadr = BIT(sync_data, 7);
427433            int hsync = BIT(sync_data, 6);
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433439                sync_addr,sync_data,txadr,scan,chadr,comp_sync,vsync,blank,clrtxadr,hsync,clrchadr);
434440            */
435441
436            int reverse = 0;
442            chr = m_video_ram[(y<<7) + x];
437443
438            UINT16 video_addr = (txadr << 7) | chadr;
439            UINT8 video_data = m_video_ram[video_addr];
440            UINT16 char_addr = 0;
441
442444            if (m_256)
443445            {
444               char_addr = (BIT(video_data, 7) << 11) | (scan << 7) | (video_data & 0x7f);
445               reverse = m_alt;
446               gfx = m_char_rom[(BIT(chr, 7) << 11) | (ra << 7) | (chr & 0x7f)];
447               inv = m_alt ? 0xff : 0;
446448            }
447449            else
448450            {
449               char_addr = (scan << 7) | (video_data & 0x7f);
450               reverse = BIT(video_data, 7);
451               gfx = m_char_rom[(ra << 7) | (chr & 0x7f)];
452               inv = BIT(chr, 7) ? 0xff : 0;
451453            }
452454
453            UINT8 char_data = m_char_rom[char_addr];
455            gfx = (blank) ? 0 : (gfx ^ inv);
454456
455            for (int x = 0; x < 8; x++)
457            for (int b = 0; b < 8; b++)
456458            {
457               int color = (BIT(char_data, 7 - x) ^ reverse) & !blank;
459               int color = BIT(gfx, 7 - b);
458460
459               bitmap.pix32((txadr * 10) + scan, (chadr * 8) + x) = pen[color];
461               bitmap.pix32((y * 10) + ra, (x * 8) + b) = pen[color];
460462            }
461463         }
462464      }
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537539   m_fdc->dden_w(BIT(data, 2));
538540
539541   // charset
540   m_alt = BIT(data, 3);
541   m_256 = BIT(data, 4);
542   m_alt = !BIT(data, 3);
543   m_256 = !BIT(data, 4);
542544
543545   // beep enable
544   m_discrete->write(space, NODE_01, BIT(data, 5));
546   m_discrete->write(space, NODE_01, !BIT(data, 5));
545547}
546548
547549//-------------------------------------------------
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690692void vixen_state::machine_start()
691693{
692694   // configure memory banking
693   UINT8 *ram = m_ram->pointer();
694695
695   membank("bank1")->configure_entry(0, ram);
696   membank("bank1")->configure_entry(1, m_rom);
697
698   membank("bank2")->configure_entry(0, ram);
699   membank("bank2")->configure_entry(1, m_video_ram);
700
701696   membank("bank3")->configure_entry(0, m_video_ram);
702697   membank("bank3")->configure_entry(1, m_rom);
703698
704699   membank("bank4")->configure_entry(0, m_video_ram);
705700
706701   // register for state saving
707   save_item(NAME(m_reset));
708702   save_item(NAME(m_col));
709703   save_item(NAME(m_cmd_d0));
710704   save_item(NAME(m_cmd_d1));
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714708
715709void vixen_state::machine_reset()
716710{
717   address_space &program = m_maincpu->space(AS_PROGRAM);
718
719   program.install_read_bank(0x0000, 0xefff, 0xfff, 0, "bank1");
720   program.install_write_bank(0x0000, 0xefff, 0xfff, 0, "bank2");
721
722   membank("bank1")->set_entry(1);
723   membank("bank2")->set_entry(1);
724711   membank("bank3")->set_entry(1);
725712
726   m_reset = 1;
727
728713   m_vsync = 0;
729714   m_cmd_d0 = 0;
730715   m_cmd_d1 = 0;
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733718   m_fdc->reset();
734719   m_io_i8155->reset();
735720   m_usart->reset();
721   m_maincpu->set_state_int(Z80_PC, 0xf000);
736722}
737723
738724
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749735   // basic machine hardware
750736   MCFG_CPU_ADD(Z8400A_TAG, Z80, XTAL_23_9616MHz/6)
751737   MCFG_CPU_PROGRAM_MAP(vixen_mem)
738   MCFG_CPU_DECRYPTED_OPCODES_MAP(bios_mem)
752739   MCFG_CPU_IO_MAP(vixen_io)
753740   MCFG_CPU_IRQ_ACKNOWLEDGE_DRIVER(vixen_state,vixen_int_ack)
754741
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793780   MCFG_FD1797_ADD(FDC1797_TAG, XTAL_23_9616MHz/24)
794781   MCFG_WD_FDC_INTRQ_CALLBACK(WRITELINE(vixen_state, fdc_intrq_w))
795782   MCFG_FLOPPY_DRIVE_ADD(FDC1797_TAG":0", vixen_floppies, "525dd", floppy_image_device::default_floppy_formats)
783   MCFG_FLOPPY_DRIVE_SOUND(true)
796784   MCFG_FLOPPY_DRIVE_ADD(FDC1797_TAG":1", vixen_floppies, "525dd", floppy_image_device::default_floppy_formats)
785   MCFG_FLOPPY_DRIVE_SOUND(true)
797786   MCFG_IEEE488_BUS_ADD()
798787   MCFG_IEEE488_SRQ_CALLBACK(WRITELINE(vixen_state, srq_w))
799788   MCFG_IEEE488_ATN_CALLBACK(WRITELINE(vixen_state, atn_w))
r249962r249963
837826//  DRIVER_INIT( vixen )
838827//-------------------------------------------------
839828
840DIRECT_UPDATE_MEMBER(vixen_state::vixen_direct_update_handler)
841{
842   if (address >= 0xf000)
843   {
844      if (m_reset)
845      {
846         address_space &program = m_maincpu->space(AS_PROGRAM);
847829
848         program.install_read_bank(0x0000, 0xefff, "bank1");
849         program.install_write_bank(0x0000, 0xefff, "bank2");
850
851         membank("bank1")->set_entry(0);
852         membank("bank2")->set_entry(0);
853
854         m_reset = 0;
855      }
856
857      direct.explicit_configure(0xf000, 0xffff, 0xfff, m_rom);
858
859      return ~0;
860   }
861
862   return address;
863}
864
865830DRIVER_INIT_MEMBER(vixen_state,vixen)
866831{
867   m_maincpu->space(AS_PROGRAM).set_direct_update_handler(direct_update_delegate(FUNC(vixen_state::vixen_direct_update_handler), this));
832   m_program = &m_maincpu->space(AS_PROGRAM);
868833}
869834
870835
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873838//  SYSTEM DRIVERS
874839//**************************************************************************
875840
876//    YEAR  NAME    PARENT  COMPAT   MACHINE    INPUT    INIT    COMPANY   FULLNAME       FLAGS
877COMP( 1984, vixen,  0,       0,     vixen,  vixen, vixen_state,  vixen,  "Osborne",   "Vixen",      MACHINE_NOT_WORKING )
841//    YEAR  NAME    PARENT  COMPAT  MACHINE    INPUT    CLASS         INIT    COMPANY      FULLNAME       FLAGS
842COMP( 1984, vixen,  0,       0,     vixen,     vixen,   vixen_state,  vixen,  "Osborne",   "Vixen",      0 )
trunk/src/mame/includes/vixen.h
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5353         m_txrdy(0)
5454   { }
5555
56   DECLARE_READ8_MEMBER( status_r );
57   DECLARE_WRITE8_MEMBER( cmd_w );
58   DECLARE_READ8_MEMBER( ieee488_r );
59   DECLARE_READ8_MEMBER( port3_r );
60   DECLARE_READ8_MEMBER( i8155_pa_r );
61   DECLARE_WRITE8_MEMBER( i8155_pb_w );
62   DECLARE_WRITE8_MEMBER( i8155_pc_w );
63   DECLARE_WRITE8_MEMBER( io_i8155_pb_w );
64   DECLARE_WRITE8_MEMBER( io_i8155_pc_w );
65   DECLARE_WRITE_LINE_MEMBER( io_i8155_to_w );
66   DECLARE_WRITE_LINE_MEMBER( srq_w );
67   DECLARE_WRITE_LINE_MEMBER( atn_w );
68   DECLARE_WRITE_LINE_MEMBER( rxrdy_w );
69   DECLARE_WRITE_LINE_MEMBER( txrdy_w );
70   DECLARE_WRITE_LINE_MEMBER( fdc_intrq_w );
71   DECLARE_DRIVER_INIT(vixen);
72   TIMER_DEVICE_CALLBACK_MEMBER(vsync_tick);
73   IRQ_CALLBACK_MEMBER(vixen_int_ack);
74   DECLARE_READ8_MEMBER(opram_r);
75   DECLARE_READ8_MEMBER(oprom_r);
76   UINT32 screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
77
78private:
5679   required_device<cpu_device> m_maincpu;
5780   required_device<fd1797_t> m_fdc;
5881   required_device<i8155_device> m_io_i8155;
r249962r249963
7093   required_shared_ptr<UINT8> m_video_ram;
7194   required_ioport_array<8> m_key;
7295
96   address_space *m_program;
97
7398   virtual void machine_start();
7499   virtual void machine_reset();
75100
76101   virtual void video_start();
77   UINT32 screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
78102
79103   void update_interrupt();
80104
81   DECLARE_WRITE8_MEMBER( ctl_w );
82   DECLARE_READ8_MEMBER( status_r );
83   DECLARE_WRITE8_MEMBER( cmd_w );
84   DECLARE_READ8_MEMBER( ieee488_r );
85   DECLARE_READ8_MEMBER( port3_r );
86   DECLARE_READ8_MEMBER( i8155_pa_r );
87   DECLARE_WRITE8_MEMBER( i8155_pb_w );
88   DECLARE_WRITE8_MEMBER( i8155_pc_w );
89   DECLARE_WRITE8_MEMBER( io_i8155_pb_w );
90   DECLARE_WRITE8_MEMBER( io_i8155_pc_w );
91   DECLARE_WRITE_LINE_MEMBER( io_i8155_to_w );
92   DECLARE_WRITE_LINE_MEMBER( srq_w );
93   DECLARE_WRITE_LINE_MEMBER( atn_w );
94   DECLARE_WRITE_LINE_MEMBER( rxrdy_w );
95   DECLARE_WRITE_LINE_MEMBER( txrdy_w );
96   DECLARE_WRITE_LINE_MEMBER( fdc_intrq_w );
97   DIRECT_UPDATE_MEMBER(vixen_direct_update_handler);
98
99   // memory state
100   int m_reset;
101
102105   // keyboard state
103106   UINT8 m_col;
104107
r249962r249963
122125   int m_enb_ring_int;
123126
124127   // video state
125   int m_alt;
126   int m_256;
127
128   DECLARE_DRIVER_INIT(vixen);
129   TIMER_DEVICE_CALLBACK_MEMBER(vsync_tick);
130   IRQ_CALLBACK_MEMBER(vixen_int_ack);
128   bool m_alt;
129   bool m_256;
131130};
132131
133132#endif

https://github.com/mamedev/mame/commit/e3af35d50a13b95ee02f10febb3b12a343fd89b0

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