trunk/src/devices/bus/vcs/dpcplus.c
| r249957 | r249958 | |
|---|
| 18 | 18 | Bankswitching uses addresses $FFF6-$FFFB |
| 19 | 19 | |
| 20 | 20 | * ARM RAM mapped at $40000000 in this area |
| 21 | | $0000-$0BFF: DPC+ driver (not accessible by 2600 itself) |
| 22 | | $0C00-$1BFF: Bank 0 - ARM code starts here, but 6507 code can also be placed here aswell |
| 21 | $0000-$0BFF: DPC+ driver (not accessible by 2600 itself) (copied to $40000000 - $40000bff on startup by ARM) |
| 22 | $0C00-$1BFF: Bank 0 (each bank can map to 0x1000 - 0x1fff in 6507 space, like other carts) |
| 23 | 23 | $1C00-$2BFF: Bank 1 |
| 24 | 24 | $2C00-$3BFF: Bank 2 |
| 25 | 25 | $3C00-$4BFF: Bank 3 |
| 26 | 26 | $4C00-$5BFF: Bank 4 |
| 27 | | $5C00-$6BFF: Bank 5 - 6507 code |
| 28 | | * ARM RAM mapped at $40000C00 in this area |
| 29 | | $6C00-$7BFF: Display Data (indirect access) |
| 30 | | * ARM RAM mapped at $40001C00 in this area |
| 31 | | $7C00-$7FFF: Synth Frequency Data (not accessible by 2600 itself) |
| 27 | $5C00-$6BFF: Bank 5 (default bank is bank 5) |
| 28 | $6C00-$7BFF: Display Data (indirect access) (copied to $40000C00 - $40001bff on startup by ARM) |
| 29 | $7C00-$7FFF: Synth Frequency Data (not accessible by 2600 itself) (copied to $40001C00 - $40001fff on startup by ARM) |
| 32 | 30 | |
| 33 | 31 | ***************************************************************************/ |
| 34 | 32 | |
| r249957 | r249958 | |
|---|
| 61 | 59 | |
| 62 | 60 | void a26_rom_dpcplus_device::device_reset() |
| 63 | 61 | { |
| 64 | | m_base_bank = 0; |
| 62 | m_base_bank = 5; |
| 65 | 63 | } |
| 66 | 64 | |
| 65 | |
| 66 | READ8_MEMBER(a26_rom_dpcplus_device::read8_r) |
| 67 | { |
| 68 | return m_rom[offset + (m_base_bank * 0x1000)]; |
| 69 | } |
| 70 | |
| 71 | |
| 67 | 72 | READ32_MEMBER(a26_rom_dpcplus_device::armrom_r) |
| 68 | 73 | { |
| 69 | | UINT32 ret = (a26_rom_f8_device::read_rom(space, offset * 4 + 3) << 24) | |
| 70 | | (a26_rom_f8_device::read_rom(space, offset * 4 + 2) << 16) | |
| 71 | | (a26_rom_f8_device::read_rom(space, offset * 4 + 1) << 8) | |
| 72 | | (a26_rom_f8_device::read_rom(space, offset * 4 + 0) << 0); |
| 74 | UINT32 ret = (m_rom[offset * 4 + 3] << 24) | |
| 75 | (m_rom[offset * 4 + 2] << 16) | |
| 76 | (m_rom[offset * 4 + 1] << 8) | |
| 77 | (m_rom[offset * 4 + 0] << 0); |
| 73 | 78 | return ret; |
| 74 | 79 | } |
| 75 | 80 | |
| r249957 | r249958 | |
|---|
| 78 | 83 | |
| 79 | 84 | } |
| 80 | 85 | |
| 86 | READ32_MEMBER(a26_rom_dpcplus_device::arm_E01FC088_r) |
| 87 | { |
| 88 | return 0xffffffff; |
| 89 | } |
| 90 | |
| 81 | 91 | static ADDRESS_MAP_START( dpcplus_arm7_map, AS_PROGRAM, 32, a26_rom_dpcplus_device ) |
| 82 | 92 | // todo: implement all this correctly |
| 83 | 93 | AM_RANGE(0x00000000, 0x00007fff) AM_READWRITE(armrom_r,armrom_w) // flash, 32k |
| 84 | 94 | AM_RANGE(0x40000000, 0x40001fff) AM_RAM // sram, 8k |
| 95 | |
| 96 | AM_RANGE(0xE01FC088, 0xE01FC08b) AM_READ(arm_E01FC088_r) |
| 85 | 97 | ADDRESS_MAP_END |
| 86 | 98 | |
| 87 | 99 | static MACHINE_CONFIG_FRAGMENT( a26_dpcplus ) |
| r249957 | r249958 | |
|---|
| 97 | 109 | |
| 98 | 110 | READ8_MEMBER(a26_rom_dpcplus_device::read_rom) |
| 99 | 111 | { |
| 100 | | return a26_rom_f8_device::read_rom(space, offset); |
| 112 | // banks start at 0xc00 |
| 113 | return read8_r(space, offset+0xc00); |
| 101 | 114 | } |
| 102 | 115 | |
| 103 | 116 | WRITE8_MEMBER(a26_rom_dpcplus_device::write_bank) |
| 104 | 117 | { |
| 105 | | a26_rom_f8_device::write_bank(space, offset, data); |
| 118 | // a26_rom_f8_device::write_bank(space, offset, data); |
| 106 | 119 | } |