trunk/src/devices/bus/vcs/dpcplus.c
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| 1 | 1 | // license:BSD-3-Clause |
| 2 | | // copyright-holders: |
| 2 | // copyright-holders:David Haywood |
| 3 | 3 | /*************************************************************************** |
| 4 | 4 | |
| 5 | 5 | Atari 2600 cart with DPC+ |
| 6 | 6 | |
| 7 | | the DPC+ adds an ARM CPU amongst other things (display improvements, etc.) |
| 7 | the DPC+ adds an ARM CPU, including video improvements plus an extra synthesizer. |
| 8 | 8 | |
| 9 | | map (according to a blogpost on atariage): |
| 10 | | NOTE: All banks are accessible via $F000 |
| 9 | Some info on the DPC+ hardware can be found on Darrell Spice Jr's guides: |
| 10 | http://atariage.com/forums/blog/148/entry-11811-dpcarm-part-6-dpc-cartridge-layout/ |
| 11 | http://atariage.com/forums/blog/148/entry-11883-dpcarm-part-7-6507arm-exchange-of-information/ |
| 12 | http://atariage.com/forums/blog/148/entry-11903-dpcarm-part-8-multiple-functions/ |
| 13 | http://atariage.com/forums/blog/148/entry-11935-dpcarm-part-9-functional-menu/ |
| 14 | http://atariage.com/forums/blog/148/entry-11964-dpcarm-part-10-score-timer-display/ |
| 15 | http://atariage.com/forums/blog/148/entry-11988-dpcarm-part-12-gamepad-support/ |
| 11 | 16 | |
| 17 | map: |
| 18 | Bankswitching uses addresses $FFF6-$FFFB |
| 19 | |
| 12 | 20 | * ARM RAM mapped at $40000000 in this area |
| 13 | 21 | $0000-$0BFF: DPC+ driver (not accessible by 2600 itself) |
| 14 | | $0C00-$1BFF: Bank 0 |
| 22 | $0C00-$1BFF: Bank 0 - ARM code starts here, but 6507 code can also be placed here aswell |
| 15 | 23 | $1C00-$2BFF: Bank 1 |
| 16 | 24 | $2C00-$3BFF: Bank 2 |
| 17 | 25 | $3C00-$4BFF: Bank 3 |
| 18 | 26 | $4C00-$5BFF: Bank 4 |
| 19 | | $5C00-$6BFF: Bank 5 |
| 27 | $5C00-$6BFF: Bank 5 - 6507 code |
| 20 | 28 | * ARM RAM mapped at $40000C00 in this area |
| 21 | 29 | $6C00-$7BFF: Display Data (indirect access) |
| 22 | 30 | * ARM RAM mapped at $40001C00 in this area |
| 23 | | $7C00-$7FFF: Frequency Data (not accessible by 2600 itself) |
| 31 | $7C00-$7FFF: Synth Frequency Data (not accessible by 2600 itself) |
| 24 | 32 | |
| 25 | 33 | ***************************************************************************/ |
| 26 | 34 | |
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| 72 | 80 | |
| 73 | 81 | static ADDRESS_MAP_START( dpcplus_arm7_map, AS_PROGRAM, 32, a26_rom_dpcplus_device ) |
| 74 | 82 | // todo: implement all this correctly |
| 75 | | AM_RANGE(0x00000000, 0x00007fff) AM_READWRITE(armrom_r,armrom_w)// flash, 32k |
| 83 | AM_RANGE(0x00000000, 0x00007fff) AM_READWRITE(armrom_r,armrom_w) // flash, 32k |
| 76 | 84 | AM_RANGE(0x40000000, 0x40001fff) AM_RAM // sram, 8k |
| 77 | 85 | ADDRESS_MAP_END |
| 78 | 86 | |
| 79 | 87 | static MACHINE_CONFIG_FRAGMENT( a26_dpcplus ) |
| 80 | | MCFG_CPU_ADD("arm", ARM7, 70000000) // correct type? |
| 88 | MCFG_CPU_ADD("arm", ARM7, 70000000) |
| 81 | 89 | MCFG_CPU_PROGRAM_MAP(dpcplus_arm7_map) |
| 82 | 90 | MACHINE_CONFIG_END |
| 83 | 91 | |
trunk/src/mame/drivers/aristmk5.c
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| 123 | 123 | U26: SGS THOMSON ST93C46 (1K (64 x 16 or 128 x 8) Serial EEPROM). |
| 124 | 124 | U27: SGS THOMSON ST93C46 (1K (64 x 16 or 128 x 8) Serial EEPROM). |
| 125 | 125 | |
| 126 | | U35: PHILIPS 74HC273. |
| 126 | U35: PHILIPS 74HC2... |
| 127 | 127 | U36: LATTICE GAL20V8B-15LJ (High Performance E2CMOS PLD Generic Array Logic, 28-Lead PLCC). |
| 128 | 128 | U40: Dallas Semiconductor DS1202S (Serial Timekeeping Chip). |
| 129 | 129 | U41: Maxim Integrated MAX705CSA (MPU Supervisory Circuits). |
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| 144 | 144 | U71: Texas Instruments TL16C452FN (UART Interface IC Dual UART w/Prl Port & w/o FIFO). |
| 145 | 145 | U72: Texas Instruments TL16C452FN (UART Interface IC Dual UART w/Prl Port & w/o FIFO). |
| 146 | 146 | U73: CX0826 72 MHz crystal. |
| 147 | | U85: ARM250: Computer system on a chip. ARM 32bit RISC processor with memory, video, and I/O controllers. |
| 148 | 147 | U89: Allegro MicroSystems UDN2543B (Protected quad power driver). |
| 149 | 148 | U149: ISSI IS41C16257-60K (256K x 16bit (4-MBIT) Dynamic RAM With Fast Page Mode). |
| 150 | 149 | U152: ISSI IS41C16257-60K (256K x 16bit (4-MBIT) Dynamic RAM With Fast Page Mode). |
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| 160 | 159 | |
| 161 | 160 | X2: Unpopulated crystal (from factory). |
| 162 | 161 | |
| 163 | | The 96-pin female connector at the bottom of the ROM banks is intended for a sub board |
| 164 | | with two ROM sockets, that once plugged switch the ROM bank 0 with the sub board bank. |
| 165 | | Just to place the clear chips without removing the U7 & U11 EPROMS. |
| 166 | | |
| 167 | 162 | *****************************************************************************************************************/ |
| 168 | 163 | |
| 169 | 164 | #define MASTER_CLOCK XTAL_72MHz /* confirmed */ |