trunk/src/mame/drivers/queen.c
| r249148 | r249149 | |
| 32 | 32 | #include "machine/pcshare.h" |
| 33 | 33 | #include "machine/pckeybrd.h" |
| 34 | 34 | #include "machine/idectrl.h" |
| 35 | | #include "video/pc_vga.h" |
| 35 | #include "bus/isa/trident.h" |
| 36 | 36 | |
| 37 | 37 | |
| 38 | 38 | class queen_state : public pcat_base_state |
| 39 | 39 | { |
| 40 | 40 | public: |
| 41 | 41 | queen_state(const machine_config &mconfig, device_type type, const char *tag) |
| 42 | | : pcat_base_state(mconfig, type, tag) |
| 42 | : pcat_base_state(mconfig, type, tag), |
| 43 | m_vga(*this, "vga") |
| 43 | 44 | { |
| 44 | 45 | } |
| 45 | 46 | |
| 46 | 47 | UINT32 *m_bios_ram; |
| 47 | 48 | UINT32 *m_bios_ext_ram; |
| 49 | |
| 50 | required_device<trident_vga_device> m_vga; |
| 51 | |
| 48 | 52 | UINT8 m_mtxc_config_reg[256]; |
| 49 | 53 | UINT8 m_piix4_config_reg[4][256]; |
| 54 | UINT8 m_pci_vga_reg[256]; |
| 50 | 55 | |
| 51 | 56 | DECLARE_WRITE32_MEMBER( bios_ext_ram_w ); |
| 52 | 57 | |
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| 54 | 59 | virtual void machine_start(); |
| 55 | 60 | virtual void machine_reset(); |
| 56 | 61 | void intel82439tx_init(); |
| 62 | void pci_vga_init(); |
| 57 | 63 | }; |
| 58 | 64 | |
| 59 | 65 | |
| r249148 | r249149 | |
| 70 | 76 | static void mtxc_config_w(device_t *busdevice, device_t *device, int function, int reg, UINT8 data) |
| 71 | 77 | { |
| 72 | 78 | queen_state *state = busdevice->machine().driver_data<queen_state>(); |
| 73 | | printf("MTXC: write %d, %02X, %02X\n", function, reg, data); |
| 79 | // osd_printf_debug("MXTC: write %d, %02X, %02X\n", function, reg, data); |
| 74 | 80 | |
| 75 | 81 | /* |
| 76 | 82 | memory banking with North Bridge: |
| r249148 | r249149 | |
| 99 | 105 | |
| 100 | 106 | void queen_state::intel82439tx_init() |
| 101 | 107 | { |
| 108 | m_mtxc_config_reg[0] = 0x86; |
| 109 | m_mtxc_config_reg[1] = 0x80; // Vendor ID, Intel |
| 110 | m_mtxc_config_reg[3] = 0x70; // Device ID, MXTC |
| 111 | |
| 112 | m_mtxc_config_reg[0x0b] = 0x06; // PCI Class Bridge |
| 113 | |
| 102 | 114 | m_mtxc_config_reg[0x60] = 0x02; |
| 103 | 115 | m_mtxc_config_reg[0x61] = 0x02; |
| 104 | 116 | m_mtxc_config_reg[0x62] = 0x02; |
| r249148 | r249149 | |
| 212 | 224 | } |
| 213 | 225 | } |
| 214 | 226 | |
| 227 | void queen_state::pci_vga_init() |
| 228 | { |
| 229 | m_pci_vga_reg[0x00] = 0x23; |
| 230 | m_pci_vga_reg[0x01] = 0x10; |
| 231 | m_pci_vga_reg[0x02] = 0x50; |
| 232 | m_pci_vga_reg[0x03] = 0x97; // Trident 3DImage 9750 (seems must be that or the Blade 3D) |
| 233 | m_pci_vga_reg[0x04] = 0x01; // PCI_CMD_IO_ENABLE |
| 234 | m_pci_vga_reg[0x0b] = 0x03; // PCI class display |
| 235 | } |
| 215 | 236 | |
| 237 | static UINT8 pci_vga_config_r(device_t *busdevice, device_t *device, int function, int reg) |
| 238 | { |
| 239 | queen_state *state = busdevice->machine().driver_data<queen_state>(); |
| 240 | // osd_printf_debug("%s:PIIX4: write %d, %02X, %02X\n", machine.describe_context(), function, reg, data); |
| 241 | return state->m_pci_vga_reg[reg]; |
| 242 | } |
| 243 | |
| 244 | static UINT32 pci_vga_r(device_t *busdevice, device_t *device, int function, int reg, UINT32 mem_mask) |
| 245 | { |
| 246 | UINT32 r = 0; |
| 247 | if (ACCESSING_BITS_24_31) |
| 248 | { |
| 249 | r |= pci_vga_config_r(busdevice, device, function, reg + 3) << 24; |
| 250 | } |
| 251 | if (ACCESSING_BITS_16_23) |
| 252 | { |
| 253 | r |= pci_vga_config_r(busdevice, device, function, reg + 2) << 16; |
| 254 | } |
| 255 | if (ACCESSING_BITS_8_15) |
| 256 | { |
| 257 | r |= pci_vga_config_r(busdevice, device, function, reg + 1) << 8; |
| 258 | } |
| 259 | if (ACCESSING_BITS_0_7) |
| 260 | { |
| 261 | r |= pci_vga_config_r(busdevice, device, function, reg + 0) << 0; |
| 262 | } |
| 263 | return r; |
| 264 | } |
| 265 | |
| 266 | |
| 267 | static void pci_vga_config_w(device_t *busdevice, device_t *device, int function, int reg, UINT8 data) |
| 268 | { |
| 269 | queen_state *state = busdevice->machine().driver_data<queen_state>(); |
| 270 | // osd_printf_debug("%s:PIIX4: write %d, %02X, %02X\n", machine.describe_context(), function, reg, data); |
| 271 | state->m_pci_vga_reg[reg] = data; |
| 272 | } |
| 273 | |
| 274 | static void pci_vga_w(device_t *busdevice, device_t *device, int function, int reg, UINT32 data, UINT32 mem_mask) |
| 275 | { |
| 276 | osd_printf_warning("PCI write: %x %x\n", reg, data); |
| 277 | if (ACCESSING_BITS_24_31) |
| 278 | { |
| 279 | pci_vga_config_w(busdevice, device, function, reg + 3, (data >> 24) & 0xff); |
| 280 | } |
| 281 | if (ACCESSING_BITS_16_23) |
| 282 | { |
| 283 | pci_vga_config_w(busdevice, device, function, reg + 2, (data >> 16) & 0xff); |
| 284 | } |
| 285 | if (ACCESSING_BITS_8_15) |
| 286 | { |
| 287 | pci_vga_config_w(busdevice, device, function, reg + 1, (data >> 8) & 0xff); |
| 288 | } |
| 289 | if (ACCESSING_BITS_0_7) |
| 290 | { |
| 291 | if (reg == 4) |
| 292 | { |
| 293 | data |= 1; // PCI_CMD_IO_ENABLE |
| 294 | } |
| 295 | |
| 296 | pci_vga_config_w(busdevice, device, function, reg + 0, (data >> 0) & 0xff); |
| 297 | } |
| 298 | } |
| 299 | |
| 216 | 300 | WRITE32_MEMBER(queen_state::bios_ext_ram_w) |
| 217 | 301 | { |
| 218 | 302 | if (m_mtxc_config_reg[0x63] & 0x40) // write to RAM if this region is write-enabled |
| r249148 | r249149 | |
| 233 | 317 | static ADDRESS_MAP_START( queen_map, AS_PROGRAM, 32, queen_state ) |
| 234 | 318 | AM_RANGE(0x00000000, 0x0009ffff) AM_RAM |
| 235 | 319 | AM_RANGE(0x000a0000, 0x000bffff) AM_DEVREADWRITE8("vga", vga_device, mem_r, mem_w, 0xffffffff) |
| 320 | AM_RANGE(0x000c0000, 0x000c7fff) AM_ROM AM_REGION("video_bios", 0) |
| 236 | 321 | AM_RANGE(0x000e0000, 0x000effff) AM_ROMBANK("bios_ext") AM_WRITE(bios_ext_ram_w) |
| 237 | 322 | AM_RANGE(0x000f0000, 0x000fffff) AM_ROMBANK("bios_bank") AM_WRITE(bios_ram_w) |
| 238 | | AM_RANGE(0x00100000, 0x01ffffff) AM_RAM |
| 323 | AM_RANGE(0x00100000, 0x07ffffff) AM_RAM // 128MB RAM |
| 239 | 324 | AM_RANGE(0xfffc0000, 0xffffffff) AM_ROM AM_REGION("bios", 0) /* System BIOS */ |
| 240 | 325 | ADDRESS_MAP_END |
| 241 | 326 | |
| r249148 | r249149 | |
| 260 | 345 | m_bios_ext_ram = auto_alloc_array(machine(), UINT32, 0x10000/4); |
| 261 | 346 | |
| 262 | 347 | intel82439tx_init(); |
| 348 | pci_vga_init(); |
| 263 | 349 | } |
| 264 | 350 | |
| 265 | 351 | void queen_state::machine_reset() |
| r249148 | r249149 | |
| 281 | 367 | MCFG_PCI_BUS_LEGACY_ADD("pcibus", 0) |
| 282 | 368 | MCFG_PCI_BUS_LEGACY_DEVICE(0, NULL, intel82439tx_pci_r, intel82439tx_pci_w) |
| 283 | 369 | MCFG_PCI_BUS_LEGACY_DEVICE(7, NULL, intel82371ab_pci_r, intel82371ab_pci_w) |
| 370 | MCFG_PCI_BUS_LEGACY_DEVICE(9, NULL, pci_vga_r, pci_vga_w) |
| 284 | 371 | |
| 285 | 372 | MCFG_IDE_CONTROLLER_ADD("ide", ata_devices, "hdd", NULL, true) |
| 286 | 373 | MCFG_ATA_INTERFACE_IRQ_HANDLER(DEVWRITELINE("pic8259_2", pic8259_device, ir6_w)) |
| r249148 | r249149 | |
| 289 | 376 | MCFG_ATA_INTERFACE_IRQ_HANDLER(DEVWRITELINE("pic8259_2", pic8259_device, ir7_w)) |
| 290 | 377 | |
| 291 | 378 | /* video hardware */ |
| 292 | | MCFG_FRAGMENT_ADD( pcvideo_vga ) |
| 379 | MCFG_FRAGMENT_ADD( pcvideo_trident_vga ) |
| 293 | 380 | MACHINE_CONFIG_END |
| 294 | 381 | |
| 295 | 382 | |
| r249148 | r249149 | |
| 299 | 386 | ROM_REGION( 0x40000, "bios", 0 ) |
| 300 | 387 | ROM_LOAD( "bios-original.bin", 0x00000, 0x40000, CRC(feb542d4) SHA1(3cc5d8aeb0e3b7d9ed33248a4f3dc507d29debd9) ) |
| 301 | 388 | |
| 302 | | ROM_REGION( 0x8000, "video_bios", ROMREGION_ERASEFF ) // TODO: no VGA card is hooked up, to be removed |
| 303 | | // ROM_LOAD16_BYTE( "trident_tgui9680_bios.bin", 0x0000, 0x4000, BAD_DUMP CRC(1eebde64) SHA1(67896a854d43a575037613b3506aea6dae5d6a19) ) |
| 304 | | // ROM_CONTINUE( 0x0001, 0x4000 ) |
| 389 | ROM_REGION( 0x8000, "video_bios", 0 ) |
| 390 | ROM_LOAD16_BYTE( "trident_tgui9680_bios.bin", 0x0000, 0x4000, BAD_DUMP CRC(1eebde64) SHA1(67896a854d43a575037613b3506aea6dae5d6a19) ) |
| 391 | ROM_CONTINUE( 0x0001, 0x4000 ) |
| 305 | 392 | |
| 306 | 393 | DISK_REGION( "ide:0:hdd:image" ) |
| 307 | 394 | DISK_IMAGE( "pqiidediskonmodule", 0,SHA1(a56efcc711b1c5a2e63160b3088001a8c4fb56c2) ) |