trunk/src/mame/drivers/konendev.c
| r249107 | r249108 | |
| 63 | 63 | |
| 64 | 64 | DECLARE_READ32_MEMBER(mcu2_r); |
| 65 | 65 | DECLARE_READ32_MEMBER(ifu2_r); |
| 66 | | DECLARE_READ32_MEMBER(unk_78800004_r); |
| 67 | | DECLARE_READ32_MEMBER(unk_78a00000_r); |
| 68 | | DECLARE_READ32_MEMBER(unk_78e00000_r); |
| 66 | DECLARE_READ32_MEMBER(ctrl0_r); |
| 67 | DECLARE_READ32_MEMBER(ctrl1_r); |
| 68 | DECLARE_READ32_MEMBER(ctrl2_r); |
| 69 | DECLARE_READ32_MEMBER(rtc_r); |
| 70 | DECLARE_WRITE32_MEMBER(rtc_w); |
| 69 | 71 | DECLARE_WRITE32_MEMBER(eeprom_w); |
| 72 | DECLARE_READ32_MEMBER(sound_data_r); |
| 73 | DECLARE_WRITE32_MEMBER(sound_data_w); |
| 70 | 74 | |
| 71 | 75 | DECLARE_WRITE_LINE_MEMBER(gcu_interrupt); |
| 76 | INTERRUPT_GEN_MEMBER(vbl_interrupt); |
| 72 | 77 | |
| 78 | UINT8 rtc_dev_r(UINT32 reg); |
| 79 | |
| 73 | 80 | UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect); |
| 74 | 81 | }; |
| 75 | 82 | |
| r249107 | r249108 | |
| 94 | 101 | { |
| 95 | 102 | r &= ~0x4000; // MCU2 presence |
| 96 | 103 | r &= ~0x2000; // IFU2 presence |
| 97 | | r &= ~0x1000; // FMU2 presence |
| 104 | r &= ~0x1000; // FMU2 presence |
| 98 | 105 | } |
| 99 | 106 | if (ACCESSING_BITS_0_7) |
| 100 | 107 | { |
| 101 | | r |= 0x40; // logic door |
| 102 | | r |= 0x04; // battery 1 status |
| 103 | | r |= 0x10; // battery 2 status |
| 108 | r |= ioport("DSW")->read() & 0xff; |
| 109 | |
| 110 | //r |= 0x80; // 0 = ram clear? |
| 111 | //r |= 0x40; // logic door |
| 112 | r |= 0x04; // battery 1 status |
| 113 | r |= 0x10; // battery 2 status |
| 104 | 114 | } |
| 105 | 115 | |
| 106 | 116 | return r; |
| r249107 | r249108 | |
| 118 | 128 | return r; |
| 119 | 129 | } |
| 120 | 130 | |
| 121 | | READ32_MEMBER(konendev_state::unk_78800004_r) |
| 131 | // This seems to be Epson RTC-72423 |
| 132 | UINT8 konendev_state::rtc_dev_r(UINT32 reg) |
| 122 | 133 | { |
| 123 | | return 0xffffffff; |
| 134 | switch (reg) |
| 135 | { |
| 136 | case 0x0: return 9; |
| 137 | case 0x1: return 5; |
| 138 | case 0x2: return 3; |
| 139 | case 0x3: return 2; |
| 140 | case 0x4: return 1; |
| 141 | case 0x5: return 0; |
| 142 | case 0x6: return 7; |
| 143 | case 0x7: return 2; |
| 144 | case 0x8: return 2; |
| 145 | case 0x9: return 1; |
| 146 | case 0xa: return 5; |
| 147 | case 0xb: return 1; |
| 148 | case 0xc: return 3; |
| 149 | } |
| 150 | |
| 151 | return 0; |
| 124 | 152 | } |
| 125 | 153 | |
| 126 | | READ32_MEMBER(konendev_state::unk_78a00000_r) |
| 154 | READ32_MEMBER(konendev_state::rtc_r) |
| 127 | 155 | { |
| 128 | | return 0xffffffff; |
| 156 | UINT32 r = 0; |
| 157 | |
| 158 | if (ACCESSING_BITS_24_31) |
| 159 | r |= (UINT32)(rtc_dev_r(offset * 4)) << 24; |
| 160 | if (ACCESSING_BITS_16_23) |
| 161 | r |= (UINT32)(rtc_dev_r((offset * 4)+1)) << 16; |
| 162 | if (ACCESSING_BITS_8_15) |
| 163 | r |= (UINT32)(rtc_dev_r((offset * 4)+2)) << 8; |
| 164 | if (ACCESSING_BITS_0_7) |
| 165 | r |= (UINT32)(rtc_dev_r((offset * 4)+3)); |
| 166 | |
| 167 | return r; |
| 129 | 168 | } |
| 130 | 169 | |
| 131 | | READ32_MEMBER(konendev_state::unk_78e00000_r) |
| 170 | WRITE32_MEMBER(konendev_state::rtc_w) |
| 132 | 171 | { |
| 133 | | return 0xffffffff; |
| 134 | 172 | } |
| 135 | 173 | |
| 174 | READ32_MEMBER(konendev_state::ctrl0_r) |
| 175 | { |
| 176 | return ((UINT32)(ioport("IN1")->read() & 0xffff) << 16) | 0xffff; |
| 177 | } |
| 178 | |
| 179 | READ32_MEMBER(konendev_state::ctrl1_r) |
| 180 | { |
| 181 | // 0x01000000 = main door optic |
| 182 | // 0x00000010 = hard meter access |
| 183 | |
| 184 | return 0xfeffffef; |
| 185 | } |
| 186 | |
| 187 | READ32_MEMBER(konendev_state::ctrl2_r) |
| 188 | { |
| 189 | return ((UINT32)(ioport("IN0")->read() & 0xffff) << 16) | 0xffff; |
| 190 | } |
| 191 | |
| 136 | 192 | WRITE32_MEMBER(konendev_state::eeprom_w) |
| 137 | 193 | { |
| 138 | 194 | if (ACCESSING_BITS_0_7) |
| r249107 | r249108 | |
| 143 | 199 | } |
| 144 | 200 | } |
| 145 | 201 | |
| 202 | READ32_MEMBER(konendev_state::sound_data_r) |
| 203 | { |
| 204 | return 0xffffffff; |
| 205 | } |
| 206 | |
| 207 | WRITE32_MEMBER(konendev_state::sound_data_w) |
| 208 | { |
| 209 | } |
| 210 | |
| 146 | 211 | static ADDRESS_MAP_START( konendev_map, AS_PROGRAM, 32, konendev_state ) |
| 147 | 212 | AM_RANGE(0x00000000, 0x00ffffff) AM_RAM |
| 148 | 213 | AM_RANGE(0x78000000, 0x78000003) AM_READ(mcu2_r) |
| 214 | AM_RANGE(0x78080000, 0x7808000f) AM_READWRITE(rtc_r, rtc_w) |
| 215 | AM_RANGE(0x780c0000, 0x780c0003) AM_READWRITE(sound_data_r, sound_data_w) |
| 149 | 216 | AM_RANGE(0x78100000, 0x78100003) AM_WRITE(eeprom_w) |
| 150 | 217 | AM_RANGE(0x78800000, 0x78800003) AM_READ(ifu2_r) |
| 151 | | AM_RANGE(0x78800004, 0x78800007) AM_READ(unk_78800004_r) |
| 152 | | AM_RANGE(0x78a00000, 0x78a0001f) AM_READ(unk_78a00000_r) |
| 153 | | AM_RANGE(0x78e00000, 0x78e00003) AM_READ(unk_78e00000_r) |
| 154 | | // AM_RANGE(0x78000000, 0x78000003) AM_READNOP |
| 155 | | // AM_RANGE(0x78100000, 0x7810001b) AM_RAM |
| 156 | | // AM_RANGE(0x78a00014, 0x78a00017) AM_WRITENOP |
| 218 | AM_RANGE(0x78800004, 0x78800007) AM_READ(ctrl0_r) |
| 219 | AM_RANGE(0x78a00000, 0x78a0001f) AM_READ(ctrl1_r) |
| 220 | AM_RANGE(0x78e00000, 0x78e00003) AM_READ(ctrl2_r) |
| 157 | 221 | AM_RANGE(0x79000000, 0x79000003) AM_DEVWRITE("gcu", k057714_device, fifo_w) |
| 158 | 222 | AM_RANGE(0x79800000, 0x798000ff) AM_DEVREADWRITE("gcu", k057714_device, read, write) |
| 159 | 223 | AM_RANGE(0x7a000000, 0x7a01ffff) AM_RAM AM_SHARE("nvram0") |
| r249107 | r249108 | |
| 164 | 228 | |
| 165 | 229 | |
| 166 | 230 | static INPUT_PORTS_START( konendev ) |
| 231 | PORT_START("IN0") |
| 232 | PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_GAMBLE_TAKE ) // "Take Win" button |
| 233 | PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_GAMBLE_BET ) // "Gamble" button |
| 234 | PORT_BIT( 0x2000, IP_ACTIVE_LOW, IPT_BUTTON1 ) // "25 Lines" button |
| 235 | PORT_BIT( 0x1000, IP_ACTIVE_LOW, IPT_BUTTON2 ) // "20 Lines" button |
| 236 | PORT_BIT( 0x0800, IP_ACTIVE_LOW, IPT_BUTTON3 ) // "15 Lines" button |
| 237 | PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_BUTTON4 ) // "10 Lines" button |
| 238 | PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_BUTTON5 ) // "5 Lines" button |
| 239 | PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_BUTTON6 ) // "1 Line" button |
| 240 | PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_BUTTON7 ) // "Reserve" button |
| 241 | PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_BUTTON8 ) // "Collect" button |
| 242 | PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_BUTTON9 ) // "Bet 20" button |
| 243 | PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_BUTTON10 ) // "Bet 10" button |
| 244 | PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_BUTTON11 ) // "Bet 5" button |
| 245 | PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_BUTTON12 ) // "Bet 3" button |
| 246 | PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_BUTTON13 ) // "Bet 2" button |
| 247 | PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_BUTTON14 ) // "Bet 1" button |
| 248 | |
| 249 | PORT_START("IN1") |
| 250 | PORT_BIT( 0xc000, IP_ACTIVE_LOW, IPT_UNUSED ) |
| 251 | PORT_SERVICE( 0x2000, IP_ACTIVE_LOW ) // Audit key |
| 252 | PORT_BIT( 0x1000, IP_ACTIVE_LOW, IPT_BUTTON16 ) // Reset key |
| 253 | PORT_DIPNAME( 0x0800, 0x0800, "Main door switch" ) |
| 254 | PORT_DIPSETTING( 0x0800, DEF_STR( Off ) ) |
| 255 | PORT_DIPSETTING( 0x0000, DEF_STR( On ) ) |
| 256 | PORT_DIPNAME( 0x0400, 0x0400, "Cashbox door" ) |
| 257 | PORT_DIPSETTING( 0x0400, DEF_STR( Off ) ) |
| 258 | PORT_DIPSETTING( 0x0000, DEF_STR( On ) ) |
| 259 | PORT_BIT( 0x0300, IP_ACTIVE_LOW, IPT_UNUSED ) |
| 260 | PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_UNUSED ) |
| 261 | PORT_DIPNAME( 0x0040, 0x0040, "BNA Door" ) |
| 262 | PORT_DIPSETTING( 0x0040, DEF_STR( Off ) ) |
| 263 | PORT_DIPSETTING( 0x0000, DEF_STR( On ) ) |
| 264 | PORT_DIPNAME( 0x0020, 0x0020, "BNA Transport Exist" ) |
| 265 | PORT_DIPSETTING( 0x0020, DEF_STR( Off ) ) |
| 266 | PORT_DIPSETTING( 0x0000, DEF_STR( On ) ) |
| 267 | PORT_DIPNAME( 0x0010, 0x0010, "BNA Stacker Exist" ) |
| 268 | PORT_DIPSETTING( 0x0010, DEF_STR( Off ) ) |
| 269 | PORT_DIPSETTING( 0x0000, DEF_STR( On ) ) |
| 270 | PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_UNUSED ) |
| 271 | PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_UNUSED ) |
| 272 | PORT_DIPNAME( 0x0002, 0x0002, "BNA Power" ) |
| 273 | PORT_DIPSETTING( 0x0002, DEF_STR( Off ) ) |
| 274 | PORT_DIPSETTING( 0x0000, DEF_STR( On ) ) |
| 275 | PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_UNUSED ) |
| 276 | |
| 277 | PORT_START("DSW") |
| 278 | PORT_DIPNAME( 0x80, 0x80, "Ram Clear" ) |
| 279 | PORT_DIPSETTING( 0x80, DEF_STR( Off ) ) |
| 280 | PORT_DIPSETTING( 0x00, DEF_STR( On ) ) |
| 281 | PORT_DIPNAME( 0x40, 0x00, "Logic Door" ) |
| 282 | PORT_DIPSETTING( 0x00, DEF_STR( Off ) ) |
| 283 | PORT_DIPSETTING( 0x40, DEF_STR( On ) ) |
| 167 | 284 | INPUT_PORTS_END |
| 168 | 285 | |
| 169 | 286 | |
| 170 | 287 | WRITE_LINE_MEMBER(konendev_state::gcu_interrupt) |
| 171 | 288 | { |
| 172 | | m_maincpu->set_input_line(INPUT_LINE_IRQ0, state); |
| 289 | m_maincpu->set_input_line(INPUT_LINE_IRQ1, state); |
| 290 | m_maincpu->set_input_line(INPUT_LINE_IRQ3, state); |
| 173 | 291 | } |
| 174 | 292 | |
| 175 | 293 | |
| 294 | INTERRUPT_GEN_MEMBER(konendev_state::vbl_interrupt) |
| 295 | { |
| 296 | device.execute().set_input_line(INPUT_LINE_IRQ1, ASSERT_LINE); |
| 297 | device.execute().set_input_line(INPUT_LINE_IRQ3, ASSERT_LINE); |
| 298 | } |
| 176 | 299 | |
| 177 | 300 | static MACHINE_CONFIG_START( konendev, konendev_state ) |
| 178 | 301 | /* basic machine hardware */ |
| 179 | 302 | MCFG_CPU_ADD("maincpu", PPC403GCX, 32000000) // Clock unknown |
| 180 | 303 | MCFG_CPU_PROGRAM_MAP(konendev_map) |
| 304 | MCFG_CPU_VBLANK_INT_DRIVER("screen", konendev_state, vbl_interrupt) |
| 181 | 305 | |
| 182 | 306 | /* video hardware */ |
| 183 | 307 | MCFG_PALETTE_ADD_RRRRRGGGGGBBBBB("palette") |
| r249107 | r249108 | |
| 358 | 482 | DRIVER_INIT_MEMBER(konendev_state,enchlamp) |
| 359 | 483 | { |
| 360 | 484 | UINT32 *rom = (UINT32*)memregion("program")->base(); |
| 361 | | rom[0x24/4] = 0x00002743; // patch flash checksum for now |
| 485 | rom[0x24/4] = 0x00002743; // patch flash checksum for now |
| 486 | |
| 487 | // patch sound data checksums |
| 488 | rom[0x2d924/4] = 0x00000000; |
| 489 | rom[0x2d928/4] = 0x00000000; |
| 490 | rom[0x2d934/4] = 0x00000000; |
| 491 | rom[0x2d938/4] = 0x00000000; |
| 362 | 492 | |
| 363 | | rom[0] = 0xd43eb930; // new checksum for program rom |
| 493 | rom[0] = 0x5782b930; // new checksum for program rom |
| 364 | 494 | } |
| 365 | 495 | |
| 366 | 496 | // has a flash dump? |
trunk/src/mame/video/k057714.c
| r249107 | r249108 | |
| 332 | 332 | int li = ((j+y) * fb_pitch) + x; |
| 333 | 333 | UINT32 fbaddr0 = m_frame[0].base + li; |
| 334 | 334 | UINT32 fbaddr1 = m_frame[1].base + li; |
| 335 | | // UINT32 fbaddr2 = m_frame[2].base + li; |
| 335 | UINT32 fbaddr2 = m_frame[2].base + li; |
| 336 | 336 | // UINT32 fbaddr3 = m_frame[3].base + li; |
| 337 | 337 | |
| 338 | 338 | for (int i=0; i < width; i++) |
| 339 | 339 | { |
| 340 | 340 | UINT16 pix0 = vram16[fbaddr0 ^ NATIVE_ENDIAN_VALUE_LE_BE(1,0)]; |
| 341 | 341 | UINT16 pix1 = vram16[fbaddr1 ^ NATIVE_ENDIAN_VALUE_LE_BE(1,0)]; |
| 342 | | // UINT16 pix2 = vram16[fbaddr2 ^ NATIVE_ENDIAN_VALUE_LE_BE(1,0)]; |
| 342 | UINT16 pix2 = vram16[fbaddr2 ^ NATIVE_ENDIAN_VALUE_LE_BE(1,0)]; |
| 343 | 343 | // UINT16 pix3 = vram16[fbaddr3 ^ NATIVE_ENDIAN_VALUE_LE_BE(1,0)]; |
| 344 | 344 | |
| 345 | | if (pix0 & 0x8000) |
| 345 | d[i] = 0; |
| 346 | |
| 347 | if (pix2 & 0x8000) |
| 346 | 348 | { |
| 347 | | d[i] = pix0 & 0x7fff; |
| 349 | d[i] = pix2 & 0x7fff; |
| 348 | 350 | } |
| 349 | | else |
| 351 | if (pix1 & 0x8000) |
| 350 | 352 | { |
| 351 | 353 | d[i] = pix1 & 0x7fff; |
| 352 | 354 | } |
| 355 | if (pix0 & 0x8000) |
| 356 | { |
| 357 | d[i] = pix0 & 0x7fff; |
| 358 | } |
| 353 | 359 | |
| 354 | 360 | fbaddr0++; |
| 355 | 361 | fbaddr1++; |
| 356 | | // fbaddr2++; |
| 362 | fbaddr2++; |
| 357 | 363 | // fbaddr3++; |
| 358 | 364 | } |
| 359 | 365 | } |
| r249107 | r249108 | |
| 472 | 478 | if (sg > 0x1f) sg = 0x1f; |
| 473 | 479 | if (sb > 0x1f) sb = 0x1f; |
| 474 | 480 | |
| 475 | | vram16[fbaddr ^ NATIVE_ENDIAN_VALUE_LE_BE(1,0)] = (sr << 10) | (sg << 5) | sb | 0x8000; |
| 481 | vram16[fbaddr ^ NATIVE_ENDIAN_VALUE_LE_BE(1,0)] = (sr << 10) | (sg << 5) | sb | (pix & 0x8000); |
| 476 | 482 | } |
| 477 | 483 | } |
| 478 | 484 | } |
| r249107 | r249108 | |
| 480 | 486 | { |
| 481 | 487 | if (draw) |
| 482 | 488 | { |
| 483 | | vram16[fbaddr ^ NATIVE_ENDIAN_VALUE_LE_BE(1,0)] = pix | 0x8000; |
| 489 | vram16[fbaddr ^ NATIVE_ENDIAN_VALUE_LE_BE(1,0)] = pix; |
| 484 | 490 | } |
| 485 | 491 | } |
| 486 | 492 | |
| r249107 | r249108 | |
| 559 | 565 | // 0x00: -------- xxxxxxxx xxxxxxxx xxxxxxxx character data address in vram |
| 560 | 566 | |
| 561 | 567 | // 0x01: -------- -------- ------xx xxxxxxxx character x |
| 562 | | // 0x01: -------- ----xxxx xxxxxx-- -------- character y |
| 568 | // 0x01: -------- xxxxxxxx xxxxxx-- -------- character y |
| 563 | 569 | // 0x01: -------x -------- -------- -------- double height |
| 570 | // 0x01: -x------ -------- -------- -------- transparency enable |
| 564 | 571 | |
| 565 | 572 | // 0x02: xxxxxxxx xxxxxxxx -------- -------- color 0 |
| 566 | 573 | // 0x02: -------- -------- xxxxxxxx xxxxxxxx color 1 |
| r249107 | r249108 | |
| 569 | 576 | // 0x03: -------- -------- xxxxxxxx xxxxxxxx color 3 |
| 570 | 577 | |
| 571 | 578 | int x = cmd[1] & 0x3ff; |
| 572 | | int y = (cmd[1] >> 10) & 0x3ff; |
| 579 | int y = (cmd[1] >> 10) & 0x3fff; |
| 573 | 580 | UINT32 address = cmd[0] & 0xffffff; |
| 574 | 581 | UINT16 color[4]; |
| 575 | 582 | bool relative_coords = (cmd[0] & 0x10000000) ? true : false; |
| 576 | 583 | bool double_height = (cmd[1] & 0x01000000) ? true : false; |
| 584 | bool trans_enable = (cmd[1] & 0x40000000) ? true : false; |
| 577 | 585 | |
| 578 | 586 | if (relative_coords) |
| 579 | 587 | { |
| r249107 | r249108 | |
| 604 | 612 | for (int i=0; i < 8; i++) |
| 605 | 613 | { |
| 606 | 614 | int p = (line >> ((7-i) * 2)) & 3; |
| 607 | | vram16[(fbaddr+x+i) ^ NATIVE_ENDIAN_VALUE_LE_BE(1,0)] = color[p] | 0x8000; |
| 615 | bool draw = !trans_enable || (trans_enable && (color[p] & 0x8000)); |
| 616 | if (draw) |
| 617 | vram16[(fbaddr+x+i) ^ NATIVE_ENDIAN_VALUE_LE_BE(1,0)] = color[p] | 0x8000; |
| 608 | 618 | } |
| 609 | 619 | } |
| 610 | 620 | } |