MAME SVN History

199869 Revisions

r40533 Friday 28th August, 2015 at 16:57:43 UTC by Scott Stone
Commented MCFG_QUANTUM_TIME() entries in zaccaria.c driver and tested each game and noticed no ill effects. Money Money and Jack Rabbit now run over two times faster than before, overall. (nw)

[hash]	megadriv.xml x1_cass.xml
[src/emu/bus/centronics]	printer.c
[src/emu/machine]	68230pit.c 68230pit.h
[src/emu/sound]	c352.c c352.h
[src/mame/drivers]	namcofl.c namconb1.c namcond1.c namcos11.c namcos12.c namcos22.c namcos23.c zaccaria.c
[src/mess/drivers]	force68k.c mc1000.c
[src/mess/layout]	~~fccpu1.lay~~
[src/osd/modules/debugger/win]	debugviewinfo.c debugwininfo.c editwininfo.c
[src/osd/windows]	input.c output.c window.c winmain.c winutil.c winutil.h

trunk/hash/megadriv.xml
r249044	r249045
16204	16204	<info name="release" value="19920710"/>
16205	16205	<info name="alt_title" value="炎の闘球児ドッジ弾平"/>
16206	16206	<part name="cart" interface="megadriv_cart">
16207		<feature name="slot" value="rom_eeprom"/>
16208	16207	<dataarea name="rom" width="16" endianness="big" size="524288">
16209	16208	<rom name="mpr-14856.bin" size="524288" crc="630f07c6" sha1="ebdf20fd8aaeb3c7ec97302089b3330265118cf0" offset="0x000000"/>
16210	16209	</dataarea>
r249044	r249045
18271	18270	<info name="release" value="19941021"/>
18272	18271	<info name="alt_title" value="ロックマンメガワールド"/>
18273	18272	<part name="cart" interface="megadriv_cart">
18274		<feature name="slot" value="rom_sram"/>
18275	18273	<dataarea name="rom" width="16" endianness="big" size="2097152">
18276	18274	<rom name="rockman mega world (jpn) (alt).bin" size="2097152" crc="85c956ef" sha1="a435ac53589a29dbb655662c942daab425d3f6bd" offset="0x000000"/>
18277	18275	</dataarea>
18278		<dataarea name="sram" size="16384">
18279		</dataarea>
18280	18276	</part>
18281	18277	</software>
18282	18278
r249044	r249045
20366	20362	<info name="release" value="19911205"/>
20367	20363	<info name="alt_title" value="忍者武雷伝説"/>
20368	20364	<part name="cart" interface="megadriv_cart">
20369		<feature name="slot" value="rom_eeprom"/>
20370	20365	<dataarea name="rom" width="16" endianness="big" size="1048576">
20371	20366	<rom name="ninja burai densetsu (jpn).bin" size="1048576" crc="a8d828a0" sha1="9cc3419ca7ecaf0d106aa896ffc0266c7145fff7" offset="0x000000"/>
20372	20367	</dataarea>

trunk/hash/x1_cass.xml
r249044	r249045
12	12
13	13	<softwarelist name="x1_cass" description="Sharp X1 cassettes">
14	14
15		<software name="alamein">
16		<description>El Alamein</description>
17		<year>1983</year>
18		<publisher>ポニカ (Pony Canyon)</publisher>
19		<info name="alt_title" value="エル・アラメイン"/>
20		<info name="usage" value="In BASIC, type LOAD and then RUN"/>
21		<sharedfeat name="requirement" value="x1_flop:tapbas"/>
22		<part name="cass" interface="x1_cass">
23		<dataarea name="side1" size="12742140">
24		<rom name="alamein.wav" size="12742140" crc="04e00f60" sha1="42f3ef356fdb67ddd0fbdb57e473c23d267f9bf4" offset="0" />
25		</dataarea>
26		</part>
27		</software>
28
29	15	<software name="blckonyx" supported="no">
30	16	<description>The Black Onyx</description>
31	17	<year>1985</year>
r249044	r249045
90	76	</dataarea>
91	77	</part>
92	78	</software>
93
94		<software name="cball">
95		<description>Cannon Ball</description>
96		<year>1983</year>
97		<publisher>ハドソン (Hudson Soft)</publisher>
98		<info name="alt_title" value="キャノンボール"/>
99		<part name="cass" interface="x1_cass">
100		<dataarea name="side1" size="4857558">
101		<rom name="cball.wav" size="4857558" crc="4405cf21" sha1="769a43d97f69b5d72347ca8b72547e464b9d059b" offset="0" />
102		</dataarea>
103		</part>
104		</software>
105	79
106	80	<software name="cprowsp">
107	81	<description>Champion ProWres Special</description>
r249044	r249045
322	296	</dataarea>
323	297	</part>
324	298	</software>
325
326		<software name="machgjoe">
327		<description>Ginkou Goutou - Machinegun Joe vs. the Mafia</description>
328		<year>1983</year>
329		<publisher>ハドソン (Hudson Soft)</publisher>
330		<info name="alt_title" value="銀行強盗マシンガンジョー VS ザ・マフィア"/>
331		<part name="cass" interface="x1_cass">
332		<dataarea name="side1" size="15591932">
333		<rom name="machgjoe.wav" size="15591932" crc="3769199a" sha1="81614c317f432055f2c5fdcce51438de9fbdad7f" offset="0" />
334		</dataarea>
335		</part>
336		</software>
337	299
338	300	<software name="mappy">
339	301	<description>Mappy</description>

trunk/src/emu/bus/centronics/printer.c
r249044	r249045
99	99	output_busy(m_busy);
100	100	output_fault(1);
101	101	output_ack(1);
102		output_select(1);
103	102	}
104	103
105	104	/*-------------------------------------------------

trunk/src/emu/machine/68230pit.c
r249044	r249045
1	1	// license:BSD-3-Clause
2	2	// copyright-holders:Joakim Larsson Edstr??m
3	3	/**********************************************************************
4		*
5		* Motorola MC68230 PI/T Parallell Interface and Timer
6		*
7		* Revisions
8		* 2015-07-15 JLE initial
9		*
10		* Todo
11		* - Add clock and timers
12		* - Add all missing registers
13		* - Add configuration
14		**********************************************************************/
15	4
16		~~#inc~~l~~ude~~ "68230pit~~.h"~~
	5	Motorola MC68230 PI/T Parallell Interface and Timer
17	6
18		#define LOG(x) /* x */
	7	Revisions
	8	2015-07-15 JLE initial
19	9
20		//**************************************************************************
21		// DEVICE TYPE DEFINITIONS
22		//**************************************************************************
	10	Todo
	11	- Add clock and timers
	12	- Add all missing registers
	13	- Add configuration
	14	**********************************************************************/
23	15
24		const device_type PIT68230 = &device_creator<pit68230_device>;
	16	/*
	17	Force CPU-1 init sequence
	18	0801EA 0E0000 W 0000 PGCR data_w: 0000 -> 0000 & 00ff
	19	0801EA 0E0002 W 0000 PSRR data_w: 0000 -> 0001 & 00ff
	20	0801EA 0E0004 W FFFF PADDR data_w: 00ff -> 0002 & 00ff
	21	0801EA 0E0006 W 0000 PBDDR data_w: 0000 -> 0003 & 00ff
	22	0801F0 0E000C W 6060 PACR data_w: 0060 -> 0006 & 00ff
	23	0801F6 0E000E W A0A0 PBCR data_w: 00a0 -> 0007 & 00ff
	24	0801FC 0E0000 W 3030 PGCR data_w: 0030 -> 0000 & 00ff
	25	080202 0E000E W A8A8 PBCR data_w: 00a8 -> 0007 & 00ff
	26	080210 0E000E W A0A0 PBCR data_w: 00a0 -> 0007 & 00ff
25	27
26		//-------------------------------------------------
27		// pit68230_device - constructors
28		//-------------------------------------------------
29		pit68230_device::pit68230_device(const machine_config &mconfig, device_type type, const char name, const char tag, device_t owner, UINT32 clock, UINT32 variant, const char shortname, const char *source)
30		: device_t (mconfig, type, name, tag, owner, clock, shortname, source),
31		device_execute_interface (mconfig, *this)
32		, m_icount (0)
33		, m_write_pa (*this)
34		, m_write_h2 (*this)
35		{
36		}
	28	Force CPU-1 after one keypress in terminal
	29	081DC0 0E000C W 6868 PACR
	30	081DC8 0E000C W 6060 PACR
	31	*/
37	32
38	33
39		pit68230_device::pit68230_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
40		: device_t (mconfig, PIT68230, "PIT68230", tag, owner, clock, "pit68230", __FILE__),
41		device_execute_interface (mconfig, *this)
42		, m_icount (0)
43		, m_write_pa (*this)
44		, m_write_h2 (*this)
45		{
46		}
	34	#include "emu.h"
	35	#include "68230pit.h"
47	36
48		//-------------------------------------------------
49		// device_start - device-specific startup
50		//-------------------------------------------------
51		void pit68230_device::device_start ()
52		{
53		LOG (logerror ("PIT68230 device started\n"));
54		m_icountptr = &m_icount;
	37	/***************************************************************************
	38	IMPLEMENTATION
	39	***************************************************************************/
55	40
56		// resolve callbacks
57		m_write_pa.resolve_safe ();
58		m_write_h2.resolve_safe ();
59		}
	41	// device type definition
	42	const device_type PIT68230 = &device_creator<pit68230_device>;
60	43
61	44	//-------------------------------------------------
62		// device~~_reset~~ - ~~devi~~ce-s~~pecific~~ r~~ese~~t
	45	// pit68230_device - constructor
63	46	//-------------------------------------------------
64		void pit68230_device::device_reset ()
	47
	48	pit68230_device::pit68230_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
	49	: device_t(mconfig, PIT68230, "Motorola 68230 PI/T", tag, owner, clock, "pit68230", __FILE__)
65	50	{
66		LOG (logerror ("PIT68230 device reseted\n"));
67		m_pgcr = 0;
68		m_psrr = 0;
69		m_paddr = 0;
70		m_pbddr = 0;
71		m_pcddr = 0;
72		m_pacr = 0; m_write_h2 (m_pacr);
73		m_pbcr = 0;
74		m_padr = 0; m_write_pa ((offs_t)0, m_padr); // TODO: check PADDR
75		m_pbdr = 0;
76		m_psr = 0;
77	51	}
78	52
79		//-------------------------------------------------
80		// device_timer - handler timer events
81		//-------------------------------------------------
82		void pit68230_device::device_timer (emu_timer &timer, device_timer_id id, INT32 param, void *ptr)
	53	void pit68230_device::device_start()
83	54	{
	55	printf("PIT68230 device started\n");
84	56	}
85	57
86		void pit68230_device::h1_set (~~UINT8 state~~)
	58	void pit68230_device::device_reset()
87	59	{
88		LOG (logerror ("h1_set %d @ m_psr %2x => ", state, m_psr));
89		if (state) m_psr \|= 1; else m_psr &= ~1;
90		LOG (logerror ("%02x %lld\n", m_psr, machine ().firstcpu->total_cycles ()));
	60	printf("PIT68230 device reseted\n");
	61	m_pgcr = 0;
	62	m_psrr = 0;
	63	m_paddr = 0;
	64	m_pbddr = 0;
	65	m_pcddr = 0;
	66	m_pacr = 0;
	67	m_pbcr = 0;
	68	m_padr = 0;
	69	m_pbdr = 0;
	70	m_psr = 0;
91	71	}
92	72
93		~~void~~ pit68230_device::~~por~~tb_~~setbit~~ ~~(UINT8 bit, UINT8 state~~)
	73	WRITE8_MEMBER( pit68230_device::data_w )
94	74	{
95		LOG (logerror ("portb_setbit %d/%d @ m_pbdr %2x => ", bit, state, m_pbdr));
96		if (state) m_pbdr \|= (1 << bit); else m_pbdr &= ~(1 << bit);
97		LOG (logerror ("%02x %lld\n", m_pbdr, machine ().firstcpu->total_cycles ()));
	75	printf("data_w: %04x -> ", data);
	76	switch (offset)
	77	{
	78	case PIT_68230_PGCR:
	79	printf("PGCR");
	80	m_pgcr = data;
	81	break;
	82	case PIT_68230_PSRR:
	83	printf("PSRR");
	84	m_psrr = data;
	85	break;
	86	case PIT_68230_PADDR:
	87	printf("PADDR");
	88	m_paddr = data;
	89	break;
	90	case PIT_68230_PBDDR:
	91	printf("PBDDR");
	92	m_pbddr = data;
	93	break;
	94	case PIT_68230_PACR:
	95	printf("PACR");
	96	m_pacr = data;
	97	break;
	98	case PIT_68230_PBCR:
	99	printf("PBCR");
	100	m_pbcr = data;
	101	break;
	102	case PIT_68230_PADR:
	103	printf("PADR");
	104	m_padr = data;
	105	break;
	106	case PIT_68230_PSR:
	107	printf("PSR");
	108	m_padr = data;
	109	break;
	110	default:
	111	printf("unhandled register %02x", offset);
	112	}
	113	printf("\n");
98	114	}
99	115
100		//-------------------------------------------------
101		// execute_run -
102		//-------------------------------------------------
103		void pit68230_device::execute_run ()
	116	READ8_MEMBER( pit68230_device::data_r )
104	117	{
105		do {
106		synchronize ();
	118	UINT8 data = 0;
107	119
108		m_icount--;
109		} while (m_icount > 0);
110		}
	120	printf("data_r: ");
	121	switch (offset)
	122	{
	123	case PIT_68230_PGCR:
	124	printf("PGCR");
	125	data = m_pgcr;
	126	break;
	127	case PIT_68230_PSRR:
	128	printf("PSRR");
	129	data = m_psrr;
	130	break;
	131	case PIT_68230_PADDR:
	132	printf("PADDR");
	133	data = m_paddr;
	134	break;
	135	case PIT_68230_PBDDR:
	136	printf("PBDDR");
	137	data = m_pbddr;
	138	break;
	139	case PIT_68230_PACR:
	140	printf("PACR");
	141	data = m_pacr;
	142	break;
	143	case PIT_68230_PBCR:
	144	printf("PBCR");
	145	data = m_pbcr;
	146	break;
	147	case PIT_68230_PADR:
	148	printf("PADR");
	149	data = m_padr;
	150	break;
	151	case PIT_68230_PBDR:
	152	/* 4.6.2. PORT B DATA REGISTER (PBDR). The port B data register is a holding register for moving data
	153	to and from port B pins. The port B data direction register determines whether each pin is an input (zero)
	154	or an output (one). This register is readable and writable at all times. Depending on the chosen mode/submode,
	155	reading or writing may affect the double-buffered handshake mechanism. The port B data register is not affected
	156	by the assertion of the RESET pin. PB0-PB7 sits on pins 17-24 on a 48 pin DIP package */
	157	printf("PBDR");
	158	data = m_pbdr;
	159	// data = (m_pbdr & 0xfc) \| 1; // CPU-1 centronics interface expects to see 2 lowest bits equal 1 for printer
	160	break;
	161	case PIT_68230_PSR:
	162	printf("PSR");
	163	data = m_psr;
	164	// data = m_psr \| 1; // CPU-1 centronics interface expects status to be non zero
	165	break;
	166	default:
	167	printf("unhandled register %02x", offset);
	168	data = 0;
	169	}
	170	printf("\n");
111	171
112		LOG (static INT32 ow_cnt = 0);
113		LOG (static INT32 ow_data = 0);
114		LOG (static INT32 ow_ofs = 0);
115
116		WRITE8_MEMBER (pit68230_device::write){
117		switch (offset) {
118		case PIT_68230_PGCR:
119		m_pgcr = data;
120		break;
121
122		case PIT_68230_PSRR:
123		m_psrr = data;
124		break;
125
126		case PIT_68230_PADDR:
127		m_paddr = data;
128		break;
129
130		case PIT_68230_PBDDR:
131		m_pbddr = data;
132		break;
133
134		case PIT_68230_PACR:
135		m_pacr = data;
136		// callbacks
137		/*PACR in Mode 0
138		* 5 43 H2 Control in Submode 00 && 01
139		* ------------------------------------
140		* 0 XX Input pin - edge-sensitive status input, H2S is set on an asserted edge.
141		* 1 00 Output pin - negated, H2S is always clear.
142		* 1 01 Output pin - asserted, H2S is always clear.
143		* 1 10 Output pin - interlocked input handshake protocol, H2S is always clear.
144		* 1 11 Output pin - pulsed input handshake protocol, H2S is always clear.
145		*
146		* 5 43 H2 Control in Submode 1x
147		* ------------------------------------
148		* 0 XX Input pin - edge-sensitive status input, H2S is set on an asserted edge.
149		* 1 X0 Output pin - negated, H2S is always cleared.
150		* 1 X1 Output pin - asserted, H2S is always cleared.
151		*/
152		m_write_h2 (m_pacr & 0x08 ? 1 : 0); // TODO: Check mode and submodes
153		break;
154
155		case PIT_68230_PBCR:
156		m_pbcr = data;
157		break;
158
159		case PIT_68230_PADR:
160		m_padr = data;
161		// callbacks
162		m_write_pa ((offs_t)0, m_padr); // TODO: check PADDR
163		break;
164
165		case PIT_68230_PSR:
166		m_psr = data;
167		break;
168
169		default:
170		LOG (logerror ("unhandled register %02x", offset));
171		}
172
173		LOG (if (offset != ow_ofs \|\| data != ow_data \|\| ow_cnt >= 1000) {
174		logerror ("\npit68230_device::write: previous identical operation performed %02x times\n", ow_cnt);
175		ow_cnt = 0;
176		ow_data = data;
177		ow_ofs = offset;
178		logerror ("pit68230_device::write: offset=%02x data=%02x %lld\n", ow_ofs, ow_data, machine ().firstcpu->total_cycles ());
179		}
180		else
181		ow_cnt++; )
	172	return data;
182	173	}
183
184		LOG (static INT32 or_cnt = 0);
185		LOG (static INT32 or_data = 0);
186		LOG (static INT32 or_ofs = 0);
187
188		READ8_MEMBER (pit68230_device::read){
189		UINT8 data = 0;
190
191		switch (offset) {
192		case PIT_68230_PGCR:
193		data = m_pgcr;
194		break;
195
196		case PIT_68230_PSRR:
197		data = m_psrr;
198		break;
199
200		case PIT_68230_PADDR:
201		data = m_paddr;
202		break;
203
204		case PIT_68230_PBDDR:
205		data = m_pbddr;
206		break;
207
208		case PIT_68230_PACR:
209		data = m_pacr;
210		break;
211
212		case PIT_68230_PBCR:
213		data = m_pbcr;
214		break;
215
216		case PIT_68230_PADR:
217		data = m_padr;
218		break;
219
220		case PIT_68230_PBDR:
221		/* 4.6.2. PORT B DATA REGISTER (PBDR). The port B data register is a holding
222		* register for moving data to and from port B pins. The port B data direction
223		* register determines whether each pin is an input (zero) or an output (one).
224		* This register is readable and writable at all times. Depending on the chosen
225		* mode/submode, reading or writing may affect the double-buffered handshake
226		* mechanism. The port B data register is not affected by the assertion of the
227		* RESET pin. PB0-PB7 sits on pins 17-24 on a 48 pin DIP package */
228		data = m_pbdr;
229		break;
230
231		case PIT_68230_PSR:
232		/* 4.8. PORT STATUS REGISTER (PSR) The port status register contains information about
233		* handshake pin activity. Bits 7-4 show the instantaneous level of the respective handshake
234		* pin, and are independent of the handshake pin sense bits in the port general control
235		* register. Bits 3-0 are the respective status bits referred to throughout this document.
236		* Their interpretation depends on the programmed mode/submode of the PI/T. For bits
237		* 3-0 a one is the active or asserted state. */
238		data = m_psr;
239		break;
240
241		default:
242		LOG (logerror ("unhandled register %02x", offset));
243		data = 0;
244		}
245
246		LOG (if (offset != or_ofs \|\| data != or_data \|\| or_cnt >= 1000) {
247		logerror ("\npit68230_device::read: previous identical operation performed %02x times\n", or_cnt);
248		or_cnt = 0;
249		or_data = data;
250		or_ofs = offset;
251		logerror ("pit68230_device::read: offset=%02x data=%02x %lld\n", or_ofs, or_data, machine ().firstcpu->total_cycles ());
252		}
253		else
254		or_cnt++; )
255
256		return data;
257		}

trunk/src/emu/machine/68230pit.h
r249044	r249045
1	1	// license:BSD-3-Clause
2	2	// copyright-holders:Joakim Larsson Edstr??m
3	3	/**********************************************************************
4		*
5		* Motorola MC68230 PI/T Parallell Interface and Timer
6		*
7		* _____ _____
8		* D5 1 \|* \_/ \| 48 D4
9		* D6 2 \| \| 47 D3
10		* D7 3 \| \| 46 D2
11		* PA0 4 \| \| 45 D1
12		* PA1 5 \| \| 44 D0
13		* PA2 6 \| \| 43 R/W*
14		* PA3 7 \| \| 42 DTACK*
15		* PA4 8 \| \| 41 CS*
16		* PA5 9 \| \| 40 CLK
17		* PA6 10 \| \| 39 RESET*
18		* PA7 11 \| \| 38 VSS
19		* Vcc 12 \| TS68230 \| 37 PC7/TIACK*
20		* H1 13 \| SC87845 \| 36 PC6/PIACK*
21		* H2 14 \| \| 35 PC5/PIRQ*
22		* H3 15 \| \| 34 PC4/DMAREQ*
23		* H4 16 \| \| 33 PC3/TOUT
24		* PB0 17 \| \| 32 PC2/TIN
25		* PB1 18 \| \| 31 PC1
26		* PB2 19 \| \| 30 PC0
27		* PB3 20 \| \| 29 RS1
28		* PB4 21 \| \| 28 RS2
29		* PB5 22 \| \| 27 RS3
30		* PB6 23 \| \| 26 RS4
31		* PB7 24 \|_____________\| 25 RS5
32		*
33		**********************************************************************/
34	4
	5	Motorola MC68230 PI/T Parallell Interface and Timer
	6
	7	**********************************************************************/
35	8	#pragma once
36	9
37	10	#ifndef __68230PIT_H__
r249044	r249045
39	12
40	13	#include "emu.h"
41	14
42		//**************************************************************************
43		// INTERFACE CONFIGURATION MACROS
44		//**************************************************************************
45
46		#define MCFG_PIT68230_PA_OUTPUT_CALLBACK(_write) \
47		devcb = &pit68230_device::set_pa_wr_callback (*device, DEVCB_ ## _write);
48
49		#define MCFG_PIT68230_PB_OUTPUT_CALLBACK(_write) \
50		devcb = &pit68230_device::set_pb_wr_callback (*device, DEVCB_ ## _write);
51
52		#define MCFG_PIT68230_H2_CALLBACK(_write) \
53		devcb = &pit68230_device::set_h2_wr_callback (*device, DEVCB_ ## _write);
54
55	15	/*-----------------------------------------------------------------------
56		* Registers RS1-RS5 R/W Description
57		* -------------------------------------------------------------------------*/
	16	Registers RS1-RS5 R/W Description
	17	-------------------------------------------------------------------------*/
58	18	#define PIT_68230_PGCR 0x00 /* RW Port General Control register */
59	19	#define PIT_68230_PSRR 0x01 /* RW Port Service Request register */
60	20	#define PIT_68230_PADDR 0x02 /* RW Port A Data Direction register */
r249044	r249045
82	42	//**************************************************************************
83	43	// TYPE DEFINITIONS
84	44	//**************************************************************************
85		class pit68230_device : public device_t~~, public device_execute_interface~~
	45	class pit68230_device : public device_t
86	46	{
87	47	public:
88		// construction/destruction
89		pit68230_device(const machine_config &mconfig, device_type type, const char name, const char tag, device_t owner, UINT32 clock, UINT32 variant, const char shortname, const char *source);
90		pit68230_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
91		template<class _Object> static devcb_base &set_pa_wr_callback (device_t &device, _Object object)
92		{
93		return downcast<pit68230_device &>(device).m_write_pa.set_callback (object);
94		}
95		template<class _Object> static devcb_base &set_h2_wr_callback (device_t &device, _Object object)
96		{
97		return downcast<pit68230_device &>(device).m_write_h2.set_callback (object);
98		}
	48	// construction/destruction
	49	pit68230_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
	50	DECLARE_WRITE8_MEMBER( data_w );
	51	DECLARE_READ8_MEMBER( data_r );
99	52
100		DECLARE_WRITE8_MEMBER (write);
101		DECLARE_READ8_MEMBER (read);
102
103		void h1_set (UINT8 state);
104		void portb_setbit (UINT8 bit, UINT8 state);
105
106	53	protected:
107		// device-level overrides
108		virtual void device_start ();
109		virtual void device_reset ();
110		virtual void device_timer (emu_timer &timer, device_timer_id id, int param, void *ptr);
111		virtual void execute_run ();
112		int m_icount;
113		devcb_write8 m_write_pa;
114		devcb_write_line m_write_h2;
	54	// device-level overrides
	55	virtual void device_start();
	56	virtual void device_reset();
115	57
116		// peripheral ports
117		UINT8 m_pgcr; // Port General Control register
118		UINT8 m_psrr; // Port Service Request register
119		UINT8 m_paddr; // Port A Data Direction register
120		UINT8 m_pbddr; // Port B Data Direction register
121		UINT8 m_pcddr; // Port C Data Direction register
122		UINT8 m_pacr; // Port A Control register
123		UINT8 m_pbcr; // Port B Control register
124		UINT8 m_padr; // Port A Data register
125		UINT8 m_pbdr; // Port B Data register
126		UINT8 m_psr; // Port Status Register
	58	private:
	59	UINT8 m_pgcr; // Port General Control register
	60	UINT8 m_psrr; // Port Service Request register
	61	UINT8 m_paddr; // Port A Data Direction register
	62	UINT8 m_pbddr; // Port B Data Direction register
	63	UINT8 m_pcddr; // Port C Data Direction register
	64	UINT8 m_pacr; // Port A Control register
	65	UINT8 m_pbcr; // Port B Control register
	66	UINT8 m_padr; // Port A Data register
	67	UINT8 m_pbdr; // Port B Data register
	68	UINT8 m_psr; // Port Status Register
127	69	};
128	70
	71
129	72	// device type definition
130	73	extern const device_type PIT68230;
131		#endif /* __68230PIT_H__ */
	74
	75	#endif // __68230PIT__

trunk/src/emu/sound/c352.c
r249044	r249045
13	13	Supports 8-bit linear and 8-bit muLaw samples
14	14	Output: digital, 16 bit, 4 channels
15	15	Output sample rate is the input clock / (288 * 2).
16
17		superctr: The clock divider appears to be configurable for each system.
18		Below is a list of the divider values followed by the systems that use it.
19
20		* 228: System 11.
21		* 288: System 22, Super 22, NB-1/2, ND-1, FL.
22		* 296: System 23, Super 23.
23		* 332: System 12.
24	16	*/
25	17
26	18	#include "emu.h"
r249044	r249045
476	468
477	469	void c352_device::device_start()
478	470	{
479		int i;
	471	int i, divider;
480	472	double x_max = 32752.0;
481	473	double y_max = 127.0;
482	474	double u = 10.0;
r249044	r249045
484	476	// find our direct access
485	477	m_direct = &space().direct();
486	478
487		m_sample_rate_base = clock() / m_divider;
	479	switch(m_divider)
	480	{
	481	case C352_DIVIDER_228:
	482	divider=228;
	483	break;
	484	case C352_DIVIDER_288:
	485	default:
	486	divider=288;
	487	break;
	488	case C352_DIVIDER_332:
	489	divider=332;
	490	break;
	491	}
488	492
	493	m_sample_rate_base = clock() / divider;
	494
489	495	m_stream = machine().sound().stream_alloc(*this, 0, 4, m_sample_rate_base);
490	496
491	497	// generate mulaw table for mulaw format samples

trunk/src/emu/sound/c352.h
r249044	r249045
6	6	#define __C352_H__
7	7
8	8	//**************************************************************************
	9	// CONSTANTS
	10	//**************************************************************************
	11
	12	enum
	13	{
	14	C352_DIVIDER_228 = 0,
	15	C352_DIVIDER_288 = 1,
	16	C352_DIVIDER_332 = 2
	17	};
	18
	19	//**************************************************************************
9	20	// INTERFACE CONFIGURATION MACROS
10	21	//**************************************************************************
11	22

trunk/src/mame/drivers/namcofl.c
r249044	r249045
610	610	MCFG_VIDEO_START_OVERRIDE(namcofl_state,namcofl)
611	611
612	612	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
613		MCFG_C352_ADD("c352", 48384000/2, 288)
	613	MCFG_C352_ADD("c352", 48384000/2, C352_DIVIDER_288)
614	614	MCFG_SOUND_ROUTE(0, "rspeaker", 1.00)
615	615	MCFG_SOUND_ROUTE(1, "lspeaker", 1.00)
616	616	MCFG_SOUND_ROUTE(2, "rspeaker", 1.00)

trunk/src/mame/drivers/namconb1.c
r249044	r249045
1126	1126	MCFG_VIDEO_START_OVERRIDE(namconb1_state,namconb1)
1127	1127
1128	1128	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
1129		MCFG_C352_ADD("c352", MASTER_CLOCK/2, 288)
	1129	MCFG_C352_ADD("c352", MASTER_CLOCK/2, C352_DIVIDER_288)
1130	1130	MCFG_SOUND_ROUTE(0, "rspeaker", 1.00)
1131	1131	MCFG_SOUND_ROUTE(1, "lspeaker", 1.00)
1132	1132	MCFG_SOUND_ROUTE(2, "rspeaker", 1.00)
r249044	r249045
1163	1163	MCFG_VIDEO_START_OVERRIDE(namconb1_state,namconb2)
1164	1164
1165	1165	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
1166		MCFG_C352_ADD("c352", MASTER_CLOCK/2, 288)
	1166	MCFG_C352_ADD("c352", MASTER_CLOCK/2, C352_DIVIDER_288)
1167	1167	MCFG_SOUND_ROUTE(0, "rspeaker", 1.00)
1168	1168	MCFG_SOUND_ROUTE(1, "lspeaker", 1.00)
1169	1169	MCFG_SOUND_ROUTE(2, "rspeaker", 1.00)

trunk/src/mame/drivers/namcond1.c
r249044	r249045
307	307	/* sound hardware */
308	308	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
309	309
310		MCFG_C352_ADD("c352", XTAL_49_152MHz/2, 288)
	310	MCFG_C352_ADD("c352", XTAL_49_152MHz/2, C352_DIVIDER_288)
311	311	MCFG_SOUND_ROUTE(0, "rspeaker", 1.00)
312	312	MCFG_SOUND_ROUTE(1, "lspeaker", 1.00)
313	313	MCFG_SOUND_ROUTE(2, "rspeaker", 1.00)

trunk/src/mame/drivers/namcos11.c
r249044	r249045
571	571
572	572	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
573	573
574		MCFG_C352_ADD("c352", 20013200, 228)
	574	MCFG_C352_ADD("c352", 20013200, C352_DIVIDER_228)
575	575	MCFG_SOUND_ROUTE(0, "rspeaker", 1.00)
576	576	MCFG_SOUND_ROUTE(1, "lspeaker", 1.00)
577	577	MCFG_SOUND_ROUTE(2, "rspeaker", 1.00)

trunk/src/mame/drivers/namcos12.c
r249044	r249045
1622	1622	/* sound hardware */
1623	1623	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
1624	1624
1625		MCFG_C352_ADD("c352", 29168000, 332)
	1625	MCFG_C352_ADD("c352", 29168000, C352_DIVIDER_332)
1626	1626	MCFG_SOUND_ROUTE(0, "rspeaker", 1.00)
1627	1627	MCFG_SOUND_ROUTE(1, "lspeaker", 1.00)
1628	1628	MCFG_SOUND_ROUTE(2, "rspeaker", 1.00)

trunk/src/mame/drivers/namcos22.c
r249044	r249045
3781	3781	/* sound hardware */
3782	3782	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
3783	3783
3784		MCFG_C352_ADD("c352", SS22_MASTER_CLOCK/2, 288)
	3784	MCFG_C352_ADD("c352", SS22_MASTER_CLOCK/2, C352_DIVIDER_288)
3785	3785	MCFG_SOUND_ROUTE(0, "rspeaker", 1.00)
3786	3786	MCFG_SOUND_ROUTE(1, "lspeaker", 1.00)
3787	3787	MCFG_SOUND_ROUTE(2, "rspeaker", 1.00)
r249044	r249045
3830	3830	/* sound hardware */
3831	3831	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
3832	3832
3833		MCFG_C352_ADD("c352", SS22_MASTER_CLOCK/2, 288)
	3833	MCFG_C352_ADD("c352", SS22_MASTER_CLOCK/2, C352_DIVIDER_288)
3834	3834	MCFG_SOUND_ROUTE(0, "rspeaker", 1.00)
3835	3835	MCFG_SOUND_ROUTE(1, "lspeaker", 1.00)
3836	3836	MCFG_SOUND_ROUTE(2, "rspeaker", 1.00)

trunk/src/mame/drivers/namcos23.c
r249044	r249045
1247	1247	#define JVSCLOCK (XTAL_14_7456MHz)
1248	1248	#define H8CLOCK (16737350) /* from 2061 */
1249	1249	#define BUSCLOCK (167373502) / 33MHz CPU bus clock / input */
1250		#define C352CLOCK (25992000) /* measured at 25.992MHz from 2061 pin 9 */
1251		#define C352DIV (296)
	1250	#define C352CLOCK (25992000) /* measured at 25.992MHz from 2061 pin 9 (System 12 uses a divider of 332) */
1252	1251	#define VSYNC1 (59.8824)
1253	1252	#define VSYNC2 (59.915)
1254	1253	#define HSYNC (16666150)
r249044	r249045
3321	3320	/* sound hardware */
3322	3321	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
3323	3322
3324		MCFG_C352_ADD("c352", C352CLOCK, C352DIV)
	3323	MCFG_C352_ADD("c352", C352CLOCK, C352_DIVIDER_332)
3325	3324	MCFG_SOUND_ROUTE(0, "rspeaker", 1.00)
3326	3325	MCFG_SOUND_ROUTE(1, "lspeaker", 1.00)
3327	3326	MCFG_SOUND_ROUTE(2, "rspeaker", 1.00)
r249044	r249045
3390	3389	/* sound hardware */
3391	3390	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
3392	3391
3393		MCFG_C352_ADD("c352", C352CLOCK, C352DIV)
	3392	MCFG_C352_ADD("c352", C352CLOCK, C352_DIVIDER_332)
3394	3393	MCFG_SOUND_ROUTE(0, "rspeaker", 1.00)
3395	3394	MCFG_SOUND_ROUTE(1, "lspeaker", 1.00)
3396	3395	MCFG_SOUND_ROUTE(2, "rspeaker", 1.00)
r249044	r249045
3470	3469	/* sound hardware */
3471	3470	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
3472	3471
3473		MCFG_C352_ADD("c352", C352CLOCK, C352DIV)
	3472	MCFG_C352_ADD("c352", C352CLOCK, C352_DIVIDER_332)
3474	3473	MCFG_SOUND_ROUTE(0, "rspeaker", 1.00)
3475	3474	MCFG_SOUND_ROUTE(1, "lspeaker", 1.00)
3476	3475	MCFG_SOUND_ROUTE(2, "rspeaker", 1.00)

trunk/src/mame/drivers/zaccaria.c
r249044	r249045
506	506	MCFG_CPU_ADD("maincpu", Z80,XTAL_18_432MHz/6) /* verified on pcb */
507	507	MCFG_CPU_PROGRAM_MAP(main_map)
508	508	MCFG_CPU_VBLANK_INT_DRIVER("screen", zaccaria_state, vblank_irq)
509		MCFG_QUANTUM_TIME(attotime::from_hz(1000000))
	509	// MCFG_QUANTUM_TIME(attotime::from_hz(1000000))
510	510
511	511	MCFG_CPU_ADD("audiocpu", M6802,XTAL_3_579545MHz) /* verified on pcb */
512	512	MCFG_CPU_PROGRAM_MAP(sound_map_1)
513	513	MCFG_CPU_PERIODIC_INT_DRIVER(zaccaria_state, cb1_toggle, (double)XTAL_3_579545MHz/4096)
514		MCFG_QUANTUM_TIME(attotime::from_hz(1000000))
	514	// MCFG_QUANTUM_TIME(attotime::from_hz(1000000))
515	515
516	516	MCFG_CPU_ADD("audio2", M6802,XTAL_3_579545MHz) /* verified on pcb */
517	517	MCFG_CPU_PROGRAM_MAP(sound_map_2)
518		MCFG_QUANTUM_TIME(attotime::from_hz(1000000))
	518	// MCFG_QUANTUM_TIME(attotime::from_hz(1000000))
519	519
520	520	MCFG_DEVICE_ADD("ppi8255", I8255A, 0)
521	521	MCFG_I8255_IN_PORTA_CB(IOPORT("P1"))

trunk/src/mess/drivers/force68k.c
r249044	r249045
1	1	// license:BSD-3-Clause
2	2	// copyright-holders:Joakim Larsson Edstr??m
3	3	/***************************************************************************
4		*
5		* Force SYS68K CPU-1/CPU-6 VME SBC drivers, initially based on the 68ksbc.c
6		*
7		* 13/06/2015
8		*
9		* The info found on the links below is for a later revisions of the board I have
10		* but it is somewhat compatible so I got the system ROM up and running in terminal.
11		* My CPU-1 board has proms from 1983 and the PCB has no rev markings so probably
12		* the original or a very early design. The board real estate differs from the later
13		* CPU-1:s I found pictures of but has the same main chips and functions.
14		*
15		* http://bitsavers.trailing-edge.com/pdf/forceComputers/1988_Force_VMEbus_Products.pdf
16		* http://www.artisantg.com/info/P_wUovN.pdf
17		*
18		* Some info from those documents:
19		*
20		* Address Map
21		* ----------------------------------------------------------
22		* Address Range Description
23		* ----------------------------------------------------------
24		* 000 000 - 000 007 Initialisation vectors from system EPROM
25		* 000 008 - 01F FFF Dynamic RAM on CPU-1 B
26		* 000 008 - 07F FFF Dynamic RAM on CPU-1 D
27		* 080 008 - 09F FFF SYSTEM EPROM Area
28		* OAO 000 - OBF FFF USER EPROMArea
29		* 0C0 041 - 0C0 043 ACIA (P3) Host
30		* 0C0 080 - 0C0 082 ACIA (P4) Terminal
31		* 0C0 101 - 0C0 103 ACIA (P5) Remote device (eg serial printer)
32		* 0C0 401 - 0C0 42F RTC
33		* OEO 001 - 0E0 035 PI/T (eg centronics printer)
34		* OEO 200 - 0E0 2FF FPU
35		* OEO 300 - 0E0 300 Reset Off
36		* OEO 380 - 0E0 380 Reset On
37		* 100 000 - FEF FFF VMEbus addresses (A24)
38		* FFO 000 - FFF FFF VMEbus Short I/O (A16)
39		* ----------------------------------------------------------
40		*
41		* Interrupt sources
42		* ----------------------------------------------------------
43		* Description Device Lvl IRQ VME board
44		* /Board Vector Address
45		* ----------------------------------------------------------
46		* On board Sources
47		* ABORT Switch 7 31
48		* Real Time Clock (RTC) 58167A 6 30
49		* Parallel/Timer (PI/T) 68230 5 29
50		* Terminal ACIA 6850 4 28
51		* Remote ACIA 6850 3 27
52		* Host ACIA 6850 2 26
53		* ACFAIL, SYSFAIL VME 5 29
54		* Off board Sources (other VME boards)
55		* 6 Port Serial I/O board SIO 4 64-75 0xb00000
56		* 8 Port Serial I/O board ISIO 4 76-83 0x960000
57		* Disk Controller WFC 3 119 0xb01000
58		* SCSI Controller ISCSI 4 119 0xa00000
59		* Slot 1 Controller Board ASCU 7 31 0xb02000
60		* ----------------------------------------------------------
61		*
62		* TODO:
63		* - Finish 3 x ACIA6850, host and remote interface left, terminal works
64		* - Finish 1 x 68230 Motorola, Parallel Interface / Timer as required by ROM
65		* - Configure PIT to the Centronics device printer interface as
66		* supported by ROM (DONE)
67		* - Add 1 x Abort Switch
68		* - Add 1 x Reset Switch
69		* - Add 1 x Halt LED
70		* - Add a jumper field device as supported by PCB
71		* - Add configurable serial connector between ACIA:s and
72		* - Real terminal emulator, ie rs232 "socket"
73		* - Debug console
74		* - Add VME bus driver
75		*
76		****************************************************************************/
77	4
	5	Force SYS68K CPU-1/CPU-6 VME SBC drivers, initially based on the 68ksbc.c
	6
	7	13/06/2015
	8
	9	The info found on the links below is for a later revisions of the board I have
	10	but I hope it is somewhat compatible so I can get it up and running at least.
	11	My CPU-1 board has proms from 1983 and no rev markings so probably the original.
	12
	13	http://bitsavers.trailing-edge.com/pdf/forceComputers/1988_Force_VMEbus_Products.pdf
	14	http://www.artisantg.com/info/P_wUovN.pdf
	15
	16	Some info from those documents:
	17
	18	Address Map
	19	----------------------------------------------------------
	20	Address Range Description
	21	----------------------------------------------------------
	22	000 000 - 000 007 Initialisation vectors from system EPROM
	23	000 008 - 01F FFF Dynamic RAM on CPU-1 B
	24	000 008 - 07F FFF Dynamic RAM on CPU-1 D
	25	080 008 - 09F FFF SYSTEM EPROM Area
	26	OAO 000 - OBF FFF USER EPROMArea
	27	0C0 041 - 0C0 043 ACIA (P3) Host
	28	0C0 080 - 0C0 082 ACIA (P4) Terminal
	29	0C0 101 - 0C0 103 ACIA (P5) Remote device (eg serial printer)
	30	0C0 401 - 0C0 42F RTC
	31	OEO 001 - 0E0 035 PI/T (eg centronics printer)
	32	OEO 200 - 0E0 2FF FPU
	33	OEO 300 - 0E0 300 Reset Off
	34	OEO 380 - 0E0 380 Reset On
	35	100 000 - FEF FFF VMEbus addresses (A24)
	36	FFO 000 - FFF FFF VMEbus Short I/O (A16)
	37	----------------------------------------------------------
	38
	39	Interrupt sources
	40	----------------------------------------------------------
	41	Description Device Lvl IRQ VME board
	42	/Board Vector Address
	43	----------------------------------------------------------
	44	On board Sources
	45	ABORT Switch 7 31
	46	Real Time Clock (RTC) 58167A 6 30
	47	Parallel/Timer (PI/T) 68230 5 29
	48	Terminal ACIA 6850 4 28
	49	Remote ACIA 6850 3 27
	50	Host ACIA 6850 2 26
	51	ACFAIL, SYSFAIL VME 5 29
	52	Off board Sources (other VME boards)
	53	6 Port Serial I/O board SIO 4 64-75 0xb00000
	54	8 Port Serial I/O board ISIO 4 76-83 0x960000
	55	Disk Controller WFC 3 119 0xb01000
	56	SCSI Controller ISCSI 4 119 0xa00000
	57	Slot 1 Controller Board ASCU 7 31 0xb02000
	58	----------------------------------------------------------
	59
	60	10. The VMEbus
	61	---------------
	62	The implemented VMEbus Interface includes 24 address, 16 data,
	63	6 address modifier and the asynchronous control signals.
	64	A single level bus arbiter is provided to build multi master
	65	systems. In addition to the bus arbiter, a separate slave bus
	66	arbitration allows selection of the arbitration level (0-3).
	67
	68	The address modifier range .,Short 110 Access?? can be selected
	69	via a jumper for variable system generation. The 7 interrupt
	70	request levels of the VMEbus are fully supported from the
	71	SYS68K1CPU-1 B/D. For multi-processing, each IRQ signal can be
	72	enabled/disabled via a jumper field.
	73
	74	Additionally, the SYS68K1CPU-1 B/D supports the ACFAIL, SYSRESET,
	75	SYSFAIL and SYSCLK signal (16 MHz).
	76
	77
	78	TODO:
	79	- Finish 2 x ACIA6850, host and remote interface left, terminal works
	80	- Finish 1 x 68230 Motorola, Parallel Interface / Timer
	81	- Connect Port B to a Centronics printer interface
	82	- Add 1 x Abort Switch
	83	- Add configurable serial connector between ACIA:s and
	84	- Real terminal emulator, ie rs232 "socket"
	85	- Debug console
	86	- Add VME bus driver
	87
	88	****************************************************************************/
	89
78	90	#include "emu.h"
79	91	#include "bus/rs232/rs232.h"
80	92	#include "cpu/m68000/m68000.h"
r249044	r249045
82	94	#include "machine/68230pit.h"
83	95	#include "machine/6850acia.h"
84	96	#include "machine/clock.h"
85		#include "bus/centronics/ctronics.h"
86		#include "bus/generic/slot.h"
87		#include "bus/generic/carts.h"
88	97
89		#define LOG(x) x
90
91	98	#define BAUDGEN_CLOCK XTAL_1_8432MHz
92	99	/*
93		* The baudrate on the Force68k CPU-1 to CPU-6 is generated by a
94		* Motorola 14411 bitrate generator, the CPU-6 documents matches the circuits
95		* that I could find on the CPU-1 board. Here how I calculated the clock for
96		* the factory settings. No need to add selectors until terminal.c supports
97		* configurable baudrates. Fortunality CPU-1 was shipped with 9600N8!
98		*
99		* From the documents:
100		*
101		* 3 RS232C interfaces, strap selectable baud rate from 110-9600 or 600-19200 baud
102		*
103		* Default Jumper Settings of B7:
104		* --------------------------------
105		* GND 10 - 11 RSA input on 14411
106		* F1 on 14411 1 - 20 Baud selector of the terminal port
107		* F1 on 14411 3 - 18 Baud selector of the host port
108		* F1 on 14411 5 - 16 Baud selector of the remote port
109		*
110		* The RSB input on the 14411 is kept high always so RSA=0, RSB=1 and a 1.8432MHz crystal
111		* generates 153600 on the F1 output pin which by default strapping is connected to all
112		* three 6850 acias on the board. These can be strapped separatelly to speedup downloads.
113		*
114		* The selectable outputs from 14411, F1-F16:
115		* X16 RSA=0,RSB=1: 153600, 115200, 76800, 57600, 38400, 28800, 19200, 9600, 4800, 3200, 2153.3, 1758.8, 1200, 921600, 1843000
116		* X64 RSA=1,RSB=1: 614400, 460800, 307200, 230400, 153600, 115200, 76800, 57600, 38400, 28800, 19200, 9600, 4800, 921600, 1843000
117		*
118		* However, the datasheet says baudrate is strapable for 110-9600 but the output is 153600
119		* so the system rom MUST setup the acia to divide by 16 to generate the correct baudrate.
120		*
121		*/
	100	The baudrate on the Force68k CPU-1 to CPU-6 is generated by a
	101	Motorola 14411 bitrate generator, the CPU-6 documents matches the circuits
	102	that I could find on the CPU-1 board. Here how I calculated the clock for
	103	the factory settings. No need to add selectors until terminal.c supports
	104	configurable baudrates. Fortunality CPU-1 was shipped with 9600N8!
	105
	106	From the documents:
	107
	108	3 RS232C interfaces, strap selectable baud rate from 110-9600 or 600-19200 baud
	109
	110	Default Jumper Settings of B7:
	111	--------------------------------
	112	GND 10 - 11 RSA input on 14411
	113	F1 on 14411 1 - 20 Baud selector of the terminal port
	114	F1 on 14411 3 - 18 Baud selector of the host port
	115	F1 on 14411 5 - 16 Baud selector of the remote port
	116
	117	The RSB input on the 14411 is kept high always so RSA=0, RSB=1 and a 1.8432MHz crystal
	118	generates 153600 on the F1 output pin which by default strapping is connected to all
	119	three 6850 acias on the board. These can be strapped separatelly to speedup downloads.
	120
	121	The selectable outputs from 14411, F1-F16:
	122	X16 RSA=0,RSB=1: 153600, 115200, 76800, 57600, 38400, 28800, 19200, 9600, 4800, 3200, 2153.3, 1758.8, 1200, 921600, 1843000
	123	X64 RSA=1,RSB=1: 614400, 460800, 307200, 230400, 153600, 115200, 76800, 57600, 38400, 28800, 19200, 9600, 4800, 921600, 1843000
	124
	125	However, the datasheet says baudrate is strapable for 110-9600 but the output is 153600
	126	so the system rom MUST setup the acia to divide by 16 to generate the correct baudrate.
	127
	128	*/
122	129	#define ACIA_CLOCK (BAUDGEN_CLOCK / 12)
123	130
124	131	class force68k_state : public driver_device
125	132	{
126	133	public:
127		force68k_state(const machine_config &mconfig, device_type type, const char *tag) :
128		driver_device (mconfig, type, tag),
129		m_maincpu (*this, "maincpu"),
130		m_rtc (*this, "rtc"),
131		m_pit (*this, "pit"),
132		m_aciahost (*this, "aciahost"),
133		m_aciaterm (*this, "aciaterm"),
134		m_aciaremt (*this, "aciaremt"),
135		m_centronics (*this, "centronics")
136		, m_centronics_ack (0)
137		, m_centronics_busy (0)
138		, m_centronics_perror (0)
139		, m_centronics_select (0)
140		,m_cart(*this, "exp_rom1")
141		{
142		}
	134	force68k_state(const machine_config &mconfig, device_type type, const char *tag) :
	135	driver_device(mconfig, type, tag),
	136	// m_rtc(*this, "rtc")
	137	m_maincpu(*this, "maincpu"),
	138	m_rtc(*this, "rtc"),
	139	m_pit(*this, "pit"),
	140	m_aciahost(*this, "aciahost"),
	141	m_aciaterm(*this, "aciaterm"),
	142	m_aciaremt(*this, "aciaremt")
	143	{
	144	}
143	145
144		DECLARE_READ16_MEMBER (bootvect_r);
145		DECLARE_READ16_MEMBER (vme_a24_r);
146		DECLARE_WRITE16_MEMBER (vme_a24_w);
147		DECLARE_READ16_MEMBER (vme_a16_r);
148		DECLARE_WRITE16_MEMBER (vme_a16_w);
149		virtual void machine_start ();
150		// clocks
151		DECLARE_WRITE_LINE_MEMBER (write_aciahost_clock);
152		DECLARE_WRITE_LINE_MEMBER (write_aciaterm_clock);
153		DECLARE_WRITE_LINE_MEMBER (write_aciaremt_clock);
154		// centronics printer interface
155		DECLARE_WRITE_LINE_MEMBER (centronics_ack_w);
156		DECLARE_WRITE_LINE_MEMBER (centronics_busy_w);
157		DECLARE_WRITE_LINE_MEMBER (centronics_perror_w);
158		DECLARE_WRITE_LINE_MEMBER (centronics_select_w);
159		// User EPROM/SRAM slot(s)
160		int force68k_load_cart(device_image_interface &image, generic_slot_device *slot);
161		DECLARE_DEVICE_IMAGE_LOAD_MEMBER (exp1_load) { return force68k_load_cart(image, m_cart); }
162		DECLARE_READ16_MEMBER (read16_rom);
	146	DECLARE_READ16_MEMBER(bootvect_r);
	147	virtual void machine_start();
	148	DECLARE_WRITE_LINE_MEMBER(write_aciahost_clock);
	149	DECLARE_WRITE_LINE_MEMBER(write_aciaterm_clock);
	150	DECLARE_WRITE_LINE_MEMBER(write_aciaremt_clock);
163	151
164		protected:
165
166	152	private:
167		required_device<cpu_device> m_maincpu;
168		required_device<mm58167_device> m_rtc;
169		required_device<pit68230_device> m_pit;
170		required_device<acia6850_device> m_aciahost;
171		required_device<acia6850_device> m_aciaterm;
172		required_device<acia6850_device> m_aciaremt;
173		optional_device<centronics_device> m_centronics;
	153	required_device<cpu_device> m_maincpu;
	154	required_device<mm58167_device> m_rtc;
	155	required_device<pit68230_device> m_pit;
	156	required_device<acia6850_device> m_aciahost;
	157	required_device<acia6850_device> m_aciaterm;
	158	required_device<acia6850_device> m_aciaremt;
174	159
175		INT32 m_centronics_ack;
176		INT32 m_centronics_busy;
177		INT32 m_centronics_perror;
178		INT32 m_centronics_select;
179
180		// Pointer to System ROMs needed by bootvect_r
181		UINT16 *m_sysrom;
182		UINT16 *m_usrrom;
183
184		required_device<generic_slot_device> m_cart;
185
	160	// Pointer to System ROMs needed by bootvect_r
	161	UINT16 *m_sysrom;
186	162	};
187	163
188		static ADDRESS_MAP_START (force68k_mem, AS_PROGRAM, 16, force68k_state)
189		ADDRESS_MAP_UNMAP_HIGH
190		AM_RANGE (0x000000, 0x000007) AM_ROM AM_READ (bootvect_r) /* Vectors mapped from System EPROM */
191		AM_RANGE (0x000008, 0x01ffff) AM_RAM /* DRAM CPU-1B */
192		//AM_RANGE (0x020000, 0x07ffff) AM_RAM /* Additional DRAM CPU-1D */
193		AM_RANGE (0x080000, 0x083fff) AM_ROM /* System EPROM Area 16Kb DEBUGGER supplied as default on CPU-1B/D */
194		AM_RANGE (0x084000, 0x09ffff) AM_ROM /* System EPROM Area 112Kb additional space for System ROM */
195		//AM_RANGE (0x0a0000, 0x0bffff) AM_ROM /* User EPROM/SRAM Area, max 128Kb mapped by a cartslot */
196		AM_RANGE (0x0c0040, 0x0c0041) AM_DEVREADWRITE8 ("aciahost", acia6850_device, status_r, control_w, 0x00ff)
197		AM_RANGE (0x0c0042, 0x0c0043) AM_DEVREADWRITE8 ("aciahost", acia6850_device, data_r, data_w, 0x00ff)
198		AM_RANGE (0x0c0080, 0x0c0081) AM_DEVREADWRITE8 ("aciaterm", acia6850_device, status_r, control_w, 0xff00)
199		AM_RANGE (0x0c0082, 0x0c0083) AM_DEVREADWRITE8 ("aciaterm", acia6850_device, data_r, data_w, 0xff00)
200		AM_RANGE (0x0c0100, 0x0c0101) AM_DEVREADWRITE8 ("aciaremt", acia6850_device, status_r, control_w, 0x00ff)
201		AM_RANGE (0x0c0102, 0x0c0103) AM_DEVREADWRITE8 ("aciaremt", acia6850_device, data_r, data_w, 0x00ff)
202		AM_RANGE (0x0c0400, 0x0c042f) AM_DEVREADWRITE8 ("rtc", mm58167_device, read, write, 0x00ff)
203		AM_RANGE (0x0e0000, 0x0e0035) AM_DEVREADWRITE8 ("pit", pit68230_device, read, write, 0x00ff)
	164	static ADDRESS_MAP_START(force68k_mem, AS_PROGRAM, 16, force68k_state)
	165	ADDRESS_MAP_UNMAP_HIGH
	166	AM_RANGE(0x000000, 0x000007) AM_ROM AM_READ(bootvect_r) /* Vectors mapped from System EPROM */
	167	AM_RANGE(0x000008, 0x01ffff) AM_RAM /* DRAM */
	168	AM_RANGE(0x080000, 0x09ffff) AM_ROM /* System EPROM Area */
	169	// AM_RANGE(0x0a0000, 0x0bffff) AM_ROM /* User EPROM Area */
	170	AM_RANGE(0x0c0040, 0x0c0041) AM_DEVREADWRITE8("aciahost", acia6850_device, status_r, control_w, 0x00ff)
	171	AM_RANGE(0x0c0042, 0x0c0043) AM_DEVREADWRITE8("aciahost", acia6850_device, data_r, data_w, 0x00ff)
	172	AM_RANGE(0x0c0080, 0x0c0081) AM_DEVREADWRITE8("aciaterm", acia6850_device, status_r, control_w, 0xff00)
	173	AM_RANGE(0x0c0082, 0x0c0083) AM_DEVREADWRITE8("aciaterm", acia6850_device, data_r, data_w, 0xff00)
	174	AM_RANGE(0x0c0100, 0x0c0101) AM_DEVREADWRITE8("aciaremt", acia6850_device, status_r, control_w, 0x00ff)
	175	AM_RANGE(0x0c0102, 0x0c0103) AM_DEVREADWRITE8("aciaremt", acia6850_device, data_r, data_w, 0x00ff)
	176	AM_RANGE(0x0c0400, 0x0c042f) AM_DEVREADWRITE8("rtc", mm58167_device, read, write, 0x00ff)
	177	AM_RANGE(0x0e0000, 0x0e0035) AM_DEVREADWRITE8("pit", pit68230_device, data_r, data_w, 0x00ff)
204	178	// AM_RANGE(0x0e0200, 0x0e0380) AM_READWRITE(fpu_r, fpu_w) /* optional FPCP 68881 FPU interface */
205		AM_RANGE(0x100000, 0xfeffff) AM_READWRITE(vme_a24_r, vme_a24_w) /* VMEbus Rev B addresses (24 bits) */
206		AM_RANGE(0xff0000, 0xffffff) AM_READWRITE(vme_a16_r, vme_a16_w) /* VMEbus Rev B addresses (16 bits) */
	179	// AM_RANGE(0x100000, 0xfeffff) /* VMEbus Rev B addresses (24 bits) */
	180	// AM_RANGE(0xff0000, 0xffffff) /* VMEbus Rev B addresses (16 bits) */
207	181	ADDRESS_MAP_END
208	182
209	183	/* Input ports */
210		static INPUT_PORTS_START (force68k)
	184	static INPUT_PORTS_START( force68k )
211	185	INPUT_PORTS_END
212	186
213		/*
214		* Centronics support
215		*
216		* The system ROMs has support for a parallel printer interface but the signals are just routed to row A
217		* of the VME P2 connector so no on board Centronics connector is available but assumed to be added on a
218		* separate I/O board. After some detective work I found that the ROM works as follows:
219		*
220		* The 'PA' (Printer Attach) command issues a <cr> on Port A and sends a strobe on H2 it then loops over
221		* the select signal, bit 0 on Port B, and the ack signal on HS1, both to be non zero. The support is really
222		* flawed as the strobe signal goes high instead of low ( this might assume an inverting driver on the
223		* P2 board ) and the busy signal is not checked at all. Or I might have assumed it all wrong, but it now
224		* works with the generic centronics printer driver. Need the printer board documentation to improve further.
225		*
226		* When the 'PA' command is successful everything printed to screen is mirrored on the printer. Use the
227		* 'NOPA' command to stop mirroring. I had no printer ROMs so could not test it with a "real" printer.
228		*
229		* Force CPU-1 init sequence for MC68230 PIT
230		* -----------------------------------------
231		* 0801E6 0E0000 W 00 -> PGCR Mode 0 (uni8), H34 dis, H12 dis, H1234 HZ
232		* 0801E6 0E0002 W 00 -> PSRR PC4, PC5, H1S>H2S>H3S>H4S
233		* 0801E6 0E0004 W FF -> PADDR Port A all Outputs
234		* 0801E6 0E0006 W 00 -> PBDDR Port B all Inputs
235		* 0801EA 0E000C W 60 -> PACR Port A Mode 01, pin def, dbfr H1 data rec, H2 status/int, H2 output neg, H2S clrd
236		* 0801F0 0E000E W A0 -> PBCR Port B mode 1x, H4 output neg, H4S clrd, H3 int dis, H3 edg input, H3S set by assrt edg
237		* 0801F6 0E0000 W 30 -> PGCR H34 enable, H12enable
238		* 0801FC 0E000E W A8 -> PBCR +H4 asserted
239		* 08020A 0E000E W A0 -> PBCR +H4 negated
240		*
241		* Upon PA (Printer Attach) command enabling the Centronics printer mode
242		* ---------------------------------------------------------------------
243		* 081DB4 0E0011 W D0 -> PADR Data to Port A
244		* 081DB8 0E000D W 68 -> PACR H2 output asserted Centronics Strobe
245		* 081DC0 0E000D W 60 -> PACR H2 output negated
246		* 081DD0 0E0013 R 00 <- PBDR Port B polled for 01 (data) & 03 (mask)
247		*
248		*/
249
250		/* Centronics ACK handler
251		* The centronics ack signal is expected by the ROM to arrive at H1 input line
252		*/
253		WRITE_LINE_MEMBER (force68k_state::centronics_ack_w)
	187	void force68k_state::machine_start()
254	188	{
255		LOG (logerror ("centronics_ack_w(%d) %lld\n", state, m_maincpu->total_cycles ()));
256		m_centronics_ack = state;
257		m_pit->h1_set (state);
	189	m_sysrom = (UINT16*)(memregion("maincpu")->base() + 0x080000);
258	190	}
259	191
260		/* Centronics BUSY handler
261		* The centronics busy signal is not used by the ROM driver afaik
262		*/
263		WRITE_LINE_MEMBER (force68k_state::centronics_busy_w){
264		LOG (logerror ("centronics_busy_w(%d) %lld\n", state, m_maincpu->total_cycles ()));
265		m_centronics_busy = state;
	192	READ16_MEMBER(force68k_state::bootvect_r)
	193	{
	194	return m_sysrom[offset];
266	195	}
267	196
268		/* Centronics PERROR handler
269		* The centronics perror signal is not used by the ROM driver afaik
270		*/
271		WRITE_LINE_MEMBER (force68k_state::centronics_perror_w){
272		LOG (logerror ("centronics_perror_w(%d) %lld\n", state, m_maincpu->total_cycles ()));
273		m_centronics_perror = state;
	197	WRITE_LINE_MEMBER(force68k_state::write_aciahost_clock)
	198	{
	199	m_aciahost->write_txc(state);
	200	m_aciahost->write_rxc(state);
274	201	}
275	202
276		/* Centronics SELECT handler
277		* The centronics select signal is expected by the ROM on Port B bit 0
278		*/
279		WRITE_LINE_MEMBER (force68k_state::centronics_select_w){
280		LOG (logerror ("centronics_select_w(%d) %lld\n", state, m_maincpu->total_cycles ()));
281		m_centronics_select = state;
282		m_pit->portb_setbit (0, state);
283		}
284
285		/* Start it up */
286		void force68k_state::machine_start ()
	203	WRITE_LINE_MEMBER(force68k_state::write_aciaterm_clock)
287	204	{
288		LOG (logerror ("machine_start\n"));
289
290		save_item (NAME (m_centronics_busy));
291		save_item (NAME (m_centronics_ack));
292		save_item (NAME (m_centronics_select));
293		save_item (NAME (m_centronics_perror));
294
295		/* Setup pointer to bootvector in ROM for bootvector handler bootvect_r */
296		m_sysrom = (UINT16*)(memregion ("maincpu")->base () + 0x080000);
297
298		/* Map user ROM/RAM socket(s) */
299		if (m_cart->exists())
300		{
301		m_usrrom = (UINT16*)m_cart->get_rom_base();
302		#if 0 // This should be the correct way but produces odd and even bytes swapped
303		m_maincpu->space(AS_PROGRAM).install_read_handler(0xa0000, 0xbffff, read16_delegate(FUNC(generic_slot_device::read16_rom), (generic_slot_device*)m_cart));
304		#else // So we installs a custom very ineffecient handler for now until we understand hwp to solve the problem better
305		m_maincpu->space(AS_PROGRAM).install_read_handler(0xa0000, 0xbffff, read16_delegate(FUNC(force68k_state::read16_rom), this));
306		#endif
307		}
	205	m_aciaterm->write_txc(state);
	206	m_aciaterm->write_rxc(state);
308	207	}
309	208
310		/* A very ineffecient User cart emulation of two 8 bit sockets (odd and even) */
311		READ16_MEMBER (force68k_state::read16_rom){
312		offset = offset % m_cart->common_get_size("rom"); // Don't read outside buffer...
313		return ((m_usrrom [offset] << 8) & 0xff00) \| ((m_usrrom [offset] >> 8) & 0x00ff);
314		}
315
316		/* Boot vector handler, the PCB hardwires the first 8 bytes from 0x80000 to 0x0 */
317		READ16_MEMBER (force68k_state::bootvect_r){
318		return m_sysrom [offset];
319		}
320
321		/* 10. The VMEbus (text from board documentation)
322		* ---------------
323		* The implemented VMEbus Interface includes 24 address, 16 data,
324		* 6 address modifier and the asynchronous control signals.
325		* A single level bus arbiter is provided to build multi master
326		* systems. In addition to the bus arbiter, a separate slave bus
327		* arbitration allows selection of the arbitration level (0-3).
328		*
329		* The address modifier range .,Short 110 Access« can be selected
330		* via a jumper for variable system generation. The 7 interrupt
331		* request levels of the VMEbus are fully supported from the
332		* SYS68K1CPU-1 B/D. For multi-processing, each IRQ signal can be
333		* enabled/disabled via a jumper field.
334		*
335		* Additionally, the SYS68K1CPU-1 B/D supports the ACFAIL, SYSRESET,
336		* SYSFAIL and SYSCLK signal (16 MHz).
337		*/
338
339		/* Dummy VME access methods until the VME bus device is ready for use */
340		READ16_MEMBER (force68k_state::vme_a24_r){
341		LOG (logerror ("vme_a24_r\n"));
342		return (UINT16) 0;
343		}
344
345		WRITE16_MEMBER (force68k_state::vme_a24_w){
346		LOG (logerror ("vme_a24_w\n"));
347		}
348
349		READ16_MEMBER (force68k_state::vme_a16_r){
350		LOG (logerror ("vme_16_r\n"));
351		return (UINT16) 0;
352		}
353
354		WRITE16_MEMBER (force68k_state::vme_a16_w){
355		LOG (logerror ("vme_a16_w\n"));
356		}
357
358		/*
359		* Serial port clock sources can all be driven by different outputs of the 14411
360		*/
361		WRITE_LINE_MEMBER (force68k_state::write_aciahost_clock){
362		m_aciahost->write_txc (state);
363		m_aciahost->write_rxc (state);
364		}
365
366		WRITE_LINE_MEMBER (force68k_state::write_aciaterm_clock){
367		m_aciaterm->write_txc (state);
368		m_aciaterm->write_rxc (state);
369		}
370
371		WRITE_LINE_MEMBER (force68k_state::write_aciaremt_clock){
372		m_aciaremt->write_txc (state);
373		m_aciaremt->write_rxc (state);
374		}
375
376		/*
377		* 4. The USER Area (Text from the board manual)
378		The USER area contains two 28 pin sockets with JEDEC compatible pin out.
379		To allow the usage of static RAM's, the access to the USER area is byte
380		oriented. Table 3. lists the usable device types.
381
382		Bits Bytes EPROM SRAM
383		--------------------------
384		2Kx16 4 Kbyte 2716 6116
385		4Kx16 8 Kbyte 2732
386		8Kx16 16 Kbyte 2764 6264
387		16Kx16 32 Kbyte 27128
388		32Kx16 64 Kbyte 27256
389		--------------------------
390		*/
391		// Implementation of static 2 x 64K EPROM in sockets J10/J11 as 16 bit wide cartridge for easier
392		// software handling. TODO: make configurable according to table above.
393		static MACHINE_CONFIG_FRAGMENT( fccpu1_eprom_sockets )
394		MCFG_GENERIC_CARTSLOT_ADD("exp_rom1", generic_plain_slot, "fccpu1_cart")
395		MCFG_GENERIC_EXTENSIONS("bin,rom")
396		MCFG_GENERIC_WIDTH(GENERIC_ROM16_WIDTH)
397		MCFG_GENERIC_ENDIAN(ENDIANNESS_BIG)
398		MCFG_GENERIC_LOAD(force68k_state, exp1_load)
399		// MCFG_SOFTWARE_LIST_ADD("cart_list", "fccpu1_cart")
400		MACHINE_CONFIG_END
401
402		/***************************
403		Rom loading functions
404		****************************/
405		int force68k_state::force68k_load_cart(device_image_interface &image, generic_slot_device *slot)
	209	WRITE_LINE_MEMBER(force68k_state::write_aciaremt_clock)
406	210	{
407		UINT32 size = slot->common_get_size("rom");
408
409		if (size > 0x20000) // Max 128Kb
410		{
411		LOG( printf("Cartridge size exceeding max size (128Kb): %d\n", size) );
412		image.seterror(IMAGE_ERROR_UNSPECIFIED, "Cartridge size exceeding max size (128Kb)");
413		return IMAGE_INIT_FAIL;
414		}
415
416		slot->rom_alloc(size, GENERIC_ROM16_WIDTH, ENDIANNESS_BIG);
417		slot->common_load_rom(slot->get_rom_base(), size, "rom");
418
419		return IMAGE_INIT_PASS;
	211	m_aciaremt->write_txc(state);
	212	m_aciaremt->write_rxc(state);
420	213	}
421	214
422		/*
423		* Machine configuration
424		*/
425		static MACHINE_CONFIG_START (fccpu1, force68k_state)
426		/* basic machine hardware */
427		MCFG_CPU_ADD ("maincpu", M68000, XTAL_16MHz / 2)
428		MCFG_CPU_PROGRAM_MAP (force68k_mem)
	215	static MACHINE_CONFIG_START( fccpu1, force68k_state )
	216	/* basic machine hardware */
	217	MCFG_CPU_ADD("maincpu", M68000, XTAL_16MHz / 2)
	218	MCFG_CPU_PROGRAM_MAP(force68k_mem)
429	219
430		/* P3/Host Port config
431		* LO command causes ROM monitor to expect S-records on HOST port by default
432		* Implementation through nullmodem currently does not support handshakes so
433		* the ROM momitor is over-run while checking for checksums etc if used with
434		* UI mount <file> feature.
435		*/
436		MCFG_DEVICE_ADD ("aciahost", ACIA6850, 0)
	220	/* P3/Host Port config */
	221	MCFG_DEVICE_ADD("aciahost", ACIA6850, 0)
	222	MCFG_DEVICE_ADD("aciahost_clock", CLOCK, ACIA_CLOCK)
	223	MCFG_CLOCK_SIGNAL_HANDLER(WRITELINE(force68k_state, write_aciahost_clock))
437	224
438		MCFG_ACIA6850_TXD_HANDLER (DEVWRITELINE ("rs232host", rs232_port_device, write_txd))
439		MCFG_ACIA6850_RTS_HANDLER (DEVWRITELINE ("rs232host", rs232_port_device, write_rts))
	225	/* P4/Terminal Port config */
	226	MCFG_DEVICE_ADD("aciaterm", ACIA6850, 0)
440	227
441		MCFG_RS232_PORT_ADD ("rs232host", default_rs232_devices, "null_modem")
442		MCFG_RS232_RXD_HANDLER (DEVWRITELINE ("aciahost", acia6850_device, write_rxd))
443		MCFG_RS232_CTS_HANDLER (DEVWRITELINE ("aciahost", acia6850_device, write_cts))
	228	MCFG_ACIA6850_TXD_HANDLER(DEVWRITELINE("rs232trm", rs232_port_device, write_txd))
	229	MCFG_ACIA6850_RTS_HANDLER(DEVWRITELINE("rs232trm", rs232_port_device, write_rts))
444	230
445		MCFG_DEVICE_ADD ("aciahost_clock", CLOCK, ACIA_CLOCK)
446		MCFG_CLOCK_SIGNAL_HANDLER (WRITELINE (force68k_state, write_aciahost_clock))
	231	MCFG_RS232_PORT_ADD("rs232trm", default_rs232_devices, "terminal")
	232	MCFG_RS232_RXD_HANDLER(DEVWRITELINE("aciaterm", acia6850_device, write_rxd))
	233	MCFG_RS232_CTS_HANDLER(DEVWRITELINE("aciaterm", acia6850_device, write_cts))
447	234
448		/* P4/Terminal Port config */
449		MCFG_DEVICE_ADD ("aciaterm", ACIA6850, 0)
	235	MCFG_DEVICE_ADD("aciaterm_clock", CLOCK, ACIA_CLOCK)
	236	MCFG_CLOCK_SIGNAL_HANDLER(WRITELINE(force68k_state, write_aciaterm_clock))
450	237
451		MCFG_ACIA6850_TXD_HANDLER (DEVWRITELINE ("rs232trm", rs232_port_device, write_txd))
452		MCFG_ACIA6850_RTS_HANDLER (DEVWRITELINE ("rs232trm", rs232_port_device, write_rts))
	238	/* P5/Remote Port config */
	239	MCFG_DEVICE_ADD("aciaremt", ACIA6850, 0)
453	240
454		MCFG_RS232_PORT_ADD ("rs232trm", default_rs232_devices, "terminal")
455		MCFG_RS232_RXD_HANDLER (DEVWRITELINE ("aciaterm", acia6850_device, write_rxd))
456		MCFG_RS232_CTS_HANDLER (DEVWRITELINE ("aciaterm", acia6850_device, write_cts))
	241	#define PRINTER 0
	242	#if PRINTER
	243	MCFG_ACIA6850_TXD_HANDLER(DEVWRITELINE("rs232rmt", rs232_port_device, write_txd))
	244	MCFG_ACIA6850_RTS_HANDLER(DEVWRITELINE("rs232rmt", rs232_port_device, write_rts))
457	245
458		MCFG_DEVICE_ADD ("aciaterm_clock", CLOCK, ACIA_CLOCK)
459		MCFG_CLOCK_SIGNAL_HANDLER (WRITELINE (force68k_state, write_aciaterm_clock))
	246	MCFG_RS232_PORT_ADD("rs232rmt", default_rs232_devices, "printer")
	247	MCFG_RS232_RXD_HANDLER(DEVWRITELINE("aciaremt", acia6850_device, write_rxd))
	248	MCFG_RS232_CTS_HANDLER(DEVWRITELINE("aciaremt", acia6850_device, write_cts))
	249	#endif
460	250
461		/* P5/Remote Port config */
462		MCFG_DEVICE_ADD ("aciaremt", ACIA6850, 0)
	251	MCFG_DEVICE_ADD("aciaremt_clock", CLOCK, ACIA_CLOCK)
	252	MCFG_CLOCK_SIGNAL_HANDLER(WRITELINE(force68k_state, write_aciaterm_clock))
463	253
464		MCFG_DEVICE_ADD ("aciaremt_clock", CLOCK, ACIA_CLOCK)
465		MCFG_CLOCK_SIGNAL_HANDLER (WRITELINE (force68k_state, write_aciaterm_clock))
	254	/* RTC Real Time Clock device */
	255	MCFG_DEVICE_ADD("rtc", MM58167, XTAL_32_768kHz)
466	256
467		/* RTC Real Time Clock device */
468		MCFG_DEVICE_ADD ("rtc", MM58167, XTAL_32_768kHz)
	257	/* PIT Parallel Interface and Timer device, assuming strapped for on board clock */
	258	MCFG_DEVICE_ADD("pit", PIT68230, XTAL_16MHz / 2)
469	259
470		/* PIT Parallel Interface and Timer device, assuming strapped for on board clock */
471		MCFG_DEVICE_ADD ("pit", PIT68230, XTAL_16MHz / 2)
472		MCFG_PIT68230_PA_OUTPUT_CALLBACK (DEVWRITE8 ("cent_data_out", output_latch_device, write))
473		MCFG_PIT68230_H2_CALLBACK (DEVWRITELINE ("centronics", centronics_device, write_strobe))
	260	MACHINE_CONFIG_END
474	261
475		// centronics
476		MCFG_CENTRONICS_ADD ("centronics", centronics_devices, "printer")
477		MCFG_CENTRONICS_ACK_HANDLER (WRITELINE (force68k_state, centronics_ack_w))
478		MCFG_CENTRONICS_BUSY_HANDLER (WRITELINE (force68k_state, centronics_busy_w))
479		MCFG_CENTRONICS_PERROR_HANDLER (WRITELINE (force68k_state, centronics_perror_w))
480		MCFG_CENTRONICS_SELECT_HANDLER (WRITELINE (force68k_state, centronics_select_w))
481		MCFG_CENTRONICS_OUTPUT_LATCH_ADD ("cent_data_out", "centronics")
	262	#if 0
482	263
483		// EPROM sockets
484		MCFG_FRAGMENT_ADD(fccpu1_eprom_sockets)
	264	static MACHINE_CONFIG_START( fccpu6, force68k_state )
	265	MCFG_CPU_ADD("maincpu", M68000, XTAL_8MHz) /* Jumper B10 Mode B */
	266	MCFG_CPU_PROGRAM_MAP(force68k_mem)
485	267	MACHINE_CONFIG_END
486	268
487		#if 0 /*
488		* CPU-6 family is device and adressmap compatible with CPU-1 but with additions
489		* such as an optional 68881 FPU
490		*/
491		static MACHINE_CONFIG_START (fccpu6, force68k_state)
492		MCFG_CPU_ADD ("maincpu", M68000, XTAL_8MHz) /* Jumper B10 Mode B */
493		MCFG_CPU_PROGRAM_MAP (force68k_mem)
	269	static MACHINE_CONFIG_START( fccpu6a, force68k_state )
	270	MCFG_CPU_ADD("maincpu", M68000, XTAL_12_5MHz) /* Jumper B10 Mode A */
	271	MCFG_CPU_PROGRAM_MAP(force68k_mem)
494	272	MACHINE_CONFIG_END
495	273
496		static MACHINE_CONFIG_START (fccpu6a, force68k_state)
497		MCFG_CPU_ADD ("maincpu", M68000, XTAL_12_5MHz) /* Jumper B10 Mode A */
498		MCFG_CPU_PROGRAM_MAP (force68k_mem)
	274	static MACHINE_CONFIG_START( fccpu6v, force68k_state )
	275	MCFG_CPU_ADD("maincpu", M68010, XTAL_8MHz) /* Jumper B10 Mode B */
	276	MCFG_CPU_PROGRAM_MAP(force68k_mem)
499	277	MACHINE_CONFIG_END
500	278
501		static MACHINE_CONFIG_START (fccpu6v, force68k_state)
502		MCFG_CPU_ADD ("maincpu", M68010, XTAL_8MHz) /* Jumper B10 Mode B */
503		MCFG_CPU_PROGRAM_MAP (force68k_mem)
	279	static MACHINE_CONFIG_START( fccpu6va, force68k_state )
	280	MCFG_CPU_ADD("maincpu", M68010, XTAL_12_5MHz) /* Jumper B10 Mode A */
	281	MCFG_CPU_PROGRAM_MAP(force68k_mem)
504	282	MACHINE_CONFIG_END
505	283
506		static MACHINE_CONFIG_START (fccpu6va, force68k_state)
507		MCFG_CPU_ADD ("maincpu", M68010, XTAL_12_5MHz) /* Jumper B10 Mode A */
508		MCFG_CPU_PROGRAM_MAP (force68k_mem)
	284	static MACHINE_CONFIG_START( fccpu6vb, force68k_state )
	285	MCFG_CPU_ADD("maincpu", M68010, XTAL_12_5MHz) /* Jumper B10 Mode A */
	286	MCFG_CPU_PROGRAM_MAP(force68k_mem)
509	287	MACHINE_CONFIG_END
510
511		static MACHINE_CONFIG_START (fccpu6vb, force68k_state)
512		MCFG_CPU_ADD ("maincpu", M68010, XTAL_12_5MHz) /* Jumper B10 Mode A */
513		MCFG_CPU_PROGRAM_MAP (force68k_mem)
514		MACHINE_CONFIG_END
515	288	#endif
516	289
517	290	/* ROM definitions */
518		ROM_START (fccpu1)
519		ROM_REGION (0x1000000, "maincpu", 0)
	291	ROM_START( fccpu1 )
	292	ROM_REGION(0x1000000, "maincpu", 0)
520	293
521		ROM_LOAD16_BYTE ("fccpu1V1.0L.j8.bin", 0x080001, 0x2000, CRC (3ac6f08f) SHA1 (502f6547b508d8732bd68bbbb2402d8c30fefc3b))
522		ROM_LOAD16_BYTE ("fccpu1V1.0L.j9.bin", 0x080000, 0x2000, CRC (035315fb) SHA1 (90dc44d9c25d28428233e6846da6edce2d69e440))
523
524		/*
525		* System ROM terminal commands
526		*
527		* COMMAND SUMMARY DESCRIPTION (From CPU-1B datasheet, ROMs were dumped
528		* from a CPU-1 board so some features might be missing or different)
529		* ---------------------------------------------------------------------------
530		* BF <address1> <address2> <data> <CR> Block Fill memory - from addr1 through addr2 with data
531		* BM <address1> <address2> <address 3> <CR> Block Move - move from addr1 through addr2to addr3
532		* BR [<address> [; <count>] ... ] <CR> Set/display Breakpoint
533		* BS <address1> <address2> <data> <CR> Block Search - search addr1 through addr2 for data
534		* BT <address1> <address2> <CR> Block Test of memory
535		* DC <expression> <CR> Data Conversion
536		* DF <CR> Display Formatted registers
537		* DU [n] <address1> <address2>[<string>] <CR> Dump memory to object file
538		* GO or G [<address] <CR> Execute program.
539		* GD [<address] <CR> Go Direct
540		* GT <address> <CR> Exec prog: temporary breakpoint
541		* HE<CR> Help; display monitor commands
542		* LO [n] [;<options] <CR> Load Object file
543		* MD <address> [<count>] <CR> Memory Display
544		* MM or M <address> [<data<][;<options>] <CR> Memory Modify
545		* MS <address> <data1 > <data2> < ... <CR> Memory Set - starting at addr with data 1. data 2 ...
546		* NOBR [<address> ... ] <CR> Remove Breakpoint
547		* NOPA <CR> Printer Detach (Centronics on PIT/P2)
548		* OF <CR> Offset
549		* PA <CR> Printer Attach (Centronics on PIT/P2)
550		* PF[n] <CR> Set/display Port Format
551		* RM <CR> Register Modify
552		* TM [<exit character>] <CR> Transparent Mode
553		* TR OR T [<count] <CR> Trace
554		* TT <address> <CR> Trace: temporary breakpoint
555		* VE [n] [<string] <CR> Verify memory/object file
556		* ----------------------------------------------------------------------------
557		* .AO - .A7 [<expression] <CR> Display/set address register
558		* .00 - .07 [<expression] <CR> Display/set data register
559		* .RO - .R6 [<expression] <CR> Display/set offset register
560		* .PC [<expression] <CR> Display/set program counter
561		* .SR [<expression] <CR> Display/set status register
562		* .SS [<expression] <CR> Display/set supervisor stack
563		* .US [<expression] <CR> Display/set user stack
564		* ----------------------------------------------------------------------------
565		* MD <address> [<count>]; DI <CR> Disassemble memory location
566		* MM <address>; DI <CR> Disassemble/Assemble memory location
567		* ----------------------------------------------------------------------------
568		* Undocumented commands found in ROM table at address 0x80308
569		* .* No WHAT message displayed, no action seen.
570		*/
	294	ROM_LOAD16_BYTE( "fccpu1V1.0L.j8.bin", 0x080001, 0x2000, CRC(3ac6f08f) SHA1(502f6547b508d8732bd68bbbb2402d8c30fefc3b) )
	295	ROM_LOAD16_BYTE( "fccpu1V1.0L.j9.bin", 0x080000, 0x2000, CRC(035315fb) SHA1(90dc44d9c25d28428233e6846da6edce2d69e440) )
	296	/* COMMAND SUMMARY DESCRIPTION (From CPU-1B datasheet, ROMs were dumped
	297	from a CPU-1 board so some features might be missing or different)
	298	---------------------------------------------------------------------------
	299	BF <address1> <address2> <data> <CR> Block Fill memory - from addr1 through addr2 with data
	300	BM <address1> <address2> <address 3> <CR> Block Move - move from addr1 through addr2to addr3
	301	BR [<address> [; <count>] ... ] <CR> Set/display Breakpoint
	302	BS <address1> <address2> <data> <CR> Block Search - search addr1 through addr2 for data
	303	BT <address1> <address2> <CR> Block Test of memory
	304	DC <expression> <CR> Data Conversion
	305	DF <CR> Display Formatted registers
	306	DU [n] <address1> <address2>[<string>] <CR> Dump memory to object file
	307	GO [<address] <CR> Execute program
	308	GD [<address] <CR> Go Direct
	309	GT <address> <CR> Exec prog: temporary breakpoint
	310	HE<CR> Help; display monitor commands
	311	LO [n] [;<options] <CR> Load Object file
	312	MD <address> [<count?? <CR> Memory Display
	313	MM <address> [<data?? [;<options?? <CR> Memory Modify
	314	MS <address> <data1 > <data2> < ... <CR> Memory Set - starting at addr with data 1. data 2 ...
	315	NOBR [<address> ... ] <CR> Remove Breakpoint
	316	NOPA <CR> Printer Detach (Centronics on PIT/P2)
	317	OF <CR> Offset
	318	PA <CR> Printer Attach (Centronics on PIT/P2)
	319	PF[n] <CR> Set/display Port Format
	320	RM <CR> Register Modify
	321	TM [<exit character?? <CR> Transparent Mode
	322	TR [<count] <CR> Trace
	323	TT <address> <CR> Trace: temporary breakpoint
	324	VE [n] [<string] <CR> Verify memory/object file
	325	----------------------------------------------------------------------------
	326	.AO - .A7 [<expression] <CR> Display/set address register
	327	.00 - .07 [<expression] <CR> Display/set data register
	328	.RO - .R6 [<expression] <CR> Display/set offset register
	329	.PC [<expression] <CR> Display/set program counter
	330	.SR [<expression] <CR> Display/set status register
	331	.SS [<expression] <CR> Display/set supervisor stack
	332	.US [<expression] <CR> Display/set user stack
	333	----------------------------------------------------------------------------
	334	MD <address> [<count>]; D1 <CR> Disassemble memory location
	335	MM <address>; DI <CR> Disassemble/Assemble memory location
	336	----------------------------------------------------------------------------
	337	*/
571	338	ROM_END
572	339
573		/*
574		* CPU-6 ROMs were generally based om VMEPROM which contained the PDOS RTOS from Eyring Research.
575		* I don't have these but if anyone can dump them and send to me I can verify that they work as expected.
576		*/
577	340	#if 0
578		ROM_START (fccpu6)
579		ROM_REGION (0x1000000, "maincpu", 0)
	341	ROM_START( fccpu6 )
	342	ROM_REGION(0x1000000, "maincpu", 0)
580	343	ROM_END
581	344
582		ROM_START (fccpu6a)
583		ROM_REGION (0x1000000, "maincpu", 0)
	345	ROM_START( fccpu6a )
	346	ROM_REGION(0x1000000, "maincpu", 0)
584	347	ROM_END
585	348
586		ROM_START (fccpu6v)
587		ROM_REGION (0x1000000, "maincpu", 0)
	349	ROM_START( fccpu6v )
	350	ROM_REGION(0x1000000, "maincpu", 0)
588	351	ROM_END
589	352
590		ROM_START (fccpu6va)
591		ROM_REGION (0x1000000, "maincpu", 0)
	353	ROM_START( fccpu6va )
	354	ROM_REGION(0x1000000, "maincpu", 0)
592	355	ROM_END
593	356
594		ROM_START (fccpu6vb)
595		ROM_REGION (0x1000000, "maincpu", 0)
	357	ROM_START( fccpu6vb )
	358	ROM_REGION(0x1000000, "maincpu", 0)
596	359	ROM_END
597	360	#endif
598	361

trunk/src/mess/drivers/mc1000.c
r249044	r249045
378	378	+---------------o V+
379	379	\| \| \|
380	380	+-+ \| \|
381		\| \|390K \| \|
	381	\| \|309K \| \|
382	382	\| \|R17 \|8 \|4
383	383	+-+ +-------+
384	384	\| 7\| \|3
r249044	r249045
390	390	\| \| \| \| 555 \|
391	391	+-+ \| \| \|
392	392	\| \| 6\| \|5
393		------\| \|---+
	393	----?-\| \|---+
394	394	\| \| \| \|
395	395	---C30 +-------+ ---C29
396		---10n \|1 ---10n
	396	---103 \|1 ---103
397	397	_\|_ _\|_ _\|_
398	398	/// /// ///
399	399
400	400	Calculated properties:
401	401
402	402	* 99.74489795918367 Duty Cycle Percentage
403		* 367.34693~~87755~~102 Frequency in Hertz
	403	* 368.1126130105722 Frequency in Hertz
404	404	* 0.00000693 Seconds Low
405		* 0.00270963 Seconds High
	405	* 0.0027096299999999998 Seconds High
406	406
407	407	*/
408	408
409		#define MC1000_NE555_FREQ (367) /* Hz */
	409	#define MC1000_NE555_FREQ (368) /* Hz */
410	410	#define MC1000_NE555_DUTY_CYCLE (99.745) /* % */
411	411
412	412	TIMER_DEVICE_CALLBACK_MEMBER(mc1000_state::ne555_tick)

trunk/src/mess/layout/fccpu1.lay
r249044	r249045
1		<?xml version="1.0"?>
2		<!-- fccpu1.lay -->
3		<!-- 2015-07-27: Initial version. [JLE] -->
4		<mamelayout version="2">
5		<element name="front">
6		<image file="front.png" />
7		</element>
8		<view name="Force Computers SYS68K/CPU-1">
9		<screen index="0">
10		<bounds left="100" top="0" right="640" bottom="480" />
11		</screen>
12		<bezel name="frontpanel" element="front">
13		<bounds x="0" y="0" width="36" height="480" />
14		</bezel>
15		</view>
16		</mamelayout>
17

trunk/src/osd/modules/debugger/win/debugviewinfo.c
r249044	r249045
15	15
16	16	#include "strconv.h"
17	17
18		#include "winutil.h"
19	18
20
21	19	// debugger view styles
22	20	#define DEBUG_VIEW_STYLE WS_CHILD \| WS_VISIBLE \| WS_CLIPCHILDREN
23	21	#define DEBUG_VIEW_STYLE_EX 0
r249044	r249045
50	48
51	49	// create the child view
52	50	m_wnd = CreateWindowEx(DEBUG_VIEW_STYLE_EX, TEXT("MAMEDebugView"), NULL, DEBUG_VIEW_STYLE,
53		0, 0, 100, 100, parent, NULL, GetModuleHandle~~Uni~~(), this);
	51	0, 0, 100, 100, parent, NULL, GetModuleHandle(NULL), this);
54	52	if (m_wnd == NULL)
55	53	goto cleanup;
56	54
57	55	// create the scroll bars
58	56	m_hscroll = CreateWindowEx(HSCROLL_STYLE_EX, TEXT("SCROLLBAR"), NULL, HSCROLL_STYLE,
59		0, 0, 100, CW_USEDEFAULT, m_wnd, NULL, GetModuleHandle~~Uni~~(), this);
	57	0, 0, 100, CW_USEDEFAULT, m_wnd, NULL, GetModuleHandle(NULL), this);
60	58	m_vscroll = CreateWindowEx(VSCROLL_STYLE_EX, TEXT("SCROLLBAR"), NULL, VSCROLL_STYLE,
61		0, 0, CW_USEDEFAULT, 100, m_wnd, NULL, GetModuleHandle~~Uni~~(), this);
	59	0, 0, CW_USEDEFAULT, 100, m_wnd, NULL, GetModuleHandle(NULL), this);
62	60	if ((m_hscroll == NULL) \|\| (m_vscroll == NULL))
63	61	goto cleanup;
64	62
r249044	r249045
256	254	{
257	255	// create a combo box
258	256	HWND const result = CreateWindowEx(COMBO_BOX_STYLE_EX, TEXT("COMBOBOX"), NULL, COMBO_BOX_STYLE,
259		0, 0, 100, 1000, parent, NULL, GetModuleHandle~~Uni~~(), NULL);
	257	0, 0, 100, 1000, parent, NULL, GetModuleHandle(NULL), NULL);
260	258	SetWindowLongPtr(result, GWLP_USERDATA, userdata);
261	259	SendMessage(result, WM_SETFONT, (WPARAM)metrics().debug_font(), (LPARAM)FALSE);
262	260
r249044	r249045
791	789
792	790	// initialize the description of the window class
793	791	wc.lpszClassName = TEXT("MAMEDebugView");
794		wc.hInstance = GetModuleHandle~~Uni~~();
	792	wc.hInstance = GetModuleHandle(NULL);
795	793	wc.lpfnWndProc = &debugview_info::static_view_proc;
796	794	wc.hCursor = LoadCursor(NULL, IDC_ARROW);
797	795	wc.hIcon = LoadIcon(wc.hInstance, MAKEINTRESOURCE(2));
r249044	r249045
800	798	wc.style = 0;
801	799	wc.cbClsExtra = 0;
802	800	wc.cbWndExtra = 0;
803
804		UnregisterClass(wc.lpszClassName, wc.hInstance);
805	801
806	802	// register the class; fail if we can't
807	803	if (!RegisterClass(&wc))

trunk/src/osd/modules/debugger/win/debugwininfo.c
r249044	r249045
17	17	#include "window.h"
18	18	#include "winutf8.h"
19	19
20		#include "winutil.h"
21	20
22
23	21	bool debugwin_info::s_window_class_registered = false;
24	22
25	23
r249044	r249045
38	36	register_window_class();
39	37
40	38	m_wnd = win_create_window_ex_utf8(DEBUG_WINDOW_STYLE_EX, "MAMEDebugWindow", title, DEBUG_WINDOW_STYLE,
41		0, 0, 100, 100, win_window_list->m_hwnd, create_standard_menubar(), GetModuleHandle~~Uni~~(), this);
	39	0, 0, 100, 100, win_window_list->m_hwnd, create_standard_menubar(), GetModuleHandle(NULL), this);
42	40	if (m_wnd == NULL)
43	41	return;
44	42
r249044	r249045
582	580
583	581	// initialize the description of the window class
584	582	wc.lpszClassName = TEXT("MAMEDebugWindow");
585		wc.hInstance = GetModuleHandle~~Uni~~();
	583	wc.hInstance = GetModuleHandle(NULL);
586	584	wc.lpfnWndProc = &debugwin_info::static_window_proc;
587	585	wc.hCursor = LoadCursor(NULL, IDC_ARROW);
588	586	wc.hIcon = LoadIcon(wc.hInstance, MAKEINTRESOURCE(2));
r249044	r249045
591	589	wc.style = 0;
592	590	wc.cbClsExtra = 0;
593	591	wc.cbWndExtra = 0;
594
595		UnregisterClass(wc.lpszClassName, wc.hInstance);
596	592
597	593	// register the class; fail if we can't
598	594	if (!RegisterClass(&wc))

trunk/src/osd/modules/debugger/win/editwininfo.c
r249044	r249045
13	13
14	14	#include "strconv.h"
15	15
16		#include "winutil.h"
17	16
18
19	17	// edit box styles
20	18	#define EDIT_BOX_STYLE WS_CHILD \| WS_VISIBLE \| ES_AUTOHSCROLL
21	19	#define EDIT_BOX_STYLE_EX 0
r249044	r249045
34	32
35	33	// create an edit box and override its key handling
36	34	m_editwnd = CreateWindowEx(EDIT_BOX_STYLE_EX, TEXT("EDIT"), NULL, EDIT_BOX_STYLE,
37		0, 0, 100, 100, window(), NULL, GetModuleHandle~~Uni~~(), NULL);
	35	0, 0, 100, 100, window(), NULL, GetModuleHandle(NULL), NULL);
38	36	m_original_editproc = (WNDPROC)(FPTR)GetWindowLongPtr(m_editwnd, GWLP_WNDPROC);
39	37	SetWindowLongPtr(m_editwnd, GWLP_USERDATA, (LONG_PTR)this);
40	38	SetWindowLongPtr(m_editwnd, GWLP_WNDPROC, (LONG_PTR)&editwin_info::static_edit_proc);

trunk/src/osd/windows/input.c
r249044	r249045
38	38	#include "strconv.h"
39	39	#include "config.h"
40	40
41		#include "winutil.h"
42
43	41	//============================================================
44	42	// PARAMETERS
45	43	//============================================================
r249044	r249045
1119	1117	int didevtype_joystick = DI8DEVCLASS_GAMECTRL;
1120	1118
1121	1119	dinput_version = DIRECTINPUT_VERSION;
1122		result = DirectInput8Create(GetModuleHandle~~Uni~~(), dinput_version, IID_IDirectInput8, (void **)&dinput, NULL);
	1120	result = DirectInput8Create(GetModuleHandle(NULL), dinput_version, IID_IDirectInput8, (void **)&dinput, NULL);
1123	1121	if (result != DI_OK)
1124	1122	{
1125	1123	dinput_version = 0;
r249044	r249045
1132	1130
1133	1131	// first attempt to initialize DirectInput at the current version
1134	1132	dinput_version = DIRECTINPUT_VERSION;
1135		result = DirectInputCreate(GetModuleHandle~~Uni~~(), dinput_version, &dinput, NULL);
	1133	result = DirectInputCreate(GetModuleHandle(NULL), dinput_version, &dinput, NULL);
1136	1134	if (result != DI_OK)
1137	1135	{
1138	1136	// if that fails, try version 5
1139	1137	dinput_version = 0x0500;
1140		result = DirectInputCreate(GetModuleHandle~~Uni~~(), dinput_version, &dinput, NULL);
	1138	result = DirectInputCreate(GetModuleHandle(NULL), dinput_version, &dinput, NULL);
1141	1139	if (result != DI_OK)
1142	1140	{
1143	1141	// if that fails, try version 3
1144	1142	dinput_version = 0x0300;
1145		result = DirectInputCreate(GetModuleHandle~~Uni~~(), dinput_version, &dinput, NULL);
	1143	result = DirectInputCreate(GetModuleHandle(NULL), dinput_version, &dinput, NULL);
1146	1144	if (result != DI_OK)
1147	1145	{
1148	1146	dinput_version = 0;

trunk/src/osd/windows/output.c
r249044	r249045
17	17	// MAMEOS headers
18	18	#include "output.h"
19	19
20		#include "winutil.h"
21	20
22	21
23
24	22	//============================================================
25	23	// CONSTANTS
26	24	//============================================================
r249044	r249045
103	101	1, 1,
104	102	NULL,
105	103	NULL,
106		GetModuleHandle~~Uni~~(),
	104	GetModuleHandle(NULL),
107	105	NULL);
108	106	assert(output_hwnd != NULL);
109	107
r249044	r249045
169	167
170	168	// initialize the description of the window class
171	169	wc.lpszClassName = OUTPUT_WINDOW_CLASS;
172		wc.hInstance = GetModuleHandle~~Uni~~();
	170	wc.hInstance = GetModuleHandle(NULL);
173	171	wc.lpfnWndProc = output_window_proc;
174
175		UnregisterClass(wc.lpszClassName, wc.hInstance);
176	172
177	173	// register the class; fail if we can't
178	174	if (!RegisterClass(&wc))

trunk/src/osd/windows/window.c
r249044	r249045
35	35	#include "config.h"
36	36	#include "winutf8.h"
37	37
38		#include "winutil.h"
39
40	38	extern int drawnone_init(running_machine &machine, osd_draw_callbacks *callbacks);
41	39	extern int drawgdi_init(running_machine &machine, osd_draw_callbacks *callbacks);
42	40	extern int drawdd_init(running_machine &machine, osd_draw_callbacks *callbacks);
r249044	r249045
887	885
888	886	// initialize the description of the window class
889	887	wc.lpszClassName = TEXT("MAME");
890		wc.hInstance = GetModuleHandle~~Uni~~();
	888	wc.hInstance = GetModuleHandle(NULL);
891	889	wc.lpfnWndProc = winwindow_video_window_proc_ui;
892	890	wc.hCursor = LoadCursor(NULL, IDC_ARROW);
893	891	wc.hIcon = LoadIcon(wc.hInstance, MAKEINTRESOURCE(2));
894
895		UnregisterClass(wc.lpszClassName, wc.hInstance);
896	892
897	893	// register the class; fail if we can't
898	894	if (!RegisterClass(&wc))
r249044	r249045
1195	1191	monitorbounds.left() + 100, monitorbounds.top() + 100,
1196	1192	NULL,//(win_window_list != NULL) ? win_window_list->m_hwnd : NULL,
1197	1193	menu,
1198		GetModuleHandle~~Uni~~(),
	1194	GetModuleHandle(NULL),
1199	1195	NULL);
1200	1196	if (m_hwnd == NULL)
1201	1197	return 1;

trunk/src/osd/windows/winmain.c
r249044	r249045
1321	1321	dynamic_bind<PIMAGE_NT_HEADERS (WINAPI *)(PVOID)> image_nt_header(TEXT("dbghelp.dll"), "ImageNtHeader");
1322	1322
1323	1323	// start with the image base
1324		PVOID base = reinterpret_cast<PVOID>(GetModuleHandle~~Uni~~());
	1324	PVOID base = reinterpret_cast<PVOID>(GetModuleHandle(NULL));
1325	1325	assert(base != NULL);
1326	1326
1327	1327	// make sure we have the functions we need

trunk/src/osd/windows/winutil.c
r249044	r249045
92	92	is_first_time = FALSE;
93	93
94	94	// get the current module
95		module = GetModuleHandle~~Uni~~();
	95	module = GetModuleHandle(NULL);
96	96	if (!module)
97	97	return FALSE;
98	98	image_ptr = (BYTE*) module;
r249044	r249045
122	122	}
123	123	return is_gui_frontend;
124	124	}
125
126		//-------------------------------------------------
127		// Universal way to get module handle
128		//-------------------------------------------------
129
130		HMODULE WINAPI GetModuleHandleUni()
131		{
132		MEMORY_BASIC_INFORMATION mbi;
133		VirtualQuery((LPCVOID)GetModuleHandleUni, &mbi, sizeof(mbi));
134		return (HMODULE)mbi.AllocationBase;
135		}

trunk/src/osd/windows/winutil.h
r249044	r249045
15	15	file_error win_error_to_file_error(DWORD error);
16	16	osd_dir_entry_type win_attributes_to_entry_type(DWORD attributes);
17	17	BOOL win_is_gui_application(void);
18		HMODULE WINAPI GetModuleHandleUni();
19	18
20	19	#endif // __WINUTIL__

https://github.com/mamedev/mame/commit/22eb94cb71d5066a9f6a5f6b017effbe54626328

199869 Revisions