Previous 199869 Revisions Next

r39866 Tuesday 21st July, 2015 at 00:30:04 UTC by Joakim Larsson Edström
started support for CPU-1 Centronics port on Port B
[src/emu/machine]68230pit.c 68230pit.h

trunk/src/emu/machine/68230pit.c
r248377r248378
6767  m_pbcr = 0;
6868  m_padr = 0;
6969  m_pbdr = 0;
70  m_psr = 0;
7071}
7172
7273WRITE8_MEMBER( pit68230_device::data_w )
r248377r248378
9899    printf("PBCR");
99100    m_pbcr = data;
100101    break;
102  case PIT_68230_PADR:
103    printf("PADR");
104    m_padr = data;
105    break;
106  case PIT_68230_PSR:
107    printf("PSR");
108    m_padr = data;
109    break;
101110  default:
102111    printf("unhandled register %02x", offset);
103112  }
r248377r248378
139148    printf("PADR");
140149    data = m_padr;
141150    break;
142  case PIT_68230_PBDR:
151  case PIT_68230_PBDR:
152    /* 4.6.2. PORT B DATA REGISTER (PBDR). The port B data register is a holding register for moving data
153to and from port B pins. The port B data direction register determines whether each pin is an input (zero)
154or an output (one). This register is readable and writable at all times. Depending on the chosen mode/submode,
155reading or writing may affect the double-buffered handshake mechanism. The port B data register is not affected
156by the assertion of the RESET pin. PB0-PB7 sits on pins 17-24 on a 48 pin DIP package */
143157    printf("PBDR");
144158    data = m_pbdr;
159    //    data = (m_pbdr & 0xfc) | 1; // CPU-1 centronics interface expects to see 2 lowest bits equal 1 for printer
145160    break;
161  case PIT_68230_PSR:
162    printf("PSR");
163    data = m_psr;
164    //    data = m_psr | 1; // CPU-1 centronics interface expects status to be non zero
165    break;
146166  default:
147167    printf("unhandled register %02x", offset);
168    data = 0;
148169  }
149170  printf("\n");
150171
trunk/src/emu/machine/68230pit.h
r248377r248378
6666   UINT8  m_pbcr;  // Port B Control register
6767   UINT8  m_padr;  // Port A Data register
6868   UINT8  m_pbdr;  // Port B Data register
69   UINT8  m_psr;   // Port Status Register
6970};
7071
7172


Previous 199869 Revisions Next


© 1997-2024 The MAME Team