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r37198 Wednesday 15th April, 2015 at 21:16:05 UTC by Curt Coder
(MESS) pet: Implemented write mode on the Commodore 8050/8250/SFD-1001 floppy drives. [Curt Coder]
(MESS) victor9k: Separated read/write modes in the floppy controller. (nw)
fdc_pll: Removed write_next_bit_prev_cell hack. (nw)
[src/emu/bus/ieee488]c8050fdc.c c8050fdc.h
[src/emu/machine]fdc_pll.c fdc_pll.h
[src/mess/machine]victor9k_fdc.c victor9k_fdc.h

trunk/src/emu/bus/ieee488/c8050fdc.c
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1313
1414   TODO:
1515
16   - write mode
1716    - write protect
18    - separate read/write methods
1917
2018*/
2119
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2826//**************************************************************************
2927
3028#define LOG 0
29#define LOG_MORE 0
30#define LOG_BITS 0
3131
3232#define GCR_DECODE(_e, _i) \
3333   ((BIT(_e, 6) << 7) | (BIT(_i, 7) << 6) | (_e & 0x33) | (BIT(_e, 2) << 3) | (_i & 0x04))
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7474//-------------------------------------------------
7575
7676c8050_fdc_t::c8050_fdc_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
77   device_t(mconfig, C8050_FDC, "C8050 FDC", tag, owner, clock, "c8050fdc", __FILE__),
77   device_t(mconfig, C8050_FDC, "Commodore 8050 FDC", tag, owner, clock, "c8050fdc", __FILE__),
7878   m_write_sync(*this),
7979   m_write_ready(*this),
8080   m_write_brdy(*this),
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8989   m_ds(0),
9090   m_drv_sel(0),
9191   m_mode_sel(0),
92   m_rw_sel(0)
92   m_rw_sel(1)
9393{
9494   cur_live.tm = attotime::never;
9595   cur_live.state = IDLE;
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210210   {
211211      live_sync();
212212      m_ds = cur_live.ds = ds;
213      pll_reset(cur_live.tm, attotime::from_hz(clock() / (16 - m_ds)));
213      pll_reset(cur_live.tm);
214      if (LOG) logerror("%s %s DS %u\n", machine().time().as_string(), machine().describe_context(), ds);
214215      checkpoint();
215216      live_run();
216217   }
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240241   cur_live.rw_sel = m_rw_sel;
241242   cur_live.pi = m_pi;
242243
243   pll_reset(cur_live.tm, attotime::from_hz(clock() / (16 - m_ds)));
244   pll_reset(cur_live.tm);
244245   checkpoint_live = cur_live;
245246   pll_save_checkpoint();
246247
247248   live_run();
248249}
249250
250void c8050_fdc_t::pll_reset(const attotime &when, const attotime &clock)
251void c8050_fdc_t::pll_reset(const attotime &when)
251252{
252253   cur_pll.reset(when);
253   cur_pll.set_clock(clock);
254   cur_pll.set_clock(attotime::from_hz(clock() / (16 - m_ds)));
254255}
255256
256257void c8050_fdc_t::pll_start_writing(const attotime &tm)
257258{
258259   cur_pll.start_writing(tm);
260   pll_reset(cur_live.tm);
259261}
260262
261263void c8050_fdc_t::pll_commit(floppy_image_device *floppy, const attotime &tm)
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266268void c8050_fdc_t::pll_stop_writing(floppy_image_device *floppy, const attotime &tm)
267269{
268270   cur_pll.stop_writing(floppy, tm);
271   pll_reset(cur_live.tm);
269272}
270273
271274void c8050_fdc_t::pll_save_checkpoint()
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285288
286289bool c8050_fdc_t::pll_write_next_bit(bool bit, attotime &tm, floppy_image_device *floppy, const attotime &limit)
287290{
288   return cur_pll.write_next_bit_prev_cell(bit, tm, floppy, limit);
291   return cur_pll.write_next_bit(bit, tm, floppy, limit);
289292}
290293
291294void c8050_fdc_t::checkpoint()
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366369            return;
367370
368371         // read bit
369         int bit = pll_get_next_bit(cur_live.tm, get_floppy(), limit);
370         if(bit < 0)
371            return;
372         int bit = 0;
373         if (cur_live.rw_sel) {
374            bit = pll_get_next_bit(cur_live.tm, get_floppy(), limit);
375            if(bit < 0)
376               return;
377         }
372378
379         // write bit
380         int write_bit = BIT(cur_live.shift_reg_write, 9);
381         if (!cur_live.rw_sel) { // TODO WPS
382            /*
383            write precompensation
384
385            UA5.A = UM6.Qc
386            UA5.B = !(!(!BRDY && UM6.Qa) && !(BRDY && E7))
387            UA5.C0 = UA4.Qb = bit clock delayed 333ns
388            UA5.C1 = UA4.Qa = bit clock delayed 166ns
389            UA5.C2 = UA4.Qc = bit clock delayed 499ns
390            UA5.C3 = UA5.Qb = bit clock delayed 333ns
391
392            DATA OUT = !(!BITCLK || !(UA5.Y && !(WRITE_ENABLE && !UM6.Qb)))
393            */
394            if (pll_write_next_bit(write_bit, cur_live.tm, get_floppy(), limit))
395               return;
396         }
397
398         // clock read shift register
373399         cur_live.shift_reg <<= 1;
374400         cur_live.shift_reg |= bit;
375401         cur_live.shift_reg &= 0x3ff;
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378404         int sync = !((cur_live.shift_reg == 0x3ff) && cur_live.rw_sel);
379405
380406         // bit counter
381         if (cur_live.rw_sel) {
382            if (!sync) {
383               cur_live.bit_counter = 0;
384            } else if (cur_live.sync) {
385               cur_live.bit_counter++;
386               if (cur_live.bit_counter == 10) {
387                  cur_live.bit_counter = 0;
388               }
389            }
390         } else {
407         if (!sync) {
408            cur_live.bit_counter = 0;
409         } else if (cur_live.sync) {
391410            cur_live.bit_counter++;
392411            if (cur_live.bit_counter == 10) {
393412               cur_live.bit_counter = 0;
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403422
404423         cur_live.e = m_gcr_rom->base()[cur_live.i];
405424
406         if (LOG) logerror("%s cyl %u bit %u sync %u bc %u sr %03x i %03x e %02x\n",cur_live.tm.as_string(),get_floppy()->get_cyl(),bit,sync,cur_live.bit_counter,cur_live.shift_reg,cur_live.i,cur_live.e);
407
408425         // byte ready
409426         int ready = !(cur_live.bit_counter == 9); // 74190 _RC, should be triggered on the falling edge of the clock
410427         int brdy = ready; // 74190 TC
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412429         // GCR error
413430         int error = !(ready || BIT(cur_live.e, 3));
414431
415         // write bit
416         if (!cur_live.rw_sel) { // TODO WPS
417            int write_bit = BIT(cur_live.shift_reg_write, 9);
418            if (LOG) logerror("%s writing bit %u sr %03x\n",cur_live.tm.as_string(),write_bit,cur_live.shift_reg_write);
419            pll_write_next_bit(write_bit, cur_live.tm, get_floppy(), limit);
432         if (LOG_BITS) {
433            if (cur_live.rw_sel) {
434               logerror("%s cyl %u bit %u sync %u bc %u sr %03x i %03x e %02x\n",cur_live.tm.as_string(),get_floppy()->get_cyl(),bit,sync,cur_live.bit_counter,cur_live.shift_reg,cur_live.i,cur_live.e);
435            } else {
436               logerror("%s cyl %u writing bit %u bc %u sr %03x i %03x e %02x\n",cur_live.tm.as_string(),get_floppy()->get_cyl(),write_bit,cur_live.bit_counter,cur_live.shift_reg_write,cur_live.i,cur_live.e);
437            }
420438         }
421439
422440         if (!ready) {
423441            // load write shift register
424442            cur_live.shift_reg_write = GCR_ENCODE(cur_live.e, cur_live.i);
425443
426            if (LOG) logerror("%s load write shift register %03x\n",cur_live.tm.as_string(),cur_live.shift_reg_write);
444            if (LOG_BITS) logerror("%s load write shift register %03x\n",cur_live.tm.as_string(),cur_live.shift_reg_write);
427445         } else {
428446            // clock write shift register
429447            cur_live.shift_reg_write <<= 1;
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431449         }
432450
433451         if (ready != cur_live.ready) {
434            if (LOG) logerror("%s READY %u : %02x\n", cur_live.tm.as_string(),ready,GCR_DECODE(cur_live.e, cur_live.i));
452            if (cur_live.rw_sel && !ready)
453               if (LOG) logerror("%s READY %u : %02x\n", cur_live.tm.as_string(),ready,GCR_DECODE(cur_live.e, cur_live.i));
435454            cur_live.ready = ready;
436455            syncpoint = true;
437456         }
438457
439458         if (brdy != cur_live.brdy) {
440            if (LOG) logerror("%s BRDY %u\n", cur_live.tm.as_string(), brdy);
459            if (LOG_MORE) logerror("%s BRDY %u\n", cur_live.tm.as_string(), brdy);
441460            cur_live.brdy = brdy;
442461            syncpoint = true;
443462         }
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449468         }
450469
451470         if (error != cur_live.error) {
452            if (LOG) logerror("%s ERROR %u\n", cur_live.tm.as_string(), error);
471            if (LOG_MORE) logerror("%s ERROR %u\n", cur_live.tm.as_string(), error);
453472            cur_live.error = error;
454473            syncpoint = true;
455474         }
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462481      }
463482
464483      case RUNNING_SYNCPOINT: {
465         if (LOG) {
466            if (!cur_live.sync) logerror("%s SYNC\n",cur_live.tm.as_string());
467            if (!cur_live.ready && cur_live.bit_counter == 9) logerror("%s DATA %02x\n",cur_live.tm.as_string(),GCR_DECODE(cur_live.e,cur_live.i));
468         }
469484         m_write_ready(cur_live.ready);
470485         m_write_brdy(cur_live.brdy);
471486         m_write_sync(cur_live.sync);
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484499   UINT8 e = checkpoint_live.e;
485500   offs_t i = checkpoint_live.i;
486501
487   UINT8 data = GCR_DECODE(e, i);
488
489   if (LOG)logerror("%s %s VIA reads data %02x (%03x)\n", machine().time().as_string(), machine().describe_context(), data, checkpoint_live.shift_reg);
490
491   return data;
502   return GCR_DECODE(e, i);
492503}
493504
494505WRITE8_MEMBER( c8050_fdc_t::write )
495506{
507   if (LOG) logerror("%s %s PI %02x\n", machine().time().as_string(), machine().describe_context(), data);
508
496509   if (m_pi != data)
497510   {
498511      live_sync();
499512      m_pi = cur_live.pi = data;
500513      checkpoint();
501      if (LOG) logerror("%s %s PI %02x\n", machine().time().as_string(), machine().describe_context(), data);
502514      live_run();
503515   }
504516}
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548560      checkpoint();
549561      if (LOG) logerror("%s %s RW SEL %u\n", machine().time().as_string(), machine().describe_context(), state);
550562      if (m_rw_sel) {
551         pll_stop_writing(get_floppy(), machine().time());
563         pll_stop_writing(get_floppy(), cur_live.tm);
552564      } else {
553         pll_start_writing(machine().time());
565         pll_start_writing(cur_live.tm);
554566      }
555567      live_run();
556568   }
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616628
617629WRITE_LINE_MEMBER( c8050_fdc_t::pull_sync_w )
618630{
619   if (LOG) logerror("%s %s PULL SYNC %u\n", machine().time().as_string(), machine().describe_context(), state);
631   if (LOG_MORE) logerror("%s %s PULL SYNC %u\n", machine().time().as_string(), machine().describe_context(), state);
620632}
trunk/src/emu/bus/ieee488/c8050fdc.h
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150150   void live_start();
151151   void checkpoint();
152152   void rollback();
153   void pll_reset(const attotime &when, const attotime &clock);
153   void pll_reset(const attotime &when);
154154   void pll_start_writing(const attotime &tm);
155155   void pll_commit(floppy_image_device *floppy, const attotime &tm);
156156   void pll_stop_writing(floppy_image_device *floppy, const attotime &tm);
trunk/src/emu/machine/fdc_pll.c
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2222void fdc_pll_t::reset(const attotime &when)
2323{
2424   ctime = when;
25   write_ctime = when;
2625   phase_adjust = attotime::zero;
2726   freq_hist = 0;
2827   write_position = 0;
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6665   if(next > limit)
6766      return -1;
6867
69   write_ctime = ctime;
7068   ctime = next;
7169   tm = next;
7270
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132130   ctime = etime;
133131   return false;
134132}
135
136bool fdc_pll_t::write_next_bit_prev_cell(bool bit, attotime &tm, floppy_image_device *floppy, const attotime &limit)
137{
138   if(write_start_time.is_never()) {
139      write_start_time = write_ctime;
140      write_position = 0;
141   }
142
143   attotime etime = write_ctime + period;
144   if(etime > limit)
145      return true;
146
147   if(bit && write_position < ARRAY_LENGTH(write_buffer))
148      write_buffer[write_position++] = write_ctime + period/2;
149
150   return false;
151}
trunk/src/emu/machine/fdc_pll.h
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1212public:
1313   attotime ctime, period, min_period, max_period, period_adjust_base, phase_adjust;
1414
15   attotime write_ctime;
1615   attotime write_start_time;
1716   attotime write_buffer[32];
1817   int write_position;
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2221   void reset(const attotime &when);
2322   int get_next_bit(attotime &tm, floppy_image_device *floppy, const attotime &limit);
2423   bool write_next_bit(bool bit, attotime &tm, floppy_image_device *floppy, const attotime &limit);
25   bool write_next_bit_prev_cell(bool bit, attotime &tm, floppy_image_device *floppy, const attotime &limit);
2624   void start_writing(const attotime &tm);
2725   void commit(floppy_image_device *floppy, const attotime &tm);
2826   void stop_writing(floppy_image_device *floppy, const attotime &tm);
trunk/src/mess/machine/victor9k_fdc.c
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5454#define LOG 0
5555#define LOG_VIA 0
5656#define LOG_SCP 0
57#define LOG_BITS 0
5758
5859#define I8048_TAG       "5d"
5960#define M6522_4_TAG     "1f"
r245709r245710
10691070   cur_live.wrsync = m_wrsync;
10701071   cur_live.erase = m_erase;
10711072
1072   pll_reset(cur_live.tm, attotime::from_nsec(2130));
1073   pll_reset(cur_live.tm);
10731074   checkpoint_live = cur_live;
10741075   pll_save_checkpoint();
10751076
10761077   live_run();
10771078}
10781079
1079void victor_9000_fdc_t::pll_reset(const attotime &when, const attotime &clock)
1080void victor_9000_fdc_t::pll_reset(const attotime &when)
10801081{
10811082   cur_pll.reset(when);
1082   cur_pll.set_clock(clock);
1083   cur_pll.set_clock(attotime::from_nsec(2130));
10831084}
10841085
10851086void victor_9000_fdc_t::pll_start_writing(const attotime &tm)
10861087{
10871088   cur_pll.start_writing(tm);
1089   pll_reset(cur_live.tm);
10881090}
10891091
10901092void victor_9000_fdc_t::pll_commit(floppy_image_device *floppy, const attotime &tm)
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10951097void victor_9000_fdc_t::pll_stop_writing(floppy_image_device *floppy, const attotime &tm)
10961098{
10971099   cur_pll.stop_writing(floppy, tm);
1100   pll_reset(cur_live.tm);
10981101}
10991102
11001103void victor_9000_fdc_t::pll_save_checkpoint()
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11141117
11151118bool victor_9000_fdc_t::pll_write_next_bit(bool bit, attotime &tm, floppy_image_device *floppy, const attotime &limit)
11161119{
1117   return cur_pll.write_next_bit_prev_cell(bit, tm, floppy, limit);
1120   return cur_pll.write_next_bit(bit, tm, floppy, limit);
11181121}
11191122
11201123void victor_9000_fdc_t::checkpoint()
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11971200            return;
11981201
11991202         // read bit
1200         int bit = pll_get_next_bit(cur_live.tm, get_floppy(), limit);
1201         if(bit < 0)
1202            return;
1203         int bit = 0;
1204         if (cur_live.drw) {
1205            bit = pll_get_next_bit(cur_live.tm, get_floppy(), limit);
1206            if(bit < 0)
1207               return;
1208         }
12031209
1210         // write bit
1211         int write_bit = 0;
1212         if (!cur_live.drw) { // TODO WPS
1213            write_bit = BIT(cur_live.shift_reg_write, 9);
1214            if (pll_write_next_bit(write_bit, cur_live.tm, get_floppy(), limit))
1215               return;
1216         }
1217
1218         // clock read shift register
12041219         cur_live.shift_reg <<= 1;
12051220         cur_live.shift_reg |= bit;
12061221         cur_live.shift_reg &= 0x3ff;
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12611276         // GCR error
12621277         int gcr_err = !(brdy || BIT(cur_live.e, 3));
12631278
1264         // write bit
1265         if (!cur_live.drw) { // TODO WPS
1266            int write_bit = BIT(cur_live.shift_reg_write, 9);
1267            if (LOG) logerror("%s writing bit %u sr %03x\n",cur_live.tm.as_string(),write_bit,cur_live.shift_reg_write);
1268            pll_write_next_bit(write_bit, cur_live.tm, get_floppy(), limit);
1279         if (LOG_BITS) {
1280            if (cur_live.drw) {
1281               logerror("%s cyl %u bit %u sync %u bc %u sr %03x i %03x e %02x\n",cur_live.tm.as_string(),get_floppy()->get_cyl(),bit,sync,cur_live.bit_counter,cur_live.shift_reg,cur_live.i,cur_live.e);
1282            } else {
1283               logerror("%s cyl %u writing bit %u bc %u sr %03x i %03x e %02x\n",cur_live.tm.as_string(),get_floppy()->get_cyl(),write_bit,cur_live.bit_counter,cur_live.shift_reg_write,cur_live.i,cur_live.e);
1284            }
12691285         }
12701286
12711287         if (!brdy) {
trunk/src/mess/machine/victor9k_fdc.h
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218218
219219   floppy_image_device* get_floppy();
220220   void live_start();
221   void pll_reset(const attotime &when, const attotime &clock);
221   void pll_reset(const attotime &when);
222222   void pll_start_writing(const attotime &tm);
223223   void pll_commit(floppy_image_device *floppy, const attotime &tm);
224224   void pll_stop_writing(floppy_image_device *floppy, const attotime &tm);

https://github.com/mamedev/mame/commit/19bbe2ac4dbe3fe5801bb262d685220121f3c408

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