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r37145 Sunday 12th April, 2015 at 21:04:47 UTC by Ted Green
Code cleanup

[src/emu/video]	voodoo_pci.c voodoo_pci.h
[src/mame/drivers]	iteagle.c
[src/mame/machine]	iteagle_fpga.c

trunk/src/emu/video/voodoo_pci.c

r245656	r245657
31	31
32	32	void voodoo_pci_device::set_cpu_tag(const char *_cpu_tag)
33	33	{
34		cpu_tag = _cpu_tag;
	34	m_cpu_tag = _cpu_tag;
35	35	}
36	36
37	37	void voodoo_pci_device::device_start()
38	38	{
39		voodoo_device::static_set_cpu_tag(m_voodoo, cpu_tag);
	39	voodoo_device::static_set_cpu_tag(m_voodoo, m_cpu_tag);
40	40	pci_device::device_start();
41	41	add_map(32*1024*1024, M_MEM, FUNC(voodoo_pci_device::reg_map));
42	42	add_map(32*1024*1024, M_MEM, FUNC(voodoo_pci_device::lfb_map));
r245656	r245657
51	51	void voodoo_pci_device::map_extra(UINT64 memory_window_start, UINT64 memory_window_end, UINT64 memory_offset, address_space *memory_space,
52	52	UINT64 io_window_start, UINT64 io_window_end, UINT64 io_offset, address_space *io_space)
53	53	{
54		logerror("%s: map_extra\n", tag());
	54	logerror("%s: map_extra\n", this->tag());
55	55	// Really awkward way of getting vga address space mapped
56	56	// Should really be dependent on voodoo VGAINIT0 bit 8 and IO base + 0xc3 bit 0
57	57	if (1) {
r245656	r245657
75	75	start = (start & 0xFFFF0000) + 0x300;
76	76	UINT64 end = (start & 0xFFFF0000) + 0x3ef;
77	77	space->install_device_delegate(start, end, *this, bi.map);
78		logerror("%s: map %s at %0*x-%0*x\n", tag(), bi.map.name(), bi.flags & M_IO ? 4 : 8, UINT32(start), bi.flags & M_IO ? 4 : 8, UINT32(end));
	78	logerror("%s: map %s at %0*x-%0*x\n", this->tag(), bi.map.name(), bi.flags & M_IO ? 4 : 8, UINT32(start), bi.flags & M_IO ? 4 : 8, UINT32(end));
79	79	}
80	80
81	81	}

trunk/src/emu/video/voodoo_pci.h

r245656	r245657
27	27
28	28	private:
29	29	required_device<voodoo_banshee_device> m_voodoo;
30		const char *cpu_tag;
	30	const char *m_cpu_tag;
31	31
32	32	DECLARE_ADDRESS_MAP(reg_map, 32);
33	33	DECLARE_ADDRESS_MAP(lfb_map, 32);

trunk/src/mame/drivers/iteagle.c

r245656	r245657
152	152	MCFG_SCREEN_VIDEO_ATTRIBUTES(VIDEO_UPDATE_BEFORE_VBLANK)
153	153	MCFG_SCREEN_REFRESH_RATE(59)
154	154	MCFG_SCREEN_SIZE(512, 384)
155		MCFG_SCREEN_VISIBLE_AREA(0, 511, 0, 383)
156	155	MCFG_SCREEN_UPDATE_DEVICE(":pci:09.0", voodoo_pci_device, screen_update)
157	156
158	157

trunk/src/mame/machine/iteagle_fpga.c

r245656	r245657
47	47	//m_rtc_regs[0] = 0x11223344;
48	48	switch ((machine().root_device().ioport("VERSION")->read()>>4)&0xF) {
49	49	case 3:
50		m_seq = 0x0a0b0a; // gt02o
51		break;
	50	m_seq = 0x0a0b0a; // gt02
	51	break;
52	52	case 4:
53		m_seq = 0x0a020b; // gt04
54		break;
	53	m_seq = 0x0a020b; // gt04
	54	break;
55	55	case 5:
56		m_seq = 0x0b0a0c; // gt05
57		break;
	56	m_seq = 0x0b0a0c; // gt05
	57	break;
58	58	default:
59		m_seq = 0x0c0b0d; // gt02
60		break;
61		}
	59	m_seq = 0x0c0b0d; // gt06
	60	break;
	61	}
62	62
63		m_seq_rem1 = 0;
64		m_seq_rem2 = 0;
	63	m_seq_rem1 = 0;
	64	m_seq_rem2 = 0;
65	65
66	66	// 0x00&0x2 == 1 for boot
67	67	//m_fpga_regs[0x00/4] =  0xC1110002; // 0xCF000002;// byte 3 is voltage sensor? high = 0x40 good = 0xC0 0xF0 0xFF; //0x80 0x30 0x00FF = voltage low
r245656	r245657
97	97	UINT32 val1, feed;
98	98	feed = ((m_seq<<4) ^ m_seq)>>7;
99	99	if (data & 0x1) {
100		val1 = ((m_seq & 0x2)<<1) | ((m_seq & 0x4)>>1) | ((m_seq & 0x8)>>3);
101		m_seq_rem1 = ((m_seq & 0x10)) | ((m_seq & 0x20)>>2) | ((m_seq & 0x40)>>4);
102		m_seq_rem2 = ((m_seq & 0x80)>>1) | ((m_seq & 0x100)>>3) | ((m_seq & 0x200)>>5);
103		m_seq = (m_seq>>9) | ((feed&0x1ff)<<15);
104		m_fpga_regs[offset] = (m_fpga_regs[offset]&0xFFFFFF00) | ((val1 + m_seq_rem1 + m_seq_rem2)&0xFF);
	100	val1 = ((m_seq & 0x2)<<1) | ((m_seq & 0x4)>>1) | ((m_seq & 0x8)>>3);
	101	m_seq_rem1 = ((m_seq & 0x10)) | ((m_seq & 0x20)>>2) | ((m_seq & 0x40)>>4);
	102	m_seq_rem2 = ((m_seq & 0x80)>>1) | ((m_seq & 0x100)>>3) | ((m_seq & 0x200)>>5);
	103	m_seq = (m_seq>>9) | ((feed&0x1ff)<<15);
	104	m_fpga_regs[offset] = (m_fpga_regs[offset]&0xFFFFFF00) | ((val1 + m_seq_rem1 + m_seq_rem2)&0xFF);
105	105	} else if (data & 0x2) {
106		val1 = ((m_seq & 0x2)<<1) | ((m_seq & 0x4)>>1) | ((m_seq & 0x8)>>3);
107		m_seq_rem1 = ((m_seq & 0x10)) | ((m_seq & 0x20)>>2) | ((m_seq & 0x40)>>4);
108		m_seq = (m_seq>>6) | ((feed&0x3f)<<18);
109		m_fpga_regs[offset] = (m_fpga_regs[offset]&0xFFFFFF00) | ((val1 + m_seq_rem1 + m_seq_rem2)&0xFF);
	106	val1 = ((m_seq & 0x2)<<1) | ((m_seq & 0x4)>>1) | ((m_seq & 0x8)>>3);
	107	m_seq_rem1 = ((m_seq & 0x10)) | ((m_seq & 0x20)>>2) | ((m_seq & 0x40)>>4);
	108	m_seq = (m_seq>>6) | ((feed&0x3f)<<18);
	109	m_fpga_regs[offset] = (m_fpga_regs[offset]&0xFFFFFF00) | ((val1 + m_seq_rem1 + m_seq_rem2)&0xFF);
110	110	} else {
111	111	val1 = ((m_seq & 0x2)<<6) | ((m_seq & 0x4)<<4) | ((m_seq & 0x8)<<2) | ((m_seq & 0x10)<<0)
112	112	| ((m_seq & 0x20)>>2) | ((m_seq & 0x40)>>4) | ((m_seq & 0x80)>>6) | ((m_seq & 0x100)>>8);
113		m_seq = (m_seq>>8) | ((feed&0xff)<<16);
114		m_fpga_regs[offset] = (m_fpga_regs[offset]&0xFFFFFF00) | ((val1 + m_seq_rem1 + m_seq_rem2) & 0xff);
	113	m_seq = (m_seq>>8) | ((feed&0xff)<<16);
	114	m_fpga_regs[offset] = (m_fpga_regs[offset]&0xFFFFFF00) | ((val1 + m_seq_rem1 + m_seq_rem2) & 0xff);
115	115	}
116	116	if (0 && LOG_FPGA)
117	117	logerror("%s:fpga update_sequence In: %02X Seq: %06X Out: %02X\n", machine().describe_context(), data, m_seq, m_fpga_regs[offset]&0xff);

https://github.com/mamedev/mame/commit/c81f94ab513f83c60ab3d60b8d797985f709c5b8

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