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r37130 Sunday 12th April, 2015 at 07:12:26 UTC by Fabio Priuli
(MESS) gameboy: removed separate implementation of
MBC-1 collection cart, since it is just plain MBC-1 mapper
with slightly different address lines wiring. [Tauwasser]

out of whatsnew: thanks a lot Tauwasser for the contribution!
I have made some minor changes to adhere to current MESS conventions,
but I think the spirit of the patch has been kept :)
[hash]gbcolor.xml
[src/emu/bus/gameboy]gb_slot.c gb_slot.h mbc.c mbc.h
[src/mess/drivers]gb.c

trunk/hash/gbcolor.xml
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55845584   <software name="bombmsel">
55855585      <!-- Notes: GBC only -->
55865586      <description>Bomberman Selection (Kor)</description>
5587      <year>1996?</year>
5587      <year>2003</year>
55885588      <publisher>Hudson Soft</publisher>
55895589      <info name="serial" value="CGB-B2CK-KOR"/>
55905590      <part name="cart" interface="gameboy_cart">
trunk/src/emu/bus/gameboy/gb_slot.c
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300300      else
301301         m_type = get_cart_type(ROM + offset, len - offset);
302302
303      // setup additional mask/shift for MBC1 variants:
304      // a few game collections use the same mapper with slightly
305      // different lines connection with the ROM / RAM
306      if (m_type == GB_MBC_MBC1 || m_type == GB_MBC_188IN1)
307         m_cart->set_additional_wirings(0x1f, 0);
308      if (m_type == GB_MBC_MBC1_COL)
309         m_cart->set_additional_wirings(0x0f, -1);
310
303311      // setup RAM/NVRAM/RTC/RUMBLE
304312      if (software_entry() != NULL)
305313      {
trunk/src/emu/bus/gameboy/gb_slot.h
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2222   GB_MBC_MBC6,         /*    ?? ROM,  32KB SRAM                         */
2323   GB_MBC_MBC7,         /*    ?? ROM,    ?? RAM                          */
2424   GB_MBC_WISDOM,       /*    ?? ROM,    ?? RAM - Wisdom tree controller */
25   GB_MBC_MBC1_COL,     /*   1MB ROM,    ?? RAM - MBC1 variant for multigame carts  */
25   GB_MBC_MBC1_COL,     /*   1MB ROM,  32KB RAM - workaround for MBC1 on PCB that maps rom address lines differently */
2626   GB_MBC_YONGYONG,     /*    ?? ROM,    ?? RAM - Appears in Sonic 3D Blast 5 pirate */
2727   GB_MBC_LASAMA,       /*    ?? ROM,    ?? RAM - Appears in La Sa Ma */
2828   GB_MBC_ATVRACIN,
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6666   void rom_map_setup(UINT32 size);
6767   void ram_map_setup(UINT8 banks);
6868
69   virtual void set_additional_wirings(UINT8 mask, int shift) { }   // MBC-1 will then overwrite this!
6970   void set_has_timer(bool val) { has_timer = val; }
7071   void set_has_rumble(bool val) { has_rumble = val; }
7172   void set_has_battery(bool val) { has_battery = val; }
trunk/src/emu/bus/gameboy/mbc.c
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1717//-------------------------------------------------
1818
1919const device_type GB_ROM_MBC1 = &device_creator<gb_rom_mbc1_device>;
20const device_type GB_ROM_MBC1_COL = &device_creator<gb_rom_mbc1col_device>;
2120const device_type GB_ROM_MBC2 = &device_creator<gb_rom_mbc2_device>;
2221const device_type GB_ROM_MBC3 = &device_creator<gb_rom_mbc3_device>;
2322const device_type GB_ROM_MBC5 = &device_creator<gb_rom_mbc5_device>;
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4039}
4140
4241gb_rom_mbc1_device::gb_rom_mbc1_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source)
43               : gb_rom_mbc_device(mconfig, type, name, tag, owner, clock, shortname, source)
42               : gb_rom_mbc_device(mconfig, type, name, tag, owner, clock, shortname, source),
43                  m_mask(0x1f),
44                  m_shift(0)
4445{
4546}
4647
4748gb_rom_mbc1_device::gb_rom_mbc1_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
48               : gb_rom_mbc_device(mconfig, GB_ROM_MBC1, "GB MBC1 Carts", tag, owner, clock, "gb_rom_mbc1", __FILE__)
49               : gb_rom_mbc_device(mconfig, GB_ROM_MBC1, "GB MBC1 Carts", tag, owner, clock, "gb_rom_mbc1", __FILE__),
50                  m_mask(0x1f),
51                  m_shift(0)
4952{
5053}
5154
52gb_rom_mbc1col_device::gb_rom_mbc1col_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
53               : gb_rom_mbc_device(mconfig, GB_ROM_MBC1_COL, "GB MBC1 Collection Carts", tag, owner, clock, "gb_rom_mbc1col", __FILE__)
54{
55}
56
5755gb_rom_mbc2_device::gb_rom_mbc2_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
5856               : gb_rom_mbc_device(mconfig, GB_ROM_MBC2, "GB MBC2 Carts", tag, owner, clock, "gb_rom_mbc2", __FILE__)
5957{
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135133   save_item(NAME(m_latch_bank2));
136134   save_item(NAME(m_ram_bank));
137135   save_item(NAME(m_ram_enable));
138   save_item(NAME(m_mode));
139136}
140137
141138//-------------------------------------------------
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148145   m_latch_bank2 = 1;
149146   m_ram_bank = 0;
150147   m_ram_enable = 0;
151   m_mode = 0;
152148}
153149
154150//-------------------------------------------------
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177173   save_item(NAME(m_latch_bank2));
178174   save_item(NAME(m_ram_bank));
179175   save_item(NAME(m_ram_enable));
180   save_item(NAME(m_mode));
181176}
182177
183178void gb_rom_mbc6_device::device_reset()
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191186   m_latch_bank2 = 3;  // correct default?
192187   m_ram_bank = 0;
193188   m_ram_enable = 0;
194   m_mode = 0;
195189}
196190
197191void gb_rom_mmm01_device::device_start()
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276270READ8_MEMBER(gb_rom_mbc1_device::read_rom)
277271{
278272   if (offset < 0x4000)
279      return m_rom[rom_bank_map[m_latch_bank] * 0x4000 + (offset & 0x3fff)];
273   {
274      int bank = (m_mode == MODE_4M_256k) ? (m_ram_bank << (5 + m_shift)) : 0;
275      return m_rom[rom_bank_map[bank] * 0x4000 + (offset & 0x3fff)];
276   }
280277   else
281      return m_rom[rom_bank_map[m_latch_bank2] * 0x4000 + (offset & 0x3fff)];
278      return m_rom[rom_bank_map[(m_ram_bank << (5 + m_shift)) | m_latch_bank2] * 0x4000 + (offset & 0x3fff)];
282279}
283280
284281WRITE8_MEMBER(gb_rom_mbc1_device::write_bank)
285282{
286   if (offset < 0x2000)
283   if (offset < 0x2000)   // RAM Enable Register
287284      m_ram_enable = ((data & 0x0f) == 0x0a) ? 1 : 0;
288   else if (offset < 0x4000)
285   else if (offset < 0x4000)   // ROM Bank Register
289286   {
290      // 5bits only
291287      data &= 0x1f;
292      // bank = 0 => bank = 1
293      if (data == 0)
294         data = 1;
295
296      m_latch_bank2 = (m_latch_bank2 & 0x01e0) | data;
288      m_latch_bank2 = data ? data : 0x01u;
289      m_latch_bank2 &= m_mask;
297290   }
298   else if (offset < 0x6000)
299   {
300      // 2bits only
301      data &= 0x3;
302      m_latch_bank2 = (m_latch_bank2 & 0x001f) | (data << 5);
303   }
304   else
305      m_mode = data & 0x1;
291   else if (offset < 0x6000)   // RAM Bank Register
292      m_ram_bank = data & 0x3;
293   else   // MBC1 Mode Register
294      m_mode = (data & 0x1) ? MODE_4M_256k : MODE_16M_8k;
306295}
307296
308297READ8_MEMBER(gb_rom_mbc1_device::read_ram)
309298{
310299   if (m_ram && m_ram_enable)
311300   {
312      m_ram_bank = m_mode ? (m_latch_bank2 >> 5) : 0;
313      return m_ram[ram_bank_map[m_ram_bank] * 0x2000 + offset];
301      int bank = (m_mode == MODE_4M_256k) ? m_ram_bank : 0;
302      return m_ram[ram_bank_map[bank] * 0x2000 + offset];
314303   }
315304   else
316305      return 0xff;
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320309{
321310   if (m_ram && m_ram_enable)
322311   {
323      m_ram_bank = m_mode ? (m_latch_bank2 >> 5) : 0;
324      m_ram[ram_bank_map[m_ram_bank] * 0x2000 + offset] = data;
312      int bank = (m_mode == MODE_4M_256k) ? m_ram_bank : 0;
313      m_ram[ram_bank_map[bank] * 0x2000 + offset] = data;
325314   }
326315}
327316
328317
329// MBC1 Korean variant (used by Bomberman Selection)
330
331READ8_MEMBER(gb_rom_mbc1col_device::read_rom)
332{
333   if (offset < 0x4000)
334      return m_rom[rom_bank_map[m_latch_bank] * 0x4000 + (offset & 0x3fff)];
335   else
336      return m_rom[rom_bank_map[m_latch_bank2] * 0x4000 + (offset & 0x3fff)];
337}
338
339WRITE8_MEMBER(gb_rom_mbc1col_device::write_bank)
340{
341   if (offset < 0x2000)
342      m_ram_enable = ((data & 0x0f) == 0x0a) ? 1 : 0;
343   else if (offset < 0x4000)
344   {
345      // 4bits only?
346      data &= 0x0f;
347      // bank = 0 => bank = 1
348      if (data == 0)
349         data = 1;
350
351      m_latch_bank2 = (m_latch_bank2 & 0x01f0) | data;
352   }
353   else if (offset < 0x6000)
354   {
355      // 2bits only
356      data &= 0x3;
357      m_latch_bank2 = (m_latch_bank2 & 0x000f) | (data << 4);
358      m_latch_bank = m_latch_bank2 & 0x30;
359   }
360   else
361      m_mode = data & 0x1;
362}
363
364// RAM access is the same as usual MBC1
365READ8_MEMBER(gb_rom_mbc1col_device::read_ram)
366{
367   if (m_ram && m_ram_enable)
368   {
369      m_ram_bank = m_mode ? (m_latch_bank2 >> 5) : 0;
370      return m_ram[ram_bank_map[m_ram_bank] * 0x2000 + offset];
371   }
372   else
373      return 0xff;
374}
375
376WRITE8_MEMBER(gb_rom_mbc1col_device::write_ram)
377{
378   if (m_ram && m_ram_enable)
379   {
380      m_ram_bank = m_mode ? (m_latch_bank2 >> 5) : 0;
381      m_ram[ram_bank_map[m_ram_bank] * 0x2000 + offset] = data;
382   }
383}
384
385318// MBC2
386319
387320READ8_MEMBER(gb_rom_mbc2_device::read_rom)
trunk/src/emu/bus/gameboy/mbc.h
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2626   virtual DECLARE_WRITE8_MEMBER(write_ram);
2727
2828   UINT8 m_ram_enable;
29   UINT8 m_mode;
3029};
3130
3231// ======================> gb_rom_mbc1_device
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3433class gb_rom_mbc1_device : public gb_rom_mbc_device
3534{
3635public:
36   
37   enum {
38      MODE_16M_8k  = 0, /// 16Mbit ROM, 8kBit RAM
39      MODE_4M_256k = 1, /// 4Mbit ROM, 256kBit RAM
40   };
41   
3742   // construction/destruction
3843   gb_rom_mbc1_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source);
3944   gb_rom_mbc1_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
4045
4146   // device-level overrides
42   virtual void device_start() { shared_start(); };
43   virtual void device_reset() { shared_reset(); };
47   virtual void device_start() { shared_start(); save_item(NAME(m_mode)); };
48   virtual void device_reset() { shared_reset(); m_mode = MODE_16M_8k; };
49   virtual void set_additional_wirings(UINT8 mask, int shift) { m_mask = mask; m_shift = shift; }   // these get set at cart loading
4450
4551   virtual DECLARE_READ8_MEMBER(read_rom);
4652   virtual DECLARE_WRITE8_MEMBER(write_bank);
4753   virtual DECLARE_READ8_MEMBER(read_ram);
4854   virtual DECLARE_WRITE8_MEMBER(write_ram);
49};
5055
51// ======================> gb_rom_mbc1col_device
52
53class gb_rom_mbc1col_device : public gb_rom_mbc_device
54{
55public:
56   // construction/destruction
57   gb_rom_mbc1col_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
58
59   // device-level overrides
60   virtual void device_start() { shared_start(); };
61   virtual void device_reset() { shared_reset(); };
62
63   virtual DECLARE_READ8_MEMBER(read_rom);
64   virtual DECLARE_WRITE8_MEMBER(write_bank);
65   virtual DECLARE_READ8_MEMBER(read_ram);
66   virtual DECLARE_WRITE8_MEMBER(write_ram);
56   UINT8 m_mode, m_mask;
57   int m_shift;
6758};
6859
6960// ======================> gb_rom_mbc2_device
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298289   virtual DECLARE_WRITE8_MEMBER(write_bank);
299290   virtual DECLARE_READ8_MEMBER(read_ram);
300291   virtual DECLARE_WRITE8_MEMBER(write_ram);
301   UINT8 m_bank_mask, m_bank, m_reg;
292   UINT8 m_bank_mask, m_bank, m_reg, m_mode;
302293};
303294
304295
trunk/src/mess/drivers/gb.c
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638638static SLOT_INTERFACE_START(gb_cart)
639639   SLOT_INTERFACE_INTERNAL("rom",         GB_STD_ROM)
640640   SLOT_INTERFACE_INTERNAL("rom_mbc1",    GB_ROM_MBC1)
641   SLOT_INTERFACE_INTERNAL("rom_mbc1col", GB_ROM_MBC1_COL)
641   SLOT_INTERFACE_INTERNAL("rom_mbc1col", GB_ROM_MBC1)
642642   SLOT_INTERFACE_INTERNAL("rom_mbc2",    GB_ROM_MBC2)
643643   SLOT_INTERFACE_INTERNAL("rom_mbc3",    GB_ROM_MBC3)
644644   SLOT_INTERFACE_INTERNAL("rom_huc1",    GB_ROM_MBC3)

https://github.com/mamedev/mame/commit/3dd6c7d35564a491020a026937dc5222a2c4ba69

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