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r36954 Sunday 5th April, 2015 at 14:03:20 UTC by R. Belmont
More iteagle improvements: [Ted Green] - PCI: allow BAR of 0; change "invalid" from 0 to -1 - vrc4373: implement bus-master DMA - es1373: Do some processing and DMA, and issue IRQs

[src/emu/machine]	pci.c vrc4373.c vrc4373.h
[src/emu/sound]	es1373.c es1373.h
[src/mame/drivers]	iteagle.c

trunk/src/emu/machine/pci.c

r245465	r245466
81	81	status = 0x0000;
82	82
83	83	for(int i=0; i<6; i++) {
84		bank_infos[i].adr = 0;
	84	bank_infos[i].adr = -1;
85	85	bank_infos[i].size = 0;
86	86	bank_infos[i].flags = 0;
87	87	bank_reg_infos[i].bank = -1;
r245465	r245466
257	257	{
258	258	for(int i=0; i<bank_count; i++) {
259	259	bank_info &bi = bank_infos[i];
260		if(!bi.adr)
	260	if(bi.adr==-1)
261	261	continue;
262	262	if(UINT32(bi.adr) == UINT32(~(bi.size - 1)))
263	263	continue;

trunk/src/emu/machine/vrc4373.c

r245465	r245466
1	1	#include "vrc4373.h"
2	2
3		#define LOG_NILE            (1)
	3	#define LOG_NILE            (0)
4	4	#define LOG_NILE_MASTER     (0)
5		#define LOG_NILE_TARGET     (1)
	5	#define LOG_NILE_TARGET     (0)
6	6
7	7	const device_type VRC4373      = &device_creator<vrc4373_device>;
8	8
r245465	r245466
217	217	{
218	218	UINT32 result = m_cpu->space(AS_PROGRAM).read_dword(m_target1_laddr | (offset*4), mem_mask);
219	219	if (LOG_NILE_TARGET)
220		logerror("%06X:nile target1 read from offset %02X = %08X & %08X\n", space.device().safe_pc(), offset*4, result, mem_mask);
	220	logerror("%08X:nile target1 read from offset %02X = %08X & %08X\n", m_cpu->device_t::safe_pc(), offset*4, result, mem_mask);
221	221	return result;
222	222	}
223	223	WRITE32_MEMBER (vrc4373_device::target1_w)
224	224	{
225	225	m_cpu->space(AS_PROGRAM).write_dword(m_target1_laddr | (offset*4), data, mem_mask);
226	226	if (LOG_NILE_TARGET)
227		logerror("%06X:nile target1 write to offset %02X = %08X & %08X\n", space.device().safe_pc(), offset*4, data, mem_mask);
	227	logerror("%08X:nile target1 write to offset %02X = %08X & %08X\n", m_cpu->device_t::safe_pc(), offset*4, data, mem_mask);
228	228	}
229	229
230	230	// PCI Target Window 2
r245465	r245466
232	232	{
233	233	UINT32 result = m_cpu->space(AS_PROGRAM).read_dword(m_target2_laddr | (offset*4), mem_mask);
234	234	if (LOG_NILE_TARGET)
235		logerror("%06X:nile target2 read from offset %02X = %08X & %08X\n", space.device().safe_pc(), offset*4, result, mem_mask);
	235	logerror("%08X:nile target2 read from offset %02X = %08X & %08X\n", m_cpu->device_t::safe_pc(), offset*4, result, mem_mask);
236	236	return result;
237	237	}
238	238	WRITE32_MEMBER (vrc4373_device::target2_w)
239	239	{
240	240	m_cpu->space(AS_PROGRAM).write_dword(m_target2_laddr | (offset*4), data, mem_mask);
241	241	if (LOG_NILE_TARGET)
242		logerror("%06X:nile target2 write to offset %02X = %08X & %08X\n", space.device().safe_pc(), offset*4, data, mem_mask);
	242	logerror("%08X:nile target2 write to offset %02X = %08X & %08X\n", m_cpu->device_t::safe_pc(), offset*4, data, mem_mask);
243	243	}
244	244
	245	// DMA Transfer
	246	void vrc4373_device::dma_transfer(int which)
	247	{
	248	if (LOG_NILE)
	249	logerror("%08X:nile Start dma PCI: %08X MEM: %08X Words: %X\n", m_cpu->space(AS_PROGRAM).device().safe_pc(), m_cpu_regs[NREG_DMA_CPAR], m_cpu_regs[NREG_DMA_CMAR], m_cpu_regs[NREG_DMA_REM]);
	250	int pciSel = (m_cpu_regs[NREG_DMACR1+which*0xC] & DMA_MIO) ? AS_DATA : AS_IO;
	251	UINT32 mem_mask = 0xffffffff;
	252	while (m_cpu_regs[NREG_DMA_REM]>0) {
	253	if (0 && LOG_NILE)
	254	logerror("dma_transfer PCI: %08X Mem: %08X Words Remaining: %X\n", m_cpu_regs[NREG_DMA_CPAR], m_cpu_regs[NREG_DMA_CMAR], m_cpu_regs[NREG_DMA_REM]);
	255	if (m_cpu_regs[NREG_DMACR1+which*0xC]&DMA_RW) {
	256	// Read data from PCI and write to local
	257	m_cpu->space(AS_PROGRAM).write_dword(m_cpu_regs[NREG_DMA_CMAR], this->space(pciSel).read_dword(m_cpu_regs[NREG_DMA_CPAR], mem_mask), mem_mask);
	258	} else {
	259	// Read data from local and write to PCI
	260	this->space(pciSel).write_dword(m_cpu_regs[NREG_DMA_CPAR], m_cpu->space(AS_PROGRAM).read_dword(m_cpu_regs[NREG_DMA_CMAR], mem_mask), mem_mask);
	261	}
	262	m_cpu_regs[NREG_DMA_CMAR] += 0x4;
	263	m_cpu_regs[NREG_DMA_CPAR] += 0x4;
	264	m_cpu_regs[NREG_DMA_REM]--;
	265	}
	266	}
245	267	// CPU I/F
246	268	READ32_MEMBER (vrc4373_device::cpu_if_r)
247	269	{
r245465	r245466
253	275	case NREG_PCICDR:
254	276	result = config_data_r(space, offset);
255	277	break;
	278	case NREG_DMACR1:
	279	case NREG_DMACR2:
	280	// Clear busy and go on read
	281	if (m_cpu_regs[NREG_DMA_REM]==0) {
	282	int which = (offset-NREG_DMACR1)>>3;
	283	m_cpu_regs[NREG_DMACR1+which*0xc] &= ~DMA_BUSY;
	284	m_cpu_regs[NREG_DMACR1+which*0xc] &= ~DMA_GO;
	285	}
	286	break;
256	287	default:
257	288	break;
258	289	}
r245465	r245466
266	297	if (LOG_NILE)
267	298	logerror("%06X:nile write to offset %02X = %08X & %08X\n", space.device().safe_pc(), offset*4, data, mem_mask);
268	299
269		UINT32 modData;
	300	UINT32 modData, oldData;
	301	oldData = m_cpu_regs[offset];
270	302	COMBINE_DATA(&m_cpu_regs[offset]);
271	303	switch (offset) {
272	304	case NREG_PCIMW1:
r245465	r245466
312	344	case NREG_PCICDR:
313	345	pci_host_device::config_data_w(space, offset, data);
314	346	break;
	347	case NREG_DMACR1:
	348	case NREG_DMACR2:
	349	// Start when DMA_GO bit is set
	350	if (!(oldData & DMA_GO) && (data & DMA_GO)) {
	351	int which = (offset-NREG_DMACR1)>>3;
	352	// Check to see DMA is not already started
	353	if (!(data&DMA_BUSY)) {
	354	// Set counts and address
	355	m_cpu_regs[NREG_DMA_CPAR] = m_cpu_regs[NREG_DMAPCI1+which*0xC];
	356	m_cpu_regs[NREG_DMA_CMAR] = m_cpu_regs[NREG_DMAMAR1+which*0xC];
	357	m_cpu_regs[NREG_DMA_REM] = (data & DMA_BLK_SIZE)>>2;
	358	m_cpu_regs[NREG_DMACR1+which*0xc] |= DMA_BUSY;
	359	// Start the transfer
	360	dma_transfer(which);
	361	}
	362	}
	363	break;
315	364	case NREG_BMCR:
316	365	if ((data>>3)&0x1) {
317	366	m_ram_size = 1<<22;  // 4MB

trunk/src/emu/machine/vrc4373.h

r245465	r245466
38	38	#define NREG_DRAMRCR        (0x058/4)
39	39	#define NREG_BOOTWP         (0x05C/4)
40	40	#define NREG_PCIEAR         (0x060/4)
41		#define NREG_DMA_WR         (0x064/4)
	41	#define NREG_DMA_REM        (0x064/4)
42	42	#define NREG_DMA_CMAR       (0x068/4)
43	43	#define NREG_DMA_CPAR       (0x06C/4)
44	44	#define NREG_PCIRC          (0x070/4)
45	45	#define NREG_PCIEN          (0x074/4)
46	46	#define NREG_PMIR           (0x078/4)
47	47
	48	#define DMA_BUSY            0x80000000
	49	#define DMA_INT_EN         0x40000000
	50	#define DMA_RW               0x20000000
	51	#define DMA_GO               0x10000000
	52	#define DMA_SUS               0x08000000
	53	#define DMA_INC             0x04000000
	54	#define DMA_MIO               0x02000000
	55	#define DMA_RST               0x01000000
	56	#define DMA_BLK_SIZE      0x000fffff
	57
	58
48	59	class vrc4373_device : public pci_host_device {
49	60	public:
50	61	vrc4373_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
r245465	r245466
86	97	virtual const address_space_config *memory_space_config(address_spacenum spacenum) const;
87	98	virtual void device_start();
88	99	virtual void device_reset();
	100	void dma_transfer(int which);
89	101
90	102	private:
91	103	cpu_device *m_cpu;
r245465	r245466
108	120
109	121	UINT32 m_pci1_laddr, m_pci2_laddr, m_pci_io_laddr;
110	122	UINT32 m_target1_laddr, m_target2_laddr;
	123
111	124	};
112	125
113	126

trunk/src/emu/sound/es1373.c

r245465	r245466
1	1	#include "es1373.h"
2	2
3	3	#define LOG_ES            (1)
	4	#define LOG_ES_REG        (0)
4	5
	6	static MACHINE_CONFIG_FRAGMENT( es1373 )
	7	MCFG_TIMER_DRIVER_ADD_PERIODIC("sound_timer", es1373_device, es_timer_callback,  attotime::from_hz(44100/16384))
	8	MACHINE_CONFIG_END
	9
	10	machine_config_constructor es1373_device::device_mconfig_additions() const
	11	{
	12	return MACHINE_CONFIG_NAME( es1373 );
	13	}
	14
5	15	const device_type ES1373 = &device_creator<es1373_device>;
6	16
7	17	DEVICE_ADDRESS_MAP_START(map, 32, es1373_device)
r245465	r245466
9	19	ADDRESS_MAP_END
10	20
11	21	es1373_device::es1373_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
12		: pci_device(mconfig, ES1373, "Creative Labs Ensoniq AudioPCI97 ES1373", tag, owner, clock, "es1373", __FILE__)
	22	: pci_device(mconfig, ES1373, "Creative Labs Ensoniq AudioPCI97 ES1373", tag, owner, clock, "es1373", __FILE__),
	23	m_irq_num(-1)
13	24	{
14	25	}
15	26
	27	void es1373_device::set_irq_info(const char *tag, const int irq_num)
	28	{
	29	m_cpu_tag = tag;
	30	m_irq_num = irq_num;
	31	}
	32
16	33	void es1373_device::device_start()
17	34	{
	35	//m_cpu = machine().device<cpu_device>(":maincpu");
	36	m_cpu = machine().device<cpu_device>(m_cpu_tag);
18	37	pci_device::device_start();
19	38	add_map(0x40, M_IO, FUNC(es1373_device::map));
20	39	}
r245465	r245466
25	44	memset(m_es_regs, 0, sizeof(m_es_regs));
26	45	memset(m_ac97_regs, 0, sizeof(m_ac97_regs));
27	46	m_ac97_regs[0] = 0x0800;
	47	// Reset ADC channel info
	48	m_adc.enable = false;
	49	m_adc.int_en = false;
	50	m_adc.loop_en = false;
	51	m_adc.initialized = false;
	52	m_adc.buf_count = 0;
	53	m_adc.buf_size = 0;
	54	m_adc.buf_rptr = 0x20;
	55	m_adc.buf_wptr = 0x20;
	56	// Reset DAC1 channel info
	57	m_dac1.enable = false;
	58	m_dac1.int_en = false;
	59	m_dac1.loop_en = false;
	60	m_dac1.initialized = false;
	61	m_dac1.buf_count = 0;
	62	m_dac1.buf_size = 0;
	63	m_dac1.buf_rptr = 0x0;
	64	m_dac1.buf_wptr = 0x0;
	65	// Reset DAC2 channel info
	66	m_dac2.enable = false;
	67	m_dac2.int_en = false;
	68	m_dac2.loop_en = false;
	69	m_dac2.initialized = false;
	70	m_dac2.buf_count = 0;
	71	m_dac2.buf_size = 0;
	72	m_dac2.buf_rptr = 0x10;
	73	m_dac2.buf_wptr = 0x10;
28	74	}
29	75
	76	void es1373_device::map_extra(UINT64 memory_window_start, UINT64 memory_window_end, UINT64 memory_offset, address_space *memory_space,
	77	UINT64 io_window_start, UINT64 io_window_end, UINT64 io_offset, address_space *io_space)
	78	{
	79	m_memory_space = memory_space;
	80	}
	81
	82	TIMER_DEVICE_CALLBACK_MEMBER(es1373_device::es_timer_callback)
	83	{
	84	// Only transfer PCI data if bus mastering is enabled
	85	if (command & 0x4) {
	86	if (m_dac2.enable && (!(m_dac2.buf_rptr&0x7))) {
	87	transfer_pci_audio(m_dac2, ES_PCI_READ);
	88	}
	89	if (m_dac2.pci_count>8) {
	90	m_dac2.initialized = true;
	91	}
	92	}
	93	if (m_dac2.enable) {
	94	// The initalized is to signal that inital buffer has been written
	95	if (m_dac2.buf_count<=m_dac2.buf_size && m_dac2.initialized) {
	96	// Send data to sound???
	97	// sound = m_sound_cache[chan.buf_rptr]
	98	if (0 && LOG_ES)
	99	logerror("%X: DAC2 buf_count: %i buf_size: %X buf_rptr: %X buf_wptr: %X\n", machine().device("maincpu")->safe_pc(),
	100	m_dac2.buf_count, m_dac2.buf_size, m_dac2.buf_rptr, m_dac2.buf_wptr);
	101	if (m_dac2.buf_count==m_dac2.buf_size) {
	102	if (m_dac2.int_en) {
	103	m_es_regs[ES_INT_CS_STATUS] |= ICSTATUS_DAC2_INT_MASK;
	104	if (LOG_ES)
	105	logerror("%X: es_timer_callback Setting DAC2 interrupt\n", machine().device("maincpu")->safe_pc());
	106	}
	107	if (m_dac2.loop_en) {
	108	// Keep playing
	109	m_dac2.buf_count = m_dac2.buf_count + 1 - 4;  // Should check SCTRL_P2_END_MASK
	110	} else {
	111	// Stop
	112	//m_dac2.enable = false;
	113	}
	114	} else {
	115	m_dac2.buf_count++;
	116	}
	117	m_dac2.buf_rptr++;
	118	if (!(m_dac2.buf_rptr&0xf)) {
	119	m_dac2.buf_rptr -= 0x10;
	120	}
	121	}
	122	}
	123	if (m_adc.enable) {
	124	if (m_adc.buf_count<=m_adc.buf_size) {
	125	if (LOG_ES)
	126	logerror("%s: ADC buf_count: %i buf_size: %i buf_rptr: %i buf_wptr: %i\n", machine().describe_context(),
	127	m_adc.buf_count, m_adc.buf_size, m_adc.buf_rptr, m_adc.buf_wptr);
	128	if (m_adc.int_en && m_adc.buf_count==m_adc.buf_size) {
	129	m_es_regs[ES_INT_CS_STATUS] |= ICSTATUS_ADC_INT_MASK;
	130	if (LOG_ES)
	131	logerror("%s: es_timer_callback Setting ADC interrupt\n", tag());
	132	}
	133	m_adc.buf_count++;
	134	m_adc.buf_wptr++;
	135	if (!(m_adc.buf_wptr&0xf)) {
	136	m_adc.buf_wptr -= 0x10;
	137	}
	138	}
	139	}
	140	// PCI Write Transfer
	141	if (command & 0x4) {
	142	if (m_adc.enable && (!(m_adc.buf_wptr&0x7))) {
	143	transfer_pci_audio(m_adc, ES_PCI_WRITE);
	144	}
	145	}
	146	if (m_es_regs[ES_INT_CS_STATUS]&(ICSTATUS_DAC1_INT_MASK|ICSTATUS_DAC2_INT_MASK|ICSTATUS_ADC_INT_MASK)) {
	147	m_es_regs[ES_INT_CS_STATUS] |= ICSTATUS_INTR_MASK;
	148	// Assert interrupt
	149	//m_cpu->set_input_line(ES_IRQ_NUM, ASSERT_LINE);
	150	if (m_irq_num!=-1) {
	151	m_cpu->set_input_line(m_irq_num, ASSERT_LINE);
	152	}
	153	}
	154	}
	155
	156	void es1373_device::transfer_pci_audio(chan_info& chan, int type)
	157	{
	158	UINT32 pci_addr, data;
	159	pci_addr = chan.pci_addr + (chan.pci_count<<2);
	160	if (type==ES_PCI_READ) {
	161	// Transfer from PCI to sound cache
	162	// Always transfer 8 longwords
	163	for (int i=0; i<8 && (chan.pci_count<=chan.pci_size); i++) {
	164	data = m_memory_space->read_dword(pci_addr, 0xffffffff);
	165	m_sound_cache[chan.buf_wptr++] = data;
	166	if (!(chan.buf_wptr&0xf)) {
	167	chan.buf_wptr -= 0x10;
	168	}
	169	chan.pci_count++;
	170	pci_addr += 4;
	171	}
	172	} else {
	173	// Transfer from sound cache to PCI
	174	// Always transfer 8 longwords
	175	for (int i=0; i<8 && chan.pci_count<=chan.pci_size; i++) {
	176	data = m_sound_cache[chan.buf_rptr++];
	177	m_memory_space->write_dword(pci_addr, data);
	178	if (!(chan.buf_rptr&0xf)) {
	179	chan.buf_rptr -= 0x10;
	180	}
	181	chan.pci_count++;
	182	pci_addr += 4;
	183	}
	184	}
	185	}
	186
30	187	READ32_MEMBER (es1373_device::reg_r)
31	188	{
32	189	UINT32 result = m_es_regs[offset];
33	190	switch (offset) {
34	191	case ES_CODEC:
35	192	break;
	193	case ES_DAC2_CNT:
	194	result = ((m_dac2.buf_size-m_dac2.buf_count)<<16) | m_dac2.buf_size;
	195	break;
36	196	case ES_HOST_IF0: // 0x30
	197	result = m_sound_cache[(m_es_regs[ES_MEM_PAGE]<<2) | 0x0];
37	198	switch (m_es_regs[ES_MEM_PAGE]&0xf) {
38	199	case 0xc:
39		result = m_dac1_fr.pci_addr;
	200	result = m_dac1.pci_addr;
40	201	break;
41	202	case 0xd:
42		result = m_adc_fr.pci_addr;
	203	result = m_adc.pci_addr;
43	204	break;
44		case 0xe:
45		case 0xf:
46		logerror("%06X:ES1373 Read UART offset %02X & %08X\n", space.device().safe_pc(), offset*4, mem_mask);
47	205	default:
48	206	break;
49	207	}
50	208	break;
51	209	case ES_HOST_IF1: // 0x34
	210	result = m_sound_cache[(m_es_regs[ES_MEM_PAGE]<<2) | 0x1];
52	211	switch (m_es_regs[ES_MEM_PAGE]&0xf) {
53	212	case 0xc:
54		result = (m_dac1_fr.curr_count<<16) | m_dac1_fr.buff_size;
	213	result = (m_dac1.pci_count<<16) | m_dac1.pci_size;
55	214	break;
56	215	case 0xd:
57		result = (m_adc_fr.curr_count<<16) | m_adc_fr.buff_size;
	216	result = (m_adc.pci_count<<16) | m_adc.pci_size;
58	217	break;
59		case 0xe:
60		case 0xf:
61		logerror("%06X:ES1373 write UART offset %02X & %08X\n", space.device().safe_pc(), offset*4, mem_mask);
62	218	default:
63	219	break;
64	220	}
65	221	break;
66	222	case ES_HOST_IF2: // 0x38
	223	result = m_sound_cache[(m_es_regs[ES_MEM_PAGE]<<2) | 0x2];
67	224	switch (m_es_regs[ES_MEM_PAGE]&0xf) {
68	225	case 0xc:
69		result = m_dac2_fr.pci_addr;
	226	result = m_dac2.pci_addr;
70	227	break;
71		case 0xd:
72		logerror("%06X:ES1373 read Unknown place offset %02X & %08X\n", space.device().safe_pc(), offset*4, mem_mask);
73		break;
74		case 0xe:
75		case 0xf:
76		logerror("%06X:ES1373 read UART offset %02X  & %08X\n", space.device().safe_pc(), offset*4, mem_mask);
77	228	default:
78	229	break;
79	230	}
80	231	break;
81	232	case ES_HOST_IF3: // 0x3C
	233	result = m_sound_cache[(m_es_regs[ES_MEM_PAGE]<<2) | 0x3];
82	234	switch (m_es_regs[ES_MEM_PAGE]&0xf) {
83	235	case 0xc:
84		result = (m_dac2_fr.curr_count<<16) | m_dac2_fr.buff_size;
	236	result = ((m_dac2.pci_count)<<16) | m_dac2.pci_size;
85	237	break;
86		case 0xd:
87		logerror("%06X:ES1373 read Unknown place offset %02X & %08X\n", space.device().safe_pc(), offset*4, mem_mask);
88		break;
89		case 0xe:
90		case 0xf:
91		logerror("%06X:ES1373 read UART offset %02X & %08X\n", space.device().safe_pc(), offset*4, mem_mask);
92	238	default:
93	239	break;
94	240	}
r245465	r245466
96	242	default:
97	243	break;
98	244	}
99		if (LOG_ES)
100		logerror("%06X:ES1373 read from offset %02X = %08X & %08X\n", space.device().safe_pc(), offset*4, result, mem_mask);
	245	if (LOG_ES_REG)
	246	logerror("%08X:ES1373 read from offset %02X = %08X & %08X\n", machine().device("maincpu")->safe_pc(), offset*4, result, mem_mask);
101	247	return result;
102	248	}
103	249
r245465	r245466
105	251	{
106	252	COMBINE_DATA(&m_es_regs[offset]);
107	253	switch (offset) {
	254	case ES_INT_CS_CTRL:
	255	m_dac1.enable = (m_es_regs[ES_INT_CS_CTRL] & ICCTRL_DAC1_EN_MASK);
	256	m_dac2.enable = (m_es_regs[ES_INT_CS_CTRL] & ICCTRL_DAC2_EN_MASK);
	257	m_adc.enable = (m_es_regs[ES_INT_CS_CTRL] & ICCTRL_ADC_EN_MASK);
	258	break;
108	259	case ES_SRC_IF:
109	260	if (data&(1<<24)) {
110	261	// Write to Sample Rate Converter Ram
r245465	r245466
123	274	m_ac97_regs[(data>>16)&0x7f] = data&0xFFFF;
124	275	}
125	276	break;
	277	case ES_SERIAL_CTRL:
	278	m_adc.loop_en  = !(m_es_regs[ES_SERIAL_CTRL] & SCTRL_R1_LOOP_MASK);
	279	m_dac2.loop_en = !(m_es_regs[ES_SERIAL_CTRL] & SCTRL_P2_LOOP_MASK);
	280	m_dac1.loop_en = !(m_es_regs[ES_SERIAL_CTRL] & SCTRL_P1_LOOP_MASK);
	281	m_adc.int_en  = m_es_regs[ES_SERIAL_CTRL] & SCTRL_R1_INT_EN_MASK;
	282	m_dac2.int_en = m_es_regs[ES_SERIAL_CTRL] & SCTRL_P2_INT_EN_MASK;
	283	m_dac1.int_en = m_es_regs[ES_SERIAL_CTRL] & SCTRL_P1_INT_EN_MASK;
	284	if (!m_adc.int_en) m_es_regs[ES_INT_CS_STATUS]  &= ~ICSTATUS_ADC_INT_MASK;
	285	if (!m_dac1.int_en) m_es_regs[ES_INT_CS_STATUS] &= ~ICSTATUS_DAC1_INT_MASK;
	286	if (!m_dac2.int_en) m_es_regs[ES_INT_CS_STATUS] &= ~ICSTATUS_DAC2_INT_MASK;
	287	// Clear the summary interrupt and irq line
	288	if (!(m_es_regs[ES_INT_CS_STATUS]&(ICSTATUS_DAC1_INT_MASK|ICSTATUS_DAC2_INT_MASK|ICSTATUS_ADC_INT_MASK))) {
	289	// Deassert interrupt
	290	if (m_es_regs[ES_INT_CS_STATUS]&ICSTATUS_INTR_MASK && m_irq_num!=-1) {
	291	m_cpu->set_input_line(m_irq_num, CLEAR_LINE);
	292	m_es_regs[ES_INT_CS_STATUS] &= ~ICSTATUS_INTR_MASK;
	293	if (LOG_ES)
	294	logerror("%X: es1373_device::reg_w Clearing interrupt\n", machine().device("maincpu")->safe_pc());
	295	}
	296	}
	297	if (LOG_ES_REG)
	298	logerror("%s: es1373_device::reg_w adc_int_en: %i dac1_int_en: %i dac2_int_en: %i\n", tag(), m_adc.int_en, m_dac1.int_en, m_dac2.int_en);
	299	break;
	300	case ES_DAC2_CNT:
	301	m_dac2.buf_count = 0;
	302	m_dac2.buf_size = data&0xffff;
	303	break;
126	304	case ES_HOST_IF0: // 0x30
	305	m_sound_cache[(m_es_regs[ES_MEM_PAGE]<<2) | 0x0] = data;
127	306	switch (m_es_regs[ES_MEM_PAGE]&0xf) {
128	307	case 0xc:
129		m_dac1_fr.pci_addr = data;
	308	m_dac1.pci_addr = data;
130	309	break;
131	310	case 0xd:
132		m_adc_fr.pci_addr = data;
	311	m_adc.pci_addr = data;
133	312	break;
134		case 0xe:
135		case 0xf:
136		logerror("%06X:ES1373 write UART offset %02X = %08X & %08X\n", space.device().safe_pc(), offset*4, data, mem_mask);
137	313	default:
138	314	break;
139	315	}
140	316	break;
141	317	case ES_HOST_IF1: // 0x34
	318	m_sound_cache[(m_es_regs[ES_MEM_PAGE]<<2) | 0x1] = data;
142	319	switch (m_es_regs[ES_MEM_PAGE]&0xf) {
143	320	case 0xc:
144		m_dac1_fr.curr_count = (data>>16)&0xffff;
145		m_dac1_fr.buff_size = data&0xffff;
	321	m_dac1.pci_count = (data>>16)&0xffff;
	322	m_dac1.pci_size = data&0xffff;
146	323	break;
147	324	case 0xd:
148		m_adc_fr.curr_count = (data>>16)&0xffff;
149		m_adc_fr.buff_size = data&0xffff;
	325	m_adc.pci_count = (data>>16)&0xffff;
	326	m_adc.pci_size = data&0xffff;
150	327	break;
151		case 0xe:
152		case 0xf:
153		logerror("%06X:ES1373 write UART offset %02X = %08X & %08X\n", space.device().safe_pc(), offset*4, data, mem_mask);
154	328	default:
155	329	break;
156	330	}
157	331	break;
158	332	case ES_HOST_IF2: // 0x38
	333	m_sound_cache[(m_es_regs[ES_MEM_PAGE]<<2) | 0x2] = data;
159	334	switch (m_es_regs[ES_MEM_PAGE]&0xf) {
160	335	case 0xc:
161		m_dac2_fr.pci_addr = data;
	336	m_dac2.pci_addr = data;
162	337	break;
163		case 0xd:
164		logerror("%06X:ES1373 write Unknown place offset %02X = %08X & %08X\n", space.device().safe_pc(), offset*4, data, mem_mask);
165		break;
166		case 0xe:
167		case 0xf:
168		logerror("%06X:ES1373 write UART offset %02X = %08X & %08X\n", space.device().safe_pc(), offset*4, data, mem_mask);
169	338	default:
170	339	break;
171	340	}
172	341	break;
173	342	case ES_HOST_IF3: // 0x3C
	343	m_sound_cache[(m_es_regs[ES_MEM_PAGE]<<2) | 0x3] = data;
174	344	switch (m_es_regs[ES_MEM_PAGE]&0xf) {
175	345	case 0xc:
176		m_dac2_fr.curr_count = (data>>16)&0xffff;
177		m_dac2_fr.buff_size = data&0xffff;
	346	m_dac2.pci_count = (data>>16)&0xffff;
	347	m_dac2.pci_size = data&0xffff;
178	348	break;
179		case 0xd:
180		logerror("%06X:ES1373 write Unknown place offset %02X = %08X & %08X\n", space.device().safe_pc(), offset*4, data, mem_mask);
181		break;
182		case 0xe:
183		case 0xf:
184		logerror("%06X:ES1373 write UART offset %02X = %08X & %08X\n", space.device().safe_pc(), offset*4, data, mem_mask);
185	349	default:
186	350	break;
187	351	}
r245465	r245466
190	354	break;
191	355	}
192	356
193		if (LOG_ES)
194		logerror("%06X:ES1373 write to offset %02X = %08X & %08X\n", space.device().safe_pc(), offset*4, data, mem_mask);
	357	if (LOG_ES_REG)
	358	logerror("%08X:ES1373 write to offset %02X = %08X & %08X\n", machine().device("maincpu")->safe_pc(), offset*4, data, mem_mask);
195	359
196	360	}

trunk/src/emu/sound/es1373.h

r245465	r245466
5	5
6	6	#include "machine/pci.h"
7	7
	8	// No interrupts
8	9	#define MCFG_ES1373_ADD(_tag) \
9	10	MCFG_PCI_DEVICE_ADD(_tag, ES1373, 0x12741371, 0x04, 0x040100, 0x12741371)
10	11
	12	#define MCFG_ES1373_IRQ_ADD(_cpu_tag, _irq_num) \
	13	downcast<es1373_device *>(device)->set_irq_info(_cpu_tag, _irq_num);
	14
11	15	/* Ensonic ES1373 registers 0x00-0x3f */
12	16	#define ES_INT_CS_CTRL          (0x00/4)
13	17	#define ES_INT_CS_STATUS        (0x04/4)
14		#define ES_UART_DATA              (0x08/4)
15		#define ES_UART_STATUS            (0x09/4)
16		#define ES_UART_CTRL              (0x09/4)
17		#define ES_UART_RSVD              (0x0A/4)
18		#define ES_MEM_PAGE               (0x0C/4)
	18	#define ES_UART_DATA            (0x08/4)
	19	#define ES_UART_STATUS          (0x09/4)
	20	#define ES_UART_CTRL            (0x09/4)
	21	#define ES_UART_RSVD            (0x0A/4)
	22	#define ES_MEM_PAGE             (0x0C/4)
19	23	#define ES_SRC_IF               (0x10/4)
20		#define ES_CODEC                  (0x14/4)
21		#define ES_LEGACY                 (0x18/4)
22		#define ES_CHAN_CTRL              (0x1C/4)
	24	#define ES_CODEC                (0x14/4)
	25	#define ES_LEGACY               (0x18/4)
	26	#define ES_CHAN_CTRL            (0x1C/4)
23	27	#define ES_SERIAL_CTRL          (0x20/4)
24	28	#define ES_DAC1_CNT             (0x24/4)
25	29	#define ES_DAC2_CNT             (0x28/4)
26	30	#define ES_ADC_CNT              (0x2C/4)
27		#define ES_ADC_CNT              (0x2C/4)
28	31	#define ES_HOST_IF0             (0x30/4)
29	32	#define ES_HOST_IF1             (0x34/4)
30	33	#define ES_HOST_IF2             (0x38/4)
31	34	#define ES_HOST_IF3             (0x3C/4)
32	35
33		struct frame_reg {
34		UINT32 pci_addr;
35		UINT16 curr_count;
36		UINT16 buff_size;
37		frame_reg() : pci_addr(0), curr_count(0), buff_size(0) {}
	36	// Interrupt/Chip Select Control Register (ES_INT_CS_CTRL) bits
	37	#define ICCTRL_ADC_STOP_MASK   0x00002000
	38	#define ICCTRL_DAC1_EN_MASK    0x00000040
	39	#define ICCTRL_DAC2_EN_MASK    0x00000020
	40	#define ICCTRL_ADC_EN_MASK     0x00000010
	41	#define ICCTRL_UART_EN_MASK    0x00000008
	42	#define ICCTRL_JYSTK_EN_MASK   0x00000004
	43
	44	// Interrupt/Chip Select Status Register (ES_INT_CS_STATUS) bits
	45	#define ICSTATUS_INTR_MASK        0x80000000
	46	#define ICSTATUS_DAC1_INT_MASK    0x00000004
	47	#define ICSTATUS_DAC2_INT_MASK    0x00000002
	48	#define ICSTATUS_ADC_INT_MASK     0x00000001
	49
	50	// Serial Interface Control Register (ES_SERIAL_CTRL) bits
	51	#define SCTRL_P2_END_MASK     0x00380000
	52	#define SCTRL_P2_START_MASK   0x00070000
	53	#define SCTRL_R1_LOOP_MASK    0x00008000
	54	#define SCTRL_P2_LOOP_MASK    0x00004000
	55	#define SCTRL_P1_LOOP_MASK    0x00002000
	56	#define SCTRL_P2_PAUSE_MASK   0x00001000
	57	#define SCTRL_P1_PAUSE_MASK   0x00000800
	58	#define SCTRL_R1_INT_EN_MASK  0x00000400
	59	#define SCTRL_P2_INT_EN_MASK  0x00000200
	60	#define SCTRL_P1_INT_EN_MASK  0x00000100
	61	#define SCTRL_P1_RELOAD_MASK  0x00000080
	62	#define SCTRL_P2_STOP_MASK    0x00000040
	63	#define SCTRL_R1_S_MASK       0x00000030
	64	#define SCTRL_P2_S_MASK       0x0000000C
	65	#define SCTRL_P1_S_MASK       0x00000003
	66
	67	#define ES_PCI_READ 0
	68	#define ES_PCI_WRITE 1
	69
	70	struct chan_info {
	71	bool enable;
	72	bool int_en;
	73	bool loop_en;
	74	bool initialized;
	75	UINT32 samp_size;    // Size of one sample in log2(bytes)
	76	UINT32 buf_wptr;     // Address to sample cache memory
	77	UINT32 buf_rptr;     // Address to sample cache memory
	78	UINT16 buf_count;    // Number of samples that have been played
	79	UINT16 buf_size;     // Number of samples minus one to play
	80	UINT32 pci_addr;     // PCI Addresss for system memory accesses
	81	UINT16 pci_count;    // Number of 32 bits transfered
	82	UINT16 pci_size;     // Total number of words (32 bits) minus one in system memory
38	83	};
39	84
40	85	class es1373_device : public pci_device {
41	86	public:
42	87	es1373_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	88	virtual void map_extra(UINT64 memory_window_start, UINT64 memory_window_end, UINT64 memory_offset, address_space *memory_space,
	89	UINT64 io_window_start, UINT64 io_window_end, UINT64 io_offset, address_space *io_space);
43	90
	91	void set_irq_info(const char *tag, const int irq_num);
	92
44	93	DECLARE_READ32_MEMBER (reg_r);
45	94	DECLARE_WRITE32_MEMBER(reg_w);
46
	95	TIMER_DEVICE_CALLBACK_MEMBER(es_timer_callback);
	96	// optional information overrides
	97	virtual machine_config_constructor device_mconfig_additions() const;
47	98	protected:
48	99	virtual void device_start();
49	100	virtual void device_reset();
	101	address_space *m_memory_space;
	102	//virtual const address_space_config *memory_space_config(address_spacenum spacenum) const;
50	103
51	104	private:
	105	const char *m_cpu_tag;
	106	cpu_device *m_cpu;
	107	int m_irq_num;
52	108	DECLARE_ADDRESS_MAP(map, 32);
53	109	UINT16 m_ac97_regs[0x80];
54	110	UINT32 m_es_regs[0x10];
	111	UINT32 m_sound_cache[0x40];
55	112	UINT16 m_src_ram[0x80];
56		frame_reg m_dac1_fr;
57		frame_reg m_dac2_fr;
58		frame_reg m_adc_fr;
	113	chan_info m_dac1;
	114	chan_info m_dac2;
	115	chan_info m_adc;
	116	void transfer_pci_audio(chan_info& chan, int type);
	117
59	118	};
60	119
61	120	extern const device_type ES1373;

trunk/src/mame/drivers/iteagle.c

r245465	r245466
135	135	MCFG_ITEAGLE_FPGA_ADD(            ":pci:06.0")
136	136	MCFG_ITEAGLE_IDE_ADD(             ":pci:06.1")
137	137	MCFG_ES1373_ADD(                  ":pci:07.0")
	138	MCFG_ES1373_IRQ_ADD(              ":maincpu", MIPS3_IRQ3)
138	139	MCFG_VOODOO_ADD(                  ":pci:09.0")
139	140	MCFG_ITEAGLE_EEPROM_ADD(          ":pci:0a.0")
140	141
r245465	r245466
161	162	PORT_DIPSETTING(0x1, "Medium" )
162	163	PORT_DIPSETTING(0x0, "Low" )
163	164	PORT_DIPSETTING(0x2, "Low_Alt" )
164		PORT_DIPNAME( 0xC, 0x0, "Always" )
165	165
	166	PORT_START("SW51")
	167	PORT_DIPNAME( 0x3, 0x0, "Mode" )
	168	PORT_DIPSETTING(0x0, "Normal" )
	169	PORT_DIPSETTING(0x1, "Operator" )
	170
	171	PORT_START("IN1")
	172	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_COIN1 )
	173	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_START1 )
	174	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_NAME( "Left" )
	175	PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_NAME( "Right" )
	176	PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_NAME( "Fly By" )
	177	PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_BUTTON4 ) PORT_NAME( "Backspin" )
	178	PORT_BIT( 0x00c0, IP_ACTIVE_HIGH, IPT_UNUSED )
	179	PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_COIN2 )
	180	PORT_BIT( 0xfe00, IP_ACTIVE_HIGH, IPT_UNUSED )
	181
	182	PORT_START("SYSTEM")
	183	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_SERVICE )
	184	PORT_SERVICE_NO_TOGGLE( 0x0002, IP_ACTIVE_HIGH )
	185	PORT_BIT( 0x00fc, IP_ACTIVE_HIGH, IPT_UNUSED )
	186	PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_VOLUME_UP )
	187	PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_VOLUME_DOWN )
	188	PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_BILL1 )
	189	PORT_BIT( 0x0800, IP_ACTIVE_HIGH, IPT_UNUSED )
	190	PORT_BIT( 0x3000, IP_ACTIVE_HIGH, IPT_UNKNOWN )
	191	PORT_DIPNAME( 0xC000, 0xC000, "Voltage" )
	192	PORT_DIPSETTING(0xC000, "OK" )
	193	PORT_DIPSETTING(0x8000, "Low" )
	194	PORT_DIPSETTING(0x4000, "High" )
	195	PORT_DIPSETTING(0x0000, "Not Detected" )
	196
	197	PORT_START("TRACKX1")
	198	PORT_BIT( 0xff, 0x00, IPT_TRACKBALL_X ) PORT_SENSITIVITY(25) PORT_KEYDELTA(32) PORT_REVERSE PORT_PLAYER(1)
	199
	200	PORT_START("TRACKY1")
	201	PORT_BIT( 0xff, 0x00, IPT_TRACKBALL_Y ) PORT_SENSITIVITY(25) PORT_KEYDELTA(32) PORT_PLAYER(1)
	202
166	203	PORT_START("VERSION")
167	204	PORT_DIPNAME( 0x0F00, 0x0000, "GAME" )
168	205	PORT_DIPNAME( 0x00F0, 0x0000, "MAJOR" )
r245465	r245466
243	280	ROM_LOAD( "17s20lpc_sb4.u26", 0x000000, 0x008000, CRC(62c4af8a) SHA1(6eca277b9c66a401990599e98fdca64a9e38cc9a) ) \
244	281	ROM_LOAD( "17s20lpc_sb5.u26", 0x008000, 0x008000, CRC(c88b9d42) SHA1(b912d0fc50ecdc6a198c626f6e1644e8405fac6e) ) \
245	282	ROM_LOAD( "17s50a_red1.u26", 0x010000, 0x020000, CRC(f5cf3187) SHA1(83b4a14de9959e5a776d97d424945d43501bda7f) ) \
246		ROM_REGION( 0x80, "eeprom", 0 ) \
247		ROM_COPY( "fpga", 0x0, 0x0, 0x80 ) \
248	283	ROM_REGION( 0x2000, "pals", 0 ) \
249	284	ROM_LOAD( "e2-card1.u22.jed", 0x000000, 0x000bd1, CRC(9d1e1ace) SHA1(287d6a30e9f32137ef4eba54f0effa092c97a6eb) ) \
250	285	ROM_LOAD( "e2-res3.u117.jed", 0x001000, 0x000bd1, CRC(4f1ff45a) SHA1(213cbdd6cd37ad9b5bfc9545084892a68d29f5ff) )
251	286
	287
252	288	ROM_START( iteagle )
253	289	EAGLE_BIOS
254	290

https://github.com/mamedev/mame/commit/88faf7bec1a3af5d3ffc8817271dbd1ff2957fc2

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