trunk/src/mess/drivers/pc88va.c
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| 34 | 34 | #include "machine/upd765.h" |
| 35 | 35 | #include "sound/2203intf.h" |
| 36 | 36 | #include "formats/xdf_dsk.h" |
| 37 | | #include "machine/upd71071.h" |
| 37 | //#include "machine/upd71071.h" |
| 38 | #include "machine/am9517a.h" |
| 38 | 39 | |
| 40 | |
| 39 | 41 | /* Note: for the time being, just disable FDC CPU, it's for PC-8801 compatibility mode anyway ... */ |
| 40 | 42 | #define TEST_SUBFDC 0 |
| 41 | 43 | |
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| 79 | 81 | |
| 80 | 82 | required_device<cpu_device> m_maincpu; |
| 81 | 83 | required_device<upd765a_device> m_fdc; |
| 82 | | required_device<upd71071_device> m_dmac; |
| 84 | required_device<am9517a_device> m_dmac; |
| 83 | 85 | required_shared_ptr<UINT16> m_palram; |
| 84 | 86 | UINT16 m_bank_reg; |
| 85 | 87 | UINT16 m_screen_ctrl_reg; |
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| 158 | 160 | // void m_fdc_dma_w(UINT16 data); |
| 159 | 161 | DECLARE_WRITE_LINE_MEMBER(pc88va_hlda_w); |
| 160 | 162 | DECLARE_WRITE_LINE_MEMBER(pc88va_tc_w); |
| 161 | | DECLARE_READ16_MEMBER(fdc_dma_r); |
| 162 | | DECLARE_WRITE16_MEMBER(fdc_dma_w); |
| 163 | DECLARE_READ8_MEMBER(fdc_dma_r); |
| 164 | DECLARE_WRITE8_MEMBER(fdc_dma_w); |
| 163 | 165 | |
| 164 | 166 | DECLARE_WRITE_LINE_MEMBER(fdc_irq); |
| 165 | 167 | DECLARE_WRITE_LINE_MEMBER(fdc_drq); |
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| 1146 | 1148 | timer_set(attotime::from_msec(100), TIMER_PC88VA_FDC_TIMER); |
| 1147 | 1149 | |
| 1148 | 1150 | if((m_fdc_ctrl_2 & 0x10) != (data & 0x10)) |
| 1149 | | m_dmac->dmarq(1, 2); |
| 1151 | m_dmac->dreq2_w(1); |
| 1150 | 1152 | |
| 1151 | 1153 | if(data & 0x80) // correct? |
| 1152 | 1154 | machine().device<upd765a_device>("upd765")->reset(); |
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| 1283 | 1285 | AM_RANGE(0x0156, 0x0157) AM_READ8(rom_bank_r,0x00ff) // ROM bank status |
| 1284 | 1286 | // AM_RANGE(0x0158, 0x0159) Interruption Mode Modification |
| 1285 | 1287 | // AM_RANGE(0x015c, 0x015f) NMI mask port (strobe port) |
| 1286 | | AM_RANGE(0x0160, 0x016f) AM_DEVREADWRITE8("dmac", upd71071_device, read, write, 0xffff) // DMA Controller |
| 1288 | AM_RANGE(0x0160, 0x016f) AM_DEVREADWRITE8("dmac", am9517a_device, read, write, 0xffff) // DMA Controller |
| 1287 | 1289 | AM_RANGE(0x0184, 0x0187) AM_DEVREADWRITE8("pic8259_slave", pic8259_device, read, write, 0x00ff) |
| 1288 | 1290 | AM_RANGE(0x0188, 0x018b) AM_DEVREADWRITE8("pic8259_master", pic8259_device, read, write, 0x00ff) // ICU, also controls 8214 emulation |
| 1289 | 1291 | // AM_RANGE(0x0190, 0x0191) System Port 5 |
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| 1704 | 1706 | WRITE_LINE_MEMBER( pc88va_state::fdc_drq ) |
| 1705 | 1707 | { |
| 1706 | 1708 | printf("%02x DRQ\n",state); |
| 1707 | | m_dmac->dmarq(state, 2); |
| 1709 | m_dmac->dreq2_w(state); |
| 1708 | 1710 | } |
| 1709 | 1711 | |
| 1710 | 1712 | WRITE_LINE_MEMBER( pc88va_state::fdc_irq ) |
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| 1723 | 1725 | |
| 1724 | 1726 | WRITE_LINE_MEMBER(pc88va_state::pc88va_hlda_w) |
| 1725 | 1727 | { |
| 1726 | | m_maincpu->set_input_line(INPUT_LINE_HALT, state ? ASSERT_LINE : CLEAR_LINE); |
| 1728 | // m_maincpu->set_input_line(INPUT_LINE_HALT, state ? ASSERT_LINE : CLEAR_LINE); |
| 1727 | 1729 | |
| 1728 | | // m_dmac->hack_w(state); |
| 1730 | m_dmac->hack_w(state); |
| 1729 | 1731 | |
| 1730 | 1732 | // printf("%02x HLDA\n",state); |
| 1731 | 1733 | } |
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| 1739 | 1741 | } |
| 1740 | 1742 | |
| 1741 | 1743 | |
| 1742 | | READ16_MEMBER(pc88va_state::fdc_dma_r) |
| 1744 | READ8_MEMBER(pc88va_state::fdc_dma_r) |
| 1743 | 1745 | { |
| 1744 | 1746 | printf("R DMA\n"); |
| 1745 | 1747 | return m_fdc->dma_r(); |
| 1746 | 1748 | } |
| 1747 | 1749 | |
| 1748 | | WRITE16_MEMBER(pc88va_state::fdc_dma_w) |
| 1750 | WRITE8_MEMBER(pc88va_state::fdc_dma_w) |
| 1749 | 1751 | { |
| 1750 | 1752 | printf("W DMA %08x\n",data); |
| 1751 | 1753 | m_fdc->dma_w(data); |
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| 1809 | 1811 | |
| 1810 | 1812 | MCFG_PIC8259_ADD( "pic8259_slave", DEVWRITELINE("pic8259_master", pic8259_device, ir7_w), GND, NULL ) |
| 1811 | 1813 | |
| 1812 | | MCFG_DEVICE_ADD("dmac", UPD71071, 0) /* ch2 is FDC, ch0/3 are "user". ch1 is unused */ |
| 1813 | | MCFG_UPD71071_CPU("maincpu") |
| 1814 | | MCFG_UPD71071_CLOCK(8000000) |
| 1815 | | MCFG_UPD71071_OUT_HREQ_CB(WRITELINE(pc88va_state, pc88va_hlda_w)) |
| 1816 | | MCFG_UPD71071_OUT_EOP_CB(WRITELINE(pc88va_state, pc88va_tc_w)) |
| 1817 | | MCFG_UPD71071_DMA_READ_2_CB(READ16(pc88va_state, fdc_dma_r)) |
| 1818 | | MCFG_UPD71071_DMA_WRITE_2_CB(WRITE16(pc88va_state, fdc_dma_w)) |
| 1814 | MCFG_DEVICE_ADD("dmac", AM9517A, 8000000) /* ch2 is FDC, ch0/3 are "user". ch1 is unused */ |
| 1815 | MCFG_AM9517A_OUT_HREQ_CB(WRITELINE(pc88va_state, pc88va_hlda_w)) |
| 1816 | MCFG_AM9517A_OUT_EOP_CB(WRITELINE(pc88va_state, pc88va_tc_w)) |
| 1817 | MCFG_AM9517A_IN_IOR_2_CB(READ8(pc88va_state, fdc_dma_r)) |
| 1818 | MCFG_AM9517A_OUT_IOW_2_CB(WRITE8(pc88va_state, fdc_dma_w)) |
| 1819 | 1819 | |
| 1820 | |
| 1820 | 1821 | MCFG_UPD765A_ADD("upd765", false, true) |
| 1821 | 1822 | MCFG_UPD765_INTRQ_CALLBACK(WRITELINE(pc88va_state, fdc_irq)) |
| 1822 | 1823 | MCFG_UPD765_INTRQ_CALLBACK(WRITELINE(pc88va_state, fdc_drq)) |